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-rw-r--r--library/SubcircuitLibrary/CY74FCT480T/74480.sub90
1 files changed, 90 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CY74FCT480T/74480.sub b/library/SubcircuitLibrary/CY74FCT480T/74480.sub
new file mode 100644
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+++ b/library/SubcircuitLibrary/CY74FCT480T/74480.sub
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+* Subcircuit 74480
+.subckt 74480 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_
+* c:\fossee\esim\library\subcircuitlibrary\74480\74480.cir
+* u4 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad1_ d_xor
+* u5 net-_u1-pad3_ net-_u1-pad4_ net-_u10-pad2_ d_xor
+* u6 net-_u1-pad5_ net-_u1-pad6_ net-_u11-pad1_ d_xor
+* u7 net-_u1-pad7_ net-_u1-pad8_ net-_u11-pad2_ d_xor
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_xor
+* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u14-pad3_ d_xor
+* u8 net-_u1-pad11_ net-_u1-pad12_ net-_u12-pad1_ d_xor
+* u9 net-_u1-pad13_ net-_u1-pad14_ net-_u12-pad2_ d_xor
+* u2 net-_u1-pad15_ net-_u1-pad16_ net-_u13-pad1_ d_xor
+* u3 net-_u1-pad17_ net-_u1-pad18_ net-_u13-pad2_ d_xor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_xor
+* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u15-pad3_ d_xor
+* u20 net-_u14-pad3_ net-_u18-pad2_ net-_u1-pad20_ d_xor
+* u21 net-_u15-pad3_ net-_u19-pad2_ net-_u1-pad22_ d_xor
+* u22 net-_u1-pad20_ net-_u1-pad22_ net-_u1-pad21_ d_nor
+* u18 net-_u16-pad3_ net-_u18-pad2_ d_inverter
+* u16 net-_u1-pad9_ net-_u1-pad10_ net-_u16-pad3_ d_and
+* u17 net-_u1-pad10_ net-_u1-pad19_ net-_u17-pad3_ d_and
+* u19 net-_u17-pad3_ net-_u19-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad1_ u4
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u10-pad2_ u5
+a3 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u11-pad1_ u6
+a4 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u11-pad2_ u7
+a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a7 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u14-pad3_ u14
+a8 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u12-pad1_ u8
+a9 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u12-pad2_ u9
+a10 [net-_u1-pad15_ net-_u1-pad16_ ] net-_u13-pad1_ u2
+a11 [net-_u1-pad17_ net-_u1-pad18_ ] net-_u13-pad2_ u3
+a12 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a13 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u15-pad3_ u15
+a15 [net-_u14-pad3_ net-_u18-pad2_ ] net-_u1-pad20_ u20
+a16 [net-_u15-pad3_ net-_u19-pad2_ ] net-_u1-pad22_ u21
+a17 [net-_u1-pad20_ net-_u1-pad22_ ] net-_u1-pad21_ u22
+a18 net-_u16-pad3_ net-_u18-pad2_ u18
+a19 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u16-pad3_ u16
+a20 [net-_u1-pad10_ net-_u1-pad19_ ] net-_u17-pad3_ u17
+a21 net-_u17-pad3_ net-_u19-pad2_ u19
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u15 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u21 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74480 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-06-01 17:18:40 +0000