diff options
Diffstat (limited to 'library/SubcircuitLibrary/74F350')
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and-cache.lib | 61 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and.cir | 13 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and.cir.out | 20 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and.pro | 43 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and.sch | 130 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and.sub | 14 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350-cache.lib | 112 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350.cir | 48 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350.cir.out | 113 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350.pro | 69 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350.sch | 1000 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350.sub | 107 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74F350/analysis | 1 |
15 files changed, 1733 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74F350/3_and-cache.lib b/library/SubcircuitLibrary/74F350/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/3_and.cir b/library/SubcircuitLibrary/74F350/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.cir.out b/library/SubcircuitLibrary/74F350/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.pro b/library/SubcircuitLibrary/74F350/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/3_and.sch b/library/SubcircuitLibrary/74F350/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/3_and.sub b/library/SubcircuitLibrary/74F350/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350-cache.lib b/library/SubcircuitLibrary/74F350/74F350-cache.lib new file mode 100644 index 00000000..8256d8a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350-cache.lib @@ -0,0 +1,112 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/74F350.cir b/library/SubcircuitLibrary/74F350/74F350.cir new file mode 100644 index 00000000..87560c28 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir @@ -0,0 +1,48 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\74F350\74F350.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:58:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X16 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad7_ Net-_U16-Pad1_ 3_and +X15 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U16-Pad2_ 3_and +X14 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad5_ Net-_U13-Pad1_ 3_and +X13 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U13-Pad2_ 3_and +X12 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U12-Pad1_ 3_and +X11 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U12-Pad2_ 3_and +X10 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U9-Pad1_ 3_and +X9 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U9-Pad2_ 3_and +X8 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U8-Pad1_ 3_and +X7 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U8-Pad2_ 3_and +X6 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U6-Pad1_ 3_and +X5 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U6-Pad2_ 3_and +X4 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad1_ 3_and +X3 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad2_ 3_and +X2 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U2-Pad1_ 3_and +X1 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad1_ Net-_U2-Pad2_ 3_and +U26 Net-_U1-Pad13_ Net-_U10-Pad1_ d_inverter +U24 Net-_U1-Pad10_ Net-_U24-Pad2_ d_inverter +U22 Net-_U1-Pad9_ Net-_U22-Pad2_ d_inverter +U25 Net-_U24-Pad2_ Net-_U25-Pad2_ d_inverter +U23 Net-_U22-Pad2_ Net-_U23-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U20 Net-_U10-Pad1_ Net-_U14-Pad3_ Net-_U1-Pad15_ d_and +U15 Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U1-Pad14_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad12_ d_and +U5 Net-_U10-Pad1_ Net-_U3-Pad3_ Net-_U1-Pad11_ d_and +U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U7 Net-_U7-Pad1_ Net-_U6-Pad3_ Net-_U10-Pad2_ d_or +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U14-Pad1_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U11-Pad2_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U7-Pad1_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ d_or +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_or +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.cir.out b/library/SubcircuitLibrary/74F350/74F350.cir.out new file mode 100644 index 00000000..b90caa5e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir.out @@ -0,0 +1,113 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir + +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.pro b/library/SubcircuitLibrary/74F350/74F350.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/74F350.sch b/library/SubcircuitLibrary/74F350/74F350.sch new file mode 100644 index 00000000..989985a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sch @@ -0,0 +1,1000 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:74F350-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X16 +U 1 1 679DB336 +P 15400 7400 +F 0 "X16" H 15500 7350 60 0000 C CNN +F 1 "3_and" H 15550 7550 60 0000 C CNN +F 2 "" H 15400 7400 60 0000 C CNN +F 3 "" H 15400 7400 60 0000 C CNN + 1 15400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X15 +U 1 1 679DB473 +P 14650 7400 +F 0 "X15" H 14750 7350 60 0000 C CNN +F 1 "3_and" H 14800 7550 60 0000 C CNN +F 2 "" H 14650 7400 60 0000 C CNN +F 3 "" H 14650 7400 60 0000 C CNN + 1 14650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X14 +U 1 1 679DB4EB +P 14050 7400 +F 0 "X14" H 14150 7350 60 0000 C CNN +F 1 "3_and" H 14200 7550 60 0000 C CNN +F 2 "" H 14050 7400 60 0000 C CNN +F 3 "" H 14050 7400 60 0000 C CNN + 1 14050 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X13 +U 1 1 679DB4F1 +P 13300 7400 +F 0 "X13" H 13400 7350 60 0000 C CNN +F 1 "3_and" H 13450 7550 60 0000 C CNN +F 2 "" H 13300 7400 60 0000 C CNN +F 3 "" H 13300 7400 60 0000 C CNN + 1 13300 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X12 +U 1 1 679DB5C3 +P 12750 7400 +F 0 "X12" H 12850 7350 60 0000 C CNN +F 1 "3_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12750 7400 60 0000 C CNN +F 3 "" H 12750 7400 60 0000 C CNN + 1 12750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X11 +U 1 1 679DB5C9 +P 12000 7400 +F 0 "X11" H 12100 7350 60 0000 C CNN +F 1 "3_and" H 12150 7550 60 0000 C CNN +F 2 "" H 12000 7400 60 0000 C CNN +F 3 "" H 12000 7400 60 0000 C CNN + 1 12000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X10 +U 1 1 679DB5CF +P 11400 7400 +F 0 "X10" H 11500 7350 60 0000 C CNN +F 1 "3_and" H 11550 7550 60 0000 C CNN +F 2 "" H 11400 7400 60 0000 C CNN +F 3 "" H 11400 7400 60 0000 C CNN + 1 11400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X9 +U 1 1 679DB5D5 +P 10650 7400 +F 0 "X9" H 10750 7350 60 0000 C CNN +F 1 "3_and" H 10800 7550 60 0000 C CNN +F 2 "" H 10650 7400 60 0000 C CNN +F 3 "" H 10650 7400 60 0000 C CNN + 1 10650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X8 +U 1 1 679DB885 +P 10100 7400 +F 0 "X8" H 10200 7350 60 0000 C CNN +F 1 "3_and" H 10250 7550 60 0000 C CNN +F 2 "" H 10100 7400 60 0000 C CNN +F 3 "" H 10100 7400 60 0000 C CNN + 1 10100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X7 +U 1 1 679DB88B +P 9350 7400 +F 0 "X7" H 9450 7350 60 0000 C CNN +F 1 "3_and" H 9500 7550 60 0000 C CNN +F 2 "" H 9350 7400 60 0000 C CNN +F 3 "" H 9350 7400 60 0000 C CNN + 1 9350 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X6 +U 1 1 679DB891 +P 8750 7400 +F 0 "X6" H 8850 7350 60 0000 C CNN +F 1 "3_and" H 8900 7550 60 0000 C CNN +F 2 "" H 8750 7400 60 0000 C CNN +F 3 "" H 8750 7400 60 0000 C CNN + 1 8750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X5 +U 1 1 679DB897 +P 8000 7400 +F 0 "X5" H 8100 7350 60 0000 C CNN +F 1 "3_and" H 8150 7550 60 0000 C CNN +F 2 "" H 8000 7400 60 0000 C CNN +F 3 "" H 8000 7400 60 0000 C CNN + 1 8000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X4 +U 1 1 679DB89D +P 7450 7400 +F 0 "X4" H 7550 7350 60 0000 C CNN +F 1 "3_and" H 7600 7550 60 0000 C CNN +F 2 "" H 7450 7400 60 0000 C CNN +F 3 "" H 7450 7400 60 0000 C CNN + 1 7450 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X3 +U 1 1 679DB8A3 +P 6700 7400 +F 0 "X3" H 6800 7350 60 0000 C CNN +F 1 "3_and" H 6850 7550 60 0000 C CNN +F 2 "" H 6700 7400 60 0000 C CNN +F 3 "" H 6700 7400 60 0000 C CNN + 1 6700 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X2 +U 1 1 679DB8A9 +P 6100 7400 +F 0 "X2" H 6200 7350 60 0000 C CNN +F 1 "3_and" H 6250 7550 60 0000 C CNN +F 2 "" H 6100 7400 60 0000 C CNN +F 3 "" H 6100 7400 60 0000 C CNN + 1 6100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 679DB8AF +P 5350 7400 +F 0 "X1" H 5450 7350 60 0000 C CNN +F 1 "3_and" H 5500 7550 60 0000 C CNN +F 2 "" H 5350 7400 60 0000 C CNN +F 3 "" H 5350 7400 60 0000 C CNN + 1 5350 7400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U26 +U 1 1 679DBBC7 +P 17700 3200 +F 0 "U26" H 17700 3100 60 0000 C CNN +F 1 "d_inverter" H 17700 3350 60 0000 C CNN +F 2 "" H 17750 3150 60 0000 C CNN +F 3 "" H 17750 3150 60 0000 C CNN + 1 17700 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 679DBC88 +P 16900 3200 +F 0 "U24" H 16900 3100 60 0000 C CNN +F 1 "d_inverter" H 16900 3350 60 0000 C CNN +F 2 "" H 16950 3150 60 0000 C CNN +F 3 "" H 16950 3150 60 0000 C CNN + 1 16900 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U22 +U 1 1 679DBCDF +P 16150 3200 +F 0 "U22" H 16150 3100 60 0000 C CNN +F 1 "d_inverter" H 16150 3350 60 0000 C CNN +F 2 "" H 16200 3150 60 0000 C CNN +F 3 "" H 16200 3150 60 0000 C CNN + 1 16150 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U25 +U 1 1 679DBD6D +P 16900 4200 +F 0 "U25" H 16900 4100 60 0000 C CNN +F 1 "d_inverter" H 16900 4350 60 0000 C CNN +F 2 "" H 16950 4150 60 0000 C CNN +F 3 "" H 16950 4150 60 0000 C CNN + 1 16900 4200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U23 +U 1 1 679DBD73 +P 16150 4200 +F 0 "U23" H 16150 4100 60 0000 C CNN +F 1 "d_inverter" H 16150 4350 60 0000 C CNN +F 2 "" H 16200 4150 60 0000 C CNN +F 3 "" H 16200 4150 60 0000 C CNN + 1 16150 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 679EA80D +P 17700 2050 +F 0 "U1" H 17750 2150 30 0000 C CNN +F 1 "PORT" H 17700 2050 30 0000 C CNN +F 2 "" H 17700 2050 60 0000 C CNN +F 3 "" H 17700 2050 60 0000 C CNN + 13 17700 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 679EAA26 +P 16900 2050 +F 0 "U1" H 16950 2150 30 0000 C CNN +F 1 "PORT" H 16900 2050 30 0000 C CNN +F 2 "" H 16900 2050 60 0000 C CNN +F 3 "" H 16900 2050 60 0000 C CNN + 10 16900 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679EAAAF +P 16150 2100 +F 0 "U1" H 16200 2200 30 0000 C CNN +F 1 "PORT" H 16150 2100 30 0000 C CNN +F 2 "" H 16150 2100 60 0000 C CNN +F 3 "" H 16150 2100 60 0000 C CNN + 9 16150 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 679EAB54 +P 15350 2150 +F 0 "U1" H 15400 2250 30 0000 C CNN +F 1 "PORT" H 15350 2150 30 0000 C CNN +F 2 "" H 15350 2150 60 0000 C CNN +F 3 "" H 15350 2150 60 0000 C CNN + 7 15350 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 679EAD32 +P 14600 2150 +F 0 "U1" H 14650 2250 30 0000 C CNN +F 1 "PORT" H 14600 2150 30 0000 C CNN +F 2 "" H 14600 2150 60 0000 C CNN +F 3 "" H 14600 2150 60 0000 C CNN + 6 14600 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 679EAD38 +P 14000 2150 +F 0 "U1" H 14050 2250 30 0000 C CNN +F 1 "PORT" H 14000 2150 30 0000 C CNN +F 2 "" H 14000 2150 60 0000 C CNN +F 3 "" H 14000 2150 60 0000 C CNN + 5 14000 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 679EAD3E +P 13250 2150 +F 0 "U1" H 13300 2250 30 0000 C CNN +F 1 "PORT" H 13250 2150 30 0000 C CNN +F 2 "" H 13250 2150 60 0000 C CNN +F 3 "" H 13250 2150 60 0000 C CNN + 4 13250 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 679EB065 +P 10600 2300 +F 0 "U1" H 10650 2400 30 0000 C CNN +F 1 "PORT" H 10600 2300 30 0000 C CNN +F 2 "" H 10600 2300 60 0000 C CNN +F 3 "" H 10600 2300 60 0000 C CNN + 3 10600 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 679EB06B +P 7950 2200 +F 0 "U1" H 8000 2300 30 0000 C CNN +F 1 "PORT" H 7950 2200 30 0000 C CNN +F 2 "" H 7950 2200 60 0000 C CNN +F 3 "" H 7950 2200 60 0000 C CNN + 2 7950 2200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 679EB071 +P 5300 2250 +F 0 "U1" H 5350 2350 30 0000 C CNN +F 1 "PORT" H 5300 2250 30 0000 C CNN +F 2 "" H 5300 2250 60 0000 C CNN +F 3 "" H 5300 2250 60 0000 C CNN + 1 5300 2250 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 679E10AA +P 19450 7550 +F 0 "U1" H 19500 7650 30 0000 C CNN +F 1 "PORT" H 19450 7550 30 0000 C CNN +F 2 "" H 19450 7550 60 0000 C CNN +F 3 "" H 19450 7550 60 0000 C CNN + 8 19450 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 679E1213 +P 19450 7800 +F 0 "U1" H 19500 7900 30 0000 C CNN +F 1 "PORT" H 19450 7800 30 0000 C CNN +F 2 "" H 19450 7800 60 0000 C CNN +F 3 "" H 19450 7800 60 0000 C CNN + 16 19450 7800 + 1 0 0 -1 +$EndComp +NoConn ~ 19700 7550 +NoConn ~ 19700 7800 +Wire Wire Line + 17700 2300 17700 2900 +Wire Wire Line + 16900 2300 16900 2900 +Wire Wire Line + 16150 2350 16150 2900 +Wire Wire Line + 16900 3500 16900 3900 +Wire Wire Line + 16150 3500 16150 3900 +Wire Wire Line + 16900 6750 16900 4500 +Wire Wire Line + 5500 6750 16900 6750 +Wire Wire Line + 14800 6750 14800 7050 +Wire Wire Line + 13450 6750 13450 7050 +Connection ~ 14800 6750 +Wire Wire Line + 12150 6750 12150 7050 +Connection ~ 13450 6750 +Wire Wire Line + 10800 6750 10800 7050 +Connection ~ 12150 6750 +Wire Wire Line + 9500 6750 9500 7050 +Connection ~ 10800 6750 +Wire Wire Line + 8150 6750 8150 7050 +Connection ~ 9500 6750 +Wire Wire Line + 6850 6750 6850 7050 +Connection ~ 8150 6750 +Wire Wire Line + 5500 6750 5500 7050 +Connection ~ 6850 6750 +Wire Wire Line + 16900 3750 16550 3750 +Wire Wire Line + 16550 3750 16550 6550 +Wire Wire Line + 16550 6550 6250 6550 +Wire Wire Line + 15550 6550 15550 7050 +Connection ~ 16900 3750 +Wire Wire Line + 14200 6550 14200 7050 +Connection ~ 15550 6550 +Wire Wire Line + 12900 6550 12900 7050 +Connection ~ 14200 6550 +Wire Wire Line + 11550 6550 11550 7050 +Connection ~ 12900 6550 +Wire Wire Line + 10250 6550 10250 7050 +Connection ~ 11550 6550 +Wire Wire Line + 8900 6550 8900 7050 +Connection ~ 10250 6550 +Wire Wire Line + 7600 6550 7600 7050 +Connection ~ 8900 6550 +Wire Wire Line + 6250 6550 6250 7050 +Connection ~ 7600 6550 +Wire Wire Line + 16150 6350 16150 4500 +Wire Wire Line + 5400 6350 16150 6350 +Wire Wire Line + 14100 6350 14100 7050 +Wire Wire Line + 13350 6350 13350 7050 +Connection ~ 14100 6350 +Wire Wire Line + 11450 6350 11450 7050 +Connection ~ 13350 6350 +Wire Wire Line + 10700 6350 10700 7050 +Connection ~ 11450 6350 +Wire Wire Line + 8800 6350 8800 7050 +Connection ~ 10700 6350 +Wire Wire Line + 8050 6350 8050 7050 +Connection ~ 8800 6350 +Wire Wire Line + 6150 6350 6150 7050 +Connection ~ 8050 6350 +Wire Wire Line + 5400 6350 5400 7050 +Connection ~ 6150 6350 +Wire Wire Line + 16150 3750 15750 3750 +Wire Wire Line + 15750 3750 15750 6150 +Wire Wire Line + 15750 6150 6750 6150 +Wire Wire Line + 15450 6150 15450 7050 +Connection ~ 16150 3750 +Wire Wire Line + 14700 6150 14700 7050 +Connection ~ 15450 6150 +Wire Wire Line + 12800 6150 12800 7050 +Connection ~ 14700 6150 +Wire Wire Line + 12050 6150 12050 7050 +Connection ~ 12800 6150 +Wire Wire Line + 10150 6150 10150 7050 +Connection ~ 12050 6150 +Wire Wire Line + 9400 6150 9400 7050 +Connection ~ 10150 6150 +Wire Wire Line + 7500 6150 7500 7050 +Connection ~ 9400 6150 +Wire Wire Line + 6750 6150 6750 7050 +Connection ~ 7500 6150 +Wire Wire Line + 15350 2400 15350 7050 +Wire Wire Line + 14600 2400 14600 7050 +Wire Wire Line + 14000 2400 14000 7050 +Wire Wire Line + 13250 2400 13250 7050 +Wire Wire Line + 5300 2500 5300 7050 +Wire Wire Line + 7950 2450 7950 7050 +Wire Wire Line + 10600 2550 10600 7050 +Wire Wire Line + 12700 7050 12700 4400 +Wire Wire Line + 12700 4400 14600 4400 +Connection ~ 14600 4400 +Wire Wire Line + 11950 7050 11950 4600 +Wire Wire Line + 10050 4600 14000 4600 +Connection ~ 14000 4600 +Wire Wire Line + 11350 7050 11350 4850 +Wire Wire Line + 7400 4850 13250 4850 +Connection ~ 13250 4850 +Wire Wire Line + 10050 7050 10050 4600 +Connection ~ 11950 4600 +Wire Wire Line + 9300 7050 9300 4850 +Connection ~ 11350 4850 +Wire Wire Line + 8700 7050 8700 4200 +Wire Wire Line + 6650 4200 10600 4200 +Connection ~ 10600 4200 +Wire Wire Line + 7400 4850 7400 7050 +Connection ~ 9300 4850 +Wire Wire Line + 6050 7050 6050 5100 +Wire Wire Line + 6050 5100 7950 5100 +Connection ~ 7950 5100 +Wire Wire Line + 6650 7050 6650 4200 +Connection ~ 8700 4200 +Wire Wire Line + 15450 7900 15450 8250 +Wire Wire Line + 15450 8250 15250 8250 +Wire Wire Line + 15250 8250 15250 8500 +Wire Wire Line + 15150 8500 15150 8250 +Wire Wire Line + 15150 8250 14700 8250 +Wire Wire Line + 14700 8250 14700 7900 +Wire Wire Line + 14100 7900 14100 8150 +Wire Wire Line + 14100 8150 13800 8150 +Wire Wire Line + 13800 8150 13800 8500 +Wire Wire Line + 13700 8200 13700 8500 +Wire Wire Line + 13700 8200 13350 8200 +Wire Wire Line + 13350 8200 13350 7900 +Wire Wire Line + 12800 7900 12800 8200 +Wire Wire Line + 12800 8200 12600 8200 +Wire Wire Line + 12600 8200 12600 8500 +Wire Wire Line + 12500 8500 12500 8250 +Wire Wire Line + 12500 8250 12050 8250 +Wire Wire Line + 12050 8250 12050 7900 +Wire Wire Line + 11450 7900 11450 8100 +Wire Wire Line + 11450 8100 11150 8100 +Wire Wire Line + 11150 8100 11150 8500 +Wire Wire Line + 11000 8500 11000 8250 +Wire Wire Line + 11000 8250 10700 8250 +Wire Wire Line + 10700 8250 10700 7900 +Wire Wire Line + 11000 8500 11050 8500 +Wire Wire Line + 10150 7900 10150 8150 +Wire Wire Line + 10150 8150 9900 8150 +Wire Wire Line + 9900 8150 9900 8600 +Wire Wire Line + 9800 8600 9800 8150 +Wire Wire Line + 9800 8150 9400 8150 +Wire Wire Line + 9400 8150 9400 7900 +Wire Wire Line + 8800 7900 8800 8200 +Wire Wire Line + 8800 8200 8450 8200 +Wire Wire Line + 8450 8200 8450 8600 +Wire Wire Line + 8350 8250 8350 8600 +Wire Wire Line + 8350 8250 8050 8250 +Wire Wire Line + 8050 8250 8050 7900 +Wire Wire Line + 7500 7900 7500 8200 +Wire Wire Line + 7500 8200 7250 8200 +Wire Wire Line + 7250 8200 7250 8600 +Wire Wire Line + 7150 8600 7150 8300 +Wire Wire Line + 7150 8300 6750 8300 +Wire Wire Line + 6750 8300 6750 7900 +Wire Wire Line + 6150 7900 6150 8150 +Wire Wire Line + 6150 8150 5800 8150 +Wire Wire Line + 5800 8150 5800 8600 +Wire Wire Line + 5700 8600 5700 8150 +Wire Wire Line + 5700 8150 5400 8150 +Wire Wire Line + 5400 8150 5400 7900 +Wire Wire Line + 15200 9400 15200 9600 +Wire Wire Line + 15200 9600 14600 9600 +Wire Wire Line + 14600 9600 14600 9900 +Wire Wire Line + 14500 9650 14500 9900 +Wire Wire Line + 14500 9650 13750 9650 +Wire Wire Line + 13750 9650 13750 9400 +Wire Wire Line + 12550 9400 12550 9550 +Wire Wire Line + 12550 9550 11950 9550 +Wire Wire Line + 11950 9550 11950 9900 +Wire Wire Line + 11850 9600 11850 9900 +Wire Wire Line + 11850 9600 11100 9600 +Wire Wire Line + 11100 9600 11100 9400 +Wire Wire Line + 9850 9500 9850 9700 +Wire Wire Line + 9850 9700 9250 9700 +Wire Wire Line + 9250 9700 9250 10000 +Wire Wire Line + 9150 10000 9150 9750 +Wire Wire Line + 9150 9750 8400 9750 +Wire Wire Line + 8400 9750 8400 9500 +Wire Wire Line + 7200 9500 7200 9750 +Wire Wire Line + 7200 9750 6600 9750 +Wire Wire Line + 6600 9750 6600 10000 +Wire Wire Line + 6500 9750 6500 10000 +Wire Wire Line + 6500 9750 5750 9750 +Wire Wire Line + 5750 9750 5750 9500 +Wire Wire Line + 17700 11300 17700 3500 +Wire Wire Line + 14600 12500 14600 12850 +Wire Wire Line + 11950 12500 11950 12800 +$Comp +L PORT U1 +U 15 1 679DE2A7 +P 14600 13100 +F 0 "U1" H 14650 13200 30 0000 C CNN +F 1 "PORT" H 14600 13100 30 0000 C CNN +F 2 "" H 14600 13100 60 0000 C CNN +F 3 "" H 14600 13100 60 0000 C CNN + 15 14600 13100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 679DE336 +P 11950 13050 +F 0 "U1" H 12000 13150 30 0000 C CNN +F 1 "PORT" H 11950 13050 30 0000 C CNN +F 2 "" H 11950 13050 60 0000 C CNN +F 3 "" H 11950 13050 60 0000 C CNN + 14 11950 13050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 679DE476 +P 9250 12950 +F 0 "U1" H 9300 13050 30 0000 C CNN +F 1 "PORT" H 9250 12950 30 0000 C CNN +F 2 "" H 9250 12950 60 0000 C CNN +F 3 "" H 9250 12950 60 0000 C CNN + 12 9250 12950 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 679DE565 +P 6600 13000 +F 0 "U1" H 6650 13100 30 0000 C CNN +F 1 "PORT" H 6600 13000 30 0000 C CNN +F 2 "" H 6600 13000 60 0000 C CNN +F 3 "" H 6600 13000 60 0000 C CNN + 11 6600 13000 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6550 10900 6550 11750 +Wire Wire Line + 9200 10900 9200 11750 +Wire Wire Line + 11900 10800 11900 11600 +Wire Wire Line + 14550 10800 14550 11600 +$Comp +L d_and U20 +U 1 1 679EFE6B +P 14550 12050 +F 0 "U20" H 14550 12050 60 0000 C CNN +F 1 "d_and" H 14600 12150 60 0000 C CNN +F 2 "" H 14550 12050 60 0000 C CNN +F 3 "" H 14550 12050 60 0000 C CNN + 1 14550 12050 + 0 1 1 0 +$EndComp +$Comp +L d_and U15 +U 1 1 679EFF83 +P 11900 12050 +F 0 "U15" H 11900 12050 60 0000 C CNN +F 1 "d_and" H 11950 12150 60 0000 C CNN +F 2 "" H 11900 12050 60 0000 C CNN +F 3 "" H 11900 12050 60 0000 C CNN + 1 11900 12050 + 0 1 1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 679F0140 +P 9200 12200 +F 0 "U10" H 9200 12200 60 0000 C CNN +F 1 "d_and" H 9250 12300 60 0000 C CNN +F 2 "" H 9200 12200 60 0000 C CNN +F 3 "" H 9200 12200 60 0000 C CNN + 1 9200 12200 + 0 1 1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 679F01D7 +P 6550 12200 +F 0 "U5" H 6550 12200 60 0000 C CNN +F 1 "d_and" H 6600 12300 60 0000 C CNN +F 2 "" H 6550 12200 60 0000 C CNN +F 3 "" H 6550 12200 60 0000 C CNN + 1 6550 12200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6600 12750 6600 12650 +Wire Wire Line + 9250 12700 9250 12650 +Wire Wire Line + 17700 11300 15050 11300 +Wire Wire Line + 15050 10850 15050 11600 +Wire Wire Line + 15050 11600 14650 11600 +Wire Wire Line + 7100 10850 15050 10850 +Wire Wire Line + 12300 11600 12000 11600 +Connection ~ 15050 11300 +Wire Wire Line + 9950 11750 9300 11750 +Connection ~ 12300 10850 +Wire Wire Line + 7100 11750 6650 11750 +Connection ~ 9950 10850 +$Comp +L d_or U14 +U 1 1 67A37333 +P 14500 10350 +F 0 "U14" H 14500 10350 60 0000 C CNN +F 1 "d_or" H 14500 10450 60 0000 C CNN +F 2 "" H 14500 10350 60 0000 C CNN +F 3 "" H 14500 10350 60 0000 C CNN + 1 14500 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U11 +U 1 1 67A375DC +P 11850 10350 +F 0 "U11" H 11850 10350 60 0000 C CNN +F 1 "d_or" H 11850 10450 60 0000 C CNN +F 2 "" H 11850 10350 60 0000 C CNN +F 3 "" H 11850 10350 60 0000 C CNN + 1 11850 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U7 +U 1 1 67A376D5 +P 9150 10450 +F 0 "U7" H 9150 10450 60 0000 C CNN +F 1 "d_or" H 9150 10550 60 0000 C CNN +F 2 "" H 9150 10450 60 0000 C CNN +F 3 "" H 9150 10450 60 0000 C CNN + 1 9150 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U3 +U 1 1 67A377D6 +P 6500 10450 +F 0 "U3" H 6500 10450 60 0000 C CNN +F 1 "d_or" H 6500 10550 60 0000 C CNN +F 2 "" H 6500 10450 60 0000 C CNN +F 3 "" H 6500 10450 60 0000 C CNN + 1 6500 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U16 +U 1 1 67A37A21 +P 15150 8950 +F 0 "U16" H 15150 8950 60 0000 C CNN +F 1 "d_or" H 15150 9050 60 0000 C CNN +F 2 "" H 15150 8950 60 0000 C CNN +F 3 "" H 15150 8950 60 0000 C CNN + 1 15150 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U13 +U 1 1 67A37ADA +P 13700 8950 +F 0 "U13" H 13700 8950 60 0000 C CNN +F 1 "d_or" H 13700 9050 60 0000 C CNN +F 2 "" H 13700 8950 60 0000 C CNN +F 3 "" H 13700 8950 60 0000 C CNN + 1 13700 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U12 +U 1 1 67A37C7D +P 12500 8950 +F 0 "U12" H 12500 8950 60 0000 C CNN +F 1 "d_or" H 12500 9050 60 0000 C CNN +F 2 "" H 12500 8950 60 0000 C CNN +F 3 "" H 12500 8950 60 0000 C CNN + 1 12500 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U9 +U 1 1 67A37CFE +P 11050 8950 +F 0 "U9" H 11050 8950 60 0000 C CNN +F 1 "d_or" H 11050 9050 60 0000 C CNN +F 2 "" H 11050 8950 60 0000 C CNN +F 3 "" H 11050 8950 60 0000 C CNN + 1 11050 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U8 +U 1 1 67A37DF9 +P 9800 9050 +F 0 "U8" H 9800 9050 60 0000 C CNN +F 1 "d_or" H 9800 9150 60 0000 C CNN +F 2 "" H 9800 9050 60 0000 C CNN +F 3 "" H 9800 9050 60 0000 C CNN + 1 9800 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U6 +U 1 1 67A37FCE +P 8350 9050 +F 0 "U6" H 8350 9050 60 0000 C CNN +F 1 "d_or" H 8350 9150 60 0000 C CNN +F 2 "" H 8350 9050 60 0000 C CNN +F 3 "" H 8350 9050 60 0000 C CNN + 1 8350 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U4 +U 1 1 67A38059 +P 7150 9050 +F 0 "U4" H 7150 9050 60 0000 C CNN +F 1 "d_or" H 7150 9150 60 0000 C CNN +F 2 "" H 7150 9050 60 0000 C CNN +F 3 "" H 7150 9050 60 0000 C CNN + 1 7150 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U2 +U 1 1 67A38154 +P 5700 9050 +F 0 "U2" H 5700 9050 60 0000 C CNN +F 1 "d_or" H 5700 9150 60 0000 C CNN +F 2 "" H 5700 9050 60 0000 C CNN +F 3 "" H 5700 9050 60 0000 C CNN + 1 5700 9050 + 0 1 1 0 +$EndComp +Wire Wire Line + 12300 11600 12300 10850 +Wire Wire Line + 9950 11750 9950 10850 +Wire Wire Line + 7100 10850 7100 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/74F350.sub b/library/SubcircuitLibrary/74F350/74F350.sub new file mode 100644 index 00000000..39ba9abb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sub @@ -0,0 +1,107 @@ +* Subcircuit 74F350 +.subckt 74F350 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74F350
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml new file mode 100644 index 00000000..bc7f0ee5 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u26 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u26><u24 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u25><u23 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u21 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u12 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u11><u7 name="type">d_nor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_nor<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u6><u2 name="type">d_nor<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nor<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u3><u20 name="type">d_tristate<field52 name="Enter Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Enable Load (default=1.0e-12)" /></u20><u15 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u15><u10 name="type">d_tristate<field58 name="Enter Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Enable Load (default=1.0e-12)" /></u10><u5 name="type">d_tristate<field61 name="Enter Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Enable Load (default=1.0e-12)" /></u5><u4 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u14><u19 name="type">d_inverter<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u19><u10 name="type">d_nand<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_nand<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_nand<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u4><u20 name="type">d_and<field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u20><u15 name="type">d_and<field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u10><u5 name="type">d_and<field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u5><u14 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u11 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u11><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u3 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u16 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u16><u13 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u13><u12 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u12><u9 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u8 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u8><u6 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_or<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x10><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x15><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x16></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/analysis b/library/SubcircuitLibrary/74F350/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |