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-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib110
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286.cir31
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out92
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286.pro73
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286.proj1
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286.sch505
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286.sub86
-rw-r--r--library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74ACT11286/analysis1
9 files changed, 900 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib b/library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib
new file mode 100644
index 00000000..001e0ac1
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir
new file mode 100644
index 00000000..5af79599
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir
@@ -0,0 +1,31 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74ACT11286\74ACT11286.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/15/24 21:23:24
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U17 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U17-Pad3_ d_xnor
+U21 Net-_U1-Pad3_ Net-_U21-Pad2_ d_inverter
+U25 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U25-Pad3_ d_xnor
+U18 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad3_ d_xnor
+U22 Net-_U1-Pad6_ Net-_U22-Pad2_ d_inverter
+U26 Net-_U18-Pad3_ Net-_U22-Pad2_ Net-_U26-Pad3_ d_xnor
+U19 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U19-Pad3_ d_xnor
+U23 Net-_U1-Pad9_ Net-_U23-Pad2_ d_inverter
+U27 Net-_U19-Pad3_ Net-_U23-Pad2_ Net-_U27-Pad3_ d_xnor
+U29 Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U29-Pad3_ d_xnor
+U30 Net-_U27-Pad3_ Net-_U30-Pad2_ d_inverter
+U31 Net-_U29-Pad3_ Net-_U30-Pad2_ Net-_U24-Pad1_ d_xnor
+U32 Net-_U24-Pad1_ Net-_U32-Pad2_ d_inverter
+U33 Net-_U32-Pad2_ Net-_U28-Pad2_ Net-_U33-Pad3_ d_xnor
+U35 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U1-Pad12_ d_nand
+U34 Net-_U20-Pad2_ Net-_U34-Pad2_ d_inverter
+U28 Net-_U1-Pad10_ Net-_U28-Pad2_ d_inverter
+U20 Net-_U1-Pad11_ Net-_U20-Pad2_ d_inverter
+U24 Net-_U24-Pad1_ Net-_U20-Pad2_ Net-_U16-Pad1_ d_tristate
+U16 Net-_U16-Pad1_ Net-_U1-Pad10_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out
new file mode 100644
index 00000000..25df9f76
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out
@@ -0,0 +1,92 @@
+* c:\fossee\esim\library\subcircuitlibrary\74act11286\74act11286.cir
+
+* u17 net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_xnor
+* u21 net-_u1-pad3_ net-_u21-pad2_ d_inverter
+* u25 net-_u17-pad3_ net-_u21-pad2_ net-_u25-pad3_ d_xnor
+* u18 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad3_ d_xnor
+* u22 net-_u1-pad6_ net-_u22-pad2_ d_inverter
+* u26 net-_u18-pad3_ net-_u22-pad2_ net-_u26-pad3_ d_xnor
+* u19 net-_u1-pad7_ net-_u1-pad8_ net-_u19-pad3_ d_xnor
+* u23 net-_u1-pad9_ net-_u23-pad2_ d_inverter
+* u27 net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad3_ d_xnor
+* u29 net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad3_ d_xnor
+* u30 net-_u27-pad3_ net-_u30-pad2_ d_inverter
+* u31 net-_u29-pad3_ net-_u30-pad2_ net-_u24-pad1_ d_xnor
+* u32 net-_u24-pad1_ net-_u32-pad2_ d_inverter
+* u33 net-_u32-pad2_ net-_u28-pad2_ net-_u33-pad3_ d_xnor
+* u35 net-_u33-pad3_ net-_u34-pad2_ net-_u1-pad12_ d_nand
+* u34 net-_u20-pad2_ net-_u34-pad2_ d_inverter
+* u28 net-_u1-pad10_ net-_u28-pad2_ d_inverter
+* u20 net-_u1-pad11_ net-_u20-pad2_ d_inverter
+* u24 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_tristate
+* u16 net-_u16-pad1_ net-_u1-pad10_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17
+a2 net-_u1-pad3_ net-_u21-pad2_ u21
+a3 [net-_u17-pad3_ net-_u21-pad2_ ] net-_u25-pad3_ u25
+a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad3_ u18
+a5 net-_u1-pad6_ net-_u22-pad2_ u22
+a6 [net-_u18-pad3_ net-_u22-pad2_ ] net-_u26-pad3_ u26
+a7 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u19-pad3_ u19
+a8 net-_u1-pad9_ net-_u23-pad2_ u23
+a9 [net-_u19-pad3_ net-_u23-pad2_ ] net-_u27-pad3_ u27
+a10 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad3_ u29
+a11 net-_u27-pad3_ net-_u30-pad2_ u30
+a12 [net-_u29-pad3_ net-_u30-pad2_ ] net-_u24-pad1_ u31
+a13 net-_u24-pad1_ net-_u32-pad2_ u32
+a14 [net-_u32-pad2_ net-_u28-pad2_ ] net-_u33-pad3_ u33
+a15 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u1-pad12_ u35
+a16 net-_u20-pad2_ net-_u34-pad2_ u34
+a17 net-_u1-pad10_ net-_u28-pad2_ u28
+a18 net-_u1-pad11_ net-_u20-pad2_ u20
+a19 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ u24
+a20 net-_u16-pad1_ net-_u1-pad10_ u16
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u17 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u31 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u33 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.pro b/library/SubcircuitLibrary/74ACT11286/74ACT11286.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.proj b/library/SubcircuitLibrary/74ACT11286/74ACT11286.proj
new file mode 100644
index 00000000..ab6299e8
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.proj
@@ -0,0 +1 @@
+schematicFile 74ACT11286.sch
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.sch b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sch
new file mode 100644
index 00000000..2cf134b4
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sch
@@ -0,0 +1,505 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74ACT11286-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xnor U17
+U 1 1 666D7714
+P 15100 8600
+F 0 "U17" H 15100 8600 60 0000 C CNN
+F 1 "d_xnor" H 15150 8700 47 0000 C CNN
+F 2 "" H 15100 8600 60 0000 C CNN
+F 3 "" H 15100 8600 60 0000 C CNN
+ 1 15100 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 666D7745
+P 15250 8850
+F 0 "U21" H 15250 8750 60 0000 C CNN
+F 1 "d_inverter" H 15250 9000 60 0000 C CNN
+F 2 "" H 15300 8800 60 0000 C CNN
+F 3 "" H 15300 8800 60 0000 C CNN
+ 1 15250 8850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U25
+U 1 1 666D7764
+P 16000 8750
+F 0 "U25" H 16000 8750 60 0000 C CNN
+F 1 "d_xnor" H 16050 8850 47 0000 C CNN
+F 2 "" H 16000 8750 60 0000 C CNN
+F 3 "" H 16000 8750 60 0000 C CNN
+ 1 16000 8750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 15550 8650 15550 8550
+Wire Wire Line
+ 15550 8750 15550 8850
+Wire Wire Line
+ 14450 8500 14650 8500
+Wire Wire Line
+ 14450 8600 14650 8600
+Wire Wire Line
+ 14450 8850 14950 8850
+$Comp
+L d_xnor U18
+U 1 1 666D78DF
+P 15100 9550
+F 0 "U18" H 15100 9550 60 0000 C CNN
+F 1 "d_xnor" H 15150 9650 47 0000 C CNN
+F 2 "" H 15100 9550 60 0000 C CNN
+F 3 "" H 15100 9550 60 0000 C CNN
+ 1 15100 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U22
+U 1 1 666D78E5
+P 15250 9800
+F 0 "U22" H 15250 9700 60 0000 C CNN
+F 1 "d_inverter" H 15250 9950 60 0000 C CNN
+F 2 "" H 15300 9750 60 0000 C CNN
+F 3 "" H 15300 9750 60 0000 C CNN
+ 1 15250 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U26
+U 1 1 666D78EB
+P 16000 9700
+F 0 "U26" H 16000 9700 60 0000 C CNN
+F 1 "d_xnor" H 16050 9800 47 0000 C CNN
+F 2 "" H 16000 9700 60 0000 C CNN
+F 3 "" H 16000 9700 60 0000 C CNN
+ 1 16000 9700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 15550 9600 15550 9500
+Wire Wire Line
+ 15550 9700 15550 9800
+Wire Wire Line
+ 14450 9450 14650 9450
+Wire Wire Line
+ 14450 9550 14650 9550
+Wire Wire Line
+ 14450 9800 14950 9800
+$Comp
+L d_xnor U19
+U 1 1 666D799B
+P 15150 10450
+F 0 "U19" H 15150 10450 60 0000 C CNN
+F 1 "d_xnor" H 15200 10550 47 0000 C CNN
+F 2 "" H 15150 10450 60 0000 C CNN
+F 3 "" H 15150 10450 60 0000 C CNN
+ 1 15150 10450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U23
+U 1 1 666D79A1
+P 15300 10700
+F 0 "U23" H 15300 10600 60 0000 C CNN
+F 1 "d_inverter" H 15300 10850 60 0000 C CNN
+F 2 "" H 15350 10650 60 0000 C CNN
+F 3 "" H 15350 10650 60 0000 C CNN
+ 1 15300 10700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U27
+U 1 1 666D79A7
+P 16050 10600
+F 0 "U27" H 16050 10600 60 0000 C CNN
+F 1 "d_xnor" H 16100 10700 47 0000 C CNN
+F 2 "" H 16050 10600 60 0000 C CNN
+F 3 "" H 16050 10600 60 0000 C CNN
+ 1 16050 10600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 15600 10500 15600 10400
+Wire Wire Line
+ 15600 10600 15600 10700
+Wire Wire Line
+ 14500 10350 14700 10350
+Wire Wire Line
+ 14500 10450 14700 10450
+Wire Wire Line
+ 14500 10700 15000 10700
+$Comp
+L d_xnor U29
+U 1 1 666D7CAF
+P 17400 9600
+F 0 "U29" H 17400 9600 60 0000 C CNN
+F 1 "d_xnor" H 17450 9700 47 0000 C CNN
+F 2 "" H 17400 9600 60 0000 C CNN
+F 3 "" H 17400 9600 60 0000 C CNN
+ 1 17400 9600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U30
+U 1 1 666D7CB5
+P 17550 9850
+F 0 "U30" H 17550 9750 60 0000 C CNN
+F 1 "d_inverter" H 17550 10000 60 0000 C CNN
+F 2 "" H 17600 9800 60 0000 C CNN
+F 3 "" H 17600 9800 60 0000 C CNN
+ 1 17550 9850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U31
+U 1 1 666D7CBB
+P 18300 9750
+F 0 "U31" H 18300 9750 60 0000 C CNN
+F 1 "d_xnor" H 18350 9850 47 0000 C CNN
+F 2 "" H 18300 9750 60 0000 C CNN
+F 3 "" H 18300 9750 60 0000 C CNN
+ 1 18300 9750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 17850 9650 17850 9550
+Wire Wire Line
+ 17850 9750 17850 9850
+Wire Wire Line
+ 16750 9500 16950 9500
+Wire Wire Line
+ 16750 9600 16950 9600
+Wire Wire Line
+ 16750 9850 17250 9850
+$Comp
+L d_inverter U32
+U 1 1 666D7CDE
+P 19200 9700
+F 0 "U32" H 19200 9600 60 0000 C CNN
+F 1 "d_inverter" H 19200 9850 60 0000 C CNN
+F 2 "" H 19250 9650 60 0000 C CNN
+F 3 "" H 19250 9650 60 0000 C CNN
+ 1 19200 9700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U33
+U 1 1 666D7D3F
+P 20050 9800
+F 0 "U33" H 20050 9800 60 0000 C CNN
+F 1 "d_xnor" H 20100 9900 47 0000 C CNN
+F 2 "" H 20050 9800 60 0000 C CNN
+F 3 "" H 20050 9800 60 0000 C CNN
+ 1 20050 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U35
+U 1 1 666D7DCD
+P 21150 9850
+F 0 "U35" H 21150 9850 60 0000 C CNN
+F 1 "d_nand" H 21200 9950 60 0000 C CNN
+F 2 "" H 21150 9850 60 0000 C CNN
+F 3 "" H 21150 9850 60 0000 C CNN
+ 1 21150 9850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 666D7E1D
+P 20650 10400
+F 0 "U34" H 20650 10300 60 0000 C CNN
+F 1 "d_inverter" H 20650 10550 60 0000 C CNN
+F 2 "" H 20700 10350 60 0000 C CNN
+F 3 "" H 20700 10350 60 0000 C CNN
+ 1 20650 10400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U28
+U 1 1 666D7F1E
+P 16400 11550
+F 0 "U28" H 16400 11450 60 0000 C CNN
+F 1 "d_inverter" H 16400 11700 60 0000 C CNN
+F 2 "" H 16450 11500 60 0000 C CNN
+F 3 "" H 16450 11500 60 0000 C CNN
+ 1 16400 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U20
+U 1 1 666D7FCA
+P 15200 11750
+F 0 "U20" H 15200 11650 60 0000 C CNN
+F 1 "d_inverter" H 15200 11900 60 0000 C CNN
+F 2 "" H 15250 11700 60 0000 C CNN
+F 3 "" H 15250 11700 60 0000 C CNN
+ 1 15200 11750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_tristate U24
+U 1 1 666D806E
+P 15750 11500
+F 0 "U24" H 15500 11750 60 0000 C CNN
+F 1 "d_tristate" H 15550 11950 60 0000 C CNN
+F 2 "" H 15650 11850 60 0000 C CNN
+F 3 "" H 15650 11850 60 0000 C CNN
+ 1 15750 11500
+ -1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 666D80CE
+P 14900 11150
+F 0 "U16" H 14900 11050 60 0000 C CNN
+F 1 "d_inverter" H 14900 11300 60 0000 C CNN
+F 2 "" H 14950 11100 60 0000 C CNN
+F 3 "" H 14950 11100 60 0000 C CNN
+ 1 14900 11150
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 15800 11450 15800 11750
+Wire Wire Line
+ 15500 11750 20650 11750
+Wire Wire Line
+ 16100 11550 14600 11550
+Wire Wire Line
+ 14600 11550 14600 11150
+Wire Wire Line
+ 14600 11150 14500 11150
+Wire Wire Line
+ 14900 11750 14500 11750
+Wire Wire Line
+ 16350 11150 18850 11150
+Wire Wire Line
+ 18850 11150 18850 9700
+Wire Wire Line
+ 18750 9700 18900 9700
+Connection ~ 18850 9700
+Wire Wire Line
+ 19600 9700 19500 9700
+Wire Wire Line
+ 19600 9800 19600 11550
+Wire Wire Line
+ 19600 11550 16700 11550
+Wire Wire Line
+ 20650 11750 20650 10700
+Connection ~ 15800 11750
+Wire Wire Line
+ 20650 10100 20650 9850
+Wire Wire Line
+ 20650 9850 20700 9850
+Wire Wire Line
+ 20700 9750 20500 9750
+Wire Wire Line
+ 16750 9850 16750 10550
+Wire Wire Line
+ 16750 10550 16500 10550
+Wire Wire Line
+ 16750 9600 16750 9650
+Wire Wire Line
+ 16750 9650 16450 9650
+Wire Wire Line
+ 16750 9500 16750 8700
+Wire Wire Line
+ 16750 8700 16450 8700
+Wire Wire Line
+ 14500 11150 14500 11350
+Wire Wire Line
+ 14500 11750 14500 11450
+Wire Wire Line
+ 14500 10700 14500 10550
+Wire Wire Line
+ 14450 9800 14450 9650
+Wire Wire Line
+ 14450 8850 14450 8700
+$Comp
+L PORT U1
+U 1 1 666DBDFE
+P 14200 8500
+F 0 "U1" H 14250 8600 30 0000 C CNN
+F 1 "PORT" H 14200 8500 30 0000 C CNN
+F 2 "" H 14200 8500 60 0000 C CNN
+F 3 "" H 14200 8500 60 0000 C CNN
+ 1 14200 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 666DBE49
+P 14200 8600
+F 0 "U1" H 14250 8700 30 0000 C CNN
+F 1 "PORT" H 14200 8600 30 0000 C CNN
+F 2 "" H 14200 8600 60 0000 C CNN
+F 3 "" H 14200 8600 60 0000 C CNN
+ 2 14200 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 666DBE8A
+P 14200 8700
+F 0 "U1" H 14250 8800 30 0000 C CNN
+F 1 "PORT" H 14200 8700 30 0000 C CNN
+F 2 "" H 14200 8700 60 0000 C CNN
+F 3 "" H 14200 8700 60 0000 C CNN
+ 3 14200 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 666DBFCA
+P 14200 9450
+F 0 "U1" H 14250 9550 30 0000 C CNN
+F 1 "PORT" H 14200 9450 30 0000 C CNN
+F 2 "" H 14200 9450 60 0000 C CNN
+F 3 "" H 14200 9450 60 0000 C CNN
+ 4 14200 9450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 666DC00F
+P 14200 9550
+F 0 "U1" H 14250 9650 30 0000 C CNN
+F 1 "PORT" H 14200 9550 30 0000 C CNN
+F 2 "" H 14200 9550 60 0000 C CNN
+F 3 "" H 14200 9550 60 0000 C CNN
+ 5 14200 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 666DC056
+P 14200 9650
+F 0 "U1" H 14250 9750 30 0000 C CNN
+F 1 "PORT" H 14200 9650 30 0000 C CNN
+F 2 "" H 14200 9650 60 0000 C CNN
+F 3 "" H 14200 9650 60 0000 C CNN
+ 6 14200 9650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 666DC1A3
+P 14250 10350
+F 0 "U1" H 14300 10450 30 0000 C CNN
+F 1 "PORT" H 14250 10350 30 0000 C CNN
+F 2 "" H 14250 10350 60 0000 C CNN
+F 3 "" H 14250 10350 60 0000 C CNN
+ 7 14250 10350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 666DC1EE
+P 14250 10450
+F 0 "U1" H 14300 10550 30 0000 C CNN
+F 1 "PORT" H 14250 10450 30 0000 C CNN
+F 2 "" H 14250 10450 60 0000 C CNN
+F 3 "" H 14250 10450 60 0000 C CNN
+ 8 14250 10450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 666DC23B
+P 14250 10550
+F 0 "U1" H 14300 10650 30 0000 C CNN
+F 1 "PORT" H 14250 10550 30 0000 C CNN
+F 2 "" H 14250 10550 60 0000 C CNN
+F 3 "" H 14250 10550 60 0000 C CNN
+ 9 14250 10550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 666DC28A
+P 14250 11350
+F 0 "U1" H 14300 11450 30 0000 C CNN
+F 1 "PORT" H 14250 11350 30 0000 C CNN
+F 2 "" H 14250 11350 60 0000 C CNN
+F 3 "" H 14250 11350 60 0000 C CNN
+ 10 14250 11350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 666DC2DD
+P 14250 11450
+F 0 "U1" H 14300 11550 30 0000 C CNN
+F 1 "PORT" H 14250 11450 30 0000 C CNN
+F 2 "" H 14250 11450 60 0000 C CNN
+F 3 "" H 14250 11450 60 0000 C CNN
+ 11 14250 11450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 666DC4E2
+P 21850 9800
+F 0 "U1" H 21900 9900 30 0000 C CNN
+F 1 "PORT" H 21850 9800 30 0000 C CNN
+F 2 "" H 21850 9800 60 0000 C CNN
+F 3 "" H 21850 9800 60 0000 C CNN
+ 12 21850 9800
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub
new file mode 100644
index 00000000..bcf12808
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub
@@ -0,0 +1,86 @@
+* Subcircuit 74ACT11286
+.subckt 74ACT11286 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_
+* c:\fossee\esim\library\subcircuitlibrary\74act11286\74act11286.cir
+* u17 net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_xnor
+* u21 net-_u1-pad3_ net-_u21-pad2_ d_inverter
+* u25 net-_u17-pad3_ net-_u21-pad2_ net-_u25-pad3_ d_xnor
+* u18 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad3_ d_xnor
+* u22 net-_u1-pad6_ net-_u22-pad2_ d_inverter
+* u26 net-_u18-pad3_ net-_u22-pad2_ net-_u26-pad3_ d_xnor
+* u19 net-_u1-pad7_ net-_u1-pad8_ net-_u19-pad3_ d_xnor
+* u23 net-_u1-pad9_ net-_u23-pad2_ d_inverter
+* u27 net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad3_ d_xnor
+* u29 net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad3_ d_xnor
+* u30 net-_u27-pad3_ net-_u30-pad2_ d_inverter
+* u31 net-_u29-pad3_ net-_u30-pad2_ net-_u24-pad1_ d_xnor
+* u32 net-_u24-pad1_ net-_u32-pad2_ d_inverter
+* u33 net-_u32-pad2_ net-_u28-pad2_ net-_u33-pad3_ d_xnor
+* u35 net-_u33-pad3_ net-_u34-pad2_ net-_u1-pad12_ d_nand
+* u34 net-_u20-pad2_ net-_u34-pad2_ d_inverter
+* u28 net-_u1-pad10_ net-_u28-pad2_ d_inverter
+* u20 net-_u1-pad11_ net-_u20-pad2_ d_inverter
+* u24 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_tristate
+* u16 net-_u16-pad1_ net-_u1-pad10_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17
+a2 net-_u1-pad3_ net-_u21-pad2_ u21
+a3 [net-_u17-pad3_ net-_u21-pad2_ ] net-_u25-pad3_ u25
+a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad3_ u18
+a5 net-_u1-pad6_ net-_u22-pad2_ u22
+a6 [net-_u18-pad3_ net-_u22-pad2_ ] net-_u26-pad3_ u26
+a7 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u19-pad3_ u19
+a8 net-_u1-pad9_ net-_u23-pad2_ u23
+a9 [net-_u19-pad3_ net-_u23-pad2_ ] net-_u27-pad3_ u27
+a10 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad3_ u29
+a11 net-_u27-pad3_ net-_u30-pad2_ u30
+a12 [net-_u29-pad3_ net-_u30-pad2_ ] net-_u24-pad1_ u31
+a13 net-_u24-pad1_ net-_u32-pad2_ u32
+a14 [net-_u32-pad2_ net-_u28-pad2_ ] net-_u33-pad3_ u33
+a15 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u1-pad12_ u35
+a16 net-_u20-pad2_ net-_u34-pad2_ u34
+a17 net-_u1-pad10_ net-_u28-pad2_ u28
+a18 net-_u1-pad11_ net-_u20-pad2_ u20
+a19 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ u24
+a20 net-_u16-pad1_ net-_u1-pad10_ u16
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u17 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u31 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u33 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74ACT11286 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml b/library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml
new file mode 100644
index 00000000..805c7021
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u17 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u17><u21 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u21><u25 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u25><u18 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u18><u22 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_xnor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u26><u19 name="type">d_xnor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u23><u27 name="type">d_xnor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u27><u29 name="type">d_xnor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_xnor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_xnor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u33><u35 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u35><u34 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u34><u28 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u28><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u24 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u24><u16 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u16></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ACT11286/analysis b/library/SubcircuitLibrary/74ACT11286/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74ACT11286/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-21 17:07:33 +0000