diff options
Diffstat (limited to 'library/SubcircuitLibrary/74ACT11286/74ACT11286.cir')
-rw-r--r-- | library/SubcircuitLibrary/74ACT11286/74ACT11286.cir | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir new file mode 100644 index 00000000..5af79599 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74ACT11286\74ACT11286.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/15/24 21:23:24 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U17 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U17-Pad3_ d_xnor +U21 Net-_U1-Pad3_ Net-_U21-Pad2_ d_inverter +U25 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U25-Pad3_ d_xnor +U18 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad3_ d_xnor +U22 Net-_U1-Pad6_ Net-_U22-Pad2_ d_inverter +U26 Net-_U18-Pad3_ Net-_U22-Pad2_ Net-_U26-Pad3_ d_xnor +U19 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U19-Pad3_ d_xnor +U23 Net-_U1-Pad9_ Net-_U23-Pad2_ d_inverter +U27 Net-_U19-Pad3_ Net-_U23-Pad2_ Net-_U27-Pad3_ d_xnor +U29 Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U29-Pad3_ d_xnor +U30 Net-_U27-Pad3_ Net-_U30-Pad2_ d_inverter +U31 Net-_U29-Pad3_ Net-_U30-Pad2_ Net-_U24-Pad1_ d_xnor +U32 Net-_U24-Pad1_ Net-_U32-Pad2_ d_inverter +U33 Net-_U32-Pad2_ Net-_U28-Pad2_ Net-_U33-Pad3_ d_xnor +U35 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U1-Pad12_ d_nand +U34 Net-_U20-Pad2_ Net-_U34-Pad2_ d_inverter +U28 Net-_U1-Pad10_ Net-_U28-Pad2_ d_inverter +U20 Net-_U1-Pad11_ Net-_U20-Pad2_ d_inverter +U24 Net-_U24-Pad1_ Net-_U20-Pad2_ Net-_U16-Pad1_ d_tristate +U16 Net-_U16-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT + +.end |