1 files changed, 72 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/4017/4017.cir.out b/library/SubcircuitLibrary/4017/4017.cir.out
new file mode 100644
index 00000000..e3a384c5
--- /dev/null
+++ b/library/SubcircuitLibrary/4017/4017.cir.out
@@ -0,0 +1,72 @@
+* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir
+
+* u7  net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff
+* u11  net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff
+* u15  net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff
+* u19  net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff
+* u22  net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and
+* u3  net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and
+* u4  net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and
+* u5  net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and
+* u6  net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and
+* u8  net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and
+* u9  net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and
+a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7
+a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11
+a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15
+a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19
+a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22
+a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3
+a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4
+a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5
+a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6
+a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8
+a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9
+a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10
+a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12
+a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 5e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end