diff options
Diffstat (limited to 'library/SubcircuitLibrary/10bitDAC')
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib | 91 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC.cir | 32 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out | 66 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC.pro | 71 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC.sch | 555 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC.sub | 61 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/10bitDAC/analysis | 1 |
8 files changed, 878 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib new file mode 100644 index 00000000..f7dfef8a --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# summer +# +DEF summer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "summer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN1 1 -400 150 200 R 50 50 1 1 I +X IN2 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir new file mode 100644 index 00000000..7090a7d0 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir @@ -0,0 +1,32 @@ +* /home/sumanto/eSim-2.1/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Feb 7 03:24:28 2022 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 1024k +R2 Net-_R2-Pad1_ Net-_R1-Pad2_ 512k +R3 Net-_R3-Pad1_ Net-_R1-Pad2_ 256k +R4 Net-_R4-Pad1_ Net-_R1-Pad2_ 128k +R5 Net-_R5-Pad1_ Net-_R1-Pad2_ 64k +R6 Net-_R6-Pad1_ Net-_R1-Pad2_ 32k +R7 Net-_R7-Pad1_ Net-_R1-Pad2_ 16k +R9 Net-_R9-Pad1_ Net-_R1-Pad2_ 8k +R10 Net-_R10-Pad1_ Net-_R1-Pad2_ 4k +R11 Net-_R11-Pad1_ Net-_R1-Pad2_ 2k +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT +U2 Net-_R1-Pad2_ GND Net-_U1-Pad11_ summer +U3 Net-_U1-Pad1_ GND Net-_R1-Pad1_ summer +U8 Net-_U1-Pad2_ GND Net-_R2-Pad1_ summer +U4 Net-_U1-Pad3_ GND Net-_R3-Pad1_ summer +U5 Net-_U1-Pad4_ GND Net-_R4-Pad1_ summer +U9 Net-_U1-Pad5_ GND Net-_R5-Pad1_ summer +U10 Net-_U1-Pad6_ GND Net-_R6-Pad1_ summer +U6 Net-_U1-Pad7_ GND Net-_R7-Pad1_ summer +U7 Net-_U1-Pad8_ GND Net-_R9-Pad1_ summer +U12 Net-_U1-Pad9_ GND Net-_R10-Pad1_ summer +U11 Net-_U1-Pad10_ GND Net-_R11-Pad1_ summer + +.end diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out new file mode 100644 index 00000000..725a6302 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out @@ -0,0 +1,66 @@ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/10bitdac/10bitdac.cir + +r1 net-_r1-pad1_ net-_r1-pad2_ 1024k +r2 net-_r2-pad1_ net-_r1-pad2_ 512k +r3 net-_r3-pad1_ net-_r1-pad2_ 256k +r4 net-_r4-pad1_ net-_r1-pad2_ 128k +r5 net-_r5-pad1_ net-_r1-pad2_ 64k +r6 net-_r6-pad1_ net-_r1-pad2_ 32k +r7 net-_r7-pad1_ net-_r1-pad2_ 16k +r9 net-_r9-pad1_ net-_r1-pad2_ 8k +r10 net-_r10-pad1_ net-_r1-pad2_ 4k +r11 net-_r11-pad1_ net-_r1-pad2_ 2k +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +* u2 net-_r1-pad2_ gnd net-_u1-pad11_ summer +* u3 net-_u1-pad1_ gnd net-_r1-pad1_ summer +* u8 net-_u1-pad2_ gnd net-_r2-pad1_ summer +* u4 net-_u1-pad3_ gnd net-_r3-pad1_ summer +* u5 net-_u1-pad4_ gnd net-_r4-pad1_ summer +* u9 net-_u1-pad5_ gnd net-_r5-pad1_ summer +* u10 net-_u1-pad6_ gnd net-_r6-pad1_ summer +* u6 net-_u1-pad7_ gnd net-_r7-pad1_ summer +* u7 net-_u1-pad8_ gnd net-_r9-pad1_ summer +* u12 net-_u1-pad9_ gnd net-_r10-pad1_ summer +* u11 net-_u1-pad10_ gnd net-_r11-pad1_ summer +a1 [net-_r1-pad2_ gnd ] net-_u1-pad11_ u2 +a2 [net-_u1-pad1_ gnd ] net-_r1-pad1_ u3 +a3 [net-_u1-pad2_ gnd ] net-_r2-pad1_ u8 +a4 [net-_u1-pad3_ gnd ] net-_r3-pad1_ u4 +a5 [net-_u1-pad4_ gnd ] net-_r4-pad1_ u5 +a6 [net-_u1-pad5_ gnd ] net-_r5-pad1_ u9 +a7 [net-_u1-pad6_ gnd ] net-_r6-pad1_ u10 +a8 [net-_u1-pad7_ gnd ] net-_r7-pad1_ u6 +a9 [net-_u1-pad8_ gnd ] net-_r9-pad1_ u7 +a10 [net-_u1-pad9_ gnd ] net-_r10-pad1_ u12 +a11 [net-_u1-pad10_ gnd ] net-_r11-pad1_ u11 +* Schematic Name: summer, NgSpice Name: summer +.model u2 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u3 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u8 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u4 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u5 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u9 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u10 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u6 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u7 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u12 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u11 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +.tran 1e-03 10e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro b/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch new file mode 100644 index 00000000..09d81434 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch @@ -0,0 +1,555 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:10bitDAC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 61DEB37D +P 4400 2250 +F 0 "R1" H 4450 2380 50 0000 C CNN +F 1 "1024k" H 4450 2200 50 0000 C CNN +F 2 "" H 4450 2230 30 0000 C CNN +F 3 "" V 4450 2300 30 0000 C CNN + 1 4400 2250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 61DEB37E +P 4450 2550 +F 0 "R2" H 4500 2680 50 0000 C CNN +F 1 "512k" H 4500 2500 50 0000 C CNN +F 2 "" H 4500 2530 30 0000 C CNN +F 3 "" V 4500 2600 30 0000 C CNN + 1 4450 2550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 61DEB37F +P 4450 2850 +F 0 "R3" H 4500 2980 50 0000 C CNN +F 1 "256k" H 4500 2800 50 0000 C CNN +F 2 "" H 4500 2830 30 0000 C CNN +F 3 "" V 4500 2900 30 0000 C CNN + 1 4450 2850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 61DEB380 +P 4450 3200 +F 0 "R4" H 4500 3330 50 0000 C CNN +F 1 "128k" H 4500 3150 50 0000 C CNN +F 2 "" H 4500 3180 30 0000 C CNN +F 3 "" V 4500 3250 30 0000 C CNN + 1 4450 3200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 61DEB381 +P 4450 3550 +F 0 "R5" H 4500 3680 50 0000 C CNN +F 1 "64k" H 4500 3500 50 0000 C CNN +F 2 "" H 4500 3530 30 0000 C CNN +F 3 "" V 4500 3600 30 0000 C CNN + 1 4450 3550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 61DEB382 +P 4450 3900 +F 0 "R6" H 4500 4030 50 0000 C CNN +F 1 "32k" H 4500 3850 50 0000 C CNN +F 2 "" H 4500 3880 30 0000 C CNN +F 3 "" V 4500 3950 30 0000 C CNN + 1 4450 3900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 61DEB383 +P 4450 4250 +F 0 "R7" H 4500 4380 50 0000 C CNN +F 1 "16k" H 4500 4200 50 0000 C CNN +F 2 "" H 4500 4230 30 0000 C CNN +F 3 "" V 4500 4300 30 0000 C CNN + 1 4450 4250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 61DEB384 +P 4450 4600 +F 0 "R9" H 4500 4730 50 0000 C CNN +F 1 "8k" H 4500 4550 50 0000 C CNN +F 2 "" H 4500 4580 30 0000 C CNN +F 3 "" V 4500 4650 30 0000 C CNN + 1 4450 4600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 61DEB385 +P 4450 4900 +F 0 "R10" H 4500 5030 50 0000 C CNN +F 1 "4k" H 4500 4850 50 0000 C CNN +F 2 "" H 4500 4880 30 0000 C CNN +F 3 "" V 4500 4950 30 0000 C CNN + 1 4450 4900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 61DEB386 +P 4400 5200 +F 0 "R11" H 4450 5330 50 0000 C CNN +F 1 "2k" H 4450 5150 50 0000 C CNN +F 2 "" H 4450 5180 30 0000 C CNN +F 3 "" V 4450 5250 30 0000 C CNN + 1 4400 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 61DEFF7E +P 2100 6350 +F 0 "U1" H 2150 6450 30 0000 C CNN +F 1 "PORT" H 2100 6350 30 0000 C CNN +F 2 "" H 2100 6350 60 0000 C CNN +F 3 "" H 2100 6350 60 0000 C CNN + 10 2100 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 61DEFFF5 +P 2100 5800 +F 0 "U1" H 2150 5900 30 0000 C CNN +F 1 "PORT" H 2100 5800 30 0000 C CNN +F 2 "" H 2100 5800 60 0000 C CNN +F 3 "" H 2100 5800 60 0000 C CNN + 9 2100 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 61DF0058 +P 2050 5250 +F 0 "U1" H 2100 5350 30 0000 C CNN +F 1 "PORT" H 2050 5250 30 0000 C CNN +F 2 "" H 2050 5250 60 0000 C CNN +F 3 "" H 2050 5250 60 0000 C CNN + 8 2050 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 61DF00BB +P 2050 4650 +F 0 "U1" H 2100 4750 30 0000 C CNN +F 1 "PORT" H 2050 4650 30 0000 C CNN +F 2 "" H 2050 4650 60 0000 C CNN +F 3 "" H 2050 4650 60 0000 C CNN + 7 2050 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 61DF0148 +P 2100 4000 +F 0 "U1" H 2150 4100 30 0000 C CNN +F 1 "PORT" H 2100 4000 30 0000 C CNN +F 2 "" H 2100 4000 60 0000 C CNN +F 3 "" H 2100 4000 60 0000 C CNN + 6 2100 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 61DF01D7 +P 2100 3450 +F 0 "U1" H 2150 3550 30 0000 C CNN +F 1 "PORT" H 2100 3450 30 0000 C CNN +F 2 "" H 2100 3450 60 0000 C CNN +F 3 "" H 2100 3450 60 0000 C CNN + 5 2100 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 61DF026C +P 2050 2900 +F 0 "U1" H 2100 3000 30 0000 C CNN +F 1 "PORT" H 2050 2900 30 0000 C CNN +F 2 "" H 2050 2900 60 0000 C CNN +F 3 "" H 2050 2900 60 0000 C CNN + 4 2050 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 61DF0309 +P 2050 2350 +F 0 "U1" H 2100 2450 30 0000 C CNN +F 1 "PORT" H 2050 2350 30 0000 C CNN +F 2 "" H 2050 2350 60 0000 C CNN +F 3 "" H 2050 2350 60 0000 C CNN + 3 2050 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 61DF03AE +P 2100 1850 +F 0 "U1" H 2150 1950 30 0000 C CNN +F 1 "PORT" H 2100 1850 30 0000 C CNN +F 2 "" H 2100 1850 60 0000 C CNN +F 3 "" H 2100 1850 60 0000 C CNN + 2 2100 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 61DF041D +P 2050 1250 +F 0 "U1" H 2100 1350 30 0000 C CNN +F 1 "PORT" H 2050 1250 30 0000 C CNN +F 2 "" H 2050 1250 60 0000 C CNN +F 3 "" H 2050 1250 60 0000 C CNN + 1 2050 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 61DF0D04 +P 7650 5200 +F 0 "U1" H 7700 5300 30 0000 C CNN +F 1 "PORT" H 7650 5200 30 0000 C CNN +F 2 "" H 7650 5200 60 0000 C CNN +F 3 "" H 7650 5200 60 0000 C CNN + 11 7650 5200 + -1 0 0 -1 +$EndComp +$Comp +L summer U2 +U 1 1 61DEBE2F +P 6550 4000 +F 0 "U2" H 6550 3950 60 0000 C CNN +F 1 "summer" H 6550 4050 60 0000 C CNN +F 2 "" H 6550 4000 60 0000 C CNN +F 3 "" H 6550 4000 60 0000 C CNN + 1 6550 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 61DEBEC1 +P 6150 4150 +F 0 "#PWR2" H 6150 3900 50 0001 C CNN +F 1 "GND" H 6150 4000 50 0000 C CNN +F 2 "" H 6150 4150 50 0001 C CNN +F 3 "" H 6150 4150 50 0001 C CNN + 1 6150 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4850 4650 4850 +Wire Wire Line + 5100 2200 5100 5150 +Wire Wire Line + 5100 5150 4600 5150 +Wire Wire Line + 4600 2200 5100 2200 +Connection ~ 5100 4850 +Wire Wire Line + 4650 2500 5100 2500 +Connection ~ 5100 2500 +Wire Wire Line + 4650 2800 5100 2800 +Connection ~ 5100 2800 +Wire Wire Line + 4650 3150 5100 3150 +Connection ~ 5100 3150 +Wire Wire Line + 4650 3500 5100 3500 +Connection ~ 5100 3500 +Connection ~ 5100 3850 +Wire Wire Line + 4650 4200 5100 4200 +Connection ~ 5100 4200 +Wire Wire Line + 4650 4550 5100 4550 +Connection ~ 5100 4550 +Connection ~ 5750 3850 +Wire Wire Line + 7050 4000 7050 5200 +Wire Wire Line + 7050 5200 7400 5200 +Wire Wire Line + 4650 3850 6150 3850 +Wire Wire Line + 3700 2200 4300 2200 +Wire Wire Line + 3600 2500 4350 2500 +Wire Wire Line + 3500 2800 4350 2800 +Wire Wire Line + 3700 3150 4350 3150 +Wire Wire Line + 3250 3500 4350 3500 +Wire Wire Line + 3250 3850 4350 3850 +Wire Wire Line + 3200 4200 4350 4200 +Wire Wire Line + 3250 4600 4350 4600 +Wire Wire Line + 4350 4600 4350 4550 +Wire Wire Line + 3300 4850 4350 4850 +Wire Wire Line + 3700 5150 4300 5150 +Wire Wire Line + 2350 5800 2400 5800 +$Comp +L summer U3 +U 1 1 62005AB8 +P 2700 1400 +F 0 "U3" H 2700 1350 60 0000 C CNN +F 1 "summer" H 2700 1450 60 0000 C CNN +F 2 "" H 2700 1400 60 0000 C CNN +F 3 "" H 2700 1400 60 0000 C CNN + 1 2700 1400 + 1 0 0 -1 +$EndComp +$Comp +L summer U8 +U 1 1 62006578 +P 2750 2000 +F 0 "U8" H 2750 1950 60 0000 C CNN +F 1 "summer" H 2750 2050 60 0000 C CNN +F 2 "" H 2750 2000 60 0000 C CNN +F 3 "" H 2750 2000 60 0000 C CNN + 1 2750 2000 + 1 0 0 -1 +$EndComp +$Comp +L summer U4 +U 1 1 6200669E +P 2700 2500 +F 0 "U4" H 2700 2450 60 0000 C CNN +F 1 "summer" H 2700 2550 60 0000 C CNN +F 2 "" H 2700 2500 60 0000 C CNN +F 3 "" H 2700 2500 60 0000 C CNN + 1 2700 2500 + 1 0 0 -1 +$EndComp +$Comp +L summer U5 +U 1 1 620067C5 +P 2700 3050 +F 0 "U5" H 2700 3000 60 0000 C CNN +F 1 "summer" H 2700 3100 60 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L summer U9 +U 1 1 62006869 +P 2750 3600 +F 0 "U9" H 2750 3550 60 0000 C CNN +F 1 "summer" H 2750 3650 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 + 1 0 0 -1 +$EndComp +$Comp +L summer U10 +U 1 1 62006A63 +P 2750 4150 +F 0 "U10" H 2750 4100 60 0000 C CNN +F 1 "summer" H 2750 4200 60 0000 C CNN +F 2 "" H 2750 4150 60 0000 C CNN +F 3 "" H 2750 4150 60 0000 C CNN + 1 2750 4150 + 1 0 0 -1 +$EndComp +$Comp +L summer U6 +U 1 1 62006B47 +P 2700 4800 +F 0 "U6" H 2700 4750 60 0000 C CNN +F 1 "summer" H 2700 4850 60 0000 C CNN +F 2 "" H 2700 4800 60 0000 C CNN +F 3 "" H 2700 4800 60 0000 C CNN + 1 2700 4800 + 1 0 0 -1 +$EndComp +$Comp +L summer U7 +U 1 1 62006C2E +P 2700 5400 +F 0 "U7" H 2700 5350 60 0000 C CNN +F 1 "summer" H 2700 5450 60 0000 C CNN +F 2 "" H 2700 5400 60 0000 C CNN +F 3 "" H 2700 5400 60 0000 C CNN + 1 2700 5400 + 1 0 0 -1 +$EndComp +$Comp +L summer U12 +U 1 1 62006D0E +P 2800 5950 +F 0 "U12" H 2800 5900 60 0000 C CNN +F 1 "summer" H 2800 6000 60 0000 C CNN +F 2 "" H 2800 5950 60 0000 C CNN +F 3 "" H 2800 5950 60 0000 C CNN + 1 2800 5950 + 1 0 0 -1 +$EndComp +$Comp +L summer U11 +U 1 1 62006DC0 +P 2750 6500 +F 0 "U11" H 2750 6450 60 0000 C CNN +F 1 "summer" H 2750 6550 60 0000 C CNN +F 2 "" H 2750 6500 60 0000 C CNN +F 3 "" H 2750 6500 60 0000 C CNN + 1 2750 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3200 1400 3700 1400 +Wire Wire Line + 3700 1400 3700 2200 +Wire Wire Line + 3600 2500 3600 2000 +Wire Wire Line + 3600 2000 3250 2000 +Wire Wire Line + 3200 2500 3500 2500 +Wire Wire Line + 3500 2500 3500 2800 +Wire Wire Line + 3200 3050 3700 3050 +Wire Wire Line + 3700 3050 3700 3150 +Wire Wire Line + 3250 3500 3250 3600 +Wire Wire Line + 3250 3850 3250 4150 +Wire Wire Line + 3200 4200 3200 4800 +Wire Wire Line + 3250 4600 3250 5400 +Wire Wire Line + 3250 5400 3200 5400 +Wire Wire Line + 3300 4850 3300 5950 +Wire Wire Line + 3700 5150 3700 6500 +Wire Wire Line + 3700 6500 3250 6500 +$Comp +L GND #PWR1 +U 1 1 620071B7 +P 1400 6750 +F 0 "#PWR1" H 1400 6500 50 0001 C CNN +F 1 "GND" H 1400 6600 50 0000 C CNN +F 2 "" H 1400 6750 50 0001 C CNN +F 3 "" H 1400 6750 50 0001 C CNN + 1 1400 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2350 6650 1400 6650 +Wire Wire Line + 1400 6650 1400 6750 +Wire Wire Line + 2400 6100 1450 6100 +Wire Wire Line + 1450 4300 1450 6650 +Connection ~ 1450 6650 +Wire Wire Line + 2300 5550 1450 5550 +Connection ~ 1450 6100 +Wire Wire Line + 2300 4950 1450 4950 +Connection ~ 1450 5550 +Wire Wire Line + 2350 4300 1450 4300 +Connection ~ 1450 4950 +Wire Wire Line + 2350 3750 1450 3750 +Wire Wire Line + 1450 1550 1450 4350 +Connection ~ 1450 4350 +Wire Wire Line + 2300 3200 1450 3200 +Connection ~ 1450 3750 +Wire Wire Line + 2300 2650 1450 2650 +Connection ~ 1450 3200 +Wire Wire Line + 2350 2150 1450 2150 +Connection ~ 1450 2650 +Wire Wire Line + 2300 1550 1450 1550 +Connection ~ 1450 2150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub new file mode 100644 index 00000000..0a0445d9 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub @@ -0,0 +1,61 @@ +* Subcircuit 10bitDAC + +.subckt 10bitDAC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/10bitdac/10bitdac.cir +r1 net-_r1-pad1_ net-_r1-pad2_ 1024k +r2 net-_r2-pad1_ net-_r1-pad2_ 512k +r3 net-_r3-pad1_ net-_r1-pad2_ 256k +r4 net-_r4-pad1_ net-_r1-pad2_ 128k +r5 net-_r5-pad1_ net-_r1-pad2_ 64k +r6 net-_r6-pad1_ net-_r1-pad2_ 32k +r7 net-_r7-pad1_ net-_r1-pad2_ 16k +r9 net-_r9-pad1_ net-_r1-pad2_ 8k +r10 net-_r10-pad1_ net-_r1-pad2_ 4k +r11 net-_r11-pad1_ net-_r1-pad2_ 2k +* u2 net-_r1-pad2_ gnd net-_u1-pad11_ summer +* u3 net-_u1-pad1_ gnd net-_r1-pad1_ summer +* u8 net-_u1-pad2_ gnd net-_r2-pad1_ summer +* u4 net-_u1-pad3_ gnd net-_r3-pad1_ summer +* u5 net-_u1-pad4_ gnd net-_r4-pad1_ summer +* u9 net-_u1-pad5_ gnd net-_r5-pad1_ summer +* u10 net-_u1-pad6_ gnd net-_r6-pad1_ summer +* u6 net-_u1-pad7_ gnd net-_r7-pad1_ summer +* u7 net-_u1-pad8_ gnd net-_r9-pad1_ summer +* u12 net-_u1-pad9_ gnd net-_r10-pad1_ summer +* u11 net-_u1-pad10_ gnd net-_r11-pad1_ summer +a1 [net-_r1-pad2_ gnd ] net-_u1-pad11_ u2 +a2 [net-_u1-pad1_ gnd ] net-_r1-pad1_ u3 +a3 [net-_u1-pad2_ gnd ] net-_r2-pad1_ u8 +a4 [net-_u1-pad3_ gnd ] net-_r3-pad1_ u4 +a5 [net-_u1-pad4_ gnd ] net-_r4-pad1_ u5 +a6 [net-_u1-pad5_ gnd ] net-_r5-pad1_ u9 +a7 [net-_u1-pad6_ gnd ] net-_r6-pad1_ u10 +a8 [net-_u1-pad7_ gnd ] net-_r7-pad1_ u6 +a9 [net-_u1-pad8_ gnd ] net-_r9-pad1_ u7 +a10 [net-_u1-pad9_ gnd ] net-_r10-pad1_ u12 +a11 [net-_u1-pad10_ gnd ] net-_r11-pad1_ u11 +* Schematic Name: summer, NgSpice Name: summer +.model u2 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u3 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u8 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u4 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u5 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u9 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u10 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u6 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u7 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u12 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u11 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Control Statements + +.ends 10bitDAC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml b/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml new file mode 100644 index 00000000..25253eac --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1></source><model><u2 name="type">summer<field1 name="Enter offset for input (default=0.0) 1" /><field2 name="Enter offset for input (default=0.0) 2" /><field3 name="Enter gain for input(default=1.0) 1" /><field4 name="Enter gain for input(default=1.0) 2" /><field5 name="Enter gain for output (default=1.0)" /><field6 name="Enter offset for output (default=0.0)" /></u2><u12 name="type">summer<field1 name="Enter offset for input (default=0.0) 1" /><field2 name="Enter offset for input (default=0.0) 2" /><field3 name="Enter gain for input(default=1.0) 1" /><field4 name="Enter gain for input(default=1.0) 2" /><field5 name="Enter gain for output (default=1.0)" /><field6 name="Enter offset for output (default=0.0)" /></u12><u3 name="type">gain<field7 name="Enter offset for input (default=0.0)" /><field8 name="Enter gain (default=1.0) 1" /><field9 name="Enter offset for output (default=0.0)" /></u3><u4 name="type">gain<field10 name="Enter offset for input (default=0.0)" /><field11 name="Enter gain (default=1.0) 1" /><field12 name="Enter offset for output (default=0.0)" /></u4><u5 name="type">gain<field13 name="Enter offset for input (default=0.0)" /><field14 name="Enter gain (default=1.0) 1" /><field15 name="Enter offset for output (default=0.0)" /></u5><u6 name="type">gain<field16 name="Enter offset for input (default=0.0)" /><field17 name="Enter gain (default=1.0) 1" /><field18 name="Enter offset for output (default=0.0)" /></u6><u7 name="type">gain<field19 name="Enter offset for input (default=0.0)" /><field20 name="Enter gain (default=1.0) 1" /><field21 name="Enter offset for output (default=0.0)" /></u7><u8 name="type">gain<field22 name="Enter offset for input (default=0.0)" /><field23 name="Enter gain (default=1.0) 1" /><field24 name="Enter offset for output (default=0.0)" /></u8><u9 name="type">gain<field25 name="Enter offset for input (default=0.0)" /><field26 name="Enter gain (default=1.0) 1" /><field27 name="Enter offset for output (default=0.0)" /></u9><u10 name="type">gain<field28 name="Enter offset for input (default=0.0)" /><field29 name="Enter gain (default=1.0) 1" /><field30 name="Enter offset for output (default=0.0)" /></u10><u12 name="type">gain<field31 name="Enter offset for input (default=0.0)" /><field32 name="Enter gain (default=1.0) 1" /><field33 name="Enter offset for output (default=0.0)" /></u12><u11 name="type">gain<field34 name="Enter offset for input (default=0.0)" /><field35 name="Enter gain (default=1.0) 1" /><field36 name="Enter offset for output (default=0.0)" /></u11><u3 name="type">summer<field7 name="Enter offset for input (default=0.0) 1" /><field8 name="Enter offset for input (default=0.0) 2" /><field9 name="Enter gain for input(default=1.0) 1" /><field10 name="Enter gain for input(default=1.0) 2" /><field11 name="Enter gain for output (default=1.0)" /><field12 name="Enter offset for output (default=0.0)" /></u3><u8 name="type">summer<field13 name="Enter offset for input (default=0.0) 1" /><field14 name="Enter offset for input (default=0.0) 2" /><field15 name="Enter gain for input(default=1.0) 1" /><field16 name="Enter gain for input(default=1.0) 2" /><field17 name="Enter gain for output (default=1.0)" /><field18 name="Enter offset for output (default=0.0)" /></u8><u4 name="type">summer<field19 name="Enter offset for input (default=0.0) 1" /><field20 name="Enter offset for input (default=0.0) 2" /><field21 name="Enter gain for input(default=1.0) 1" /><field22 name="Enter gain for input(default=1.0) 2" /><field23 name="Enter gain for output (default=1.0)" /><field24 name="Enter offset for output (default=0.0)" /></u4><u5 name="type">summer<field25 name="Enter offset for input (default=0.0) 1" /><field26 name="Enter offset for input (default=0.0) 2" /><field27 name="Enter gain for input(default=1.0) 1" /><field28 name="Enter gain for input(default=1.0) 2" /><field29 name="Enter gain for output (default=1.0)" /><field30 name="Enter offset for output (default=0.0)" /></u5><u9 name="type">summer<field31 name="Enter offset for input (default=0.0) 1" /><field32 name="Enter offset for input (default=0.0) 2" /><field33 name="Enter gain for input(default=1.0) 1" /><field34 name="Enter gain for input(default=1.0) 2" /><field35 name="Enter gain for output (default=1.0)" /><field36 name="Enter offset for output (default=0.0)" /></u9><u10 name="type">summer<field37 name="Enter offset for input (default=0.0) 1" /><field38 name="Enter offset for input (default=0.0) 2" /><field39 name="Enter gain for input(default=1.0) 1" /><field40 name="Enter gain for input(default=1.0) 2" /><field41 name="Enter gain for output (default=1.0)" /><field42 name="Enter offset for output (default=0.0)" /></u10><u6 name="type">summer<field43 name="Enter offset for input (default=0.0) 1" /><field44 name="Enter offset for input (default=0.0) 2" /><field45 name="Enter gain for input(default=1.0) 1" /><field46 name="Enter gain for input(default=1.0) 2" /><field47 name="Enter gain for output (default=1.0)" /><field48 name="Enter offset for output (default=0.0)" /></u6><u7 name="type">summer<field49 name="Enter offset for input (default=0.0) 1" /><field50 name="Enter offset for input (default=0.0) 2" /><field51 name="Enter gain for input(default=1.0) 1" /><field52 name="Enter gain for input(default=1.0) 2" /><field53 name="Enter gain for output (default=1.0)" /><field54 name="Enter offset for output (default=0.0)" /></u7><u11 name="type">summer<field61 name="Enter offset for input (default=0.0) 1" /><field62 name="Enter offset for input (default=0.0) 2" /><field63 name="Enter gain for input(default=1.0) 1" /><field64 name="Enter gain for input(default=1.0) 2" /><field65 name="Enter gain for output (default=1.0)" /><field66 name="Enter offset for output (default=0.0)" /></u11></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/10bitDAC/analysis b/library/SubcircuitLibrary/10bitDAC/analysis new file mode 100644 index 00000000..14b93089 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/analysis @@ -0,0 +1 @@ +.tran 1e-03 10e-03 0e-00
\ No newline at end of file |