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Diffstat (limited to 'Windows/spice/examples')
148 files changed, 11648 insertions, 0 deletions
diff --git a/Windows/spice/examples/Monte_Carlo/MC_2_circ.sp b/Windows/spice/examples/Monte_Carlo/MC_2_circ.sp new file mode 100644 index 00000000..bacd07b9 --- /dev/null +++ b/Windows/spice/examples/Monte_Carlo/MC_2_circ.sp @@ -0,0 +1,109 @@ +Circuit to perform Monte Carlo simulation in ngspice +* 25 stage Ring-Osc. using inverters with BSIM3 + +vin in out dc 0.5 pulse 0.5 0 0.1n 5n 1 1 1 +vdd dd 0 dc 3.3 +vss ss 0 dc 0 +ve sub 0 dc 0 +vpe well 0 dc 3.3 + +.subckt inv1 dd ss sub well in out +mn1 out in ss sub n1 w=2u l=0.35u as=3p ad=3p ps=4u pd=4u +mp1 out in dd well p1 w=4u l=0.35u as=7p ad=7p ps=6u pd=6u +.ends inv1 + +.subckt inv5 dd ss sub well in out +xinv1 dd ss sub well in 1 inv1 +xinv2 dd ss sub well 1 2 inv1 +xinv3 dd ss sub well 2 3 inv1 +xinv4 dd ss sub well 3 4 inv1 +xinv5 dd ss sub well 4 out inv1 +.ends inv5 + +xinv1 dd ss sub well in out5 inv5 +xinv2 dd ss sub well out5 out10 inv5 +xinv3 dd ss sub well out10 out15 inv5 +xinv4 dd ss sub well out15 out20 inv5 +xinv5 dd ss sub well out20 out inv5 +xinv11 dd 0 sub well out buf inv1 +* output is buf +cout buf ss 0.2pF +* +.options noacct + +* The following model parameters are varying statistically: +* vth0, u0, tox +* see the AGAUSS function used to define the parameter +* the deviation is 10%, just for example, not measured + +******************************************************************************** +.model n1 nmos ++level=8 ++version=3.3.0 ++tnom=27.0 ++nch=2.498e+17 tox=AGAUSS(9e-09, 9e-09, 10) xj=1.00000e-07 ++lint=9.36e-8 wint=1.47e-7 ++vth0=AGAUSS(.6322,.6322,10) k1=.756 k2=-3.83e-2 k3=-2.612 ++dvt0=2.812 dvt1=0.462 dvt2=-9.17e-2 ++nlx=3.52291e-08 w0=1.163e-6 ++k3b=2.233 ++vsat=86301.58 ua=6.47e-9 ub=4.23e-18 uc=-4.706281e-11 ++rdsw=650 u0=AGAUSS(388.3203,388.3203,10) wr=1 ++a0=.3496967 ags=.1 b0=0.546 b1=1 ++dwg=-6.0e-09 dwb=-3.56e-09 prwb=-.213 ++keta=-3.605872e-02 a1=2.778747e-02 a2=.9 ++voff=-6.735529e-02 nfactor=1.139926 cit=1.622527e-04 ++cdsc=-2.147181e-05 ++cdscb=0 dvt0w=0 dvt1w=0 dvt2w=0 ++cdscd=0 prwg=0 ++eta0=1.0281729e-02 etab=-5.042203e-03 ++dsub=.31871233 ++pclm=1.114846 pdiblc1=2.45357e-03 pdiblc2=6.406289e-03 ++drout=.31871233 pscbe1=5000000 pscbe2=5e-09 pdiblcb=-.234 ++pvag=0 delta=0.01 ++wl=0 ww=-1.420242e-09 wwl=0 ++wln=0 wwn=.2613948 ll=1.300902e-10 ++lw=0 lwl=0 lln=.316394 lwn=0 ++kt1=-.3 kt2=-.051 ++at=22400 ++ute=-1.48 ++ua1=3.31e-10 ub1=2.61e-19 uc1=-3.42e-10 ++kt1l=0 prt=764.3 ++noimod=2 ++af=1.075e+00 kf=9.670e-28 ef=1.056e+00 ++noia=1.130e+20 noib=7.530e+04 noic=-8.950e-13 +**** PMOS *** +.model p1 pmos ++level=8 ++version=3.3.0 ++tnom=27.0 ++nch=3.533024e+17 tox=AGAUSS(9e-09,9e-09,10) xj=1.00000e-07 ++lint=6.23e-8 wint=1.22e-7 ++vth0=AGAUSS(-.6732829,-.6732829,10) k1=.8362093 k2=-8.606622e-02 k3=1.82 ++dvt0=1.903801 dvt1=.5333922 dvt2=-.1862677 ++nlx=1.28e-8 w0=2.1e-6 ++k3b=-0.24 prwg=-0.001 prwb=-0.323 ++vsat=103503.2 ua=1.39995e-09 ub=1.e-19 uc=-2.73e-11 ++rdsw=460 u0=AGAUSS(138.7609,138.7609,10) ++a0=.4716551 ags=0.12 ++keta=-1.871516e-03 a1=.3417965 a2=0.83 ++voff=-.074182 nfactor=1.54389 cit=-1.015667e-03 ++cdsc=8.937517e-04 ++cdscb=1.45e-4 cdscd=1.04e-4 ++dvt0w=0.232 dvt1w=4.5e6 dvt2w=-0.0023 ++eta0=6.024776e-02 etab=-4.64593e-03 ++dsub=.23222404 ++pclm=.989 pdiblc1=2.07418e-02 pdiblc2=1.33813e-3 ++drout=.3222404 pscbe1=118000 pscbe2=1e-09 ++pvag=0 ++kt1=-0.25 kt2=-0.032 prt=64.5 ++at=33000 ++ute=-1.5 ++ua1=4.312e-9 ub1=6.65e-19 uc1=0 ++kt1l=0 ++noimod=2 ++af=9.970e-01 kf=2.080e-29 ef=1.015e+00 ++noia=1.480e+18 noib=3.320e+03 noic=1.770e-13 +.end + +.end diff --git a/Windows/spice/examples/Monte_Carlo/MC_2_control.sp b/Windows/spice/examples/Monte_Carlo/MC_2_control.sp new file mode 100644 index 00000000..9b9f3606 --- /dev/null +++ b/Windows/spice/examples/Monte_Carlo/MC_2_control.sp @@ -0,0 +1,43 @@ +* Perform Monte Carlo simulation in ngspice +* script for use with 25 stage Ring-Osc. BSIM3 +* circuit is in MC_2_circ.sp +* edit 'set sourcepath' for your path to circuit file +* start script by 'ngspice -o MC_2_control.log MC_2_control.sp' +* +.control + save buf $ we just need output vector buf, save memory by more than 10x + let mc_runs = 100 $ number of runs for monte carlo + let run = 1 $ number of the actual run + +* Where to find the circuit netlist file MC_2_circ.sp + set sourcepath = ( D:\Spice_general\ngspice\examples\Monte_Carlo ) + +* create file for frequency information + echo Monte Carlo, frequency of R.O. > MC_frequ.log + +* run the simulation loop + dowhile run <= mc_runs + * without the reset switch there is some strange drift + * towards lower and lower frequencies + reset + set run ="$&run" $ create a variable from the vector + set rndseed = $run $ set the rnd seed value to the loop index + source MC_2_circ.sp $ load the circuit, including model data + tran 15p 200n 0 + write mc_ring{$run}.out buf $ write each sim output to its own rawfile + linearize buf $ lienarize buf to allow fft + fft buf $ run fft on vector buf + let buf2=db(mag(buf)) + * find the frequency where buf has its maximum of the fft signal + meas sp fft_max MAX_AT buf2 from=0.1G to=0.7G + print fft_max >> MC_frequ.log $ print frequency to file + destroy all $ delete all output vectors + remcirc $ delete circuit + let run = run + 1 $ increase loop counter + end + + quit + +.endc + +.end diff --git a/Windows/spice/examples/Monte_Carlo/MC_ring.sp b/Windows/spice/examples/Monte_Carlo/MC_ring.sp new file mode 100644 index 00000000..58e5c141 --- /dev/null +++ b/Windows/spice/examples/Monte_Carlo/MC_ring.sp @@ -0,0 +1,251 @@ +Perform Monte Carlo simulation in ngspice +* 25 stage Ring-Osc. BSIM3 + +vin in out dc 0.5 pulse 0.5 0 0.1n 5n 1 1 1 +vdd dd 0 dc 3.3 +vss ss 0 dc 0 +ve sub 0 dc 0 +vpe well 0 dc 3.3 + +.subckt inv1 dd ss sub well in out +mn1 out in ss sub n1 w=2u l=0.35u as=3p ad=3p ps=4u pd=4u +mp1 out in dd well p1 w=4u l=0.35u as=7p ad=7p ps=6u pd=6u +.ends inv1 + +.subckt inv5 dd ss sub well in out +xinv1 dd ss sub well in 1 inv1 +xinv2 dd ss sub well 1 2 inv1 +xinv3 dd ss sub well 2 3 inv1 +xinv4 dd ss sub well 3 4 inv1 +xinv5 dd ss sub well 4 out inv1 +.ends inv5 + +xinv1 dd ss sub well in out5 inv5 +xinv2 dd ss sub well out5 out10 inv5 +xinv3 dd ss sub well out10 out15 inv5 +xinv4 dd ss sub well out15 out20 inv5 +xinv5 dd ss sub well out20 out inv5 +xinv11 dd 0 sub well out buf inv1 +cout buf ss 0.2pF +* +.options noacct +.control + save buf $ we just need buf, save memory by more than 10x + let mc_runs = 10 $ number of runs for monte carlo + let run = 0 $ number of actual run + set curplot = new $ create a new plot + set curplottitle = "Transient outputs" + set plot_out = $curplot $ store its name to 'plot_out' + set curplot = new $ create a new plot + set curplottitle = "FFT outputs" + set plot_fft = $curplot $ store its name to 'plot_fft' + set curplot = new $ create a new plot + set curplottitle = "Oscillation frequency" + set max_fft = $curplot $ store its name to 'max_fft' + let mc_runsp = mc_runs + 1 + let maxffts = unitvec(mc_runsp) $ vector for storing max measure results + let halfffts = unitvec(mc_runsp)$ vector for storing measure results at -40dB rising +* +* define distributions for random numbers: +* unif: uniform distribution, deviation relativ to nominal value +* aunif: uniform distribution, deviation absolut +* gauss: Gaussian distribution, deviation relativ to nominal value +* agauss: Gaussian distribution, deviation absolut + define unif(nom, var) (nom + (nom*var) * sunif(0)) + define aunif(nom, avar) (nom + avar * sunif(0)) + define gauss(nom, var, sig) (nom + (nom*var)/sig * sgauss(0)) + define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) +* +* We want to vary the model parameters vth0, u0, tox, lint, and wint +* of the BSIM3 model for the NMOS and PMOS transistors. +* We may obtain the nominal values (nom) by manually extracting them from +* the parameter set. Here we get them automatically and store them into +* variables. This has the advantage that you may change the parameter set +* without having to look up the values again. + set n1vth0=@n1[vth0] + set n1u0=@n1[u0] + set n1tox=@n1[tox] + set n1lint=@n1[lint] + set n1wint=@n1[wint] + set p1vth0=@p1[vth0] + set p1u0=@p1[u0] + set p1tox=@p1[tox] + set p1lint=@p1[lint] + set p1wint=@p1[wint] +* +* run the simulation loop + dowhile run <= mc_runs + * without the reset switch there is some strange drift + * towards lower and lower frequencies + reset + * run=0 simulates with nominal parameters + if run > 0 + altermod @n1[vth0]=gauss($n1vth0, 0.1, 3) + altermod @n1[u0]=gauss($n1u0, 0.05, 3) + altermod @n1[tox]=gauss($n1tox, 0.1, 3) + altermod @n1[lint]=gauss($n1lint, 0.1, 3) + altermod @n1[wint]=gauss($n1wint, 0.1, 3) + altermod @p1[vth0]=gauss($p1vth0, 0.1, 3) + altermod @p1[u0]=gauss($p1u0, 0.1, 3) + altermod @p1[tox]=gauss($p1tox, 0.1, 3) + altermod @p1[lint]=gauss($p1lint, 0.1, 3) + altermod @p1[wint]=gauss($p1wint, 0.1, 3) + end + tran 15p 50n 0 +* select stop and step so that number of data points after linearization is not too +* close to 8192, which would yield varying number of line length and thus scale for fft. +* +* We have to figure out what to do if a single simulation will not converge. +* Is there a variable which may be set if there is no convergence? +* Then we might skip this run and continue with a new run. It does not exist for now. +* So we have to rely on the robustness of the following steps not leading +* to a seg fault if the tran data are missing. +* + set run ="$&run" $ create a variable from the vector + set mc_runs ="$&mc_runs" $ create a variable from the vector + echo simulation run no. $run of $mc_runs + * save the linearized data for having equal time scales for all runs + linearize buf $ linearize only buf, no other vectors needed + set dt = $curplot $ store the current plot to dt (tran i+1) + setplot $plot_out $ make 'plt_out' the active plot + * firstly save the time scale once to become the default scale + if run=0 + let time={$dt}.time + end + let vout{$run}={$dt}.buf $ store the output vector to plot 'plot_out' + setplot $dt $ go back to the previous plot (tran i+1) + fft buf $ run fft on vector buf + let buf2=db(mag(buf)) + * find the frequency where buf has its maximum of the fft signal + meas sp fft_max MAX_AT buf2 from=0.1G to=0.7G + * find the frequency where buf is -40dB at rising fft signal + meas sp fft_40 WHEN buf2=-40 RISE=1 from=0.1G to=0.7G + * store the fft vector + set dt = $curplot $ store the current plot to dt (spec i) + setplot $plot_fft $ make 'plot_fft' the active plot + if run=0 + let frequency={$dt}.frequency + end + let fft{$run}={$dt}.buf $ store the output vector to plot 'plot_fft' + * store the measured value + setplot $max_fft $ make 'max_fft' the active plot + let maxffts[{$run}]={$dt}.fft_max + let halfffts[{$run}]={$dt}.fft_40 +* setplot $plot_out +* The following command does not work here. Why not? Probably not a real copy. +* destroy $dt $ save memory, we don't need this plot (spec) any more + setplot $dt $ go back to the previous plot + let run = run + 1 + end +***** plotting ********************************************************** +* plot {$plot_out}.allv + plot {$plot_out}.vout0 $ just plot the tran output with nominal parameters +* setplot $plot_fft +* plot db(mag(ally)) xlimit .1G 1G ylimit -80 10 + plot db(mag({$plot_fft}.ally)) xlimit .1G 1G ylimit -80 10 +* +* create a histogram from vector maxffts + setplot $max_fft $ make 'max_fft' the active plot + set startfreq=400MEG + set bin_size=5MEG + set bin_count=20 + compose xvec start=$startfreq step=$bin_size lin=$bin_count $ requires variables as parameters + settype frequency xvec + let bin_count=$bin_count $ create a vector from the variable + let yvec=unitvec(bin_count) $ requires vector as parameter + let startfreq=$startfreq + let bin_size=$bin_size + * put data into the correct bins + let run = 0 + dowhile run < mc_runs + set run = "$&run" $ create a variable from the vector + let val = maxffts[{$run}] + let part = 0 + * Check if val fits into a bin. If yes, raise bin by 1 + dowhile part < bin_count + if ((val < (startfreq + (part+1)*bin_size)) & (val > (startfreq + part*bin_size))) + let yvec[part] = yvec[part] + 1 + break + end + let part = part + 1 + end + let run = run + 1 + end + * plot the histogram + set plotstyle=combplot + plot yvec-1 vs xvec $ subtract 1 because with started with unitvec containing ones +* calculate jitter + let diff40 = (vecmax(halfffts) - vecmin(halfffts))*1e-6 + echo + echo Max. jitter is "$&diff40" MHz + rusage +.endc +******************************************************************************** +.model n1 nmos ++level=8 ++version=3.3.0 ++tnom=27.0 ++nch=2.498e+17 tox=9e-09 xj=1.00000e-07 ++lint=9.36e-8 wint=1.47e-7 ++vth0=.6322 k1=.756 k2=-3.83e-2 k3=-2.612 ++dvt0=2.812 dvt1=0.462 dvt2=-9.17e-2 ++nlx=3.52291e-08 w0=1.163e-6 ++k3b=2.233 ++vsat=86301.58 ua=6.47e-9 ub=4.23e-18 uc=-4.706281e-11 ++rdsw=650 u0=388.3203 wr=1 ++a0=.3496967 ags=.1 b0=0.546 b1=1 ++dwg=-6.0e-09 dwb=-3.56e-09 prwb=-.213 ++keta=-3.605872e-02 a1=2.778747e-02 a2=.9 ++voff=-6.735529e-02 nfactor=1.139926 cit=1.622527e-04 ++cdsc=-2.147181e-05 ++cdscb=0 dvt0w=0 dvt1w=0 dvt2w=0 ++cdscd=0 prwg=0 ++eta0=1.0281729e-02 etab=-5.042203e-03 ++dsub=.31871233 ++pclm=1.114846 pdiblc1=2.45357e-03 pdiblc2=6.406289e-03 ++drout=.31871233 pscbe1=5000000 pscbe2=5e-09 pdiblcb=-.234 ++pvag=0 delta=0.01 ++wl=0 ww=-1.420242e-09 wwl=0 ++wln=0 wwn=.2613948 ll=1.300902e-10 ++lw=0 lwl=0 lln=.316394 lwn=0 ++kt1=-.3 kt2=-.051 ++at=22400 ++ute=-1.48 ++ua1=3.31e-10 ub1=2.61e-19 uc1=-3.42e-10 ++kt1l=0 prt=764.3 ++noimod=2 ++af=1.075e+00 kf=9.670e-28 ef=1.056e+00 ++noia=1.130e+20 noib=7.530e+04 noic=-8.950e-13 +**** PMOS *** +.model p1 pmos ++level=8 ++version=3.3.0 ++tnom=27.0 ++nch=3.533024e+17 tox=9e-09 xj=1.00000e-07 ++lint=6.23e-8 wint=1.22e-7 ++vth0=-.6732829 k1=.8362093 k2=-8.606622e-02 k3=1.82 ++dvt0=1.903801 dvt1=.5333922 dvt2=-.1862677 ++nlx=1.28e-8 w0=2.1e-6 ++k3b=-0.24 prwg=-0.001 prwb=-0.323 ++vsat=103503.2 ua=1.39995e-09 ub=1.e-19 uc=-2.73e-11 ++rdsw=460 u0=138.7609 ++a0=.4716551 ags=0.12 ++keta=-1.871516e-03 a1=.3417965 a2=0.83 ++voff=-.074182 nfactor=1.54389 cit=-1.015667e-03 ++cdsc=8.937517e-04 ++cdscb=1.45e-4 cdscd=1.04e-4 ++dvt0w=0.232 dvt1w=4.5e6 dvt2w=-0.0023 ++eta0=6.024776e-02 etab=-4.64593e-03 ++dsub=.23222404 ++pclm=.989 pdiblc1=2.07418e-02 pdiblc2=1.33813e-3 ++drout=.3222404 pscbe1=118000 pscbe2=1e-09 ++pvag=0 ++kt1=-0.25 kt2=-0.032 prt=64.5 ++at=33000 ++ute=-1.5 ++ua1=4.312e-9 ub1=6.65e-19 uc1=0 ++kt1l=0 ++noimod=2 ++af=9.970e-01 kf=2.080e-29 ef=1.015e+00 ++noia=1.480e+18 noib=3.320e+03 noic=1.770e-13 +.end diff --git a/Windows/spice/examples/Monte_Carlo/MonteCarlo.sp b/Windows/spice/examples/Monte_Carlo/MonteCarlo.sp new file mode 100644 index 00000000..608dc4cf --- /dev/null +++ b/Windows/spice/examples/Monte_Carlo/MonteCarlo.sp @@ -0,0 +1,68 @@ +* Effecting a Monte Carlo calculation in ngspice +V1 N001 0 AC 1 DC 0 +R1 N002 N001 141 +* +C1 OUT 0 1e-09 +L1 OUT 0 10e-06 +C2 N002 0 1e-09 +L2 N002 0 10e-06 +L3 N003 N002 40e-06 +C3 OUT N003 250e-12 +* +R2 0 OUT 141 +.control + let mc_runs = 5 + let run = 0 + set curplot=new $ create a new plot + set scratch=$curplot $ store its name to 'scratch' + setplot $scratch $ make 'scratch' the active plot + let bwh=unitvec(mc_runs) $ create a vector in plot 'scratch' to store bandwidth data + +* define distributions for random numbers: +* unif: uniform distribution, deviation relativ to nominal value +* aunif: uniform distribution, deviation absolut +* gauss: Gaussian distribution, deviation relativ to nominal value +* agauss: Gaussian distribution, deviation absolut +* limit: if unif. distributed value >=0 then add +avar to nom, else -avar + define unif(nom, rvar) (nom + (nom*rvar) * sunif(0)) + define aunif(nom, avar) (nom + avar * sunif(0)) + define gauss(nom, rvar, sig) (nom + (nom*rvar)/sig * sgauss(0)) + define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) +* define limit(nom, avar) (nom + ((sgauss(0) ge 0) ? avar : -avar)) + define limit(nom, avar) (nom + ((sgauss(0) >= 0) ? avar : -avar)) +* +* + dowhile run < mc_runs $ loop starts here +* +* alter c1 = unif(1e-09, 0.1) +* alter c1 = aunif(1e-09, 100e-12) +* alter c1 = gauss(1e-09, 0.1, 3) +* alter c1 = agauss(1e-09, 100e-12, 3) +* + alter c1 = unif(1e-09, 0.1) + alter l1 = unif(10e-06, 0.1) + alter c2 = unif(1e-09, 0.1) + alter l2 = unif(10e-06, 0.1) + alter l3 = unif(40e-06, 0.1) + alter c3 = limit(250e-12, 25e-12) +* + ac oct 100 250K 10Meg +* +* measure bandwidth at -10 dB + meas ac bw trig vdb(out) val=-10 rise=1 targ vdb(out) val=-10 fall=1 +* + set run ="$&run" $ create a variable from the vector + set dt = $curplot $ store the current plot to dt + setplot $scratch $ make 'scratch' the active plot + let vout{$run}={$dt}.v(out) $ store the output vector to plot 'scratch' + let bwh[run]={$dt}.bw $ store bw to vector bwh in plot 'scratch' + setplot $dt $ go back to the previous plot + let run = run + 1 + end $ loop ends here +* + plot db({$scratch}.allv) + echo + print {$scratch}.bwh +.endc + +.end diff --git a/Windows/spice/examples/Monte_Carlo/OpWien.sp b/Windows/spice/examples/Monte_Carlo/OpWien.sp new file mode 100644 index 00000000..91b45d08 --- /dev/null +++ b/Windows/spice/examples/Monte_Carlo/OpWien.sp @@ -0,0 +1,87 @@ +OPWIEN.CIR - OPAMP WIEN-BRIDGE OSCILLATOR +* http://www.ecircuitcenter.com/circuits/opwien/opwien.htm +* single simulation run +* 2 resistors and 2 capacitors of Wien bridge a varied statistically +* number of variations: varia + +* Simulation time +.param ttime=12000m +.param varia=100 +.param ttime10 = 'ttime/varia' + +* nominal resistor and capacitor values +.param res = 10k +.param cn = 16NF + +* CURRENT PULSE TO START OSCILLATIONS +IS 0 3 dc 0 PWL(0US 0MA 10US 0.1MA 40US 0.1MA 50US 0MA 10MS 0MA) +* +* RC TUNING +VR2 r2 0 dc 0 trrandom (2 'ttime10' 0 1) $ Gauss controlling voltage +* +*VR2 r2 0 dc 0 trrandom (1 'ttime10' 0 3) $ Uniform within -3 3 +* +* If Gauss, factor 0.033 is 10% equivalent to 3 sigma +* if uniform, uniform between +/- 10% +R2 4 6 R = 'res + 0.033 * res*V(r2)' $ behavioral resistor +*R2 4 6 'res' $ constant R + +VC2 c2 0 dc 0 trrandom (2 'ttime10' 0 1) +*C2 6 3'cn' $ constant C +C2 6 3 C = 'cn + 0.033 * cn*V(c2)' $ behavioral capacitor + +VR1 r1 0 dc 0 trrandom (2 'ttime10' 0 1) +*VR1 r1 0 dc 0 trrandom (1 'ttime10' 0 3) +R1 3 0 R = 'res + 0.033 * res*V(r1)' +*R1 3 0 'res' + +VC1 c1 0 dc 0 trrandom (2 'ttime10' 0 1) +C1 3 0 C = 'cn + 0.033 * cn*V(c2)' +*C1 3 0 'cn' + +* NON-INVERTING OPAMP +R10 0 2 10K +R11 2 5 18K +XOP 3 2 4 OPAMP1 +* AMPLITUDE STABILIZATION +R12 5 4 5K +D1 5 4 D1N914 +D2 4 5 D1N914 +* +.model D1N914 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100 Ibv=0.4n) +* +* OPAMP MACRO MODEL, SINGLE-POLE +* connections: non-inverting input +* | inverting input +* | | output +* | | | +.SUBCKT OPAMP1 1 2 6 +* INPUT IMPEDANCE +RIN 1 2 10MEG +* DC GAIN (100K) AND POLE 1 (100HZ) +EGAIN 3 0 1 2 100K +RP1 3 4 1K +CP1 4 0 1.5915UF +* OUTPUT BUFFER AND RESISTANCE +EBUFFER 5 0 4 0 1 +ROUT 5 6 10 +.ENDS +* +* ANALYSIS +.TRAN 0.05MS 'ttime' +* +* VIEW RESULTS +.control +option noinit +run +plot V(4) 5*V(r1) 5*V(r2) 5*V(c1) 5*V(c2) +linearize v(4) +fft v(4) +let v4mag = mag(v(4)) +plot v4mag +plot v4mag xlimit 500 1500 +*wrdata histo v4mag +rusage +.endc + +.END diff --git a/Windows/spice/examples/TransImpedanceAmp/README b/Windows/spice/examples/TransImpedanceAmp/README new file mode 100644 index 00000000..ea5c249d --- /dev/null +++ b/Windows/spice/examples/TransImpedanceAmp/README @@ -0,0 +1,41 @@ +This directory holds a SPICE netlist with SPICE2 POLY constructs in +controlled sources as typically found in vendor models. The circuit +is just a two-stage transimpedance amp using an AD8009, +along with some slow components (AD780 and OP177A) to set bias +points. Vendor models are used for all active components. +Successfully running this test shows that you have successfully built +the XSpice stuff with the POLY codemodel, and that you should be able +to simulate SPICE netlists with embedded vendor models. + +To run this netlist, just do the following: + +[localhost]# ngspice +ngspice 1 -> source output.net +ngspice 2 -> run +ngspice 3 -> plot Vout2 + +(Note that when you read in the netlist, you will get a bunch of +warnings saying stuff like: + +Warning -- Level not specified on line "()" +Using level 1. + +Also, ngspice will complain about: + +Error on line 50 : r:u101:1 u101:40 0 1e3 tc=7e-6 + unknown parameter (tc) +Error on line 283 : .temp 0 25 50 75 100 + Warning: .TEMP card obsolete - use .options TEMP and TNOM + +You can ignore all this stuff . . . .) + +You should get a pop-up window showing two square pulses (the second +smaller than the first) with a little bit of overshoot on the rising +and falling edges. + +This stuff was done as an adjunct to work on the gEDA project. +Information about gEDA is available at http://geda.seul.org/ . +Please direct all questions/suggestions/bugs/complaints about XSpice +extensions to ngspice to Stuart Brorson -- mailto:sdb@cloud9.net. + +6.23.2002 -- SDB. diff --git a/Windows/spice/examples/TransImpedanceAmp/output.net b/Windows/spice/examples/TransImpedanceAmp/output.net new file mode 100644 index 00000000..d6eb355f --- /dev/null +++ b/Windows/spice/examples/TransImpedanceAmp/output.net @@ -0,0 +1,454 @@ +********************************************************* +* Spice file generated by gnetlist * +* spice-SDB version 3.30.2003 by SDB -- * +* provides advanced spice netlisting capability. * +* Documentation at http://www.brorson.com/gEDA/SPICE/ * +********************************************************* +* Command stuff +.options gmin=1e-9 +.options method=gear +.options abstol=1e-11 +* .ac dec 10 10MegHz 10 Ghz +* Remainder of file +R112 0 6 1Meg +R111 0 8 10Meg +R110 0 7 1Meg +Rref2in 11 VU780out 25000 +Rref2fb VU2bias+ 11 33 +C201 0 9 1uF +C202 10 0 1uF +XU200 0 11 10 9 VU2bias+ OP177A +R202 10 +5V 22 +R201 -5V 9 22 +Rref1in VU100in- VU780out 9130 +Rref1fb VU1bias+ VU100in- 33 +XU101 +5V 7 0 6 VU780out 8 AD780A +* AD780A SPICE Macromodel 5/93, Rev. A +* AAG / PMI +* +* This version of the AD780 voltage reference model simulates the worst case +* parameters of the 'A' grade. The worst case parameters used +* correspond to those in the data sheet. +* +* Copyright 1993 by Analog Devices, Inc. +* +* Refer to "README.DOC" file for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* NODE NUMBERS +* VIN +* | TEMP +* | | GND +* | | | TRIM +* | | | | VOUT +* | | | | | RANGE +* | | | | | | +.SUBCKT AD780A 2 3 4 5 6 8 +* +* BANDGAP REFERENCE +* +I1 4 40 DC 1.21174E-3 +R1 40 4 1E3 TC=7E-6 +EN 10 40 42 0 1 +G1 4 10 2 4 4.85668E-9 +F1 4 10 POLY(2) VS1 VS2 (0,2.42834E-5,3.8E-5) +Q1 2 10 11 QT +I2 11 4 DC 12.84E-6 +R2 11 3 1E3 +I3 3 4 DC 0 +* +* NOISE VOLTAGE GENERATOR +* +VN1 41 0 DC 2 +DN1 41 42 DEN +DN2 42 43 DEN +VN2 0 43 DC 2 +* +* INTERNAL OP AMP +* +G2 4 12 10 20 1.93522E-4 +R3 12 4 2.5837E9 +C1 12 4 6.8444E-11 +D1 12 13 DX +V1 2 13 DC 1.2 +* +* SECONDARY POLE @ 508 kHz +* +G3 4 14 12 4 1E-6 +R4 14 4 1E6 +C2 14 4 3.1831E-13 +* +* OUTPUT STAGE +* +ISY 2 4 6.8282E-4 +FSY 2 4 V1 -1 +RSY 2 4 500E3 +* +G4 4 15 14 4 25E-6 +R5 15 4 40E3 +Q2 4 15 16 QP +I4 2 16 DC 100E-6 +Q3 4 16 18 QP +R6 18 23 15 +R7 16 21 150E3 +R8 2 17 34.6 +Q4 17 16 19 QN +R9 21 20 6.46E3 +R10 20 4 6.1E3 +R11 20 5 53E3 +R12 20 8 15.6E3 +I5 5 4 DC 0 +I6 8 4 DC 0 +VS1 21 19 DC 0 +VS2 23 21 DC 0 +L1 21 6 1E-7 +* +* OUTPUT CURRENT LIMIT +* +FSC 15 4 VSC 1 +VSC 2 22 DC 0 +QSC 22 2 17 QN +* +.MODEL QT NPN(level=1 IS=1.68E-16 BF=1E4) +.MODEL QN NPN(level=1 IS=1E-15 BF=1E3) +.MODEL QP PNP(level=1 IS=1E-15 BF=1E3) +.MODEL DX D(IS=1E-15) +.MODEL DEN D(IS=1E-12 RS=2.425E+05 AF=1 KF=6.969E-16) +.ENDS AD780A +C101 0 U100V- 1uF +C102 U100V+ 0 1uF +XU100 0 VU100in- U100V+ U100V- VU1bias+ OP177A +* OP177A SPICE Macro-model 12/90, Rev. B +* JCB / PMI +* +* Revision History: +* REV. B +* Re-ordered subcircuit call out nodes to put the +* output node last. +* Changed Ios from 1E-9 to 0.5E-9 +* Added F1 and F2 to fix short circuit current limit. +* +* +* This version of the OP-177 model simulates the worst case +* parameters of the 'A' grade. The worst case parameters +* used correspond to those in the data book. +* +* +* Copyright 1990 by Analog Devices, Inc. +* +* Refer to "README.DOC" file for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT OP177A 1 2 99 50 39 +* +* INPUT STAGE & POLE AT 6 MHZ +* +R1 2 3 5E11 +R2 1 3 5E11 +R3 5 97 0.0606 +R4 6 97 0.0606 +CIN 1 2 4E-12 +C2 5 6 218.9E-9 +I1 4 51 1 +IOS 1 2 0.5E-9 +EOS 9 10 POLY(1) 30 33 10E-6 1 +Q1 5 2 7 QX +Q2 6 9 8 QX +R5 7 4 0.009 +R6 8 4 0.009 +D1 2 1 DX +D2 1 2 DX +EN 10 1 12 0 1 +GN1 0 2 15 0 1 +GN2 0 1 18 0 1 +* +EREF 98 0 33 0 1 +EPLUS 97 0 99 0 1 +ENEG 51 0 50 0 1 +* +* VOLTAGE NOISE SOURCE WITH FLICKER NOISE +* +DN1 11 12 DEN +DN2 12 13 DEN +VN1 11 0 DC 2 +VN2 0 13 DC 2 +* +* CURRENT NOISE SOURCE WITH FLICKER NOISE +* +DN3 14 15 DIN +DN4 15 16 DIN +VN3 14 0 DC 2 +VN4 0 16 DC 2 +* +* SECOND CURRENT NOISE SOURCE +* +DN5 17 18 DIN +DN6 18 19 DIN +VN5 17 0 DC 2 +VN6 0 19 DC 2 +* +* FIRST GAIN STAGE +* +R7 20 98 1 +G1 98 20 5 6 119.8 +D3 20 21 DX +D4 22 20 DX +E1 97 21 POLY(1) 97 33 -2.4 1 +E2 22 51 POLY(1) 33 51 -2.4 1 +* +* GAIN STAGE & DOMINANT POLE AT 0.127 HZ +* +R8 23 98 1.253E9 +C3 23 98 1E-9 +G2 98 23 20 33 33.3E-6 +V1 97 24 1.8 +V2 25 51 1.8 +D5 23 24 DX +D6 25 23 DX +* +* NEGATIVE ZERO AT -4MHZ +* +R9 26 27 1 +C4 26 27 -39.75E-9 +R10 27 98 1E-6 +E3 26 98 23 33 1E6 +* +* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ +* +R13 30 31 1 +L2 31 98 2.52E-3 +G4 98 30 3 33 0.316E-6 +D7 30 97 DX +D8 51 30 DX +* +* POLE AT 2 MHZ +* +R14 32 98 1 +C5 32 98 79.5E-9 +G5 98 32 27 33 1 +* +* OUTPUT STAGE +* +R15 33 97 1 +R16 33 51 1 +GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 +F1 34 0 V3 1 +F2 0 34 V4 1 +R17 34 99 400 +R18 34 50 400 +L3 34 39 2E-7 +G6 37 50 32 34 2.5E-3 +G7 38 50 34 32 2.5E-3 +G8 34 99 99 32 2.5E-3 +G9 50 34 32 50 2.5E-3 +V3 35 34 6.8 +V4 34 36 4.4 +D9 32 35 DX +D10 36 32 DX +D11 99 37 DX +D12 99 38 DX +D13 50 37 DY +D14 50 38 DY +* +* MODELS USED +* +.MODEL QX NPN(level=1 BF=333.3E6) +.MODEL DX D(IS=1E-15) +.MODEL DY D(IS=1E-15 BV=50) +.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) +.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) +.ENDS +R102 U100V+ +5V 22 +R101 -5V U100V- 22 +R98 0 VU2bias+ 1K +R99 0 VU1bias+ 1K +C95 VU2bias+ 0 100pF +* C96 0 5 1uF +* C97 4 0 1uF +Cphotodiode 0 Vinput 0.9pF +C99 0 VU1bias+ 100pF +R25 Vout2 2 250 +C24 Vout1 VU1in- 1pF +R24 VU1in- 1 150 +* C21 0 3 1uF +Cc Vout2 VU2in- 1pF +Rc Vout1 VU2in- 10 +RL 0 Vout2 50 +.TEMP 0 25 50 75 100 +C12 2 0 1.5pF +C11 0 V2- .01uF +C10 V2+ 0 .01uF +R13 +5V V2+ 5 +R12 V2- -5V 5 +R26 2 VU2in- 150 +R11 Vout2 VU2in- 180 +XU2 VU2bias+ VU2in- V2+ V2- Vout2 AD8009an +XU1 VU1bias+ VU1in- V1+ V1- Vout1 AD8009an +***** AD8009 SPICE model Rev B SMR/ADI 8-21-97 + +* Copyright 1997 by Analog Devices, Inc. + +* Refer to "README.DOC" file for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. + +* rev B of this model corrects a problem in the output stage that would not +* correctly reflect the output current to the voltage supplies + +* This model will give typical performance characteristics +* for the following parameters; + +* closed loop gain and phase vs bandwidth +* output current and voltage limiting +* offset voltage (is static, will not vary with vcm) +* ibias (again, is static, will not vary with vcm) +* slew rate and step response performance +* (slew rate is based on 10-90% of step response) +* current on output will be reflected to the supplies +* vnoise, referred to the input +* inoise, referred to the input + +* distortion is not characterized + +* Node assignments +* non-inverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +.SUBCKT AD8009an 1 2 99 50 28 + +* input stage * + +q1 50 3 5 qp1 +q2 99 5 4 qn1 +q3 99 3 6 qn2 +q4 50 6 4 qp2 +i1 99 5 1.625e-3 +i2 6 50 1.625e-3 +cin1 1 98 2.6e-12 +cin2 2 98 1e-12 +v1 4 2 0 + +* input error sources * + +eos 3 1 poly(1) 20 98 2e-3 1 +fbn 2 98 poly(1) vnoise3 50e-6 1e-3 +fbp 1 98 poly(1) vnoise3 50e-6 1e-3 + +* slew limiting stage * + +fsl 98 16 v1 1 +dsl1 98 16 d1 +dsl2 16 98 d1 +dsl3 16 17 d1 +dsl4 17 16 d1 +rsl 17 18 0.22 +vsl 18 98 0 + +* gain stage * + +f1 98 7 vsl 2 +rgain 7 98 2.5e5 +cgain 7 98 1.25e-12 +dcl1 7 8 d1 +dcl2 9 7 d1 +vcl1 99 8 1.83 +vcl2 9 50 1.83 + +gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5 + +* second pole * + +epole 14 98 7 98 1 +rpole 14 15 1 +cpole 15 98 2e-10 + +* reference stage * + +eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 + +ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5 + +* vnoise stage * + +rnoise1 19 98 4.6e-3 +vnoise1 19 98 0 +vnoise2 21 98 0.53 +dnoise1 21 19 dn + +fnoise1 20 98 vnoise1 1 +rnoise2 20 98 1 + +* inoise stage * + +rnoise3 22 98 8.18e-6 +vnoise3 22 98 0 +vnoise4 24 98 0.575 +dnoise2 24 22 dn + +fnoise2 23 98 vnoise3 1 +rnoise4 23 98 1 + +* buffer stage * + +gbuf 98 13 15 98 1e-2 +rbuf 98 13 1e2 + +* output current reflected to supplies * + +fcurr 98 40 voc 1 +vcur1 26 98 0 +vcur2 98 27 0 +dcur1 40 26 d1 +dcur2 27 40 d1 + +* output stage * + +vo1 99 90 0 +vo2 91 50 0 +fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1 +fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1 +gout1 90 10 13 99 0.5 +gout2 91 10 13 50 0.5 +rout1 10 90 2 +rout2 10 91 2 +voc 10 28 0 +rout3 28 98 1e6 +dcl3 13 11 d1 +dcl4 12 13 d1 +vcl3 11 10 -0.445 +vcl4 10 12 -0.445 + +.model qp1 pnp(level=1) +.model qp2 pnp(level=1) +.model qn1 npn(level=1) +.model qn2 npn(level=1) +.model d1 d() +.model dn d(af=1 kf=1e-8) +.ends +R6 1 Vout1 250 +C3 1 0 1.5pF +V3 VU1in- Vinput DC 0V +* .INCLUDE /home/sdb/OpticalReceiver/Simulation.cmd +R5 -5V Vout1 1K +I1 0 Vinput AC 1 PWL (0ns 0mA 1nS 0mA 1.01nS 1mA 10nS 1mA 10.01nS 0mA 20nS 0mA 20.01nS .1mA 30nS .1mA 30.01nS 0mA) +R4 V1- -5V 5 +C2 0 V1- .01uF +V2 -5V 0 DC -5V +R2 VU1in- Vout1 180 +V1 +5V 0 DC 5V +C1 V1+ 0 .01uF +R1 +5V V1+ 5 +* When run, this SPICE file should output a square waveform +* with a little overshoot +.tran 0.05ns 40ns +.plot tran Vout2 +.END diff --git a/Windows/spice/examples/TransmissionLines/cpl1_4_line.sp b/Windows/spice/examples/TransmissionLines/cpl1_4_line.sp new file mode 100644 index 00000000..7c46b655 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl1_4_line.sp @@ -0,0 +1,63 @@ +MOSdriver -- 6.3inch 4 lossy line CPL model -- C load + +m1 1 2 6 1 mp1p0 w = 36.0u l=1.0u +m2 1 3 7 1 mp1p0 w = 36.0u l=1.0u +m3 1 4 8 1 mp1p0 w = 36.0u l=1.0u +m4 1 10 5 1 mp1p0 w = 36.0u l=1.0u +m5 1 11 13 1 mp1p0 w = 36.0u l=1.0u +m6 1 12 13 1 mp1p0 w = 36.0u l=1.0u + +m7 0 2 6 0 mn0p9 w = 18.0u l=0.9u +m8 0 3 7 0 mn0p9 w = 18.0u l=0.9u +m9 0 4 8 0 mn0p9 w = 18.0u l=0.9u +m10 0 10 5 0 mn0p9 w = 18.0u l=0.9u +m11 14 11 13 0 mn0p9 w = 18.0u l=0.9u +m12 0 12 14 0 mn0p9 w = 18.0u l=0.9u + +* +CN5 5 0 0.025398e-12 +CN6 6 0 0.007398e-12 +CN7 7 0 0.007398e-12 +CN8 8 0 0.007398e-12 +CN9 9 0 0.097398e-12 +CN10 10 0 0.007398e-12 +CN11 11 0 0.003398e-12 +CN12 12 0 0.004398e-12 +CN13 13 0 0.008398e-12 +CN14 14 0 0.005398e-12 + +* +P1 5 6 7 8 0 9 10 11 12 0 pline + +* +* +vdd 1 0 DC 5.0 +v3 3 0 DC 5.0 +* +VS1 2 0 PULSE ( 0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS) +VS2 4 0 PULSE (0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS ) +* +.control +TRAN 0.2N 47.9N 0 0.05N +plot V(5) V(6) V(7) V(8) V(9) V(10) V(11) V(12) +.endc +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 LAMBDA=0.00 CGSO=0 CGDO=0 ++CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 LAMBDA=0.00 CGSO=0 CGDO=0 ++CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL PLINE cpl ++R=0.03 0 0 0 ++ 0.03 0 0 ++ 0.03 0 ++ 0.03 ++L=9e-9 5.4e-9 0 0 ++ 9e-9 5.4e-9 0 ++ 9e-9 5.4e-9 ++ 9e-9 ++G=0 0 0 0 0 0 0 0 0 0 ++C=3.5e-13 -3e-14 0 0 ++ 3.5e-13 -3e-14 0 ++ 3.5e-13 -3e-14 ++ 3.5e-13 ++length=6.3 +.END diff --git a/Windows/spice/examples/TransmissionLines/cpl2_2_line.sp b/Windows/spice/examples/TransmissionLines/cpl2_2_line.sp new file mode 100644 index 00000000..713e3334 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl2_2_line.sp @@ -0,0 +1,46 @@ +MOSdriver -- 24inch 2 lossy lines CPL model -- C load + +m1 0 268 299 0 mn0p9 w = 18.0u l=1.0u +m2 299 267 748 0 mn0p9 w = 18.0u l=1.0u +m3 0 168 648 0 mn0p9 w = 18.0u l=0.9u +m4 1 268 748 1 mp1p0 w = 36.0u l=1.0u +m5 1 267 748 1 mp1p0 w = 36.0u l=1.0u +m6 1 168 648 1 mp1p0 w = 36.0u l=1.0u +* +CN648 648 0 0.025398e-12 +CN651 651 0 0.007398e-12 +CN748 748 0 0.025398e-12 +CN751 751 0 0.009398e-12 +CN299 299 0 0.005398e-12 +* +P1 648 748 0 651 751 0 PLINE +* +vdd 1 0 DC 5.0 +VK 267 0 DC 5.0 +* +*VS 168 0 PWL 4 15.9N 0.0 16.1n 5.0 31.9n 5.0 32.1n 0.0 +*VS 268 0 PWL 4 15.9N 0.0 16.1n 5.0 31.9n 5.0 32.1n 0.0 +* +VS1 168 0 PULSE (0 5 15.9N 0.2N 0.2N 15.8N 60N) +VS2 268 0 PULSE (0 5 15.9N 0.2N 0.2N 15.8N 60N) +* +.control +TRAN 0.2N 47.9NS 0 1N +plot v(648) v(651) v(751) +.endc +* +.MODEL PLINE CPL ++R=0.2 0 ++ 0.2 ++L=9.13e-9 3.3e-9 ++ 9.13e-9 ++G=0 0 0 ++C=3.65e-13 -9e-14 ++ 3.65e-13 ++length=24 +******************* MODEL SPECIFICATION ********************** +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 LAMBDA=0.00 CGSO=0 CGDO=0 ++ CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 LAMBDA=0.00 CGSO=0 CGDO=0 ++ CJ=0 CJSW=0 TOX=18000N LD=0.0U +.END diff --git a/Windows/spice/examples/TransmissionLines/cpl3_4_line.sp b/Windows/spice/examples/TransmissionLines/cpl3_4_line.sp new file mode 100644 index 00000000..d5715481 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl3_4_line.sp @@ -0,0 +1,37 @@ +6.3inch 4 lossy lines CPL model -- R load + +Ra 1 2 1K +Rb 0 3 1K +Rc 0 4 1K +Rd 0 5 1K +Re 6 0 1Meg +Rf 7 0 1Meg +Rg 8 0 1Meg +Rh 9 0 1Meg +* +P1 2 3 4 5 0 6 7 8 9 0 LOSSYMODE +* +* +VS1 1 0 PWL(15.9NS 0.0 16.1Ns 5.0 31.9Ns 5.0 32.1Ns 0.0) +* +.control +TRAN 0.2NS 50NS 0 0.05N +PLOT V(1) V(2) V(6) V(7) V(8) V(9) +.endc +.MODEL LOSSYMODE CPL ++R=0.3 0 0 0 ++ 0.3 0 0 ++ 0.3 0 ++ 0.3 ++L=9e-9 5.4e-9 0 0 ++ 9e-9 5.4e-9 0 ++ 9e-9 5.4e-9 ++ 9e-9 ++G=0 0 0 0 0 0 0 0 0 0 ++C=3.5e-13 -3e-14 0 0 ++ 3.5e-13 -3e-14 0 ++ 3.5e-13 -3e-14 ++ 3.5e-13 ++length=6.3 + +.END diff --git a/Windows/spice/examples/TransmissionLines/cpl4_txl_2_line.sp b/Windows/spice/examples/TransmissionLines/cpl4_txl_2_line.sp new file mode 100644 index 00000000..986c9b63 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl4_txl_2_line.sp @@ -0,0 +1,378 @@ +BJTdriver -- 2in st. lin -- 20in coupled line CPL -- 2in st line -- DiodeCircuit + +* This unclassified circuit is from Raytheon, courtesy Gerry Marino. +* +* _______ +* -------- 2in _________________ 2in | | +* | BJT |______| |______|Diode| +* | |------| |------| | +* | Drvr | line | 2-wire | line |rcvr.| +* -------- | coupled | |_____| +* | transmission | +* |-/\/\/\/\----| line |-------\/\/\/\/\----| +* | 50ohms | | 50ohms | +* | | | | +* Ground ----------------- Ground +* +* +* Each inch of the lossy line is modelled by 10 LRC lumps in the +* Raytheon model. + +* The line parameters (derived from the Raytheon input file) are: +* L = 9.13nH per inch +* C = 3.65pF per inch +* R = 0.2 ohms per inch +* K = 0.482 [coupling coefficient; K = M/sqrt(L1*L2)] +* Cc = 1.8pF per inch +* +* coupled ltra model generated using the standalone program +* multi_decomp + +* the circuit +*tran 0.1ns 60ns + +v1 1 0 0v pulse(0 4 1ns 1ns 1ns 20ns 40ns) +*v1 1 0 4v pulse(4 0 1ns 1ns 1ns 20ns 40ns) +vcc 10 0 5v + +* series termination +*x1 1 oof 10 bjtdrvr +*rseries oof 2 50 + +x1 1 2 10 bjtdrvr +rt1 3 0 50 + + +* convolution model +x2 2 3 4 5 conv2wetcmodel + +* rlc segments model +*x2 2 3 4 5 rlc2wetcmodel + +x3 4 dioload +rt2 5 0 50 + + + +.model qmodn npn(bf=100 rb=100 cje=0.09375pF cjc=0.28125pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpd npn(bf=100 rb=100 cje=0.08187pF cjc=0.2525pF is=1e-12 ++pe=0.5 pc=0.5) +.model qmodpdmine npn(bf=100 rb=100 cje=0.08187pF cjc=0.05pF is=1e-12 ++pe=0.5 pc=0.5) + +.model dmod1 d(n=2.25 is=1.6399e-4 bv=10) + +.model dmod2 d + +.model dmod d(vj=0.3v) + +.model diod1 d(tt=0.75ns vj=0.6 rs=909 bv=10) + +.model diod2 d(tt=0.5ns vj=0.3 rs=100 bv=10) + +.options acct reltol=1e-3 abstol=1e-12 +.control +tran 0.1ns 60ns 0 0.35N +plot v(2) v(4) v(5) +.endc + +* bjt driver - 19=input, 268=output, 20=vcc; wierd node numbers from +* the Raytheon file + +.subckt bjtdrvr 19 268 20 +q1 22 18 13 qmodn +q2 18 16 13 qmodn +qd2 21 9 0 qmodn +q4 14 14 0 qmodn +q3 16 15 14 qmodpd +q5 8 13 17 qmodn +q6 25 12 0 qmodn +q7 6 17 0 qmodpd +qd1 26 10 0 qmodn +q8 7 11 10 qmodn +*q10 268 17 0 qmodpd +q10 268 17 0 qmodpdmine +q9 7 10 268 qmodn + +d1 0 19 dmod1 +d2 18 19 dmod2 +d3 13 19 dmod +dq1 18 22 dmod +dq2 16 18 dmod +d502 9 21 dmod +dq3 15 16 dmod +d10 24 8 dmod +d4 15 6 dmod +dq6 12 25 dmod +dq7 17 6 dmod +dd1 17 10 dmod +d7 11 6 dmod +dd2 17 26 dmod +d9 23 6 dmod +dq8 11 7 dmod +d501 17 268 dmod +dq9 10 7 dmod +d14 20 27 dmod +d8 0 268 dmod + +r1 18 20 6k +r2 22 20 2.2k +r4 0 13 7k +rd1 9 13 2k +rd2 21 13 3k +r3 16 20 10k +r5 15 20 15k +r9 0 17 4k +r6 24 20 750 +r10 12 17 2k +r12 24 11 1.5k +r11 25 17 3k +r15 23 20 10k +r13 0 10 15k +r14 7 27 12 + +.ends bjtdrvr + +* subckt dioload - diode load: input=28, output=4, vcc=5 + +.subckt dioload 28 +*comment out everything in dioload except d5 and r503, and watch +* the difference in results obtained between a tran 0.1ns 20ns and +* a tran 0.01ns 20ns +vccint 5 0 5v + +c1 28 0 5pF +r503 0 4 5.55 +r4 0 28 120k +r5 1 5 7.5k + +d5 4 28 diod2 +d1 1 28 diod1 +d4 2 0 diod1 +d3 3 2 diod1 +d2 1 3 diod1 +.ends dioload + +* subckt rlclump - one RLC lump of the lossy line + +.subckt rlclump 1 2 +*r1 1 3 0.02 +*c1 3 0 0.365pF +*l1 3 2 0.913nH + +l1 1 3 0.913nH +c1 2 0 0.365pF +r1 3 2 0.02 + +*r1 1 3 0.01 +*c1 3 0 0.1825pF +*l1 3 4 0.4565nH +*r2 4 5 0.01 +*c2 5 0 0.1825pF +*l2 5 2 0.4565nH + +*c1 1 0 0.365pF +*l1 1 2 0.913nH +.ends lump + +.subckt rlconeinch 1 2 +x1 1 3 rlclump +x2 3 4 rlclump +x3 4 5 rlclump +x4 5 6 rlclump +x5 6 7 rlclump +x6 7 8 rlclump +x7 8 9 rlclump +x8 9 10 rlclump +x9 10 11 rlclump +x10 11 2 rlclump +.ends rlconeinch + +.subckt rlctwoinch 1 2 +x1 1 3 rlconeinch +x2 3 2 rlconeinch +.ends rlctwoinch + +.subckt rlcfourinch 1 2 +x1 1 3 rlconeinch +x2 3 4 rlconeinch +x3 4 5 rlconeinch +x4 5 2 rlconeinch +.ends rlcfourinch + +.subckt rlcfiveinch 1 2 +x1 1 3 rlconeinch +x2 3 4 rlconeinch +x3 4 5 rlconeinch +x4 5 6 rlconeinch +x5 6 2 rlconeinch +.ends rlcfiveinch + +.subckt rlctwentyrlcfourinch 1 2 +x1 1 3 rlcfiveinch +x2 3 4 rlcfiveinch +x3 4 5 rlcfiveinch +x4 5 6 rlcfiveinch +x5 6 2 rlcfourinch +.ends rlctwentyrlcfourinch + +.subckt rlclumpstub A B C D +x1 A int1 rlcfiveinch +x2 int1 int2 rlcfiveinch +x3 int2 1 rlcfiveinch +x4 1 2 rlcfourinch +x5 1 int3 rlcfiveinch +x6 int3 B rlconeinch +x7 2 C rlcfiveinch +x8 2 D rlcfourinch +.ends rlclumpstub + +.subckt ltrastub A B C D +yy1 A 0 1 0 ylline15in +yy2 1 0 B 0 ylline6in +yy3 1 0 2 0 ylline4in +yy4 2 0 C 0 ylline5in +yy5 2 0 D 0 ylline4in +.ends ltrastub + +*modelling using R and lossless lines + +*5 segments per inch +.model yllfifth txl r=0 g=0 l=9.13e-9 c=3.65e-12 length=0.2 + +.subckt xlump 1 2 +y1 1 0 3 0 yllfifth +r1 2 3 0.04 +.ends xlump + +.subckt xoneinch 1 2 +x1 1 3 xlump +x2 3 4 xlump +x3 4 5 xlump +x4 5 6 xlump +x5 6 2 xlump +*x5 6 7 xlump +*x6 7 8 xlump +*x7 8 9 xlump +*x8 9 10 xlump +*x9 10 11 xlump +*x10 11 2 xlump +.ends xoneinch + +.subckt xFourinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 2 xoneinch +.ends xfourinch + +.subckt xfiveinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 6 xoneinch +x5 6 2 xoneinch +.ends xfiveinch + +.subckt xlumpstub A B C D +x1 A int1 xfiveinch +x2 int1 int2 xfiveinch +x3 int2 1 xfiveinch +x4 1 2 xfourinch +x5 1 int3 xfiveinch +x6 int3 B xoneinch +x7 2 C xfiveinch +x8 2 D xfourinch +.ends xlumpstub + +* modelling a 2 wire coupled system using RLC lumps +* 10 segments per inch +* +* 1---xxxxx----2 +* 3---xxxxx----4 + +.subckt rlc2wlump 1 3 2 4 +l1 1 5 0.913nH +c1 2 0 0.365pF +r1 5 2 0.02 +l2 3 6 0.913nH +c2 4 0 0.365pF +r2 6 4 0.02 +cmut 2 4 0.18pF +k12 l1 l2 0.482 +.ends rlc2wlump + +.subckt rlc2woneinch 1 2 3 4 +x1 1 2 5 6 rlc2wlump +x2 5 6 7 8 rlc2wlump +x3 7 8 9 10 rlc2wlump +x4 9 10 11 12 rlc2wlump +x5 11 12 13 14 rlc2wlump +x6 13 14 15 16 rlc2wlump +x7 15 16 17 18 rlc2wlump +x8 17 18 19 20 rlc2wlump +x9 19 20 21 22 rlc2wlump +x10 21 22 3 4 rlc2wlump +.ends rlc2woneinch + +.subckt rlc2wfiveinch 1 2 3 4 +x1 1 2 5 6 rlc2woneinch +x2 5 6 7 8 rlc2woneinch +x3 7 8 9 10 rlc2woneinch +x4 9 10 11 12 rlc2woneinch +x5 11 12 3 4 rlc2woneinch +.ends rlc2wfiveinch + +.subckt rlc2wtwentyinch 1 2 3 4 +x1 1 2 5 6 rlc2wfiveinch +x2 5 6 7 8 rlc2wfiveinch +x3 7 8 9 10 rlc2wfiveinch +x4 9 10 3 4 rlc2wfiveinch +.ends rlc2wtwentyinch + +.subckt rlc2wetcmodel 1 2 3 4 +x1 1 5 rlctwoinch +x2 5 2 6 4 rlc2wtwentyinch +x3 6 3 rlctwoinch +.ends rlc2wetcmodel + +* Subcircuit conv2wtwentyinch +* conv2wtwentyinch is a subcircuit that models a 2-conductor transmission line with +* the following parameters: l=9.13e-09, c=3.65e-12, r=0.2, g=0, +* inductive_coeff_of_coupling k=0.482, inter-line capacitance cm=1.8e-12, +* length=20. Derived parameters are: lm=4.40066e-09, ctot=5.45e-12. +* +* It is important to note that the model is a simplified one - the +* following assumptions are made: 1. The self-inductance l, the +* self-capacitance ctot (note: not c), the series resistance r and the +* parallel capacitance g are the same for all lines, and 2. Each line +* is coupled only to the two lines adjacent to it, with the same +* coupling parameters cm and lm. The first assumption imply that edge +* effects have to be neglected. The utility of these assumptions is +* that they make the sL+R and sC+G matrices symmetric, tridiagonal and +* Toeplitz, with useful consequences. +* +* It may be noted that a symmetric two-conductor line will be +* accurately represented by this model. + +* swec model +.model plines cpl ++R=0.2 0 ++ 0.2 ++L=9.13e-9 4.4e-9 ++ 9.13e-9 ++G=0 0 0 ++C=5.45e-12 -1.8e-12 ++ 5.45e-12 ++length=20 + +.model yconvtwoinch txl r=0.2 g=0 l=9.13e-9 c=3.65e-12 length=2.0 +.subckt conv2wetcmodel 1 2 3 4 +y1 1 0 5 0 yconvtwoinch +p2 5 2 0 6 4 0 plines +y2 6 0 3 0 yconvtwoinch +.ends conv2wetcmodel + +.end diff --git a/Windows/spice/examples/TransmissionLines/cpl_ibm1.sp b/Windows/spice/examples/TransmissionLines/cpl_ibm1.sp new file mode 100644 index 00000000..1077d00e --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl_ibm1.sp @@ -0,0 +1,82 @@ +6-line coupled multiconductor with ECL drivers +vemm mm 0 DC -0.4 +vepp pp 0 DC 0.4 +vein_left lin 0 PULSE (-0.4 0.4 0N 1N 1N 7N 200N) +vein_right rin 0 PULSE (-0.4 0.4 2N 1N 1N 7N 200N) + +* upper 2 lines +x1 lin 0 1 1outn ECL +x2 mm 0 2 2outn ECL +x7 7 0 7r 7routn ECL +x8 8 0 8r 8routn ECL + +c7r 7r 0 0.1P +c8r 8r 0 0.1P + +* lower 2 lines +x11 pp 0 11 11outn ECL +x12 rin 0 12 12outn ECL +x5 5 0 5l 5loutn ECL +x6 6 0 6l 6loutn ECL + +c5l 5l 0 0.1P +c6l 6l 0 0.1P + +p1 1 2 3 4 5 6 0 7 8 9 10 11 12 0 pline + +.model pline cpl ++C = 0.900000P -0.657947P -0.0767356P -0.0536544P -0.0386514P -0.0523990P ++ 1.388730P -0.607034P -0.0597635P -0.0258851P -0.0273442P ++ 1.39328P -0.625675P -0.0425551P -0.0319791P ++ 1.07821P -0.255048P -0.0715824P ++ 1.06882P -0.692091P ++ 0.900000P ++L = 0.868493E-7 0.781712E-7 0.748428E-7 0.728358E-7 0.700915E-7 0.692178E-7 ++ 0.866074E-7 0.780613E-7 0.748122E-7 0.711591E-7 0.701023E-7 ++ 0.865789E-7 0.781095E-7 0.725431E-7 0.711986E-7 ++ 0.867480E-7 0.744242E-7 0.725826E-7 ++ 0.868022E-7 0.782377E-7 ++ 0.868437E-7 ++R = 0.2 0 0 0 0 0 ++ 0.2 0 0 0 0 ++ 0.2 0 0 0 ++ 0.2 0 0 ++ 0.2 0 ++ 0.2 ++G = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ ++length = 2 + +*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +.SUBCKT ECL EIN GND 9 8 +* Input-GND-OUTP-OUTN +RIN 1 2 0.077K +REF 5 6 0.077K +R1 7 N 1.0K +R2 P 3 0.4555K +R3 P 4 0.4555K +R4 8 N 0.615K +R5 9 N 0.615K +RL1 8 GND 0.093K +RL2 9 GND 0.093K +LIN EIN 1 0.01U +LREF 5 GND 0.01U +CIN 1 GND 0.68P +CL1 8 GND 1P +CL2 9 GND 1P +Q1 3 2 7 JCTRAN +Q2 4 6 7 JCTRAN +Q3 P 3 8 JCTRAN +Q4 P 4 9 JCTRAN +VEP P GND DC 1.25 +VEN N GND DC -3 +.ENDS ECL + +.control +TRAN 0.1N 20N +plot V(3) V(5) V(8) V(11) V(12) +.endc +.MODEL JCTRAN NPN BF=150 VAF=20 IS=4E-17 RB=300 RC=100 CJE=30F CJC=30F ++ CJS=40F VJE=0.6 VJC=0.6 VJS=0.6 MJE=0.5 MJC=0.5 ++ MJS=0.5 TF=16P TR=1N +.END diff --git a/Windows/spice/examples/TransmissionLines/cpl_ibm2.sp b/Windows/spice/examples/TransmissionLines/cpl_ibm2.sp new file mode 100644 index 00000000..8aeff85d --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl_ibm2.sp @@ -0,0 +1,22 @@ +Simple coupled transmissionlines +VES IN 0 PULSE (0 1 0N 1.5N 1.5N 4.5N 200N) +R1 IN V1 50 +R2 V2 0 10 +p1 V1 V2 0 V3 V4 0 cpl1 +.model cpl1 cpl ++R = 0.5 0 ++ 0.5 ++L = 247.3e-9 31.65e-9 ++ 247.3e-9 ++C = 31.4e-12 -2.45e-12 ++ 31.4e-12 ++G = 0 0 0 ++length = 0.3048 +*length = 0.6096 +R3 V3 0 100 +R4 V4 0 100 +.control +TRAN 0.1N 20N +plot v(in) v(v1) v(v3) +.endc +.END diff --git a/Windows/spice/examples/TransmissionLines/cpl_ibm3.sp b/Windows/spice/examples/TransmissionLines/cpl_ibm3.sp new file mode 100644 index 00000000..0a0d5e22 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/cpl_ibm3.sp @@ -0,0 +1,70 @@ +Mixed single and coupled transmission lines +c1g 1 0 1P +l11a 1 1a 6e-9 +r1a7 1a 7 0.025K +rin6 in 6 0.075K +l67 6 7 10e-9 +c7g 7 0 1P +P2 1 7 0 2 8 0 PLINE +.MODEL PLINE CPL ++R = 2.25 0 ++ 2.25 ++L = 0.6e-6 0.05e-6 ++ 0.6e-6 ++G = 0 0 0 ++C = 1.2e-9 -0.11e-9 ++ 1.2e-9 ++length = 0.03 +c2g 2 0 0.5P +r2g 2 0 0.05K +r23 2 3 0.025K +l34 3 4 5e-9 +c4g 4 0 2P +l89 8 9 10e-9 +c9g 9 0 1P +Y1 9 0 10 0 txline +.model txline txl R = 1 L =0.6e-6 G = 0 C= 1.0e-9 length=0.04 +l1011 10 11 10e-9 +c11g 11 0 0.5P +r11g 11 0 0.05K +r1112 11 12 0.025K +l1213 12 13 5e-9 +c13g 13 0 2P +r1116 11 16 0.025K +l1617 16 17 5e-9 +c17g 17 0 2P +P1 4 2 13 17 0 5 14 15 18 0 PLINE1 + +.MODEL PLINE1 CPL ++R = 3.5 0 0 0 ++ 3.5 0 0 ++ 3.5 0 ++ 3.5 ++L = ++1e-6 0.11e-6 0.03e-6 0 ++ 1e-6 0.11e-6 0.03e-6 ++ 1e-6 0.11e-6 ++ 1e-6 ++G = 0 0 0 0 0 0 0 0 0 0 ++C = ++1.5e-9 -0.17e-9 -0.03e-9 0 ++ 1.5e-9 -0.17e-9 -0.03e-9 ++ 1.5e-9 -0.17e-9 ++ 1.5e-9 ++length = 0.02 + +D1 5 0 dmod +D2 14 0 dmod +D3 15 0 dmod +D4 18 0 dmod + +.model dmod d + +VES in 0 PULSE (0 5 0 1.1ns 0.1ns 0.9ns 200ns) + +.control +TRAN 0.2N 10.0N +plot v(3) v(6) v(7) v(8) v(11) v(15) +.endc + +.END diff --git a/Windows/spice/examples/TransmissionLines/ltra1_1_line.sp b/Windows/spice/examples/TransmissionLines/ltra1_1_line.sp new file mode 100644 index 00000000..2d9c93bb --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra1_1_line.sp @@ -0,0 +1,19 @@ +MOSdriver -- lossy line LTRA model -- C load +m5 0 168 2 0 mn0p9 w = 18.0u l=0.9u +m6 1 168 2 1 mp1p0 w = 36.0u l=1.0u +CN2 2 0 0.025398e-12 +CN3 3 0 0.007398e-12 +o1 2 0 3 0 lline +vdd 1 0 dc 5.0 +VS 168 0 PULSE (0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS ) +.control +TRAN 0.2N 47N 0 0.1N +plot v(2) v(3) ylimit -0.5 5 +.endc +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.model lline ltra rel=1 r=12.45 g=0 l=8.972e-9 c=0.468e-12 ++len=16 steplimit compactrel=1.0e-3 compactabs=1.0e-14 +.end diff --git a/Windows/spice/examples/TransmissionLines/ltra1_4_line.sp b/Windows/spice/examples/TransmissionLines/ltra1_4_line.sp new file mode 100644 index 00000000..8d30a757 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra1_4_line.sp @@ -0,0 +1,144 @@ +MOSdriver -- 6.3inch 4 lossy line LTRA model -- C load + +m1 1 2 6 1 mp1p0 w = 36.0u l=1.0u +m2 1 3 7 1 mp1p0 w = 36.0u l=1.0u +m3 1 4 8 1 mp1p0 w = 36.0u l=1.0u +m4 1 10 5 1 mp1p0 w = 36.0u l=1.0u +m5 1 11 13 1 mp1p0 w = 36.0u l=1.0u +m6 1 12 13 1 mp1p0 w = 36.0u l=1.0u + +m7 0 2 6 0 mn0p9 w = 18.0u l=0.9u +m8 0 3 7 0 mn0p9 w = 18.0u l=0.9u +m9 0 4 8 0 mn0p9 w = 18.0u l=0.9u +m10 0 10 5 0 mn0p9 w = 18.0u l=0.9u +m11 14 11 13 0 mn0p9 w = 18.0u l=0.9u +m12 0 12 14 0 mn0p9 w = 18.0u l=0.9u + + +* +CN5 5 0 0.025398e-12 +CN6 6 0 0.007398e-12 +CN7 7 0 0.007398e-12 +CN8 8 0 0.007398e-12 +CN9 9 0 0.097398e-12 +CN10 10 0 0.007398e-12 +CN11 11 0 0.003398e-12 +CN12 12 0 0.004398e-12 +CN13 13 0 0.008398e-12 +CN14 14 0 0.005398e-12 + +* +* Subcircuit test +* test is a subcircuit that models a 4-conductor transmission line with +* the following parameters: l=9e-09, c=2.9e-13, r=0.3, g=0, +* inductive_coeff_of_coupling k=0.6, inter-line capacitance cm=3e-14, +* length=6.3. Derived parameters are: lm=5.4e-09, ctot=3.5e-13. +* +* It is important to note that the model is a simplified one - the +* following assumptions are made: 1. The self-inductance l, the +* self-capacitance ctot (note: not c), the series resistance r and the +* parallel capacitance g are the same for all lines, and 2. Each line +* is coupled only to the two lines adjacent to it, with the same +* coupling parameters cm and lm. The first assumption implies that edge +* effects have to be neglected. The utility of these assumptions is +* that they make the sL+R and sC+G matrices symmetric, tridiagonal and +* Toeplitz, with useful consequences (see "Efficient Transient +* Simulation of Lossy Interconnect", by J.S. Roychowdhury and +* D.O Pederson, Proc. DAC 91). + +* It may be noted that a symmetric two-conductor line is +* represented accurately by this model. + +* Subckt node convention: +* +* |--------------------------| +* 1-----| |-----n+1 +* 2-----| |-----n+2 +* : | n-wire multiconductor | : +* : | line | : +* n-1-----|(node 0=common gnd plane) |-----2n-1 +* n-----| |-----2n +* |--------------------------| + + +* Lossy line models +.model mod1_test ltra rel=1.2 nocontrol r=0.3 l=2.62616456193e-10 g=0 c=3.98541019688e-13 len=6.3 +.model mod2_test ltra rel=1.2 nocontrol r=0.3 l=5.662616446e-09 g=0 c=3.68541019744e-13 len=6.3 +.model mod3_test ltra rel=1.2 nocontrol r=0.3 l=1.23373835171e-08 g=0 c=3.3145898046e-13 len=6.3 +.model mod4_test ltra rel=1.2 nocontrol r=0.3 l=1.7737383521e-08 g=0 c=3.01458980439e-13 len=6.3 + +* subcircuit m_test - modal transformation network for test +.subckt m_test 1 2 3 4 5 6 7 8 +v1 9 0 0v +v2 10 0 0v +v3 11 0 0v +v4 12 0 0v +f1 0 5 v1 0.371748033738 +f2 0 5 v2 -0.601500954587 +f3 0 5 v3 0.601500954587 +f4 0 5 v4 -0.371748036544 +f5 0 6 v1 0.60150095443 +f6 0 6 v2 -0.371748035044 +f7 0 6 v3 -0.371748030937 +f8 0 6 v4 0.601500957402 +f9 0 7 v1 0.601500954079 +f10 0 7 v2 0.37174803072 +f11 0 7 v3 -0.371748038935 +f12 0 7 v4 -0.601500955482 +f13 0 8 v1 0.371748035626 +f14 0 8 v2 0.601500956073 +f15 0 8 v3 0.601500954504 +f16 0 8 v4 0.371748032386 +e1 13 9 5 0 0.371748033909 +e2 14 13 6 0 0.601500954587 +e3 15 14 7 0 0.601500955639 +e4 1 15 8 0 0.371748036664 +e5 16 10 5 0 -0.60150095443 +e6 17 16 6 0 -0.371748035843 +e7 18 17 7 0 0.371748032386 +e8 2 18 8 0 0.601500957319 +e9 19 11 5 0 0.601500955131 +e10 20 19 6 0 -0.371748032169 +e11 21 20 7 0 -0.371748037896 +e12 3 21 8 0 0.601500954513 +e13 22 12 5 0 -0.371748035746 +e14 23 22 6 0 0.60150095599 +e15 24 23 7 0 -0.601500953534 +e16 4 24 8 0 0.371748029317 +.ends m_test + +* Subckt test +.subckt test 1 2 3 4 5 6 7 8 +x1 1 2 3 4 9 10 11 12 m_test +o1 9 0 13 0 mod1_test +o2 10 0 14 0 mod2_test +o3 11 0 15 0 mod3_test +o4 12 0 16 0 mod4_test +x2 5 6 7 8 13 14 15 16 m_test +.ends test +* +x1 5 6 7 8 9 10 11 12 test +* +* +vdd 1 0 PULSE (0 5 0Ns 0.1Ns 0.1Ns 600Ns 800Ns) +v3 3 0 PULSE (0 5 0Ns 0.1Ns 0.1Ns 600Ns 800Ns) + +.model mn0p9 nmos LEVEL=1 vto=0.8V kp=48u gamma=0.3 phi=0.55 lambda=0.00 ++ PHI=0.55 LAMBDA=0.00 CGSO=0 CGDO=0 CGBO=0 ++ CJ=0 CJSW=0 TOX=18000N NSUB=1E16 LD=0.0U + +.model mp1p0 pmos vto=-0.8V kp=21u gamma=0.45 phi=0.61 lambda=0.00 ++ PHI=0.61 LAMBDA=0.00 CGSO=0 CGDO=0 CGBO=0 ++ CJ=0 CJSW=0 TOX=18000N NSUB=3E16 LD=0.0U + +VS1 2 0 PULSE (0 5 15.9Ns 0.2Ns 0.2Ns 15.8Ns 32Ns) +VS2 4 0 PULSE (0 5 15.9Ns 0.2Ns 0.2Ns 15.8Ns 32Ns) + +.control +TRAN 0.1N 47.9N +plot v(5) v(6) v(7) v(8) v(9) v(10) v(11) v(12) +.endc +* + +.END + diff --git a/Windows/spice/examples/TransmissionLines/ltra2_2_line.sp b/Windows/spice/examples/TransmissionLines/ltra2_2_line.sp new file mode 100644 index 00000000..2a4ceaa7 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra2_2_line.sp @@ -0,0 +1,24 @@ +MOSdriver -- 2 lossy lines LTRA model -- C load +m5 0 168 2 0 mn0p9 w = 18.0u l=0.9u +m6 1 168 2 1 mp1p0 w = 36.0u l=1.0u +m1 0 3 4 0 mn0p9 w = 18.0u l=0.9u +m2 1 3 4 1 mp1p0 w = 36.0u l=1.0u +CN2 2 0 0.025398e-12 +CN3 3 0 0.007398e-12 +CN4 4 0 0.025398e-12 +CN5 5 0 0.007398e-12 +o1 2 0 3 0 lline +o2 4 0 5 0 lline +vdd 1 0 dc 5.0 +VS 168 0 PULSE (0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS ) +.control +TRAN 0.2N 47N 0 0.1N +plot v(2) v(3) v(4) v(5) +.endc +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.model lline ltra rel=1 r=12.45 g=0 l=8.972e-9 c=0.468e-12 ++len=16 steplimit compactrel=1.0e-3 compactabs=1.0e-14 +.end diff --git a/Windows/spice/examples/TransmissionLines/ltra3_2_line.sp b/Windows/spice/examples/TransmissionLines/ltra3_2_line.sp new file mode 100644 index 00000000..1a756520 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra3_2_line.sp @@ -0,0 +1,98 @@ +MOSdriver -- 24inch 2 lossy lines LTRA model -- C load + +m1 0 268 299 0 mn0p9 w = 18.0u l=1.0u +m2 299 267 748 0 mn0p9 w = 18.0u l=1.0u +m3 0 168 648 0 mn0p9 w = 18.0u l=0.9u +m4 1 268 748 1 mp1p0 w = 36.0u l=1.0u +m5 1 267 748 1 mp1p0 w = 36.0u l=1.0u +m6 1 168 648 1 mp1p0 w = 36.0u l=1.0u + +* +CN648 648 0 0.025398e-12 +CN651 651 0 0.007398e-12 +CN748 748 0 0.025398e-12 +CN751 751 0 0.009398e-12 +CN299 299 0 0.005398e-12 +* +* Subcircuit test +* test is a subcircuit that models a 2-conductor transmission line with +* the following parameters: l=9.13e-09, c=2.75e-13, r=0.2, g=0, +* inductive_coeff_of_coupling k=0.36144, inter-line capacitance cm=9e-14, +* length=24. Derived parameters are: lm=3.29995e-09, ctot=3.65e-13. +* +* It is important to note that the model is a simplified one - the +* following assumptions are made: 1. The self-inductance l, the +* self-capacitance ctot (note: not c), the series resistance r and the +* parallel capacitance g are the same for all lines, and 2. Each line +* is coupled only to the two lines adjacent to it, with the same +* coupling parameters cm and lm. The first assumption implies that edge +* effects have to be neglected. The utility of these assumptions is +* that they make the sL+R and sC+G matrices symmetric, tridiagonal and +* Toeplitz, with useful consequences (see "Efficient Transient +* Simulation of Lossy Interconnect", by J.S. Roychowdhury and +* D.O Pederson, Proc. DAC 91). + +* It may be noted that a symmetric two-conductor line is +* represented accurately by this model. + +* Subckt node convention: +* +* |--------------------------| +* 1-----| |-----n+1 +* 2-----| |-----n+2 +* : | n-wire multiconductor | : +* : | line | : +* n-1-----|(node 0=common gnd plane) |-----2n-1 +* n-----| |-----2n +* |--------------------------| + + +* Lossy line models +.model mod1_test ltra rel=1.2 nocontrol r=0.2 l=5.83005279316e-09 g=0 c=4.55000000187e-13 len=24 +.model mod2_test ltra rel=1.2 nocontrol r=0.2 l=1.24299471863e-08 g=0 c=2.75000000373e-13 len=24 + +* subcircuit m_test - modal transformation network for test +.subckt m_test 1 2 3 4 +v1 5 0 0v +v2 6 0 0v +f1 0 3 v1 0.707106779721 +f2 0 3 v2 -0.707106782652 +f3 0 4 v1 0.707106781919 +f4 0 4 v2 0.707106780454 +e1 7 5 3 0 0.707106780454 +e2 1 7 4 0 0.707106782652 +e3 8 6 3 0 -0.707106781919 +e4 2 8 4 0 0.707106779721 +.ends m_test + +* Subckt test +.subckt test 1 2 3 4 +x1 1 2 5 6 m_test +o1 5 0 7 0 mod1_test +o2 6 0 8 0 mod2_test +x2 3 4 7 8 m_test +.ends test +* +x1 648 748 651 751 test +* +* +vdd 1 0 DC 5.0 +VK 267 0 DC 5.0 +* +VS1 168 0 PULSE (0 5 15.9N 0.2N 0.2N 15.8N 60N) +VS2 268 0 PULSE (0 5 15.9N 0.2N 0.2N 15.8N 60N) +* +.control +TRAN 0.2N 47.9NS +PLOT v(648) v(651) v(751) +.endc +* +.model mn0p9 nmos LEVEL=1 vto=0.8V kp=48u gamma=0.3 phi=0.55 lambda=0.0 ++ PHI=0.55 LAMBDA=0.00 CGSO=0 CGDO=0 CGBO=0 ++ CJ=0 CJSW=0 TOX=18000N NSUB=1E16 LD=0.0U + +.model mp1p0 pmos LEVEL=1 vto=-0.8V kp=21u gamma=0.45 phi=0.61 lambda=0.0 ++ PHI=0.61 LAMBDA=0.00 CGSO=0 CGDO=0 CGBO=0 ++ CJ=0 CJSW=0 TOX=18000N NSUB=3E16 LD=0.0U + +.END diff --git a/Windows/spice/examples/TransmissionLines/ltra4_1_line.sp b/Windows/spice/examples/TransmissionLines/ltra4_1_line.sp new file mode 100644 index 00000000..8dc8ada6 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra4_1_line.sp @@ -0,0 +1,239 @@ + BJTdriver -- 24inch lossy line LTRA model -- DiodeCircuit + +* This unclassified circuit is from Raytheon, courtesy Gerry Marino. +* It consists of a BJT driver connected by a 24 inch lossy line to a +* passive load consisting mostly of diodes. Each inch +* of the lossy line is modelled by 10 LRC lumps in the Raytheon +* model. + +* The line parameters (derived from the Raytheon input file) are: +* L = 9.13nH per inch +* C = 3.65pF per inch +* R = 0.2 ohms per inch + +* the circuit + +v1 1 0 0v pulse(0 4 1ns 1ns 1ns 20ns 40ns) + +vcc 10 0 5v +*rseries 1 2 5 +x1 1 2 10 bjtdrvr +*t1 2 0 3 0 z0=50.0136 td=4.38119ns rel=10 +o2 2 0 3 0 lline1 +*x2 2 3 oneinch +*x2 100 101 twentyfourinch +*x2 100 101 xtwentyfourinch +vtest1 2 100 0 +vtest2 101 3 0 +x3 3 4 10 dioload +*rl 3 0 5 +*dl 0 3 diod2 + +.model lline1 ltra rel=1 r=0.2 g=0 l=9.13e-9 c=3.65e-12 len=24 steplimit + +.model qmodn npn(bf=100 rb=100 cje=0.09375pF cjc=0.28125pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpd npn(bf=100 rb=100 cje=0.08187pF cjc=0.2525pF is=1e-12 ++pe=0.5 pc=0.5) +.model qmodpdmine npn(bf=100 rb=100 cje=0.08187pF cjc=0.05pF is=1e-12 ++pe=0.5 pc=0.5) + +.model dmod1 d(n=2.25 is=1.6399e-4 bv=10) + +.model dmod2 d + +.model dmod d(vj=0.3v) + +.model diod1 d(tt=0.75ns vj=0.6 rs=909 bv=10) + +.model diod2 d(tt=0.5ns vj=0.3 rs=100 bv=10) + +.options acct ++reltol=1e-3 abstol=1e-14 +.control +tran 0.1ns 60ns +plot v(1) v(2) v(3) +.endc + +* bjt driver - 19=input, 268=output, 20=vcc; wierd node numbers from +* the Raytheon file + +.subckt bjtdrvr 19 268 20 +q1 22 18 13 qmodn +q2 18 16 13 qmodn +qd2 21 9 0 qmodn +q4 14 14 0 qmodn +q3 16 15 14 qmodpd +q5 8 13 17 qmodn +q6 25 12 0 qmodn +q7 6 17 0 qmodpd +qd1 26 10 0 qmodn +q8 7 11 10 qmodn +q10 268 17 0 qmodpdmine +*q10 268 17 0 qmodpd +q9 7 10 268 qmodn + +d1 0 19 dmod1 +d2 18 19 dmod2 +d3 13 19 dmod +dq1 18 22 dmod +dq2 16 18 dmod +d502 9 21 dmod +dq3 15 16 dmod +d10 24 8 dmod +d4 15 6 dmod +dq6 12 25 dmod +dq7 17 6 dmod +dd1 17 10 dmod +d7 11 6 dmod +dd2 17 26 dmod +d9 23 6 dmod +dq8 11 7 dmod +d501 17 268 dmod +dq9 10 7 dmod +d14 20 27 dmod +d8 0 268 dmod + +r1 18 20 6k +r2 22 20 2.2k +r4 0 13 7k +rd1 9 13 2k +rd2 21 13 3k +r3 16 20 10k +r5 15 20 15k +r9 0 17 4k +r6 24 20 750 +r10 12 17 2k +r12 24 11 1.5k +r11 25 17 3k +r15 23 20 10k +r13 0 10 15k +r14 7 27 12 + +.ends bjtdrvr + +* subckt dioload - diode load: input=28, output=4, vcc=5 + +.subckt dioload 28 4 5 +*comment out everything in dioload except d5 and r503, and watch +* the difference in results obtained between a tran 0.1ns 20ns and +* a tran 0.01ns 20ns +c1 28 0 5pF +r503 0 4 5.55 +r4 0 28 120k +r5 1 5 7.5k + +d5 4 28 diod2 +d1 1 28 diod1 +d4 2 0 diod1 +d3 3 2 diod1 +d2 1 3 diod1 +.ends dioload + +* subckt lump - one RLC lump of the lossy line + +*10 segments per inch +.subckt lump 1 2 +*r1 1 3 0.02 +*c1 3 0 0.365pF +*l1 3 2 0.913nH + +l1 1 3 0.913nH +c1 2 0 0.365pF +r1 3 2 0.02 + +*r1 1 3 0.01 +*c1 3 0 0.1825pF +*l1 3 4 0.4565nH +*r2 4 5 0.01 +*c2 5 0 0.1825pF +*l2 5 2 0.4565nH + +*c1 1 0 0.365pF +*l1 1 2 0.913nH +.ends lump + +.subckt oneinch 1 2 +x1 1 3 lump +x2 3 4 lump +x3 4 5 lump +x4 5 6 lump +x5 6 7 lump +x6 7 8 lump +x7 8 9 lump +x8 9 10 lump +x9 10 11 lump +x10 11 2 lump +.ends oneinch + +.subckt fourinch 1 2 +x1 1 3 oneinch +x2 3 4 oneinch +x3 4 5 oneinch +x4 5 2 oneinch +.ends fourinch + +.subckt fiveinch 1 2 +x1 1 3 oneinch +x2 3 4 oneinch +x3 4 5 oneinch +x4 5 6 oneinch +x5 6 2 oneinch +.ends fiveinch + +.subckt twentyfourinch 1 2 +x1 1 3 fiveinch +x2 3 4 fiveinch +x3 4 5 fiveinch +x4 5 6 fiveinch +x5 6 2 fourinch +.ends twentyfourinch + +*modelling using R and lossless lines +*5 segments per inch +.model llfifth ltra nocontrol noprint rel=10 r=0 g=0 l=9.13e-9 ++c=3.65e-12 len=0.2 steplimit quadinterp +.subckt xlump 1 2 +o1 1 0 3 0 llfifth +r1 2 3 0.04 +.ends xlump + +.subckt xoneinch 1 2 +x1 1 3 xlump +x2 3 4 xlump +x3 4 5 xlump +x4 5 6 xlump +x5 6 2 xlump +*x5 6 7 xlump +*x6 7 8 xlump +*x7 8 9 xlump +*x8 9 10 xlump +*x9 10 11 xlump +*x10 11 2 xlump +.ends xoneinch + +.subckt xfourinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 2 xoneinch +.ends xfourinch + +.subckt xfiveinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 6 xoneinch +x5 6 2 xoneinch +.ends xfiveinch + +.subckt xtwentyfourinch 1 2 +x1 1 3 xfiveinch +x2 3 4 xfiveinch +x3 4 5 xfiveinch +x4 5 6 xfiveinch +x5 6 2 xfourinch +.ends xtwentyfourinch + +.end diff --git a/Windows/spice/examples/TransmissionLines/ltra5_1_line.sp b/Windows/spice/examples/TransmissionLines/ltra5_1_line.sp new file mode 100644 index 00000000..35459404 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra5_1_line.sp @@ -0,0 +1,530 @@ + Example 3 for interconnect simulation + +* From neug1, Mosaic aluminum lines. 2um thick, 11um wide. Assuming +* 10um above the ground. +* Material: aluminum; resistivity (sigma) = 2.74uohm-cm = 2.74e-8 ohm-m +* Dielectric: SiO2, dielectric constant (epsilon) =3.7 +* epsilon0 = 8.85e-12 MKS units +* mu0 = 4e-7*PI +* speed of light in free space = 1/sqrt(mu0*epsilon0) = 2.9986e8 MKS units +* +* Line parameter calculations: +* capacitance: parallel plate +* C = epsilon*epsilon0 * A / l +* C = 3.7*8.85e-12 * 11e-6 * 1(metre) / 10e-6 = 36.02e-12 F/m +* + 30% = 46.8e-12 F/m = 0.468pF/cm +* +* C_freespace = 46.8e-12/epsilon = 12.65e-12 F/m +* speed of light in free space v0 = 2.9986e8 = 1/sqrt(L0*C0) +* => L0 = 1/C0*v0^2 +* L0 = 1/(12.65e-12 * 8.9916e16) = 1/113.74e4 = 0.008792e-4 H/m +* = 0.8792 uH/m = 8.792nH/cm +* +* R = rho * l / A = 2.74e-8 * 1 / (11e-6*2e-6) = 1245.45 ohms/m +* = 12.45ohms/cm +* +* transmission line parameters: +* nominal z0 = sqrt(L/C) = 137 ohms +* td = sqrt(LC) = 64.14e-12 secs/cm = 0.064ns/cm +* +* + + +vcc vcc 0 5 + +v1 1 0 0v pulse(0 5 0.1ns 0.1ns 0.1ns 1ns 100ns) +rs 1 2 10 +xdrv 1 2 vcc bjtdrvr +xrcv 3 4 vcc bjtdrvr +xrcv 3 4 vcc dioload +d1 3 vcc diod +d2 0 3 diod +cl 3 0 1pF +o1 2 0 3 0 lline +*x1 2 3 sixteencm +x1 2 3 xonecm + +.model diod d +.model lline ltra rel=1.8 r=12.45 g=0 l=8.792e-9 c=0.468e-12 len=16 steplimit + +.control +* 1cm +* 2cm +* 4cm +* 6cm +* 8cm +* 10cm +* 12cm +*tran 0.001ns 15ns 0 0.1ns +* 24cm +tran 0.001ns 10ns 0 0.1ns +* onecm10 +*tran 0.001ns 10ns 0 0.01ns +plot v(1) v(2) v(3) +.endc + + +* 1. define the subckt r10 to be one tenth of the resistance per cm. +* 2. define the subckt onecm to be one of onecm10 (modelled using +* 10 segments), onecm8, onecm4, onecm2 and lump1. Then use +* the subckts onecm, fourcm, fivecm, tencm, twelvecm, +* twentyfourcm in the circuit. The line is modelled as rlc segments. +* 3. define the subckt xonecm to be one of xonecm10, xonecm8, +* xonecm4, xonecm2 and xlump1. Use the subckts xonecm, +* xfourcm, xfivecm, xtencm, xtwelvecm, xtwentyfourcm in the +* circuit. The line will be modelled as r-lossless lumps. + +.subckt xonecm 1 2 +*x1 1 2 xlump1 +x1 1 2 xonecm4 +.ends xonecm + +.subckt onecm 1 2 +*x1 1 2 lump1 +x1 1 2 onecm4 +.ends onecm + +.subckt r10 1 2 +r1 1 2 1.245 +.ends r10 + +* ECL driver and diode receiver models - from Raytheon + +.model qmodn npn(bf=100 rb=100 cje=0.09375pF cjc=0.28125pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpd npn(bf=100 rb=100 cje=0.08187pF cjc=0.2525pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpdmine npn(bf=100 rb=100 cje=0.08187pF cjc=0.05pF is=1e-12 ++pe=0.5 pc=0.5) + +.model dmod1 d(n=2.25 is=1.6399e-4 bv=10) + +.model dmod2 d + +.model dmod d(vj=0.3v) + +.model diod1 d(tt=0.75ns vj=0.6 rs=909 bv=10) + +.model diod2 d(tt=0.5ns vj=0.3 rs=100 bv=10) + +* bjt driver - 19=input, 268=output, 20=vcc; wierd node numbers from +* the Raytheon file + +.subckt bjtdrvr 19 268 20 +q1 22 18 13 qmodn +q2 18 16 13 qmodn +qd2 21 9 0 qmodn +q4 14 14 0 qmodn +q3 16 15 14 qmodpd +q5 8 13 17 qmodn +q6 25 12 0 qmodn +q7 6 17 0 qmodpd +qd1 26 10 0 qmodn +q8 7 11 10 qmodn +q10 268 17 0 qmodpdmine +*q10 268 17 0 qmodpd +q9 7 10 268 qmodn + +d1 0 19 dmod1 +d2 18 19 dmod2 +d3 13 19 dmod +dq1 18 22 dmod +dq2 16 18 dmod +d502 9 21 dmod +dq3 15 16 dmod +d10 24 8 dmod +d4 15 6 dmod +dq6 12 25 dmod +dq7 17 6 dmod +dd1 17 10 dmod +d7 11 6 dmod +dd2 17 26 dmod +d9 23 6 dmod +dq8 11 7 dmod +d501 17 268 dmod +dq9 10 7 dmod +d14 20 27 dmod +d8 0 268 dmod + +r1 18 20 6k +r2 22 20 2.2k +r4 0 13 7k +rd1 9 13 2k +rd2 21 13 3k +r3 16 20 10k +r5 15 20 15k +r9 0 17 4k +r6 24 20 750 +r10 12 17 2k +r12 24 11 1.5k +r11 25 17 3k +r15 23 20 10k +r13 0 10 15k +r14 7 27 12 + +.ends bjtdrvr + +* subckt dioload - diode load: input=28, output=4, vcc=5 + +.subckt dioload 28 4 5 +c1 28 0 5pF +r503 0 4 5.55 +r400 0 28 120k +r500 1 5 7.5k + +d5 4 28 diod2 +d1 1 28 diod1 +d4 2 0 diod1 +d3 3 2 diod1 +d2 1 3 diod1 +.ends dioload + +* End ECL driver and Diode receiver models from Raytheon + +*10 segments per cm +.subckt lump10 1 2 +l1 1 3 0.0.8792nH +c1 2 0 0.0468pF +x1 3 2 r10 +.ends lump10 + +*1 segment per cm +.subckt lump1 1 2 +l1 1 3 8.792nH +c1 2 0 0.468pF +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 8 r10 +x6 8 9 r10 +x7 9 10 r10 +x8 10 11 r10 +x9 11 12 r10 +x10 12 2 r10 +.ends lump1 + +*2 segments per cm +.subckt lump2 1 2 +l1 1 3 4.396nH +c1 2 0 0.234pF +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 2 r10 +.ends lump2 + +*4 segments per cm +.subckt lump4 1 2 +l1 1 3 2.198nH +c1 2 0 0.117pF +x1 3 4 r10 +x2 4 5 r10 +x3 5 2 r10 +x4 5 2 r10 +.ends lump4 + +*8 segments per cm +.subckt lump8 1 2 +l1 1 3 1.099nH +c1 2 0 0.0585pF +x1 3 4 r10 +x2 4 2 r10 +x3 4 2 r10 +x4 4 2 r10 +x5 4 2 r10 +.ends lump8 + +.subckt onecm10 1 2 +x1 1 3 lump10 +x2 3 4 lump10 +x3 4 5 lump10 +x4 5 6 lump10 +x5 6 7 lump10 +x6 7 8 lump10 +x7 8 9 lump10 +x8 9 10 lump10 +x9 10 11 lump10 +x10 11 2 lump10 +.ends onecm10 + +.subckt onecm8 1 2 +x1 1 3 lump8 +x2 3 4 lump8 +x3 4 5 lump8 +x4 5 6 lump8 +x5 6 7 lump8 +x6 7 8 lump8 +x7 8 9 lump8 +x8 9 2 lump8 +.ends onecm8 + +.subckt onecm4 1 2 +x1 1 3 lump4 +x2 3 4 lump4 +x3 4 5 lump4 +x4 5 2 lump4 +.ends onecm4 + +.subckt onecm2 1 2 +x1 1 3 lump2 +x2 3 2 lump2 +.ends onecm2 + +.subckt twocm 1 2 +x1 1 3 onecm +x2 3 2 onecm +.ends twocm + +.subckt threecm 1 2 +x1 1 3 onecm +x2 3 4 onecm +x3 4 2 onecm +.ends threecm + +.subckt fourcm 1 2 +x1 1 3 onecm +x2 3 4 onecm +x3 4 5 onecm +x4 5 2 onecm +.ends fourcm + +.subckt fivecm 1 2 +x1 1 3 onecm +x2 3 4 onecm +x3 4 5 onecm +x4 5 6 onecm +x5 6 2 onecm +.ends fivecm + +.subckt sixcm 1 2 +x1 1 3 fivecm +x2 3 2 onecm +.ends sixcm + +.subckt sevencm 1 2 +x1 1 3 sixcm +x2 3 2 onecm +.ends sevencm + +.subckt eightcm 1 2 +x1 1 3 sevencm +x2 3 2 onecm +.ends eightcm + +.subckt ninecm 1 2 +x1 1 3 eightcm +x2 3 2 onecm +.ends ninecm + +.subckt tencm 1 2 +x1 1 3 fivecm +x2 3 2 fivecm +.ends tencm + +.subckt elevencm 1 2 +x1 1 3 tencm +x2 3 2 onecm +.ends elevencm + +.subckt twelvecm 1 2 +x1 1 3 tencm +x2 3 4 onecm +x3 4 2 onecm +.ends twelvecm + +.subckt sixteencm 1 2 +x1 1 3 eightcm +x2 3 2 eightcm +.ends sixteencm + +.subckt twentyfourcm 1 2 +x1 1 3 twelvecm +x2 3 2 twelvecm +.ends twentyfourcm + + +*modelling using R and lossless lines +* 10 segments per cm +.model lless10 ltra nocontrol rel=10 r=0 g=0 l=8.792e-9 ++c=0.468e-12 len=0.1 steplimit quadinterp + +* 8 segments per cm +.model lless8 ltra nocontrol rel=10 r=0 g=0 l=8.792e-9 ++c=0.468e-12 len=0.125 steplimit quadinterp + +* 4 segments per cm +.model lless4 ltra nocontrol rel=10 r=0 g=0 l=8.792e-9 ++c=0.468e-12 len=0.25 steplimit quadinterp + +* 2 segments per cm +.model lless2 ltra nocontrol rel=10 r=0 g=0 l=8.792e-9 ++c=0.468e-12 len=0.5 steplimit quadinterp + +* 1 segment per cm +.model lless1 ltra nocontrol rel=10 r=0 g=0 l=8.792e-9 ++c=0.468e-12 len=1 steplimit quadinterp + +*10 segments per cm +.subckt xlump10 1 2 +o1 1 0 3 0 lless10 +x1 3 2 r10 +.ends xlump10 + +*1 segment per cm +.subckt xlump1 1 2 +o1 1 0 3 0 lless1 +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 8 r10 +x6 8 9 r10 +x7 9 10 r10 +x8 10 11 r10 +x9 11 12 r10 +x10 12 2 r10 +.ends xlump1 + +*2 segments per cm +.subckt xlump2 1 2 +o1 1 0 3 0 lless2 +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 2 r10 +.ends xlump2 + +*4 segments per cm +.subckt xlump4 1 2 +o1 1 0 3 0 lless4 +x1 3 4 r10 +x2 4 5 r10 +x3 5 2 r10 +x4 5 2 r10 +.ends xlump4 + +*8 segments per cm +.subckt xlump8 1 2 +o1 1 0 3 0 lless8 +x1 3 4 r10 +x2 4 2 r10 +x3 4 2 r10 +x4 4 2 r10 +x5 4 2 r10 +.ends xlump8 + +.subckt xonecm10 1 2 +x1 1 3 xlump10 +x2 3 4 xlump10 +x3 4 5 xlump10 +x4 5 6 xlump10 +x5 6 7 xlump10 +x6 7 8 xlump10 +x7 8 9 xlump10 +x8 9 10 xlump10 +x9 10 11 xlump10 +x10 11 2 xlump10 +.ends xonecm10 + +.subckt xonecm8 1 2 +x1 1 3 xlump8 +x2 3 4 xlump8 +x3 4 5 xlump8 +x4 5 6 xlump8 +x5 6 7 xlump8 +x6 7 8 xlump8 +x7 8 9 xlump8 +x8 9 2 xlump8 +.ends xonecm8 + +.subckt xonecm4 1 2 +x1 1 3 xlump4 +x2 3 4 xlump4 +x3 4 5 xlump4 +x4 5 2 xlump4 +.ends xonecm4 + +.subckt xonecm2 1 2 +x1 1 3 xlump2 +x2 3 2 xlump2 +.ends xonecm2 + + +.subckt xtwocm 1 2 +x1 1 3 xonecm +x2 3 2 xonecm +.ends xtwocm + +.subckt xthreecm 1 2 +x1 1 3 xonecm +x2 3 4 xonecm +x3 4 2 xonecm +.ends xthreecm + +.subckt xfourcm 1 2 +x1 1 3 xonecm +x2 3 4 xonecm +x3 4 5 xonecm +x4 5 2 xonecm +.ends xfourcm + +.subckt xfivecm 1 2 +x1 1 3 xonecm +x2 3 4 xonecm +x3 4 5 xonecm +x4 5 6 xonecm +x5 6 2 xonecm +.ends xfivecm + +.subckt xsixcm 1 2 +x1 1 3 xfivecm +x2 3 2 xonecm +.ends xsixcm + +.subckt xsevencm 1 2 +x1 1 3 xsixcm +x2 3 2 xonecm +.ends xsevencm + +.subckt xeightcm 1 2 +x1 1 3 xsevencm +x2 3 2 xonecm +.ends xeightcm + +.subckt xninecm 1 2 +x1 1 3 xeightcm +x2 3 2 xonecm +.ends xninecm + +.subckt xtencm 1 2 +x1 1 3 xfivecm +x2 3 2 xfivecm +.ends xtencm + +.subckt xelevencm 1 2 +x1 1 3 xtencm +x2 3 2 xonecm +.ends xelevencm + +.subckt xtwelvecm 1 2 +x1 1 3 xtencm +x2 3 4 xonecm +x3 4 2 xonecm +.ends xtwelvecm + +.subckt xsixteencm 1 2 +x1 1 3 xeightcm +x2 3 2 xeightcm +.ends xsixteencm + +.subckt xtwentyfourcm 1 2 +x1 1 3 xtwelvecm +x2 3 2 xtwelvecm +.ends xtwentyfourcm + +.end diff --git a/Windows/spice/examples/TransmissionLines/ltra6_2_line.sp b/Windows/spice/examples/TransmissionLines/ltra6_2_line.sp new file mode 100644 index 00000000..45279129 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra6_2_line.sp @@ -0,0 +1,394 @@ +BJTdriver -- 2in st. lin -- 20in coupled line LTRA -- 2in st line -- DiodeCircuit + +* This unclassified circuit is from Raytheon, courtesy Gerry Marino. +* +* _______ +* -------- 2in _________________ 2in | | +* | BJT |______| |______|Diode| +* | |------| |------| | +* | Drvr | line | 2-wire | line |rcvr.| +* -------- | coupled | |_____| +* | transmission | +* |-/\/\/\/\----| line |-------\/\/\/\/\----| +* | 50ohms | | 50ohms | +* | | | | +* Ground ----------------- Ground +* +* +* Each inch of the lossy line is modelled by 10 LRC lumps in the +* Raytheon model. + +* The line parameters (derived from the Raytheon input file) are: +* L = 9.13nH per inch +* C = 3.65pF per inch +* R = 0.2 ohms per inch +* K = 0.482 [coupling coefficient; K = M/sqrt(L1*L2)] +* Cc = 1.8pF per inch +* +* coupled ltra model generated using the standalone program +* multi_decomp + +* the circuit + +v1 1 0 0v pulse(0 4 1ns 1ns 1ns 20ns 40ns) + +vcc 10 0 5v + +* series termination +*x1 1 oof 10 bjtdrvr +*rseries oof 2 50 + +x1 1 2 10 bjtdrvr +rt1 3 0 50 + + +* convolution model +x2 2 3 4 5 conv2wetcmodel + +* rlc segments model +*x2 2 3 4 5 rlc2wetcmodel + +x3 4 dioload +rt2 5 0 50 + + + +.model qmodn npn(bf=100 rb=100 cje=0.09375pF cjc=0.28125pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpd npn(bf=100 rb=100 cje=0.08187pF cjc=0.2525pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpdmine npn(bf=100 rb=100 cje=0.08187pF cjc=0.05pF is=1e-12 ++pe=0.5 pc=0.5) + +.model dmod1 d(n=2.25 is=1.6399e-4 bv=10) + +.model dmod2 d + +.model dmod d(vj=0.3v) + +.model diod1 d(tt=0.75ns vj=0.6 rs=909 bv=10) + +.model diod2 d(tt=0.5ns vj=0.3 rs=100 bv=10) + +.options acct reltol=1e-3 abstol=1e-12 +.control +tran 0.1ns 60ns +plot v(2) v(4) v(5) +.endc + +* bjt driver - 19=input, 268=output, 20=vcc; wierd node numbers from +* the Raytheon file + +.subckt bjtdrvr 19 268 20 +q1 22 18 13 qmodn +q2 18 16 13 qmodn +qd2 21 9 0 qmodn +q4 14 14 0 qmodn +q3 16 15 14 qmodpd +q5 8 13 17 qmodn +q6 25 12 0 qmodn +q7 6 17 0 qmodpd +qd1 26 10 0 qmodn +q8 7 11 10 qmodn +*q10 268 17 0 qmodpd +q10 268 17 0 qmodpdmine +q9 7 10 268 qmodn + +d1 0 19 dmod1 +d2 18 19 dmod2 +d3 13 19 dmod +dq1 18 22 dmod +dq2 16 18 dmod +d502 9 21 dmod +dq3 15 16 dmod +d10 24 8 dmod +d4 15 6 dmod +dq6 12 25 dmod +dq7 17 6 dmod +dd1 17 10 dmod +d7 11 6 dmod +dd2 17 26 dmod +d9 23 6 dmod +dq8 11 7 dmod +d501 17 268 dmod +dq9 10 7 dmod +d14 20 27 dmod +d8 0 268 dmod + +r1 18 20 6k +r2 22 20 2.2k +r4 0 13 7k +rd1 9 13 2k +rd2 21 13 3k +r3 16 20 10k +r5 15 20 15k +r9 0 17 4k +r6 24 20 750 +r10 12 17 2k +r12 24 11 1.5k +r11 25 17 3k +r15 23 20 10k +r13 0 10 15k +r14 7 27 12 + +.ends bjtdrvr + +* subckt dioload - diode load: input=28, output=4, vcc=5 + +.subckt dioload 28 +*comment out everything in dioload except d5 and r503, and watch +* the difference in results obtained between a tran 0.1ns 20ns and +* a tran 0.01ns 20ns +vccint 5 0 5v + +c1 28 0 5pF +r503 0 4 5.55 +r4 0 28 120k +r5 1 5 7.5k + +d5 4 28 diod2 +d1 1 28 diod1 +d4 2 0 diod1 +d3 3 2 diod1 +d2 1 3 diod1 +.ends dioload + +* subckt rlclump - one RLC lump of the lossy line + +.subckt rlclump 1 2 +*r1 1 3 0.02 +*c1 3 0 0.365pF +*l1 3 2 0.913nH + +l1 1 3 0.913nH +c1 2 0 0.365pF +r1 3 2 0.02 + +*r1 1 3 0.01 +*c1 3 0 0.1825pF +*l1 3 4 0.4565nH +*r2 4 5 0.01 +*c2 5 0 0.1825pF +*l2 5 2 0.4565nH + +*c1 1 0 0.365pF +*l1 1 2 0.913nH +.ends lump + +.subckt rlconeinch 1 2 +x1 1 3 rlclump +x2 3 4 rlclump +x3 4 5 rlclump +x4 5 6 rlclump +x5 6 7 rlclump +x6 7 8 rlclump +x7 8 9 rlclump +x8 9 10 rlclump +x9 10 11 rlclump +x10 11 2 rlclump +.ends rlconeinch + +.subckt rlctwoinch 1 2 +x1 1 3 rlconeinch +x2 3 2 rlconeinch +.ends rlctwoinch + +.subckt rlcfourinch 1 2 +x1 1 3 rlconeinch +x2 3 4 rlconeinch +x3 4 5 rlconeinch +x4 5 2 rlconeinch +.ends rlcfourinch + +.subckt rlcfiveinch 1 2 +x1 1 3 rlconeinch +x2 3 4 rlconeinch +x3 4 5 rlconeinch +x4 5 6 rlconeinch +x5 6 2 rlconeinch +.ends rlcfiveinch + +.subckt rlctwentyrlcfourinch 1 2 +x1 1 3 rlcfiveinch +x2 3 4 rlcfiveinch +x3 4 5 rlcfiveinch +x4 5 6 rlcfiveinch +x5 6 2 rlcfourinch +.ends rlctwentyrlcfourinch + +.subckt rlclumpstub A B C D +x1 A int1 rlcfiveinch +x2 int1 int2 rlcfiveinch +x3 int2 1 rlcfiveinch +x4 1 2 rlcfourinch +x5 1 int3 rlcfiveinch +x6 int3 B rlconeinch +x7 2 C rlcfiveinch +x8 2 D rlcfourinch +.ends rlclumpstub + +.subckt ltrastub A B C D +o1 A 0 1 0 lline15in +o2 1 0 B 0 lline6in +o3 1 0 2 0 lline4in +o4 2 0 C 0 lline5in +o5 2 0 D 0 lline4in +.ends ltrastub + +*modelling using R and lossless lines + +*5 segments per inch +.model llfifth ltra nocontrol rel=10 r=0 g=0 l=9.13e-9 ++c=3.65e-12 len=0.2 steplimit quadinterp + +.subckt xlump 1 2 +o1 1 0 3 0 llfifth +r1 2 3 0.04 +.ends xlump + +.subckt xoneinch 1 2 +x1 1 3 xlump +x2 3 4 xlump +x3 4 5 xlump +x4 5 6 xlump +x5 6 2 xlump +*x5 6 7 xlump +*x6 7 8 xlump +*x7 8 9 xlump +*x8 9 10 xlump +*x9 10 11 xlump +*x10 11 2 xlump +.ends xoneinch + +.subckt xFourinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 2 xoneinch +.ends xfourinch + +.subckt xfiveinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 6 xoneinch +x5 6 2 xoneinch +.ends xfiveinch + +.subckt xlumpstub A B C D +x1 A int1 xfiveinch +x2 int1 int2 xfiveinch +x3 int2 1 xfiveinch +x4 1 2 xfourinch +x5 1 int3 xfiveinch +x6 int3 B xoneinch +x7 2 C xfiveinch +x8 2 D xfourinch +.ends xlumpstub + +* modelling a 2 wire coupled system using RLC lumps +* 10 segments per inch +* +* 1---xxxxx----2 +* 3---xxxxx----4 + +.subckt rlc2wlump 1 3 2 4 +l1 1 5 0.913nH +c1 2 0 0.365pF +r1 5 2 0.02 +l2 3 6 0.913nH +c2 4 0 0.365pF +r2 6 4 0.02 +cmut 2 4 0.18pF +k12 l1 l2 0.482 +.ends rlc2wlump + +.subckt rlc2woneinch 1 2 3 4 +x1 1 2 5 6 rlc2wlump +x2 5 6 7 8 rlc2wlump +x3 7 8 9 10 rlc2wlump +x4 9 10 11 12 rlc2wlump +x5 11 12 13 14 rlc2wlump +x6 13 14 15 16 rlc2wlump +x7 15 16 17 18 rlc2wlump +x8 17 18 19 20 rlc2wlump +x9 19 20 21 22 rlc2wlump +x10 21 22 3 4 rlc2wlump +.ends rlc2woneinch + +.subckt rlc2wfiveinch 1 2 3 4 +x1 1 2 5 6 rlc2woneinch +x2 5 6 7 8 rlc2woneinch +x3 7 8 9 10 rlc2woneinch +x4 9 10 11 12 rlc2woneinch +x5 11 12 3 4 rlc2woneinch +.ends rlc2wfiveinch + +.subckt rlc2wtwentyinch 1 2 3 4 +x1 1 2 5 6 rlc2wfiveinch +x2 5 6 7 8 rlc2wfiveinch +x3 7 8 9 10 rlc2wfiveinch +x4 9 10 3 4 rlc2wfiveinch +.ends rlc2wtwentyinch + +.subckt rlc2wetcmodel 1 2 3 4 +x1 1 5 rlctwoinch +x2 5 2 6 4 rlc2wtwentyinch +x3 6 3 rlctwoinch +.ends rlc2wetcmodel + +* Subcircuit conv2wtwentyinch +* conv2wtwentyinch is a subcircuit that models a 2-conductor transmission line with +* the following parameters: l=9.13e-09, c=3.65e-12, r=0.2, g=0, +* inductive_coeff_of_coupling k=0.482, inter-line capacitance cm=1.8e-12, +* length=20. Derived parameters are: lm=4.40066e-09, ctot=5.45e-12. +* +* It is important to note that the model is a simplified one - the +* following assumptions are made: 1. The self-inductance l, the +* self-capacitance ctot (note: not c), the series resistance r and the +* parallel capacitance g are the same for all lines, and 2. Each line +* is coupled only to the two lines adjacent to it, with the same +* coupling parameters cm and lm. The first assumption imply that edge +* effects have to be neglected. The utility of these assumptions is +* that they make the sL+R and sC+G matrices symmetric, tridiagonal and +* Toeplitz, with useful consequences. +* +* It may be noted that a symmetric two-conductor line will be +* accurately represented by this model. + +* Lossy line models +.model mod1_conv2wtwentyinch ltra rel=1.2 nocontrol r=0.2 l=4.72933999088e-09 g=0 c=7.25000000373e-12 len=20 +.model mod2_conv2wtwentyinch ltra rel=1.2 nocontrol r=0.2 l=1.35306599818e-08 g=0 c=3.65000000746e-12 len=20 + +* subcircuit m_conv2wtwentyinch - modal transformation network for conv2wtwentyinch +.subckt m_conv2wtwentyinch 1 2 3 4 +v1 5 0 0v +v2 6 0 0v +f1 0 3 v1 0.707106779721 +f2 0 3 v2 -0.707106782652 +f3 0 4 v1 0.707106781919 +f4 0 4 v2 0.707106780454 +e1 7 5 3 0 0.707106780454 +e2 1 7 4 0 0.707106782652 +e3 8 6 3 0 -0.707106781919 +e4 2 8 4 0 0.707106779721 +.ends m_conv2wtwentyinch + +* Subckt conv2wtwentyinch +.subckt conv2wtwentyinch 1 2 3 4 +x1 1 2 5 6 m_conv2wtwentyinch +o1 5 0 7 0 mod1_conv2wtwentyinch +o2 6 0 8 0 mod2_conv2wtwentyinch +x2 3 4 7 8 m_conv2wtwentyinch +.ends conv2wtwentyinch + +.model convtwoinch ltra r=0.2 l=9.13e-9 c=3.65e-12 len=2.0 rel=1.2 nocontrol +.subckt conv2wetcmodel 1 2 3 4 +o1 1 0 5 0 convtwoinch +x1 5 2 6 4 conv2wtwentyinch +o2 6 0 3 0 convtwoinch +.ends conv2wetcmodel + +.end diff --git a/Windows/spice/examples/TransmissionLines/ltra7_4_line.sp b/Windows/spice/examples/TransmissionLines/ltra7_4_line.sp new file mode 100644 index 00000000..7be4615a --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/ltra7_4_line.sp @@ -0,0 +1,113 @@ +6.3inch 4 lossy lines LTRA model -- R load + +Ra 1 2 1K +Rb 0 3 1K +Rc 0 4 1K +Rd 0 5 1K +Re 6 0 1Meg +Rf 7 0 1Meg +Rg 8 0 1Meg +Rh 9 0 1Meg + + +* +* Subcircuit test +* test is a subcircuit that models a 4-conductor transmission line with +* the following parameters: l=9e-09, c=2.9e-13, r=0.3, g=0, +* inductive_coeff_of_coupling k=0.6, inter-line capacitance cm=3e-14, +* length=6.3. Derived parameters are: lm=5.4e-09, ctot=3.5e-13. +* +* It is important to note that the model is a simplified one - the +* following assumptions are made: 1. The self-inductance l, the +* self-capacitance ctot (note: not c), the series resistance r and the +* parallel capacitance g are the same for all lines, and 2. Each line +* is coupled only to the two lines adjacent to it, with the same +* coupling parameters cm and lm. The first assumption implies that edge +* effects have to be neglected. The utility of these assumptions is +* that they make the sL+R and sC+G matrices symmetric, tridiagonal and +* Toeplitz, with useful consequences (see "Efficient Transient +* Simulation of Lossy Interconnect", by J.S. Roychowdhury and +* D.O Pederson, Proc. DAC 91). + +* It may be noted that a symmetric two-conductor line is +* represented accurately by this model. + +* Subckt node convention: +* +* |--------------------------| +* 1-----| |-----n+1 +* 2-----| |-----n+2 +* : | n-wire multiconductor | : +* : | line | : +* n-1-----|(node 0=common gnd plane) |-----2n-1 +* n-----| |-----2n +* |--------------------------| + + +* Lossy line models +.model mod1_test ltra rel=1.2 nocontrol r=0.3 l=2.62616456193e-10 g=0 c=3.98541019688e-13 len=6.3 +.model mod2_test ltra rel=1.2 nocontrol r=0.3 l=5.662616446e-09 g=0 c=3.68541019744e-13 len=6.3 +.model mod3_test ltra rel=1.2 nocontrol r=0.3 l=1.23373835171e-08 g=0 c=3.3145898046e-13 len=6.3 +.model mod4_test ltra rel=1.2 nocontrol r=0.3 l=1.7737383521e-08 g=0 c=3.01458980439e-13 len=6.3 + +* subcircuit m_test - modal transformation network for test +.subckt m_test 1 2 3 4 5 6 7 8 +v1 9 0 0v +v2 10 0 0v +v3 11 0 0v +v4 12 0 0v +f1 0 5 v1 0.371748033738 +f2 0 5 v2 -0.601500954587 +f3 0 5 v3 0.601500954587 +f4 0 5 v4 -0.371748036544 +f5 0 6 v1 0.60150095443 +f6 0 6 v2 -0.371748035044 +f7 0 6 v3 -0.371748030937 +f8 0 6 v4 0.601500957402 +f9 0 7 v1 0.601500954079 +f10 0 7 v2 0.37174803072 +f11 0 7 v3 -0.371748038935 +f12 0 7 v4 -0.601500955482 +f13 0 8 v1 0.371748035626 +f14 0 8 v2 0.601500956073 +f15 0 8 v3 0.601500954504 +f16 0 8 v4 0.371748032386 +e1 13 9 5 0 0.371748033909 +e2 14 13 6 0 0.601500954587 +e3 15 14 7 0 0.601500955639 +e4 1 15 8 0 0.371748036664 +e5 16 10 5 0 -0.60150095443 +e6 17 16 6 0 -0.371748035843 +e7 18 17 7 0 0.371748032386 +e8 2 18 8 0 0.601500957319 +e9 19 11 5 0 0.601500955131 +e10 20 19 6 0 -0.371748032169 +e11 21 20 7 0 -0.371748037896 +e12 3 21 8 0 0.601500954513 +e13 22 12 5 0 -0.371748035746 +e14 23 22 6 0 0.60150095599 +e15 24 23 7 0 -0.601500953534 +e16 4 24 8 0 0.371748029317 +.ends m_test + +* Subckt test +.subckt test 1 2 3 4 5 6 7 8 +x1 1 2 3 4 9 10 11 12 m_test +o1 9 0 13 0 mod1_test +o2 10 0 14 0 mod2_test +o3 11 0 15 0 mod3_test +o4 12 0 16 0 mod4_test +x2 5 6 7 8 13 14 15 16 m_test +.ends test +* +x1 2 3 4 5 6 7 8 9 test +* +* +VS1 1 0 PWL(15.9NS 0.0 16.1Ns 5.0 31.9Ns 5.0 32.1Ns 0.0) + +.control +TRAN 0.2NS 50NS +plot v(1) v(2) v(6) v(7) v(8) v(9) +.endc +* +.END diff --git a/Windows/spice/examples/TransmissionLines/txl1_1_line.sp b/Windows/spice/examples/TransmissionLines/txl1_1_line.sp new file mode 100644 index 00000000..fdbec1ae --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/txl1_1_line.sp @@ -0,0 +1,18 @@ +MOSdriver -- lossy line TXL model -- C load +m5 0 168 2 0 mn0p9 w = 18.0u l=0.9u +m6 1 168 2 1 mp1p0 w = 36.0u l=1.0u +CN2 2 0 0.025398e-12 +CN3 3 0 0.007398e-12 +y1 2 0 3 0 ymod +vdd 1 0 dc 5.0 +VS 168 0 PULSE (0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS ) +.control +TRAN 0.2N 47N 0 0.1N +plot v(2) v(3) ylimit -0.5 5 +.endc +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL ymod txl R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 +.end diff --git a/Windows/spice/examples/TransmissionLines/txl2_3_line.sp b/Windows/spice/examples/TransmissionLines/txl2_3_line.sp new file mode 100644 index 00000000..41b54996 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/txl2_3_line.sp @@ -0,0 +1,26 @@ +MOSdriver -- 3 lossy lines TXL model -- C load +m5 0 168 2 0 mn0p9 w = 18.0u l=0.9u +m6 1 168 2 1 mp1p0 w = 36.0u l=1.0u +m1 0 3 4 0 mn0p9 w = 18.0u l=0.9u +m2 1 3 4 1 mp1p0 w = 36.0u l=1.0u +CN2 2 0 0.025398e-12 +CN3 3 0 0.007398e-12 +CN4 4 0 0.025398e-12 +CN5 5 0 0.007398e-12 +CN6 6 0 0.007398e-12 +CN7 168 0 0.007398e-12 +y1 2 0 3 0 ymod +y2 4 0 5 0 ymod +y3 6 0 168 0 ymod +vdd 1 0 dc 5.0 +VS 168 0 PULSE (0 5 15.9NS 0.2NS 0.2NS 15.8NS 32NS ) +.control +TRAN 0.2N 47N 0 0.1N +plot v(2) v(3) v(4) v(5) v(6) +.endc +.MODEL mn0p9 NMOS VTO=0.8 KP=48U GAMMA=0.30 PHI=0.55 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL mp1p0 PMOS VTO=-0.8 KP=21U GAMMA=0.45 PHI=0.61 ++LAMBDA=0.00 CGSO=0 CGDO=0 CJ=0 CJSW=0 TOX=18000N LD=0.0U +.MODEL ymod txl R=12.45 L=8.972e-9 G=0 C=0.468e-12 length=16 +.end diff --git a/Windows/spice/examples/TransmissionLines/txl3_1_line.sp b/Windows/spice/examples/TransmissionLines/txl3_1_line.sp new file mode 100644 index 00000000..466c2591 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/txl3_1_line.sp @@ -0,0 +1,236 @@ + BJTdriver -- 24inch lossy line TXL model -- DiodeCircuit + +* This unclassified circuit is from Raytheon, courtesy Gerry Marino. +* It consists of a BJT driver connected by a 24 inch lossy line to a +* passive load consisting mostly of diodes. Each inch +* of the lossy line is modelled by 10 LRC lumps in the Raytheon +* model. + +* The line parameters (derived from the Raytheon input file) are: +* L = 9.13nH per inch +* C = 3.65pF per inch +* R = 0.2 ohms per inch + +* the circuit +v1 1 0 0v pulse(0 4 1ns 1ns 1ns 20ns 40ns) +vcc 10 0 5v +*rseries 1 2 5 +x1 1 2 10 bjtdrvr +*t1 2 0 3 0 z0=50.0136 td=4.38119ns rel=10 +y2 2 0 3 0 ymod1 +*x2 2 3 oneinch +*x2 100 101 twentyfourinch +*x2 100 101 xtwentyfourinch +vtest1 2 100 0 +vtest2 101 3 0 +x3 3 4 10 dioload +*rl 3 0 5 +*dl 0 3 diod2 + +.model ymod1 txl r=0.2 g=0 l=9.13e-9 c=3.65e-12 length=24 + +.model qmodn npn(bf=100 rb=100 cje=0.09375pF cjc=0.28125pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpd npn(bf=100 rb=100 cje=0.08187pF cjc=0.2525pF is=1e-12 ++pe=0.5 pc=0.5) +.model qmodpdmine npn(bf=100 rb=100 cje=0.08187pF cjc=0.05pF is=1e-12 ++pe=0.5 pc=0.5) + +.model dmod1 d(n=2.25 is=1.6399e-4 bv=10) + +.model dmod2 d + +.model dmod d(vj=0.3v) + +.model diod1 d(tt=0.75ns vj=0.6 rs=909 bv=10) + +.model diod2 d(tt=0.5ns vj=0.3 rs=100 bv=10) + +.options acct ++reltol=1e-3 abstol=1e-14 +.control +tran 0.1ns 60ns 0 0.5ns +plot v(1) v(2) v(3) +.endc + +* bjt driver - 19=input, 268=output, 20=vcc; wierd node numbers from +* the Raytheon file + +.subckt bjtdrvr 19 268 20 +q1 22 18 13 qmodn +q2 18 16 13 qmodn +qd2 21 9 0 qmodn +q4 14 14 0 qmodn +q3 16 15 14 qmodpd +q5 8 13 17 qmodn +q6 25 12 0 qmodn +q7 6 17 0 qmodpd +qd1 26 10 0 qmodn +q8 7 11 10 qmodn +q10 268 17 0 qmodpdmine +*q10 268 17 0 qmodpd +q9 7 10 268 qmodn + +d1 0 19 dmod1 +d2 18 19 dmod2 +d3 13 19 dmod +dq1 18 22 dmod +dq2 16 18 dmod +d502 9 21 dmod +dq3 15 16 dmod +d10 24 8 dmod +d4 15 6 dmod +dq6 12 25 dmod +dq7 17 6 dmod +dd1 17 10 dmod +d7 11 6 dmod +dd2 17 26 dmod +d9 23 6 dmod +dq8 11 7 dmod +d501 17 268 dmod +dq9 10 7 dmod +d14 20 27 dmod +d8 0 268 dmod + +r1 18 20 6k +r2 22 20 2.2k +r4 0 13 7k +rd1 9 13 2k +rd2 21 13 3k +r3 16 20 10k +r5 15 20 15k +r9 0 17 4k +r6 24 20 750 +r10 12 17 2k +r12 24 11 1.5k +r11 25 17 3k +r15 23 20 10k +r13 0 10 15k +r14 7 27 12 + +.ends bjtdrvr + +* subckt dioload - diode load: input=28, output=4, vcc=5 + +.subckt dioload 28 4 5 +*comment out everything in dioload except d5 and r503, and watch +* the difference in results obtained between a tran 0.1ns 20ns and +* a tran 0.01ns 20ns +c1 28 0 5pF +r503 0 4 5.55 +r4 0 28 120k +r5 1 5 7.5k + +d5 4 28 diod2 +d1 1 28 diod1 +d4 2 0 diod1 +d3 3 2 diod1 +d2 1 3 diod1 +.ends dioload + +* subckt lump - one RLC lump of the lossy line + +*10 segments per inch +.subckt lump 1 2 +*r1 1 3 0.02 +*c1 3 0 0.365pF +*l1 3 2 0.913nH + +l1 1 3 0.913nH +c1 2 0 0.365pF +r1 3 2 0.02 + +*r1 1 3 0.01 +*c1 3 0 0.1825pF +*l1 3 4 0.4565nH +*r2 4 5 0.01 +*c2 5 0 0.1825pF +*l2 5 2 0.4565nH + +*c1 1 0 0.365pF +*l1 1 2 0.913nH +.ends lump + +.subckt oneinch 1 2 +x1 1 3 lump +x2 3 4 lump +x3 4 5 lump +x4 5 6 lump +x5 6 7 lump +x6 7 8 lump +x7 8 9 lump +x8 9 10 lump +x9 10 11 lump +x10 11 2 lump +.ends oneinch + +.subckt fourinch 1 2 +x1 1 3 oneinch +x2 3 4 oneinch +x3 4 5 oneinch +x4 5 2 oneinch +.ends fourinch + +.subckt fiveinch 1 2 +x1 1 3 oneinch +x2 3 4 oneinch +x3 4 5 oneinch +x4 5 6 oneinch +x5 6 2 oneinch +.ends fiveinch + +.subckt twentyfourinch 1 2 +x1 1 3 fiveinch +x2 3 4 fiveinch +x3 4 5 fiveinch +x4 5 6 fiveinch +x5 6 2 fourinch +.ends twentyfourinch + +*modelling using R and lossless lines +*5 segments per inch +.model ymod2 txl r=0 g=0 l=9.13e-9 c=3.65e-12 length=0.2 +.subckt xlump 1 2 +y1 1 0 3 0 ymod2 +r1 2 3 0.04 +.ends xlump + +.subckt xoneinch 1 2 +x1 1 3 xlump +x2 3 4 xlump +x3 4 5 xlump +x4 5 6 xlump +x5 6 2 xlump +*x5 6 7 xlump +*x6 7 8 xlump +*x7 8 9 xlump +*x8 9 10 xlump +*x9 10 11 xlump +*x10 11 2 xlump +.ends xoneinch + +.subckt xfourinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 2 xoneinch +.ends xfourinch + +.subckt xfiveinch 1 2 +x1 1 3 xoneinch +x2 3 4 xoneinch +x3 4 5 xoneinch +x4 5 6 xoneinch +x5 6 2 xoneinch +.ends xfiveinch + +.subckt xtwentyfourinch 1 2 +x1 1 3 xfiveinch +x2 3 4 xfiveinch +x3 4 5 xfiveinch +x4 5 6 xfiveinch +x5 6 2 xfourinch +.ends xtwentyfourinch + +.end diff --git a/Windows/spice/examples/TransmissionLines/txl4_1_line.sp b/Windows/spice/examples/TransmissionLines/txl4_1_line.sp new file mode 100644 index 00000000..91586479 --- /dev/null +++ b/Windows/spice/examples/TransmissionLines/txl4_1_line.sp @@ -0,0 +1,523 @@ + Example 3 for interconnect simulation + +* From neug1, Mosaic aluminum lines. 2um thick, 11um wide. Assuming +* 10um above the ground. +* Material: aluminum; resistivity (sigma) = 2.74uohm-cm = 2.74e-8 ohm-m +* Dielectric: SiO2, dielectric constant (epsilon) =3.7 +* epsilon0 = 8.85e-12 MKS units +* mu0 = 4e-7*PI +* speed of light in free space = 1/sqrt(mu0*epsilon0) = 2.9986e8 MKS units +* +* Line parameter calculations: +* capacitance: parallel plate +* C = epsilon*epsilon0 * A / l +* C = 3.7*8.85e-12 * 11e-6 * 1(metre) / 10e-6 = 36.02e-12 F/m +* + 30% = 46.8e-12 F/m = 0.468pF/cm +* +* C_freespace = 46.8e-12/epsilon = 12.65e-12 F/m +* speed of light in free space v0 = 2.9986e8 = 1/sqrt(L0*C0) +* => L0 = 1/C0*v0^2 +* L0 = 1/(12.65e-12 * 8.9916e16) = 1/113.74e4 = 0.008792e-4 H/m +* = 0.8792 uH/m = 8.792nH/cm +* +* R = rho * l / A = 2.74e-8 * 1 / (11e-6*2e-6) = 1245.45 ohms/m +* = 12.45ohms/cm +* +* transmission line parameters: +* nominal z0 = sqrt(L/C) = 137 ohms +* td = sqrt(LC) = 64.14e-12 secs/cm = 0.064ns/cm +* +* + + +vcc vcc 0 5 +v1 1 0 0v pulse(0 5 0.1ns 0.1ns 0.1ns 1ns 100ns) +rs 1 2 10 +xdrv 1 2 vcc bjtdrvr +xrcv 3 4 vcc bjtdrvr +xrcv 3 4 vcc dioload +d1 3 vcc diod +d2 0 3 diod +cl 3 0 1pF +y1 2 0 3 0 yline +*x1 2 3 sixteencm +x1 2 3 xonecm + +.model diod d +.model yline txl r=12.45 g=0 l=8.792e-9 c=0.468e-12 length=16 + +.control +* 1cm +* 2cm +* 4cm +* 6cm +* 8cm +* 10cm +* 12cm +*tran 0.001ns 15ns 0 0.1ns +* 24cm +tran 0.001ns 10ns 0 0.1ns +* onecm10 +*tran 0.001ns 10ns 0 0.01ns +plot v(1) v(2) v(3) +.endc + + +* 1. define the subckt r10 to be one tenth of the resistance per cm. +* 2. define the subckt onecm to be one of onecm10 (modelled using +* 10 segments), onecm8, onecm4, onecm2 and lump1. Then use +* the subckts onecm, fourcm, fivecm, tencm, twelvecm, +* twentyfourcm in the circuit. The line is modelled as rlc segments. +* 3. define the subckt xonecm to be one of xonecm10, xonecm8, +* xonecm4, xonecm2 and xlump1. Use the subckts xonecm, +* xfourcm, xfivecm, xtencm, xtwelvecm, xtwentyfourcm in the +* circuit. The line will be modelled as r-lossless lumps. + +.subckt xonecm 1 2 +*x1 1 2 xlump1 +x1 1 2 xonecm4 +.ends xonecm + +.subckt onecm 1 2 +*x1 1 2 lump1 +x1 1 2 onecm4 +.ends onecm + +.subckt r10 1 2 +r1 1 2 1.245 +.ends r10 + +* ECL driver and diode receiver models - from Raytheon + +.model qmodn npn(bf=100 rb=100 cje=0.09375pF cjc=0.28125pF is=1e-12 ++pe=0.5 pc=0.5) + +.model qmodpd npn(bf=100 rb=100 cje=0.08187pF cjc=0.2525pF is=1e-12 ++pe=0.5 pc=0.5) +.model qmodpdmine npn(bf=100 rb=100 cje=0.08187pF cjc=0.05pF is=1e-12 ++pe=0.5 pc=0.5) + +.model dmod1 d(n=2.25 is=1.6399e-4 bv=10) + +.model dmod2 d + +.model dmod d(vj=0.3v) + +.model diod1 d(tt=0.75ns vj=0.6 rs=909 bv=10) + +.model diod2 d(tt=0.5ns vj=0.3 rs=100 bv=10) + +* bjt driver - 19=input, 268=output, 20=vcc; wierd node numbers from +* the Raytheon file + +.subckt bjtdrvr 19 268 20 +q1 22 18 13 qmodn +q2 18 16 13 qmodn +qd2 21 9 0 qmodn +q4 14 14 0 qmodn +q3 16 15 14 qmodpd +q5 8 13 17 qmodn +q6 25 12 0 qmodn +q7 6 17 0 qmodpd +qd1 26 10 0 qmodn +q8 7 11 10 qmodn +q10 268 17 0 qmodpdmine +*q10 268 17 0 qmodpd +q9 7 10 268 qmodn + +d1 0 19 dmod1 +d2 18 19 dmod2 +d3 13 19 dmod +dq1 18 22 dmod +dq2 16 18 dmod +d502 9 21 dmod +dq3 15 16 dmod +d10 24 8 dmod +d4 15 6 dmod +dq6 12 25 dmod +dq7 17 6 dmod +dd1 17 10 dmod +d7 11 6 dmod +dd2 17 26 dmod +d9 23 6 dmod +dq8 11 7 dmod +d501 17 268 dmod +dq9 10 7 dmod +d14 20 27 dmod +d8 0 268 dmod + +r1 18 20 6k +r2 22 20 2.2k +r4 0 13 7k +rd1 9 13 2k +rd2 21 13 3k +r3 16 20 10k +r5 15 20 15k +r9 0 17 4k +r6 24 20 750 +r10 12 17 2k +r12 24 11 1.5k +r11 25 17 3k +r15 23 20 10k +r13 0 10 15k +r14 7 27 12 + +.ends bjtdrvr + +* subckt dioload - diode load: input=28, output=4, vcc=5 + +.subckt dioload 28 4 5 +c1 28 0 5pF +r503 0 4 5.55 +r400 0 28 120k +r500 1 5 7.5k + +d5 4 28 diod2 +d1 1 28 diod1 +d4 2 0 diod1 +d3 3 2 diod1 +d2 1 3 diod1 +.ends dioload + +* End ECL driver and Diode receiver models from Raytheon + +*10 segments per cm +.subckt lump10 1 2 +l1 1 3 0.0.8792nH +c1 2 0 0.0468pF +x1 3 2 r10 +.ends lump10 + +*1 segment per cm +.subckt lump1 1 2 +l1 1 3 8.792nH +c1 2 0 0.468pF +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 8 r10 +x6 8 9 r10 +x7 9 10 r10 +x8 10 11 r10 +x9 11 12 r10 +x10 12 2 r10 +.ends lump1 + +*2 segments per cm +.subckt lump2 1 2 +l1 1 3 4.396nH +c1 2 0 0.234pF +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 2 r10 +.ends lump2 + +*4 segments per cm +.subckt lump4 1 2 +l1 1 3 2.198nH +c1 2 0 0.117pF +x1 3 4 r10 +x2 4 5 r10 +x3 5 2 r10 +x4 5 2 r10 +.ends lump4 + +*8 segments per cm +.subckt lump8 1 2 +l1 1 3 1.099nH +c1 2 0 0.0585pF +x1 3 4 r10 +x2 4 2 r10 +x3 4 2 r10 +x4 4 2 r10 +x5 4 2 r10 +.ends lump8 + +.subckt onecm10 1 2 +x1 1 3 lump10 +x2 3 4 lump10 +x3 4 5 lump10 +x4 5 6 lump10 +x5 6 7 lump10 +x6 7 8 lump10 +x7 8 9 lump10 +x8 9 10 lump10 +x9 10 11 lump10 +x10 11 2 lump10 +.ends onecm10 + +.subckt onecm8 1 2 +x1 1 3 lump8 +x2 3 4 lump8 +x3 4 5 lump8 +x4 5 6 lump8 +x5 6 7 lump8 +x6 7 8 lump8 +x7 8 9 lump8 +x8 9 2 lump8 +.ends onecm8 + +.subckt onecm4 1 2 +x1 1 3 lump4 +x2 3 4 lump4 +x3 4 5 lump4 +x4 5 2 lump4 +.ends onecm4 + +.subckt onecm2 1 2 +x1 1 3 lump2 +x2 3 2 lump2 +.ends onecm2 + +.subckt twocm 1 2 +x1 1 3 onecm +x2 3 2 onecm +.ends twocm + +.subckt threecm 1 2 +x1 1 3 onecm +x2 3 4 onecm +x3 4 2 onecm +.ends threecm + +.subckt fourcm 1 2 +x1 1 3 onecm +x2 3 4 onecm +x3 4 5 onecm +x4 5 2 onecm +.ends fourcm + +.subckt fivecm 1 2 +x1 1 3 onecm +x2 3 4 onecm +x3 4 5 onecm +x4 5 6 onecm +x5 6 2 onecm +.ends fivecm + +.subckt sixcm 1 2 +x1 1 3 fivecm +x2 3 2 onecm +.ends sixcm + +.subckt sevencm 1 2 +x1 1 3 sixcm +x2 3 2 onecm +.ends sevencm + +.subckt eightcm 1 2 +x1 1 3 sevencm +x2 3 2 onecm +.ends eightcm + +.subckt ninecm 1 2 +x1 1 3 eightcm +x2 3 2 onecm +.ends ninecm + +.subckt tencm 1 2 +x1 1 3 fivecm +x2 3 2 fivecm +.ends tencm + +.subckt elevencm 1 2 +x1 1 3 tencm +x2 3 2 onecm +.ends elevencm + +.subckt twelvecm 1 2 +x1 1 3 tencm +x2 3 4 onecm +x3 4 2 onecm +.ends twelvecm + +.subckt sixteencm 1 2 +x1 1 3 eightcm +x2 3 2 eightcm +.ends sixteencm + +.subckt twentyfourcm 1 2 +x1 1 3 twelvecm +x2 3 2 twelvecm +.ends twentyfourcm + + +*modelling using R and lossless lines +* 10 segments per cm +.model yless10 txl r=0 g=0 l=8.792e-9 c=0.468e-12 length=0.1 + +* 8 segments per cm +.model yless8 txl r=0 g=0 l=8.792e-9 c=0.468e-12 length=0.125 + +* 4 segments per cm +.model yless4 txl r=0 g=0 l=8.792e-9 c=0.468e-12 length=0.25 + +* 2 segments per cm +.model yless2 txl r=0 g=0 l=8.792e-9 c=0.468e-12 length=0.5 + +* 1 segment per cm +.model yless1 txl r=0 g=0 l=8.792e-9 c=0.468e-12 length=1 + +*10 segments per cm +.subckt xlump10 1 2 +y1 1 0 3 0 yless10 +x1 3 2 r10 +.ends xlump10 + +*1 segment per cm +.subckt xlump1 1 2 +y1 1 0 3 0 yless1 +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 8 r10 +x6 8 9 r10 +x7 9 10 r10 +x8 10 11 r10 +x9 11 12 r10 +x10 12 2 r10 +.ends xlump1 + +*2 segments per cm +.subckt xlump2 1 2 +y1 1 0 3 0 yless2 +x1 3 4 r10 +x2 4 5 r10 +x3 5 6 r10 +x4 6 7 r10 +x5 7 2 r10 +.ends xlump2 + +*4 segments per cm +.subckt xlump4 1 2 +y1 1 0 3 0 yless4 +x1 3 4 r10 +x2 4 5 r10 +x3 5 2 r10 +x4 5 2 r10 +.ends xlump4 + +*8 segments per cm +.subckt xlump8 1 2 +y1 1 0 3 0 yless8 +x1 3 4 r10 +x2 4 2 r10 +x3 4 2 r10 +x4 4 2 r10 +x5 4 2 r10 +.ends xlump8 + +.subckt xonecm10 1 2 +x1 1 3 xlump10 +x2 3 4 xlump10 +x3 4 5 xlump10 +x4 5 6 xlump10 +x5 6 7 xlump10 +x6 7 8 xlump10 +x7 8 9 xlump10 +x8 9 10 xlump10 +x9 10 11 xlump10 +x10 11 2 xlump10 +.ends xonecm10 + +.subckt xonecm8 1 2 +x1 1 3 xlump8 +x2 3 4 xlump8 +x3 4 5 xlump8 +x4 5 6 xlump8 +x5 6 7 xlump8 +x6 7 8 xlump8 +x7 8 9 xlump8 +x8 9 2 xlump8 +.ends xonecm8 + +.subckt xonecm4 1 2 +x1 1 3 xlump4 +x2 3 4 xlump4 +x3 4 5 xlump4 +x4 5 2 xlump4 +.ends xonecm4 + +.subckt xonecm2 1 2 +x1 1 3 xlump2 +x2 3 2 xlump2 +.ends xonecm2 + + +.subckt xtwocm 1 2 +x1 1 3 xonecm +x2 3 2 xonecm +.ends xtwocm + +.subckt xthreecm 1 2 +x1 1 3 xonecm +x2 3 4 xonecm +x3 4 2 xonecm +.ends xthreecm + +.subckt xfourcm 1 2 +x1 1 3 xonecm +x2 3 4 xonecm +x3 4 5 xonecm +x4 5 2 xonecm +.ends xfourcm + +.subckt xfivecm 1 2 +x1 1 3 xonecm +x2 3 4 xonecm +x3 4 5 xonecm +x4 5 6 xonecm +x5 6 2 xonecm +.ends xfivecm + +.subckt xsixcm 1 2 +x1 1 3 xfivecm +x2 3 2 xonecm +.ends xsixcm + +.subckt xsevencm 1 2 +x1 1 3 xsixcm +x2 3 2 xonecm +.ends xsevencm + +.subckt xeightcm 1 2 +x1 1 3 xsevencm +x2 3 2 xonecm +.ends xeightcm + +.subckt xninecm 1 2 +x1 1 3 xeightcm +x2 3 2 xonecm +.ends xninecm + +.subckt xtencm 1 2 +x1 1 3 xfivecm +x2 3 2 xfivecm +.ends xtencm + +.subckt xelevencm 1 2 +x1 1 3 xtencm +x2 3 2 xonecm +.ends xelevencm + +.subckt xtwelvecm 1 2 +x1 1 3 xtencm +x2 3 4 xonecm +x3 4 2 xonecm +.ends xtwelvecm + +.subckt xsixteencm 1 2 +x1 1 3 xeightcm +x2 3 2 xeightcm +.ends xsixteencm + +.subckt xtwentyfourcm 1 2 +x1 1 3 xtwelvecm +x2 3 2 xtwelvecm +.ends xtwentyfourcm + +.end diff --git a/Windows/spice/examples/cider/bicmos/bicmos.lib b/Windows/spice/examples/cider/bicmos/bicmos.lib new file mode 100644 index 00000000..cc1eb20d --- /dev/null +++ b/Windows/spice/examples/cider/bicmos/bicmos.lib @@ -0,0 +1,127 @@ +.MODEL M_NPN nbjt level=2 ++ title TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ * Since, we are only simulating half of a device, we double the unit width ++ * 1.0 um emitter length ++ options defw=2.0u ++ output dc.debug stat ++ ++ *x.mesh w=2.5 n=5 ++ x.mesh w=2.0 h.e=0.05 h.m=0.2 r=1.5 ++ x.mesh w=0.5 h.s=0.05 h.m=0.1 r=1.5 ++ ++ y.mesh l=-0.2 n=1 ++ y.mesh l= 0.0 n=5 ++ y.mesh w=0.10 h.e=0.002 h.m=0.01 r=1.5 ++ y.mesh w=0.15 h.s=0.002 h.m=0.01 r=1.5 ++ y.mesh w=0.35 h.s=0.01 h.m=0.2 r=1.5 ++ y.mesh w=0.40 h.e=0.05 h.m=0.2 r=1.5 ++ y.mesh w=0.30 h.s=0.05 h.m=0.1 r=1.5 ++ ++ domain num=1 material=1 x.l=2.0 y.h=0.0 ++ domain num=2 material=2 x.h=2.0 y.h=0.0 ++ domain num=3 material=3 y.l=0.0 ++ material num=1 polysilicon ++ material num=2 oxide ++ material num=3 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=1.1 y.h=1.3 ++ elec num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=-0.2 ++ ++ doping gauss n.type conc=3e20 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.047 lat.rotate ++ doping gauss p.type conc=1e19 x.l=0.0 x.h=5.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.094 lat.rotate ++ doping unif n.type conc=1e16 x.l=0.0 x.h=5.0 y.l=0.0 y.h=1.3 ++ doping gauss n.type conc=5e19 x.l=0.0 x.h=5.0 y.l=1.3 y.h=1.3 ++ + char.l=0.100 lat.rotate ++ ++ method ac=direct itlim=10 ++ models bgn srh auger conctau concmob fieldmob + +.MODEL M_NMOS_1 numos ++ output dc.debug stat ++ title 1.0um NMOS Device ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.4 h.s=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.4 h.e=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1.0 x.h=2.0 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=2.5 x.h=3.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1.0 x.h=2.0 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=3.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=3.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=3.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1.0 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=2.0 x.h=3.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=2.05 x.h=3.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob fieldmob surfmob srh auger conctau bgn ^aval ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_1 numos ++ title 1.0um PMOS Device ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.4 h.s=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.4 h.e=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1.0 x.h=2.0 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=2.5 x.h=3.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1.0 x.h=2.0 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=3.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=3.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=3.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1.0 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=2.0 x.h=3.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=2.05 x.h=3.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob fieldmob surfmob srh auger conctau bgn ^aval ++ method ac=direct itlim=10 onec diff --git a/Windows/spice/examples/cider/bicmos/bicmpd.cir b/Windows/spice/examples/cider/bicmos/bicmpd.cir new file mode 100644 index 00000000..8096b49b --- /dev/null +++ b/Windows/spice/examples/cider/bicmos/bicmpd.cir @@ -0,0 +1,26 @@ +BiCMOS Pulldown Circuit + +VSS 2 0 0v + +VIN 3 2 0v (PULSE 0.0v 4.2v 0ns 1ns 1ns 9ns 20ns) + +M1 8 3 5 11 M_NMOS_1 W=4u L=1u +VD 4 8 0v +VBK 11 2 0v + +Q1 10 7 9 M_NPN AREA=8 +VC 4 10 0v +VB 5 7 0v +VE 9 2 0v + +CL 4 6 1pF +VL 6 2 0v + +.IC V(10)=5.0v V(7)=0.0v +.TRAN 0.1ns 5ns 0ns 0.1ns +.PLOT TRAN I(VIN) + +.include bicmos.lib + +.OPTIONS ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/bjt/astable.cir b/Windows/spice/examples/cider/bjt/astable.cir new file mode 100644 index 00000000..bdb4a8a8 --- /dev/null +++ b/Windows/spice/examples/cider/bjt/astable.cir @@ -0,0 +1,34 @@ +Astable multivibrator + +vin 5 0 dc 0 pulse(0 5 0 1us 1us 100us 100us) +vcc 6 0 5.0 +rc1 6 1 1k +rc2 6 2 1k +rb1 6 3 30k +rb2 5 4 30k +c1 1 4 150pf +c2 2 3 150pf +q1 1 3 0 qmod area = 100p +q2 2 4 0 qmod area = 100p + +.option acct bypass=1 +.tran 0.05us 8us 0us 0.05us +.print tran v(1) v(2) v(3) v(4) + +.model qmod nbjt level=1 ++ x.mesh node=1 loc=0.0 ++ x.mesh node=61 loc=3.0 ++ region num=1 material=1 ++ material num=1 silicon nbgnn=1e17 nbgnp=1e17 ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ doping unif n.type conc=1e17 x.l=0.0 x.h=1.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.5 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=3.0 ++ models bgnw srh conctau auger concmob fieldmob ++ options base.length=1.0 base.depth=1.25 + +.end diff --git a/Windows/spice/examples/cider/bjt/colposc.cir b/Windows/spice/examples/cider/bjt/colposc.cir new file mode 100644 index 00000000..bd4d31fa --- /dev/null +++ b/Windows/spice/examples/cider/bjt/colposc.cir @@ -0,0 +1,33 @@ +Colpitt's Oscillator Circuit + +r1 1 0 1 +q1 2 1 3 qmod area = 100p +vcc 4 0 5 +rl 4 2 750 +c1 2 3 500p +c2 4 3 4500p +l1 4 2 5uH +re 3 6 4.65k +vee 6 0 dc -15 pwl 0 -15 1e-9 -10 + +.tran 30n 12u +.print tran v(2) + +.model qmod nbjt level=1 ++ x.mesh node=1 loc=0.0 ++ x.mesh node=61 loc=3.0 ++ region num=1 material=1 ++ material num=1 silicon nbgnn=1e17 nbgnp=1e17 ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ doping unif n.type conc=1e17 x.l=0.0 x.h=1.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.5 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=3.0 ++ models bgnw srh conctau auger concmob fieldmob ++ options base.length=1.0 base.depth=1.25 + +.options acct bypass=1 +.end diff --git a/Windows/spice/examples/cider/bjt/ecp.cir b/Windows/spice/examples/cider/bjt/ecp.cir new file mode 100644 index 00000000..6fb2bda9 --- /dev/null +++ b/Windows/spice/examples/cider/bjt/ecp.cir @@ -0,0 +1,57 @@ +Emitter Coupled Pair + +VCC 1 0 5v +VEE 2 0 0v +RCP 1 11 10k +RCN 1 21 10k +VBBP 12 0 3v AC 1 +VBBN 22 0 3v +IEE 13 2 0.1mA +Q1 11 12 13 M_NPN AREA=8 +Q2 21 22 13 M_NPN AREA=8 + +.DC VBBP 2.75v 3.25001v 10mv +.PRINT V(21) V(11) + +.MODEL M_NPN nbjt level=2 ++ title TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ * Since, we are only simulating half of a device, we double the unit width ++ * 1.0 um emitter length ++ options defw=2.0u ++ ++ *x.mesh w=2.5 n=5 ++ x.mesh w=2.0 h.e=0.05 h.m=0.2 r=1.5 ++ x.mesh w=0.5 h.s=0.05 h.m=0.1 r=1.5 ++ ++ y.mesh l=-0.2 n=1 ++ y.mesh l= 0.0 n=5 ++ y.mesh w=0.10 h.e=0.002 h.m=0.01 r=1.5 ++ y.mesh w=0.15 h.s=0.002 h.m=0.01 r=1.5 ++ y.mesh w=0.35 h.s=0.01 h.m=0.2 r=1.5 ++ y.mesh w=0.40 h.e=0.05 h.m=0.2 r=1.5 ++ y.mesh w=0.30 h.s=0.05 h.m=0.1 r=1.5 ++ ++ domain num=1 material=1 x.l=2.0 y.h=0.0 ++ domain num=2 material=2 x.h=2.0 y.h=0.0 ++ domain num=3 material=3 y.l=0.0 ++ material num=1 polysilicon ++ material num=2 oxide ++ material num=3 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=1.1 y.h=1.3 ++ elec num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=-0.2 ++ ++ doping gauss n.type conc=3e20 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.047 lat.rotate ++ doping gauss p.type conc=1e19 x.l=0.0 x.h=5.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.094 lat.rotate ++ doping unif n.type conc=1e16 x.l=0.0 x.h=5.0 y.l=0.0 y.h=1.3 ++ doping gauss n.type conc=5e19 x.l=0.0 x.h=5.0 y.l=1.3 y.h=1.3 ++ + char.l=0.100 lat.rotate ++ ++ method ac=direct itlim=10 ++ models bgn srh auger conctau concmob fieldmob + +.OPTIONS ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/bjt/invchain.cir b/Windows/spice/examples/cider/bjt/invchain.cir new file mode 100644 index 00000000..92c6fad8 --- /dev/null +++ b/Windows/spice/examples/cider/bjt/invchain.cir @@ -0,0 +1,38 @@ +4 Stage RTL Inverter Chain + +vin 1 0 dc 0v pwl 0ns 0v 1ns 5v +vcc 12 0 dc 5.0v +rc1 12 3 2.5k +rb1 1 2 8k +q1 3 2 0 qmod area = 100p +rb2 3 4 8k +rc2 12 5 2.5k +q2 5 4 0 qmod area = 100p +rb3 5 6 8k +rc3 12 7 2.5k +q3 7 6 0 qmod area = 100p +rb4 7 8 8k +rc4 12 9 2.5k +q4 9 8 0 qmod area = 100p + +.print tran v(3) v(5) v(9) +.tran 1e-9 10e-9 + +.model qmod nbjt level=1 ++ x.mesh node=1 loc=0.0 ++ x.mesh node=61 loc=3.0 ++ region num=1 material=1 ++ material num=1 silicon nbgnn=1e17 nbgnp=1e17 ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ doping unif n.type conc=1e17 x.l=0.0 x.h=1.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.5 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=3.0 ++ models bgnw srh conctau auger concmob fieldmob ++ options base.length=1.0 base.depth=1.25 + +.option acct bypass=1 +.end diff --git a/Windows/spice/examples/cider/bjt/meclgate.cir b/Windows/spice/examples/cider/bjt/meclgate.cir new file mode 100644 index 00000000..33542d5d --- /dev/null +++ b/Windows/spice/examples/cider/bjt/meclgate.cir @@ -0,0 +1,74 @@ +Motorola MECL III ECL gate +*.dc vin -2.0 0 0.02 +.tran 0.2ns 20ns +vee 22 0 -6.0 +vin 1 0 pulse -0.8 -1.8 0.2ns 0.2ns 0.2ns 10ns 20ns +rs 1 2 50 +q1 4 2 6 qmod area = 100p +q2 4 3 6 qmod area = 100p +q3 5 7 6 qmod area = 100p +q4 0 8 7 qmod area = 100p + +d1 8 9 dmod +d2 9 10 dmod + +rp1 3 22 50k +rc1 0 4 100 +rc2 0 5 112 +re 6 22 380 +r1 7 22 2k +r2 0 8 350 +r3 10 22 1958 + +q5 0 5 11 qmod area = 100p +q6 0 4 12 qmod area = 100p + +rp2 11 22 560 +rp3 12 22 560 + +q7 13 12 15 qmod area = 100p +q8 14 16 15 qmod area = 100p + +re2 15 22 380 +rc3 0 13 100 +rc4 0 14 112 + +q9 0 17 16 qmod area = 100p + +r4 16 22 2k +r5 0 17 350 +d3 17 18 dmod +d4 18 19 dmod +r6 19 22 1958 + +q10 0 14 20 qmod area = 100p +q11 0 13 21 qmod area = 100p + +rp4 20 22 560 +rp5 21 22 560 + +.model dmod d rs=40 tt=0.1ns cjo=0.9pf n=1 is=1e-14 eg=1.11 vj=0.8 m=0.5 + +.model qmod nbjt level=1 ++ x.mesh node=1 loc=0.0 ++ x.mesh node=10 loc=0.9 ++ x.mesh node=20 loc=1.1 ++ x.mesh node=30 loc=1.4 ++ x.mesh node=40 loc=1.6 ++ x.mesh node=61 loc=3.0 ++ region num=1 material=1 ++ material num=1 silicon nbgnn=1e17 nbgnp=1e17 ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ doping unif n.type conc=1e17 x.l=0.0 x.h=1.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.5 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=3.0 ++ models bgnw srh conctau auger concmob fieldmob ++ options base.length=1.0 base.depth=1.25 + +.options acct bypass=1 +.print tran v(12) v(21) +.end diff --git a/Windows/spice/examples/cider/bjt/pebjt.lib b/Windows/spice/examples/cider/bjt/pebjt.lib new file mode 100644 index 00000000..afbdb36c --- /dev/null +++ b/Windows/spice/examples/cider/bjt/pebjt.lib @@ -0,0 +1,71 @@ +** +* Numerical models for a +* polysilicon emitter complementary bipolar process. +* The default device size is 1um by 10um (LxW) +** + +.model M_NPN nbjt level=1 ++ title One-Dimensional Numerical Bipolar ++ options base.depth=0.15 base.area=0.1 base.length=1.0 defa=10p ++ x.mesh loc=-0.2 n=1 ++ x.mesh loc=0.0 n=51 ++ x.mesh wid=0.15 h.e=0.0001 h.m=.004 r=1.2 ++ x.mesh wid=1.15 h.s=0.0001 h.m=.004 r=1.2 ++ domain num=1 material=1 x.l=0.0 ++ domain num=2 material=2 x.h=0.0 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ material num=2 polysilicon ++ mobility mat=2 concmod=ct fieldmod=ct ++ doping gauss n.type conc=3e20 x.l=-0.2 x.h=0.0 char.len=0.047 ++ doping gauss p.type conc=5e18 x.l=-0.2 x.h=0.0 char.len=0.100 ++ doping unif n.type conc=1e16 x.l=0.0 x.h=1.3 ++ doping gauss n.type conc=5e19 x.l=1.3 x.h=1.3 char.len=0.100 ++ models bgn srh auger conctau concmob fieldmob ^aval ++ method devtol=1e-12 ac=direct itlim=15 + +.model M_NPSUB numd level=1 ++ title One-Dimensional Numerical Collector-Substrate Diode ++ options defa=10p ++ x.mesh loc=1.3 n=1 ++ x.mesh loc=2.0 n=101 ++ domain num=1 material=1 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ doping gauss n.type conc=5e19 x.l=1.3 x.h=1.3 char.len=0.100 ++ doping unif p.type conc=1e15 x.l=0.0 x.h=2.0 ++ models bgn srh auger conctau concmob fieldmob ^aval ++ method devtol=1e-12 itlim=10 + +.model M_PNP nbjt level=1 ++ title One-Dimensional Numerical Bipolar ++ options base.depth=0.2 base.area=0.1 base.length=1.0 defa=10p ++ x.mesh loc=-0.2 n=1 ++ x.mesh loc=0.0 n=51 ++ x.mesh wid=0.20 h.e=0.0001 h.m=.004 r=1.2 ++ x.mesh wid=1.10 h.s=0.0001 h.m=.004 r=1.2 ++ domain num=1 material=1 x.l=0.0 ++ domain num=2 material=2 x.h=0.0 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ material num=2 polysilicon ++ mobility mat=2 concmod=ct fieldmod=ct ++ doping gauss p.type conc=3e20 x.l=-0.2 x.h=0.0 char.len=0.047 ++ doping gauss n.type conc=5e17 x.l=-0.2 x.h=0.0 char.len=0.200 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.3 ++ doping gauss p.type conc=5e19 x.l=1.3 x.h=1.3 char.len=0.100 ++ models bgn srh auger conctau concmob fieldmob ^aval ++ method devtol=1e-12 ac=direct itlim=15 + +.model M_PNSUB numd level=1 ++ title One-Dimensional Numerical Collector-Substrate Diode ++ options defa=10p ++ x.mesh loc=1.3 n=1 ++ x.mesh loc=2.0 n=101 ++ domain num=1 material=1 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ doping gauss p.type conc=5e19 x.l=1.3 x.h=1.3 char.len=0.100 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=2.0 ++ models bgn srh auger conctau concmob fieldmob ^aval ++ method devtol=1e-12 itlim=10 diff --git a/Windows/spice/examples/cider/bjt/pz.cir b/Windows/spice/examples/cider/bjt/pz.cir new file mode 100644 index 00000000..ad3ee675 --- /dev/null +++ b/Windows/spice/examples/cider/bjt/pz.cir @@ -0,0 +1,16 @@ +PZ Analysis of a Common Emitter Amplifier + +Vcc 1 0 5v +Vee 2 0 0v + +Vin 3 0 0.7838 AC 1 +RS 3 4 1K +Q1 5 4 2 M_NPN AREA=4 SAVE +RL 1 5 2.5k +CL 5 0 0.1pF + +.INCLUDE pebjt.lib + +.PZ 3 0 5 0 vol pz + +.END diff --git a/Windows/spice/examples/cider/bjt/rtlinv.cir b/Windows/spice/examples/cider/bjt/rtlinv.cir new file mode 100644 index 00000000..f45eb983 --- /dev/null +++ b/Windows/spice/examples/cider/bjt/rtlinv.cir @@ -0,0 +1,29 @@ +RTL inverter + +vin 1 0 dc 1 pwl 0 4 1ns 0 +vcc 12 0 dc 5.0 +rc1 12 3 2.5k +rb1 1 2 8k +q1 3 2 0 qmod area = 100p + +.option acct bypass=1 +.tran 0.5n 5n +.print tran v(2) v(3) + +.model qmod nbjt level=1 ++ x.mesh node=1 loc=0.0 ++ x.mesh node=61 loc=3.0 ++ region num=1 material=1 ++ material num=1 silicon nbgnn=1e17 nbgnp=1e17 ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ doping unif n.type conc=1e17 x.l=0.0 x.h=1.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.5 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=3.0 ++ models bgnw srh conctau auger concmob fieldmob ++ options base.length=1.0 base.depth=1.25 + +.end diff --git a/Windows/spice/examples/cider/bjt/vco.cir b/Windows/spice/examples/cider/bjt/vco.cir new file mode 100644 index 00000000..d1b1a058 --- /dev/null +++ b/Windows/spice/examples/cider/bjt/vco.cir @@ -0,0 +1,45 @@ +Voltage controlled oscillator + +rc1 7 5 1k +rc2 7 6 1k + +q5 7 7 5 qmod area = 100p +q6 7 7 6 qmod area = 100p + +q3 7 5 2 qmod area = 100p +q4 7 6 1 qmod area = 100p + +ib1 2 0 .5ma +ib2 1 0 .5ma +cb1 2 0 1pf +cb2 1 0 1pf + +q1 5 1 3 qmod area = 100p +q2 6 2 4 qmod area = 100p + +c1 3 4 .1uf + +is1 3 0 dc 2.5ma pulse 2.5ma 0.5ma 0 1us 1us 50ms +is2 4 0 1ma +vcc 7 0 10 + +.model qmod nbjt level=1 ++ x.mesh node=1 loc=0.0 ++ x.mesh node=61 loc=3.0 ++ region num=1 material=1 ++ material num=1 silicon nbgnn=1e17 nbgnp=1e17 ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ doping unif n.type conc=1e17 x.l=0.0 x.h=1.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.5 ++ doping unif n.type conc=1e15 x.l=0.0 x.h=3.0 ++ models bgnw srh conctau auger concmob fieldmob ++ options base.length=1.0 base.depth=1.25 + +.option acct bypass=1 +.tran 3us 600us 0 3us +.print tran v(4) +.end diff --git a/Windows/spice/examples/cider/diode/diode.cir b/Windows/spice/examples/cider/diode/diode.cir new file mode 100644 index 00000000..e0ace324 --- /dev/null +++ b/Windows/spice/examples/cider/diode/diode.cir @@ -0,0 +1,35 @@ +One-Dimensional Diode Simulation + +* Several simulations are performed by this file. +* They are: +* 1. An operating point at 0.7v forward bias. +* 2. An ac analysis at 0.7v forward bias. +* 3. The forward and reverse bias characteristics from -3v to 2v. + +Vpp 1 0 0.7v (PWL 0ns 3.0v 0.01ns -6.0v) (AC 1v) +Vnn 2 0 0v +D1 1 2 M_PN AREA=100 + +.model M_PN numd level=1 ++ *************************************** ++ *** One-Dimensional Numerical Diode *** ++ *************************************** ++ options defa=1p ++ x.mesh loc=0.0 n=1 ++ x.mesh loc=1.3 n=201 ++ domain num=1 material=1 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ doping gauss p.type conc=1e20 x.l=0.0 x.h=0.0 char.l=0.100 ++ doping unif n.type conc=1e16 x.l=0.0 x.h=1.3 ++ doping gauss n.type conc=5e19 x.l=1.3 x.h=1.3 char.l=0.100 ++ models bgn aval srh auger conctau concmob fieldmob ++ method ac=direct + +.option acct bypass=0 abstol=1e-18 itl2=100 +.op +.ac dec 10 100kHz 10gHz +.dc Vpp -3.0v 2.0001v 50mv +.print i(Vpp) + +.END diff --git a/Windows/spice/examples/cider/diode/diotran.cir b/Windows/spice/examples/cider/diode/diotran.cir new file mode 100644 index 00000000..110d2550 --- /dev/null +++ b/Windows/spice/examples/cider/diode/diotran.cir @@ -0,0 +1,31 @@ +Diode Reverse Recovery + +* This file simulates reverse recovery of a diode as it switched from an +* on to off state. + +Vpp 1 0 0.7v (PWL 0ns 3.0v 0.1ns 3.0v 0.11ns -6.0v) (AC 1v) +Vnn 2 0 0v +R1 1 3 1k +D1 3 2 M_PN area=100 + +.MODEL M_PN numd level=1 ++ *************************************** ++ *** One-Dimensional Numerical Diode *** ++ *************************************** ++ options defa=1p ++ x.mesh loc=0.0 n=1 ++ x.mesh loc=1.3 n=201 ++ domain num=1 material=1 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ doping gauss p.type conc=3e20 x.l=0.0 x.h=0.0 char.l=0.100 ++ doping unif n.type conc=1e16 x.l=0.0 x.h=1.3 ++ doping gauss n.type conc=5e19 x.l=1.3 x.h=1.3 char.l=0.100 ++ models bgn aval srh auger conctau concmob fieldmob ++ method ac=direct + +.option acct bypass=1 abstol=1e-15 itl2=100 +.tran 0.001ns 1.0ns +.print i(Vpp) + +.END diff --git a/Windows/spice/examples/cider/diode/pindiode.cir b/Windows/spice/examples/cider/diode/pindiode.cir new file mode 100644 index 00000000..1eb18b42 --- /dev/null +++ b/Windows/spice/examples/cider/diode/pindiode.cir @@ -0,0 +1,42 @@ +TWO-DIMENSIONAL PIN-DIODE CIRCUIT + +VIN 1 0 0.0v (PWL 0ns 0.8v 1ns -50.0v) +L1 1 2 0.5uH +VD 2 3 0.0v +D1 3 0 M_PIN AREA=200 IC.FILE="OP.0.d1" +VRC 2 4 0.0v +R1 4 5 100 +C1 5 0 1.0nF + +.MODEL M_PIN NUMD LEVEL=2 ++ options defw=1000u ++ x.mesh n=1 l=0.0 ++ x.mesh n=2 l=0.2 ++ x.mesh n=4 l=0.4 ++ x.mesh n=8 l=0.6 ++ x.mesh n=13 l=1.0 ++ ++ y.mesh n=1 l=0.0 ++ y.mesh n=9 l=4.0 ++ y.mesh n=24 l=10.0 ++ y.mesh n=29 l=15.0 ++ y.mesh n=34 l=20.0 ++ ++ domain num=1 material=1 ++ material num=1 silicon tn=20ns tp=20ns ++ ++ electrode num=1 x.l=0.6 x.h=1.0 y.h=0.0 ++ electrode num=2 y.l=20.0 ++ ++ doping gauss p.type conc=1.0e20 char.len=1.076 x.l=0.75 x.h=1.1 y.h=0.0 ++ + lat.rotate ratio=0.1 ++ doping unif n.type conc=1.0e14 ++ doping gauss n.type conc=1.0e20 char.len=1.614 x.l=-0.1 x.h=1.1 y.l=20.0 ++ ++ models bgn srh auger conctau concmob fieldmob + +.OPTION ACCT BYPASS=1 +.TRAN 1NS 100NS +.PRINT TRAN v(3) I(VIN) + +.END diff --git a/Windows/spice/examples/cider/jfet/jfet.cir b/Windows/spice/examples/cider/jfet/jfet.cir new file mode 100644 index 00000000..e3f00536 --- /dev/null +++ b/Windows/spice/examples/cider/jfet/jfet.cir @@ -0,0 +1,36 @@ +Two-dimensional Junction Field-Effect Transistor (JFET) + +VDD 1 0 0.5V +VGG 2 0 -1.0v AC 1V +VSS 3 0 0.0V +QJ1 1 2 3 M_NJF AREA=1 + +.MODEL M_NJF NBJT LEVEL=2 ++ options jfet defw=10.0um ++ output dc.debug phin phip equ.psi vac.psi ++ x.mesh w=0.2 h.e=0.001 r=1.8 ++ x.mesh w=0.8 h.s=0.001 h.m=0.1 r=2.0 ++ x.mesh w=0.8 h.e=0.001 h.m=0.1 r=2.0 ++ x.mesh w=0.2 h.s=0.001 r=1.8 ++ y.mesh w=0.2 h.e=0.01 r=1.8 ++ y.mesh w=0.8 h.s=0.01 h.m=0.1 r=1.8 ++ ++ domain num=1 mat=1 ++ material num=1 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=0.0 y.h=1.0 ++ elec num=2 x.l=0.5 x.h=1.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=2.0 y.l=0.0 y.h=1.0 ++ ++ doping unif n.type conc=3.0e15 ++ doping unif p.type conc=2.0e17 x.l=0.2 x.h=1.8 y.h=0.2 ++ ++ models bgn srh auger conctau concmob fieldmob ^aval + +.option acct bypass=1 temp=27 +*.op +.dc vgg 0.0 -2.0001 -0.1 +*.ac dec 10 1k 100g +.print i(vnn) + +.end diff --git a/Windows/spice/examples/cider/mos/bootinv.cir b/Windows/spice/examples/cider/mos/bootinv.cir new file mode 100644 index 00000000..4c2ea40d --- /dev/null +++ b/Windows/spice/examples/cider/mos/bootinv.cir @@ -0,0 +1,59 @@ +NMOS Enhancement-Load Bootstrap Inverter + +Vdd 1 0 5.0v +Vss 2 0 0.0v + +Vin 5 0 0.0v PWL (0.0ns 5.0v) (1ns 0.0v) (10ns 0.0v) (11ns 5.0v) ++ (20ns 5.0v) (21ns 0.0v) (30ns 0.0v) (31ns 5.0v) +M1 1 1 3 2 M_NMOS w=5u +M2 1 3 4 4 M_NMOS w=5u +M3 4 5 2 2 M_NMOS w=5u +CL 4 0 0.1pf +CB 3 4 0.1pf + +.model M_NMOS numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 init elec major ++ mobility material=1 init elec minor ++ mobility material=1 init hole major ++ mobility material=1 init hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif p.type conc=2.5e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif n.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif n.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob ++ method ac=direct onec + +.tran 0.2ns 40ns +.print v(4) +.options acct bypass=1 method=gear +.end diff --git a/Windows/spice/examples/cider/mos/charge.cir b/Windows/spice/examples/cider/mos/charge.cir new file mode 100644 index 00000000..845a14a8 --- /dev/null +++ b/Windows/spice/examples/cider/mos/charge.cir @@ -0,0 +1,57 @@ +MOS charge pump + +vin 4 0 dc 0v pulse 0 5 15ns 5ns 5ns 50ns 100ns +vdd 5 6 dc 0v pulse 0 5 25ns 5ns 5ns 50ns 100ns +vbb 0 7 dc 0v pulse 0 5 0ns 5ns 5ns 50ns 100ns +rd 6 2 10k +m1 5 4 3 7 mmod w=100um +vs 3 2 0 +vc 2 1 0 +c2 1 0 10pf + +.ic v(3)=1.0 +.tran 2ns 200ns +.options acct bypass=1 +.print tran v(1) v(2) + +.model mmod numos ++ x.mesh n=1 l=0 ++ x.mesh n=3 l=0.4 ++ x.mesh n=7 l=0.6 ++ x.mesh n=15 l=1.4 ++ x.mesh n=19 l=1.6 ++ x.mesh n=21 l=2.0 ++ ++ y.mesh n=1 l=0 ++ y.mesh n=4 l=0.015 ++ y.mesh n=8 l=0.05 ++ y.mesh n=12 l=0.25 ++ y.mesh n=14 l=0.35 ++ y.mesh n=17 l=0.5 ++ y.mesh n=21 l=1.0 ++ ++ region num=1 material=1 y.l=0.015 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.015 x.l=0.5 x.h=1.5 ++ material num=2 oxide ++ ++ elec num=1 ix.l=18 ix.h=21 iy.l=4 iy.h=4 ++ elec num=2 ix.l=5 ix.h=17 iy.l=1 iy.h=1 ++ elec num=3 ix.l=1 ix.h=4 iy.l=4 iy.h=4 ++ elec num=4 ix.l=1 ix.h=21 iy.l=21 iy.h=21 ++ ++ doping unif n.type conc=1e18 x.l=0.0 x.h=0.5 y.l=0.015 y.h=0.25 ++ doping unif n.type conc=1e18 x.l=1.5 x.h=2.0 y.l=0.015 y.h=0.25 ++ doping unif p.type conc=1e15 x.l=0.0 x.h=2.0 y.l=0.015 y.h=1.0 ++ doping unif p.type conc=1.3e17 x.l=0.5 x.h=1.5 y.l=0.015 y.h=0.05 ++ ++ models concmob fieldmob ++ method onec + +.end diff --git a/Windows/spice/examples/cider/mos/cmosinv.cir b/Windows/spice/examples/cider/mos/cmosinv.cir new file mode 100644 index 00000000..8f153cc7 --- /dev/null +++ b/Windows/spice/examples/cider/mos/cmosinv.cir @@ -0,0 +1,115 @@ +CMOS Inverter + +Vdd 1 0 5.0v +Vss 2 0 0.0v + +X1 1 2 3 4 INV + +Vin 3 0 2.5v + +.SUBCKT INV 1 2 3 4 +* Vdd Vss Vin Vout +M1 14 13 15 16 M_PMOS w=6.0u +M2 24 23 25 26 M_NMOS w=3.0u + +Vgp 3 13 0.0v +Vdp 4 14 0.0v +Vsp 1 15 0.0v +Vbp 1 16 0.0v + +Vgn 3 23 0.0v +Vdn 4 24 0.0v +Vsn 2 25 0.0v +Vbn 2 26 0.0v +.ENDS INV + +.model M_NMOS numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif p.type conc=2.5e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif n.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif n.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob bgn srh conctau ++ method ac=direct onec + +.model M_PMOS numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif n.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=3e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif p.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif p.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob bgn srh conctau ++ method ac=direct onec + +*.tran 0.1ns 5ns +*.op +.dc Vin 0.0v 5.001v 0.05v +.print v(4) +.options acct bypass=1 method=gear +.end diff --git a/Windows/spice/examples/cider/mos/nmosinv.cir b/Windows/spice/examples/cider/mos/nmosinv.cir new file mode 100644 index 00000000..ac49c754 --- /dev/null +++ b/Windows/spice/examples/cider/mos/nmosinv.cir @@ -0,0 +1,55 @@ +Resistive load NMOS inverter +vin 1 0 pwl 0 0.0 2ns 5 +vdd 3 0 dc 5.0 +rd 3 2 2.5k +m1 2 1 4 5 mmod w=10um +cl 2 0 2pf +vb 5 0 0 +vs 4 0 0 + +.model mmod numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif p.type conc=2.5e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif n.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif n.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob ++ method ac=direct onec + +.tran 0.2ns 30ns +.options acct bypass=1 +.print tran v(1) v(2) +.end diff --git a/Windows/spice/examples/cider/mos/pass.cir b/Windows/spice/examples/cider/mos/pass.cir new file mode 100644 index 00000000..a58c8a5f --- /dev/null +++ b/Windows/spice/examples/cider/mos/pass.cir @@ -0,0 +1,59 @@ +Turnoff transient of pass transistor + +M1 11 2 3 4 mmod w=20um +Cs 1 0 6.0pF +Cl 3 0 6.0pF +R1 3 6 200k +Vin 6 0 dc 0 +Vdrn 1 11 dc 0 +Vg 2 0 dc 5 pwl 0 5 0.1n 0 1 0 +Vb 4 0 dc 0.0 + +.tran 0.05ns 0.2ns 0.0ns 0.05ns +.print tran v(1) i(Vdrn) +.ic v(1)=0 v(3)=0 +.option acct bypass=1 + +.model mmod numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif p.type conc=2.5e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif n.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif n.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob ++ method ac=direct onec + +.end diff --git a/Windows/spice/examples/cider/mos/ringosc.cir b/Windows/spice/examples/cider/mos/ringosc.cir new file mode 100644 index 00000000..0f313320 --- /dev/null +++ b/Windows/spice/examples/cider/mos/ringosc.cir @@ -0,0 +1,122 @@ +CMOS Ring Oscillator + +Vdd 1 0 5.0v +Vss 2 0 0.0v + +X1 1 2 3 4 INV +X2 1 2 4 5 INV +X3 1 2 5 3 INV +*X4 1 2 6 7 INV +*X5 1 2 7 8 INV +*X6 1 2 8 9 INV +*X7 1 2 9 3 INV + +.IC V(3)=0.0v V(4)=2.5v V(5)=5.0v +* V(6)=0.0v V(7)=5.0v V(8)=0.0v V(9)=5.0v + +Vin 3 0 2.5v + +.SUBCKT INV 1 2 3 4 +* Vdd Vss Vin Vout +M1 14 13 15 16 M_PMOS w=6.0u +M2 24 23 25 26 M_NMOS w=3.0u + +Vgp 3 13 0.0v +Vdp 4 14 0.0v +Vsp 1 15 0.0v +Vbp 1 16 0.0v + +Vgn 3 23 0.0v +Vdn 4 24 0.0v +Vsn 2 25 0.0v +Vbn 2 26 0.0v +.ENDS INV + +.model M_NMOS numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif p.type conc=2.5e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif n.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif n.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob bgn srh conctau ++ method ac=direct onec + +.model M_PMOS numos ++ x.mesh l=0.0 n=1 ++ x.mesh l=0.6 n=4 ++ x.mesh l=0.7 n=5 ++ x.mesh l=1.0 n=7 ++ x.mesh l=1.2 n=11 ++ x.mesh l=3.2 n=21 ++ x.mesh l=3.4 n=25 ++ x.mesh l=3.7 n=27 ++ x.mesh l=3.8 n=28 ++ x.mesh l=4.4 n=31 ++ ++ y.mesh l=-.05 n=1 ++ y.mesh l=0.0 n=5 ++ y.mesh l=.05 n=9 ++ y.mesh l=0.3 n=14 ++ y.mesh l=2.0 n=19 ++ ++ region num=1 material=1 y.l=0.0 ++ material num=1 silicon ++ mobility material=1 concmod=sg fieldmod=sg ++ mobility material=1 elec major ++ mobility material=1 elec minor ++ mobility material=1 hole major ++ mobility material=1 hole minor ++ ++ region num=2 material=2 y.h=0.0 x.l=0.7 x.h=3.7 ++ material num=2 oxide ++ ++ elec num=1 x.l=3.8 x.h=4.4 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=0.7 x.h=3.7 iy.l=1 iy.h=1 ++ elec num=3 x.l=0.0 x.h=0.6 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=0.0 x.h=4.4 y.l=2.0 y.h=2.0 ++ ++ doping unif n.type conc=1e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=2.0 ++ doping unif p.type conc=3e16 x.l=0.0 x.h=4.4 y.l=0.0 y.h=0.05 ++ doping unif p.type conc=1e20 x.l=0.0 x.h=1.1 y.l=0.0 y.h=0.2 ++ doping unif p.type conc=1e20 x.l=3.3 x.h=4.4 y.l=0.0 y.h=0.2 ++ ++ models concmob fieldmob bgn srh conctau ++ method ac=direct onec + +.tran 0.1ns 5ns +.print v(4) +.options acct bypass=1 method=gear +.end diff --git a/Windows/spice/examples/cider/parallel/BICMOS.LIB b/Windows/spice/examples/cider/parallel/BICMOS.LIB new file mode 100644 index 00000000..606570ca --- /dev/null +++ b/Windows/spice/examples/cider/parallel/BICMOS.LIB @@ -0,0 +1,931 @@ +** +* BICMOS.LIB: Library of models used in the 1.0 um CBiCMOS process +* Contains CIDER input descriptions as well as matching +* SPICE models for some of the CIDER models. +** + +** +* One-dimensional models for a +* polysilicon emitter complementary bipolar process. +* The default device size is 1um by 1um (LxW) +** + +.model M_NPN1D nbjt level=1 ++ title One-Dimensional Numerical Bipolar ++ options base.depth=0.15 base.area=0.1 base.length=0.5 defa=1p ++ x.mesh loc=-0.2 n=1 ++ x.mesh loc=0.0 n=51 ++ x.mesh wid=0.15 h.e=0.0001 h.m=.004 r=1.2 ++ x.mesh wid=1.15 h.s=0.0001 h.m=.004 r=1.2 ++ domain num=1 material=1 x.l=0.0 ++ domain num=2 material=2 x.h=0.0 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ material num=2 polysilicon ++ mobility mat=2 concmod=ct fieldmod=ct ++ doping gauss n.type conc=3e20 x.l=-0.2 x.h=0.0 char.len=0.047 ++ doping gauss p.type conc=5e18 x.l=-0.2 x.h=0.0 char.len=0.100 ++ doping unif n.type conc=1e16 x.l=0.0 x.h=1.3 ++ doping gauss n.type conc=5e19 x.l=1.3 x.h=1.3 char.len=0.100 ++ models bgn srh auger conctau concmob fieldmob ++ method devtol=1e-12 ac=direct itlim=15 + +.model M_PNP1D nbjt level=1 ++ title One-Dimensional Numerical Bipolar ++ options base.depth=0.2 base.area=0.1 base.length=0.5 defa=1p ++ x.mesh loc=-0.2 n=1 ++ x.mesh loc=0.0 n=51 ++ x.mesh wid=0.20 h.e=0.0001 h.m=.004 r=1.2 ++ x.mesh wid=1.10 h.s=0.0001 h.m=.004 r=1.2 ++ domain num=1 material=1 x.l=0.0 ++ domain num=2 material=2 x.h=0.0 ++ material num=1 silicon ++ mobility mat=1 concmod=ct fieldmod=ct ++ material num=2 polysilicon ++ mobility mat=2 concmod=ct fieldmod=ct ++ doping gauss p.type conc=3e20 x.l=-0.2 x.h=0.0 char.len=0.047 ++ doping gauss n.type conc=5e17 x.l=-0.2 x.h=0.0 char.len=0.200 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=1.3 ++ doping gauss p.type conc=5e19 x.l=1.3 x.h=1.3 char.len=0.100 ++ models bgn srh auger conctau concmob fieldmob ++ method devtol=1e-12 ac=direct itlim=15 + +** +* Two-dimensional models for a +* polysilicon emitter complementary bipolar process. +* The default device size is 1um by 1um (LxW) +** + +.MODEL M_NPNS nbjt level=2 ++ title TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ * Since half the device is simulated, double the unit width to get ++ * 1.0 um emitter. Use a small mesh for this model. ++ options defw=2.0u ++ output stat ++ ++ x.mesh w=2.0 h.e=0.02 h.m=0.5 r=2.0 ++ x.mesh w=0.5 h.s=0.02 h.m=0.2 r=2.0 ++ ++ y.mesh l=-0.2 n=1 ++ y.mesh l= 0.0 n=5 ++ y.mesh w=0.10 h.e=0.004 h.m=0.05 r=2.5 ++ y.mesh w=0.15 h.s=0.004 h.m=0.02 r=2.5 ++ y.mesh w=1.05 h.s=0.02 h.m=0.1 r=2.5 ++ ++ domain num=1 material=1 x.l=2.0 y.h=0.0 ++ domain num=2 material=2 x.h=2.0 y.h=0.0 ++ domain num=3 material=3 y.l=0.0 ++ material num=1 polysilicon ++ material num=2 oxide ++ material num=3 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=1.1 y.h=1.3 ++ elec num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=-0.2 ++ ++ doping gauss n.type conc=3e20 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.047 lat.rotate ++ doping gauss p.type conc=5e18 x.l=0.0 x.h=5.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.100 lat.rotate ++ doping gauss p.type conc=1e20 x.l=0.0 x.h=0.5 y.l=-0.2 y.h=0.0 ++ + char.l=0.100 lat.rotate ratio=0.7 ++ doping unif n.type conc=1e16 x.l=0.0 x.h=5.0 y.l=0.0 y.h=1.3 ++ doping gauss n.type conc=5e19 x.l=0.0 x.h=5.0 y.l=1.3 y.h=1.3 ++ + char.l=0.100 lat.rotate ++ ++ method ac=direct itlim=10 ++ models bgn srh auger conctau concmob fieldmob + +.MODEL M_NPN nbjt level=2 ++ title TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ * Since half the device is simulated, double the unit width to get ++ * 1.0 um emitter length. Uses a finer mesh in the X direction. ++ options defw=2.0u ++ output stat ++ ++ x.mesh w=0.5 h.e=0.075 h.m=0.2 r=2.0 ++ x.mesh w=0.75 h.s=0.075 h.m=0.2 r=2.0 ++ x.mesh w=0.75 h.e=0.05 h.m=0.2 r=1.5 ++ x.mesh w=0.5 h.s=0.05 h.m=0.1 r=1.5 ++ ++ y.mesh l=-0.2 n=1 ++ y.mesh l= 0.0 n=5 ++ y.mesh w=0.10 h.e=0.003 h.m=0.01 r=1.5 ++ y.mesh w=0.15 h.s=0.003 h.m=0.02 r=1.5 ++ y.mesh w=0.35 h.s=0.02 h.m=0.2 r=1.5 ++ y.mesh w=0.40 h.e=0.05 h.m=0.2 r=1.5 ++ y.mesh w=0.30 h.s=0.05 h.m=0.1 r=1.5 ++ ++ domain num=1 material=1 x.l=2.0 y.h=0.0 ++ domain num=2 material=2 x.h=2.0 y.h=0.0 ++ domain num=3 material=3 y.l=0.0 ++ material num=1 polysilicon ++ material num=2 oxide ++ material num=3 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=1.1 y.h=1.3 ++ elec num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=-0.2 ++ ++ doping gauss n.type conc=3e20 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.047 lat.rotate ++ doping gauss p.type conc=5e18 x.l=0.0 x.h=5.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.100 lat.rotate ++ doping gauss p.type conc=1e20 x.l=0.0 x.h=0.5 y.l=-0.2 y.h=0.0 ++ + char.l=0.100 lat.rotate ratio=0.7 ++ doping unif n.type conc=1e16 x.l=0.0 x.h=5.0 y.l=0.0 y.h=1.3 ++ doping gauss n.type conc=5e19 x.l=0.0 x.h=5.0 y.l=1.3 y.h=1.3 ++ + char.l=0.100 lat.rotate ++ ++ method ac=direct itlim=10 ++ models bgn srh auger conctau concmob fieldmob + +.MODEL M_PNPS nbjt level=2 ++ title TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ * Since half the device is simulated, double the unit width to get ++ * 1.0 um emitter length. Use a small mesh for this model. ++ options defw=2.0u ++ output stat ++ ++ x.mesh w=2.0 h.e=0.02 h.m=0.5 r=2.0 ++ x.mesh w=0.5 h.s=0.02 h.m=0.2 r=2.0 ++ ++ y.mesh l=-0.2 n=1 ++ y.mesh l= 0.0 n=5 ++ y.mesh w=0.12 h.e=0.004 h.m=0.05 r=2.5 ++ y.mesh w=0.28 h.s=0.004 h.m=0.02 r=2.5 ++ y.mesh w=1.05 h.s=0.02 h.m=0.1 r=2.5 ++ ++ domain num=1 material=1 x.l=2.0 y.h=0.0 ++ domain num=2 material=2 x.h=2.0 y.h=0.0 ++ domain num=3 material=3 y.l=0.0 ++ material num=1 polysilicon ++ material num=2 oxide ++ material num=3 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=1.1 y.h=1.3 ++ elec num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=-0.2 ++ ++ doping gauss p.type conc=3e20 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.047 lat.rotate ++ doping gauss n.type conc=5e17 x.l=0.0 x.h=5.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.200 lat.rotate ++ doping gauss n.type conc=1e20 x.l=0.0 x.h=0.5 y.l=-0.2 y.h=0.0 ++ + char.l=0.100 lat.rotate ratio=0.7 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=5.0 y.l=0.0 y.h=1.3 ++ doping gauss p.type conc=5e19 x.l=0.0 x.h=5.0 y.l=1.3 y.h=1.3 ++ + char.l=0.100 lat.rotate ++ ++ method ac=direct itlim=10 ++ models bgn srh auger conctau concmob fieldmob + +.MODEL M_PNP nbjt level=2 ++ title TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ * Since half the device is simulated, double the unit width to get ++ * 1.0 um emitter length. Uses a finer mesh in the X direction. ++ options defw=2.0u ++ output stat ++ ++ x.mesh w=0.5 h.e=0.075 h.m=0.2 r=2.0 ++ x.mesh w=0.75 h.s=0.075 h.m=0.2 r=2.0 ++ x.mesh w=0.75 h.e=0.05 h.m=0.2 r=1.5 ++ x.mesh w=0.5 h.s=0.05 h.m=0.1 r=1.5 ++ ++ y.mesh l=-0.2 n=1 ++ y.mesh l= 0.0 n=5 ++ y.mesh w=0.12 h.e=0.003 h.m=0.01 r=1.5 ++ y.mesh w=0.28 h.s=0.003 h.m=0.02 r=1.5 ++ y.mesh w=0.20 h.s=0.02 h.m=0.2 r=1.5 ++ y.mesh w=0.40 h.e=0.05 h.m=0.2 r=1.5 ++ y.mesh w=0.30 h.s=0.05 h.m=0.1 r=1.5 ++ ++ domain num=1 material=1 x.l=2.0 y.h=0.0 ++ domain num=2 material=2 x.h=2.0 y.h=0.0 ++ domain num=3 material=3 y.l=0.0 ++ material num=1 polysilicon ++ material num=2 oxide ++ material num=3 silicon ++ ++ elec num=1 x.l=0.0 x.h=0.0 y.l=1.1 y.h=1.3 ++ elec num=2 x.l=0.0 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=3 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=-0.2 ++ ++ doping gauss p.type conc=3e20 x.l=2.0 x.h=3.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.047 lat.rotate ++ doping gauss n.type conc=5e17 x.l=0.0 x.h=5.0 y.l=-0.2 y.h=0.0 ++ + char.l=0.200 lat.rotate ++ doping gauss n.type conc=1e20 x.l=0.0 x.h=0.5 y.l=-0.2 y.h=0.0 ++ + char.l=0.100 lat.rotate ratio=0.7 ++ doping unif p.type conc=1e16 x.l=0.0 x.h=5.0 y.l=0.0 y.h=1.3 ++ doping gauss p.type conc=5e19 x.l=0.0 x.h=5.0 y.l=1.3 y.h=1.3 ++ + char.l=0.100 lat.rotate ++ ++ method ac=direct itlim=10 ++ models bgn srh auger conctau concmob fieldmob + +** +* Two-dimensional models for a +* complementary MOS process. +* Device models for 1um, 2um, 3um, 4um, 5um, 10um and 50um are provided. +** + +.MODEL M_NMOS_1 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.4 h.s=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.4 h.e=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=2 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=2.5 x.h=3.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=2 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=3.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=3.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=3.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=2 x.h=3.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=2.05 x.h=3.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_NMOS_2 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.005 h.m=0.2 r=2.0 ++ x.mesh w=0.9 h.e=0.005 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=3 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=3.5 x.h=4.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=3 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=4.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=4.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=4.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=3 x.h=4.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=3.05 x.h=4.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_NMOS_3 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=1.4 h.s=0.005 h.m=0.3 r=2.0 ++ x.mesh w=1.4 h.e=0.005 h.m=0.3 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=4 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=4.5 x.h=5.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=4 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=5.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=5.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=5.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=4 x.h=5.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=4.05 x.h=5.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_NMOS_4 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=1.9 h.s=0.005 h.m=0.4 r=2.0 ++ x.mesh w=1.9 h.e=0.005 h.m=0.4 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=5 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=5.5 x.h=6.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=5 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=6.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=6.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=6.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=5 x.h=6.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=5.05 x.h=6.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_NMOS_5 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=2.4 h.s=0.005 h.m=0.5 r=2.0 ++ x.mesh w=2.4 h.e=0.005 h.m=0.5 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=6 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=6.5 x.h=7.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=6 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=7.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=7.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=7.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=6 x.h=7.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=6.05 x.h=7.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_NMOS_10 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=4.9 h.s=0.005 h.m=1 r=2.0 ++ x.mesh w=4.9 h.e=0.005 h.m=1 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=11 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=11.5 x.h=12.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=11 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=12.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=12.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=12.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=11 x.h=12.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=11.05 x.h=12.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_NMOS_50 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=24.9 h.s=0.005 h.m=5 r=2.0 ++ x.mesh w=24.9 h.e=0.005 h.m=5 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=51 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=51.5 x.h=52.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=51 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=52.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss p.type conc=1.0e17 x.l=-0.1 x.h=52.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif p.type conc=5.0e15 x.l=-0.1 x.h=52.1 y.l=0.0 y.h=2.1 ++ doping gauss n.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss n.type conc=4e17 x.l=51 x.h=52.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss n.type conc=1e20 x.l=51.05 x.h=52.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=4.10 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_1 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.4 h.s=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.4 h.e=0.005 h.m=0.1 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=2 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=2.5 x.h=3.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=2 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=3.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=3.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=3.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=2 x.h=3.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=2.05 x.h=3.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_2 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.005 h.m=0.2 r=2.0 ++ x.mesh w=0.9 h.e=0.005 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=3 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=3.5 x.h=4.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=3 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=4.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=4.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=4.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=3 x.h=4.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=3.05 x.h=4.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_3 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=1.4 h.s=0.005 h.m=0.3 r=2.0 ++ x.mesh w=1.4 h.e=0.005 h.m=0.3 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=4 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=4.5 x.h=5.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=4 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=5.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=5.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=5.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=4 x.h=5.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=4.05 x.h=5.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_4 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=1.9 h.s=0.005 h.m=0.4 r=2.0 ++ x.mesh w=1.9 h.e=0.005 h.m=0.4 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=5 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=5.5 x.h=6.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=5 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=6.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=6.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=6.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=5 x.h=6.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=5.05 x.h=6.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_5 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=2.4 h.s=0.005 h.m=0.5 r=2.0 ++ x.mesh w=2.4 h.e=0.005 h.m=0.5 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=6 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=6.5 x.h=7.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=6 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=7.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=7.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=7.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=6 x.h=7.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=6.05 x.h=7.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_10 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=4.9 h.s=0.005 h.m=1 r=2.0 ++ x.mesh w=4.9 h.e=0.005 h.m=1 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=11 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=11.5 x.h=12.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=11 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=12.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=12.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=12.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=11 x.h=12.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=11.05 x.h=12.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +.MODEL M_PMOS_50 numos ++ output stat ++ ++ x.mesh w=0.9 h.e=0.020 h.m=0.2 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=24.9 h.s=0.005 h.m=5 r=2.0 ++ x.mesh w=24.9 h.e=0.005 h.m=5 r=2.0 ++ x.mesh w=0.2 h.e=0.005 h.m=0.02 r=2.0 ++ x.mesh w=0.9 h.s=0.020 h.m=0.2 r=2.0 ++ ++ y.mesh l=-.0200 n=1 ++ y.mesh l=0.0 n=6 ++ y.mesh w=0.15 h.s=0.0001 h.max=.02 r=2.0 ++ y.mesh w=0.45 h.s=0.02 h.max=0.2 r=2.0 ++ y.mesh w=1.40 h.s=0.20 h.max=0.4 r=2.0 ++ ++ region num=1 material=1 y.h=0.0 ++ region num=2 material=2 y.l=0.0 ++ interface dom=2 nei=1 x.l=1 x.h=51 layer.width=0.0 ++ material num=1 oxide ++ material num=2 silicon ++ ++ elec num=1 x.l=51.5 x.h=52.1 y.l=0.0 y.h=0.0 ++ elec num=2 x.l=1 x.h=51 iy.l=1 iy.h=1 ++ elec num=3 x.l=-0.1 x.h=0.5 y.l=0.0 y.h=0.0 ++ elec num=4 x.l=-0.1 x.h=52.1 y.l=2.0 y.h=2.0 ++ ++ doping gauss n.type conc=1.0e17 x.l=-0.1 x.h=52.1 y.l=0.0 ++ + char.l=0.30 ++ doping unif n.type conc=5.0e15 x.l=-0.1 x.h=52.1 y.l=0.0 y.h=2.1 ++ doping gauss p.type conc=4e17 x.l=-0.1 x.h=1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=-0.1 x.h=0.95 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ doping gauss p.type conc=4e17 x.l=51 x.h=52.1 y.l=0.0 y.h=0.0 ++ + char.l=0.16 lat.rotate ratio=0.65 ++ doping gauss p.type conc=1e20 x.l=51.05 x.h=52.1 y.l=0.0 y.h=0.08 ++ + char.l=0.03 lat.rotate ratio=0.65 ++ ++ contact num=2 workf=5.29 ++ models concmob surfmob transmob fieldmob srh auger conctau bgn ++ method ac=direct itlim=10 onec + +** +* BSIM1 NMOS and PMOS 1.0 \um models. +* Gummel-Poon bipolar models. +** +.model M_NSIM_1 nmos level=4 ++vfb= -1.1908 ++phi= .8399 ++k1= 1.5329 ++k2= 193.7322m ++eta= 2m ++muz= 746.0 ++u0= 90.0m ++x2mz= 10.1429 ++x2e= -2.5m ++x3e= 0.2m ++x2u0= -10.0m ++mus= 975.0 ++u1= .20 ++x2ms= 0.0 ++x2u1= 0.0 ++x3ms= 10 ++x3u1= 5.0m ++tox=2.00000e-02 ++cgdo=2.0e-10 ++cgso=2.0e-10 ++cgbo=0.0 ++temp= 27 ++vdd= 7.0 ++xpart ++n0= 1.5686 ++nb= 94.6392m ++nd=0.00000e+00 ++rsh=30.0 cj=7.000e-004 cjsw=4.20e-010 ++js=1.00e-008 pb=0.700e000 ++pbsw=0.8000e000 mj=0.5 mjsw=0.33 ++wdf=0 dell=0.20u + +.model M_PSIM_1 pmos level=4 ++vfb= -1.3674 ++phi= .8414 ++k1= 1.5686 ++k2= 203m ++eta= 2m ++muz= 340.0 ++u0= 35.0m ++x2mz= 6.0 ++x2e= 0.0 ++x3e= -0.2m ++x2u0= -15.0m ++mus= 440.0 ++u1= .38 ++x2ms= 0.0 ++x2u1= 0.0 ++x3ms= -20 ++x3u1= -10.0m ++tox=2.00000e-02 ++cgdo=2.0e-10 ++cgso=2.0e-10 ++cgbo=0.0 ++temp= 27 ++vdd= 5.0 ++xpart ++n0= 1.5686 ++nb= 94.6392m ++nd=0.00000e+00 ++rsh=80.0 cj=7.000e-004 cjsw=4.20e-010 ++js=1.00e-008 pb=0.700e000 ++pbsw=0.8000e000 mj=0.5 mjsw=0.33 ++wdf=0 dell=0.17u + +.model M_GNPN npn ++ is=1.3e-16 ++ nf=1.00 bf=262.5 ikf=25mA vaf=20v ++ nr=1.00 br=97.5 ikr=0.5mA var=1.8v ++ rc=20.0 ++ re=0.09 ++ rb=15.0 ++ ise=4.0e-16 ne=2.1 ++ isc=7.2e-17 nc=2.0 ++ tf=9.4ps itf=26uA xtf=0.5 ++ tr=10ns ++ cje=89.44fF vje=0.95 mje=0.5 ++ cjc=12.82fF vjc=0.73 mjc=0.49 + +.model M_GPNP pnp ++ is=5.8e-17 ++ nf=1.001 bf=96.4 ikf=12mA vaf=29v ++ nr=1.0 br=17.3 ikr=0.2mA var=2.0v ++ rc=50.0 ++ re=0.17 ++ rb=20.0 ++ ise=6.8e-17 ne=2.0 ++ isc=9.0e-17 nc=2.1 ++ tf=27.4ps itf=26uA xtf=0.5 ++ tr=10ns ++ cje=55.36fF vje=0.95 mje=0.58 ++ cjc=11.80fF vjc=0.72 mjc=0.46 diff --git a/Windows/spice/examples/cider/parallel/bicmpd.cir b/Windows/spice/examples/cider/parallel/bicmpd.cir new file mode 100644 index 00000000..be26e40d --- /dev/null +++ b/Windows/spice/examples/cider/parallel/bicmpd.cir @@ -0,0 +1,26 @@ +BICMOS INVERTER PULLDOWN CIRCUIT + +VSS 2 0 0V + +VIN 3 2 0V (PULSE 0.0V 4.2V 0NS 1NS 1NS 9NS 20NS) + +M1 8 3 5 11 M_NMOS_1 W=4U L=1U +VD 4 8 0V +VBK 11 2 0V + +Q1 10 7 9 M_NPNS AREA=8 +VC 4 10 0V +VB 5 7 0V +VE 9 2 0V + +CL 4 6 1PF +VL 6 2 0V + +.IC V(10)=5.0V V(7)=0.0V +.TRAN 0.1NS 5NS 0NS 0.1NS +.PLOT TRAN I(VIN) + +.INCLUDE BICMOS.LIB + +.OPTIONS ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/parallel/bicmpu.cir b/Windows/spice/examples/cider/parallel/bicmpu.cir new file mode 100644 index 00000000..7067ce14 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/bicmpu.cir @@ -0,0 +1,24 @@ +BICMOS INVERTER PULLUP CIRCUIT + +VDD 1 0 5.0V +VSS 2 0 0.0V + +VIN 3 0 0.75V + +VC 1 11 0.0V +VB 5 15 0.0V + +Q1 11 15 4 M_NPNS AREA=8 +M1 5 3 1 1 M_PMOS_1 W=10U L=1U + +CL 4 0 5.0PF + +.IC V(4)=0.75V V(5)=0.0V + +.INCLUDE BICMOS.LIB + +.TRAN 0.5NS 4.0NS +.PRINT TRAN V(3) V(4) + +.OPTION ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/parallel/clkfeed.cir b/Windows/spice/examples/cider/parallel/clkfeed.cir new file mode 100644 index 00000000..d0a06f15 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/clkfeed.cir @@ -0,0 +1,34 @@ +SWITCHED CURRENT CELL - CLOCK FEEDTHROUGH + +VDD 1 0 5.0V +VSS 2 0 0.0V + +IIN 13 0 0.0 +VIN 13 3 0.0 +VL 4 0 2.5V +VCK 6 0 5.0V PULSE 5.0V 0.0V 5.0NS 5NS 5NS 20NS 50NS + +M1 3 3 2 2 M_NMOS_5 W=5U L=5U +M2 4 5 2 2 M_NMOS_5 W=10U L=5U +M3 23 26 25 22 M_NMOS_5 W=5U L=5U +RLK1 3 0 100G +RLK2 5 0 100G +VD 3 23 0.0V +VG 6 26 0.0V +VS 5 25 0.0V +VB 2 22 0.0V + +M4 7 7 1 1 M_PMOS_IDEAL W=100U L=1U +M5 3 7 1 1 M_PMOS_IDEAL W=100U L=1U +M6 4 7 1 1 M_PMOS_IDEAL W=200U L=1U +IREF 7 0 50UA + +****** MODELS ****** +.MODEL M_PMOS_IDEAL PMOS VTO=-1.0V KP=100U + +.INCLUDE BICMOS.LIB + +.TRAN 0.1NS 50NS + +.OPTIONS ACCT BYPASS=1 METHOD=GEAR +.END diff --git a/Windows/spice/examples/cider/parallel/cmosamp.cir b/Windows/spice/examples/cider/parallel/cmosamp.cir new file mode 100644 index 00000000..f88115b5 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/cmosamp.cir @@ -0,0 +1,29 @@ +CMOS 2-STAGE OPERATIONAL AMPLIFIER + +VDD 1 0 2.5V +VSS 2 0 -2.5V + +IBIAS 9 0 100UA + +VPL 3 0 0.0V AC 0.5V +VMI 4 0 0.0V AC 0.5V 180 + +M1 6 3 5 5 M_PMOS_1 W=15U L=1U +M2 7 4 5 5 M_PMOS_1 W=15U L=1U +M3 6 6 2 2 M_NMOS_1 W=7.5U L=1U +M4 7 6 2 2 M_NMOS_1 W=7.5U L=1U +M5 8 7 2 2 M_NMOS_1 W=15U L=1U +M6 9 9 1 1 M_PMOS_1 W=15U L=1U +M7 5 9 1 1 M_PMOS_1 W=15U L=1U +M8 8 9 1 1 M_PMOS_1 W=15U L=1U + +*CC 7 8 0.1PF + +.INCLUDE BICMOS.LIB + +*.OP +*.AC DEC 10 1K 100G +.DC VPL -5MV 5MV 0.1MV + +.OPTIONS ACCT BYPASS=1 METHOD=GEAR +.END diff --git a/Windows/spice/examples/cider/parallel/eclinv.cir b/Windows/spice/examples/cider/parallel/eclinv.cir new file mode 100644 index 00000000..a63c1c14 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/eclinv.cir @@ -0,0 +1,30 @@ +ECL INVERTER +*** (FROM MEINERZHAGEN ET AL.) + +VCC 1 0 0.0V +VEE 2 0 -5.2V + +VIN 3 0 -1.25V +VRF 4 0 -1.25V + +*** INPUT STAGE +Q1 5 3 9 M_NPNS AREA=8 +Q2 6 4 9 M_NPNS AREA=8 +R1 1 5 662 +R2 1 6 662 +R3 9 2 2.65K + +*** OUTPUT BUFFERS +Q3 1 5 7 M_NPNS AREA=8 +Q4 1 6 8 M_NPNS AREA=8 +R4 7 2 4.06K +R5 8 2 4.06K + +*** MODEL LIBRARY +.INCLUDE BICMOS.LIB + +.DC VIN -2.00 0.001 0.05 +.PLOT DC V(7) V(8) + +.OPTIONS ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/parallel/ecpal.cir b/Windows/spice/examples/cider/parallel/ecpal.cir new file mode 100644 index 00000000..4485a442 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/ecpal.cir @@ -0,0 +1,19 @@ +EMITTER COUPLED PAIR WITH ACTIVE LOAD + +VCC 1 0 5V +VEE 2 0 0V +VINP 4 0 2.99925V AC 0.5V +VINM 7 0 3V AC 0.5V 180 +IEE 5 2 0.1MA +Q1 3 4 5 M_NPNS AREA=8 +Q2 6 7 5 M_NPNS AREA=8 +Q3 3 3 1 M_PNPS AREA=8 +Q4 6 3 1 M_PNPS AREA=8 + +.AC DEC 10 10K 100G +.PLOT AC VDB(6) + +.INCLUDE BICMOS.LIB + +.OPTIONS ACCT RELTOL=1E-6 +.END diff --git a/Windows/spice/examples/cider/parallel/foobar b/Windows/spice/examples/cider/parallel/foobar new file mode 100644 index 00000000..1e5e7b73 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/foobar @@ -0,0 +1,10 @@ +\section*{BICMPD Benchmark} +\section*{BICMPU Benchmark} +\section*{CLKFEED Benchmark} +\section*{CMOSAMP Benchmark} +\section*{ECLINV Benchmark} +\section*{ECPAL Benchmark} +\section*{GMAMP Benchmark} +\section*{LATCH Benchmark} +\section*{PPEF Benchmarks} +\section*{RINGOSC Benchmarks} diff --git a/Windows/spice/examples/cider/parallel/gmamp.cir b/Windows/spice/examples/cider/parallel/gmamp.cir new file mode 100644 index 00000000..e570beca --- /dev/null +++ b/Windows/spice/examples/cider/parallel/gmamp.cir @@ -0,0 +1,34 @@ +BICMOS 3-STAGE AMPLIFIER +*** IN GRAY & MEYER, 3RD ED. P.266, PROB. 3.12, 8.19 + +VDD 1 0 5.0V +VSS 2 0 0.0V + +*** VOLTAGE INPUT +*VIN 13 0 0.0V AC 1V +*CIN 13 3 1UF + +*** CURRENT INPUT +IIN 3 0 0.0 AC 1.0 + +M1 4 3 2 2 M_NMOS_1 W=300U L=1U +M2 7 7 2 2 M_NMOS_1 W=20U L=1U + +Q1 6 5 4 M_NPNS AREA=40 +Q2 5 5 7 M_NPNS AREA=40 +Q3 1 6 8 M_NPNS AREA=40 + +RL1 1 4 1K +RL2 1 6 10K +RB1 1 5 10K +RL3 8 2 1K +RF1 3 8 30K + +*** NUMERICAL MODEL LIBRARY *** +.INCLUDE BICMOS.LIB + +.AC DEC 10 100KHZ 100GHZ +.PLOT AC VDB(8) + +.OPTIONS ACCT BYPASS=1 KEEPOPINFO +.END diff --git a/Windows/spice/examples/cider/parallel/latch.cir b/Windows/spice/examples/cider/parallel/latch.cir new file mode 100644 index 00000000..3ad63335 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/latch.cir @@ -0,0 +1,46 @@ +STATIC LATCH +*** IC=1MA, RE6=3K +*** SPICE ORIGINAL 1-7-80, CIDER REVISED 4-16-93 + +*** BIAS CIRCUIT +*** RESISTORS +RCC2 6 8 3.33K +REE2 9 0 200 +*** TRANSISTORS +Q1 6 8 4 M_NPN1D AREA=8 +Q2 8 4 9 M_NPN1D AREA=8 + +*** MODELS +.INCLUDE BICMOS.LIB + +*** SOURCES +VCC 6 0 5V +VREF 3 0 2.5V +VRSET 1 0 PULSE(2V 3V 0.1NS 0.1NS 0.1NS 0.9NS 4NS) +VSET 7 0 PULSE(2V 3V 2.1NS 0.1NS 0.1NS 0.9NS 4NS) + +*** LATCH +X1 1 2 3 4 5 6 ECLNOR2 +X2 5 7 3 4 2 6 ECLNOR2 + +*** SUBCIRCUITS +.SUBCKT ECLNOR2 1 2 3 4 5 6 +** RESISTORS +RS 6 11 520 +RC2 11 10 900 +RE4 12 0 200 +RE6 5 0 6K +** TRANSISTORS +Q1 9 1 8 M_NPN1D AREA=8 +Q2 9 2 8 M_NPN1D AREA=8 +Q3 11 3 8 M_NPN1D AREA=8 +Q4 8 4 12 M_NPN1D AREA=8 +Q5 10 10 9 M_NPN1D AREA=8 +Q6 6 9 5 M_NPN1D AREA=8 +.ENDS ECLNOR2 + +*** CONTROL CARDS +.TRAN 0.01NS 8NS +.PRINT TRAN V(1) V(7) V(5) V(2) +.OPTIONS ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/parallel/ppef.1d.cir b/Windows/spice/examples/cider/parallel/ppef.1d.cir new file mode 100644 index 00000000..8690c665 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/ppef.1d.cir @@ -0,0 +1,25 @@ +PUSH-PULL EMITTER FOLLOWER - ONE-DIMENSIONAL MODELS + +VCC 1 0 5.0V +VEE 2 0 -5.0V + +VIN 3 0 0.0V (SIN 0.0V 0.1V 1KHZ) AC 1 +VBU 13 3 0.7V +VBL 3 23 0.7V + +RL 4 44 50 +VLD 44 0 0V + +Q1 5 13 4 M_NPN1D AREA=40 +Q2 4 5 1 M_PNP1D AREA=200 + +Q3 6 23 4 M_PNP1D AREA=100 +Q4 4 6 2 M_NPN1D AREA=80 + +.INCLUDE BICMOS.LIB + +.TRAN 0.01MS 1.00001MS 0US 0.01MS +.PLOT TRAN V(4) + +.OPTIONS ACCT BYPASS=1 TEMP=26.85OC RELTOL=1E-5 +.END diff --git a/Windows/spice/examples/cider/parallel/ppef.2d.cir b/Windows/spice/examples/cider/parallel/ppef.2d.cir new file mode 100644 index 00000000..07fa10fb --- /dev/null +++ b/Windows/spice/examples/cider/parallel/ppef.2d.cir @@ -0,0 +1,25 @@ +PUSH-PULL EMITTER FOLLOWER - TWO-DIMENSIONAL MODELS + +VCC 1 0 5.0V +VEE 2 0 -5.0V + +VIN 3 0 0.0V (SIN 0.0V 0.1V 1KHZ) AC 1 +VBU 13 3 0.7V +VBL 3 23 0.7V + +RL 4 44 50 +VLD 44 0 0V + +Q1 5 13 4 M_NPNS AREA=40 +Q2 4 5 1 M_PNPS AREA=200 + +Q3 6 23 4 M_PNPS AREA=100 +Q4 4 6 2 M_NPNS AREA=80 + +.INCLUDE BICMOS.LIB + +.TRAN 0.01MS 1.00001MS 0US 0.01MS +.PLOT TRAN V(4) + +.OPTIONS ACCT BYPASS=1 TEMP=26.85OC RELTOL=1E-5 +.END diff --git a/Windows/spice/examples/cider/parallel/readme b/Windows/spice/examples/cider/parallel/readme new file mode 100644 index 00000000..077c78f6 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/readme @@ -0,0 +1,3 @@ +This directory contains the additional CIDER parallel-version benchmarks +used in the thesis "Design-Oriented Mixed-Level Circuit and Device Simulation" +by David A. Gates. diff --git a/Windows/spice/examples/cider/parallel/ringosc.1u.cir b/Windows/spice/examples/cider/parallel/ringosc.1u.cir new file mode 100644 index 00000000..2304c4eb --- /dev/null +++ b/Windows/spice/examples/cider/parallel/ringosc.1u.cir @@ -0,0 +1,39 @@ +CMOS RING OSCILLATOR - 1UM DEVICES + +VDD 1 0 5.0V +VSS 2 0 0.0V + +X1 1 2 3 4 INV +X2 1 2 4 5 INV +X3 1 2 5 6 INV +X4 1 2 6 7 INV +X5 1 2 7 8 INV +X6 1 2 8 9 INV +X7 1 2 9 3 INV + +.IC V(3)=0.0V V(4)=2.5V V(5)=5.0V ++ V(6)=0.0V V(7)=5.0V V(8)=0.0V V(9)=5.0V + +.SUBCKT INV 1 2 3 4 +* VDD VSS VIN VOUT +M1 14 13 15 16 M_PMOS_1 W=6.0U +M2 24 23 25 26 M_NMOS_1 W=3.0U + +VGP 3 13 0.0V +VDP 4 14 0.0V +VSP 1 15 0.0V +VBP 1 16 0.0V + +VGN 3 23 0.0V +VDN 4 24 0.0V +VSN 2 25 0.0V +VBN 2 26 0.0V +.ENDS INV + +.INCLUDE BICMOS.LIB + +.TRAN 0.1NS 1NS +.PRINT TRAN V(3) V(4) V(5) + +.OPTIONS ACCT BYPASS=1 METHOD=GEAR +.END diff --git a/Windows/spice/examples/cider/parallel/ringosc.2u.cir b/Windows/spice/examples/cider/parallel/ringosc.2u.cir new file mode 100644 index 00000000..c79885ab --- /dev/null +++ b/Windows/spice/examples/cider/parallel/ringosc.2u.cir @@ -0,0 +1,114 @@ +CMOS RING OSCILLATOR - 2UM DEVICES + +VDD 1 0 5.0V +VSS 2 0 0.0V + +X1 1 2 3 4 INV +X2 1 2 4 5 INV +X3 1 2 5 6 INV +X4 1 2 6 7 INV +X5 1 2 7 8 INV +X6 1 2 8 9 INV +X7 1 2 9 3 INV + +.IC V(3)=0.0V V(4)=2.5V V(5)=5.0V V(6)=0.0V ++ V(7)=5.0V V(8)=0.0V V(9)=5.0V + +.SUBCKT INV 1 2 3 4 +* VDD VSS VIN VOUT +M1 14 13 15 16 M_PMOS W=6.0U +M2 24 23 25 26 M_NMOS W=3.0U + +VGP 3 13 0.0V +VDP 4 14 0.0V +VSP 1 15 0.0V +VBP 1 16 0.0V + +VGN 3 23 0.0V +VDN 4 24 0.0V +VSN 2 25 0.0V +VBN 2 26 0.0V +.ENDS INV + +.MODEL M_NMOS NUMOS ++ X.MESH L=0.0 N=1 ++ X.MESH L=0.6 N=4 ++ X.MESH L=0.7 N=5 ++ X.MESH L=1.0 N=7 ++ X.MESH L=1.2 N=11 ++ X.MESH L=3.2 N=21 ++ X.MESH L=3.4 N=25 ++ X.MESH L=3.7 N=27 ++ X.MESH L=3.8 N=28 ++ X.MESH L=4.4 N=31 ++ ++ Y.MESH L=-.05 N=1 ++ Y.MESH L=0.0 N=5 ++ Y.MESH L=.05 N=9 ++ Y.MESH L=0.3 N=14 ++ Y.MESH L=2.0 N=19 ++ ++ REGION NUM=1 MATERIAL=1 Y.L=0.0 ++ MATERIAL NUM=1 SILICON ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ ++ REGION NUM=2 MATERIAL=2 Y.H=0.0 X.L=0.7 X.H=3.7 ++ MATERIAL NUM=2 OXIDE ++ ++ ELEC NUM=1 X.L=3.8 X.H=4.4 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=2 X.L=0.7 X.H=3.7 IY.L=1 IY.H=1 ++ ELEC NUM=3 X.L=0.0 X.H=0.6 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=4 X.L=0.0 X.H=4.4 Y.L=2.0 Y.H=2.0 ++ ++ DOPING UNIF P.TYPE CONC=2.5E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=2.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=0.05 ++ DOPING UNIF N.TYPE CONC=1E20 X.L=0.0 X.H=1.1 Y.L=0.0 Y.H=0.2 ++ DOPING UNIF N.TYPE CONC=1E20 X.L=3.3 X.H=4.4 Y.L=0.0 Y.H=0.2 ++ ++ MODELS CONCMOB FIELDMOB BGN SRH CONCTAU ++ METHOD AC=DIRECT ONEC ++ OUTPUT ^ALL.DEBUG + +.MODEL M_PMOS NUMOS ++ X.MESH L=0.0 N=1 ++ X.MESH L=0.6 N=4 ++ X.MESH L=0.7 N=5 ++ X.MESH L=1.0 N=7 ++ X.MESH L=1.2 N=11 ++ X.MESH L=3.2 N=21 ++ X.MESH L=3.4 N=25 ++ X.MESH L=3.7 N=27 ++ X.MESH L=3.8 N=28 ++ X.MESH L=4.4 N=31 ++ ++ Y.MESH L=-.05 N=1 ++ Y.MESH L=0.0 N=5 ++ Y.MESH L=.05 N=9 ++ Y.MESH L=0.3 N=14 ++ Y.MESH L=2.0 N=19 ++ ++ REGION NUM=1 MATERIAL=1 Y.L=0.0 ++ MATERIAL NUM=1 SILICON ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ ++ REGION NUM=2 MATERIAL=2 Y.H=0.0 X.L=0.7 X.H=3.7 ++ MATERIAL NUM=2 OXIDE ++ ++ ELEC NUM=1 X.L=3.8 X.H=4.4 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=2 X.L=0.7 X.H=3.7 IY.L=1 IY.H=1 ++ ELEC NUM=3 X.L=0.0 X.H=0.6 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=4 X.L=0.0 X.H=4.4 Y.L=2.0 Y.H=2.0 ++ ++ DOPING UNIF N.TYPE CONC=1E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=2.0 ++ DOPING UNIF P.TYPE CONC=3E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=0.05 ++ DOPING UNIF P.TYPE CONC=1E20 X.L=0.0 X.H=1.1 Y.L=0.0 Y.H=0.2 ++ DOPING UNIF P.TYPE CONC=1E20 X.L=3.3 X.H=4.4 Y.L=0.0 Y.H=0.2 ++ ++ MODELS CONCMOB FIELDMOB BGN SRH CONCTAU ++ METHOD AC=DIRECT ONEC ++ OUTPUT ^ALL.DEBUG + +.TRAN 0.1NS 5.0NS +.PRINT V(4) +.OPTIONS ACCT BYPASS=1 METHOD=GEAR +.END diff --git a/Windows/spice/examples/cider/resistor/gaasres.cir b/Windows/spice/examples/cider/resistor/gaasres.cir new file mode 100644 index 00000000..c35d0ddc --- /dev/null +++ b/Windows/spice/examples/cider/resistor/gaasres.cir @@ -0,0 +1,30 @@ +Gallium Arsenide Resistor + +* This transient simulation demonstrates the effects of velocity overshoot +* and velocity saturation at high lateral electric fields. +* Do not try to do DC analysis of this resistor. It will not converge +* because of the peculiar characteristics of the GaAs velocity-field +* relation. In some cases, problems can arise in transient simulation +* as well. + +VPP 1 0 1v PWL 0s 0.0v 10s 1v +VNN 2 0 0.0v +D1 1 2 M_RES AREA=1 + +.MODEL M_RES numd level=1 ++ options resistor defa=1p ++ x.mesh loc=0.0 num=1 ++ x.mesh loc=1.0 num=101 ++ domain num=1 material=1 ++ material num=1 gaas ++ doping unif n.type conc=2.5e16 ++ models fieldmob srh auger conctau ++ method ac=direct + +*.OP +*.DC VPP 0.0v 10.01v 0.1v +.TRAN 1s 10.001s 0s 0.1s +.PRINT I(VPP) + +.OPTION ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/resistor/sires.cir b/Windows/spice/examples/cider/resistor/sires.cir new file mode 100644 index 00000000..45e2aa12 --- /dev/null +++ b/Windows/spice/examples/cider/resistor/sires.cir @@ -0,0 +1,26 @@ +Silicon Resistor + +* This simulation demonstrates the effects of velocity saturation at +* high lateral electric fields. + +VPP 1 0 10v PWL 0s 0.0v 100s 10v +VNN 2 0 0.0v +D1 1 2 M_RES AREA=1 + +.MODEL M_RES numd level=1 ++ options resistor defa=1p ++ x.mesh loc=0.0 num=1 ++ x.mesh loc=1.0 num=101 ++ domain num=1 material=1 ++ material num=1 silicon ++ doping unif n.type conc=2.5e16 ++ models bgn srh conctau auger concmob fieldmob ++ method ac=direct + +*.OP +.DC VPP 0.0v 10.01v 0.1v +*.TRAN 1s 100.001s 0s 0.2s +.PRINT I(VPP) + +.OPTION ACCT BYPASS=1 RELTOL=1e-12 +.END diff --git a/Windows/spice/examples/cider/serial/astable.cir b/Windows/spice/examples/cider/serial/astable.cir new file mode 100644 index 00000000..c04c6bba --- /dev/null +++ b/Windows/spice/examples/cider/serial/astable.cir @@ -0,0 +1,30 @@ +ASTABLE MULTIVIBRATOR + +VIN 5 0 DC 0 PULSE(0 5 0 1US 1US 100US 100US) +VCC 6 0 5.0 +RC1 6 1 1K +RC2 6 2 1K +RB1 6 3 30K +RB2 5 4 30K +C1 1 4 150PF +C2 2 3 150PF +Q1 1 3 0 QMOD AREA = 100P +Q2 2 4 0 QMOD AREA = 100P + +.OPTION ACCT BYPASS=1 +.TRAN 0.05US 8US 0US 0.05US +.PRINT TRAN V(1) V(2) V(3) V(4) + +.MODEL QMOD NBJT LEVEL=1 ++ X.MESH NODE=1 LOC=0.0 ++ X.MESH NODE=61 LOC=3.0 ++ REGION NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17 ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5 ++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0 ++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB ++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25 + +.END diff --git a/Windows/spice/examples/cider/serial/charge.cir b/Windows/spice/examples/cider/serial/charge.cir new file mode 100644 index 00000000..c4c689b6 --- /dev/null +++ b/Windows/spice/examples/cider/serial/charge.cir @@ -0,0 +1,53 @@ +MOS CHARGE PUMP + +VIN 4 0 DC 0V PULSE 0 5 15NS 5NS 5NS 50NS 100NS +VDD 5 6 DC 0V PULSE 0 5 25NS 5NS 5NS 50NS 100NS +VBB 0 7 DC 0V PULSE 0 5 0NS 5NS 5NS 50NS 100NS +RD 6 2 10K +M1 5 4 3 7 MMOD W=100UM +VS 3 2 0 +VC 2 1 0 +C2 1 0 10PF + +.IC V(3)=1.0 +.TRAN 2NS 200NS +.OPTIONS ACCT BYPASS=1 +.PRINT TRAN V(1) V(2) + +.MODEL MMOD NUMOS ++ X.MESH N=1 L=0 ++ X.MESH N=3 L=0.4 ++ X.MESH N=7 L=0.6 ++ X.MESH N=15 L=1.4 ++ X.MESH N=19 L=1.6 ++ X.MESH N=21 L=2.0 ++ ++ Y.MESH N=1 L=0 ++ Y.MESH N=4 L=0.015 ++ Y.MESH N=8 L=0.05 ++ Y.MESH N=12 L=0.25 ++ Y.MESH N=14 L=0.35 ++ Y.MESH N=17 L=0.5 ++ Y.MESH N=21 L=1.0 ++ ++ REGION NUM=1 MATERIAL=1 Y.L=0.015 ++ MATERIAL NUM=1 SILICON ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ ++ REGION NUM=2 MATERIAL=2 Y.H=0.015 X.L=0.5 X.H=1.5 ++ MATERIAL NUM=2 OXIDE ++ ++ ELEC NUM=1 IX.L=18 IX.H=21 IY.L=4 IY.H=4 ++ ELEC NUM=2 IX.L=5 IX.H=17 IY.L=1 IY.H=1 ++ ELEC NUM=3 IX.L=1 IX.H=4 IY.L=4 IY.H=4 ++ ELEC NUM=4 IX.L=1 IX.H=21 IY.L=21 IY.H=21 ++ ++ DOPING UNIF N.TYPE CONC=1E18 X.L=0.0 X.H=0.5 Y.L=0.015 Y.H=0.25 ++ DOPING UNIF N.TYPE CONC=1E18 X.L=1.5 X.H=2.0 Y.L=0.015 Y.H=0.25 ++ DOPING UNIF P.TYPE CONC=1E15 X.L=0.0 X.H=2.0 Y.L=0.015 Y.H=1.0 ++ DOPING UNIF P.TYPE CONC=1.3E17 X.L=0.5 X.H=1.5 Y.L=0.015 Y.H=0.05 ++ ++ MODELS CONCMOB FIELDMOB ++ METHOD ONEC + +.END diff --git a/Windows/spice/examples/cider/serial/colposc.cir b/Windows/spice/examples/cider/serial/colposc.cir new file mode 100644 index 00000000..b7d14ce9 --- /dev/null +++ b/Windows/spice/examples/cider/serial/colposc.cir @@ -0,0 +1,29 @@ +COLPITT'S OSCILLATOR CIRCUIT + +R1 1 0 1 +Q1 2 1 3 QMOD AREA = 100P +VCC 4 0 5 +RL 4 2 750 +C1 2 3 500P +C2 4 3 4500P +L1 4 2 5UH +RE 3 6 4.65K +VEE 6 0 DC -15 PWL 0 -15 1E-9 -10 + +.TRAN 30N 12U +.PRINT TRAN V(2) + +.MODEL QMOD NBJT LEVEL=1 ++ X.MESH NODE=1 LOC=0.0 ++ X.MESH NODE=61 LOC=3.0 ++ REGION NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17 ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5 ++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0 ++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB ++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25 + +.OPTIONS ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/serial/dbridge.cir b/Windows/spice/examples/cider/serial/dbridge.cir new file mode 100644 index 00000000..052ae4f0 --- /dev/null +++ b/Windows/spice/examples/cider/serial/dbridge.cir @@ -0,0 +1,30 @@ +DIODE BRIDGE RECTIFIER + +VLINE 3 4 0.0V SIN 0V 10V 60HZ +VGRND 2 0 0.0V +D1 3 1 M_PN AREA=100 +D2 4 1 M_PN AREA=100 +D3 2 3 M_PN AREA=100 +D4 2 4 M_PN AREA=100 +RL 1 2 1.0K + +.MODEL M_PN NUMD LEVEL=1 ++ *************************************** ++ *** ONE-DIMENSIONAL NUMERICAL DIODE *** ++ *************************************** ++ OPTIONS DEFA=1P ++ X.MESH LOC=0.0 N=1 ++ X.MESH LOC=30.0 N=201 ++ DOMAIN NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON ++ MOBILITY MAT=1 CONCMOD=CT FIELDMOD=CT ++ DOPING GAUSS P.TYPE CONC=1E20 X.L=0.0 X.H=0.0 CHAR.L=1.0 ++ DOPING UNIF N.TYPE CONC=1E14 X.L=0.0 X.H=30.0 ++ DOPING GAUSS N.TYPE CONC=5E19 X.L=30.0 X.H=30.0 CHAR.L=2.0 ++ MODELS BGN ^AVAL SRH AUGER CONCTAU CONCMOB FIELDMOB ++ METHOD AC=DIRECT + +.OPTION ACCT BYPASS=1 METHOD=GEAR +.TRAN 0.5MS 50MS +.PRINT I(VLINE) +.END diff --git a/Windows/spice/examples/cider/serial/invchain.cir b/Windows/spice/examples/cider/serial/invchain.cir new file mode 100644 index 00000000..c05513a0 --- /dev/null +++ b/Windows/spice/examples/cider/serial/invchain.cir @@ -0,0 +1,34 @@ +4 STAGE RTL INVERTER CHAIN + +VIN 1 0 DC 0V PWL 0NS 0V 1NS 5V +VCC 12 0 DC 5.0V +RC1 12 3 2.5K +RB1 1 2 8K +Q1 3 2 0 QMOD AREA = 100P +RB2 3 4 8K +RC2 12 5 2.5K +Q2 5 4 0 QMOD AREA = 100P +RB3 5 6 8K +RC3 12 7 2.5K +Q3 7 6 0 QMOD AREA = 100P +RB4 7 8 8K +RC4 12 9 2.5K +Q4 9 8 0 QMOD AREA = 100P + +.PRINT TRAN V(3) V(5) V(9) +.TRAN 1E-9 10E-9 + +.MODEL QMOD NBJT LEVEL=1 ++ X.MESH NODE=1 LOC=0.0 ++ X.MESH NODE=61 LOC=3.0 ++ REGION NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17 ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5 ++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0 ++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB ++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25 + +.OPTION ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/serial/meclgate.cir b/Windows/spice/examples/cider/serial/meclgate.cir new file mode 100644 index 00000000..7f5e88ba --- /dev/null +++ b/Windows/spice/examples/cider/serial/meclgate.cir @@ -0,0 +1,70 @@ +MOTOROLA MECL III ECL GATE +*.DC VIN -2.0 0 0.02 +.TRAN 0.2NS 20NS +VEE 22 0 -6.0 +VIN 1 0 PULSE -0.8 -1.8 0.2NS 0.2NS 0.2NS 10NS 20NS +RS 1 2 50 +Q1 4 2 6 QMOD AREA = 100P +Q2 4 3 6 QMOD AREA = 100P +Q3 5 7 6 QMOD AREA = 100P +Q4 0 8 7 QMOD AREA = 100P + +D1 8 9 DMOD +D2 9 10 DMOD + +RP1 3 22 50K +RC1 0 4 100 +RC2 0 5 112 +RE 6 22 380 +R1 7 22 2K +R2 0 8 350 +R3 10 22 1958 + +Q5 0 5 11 QMOD AREA = 100P +Q6 0 4 12 QMOD AREA = 100P + +RP2 11 22 560 +RP3 12 22 560 + +Q7 13 12 15 QMOD AREA = 100P +Q8 14 16 15 QMOD AREA = 100P + +RE2 15 22 380 +RC3 0 13 100 +RC4 0 14 112 + +Q9 0 17 16 QMOD AREA = 100P + +R4 16 22 2K +R5 0 17 350 +D3 17 18 DMOD +D4 18 19 DMOD +R6 19 22 1958 + +Q10 0 14 20 QMOD AREA = 100P +Q11 0 13 21 QMOD AREA = 100P + +RP4 20 22 560 +RP5 21 22 560 + +.MODEL DMOD D RS=40 TT=0.1NS CJO=0.9PF N=1 IS=1E-14 EG=1.11 VJ=0.8 M=0.5 + +.MODEL QMOD NBJT LEVEL=1 ++ X.MESH NODE=1 LOC=0.0 ++ X.MESH NODE=10 LOC=0.9 ++ X.MESH NODE=20 LOC=1.1 ++ X.MESH NODE=30 LOC=1.4 ++ X.MESH NODE=40 LOC=1.6 ++ X.MESH NODE=61 LOC=3.0 ++ REGION NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17 ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5 ++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0 ++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB ++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25 + +.OPTIONS ACCT BYPASS=1 +.PRINT TRAN V(12) V(21) +.END diff --git a/Windows/spice/examples/cider/serial/nmosinv.cir b/Windows/spice/examples/cider/serial/nmosinv.cir new file mode 100644 index 00000000..b6fa11ab --- /dev/null +++ b/Windows/spice/examples/cider/serial/nmosinv.cir @@ -0,0 +1,51 @@ +RESISTIVE LOAD NMOS INVERTER +VIN 1 0 PWL 0 0.0 2NS 5 +VDD 3 0 DC 5.0 +RD 3 2 2.5K +M1 2 1 4 5 MMOD W=10UM +CL 2 0 2PF +VB 5 0 0 +VS 4 0 0 + +.MODEL MMOD NUMOS ++ X.MESH L=0.0 N=1 ++ X.MESH L=0.6 N=4 ++ X.MESH L=0.7 N=5 ++ X.MESH L=1.0 N=7 ++ X.MESH L=1.2 N=11 ++ X.MESH L=3.2 N=21 ++ X.MESH L=3.4 N=25 ++ X.MESH L=3.7 N=27 ++ X.MESH L=3.8 N=28 ++ X.MESH L=4.4 N=31 ++ ++ Y.MESH L=-.05 N=1 ++ Y.MESH L=0.0 N=5 ++ Y.MESH L=.05 N=9 ++ Y.MESH L=0.3 N=14 ++ Y.MESH L=2.0 N=19 ++ ++ REGION NUM=1 MATERIAL=1 Y.L=0.0 ++ MATERIAL NUM=1 SILICON ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ ++ REGION NUM=2 MATERIAL=2 Y.H=0.0 X.L=0.7 X.H=3.7 ++ MATERIAL NUM=2 OXIDE ++ ++ ELEC NUM=1 X.L=3.8 X.H=4.4 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=2 X.L=0.7 X.H=3.7 IY.L=1 IY.H=1 ++ ELEC NUM=3 X.L=0.0 X.H=0.6 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=4 X.L=0.0 X.H=4.4 Y.L=2.0 Y.H=2.0 ++ ++ DOPING UNIF P.TYPE CONC=2.5E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=2.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=0.05 ++ DOPING UNIF N.TYPE CONC=1E20 X.L=0.0 X.H=1.1 Y.L=0.0 Y.H=0.2 ++ DOPING UNIF N.TYPE CONC=1E20 X.L=3.3 X.H=4.4 Y.L=0.0 Y.H=0.2 ++ ++ MODELS CONCMOB FIELDMOB ++ METHOD AC=DIRECT ONEC + +.TRAN 0.2NS 30NS +.OPTIONS ACCT BYPASS=1 +.PRINT TRAN V(1) V(2) +.END diff --git a/Windows/spice/examples/cider/serial/pass.cir b/Windows/spice/examples/cider/serial/pass.cir new file mode 100644 index 00000000..a15a6f61 --- /dev/null +++ b/Windows/spice/examples/cider/serial/pass.cir @@ -0,0 +1,55 @@ +TURNOFF TRANSIENT OF PASS TRANSISTOR + +M1 11 2 3 4 MMOD W=20UM +CS 1 0 6.0PF +CL 3 0 6.0PF +R1 3 6 200K +VIN 6 0 DC 0 +VDRN 1 11 DC 0 +VG 2 0 DC 5 PWL 0 5 0.1N 0 1 0 +VB 4 0 DC 0.0 + +.TRAN 0.05NS 0.2NS 0.0NS 0.05NS +.PRINT TRAN V(1) I(VDRN) +.IC V(1)=0 V(3)=0 +.OPTION ACCT BYPASS=1 + +.MODEL MMOD NUMOS ++ X.MESH L=0.0 N=1 ++ X.MESH L=0.6 N=4 ++ X.MESH L=0.7 N=5 ++ X.MESH L=1.0 N=7 ++ X.MESH L=1.2 N=11 ++ X.MESH L=3.2 N=21 ++ X.MESH L=3.4 N=25 ++ X.MESH L=3.7 N=27 ++ X.MESH L=3.8 N=28 ++ X.MESH L=4.4 N=31 ++ ++ Y.MESH L=-.05 N=1 ++ Y.MESH L=0.0 N=5 ++ Y.MESH L=.05 N=9 ++ Y.MESH L=0.3 N=14 ++ Y.MESH L=2.0 N=19 ++ ++ REGION NUM=1 MATERIAL=1 Y.L=0.0 ++ MATERIAL NUM=1 SILICON ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ ++ REGION NUM=2 MATERIAL=2 Y.H=0.0 X.L=0.7 X.H=3.7 ++ MATERIAL NUM=2 OXIDE ++ ++ ELEC NUM=1 X.L=3.8 X.H=4.4 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=2 X.L=0.7 X.H=3.7 IY.L=1 IY.H=1 ++ ELEC NUM=3 X.L=0.0 X.H=0.6 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=4 X.L=0.0 X.H=4.4 Y.L=2.0 Y.H=2.0 ++ ++ DOPING UNIF P.TYPE CONC=2.5E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=2.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=4.4 Y.L=0.0 Y.H=0.05 ++ DOPING UNIF N.TYPE CONC=1E20 X.L=0.0 X.H=1.1 Y.L=0.0 Y.H=0.2 ++ DOPING UNIF N.TYPE CONC=1E20 X.L=3.3 X.H=4.4 Y.L=0.0 Y.H=0.2 ++ ++ MODELS CONCMOB FIELDMOB ++ METHOD AC=DIRECT ONEC + +.END diff --git a/Windows/spice/examples/cider/serial/pullup.cir b/Windows/spice/examples/cider/serial/pullup.cir new file mode 100644 index 00000000..a4d7a4d1 --- /dev/null +++ b/Windows/spice/examples/cider/serial/pullup.cir @@ -0,0 +1,67 @@ +BICMOS INVERTER PULLUP CIRCUIT + +VDD 1 0 5.0V +VSS 2 0 0.0V + +VIN 3 0 0.75V + +VC 1 11 0.0V +VB 5 15 0.0V + +Q1 11 15 4 M_NPN AREA=4 +M1 5 3 1 1 M_PMOS W=20U L=2U AD=30P AS=30P PD=21U PS=21U + +CL 4 0 5.0PF + +.IC V(4)=0.75V V(5)=0.0V + +.MODEL M_PMOS PMOS VTO=-0.8 UO=250 TOX=25N NSUB=5E16 ++ UCRIT=10K UEXP=.15 VMAX=50K NEFF=2 XJ=.02U ++ LD=.15U CGSO=.1N CGDO=.1N CJ=.12M MJ=0.5 ++ CJSW=0.3N MJSW=0.5 LEVEL=2 + +.MODEL M_NPN NBJT LEVEL=2 ++ TITLE TWO-DIMENSIONAL NUMERICAL POLYSILICON EMITTER BIPOLAR TRANSISTOR ++ $ SINCE ONLY HALF THE DEVICE IS SIMULATED, DOUBLE THE UNIT WIDTH TO GET ++ $ 1.0 UM EMITTER. ++ OPTIONS DEFW=2.0U ++ OUTPUT STATISTICS ++ ++ X.MESH W=2.0 H.E=0.02 H.M=0.5 R=2.0 ++ X.MESH W=0.5 H.S=0.02 H.M=0.2 R=2.0 ++ ++ Y.MESH L=-0.2 N=1 ++ Y.MESH L= 0.0 N=5 ++ Y.MESH W=0.10 H.E=0.004 H.M=0.05 R=2.5 ++ Y.MESH W=0.15 H.S=0.004 H.M=0.02 R=2.5 ++ Y.MESH W=1.05 H.S=0.02 H.M=0.1 R=2.5 ++ ++ DOMAIN NUM=1 MATERIAL=1 X.L=2.0 Y.H=0.0 ++ DOMAIN NUM=2 MATERIAL=2 X.H=2.0 Y.H=0.0 ++ DOMAIN NUM=3 MATERIAL=3 Y.L=0.0 ++ MATERIAL NUM=1 POLYSILICON ++ MATERIAL NUM=2 OXIDE ++ MATERIAL NUM=3 SILICON ++ ++ ELEC NUM=1 X.L=0.0 X.H=0.0 Y.L=1.1 Y.H=1.3 ++ ELEC NUM=2 X.L=0.0 X.H=0.5 Y.L=0.0 Y.H=0.0 ++ ELEC NUM=3 X.L=2.0 X.H=3.0 Y.L=-0.2 Y.H=-0.2 ++ ++ DOPING GAUSS N.TYPE CONC=3E20 X.L=2.0 X.H=3.0 Y.L=-0.2 Y.H=0.0 ++ + CHAR.L=0.047 LAT.ROTATE ++ DOPING GAUSS P.TYPE CONC=5E18 X.L=0.0 X.H=5.0 Y.L=-0.2 Y.H=0.0 ++ + CHAR.L=0.100 LAT.ROTATE ++ DOPING GAUSS P.TYPE CONC=1E20 X.L=0.0 X.H=0.5 Y.L=-0.2 Y.H=0.0 ++ + CHAR.L=0.100 LAT.ROTATE RATIO=0.7 ++ DOPING UNIF N.TYPE CONC=1E16 X.L=0.0 X.H=5.0 Y.L=0.0 Y.H=1.3 ++ DOPING GAUSS N.TYPE CONC=5E19 X.L=0.0 X.H=5.0 Y.L=1.3 Y.H=1.3 ++ + CHAR.L=0.100 LAT.ROTATE ++ ++ METHOD AC=DIRECT ITLIM=10 ++ MODELS BGN SRH AUGER CONCTAU CONCMOB FIELDMOB + +.TRAN 0.5NS 4.0NS +.PRINT TRAN V(3) V(4) + +.OPTION ACCT BYPASS=1 +.END diff --git a/Windows/spice/examples/cider/serial/readme b/Windows/spice/examples/cider/serial/readme new file mode 100644 index 00000000..08f29304 --- /dev/null +++ b/Windows/spice/examples/cider/serial/readme @@ -0,0 +1,3 @@ +This directory contains the CIDER serial-version benchmarks used in the +thesis "Design-Oriented Mixed-Level Circuit and Device Simulation" by +David A. Gates. diff --git a/Windows/spice/examples/cider/serial/recovery.cir b/Windows/spice/examples/cider/serial/recovery.cir new file mode 100644 index 00000000..cd33be1e --- /dev/null +++ b/Windows/spice/examples/cider/serial/recovery.cir @@ -0,0 +1,40 @@ +DIODE REVERSE RECOVERY + +VPP 1 0 0.0V (PULSE 1.0V -1.0V 1NS 1PS 1PS 20NS 40NS) +VNN 2 0 0.0V +RS 1 3 1.0 +LS 3 4 0.5UH +DT 4 2 M_PIN AREA=1 + +.MODEL M_PIN NUMD LEVEL=2 ++ OPTIONS DEFW=100U ++ X.MESH N=1 L=0.0 ++ X.MESH N=2 L=0.2 ++ X.MESH N=4 L=0.4 ++ X.MESH N=8 L=0.6 ++ X.MESH N=13 L=1.0 ++ ++ Y.MESH N=1 L=0.0 ++ Y.MESH N=9 L=4.0 ++ Y.MESH N=24 L=10.0 ++ Y.MESH N=29 L=15.0 ++ Y.MESH N=34 L=20.0 ++ ++ DOMAIN NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON TN=20NS TP=20NS ++ ++ ELECTRODE NUM=1 X.L=0.6 X.H=1.0 Y.L=0.0 Y.H=0.0 ++ ELECTRODE NUM=2 X.L=-0.1 X.H=1.0 Y.L=20.0 Y.H=20.0 ++ ++ DOPING GAUSS P.TYPE CONC=1.0E19 CHAR.LEN=1.076 X.L=0.75 X.H=1.1 Y.H=0.0 ++ + LAT.ROTATE RATIO=0.1 ++ DOPING UNIF N.TYPE CONC=1.0E14 ++ DOPING GAUSS N.TYPE CONC=1.0E19 CHAR.LEN=1.614 X.L=-0.1 X.H=1.1 Y.L=20.0 ++ ++ MODELS BGN SRH AUGER CONCTAU CONCMOB FIELDMOB + +.OPTION ACCT BYPASS=1 +.TRAN 0.1NS 10NS +.PRINT TRAN V(3) I(VIN) + +.END diff --git a/Windows/spice/examples/cider/serial/rtlinv.cir b/Windows/spice/examples/cider/serial/rtlinv.cir new file mode 100644 index 00000000..ef0dd94d --- /dev/null +++ b/Windows/spice/examples/cider/serial/rtlinv.cir @@ -0,0 +1,25 @@ +RTL INVERTER + +VIN 1 0 DC 1 PWL 0 4 1NS 0 +VCC 12 0 DC 5.0 +RC1 12 3 2.5K +RB1 1 2 8K +Q1 3 2 0 QMOD AREA = 100P + +.OPTION ACCT BYPASS=1 +.TRAN 0.5N 5N +.PRINT TRAN V(2) V(3) + +.MODEL QMOD NBJT LEVEL=1 ++ X.MESH NODE=1 LOC=0.0 ++ X.MESH NODE=61 LOC=3.0 ++ REGION NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17 ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5 ++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0 ++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB ++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25 + +.END diff --git a/Windows/spice/examples/cider/serial/vco.cir b/Windows/spice/examples/cider/serial/vco.cir new file mode 100644 index 00000000..852ddd7f --- /dev/null +++ b/Windows/spice/examples/cider/serial/vco.cir @@ -0,0 +1,41 @@ +VOLTAGE CONTROLLED OSCILLATOR + +RC1 7 5 1K +RC2 7 6 1K + +Q5 7 7 5 QMOD AREA = 100P +Q6 7 7 6 QMOD AREA = 100P + +Q3 7 5 2 QMOD AREA = 100P +Q4 7 6 1 QMOD AREA = 100P + +IB1 2 0 .5MA +IB2 1 0 .5MA +CB1 2 0 1PF +CB2 1 0 1PF + +Q1 5 1 3 QMOD AREA = 100P +Q2 6 2 4 QMOD AREA = 100P + +C1 3 4 .1UF + +IS1 3 0 DC 2.5MA PULSE 2.5MA 0.5MA 0 1US 1US 50MS +IS2 4 0 1MA +VCC 7 0 10 + +.MODEL QMOD NBJT LEVEL=1 ++ X.MESH NODE=1 LOC=0.0 ++ X.MESH NODE=61 LOC=3.0 ++ REGION NUM=1 MATERIAL=1 ++ MATERIAL NUM=1 SILICON NBGNN=1E17 NBGNP=1E17 ++ MOBILITY MATERIAL=1 CONCMOD=SG FIELDMOD=SG ++ DOPING UNIF N.TYPE CONC=1E17 X.L=0.0 X.H=1.0 ++ DOPING UNIF P.TYPE CONC=1E16 X.L=0.0 X.H=1.5 ++ DOPING UNIF N.TYPE CONC=1E15 X.L=0.0 X.H=3.0 ++ MODELS BGNW SRH CONCTAU AUGER CONCMOB FIELDMOB ++ OPTIONS BASE.LENGTH=1.0 BASE.DEPTH=1.25 + +.OPTION ACCT BYPASS=1 +.TRAN 3US 600US 0 3US +.PRINT TRAN V(4) +.END diff --git a/Windows/spice/examples/control_structs/foreach_bjt_ft.sp b/Windows/spice/examples/control_structs/foreach_bjt_ft.sp new file mode 100644 index 00000000..ef5e9d47 --- /dev/null +++ b/Windows/spice/examples/control_structs/foreach_bjt_ft.sp @@ -0,0 +1,51 @@ +BJT ft Test + +vce 1 0 dc 3.0 +vgain 1 c dc 0.0 +f 0 2 vgain -1000 +l 2 b 1g +c 2 0 1g +ib 0 b dc 0.0 ac 1.0 +ic 0 c 0.01 +q1 c b 0 bfs17 + +.control +foreach myic 0.5e-3 1e-3 5e-3 10e-3 50e-3 100e-3 + alter ic = $myic + ac dec 10 10k 5g +end +*foreach mytf 50p 100p 150p 200p 250p 300p +* altermod q.x1.q1 tf = $mytf +* ac dec 10 10k 5g +*end +plot abs(ac1.vgain#branch) abs(ac2.vgain#branch) abs(ac3.vgain#branch) abs(ac4.vgain#branch) abs(ac5.vgain#branch) abs(ac6.vgain#branch) ylimit 0.1 100 loglog +.endc + +***************************************************************** +* SPICE2G6 MODEL OF THE NPN BIPOLAR TRANSISTOR BFS17 (SOT-23) * +* REV: 98.1 DANALYSE GMBH BERLIN (27.07.1998) * +***************************************************************** +.SUBCKT BFS17C 1 2 3 +Q1 6 5 7 BFS17 1.000 +LC 1 6 0.350N +L1 2 4 0.400N +LB 4 5 0.500N +L2 3 8 0.400N +LE 8 7 0.600N +CGBC 4 6 70.00F +CGBE 4 8 0.150P +CGCE 6 8 15.00F +.ENDS +.MODEL BFS17 NPN (level=1 IS=0.480F NF=1.008 BF=99.655 VAF=90.000 IKF=0.190 ++ ISE=7.490F NE=1.762 NR=1.010 BR=38.400 VAR=7.000 IKR=93.200M ++ ISC=0.200F NC=1.042 ++ RB=1.500 IRB=0.100M RBM=1.200 ++ RE=0.500 RC=2.680 ++ CJE=1.325P VJE=0.700 MJE=0.220 FC=0.890 ++ CJC=1.050P VJC=0.610 MJC=0.240 XCJC=0.400 ++ TF=56.940P TR=1.000N PTF=21.000 ++ XTF=68.398 VTF=0.600 ITF=0.700 ++ XTB=1.600 EG=1.110 XTI=3.000 ++ KF=1.000F AF=1.000) + +.end diff --git a/Windows/spice/examples/control_structs/new-check-3.sp b/Windows/spice/examples/control_structs/new-check-3.sp new file mode 100644 index 00000000..c85c19f6 --- /dev/null +++ b/Windows/spice/examples/control_structs/new-check-3.sp @@ -0,0 +1,96 @@ +new ft_getpnames parser check 3, try ternary + +* (compile (concat "tmp-1/ng-spice-rework/src/ngspice " buffer-file-name) t) + +VIN 1 0 DC=0 + +.control + +dc VIN 0 10 5 + +* trying the ternary + +let checks = 0 + +let const0 = 0 +let const5 = 5 +let const6 = 6 + + +let tmp = const0 ? const5 : const6 +if tmp eq const6 + let checks = checks + 1 +else + echo "ERROR:" +end + +let tmp = const6 ? const5 : const6 +if tmp eq const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +define foo(a,b,d) a ? b : d + +if foo(const0,const5,const6) eq const6 + let checks = checks + 1 +else + echo "ERROR:" +end + +if foo(const6,const5,const6) eq const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +let vec7 = 7*unitvec(7) +let vec8 = 8*unitvec(8) + +if length(const5 ? vec7 : vec8) eq 7 + let checks = checks + 1 +else + echo "ERROR:" +end + +if length(const0 ? vec7 : vec8) eq 8 + let checks = checks + 1 +else + echo "ERROR:" +end + +* FIXME, "1 ? 1:1" (without spaces around of ':') doesnt work, +* "1:1" is a lexem, WHY !!! +* ist that an old artifact, (ancient hierarchical name separator ':') +* +*print length(1?1:1) + +*if (1 ? 1:1) eq 1 +if (1 ? 1 : 1) eq 1 + let checks = checks + 1 +else + echo "ERROR:" +end + +print @vin[dc] + +* '"' survives, and will be processed in the ft_getpnames() lexer, that is PPlex() +* where the string will be unqoted +* thats used vor weired variable names, for example "zero(1)" +let foo = "vec8" +if foo eq vec8 + let checks = checks + 1 +else + echo "ERROR:" +end + +if checks eq 8 + echo "INFO: ok" +else + echo "ERROR:" +end + +.endc + +.end diff --git a/Windows/spice/examples/control_structs/new-check-4.sp b/Windows/spice/examples/control_structs/new-check-4.sp new file mode 100644 index 00000000..7c241f23 --- /dev/null +++ b/Windows/spice/examples/control_structs/new-check-4.sp @@ -0,0 +1,111 @@ +demonstrate < etc in ft_getpnames + +* (compile (concat "tmp-1/ng-spice-rework/src/ngspice " buffer-file-name) t) + +VIN 1 0 DC=0 + +.control + +dc VIN 0 10 5 + +let checks = 0 + +let const0 = 0 +let const5 = 5 +let const6 = 6 + +* check some relational operators, which are in danger to mixed up +* with csh semantic, that is IO redirection + +if const5 < const6 + let checks = checks + 1 +else + echo "ERROR:" +end + +if const6 > const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +if const5 >= const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +if const5 <= const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +if const5 = const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +* check some wired non-equality operators +* note: there are some awkward tranformations ahead of the ft_getpnames lexer +* transforming "><" into "> <" +* and "<>" into "< >" +* note: "!=" would have been in serious danger to be fooled up within +* csh history mechanism + +if const6 <> const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +if const6 >< const5 + let checks = checks + 1 +else + echo "ERROR:" +end + + +* check some boolean operators, which are in danger to be mixed up +* with csh semantic, `&' background '|' pipe '~' homedirectory + +if const5 & const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +if const0 | const5 + let checks = checks + 1 +else + echo "ERROR:" +end + +if ~ const0 + let checks = checks + 1 +else + echo "ERROR:" +end + +* note: +* "!=" would be in danger, '!' triggers the csh history mechanism +*if const5 != const6 +* echo "just trying" +*end + + +* Note: csh semantics swallows the '>' and '<' operators +* on most of the com lines +* witnessed by +let tmp = const5 > unwanted_output_file_1 +define foo(a,b) a > unwanted_output_file_2 +print const0 > unwanted_output_file_3 + +if checks eq 10 + echo "INFO: ok" +end + +.endc + +.end diff --git a/Windows/spice/examples/control_structs/repeat3.sp b/Windows/spice/examples/control_structs/repeat3.sp new file mode 100644 index 00000000..5650252a --- /dev/null +++ b/Windows/spice/examples/control_structs/repeat3.sp @@ -0,0 +1,148 @@ +Test sequences for ngspice control structures +*vectors are used (except foreach) +*start in interactive mode + +.control + +* test for while, repeat, if, break + let loop = 0 + while loop < 4 + let index = 0 + repeat + let index = index + 1 + if index > 4 + break + end + end + echo index "$&index" loop "$&loop" + let loop = loop + 1 + end + + +* test sequence for while, dowhile + let loop = 0 + echo + echo enter loop with "$&loop" + dowhile loop < 3 + echo within dowhile loop "$&loop" + let loop = loop + 1 + end + echo after dowhile loop "$&loop" + echo + let loop = 0 + while loop < 3 + echo within while loop "$&loop" + let loop = loop + 1 + end + echo after while loop "$&loop" + let loop = 3 + echo + echo enter loop with "$&loop" + dowhile loop < 3 + echo within dowhile loop "$&loop" $ output expected + let loop = loop + 1 + end + echo after dowhile loop "$&loop" + echo + let loop = 3 + while loop < 3 + echo within while loop "$&loop" $ no output expected + let loop = loop + 1 + end + echo after while loop "$&loop" + + +* test sequence for foreach + echo + foreach outvar 0 0.5 1 1.5 + echo parameters: $outvar $ foreach parameters are variables, not vectors! + end + +* test for if ... else ... end + echo + let loop = 0 + let index = 1 + dowhile loop < 10 + let index = index * 2 + if index < 128 + echo "$&index" lt 128 + else + echo "$&index" ge 128 + end + let loop = loop + 1 + end + +* simple test for label, goto + echo + let loop = 0 + label starthere + echo start "$&loop" + let loop = loop + 1 + if loop < 3 + goto starthere + end + echo end "$&loop" + +* test for label, nested goto + echo + let loop = 0 + label starthere1 + echo start nested "$&loop" + let loop = loop + 1 + if loop < 3 + if loop < 3 + goto starthere1 + end + end + echo end "$&loop" + +* test for label, goto + echo + let index = 0 + label starthere2 + let loop = 0 + echo We are at start with index "$&index" and loop "$&loop" + if index < 6 + label inhere + let index = index + 1 + if loop < 3 + let loop = loop + 1 + if index > 1 + echo jump2 + goto starthere2 + end + end + echo jump + goto inhere + end + echo We are at end with index "$&index" and loop "$&loop" + +* test goto in while loop + echo + let loop = 0 + if 1 $ outer loop to allow nested forward label 'endlabel' + while loop < 10 + if loop > 5 + echo jump + goto endlabel + end + let loop = loop + 1 + end + echo before $ never reached + label endlabel + echo after "$&loop" + end + +*test for using variables +* simple test for label, goto + echo + set loop = 0 + label starthe + echo start $loop + let loop = $loop + 1 $ expression needs vector at lhs + set loop = "$&loop" $ convert vector contents to variable + if $loop < 3 + goto starthe + end + echo end $loop +.endc diff --git a/Windows/spice/examples/control_structs/s-param.cir b/Windows/spice/examples/control_structs/s-param.cir new file mode 100644 index 00000000..bff277f7 --- /dev/null +++ b/Windows/spice/examples/control_structs/s-param.cir @@ -0,0 +1,120 @@ +Test for Scattering Parameters +** Two ports +** Examples: Bipolar, Tschebyschef, RC + +.param Rbase=50 Vbias_in=0 Vbias_out=0 + +*** The two-port circuit: +** port 1: in 0 +** port 2: out 0 +** Bias on both ports through resistor Rbase (to obtain operating point) + +** Example RF Bipolar mrf5711 +** VCE 1 V, IE = 5mA +** QXXXXXXX nc nb ne +** model obtained from +** http://141.69.160.32/~krausg/Spice_Model_CD/Vendor%20List/Motorola/Spice/RFBJT/ +*.include MRF5711.lib +*XMRF5711 out in e MRF5711 +*Ie e 0 5m +*Ce e 0 1 + +** Example Tschebyschef Low Pass filter +C1 in 0 33.2p +L1 in 2 99.2n +C2 2 0 57.2p +L2 2 out 99.2n +C3 out 0 33.2p + +** Example RC +** see +** http://www.allenhollister.com/allen/files/scatteringparameters.pdf +*R2 in out 10 +*C1 out int5 30p +*R1 int5 0 10 + +*** End of circuit + + +** The following subcircuit to be changed only by an experienced user! + +*** Driver and readout +X1 in out S22 S12 S_PARAM + +.SUBCKT S_PARAM 22 66 5 7 +* Resistors emulate switches with Ron=0.001 and Roff=1e12 +* to switch driver to input and readout to output (and vice versa, see below) +RS1 22 2 0.001 +RS2 66 6 0.001 +RS3 22 6 1e12 +RS4 66 2 1e12 +*Driver +Vacdc 1 0 DC 'Vbias_in' AC 1 $ ac voltage and dc bias at input (applied through load resistor) +R1 1 2 'Rbase' +E1 3 0 2 0 2 $ amplify in port ac voltage by 2 +Vac 3 4 DC 0 AC 1 $ subtract driving ac voltage +R_loop 4 5 0.001 +R3 5 0 1 $ ground return for measure node 5 +*Readout +E2 7 0 6 0 2 $ amplify out port ac voltage by 2 +R4 6 8 'Rbase' $ load resistor at output (ac) +Vdc 8 0 DC 'Vbias_out' AC 0 $ dc bias at output (applied through load resistor) +.ends + +** Check the two ac lines below for being equal! +.control +set noaskquit +set filetype=ascii +*** measurement for s11 and s21 +op +** save bias voltages to vector +let Vdcnew=V(X1.1) $ former Vacdc +let Vacdcnew=v(X1.8) $ former Vdc +** first ac measurement (change this line only together with following ac line) +*ac lin 20 0.1G 2G $ use for bip transistor +ac lin 100 2.5MEG 250MEG $ use for Tschebyschef +*ac lin 101 1k 10G $ use for RC +** +** switch input and output +alter R.X1.RS1=1e12 +alter R.X1.RS2=1e12 +alter R.X1.RS3=0.001 +alter R.X1.RS4=0.001 +** switch bias voltages between in and out +alter V.X1.Vacdc DC=op1.Vacdcnew +alter V.X1.Vdc DC=op1.Vdcnew +*** measurement for s12 and s22 +op +** second ac measurement (change this line only together with ac line above) +*ac lin 20 0.1G 2G $ use for bip transistor +ac lin 100 2.5MEG 250MEG $ use for Tschebyschef +*ac lin 101 1 10G $ use for RC +** +let s11=ac1.s22 +let s21=ac1.s12 +settype s-param S11 S21 S22 S12 + +let S11db = db(s11) +let S12db = db(s12) +let S21db = db(s21) +let S22db = db(s22) +settype decibel S11db S21db S22db S12db + +let P11=180*ph(s11)/pi +let P21=180*ph(s21)/pi +let P22=180*ph(S22)/pi +let P12=180*ph(S12)/pi +settype phase P11 P21 P22 P12 + +let Rbase=@R.X1.R4[Resistance] +settype impedance Rbase + +*plot s11db s21db S22db S12db ylimit -50 0 xlog $ used with RC +plot s11db s21db S22db S12db ylimit -0.5 0 $ used with Tschebyschef +plot P11 P21 P22 P12 +plot smithgrid S11 S12 +*wrdata s3046 mag(S11) P11 mag(S21) P21 mag(S22) P22 mag(S12) P12 $ write simple table +wrs2p s3046.s2p $ write touchstone vers. 1 file s3046.s2p +.endc + +.end diff --git a/Windows/spice/examples/measure/func_cap.sp b/Windows/spice/examples/measure/func_cap.sp new file mode 100644 index 00000000..eca14a86 --- /dev/null +++ b/Windows/spice/examples/measure/func_cap.sp @@ -0,0 +1,15 @@ +* func_cap.sp + + +.func icap_calc(A,B,C,D) '2*A*sqrt(B*C*D)' + +.param cap_val = 'max(icap_calc(1,2,3,4))' +VDD 1 0 DC 1 +C1 1 0 'cap_val' + +.measure tran capacitance param='cap_val' +.measure tran capac2 param='max(icap_calc(1,2,3,4))' + +.tran 1ps 100ps + +.end diff --git a/Windows/spice/examples/measure/inv-meas-tran-auto.sp b/Windows/spice/examples/measure/inv-meas-tran-auto.sp new file mode 100644 index 00000000..927d9a44 --- /dev/null +++ b/Windows/spice/examples/measure/inv-meas-tran-auto.sp @@ -0,0 +1,103 @@ +Inverter example circuit +* This netlist demonstrates the following: +* global nodes (vdd, gnd) +* autostop (.tran defines simulation end as 4ns but simulation stops at +* 142.5ps when .measure statements are evaluated) +* scale (all device units are in microns) +* model binning (look in device.values file for which bin chosen) +* +* m.x1.mn: +* model = nch.2 +* +* m.x1.mp: +* model = pch.2 +* +* parameters +* parameterized subckt +* vsrc with repeat +* .measure statements for delay and an example ternary operator +* device listing and parameter listing +* You can run the example circuit with this command: +* +* ngspice inverter3.sp + + +* global nodes +.global vdd gnd + +* autostop -- stop simulation early if .measure statements done +* scale -- define scale factor for mosfet device parameters (l,w,area,perimeter) +.option autostop +.option scale = 1e-6 + +* model binning +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) +.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) + +* parameters +.param vp = 1.0v +.param lmin = 0.10 +.param wmin = 0.12 +.param plmin = 'lmin' +.param nlmin = 'lmin' +.param wpmin = 'wmin' +.param wnmin = 'wmin' +.param drise = 400ps +.param dfall = 100ps +.param trise = 100ps +.param tfall = 100ps +.param period = 1ns +.param skew_meas = 'vp/2' + +* parameterized subckt +.subckt inv in out pw='wpmin' pl='plmin' nw='wnmin' nl='nlmin' +mp out in vdd vdd pch w='pw' l='pl' +mn out in gnd gnd nch w='nw' l='nl' +.ends + +v0 vdd gnd 'vp' + +* vsrc with repeat +v1 in gnd pwl ++ 0ns 'vp' ++ 'dfall-0.8*tfall' 'vp' ++ 'dfall-0.4*tfall' '0.9*vp' ++ 'dfall+0.4*tfall' '0.1*vp' ++ 'dfall+0.8*tfall' 0v ++ 'drise-0.8*trise' 0v ++ 'drise-0.4*trise' '0.1*vp' ++ 'drise+0.4*trise' '0.9*vp' ++ 'drise+0.8*trise' 'vp' ++ 'period+dfall-0.8*tfall' 'vp' ++ r='dfall-0.8*tfall' + +x1 in out inv pw=60 nw=20 +c1 out gnd 220fF + +.tran 1ps 4ns + +.meas tran inv_delay trig v(in) val='vp/2' fall=1 targ v(out) val='vp/2' rise=1 +.meas tran inv_delay2 trig v(in) val='vp/2' td=1n fall=1 targ v(out) val='vp/2' rise=1 +.meas tran test_data1 trig AT = 1n targ v(out) val='vp/2' rise=3 +.meas tran out_slew trig v(out) val='0.2*vp' rise=2 targ v(out) val='0.8*vp' rise=2 +.meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0' +.meas tran skew when v(out)=0.6 +.meas tran skew2 when v(out)=skew_meas +.meas tran skew3 when v(out)=skew_meas fall=2 +.meas tran skew4 when v(out)=skew_meas fall=LAST +.meas tran skew5 FIND v(out) AT=2n +*.measure tran v0_min min i(v0) from='dfall' to='dfall+period' +*.measure tran v0_avg avg i(v0) from='dfall' to='dfall+period' +*.measure tran v0_integ integ i(v0) from='dfall' to='dfall+period' +*.measure tran v0_rms rms i(v0) from='dfall' to='dfall+period' + +.control +run +rusage all +plot v(in) v(out) +.endc + +.end + diff --git a/Windows/spice/examples/measure/inv-meas-tran-control.sp b/Windows/spice/examples/measure/inv-meas-tran-control.sp new file mode 100644 index 00000000..48f7d09a --- /dev/null +++ b/Windows/spice/examples/measure/inv-meas-tran-control.sp @@ -0,0 +1,113 @@ +Inverter example circuit +* This netlist demonstrates the following: +* global nodes (vdd, gnd) +* autostop (.tran defines simulation end as 4ns but simulation stops at +* 142.5ps when .measure statements are evaluated) +* scale (all device units are in microns) +* model binning (look in device.values file for which bin chosen) +* +* m.x1.mn: +* model = nch.2 +* +* m.x1.mp: +* model = pch.2 +* +* parameters +* parameterized subckt +* vsrc with repeat +* .measure statements for delay and an example ternary operator +* device listing and parameter listing +* You can run the example circuit with this command: +* +* ngspice inverter3.sp + + +* global nodes +.global vdd gnd + +* autostop -- stop simulation early if .measure statements done +* scale -- define scale factor for mosfet device parameters (l,w,area,perimeter) +*.option autostop +.option scale = 1e-6 + +* model binning +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) +.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) + +* parameters +.param vp = 1.0v +.param lmin = 0.10 +.param wmin = 0.12 +.param plmin = 'lmin' +.param nlmin = 'lmin' +.param wpmin = 'wmin' +.param wnmin = 'wmin' +.param drise = 400ps +.param dfall = 100ps +.param trise = 100ps +.param tfall = 100ps +.param period = 1ns +.param skew_meas = 'vp/2' + +* parameterized subckt +.subckt inv in out pw='wpmin' pl='plmin' nw='wnmin' nl='nlmin' +mp out in vdd vdd pch w='pw' l='pl' +mn out in gnd gnd nch w='nw' l='nl' +.ends + +v0 vdd gnd 'vp' + +* vsrc with repeat +v1 in gnd pwl ++ 0ns 'vp' ++ 'dfall-0.8*tfall' 'vp' ++ 'dfall-0.4*tfall' '0.9*vp' ++ 'dfall+0.4*tfall' '0.1*vp' ++ 'dfall+0.8*tfall' 0v ++ 'drise-0.8*trise' 0v ++ 'drise-0.4*trise' '0.1*vp' ++ 'drise+0.4*trise' '0.9*vp' ++ 'drise+0.8*trise' 'vp' ++ 'period+dfall-0.8*tfall' 'vp' ++ r='dfall-0.8*tfall' + +x1 in out inv pw=60 nw=20 +c1 out gnd 220fF + +.control +tran 1ps 4ns +meas tran inv_delay trig v(in) val=0.5 fall=1 targ v(out) val=0.5 rise=1 +meas tran inv_delay2 trig v(in) val=0.5 td=1n fall=1 targ v(out) val=0.5 rise=1 +meas tran test_data1 trig AT = 1n targ v(out) val=0.5 rise=3 +meas tran out_slew trig v(out) val=0.2 rise=2 targ v(out) val=0.8 rise=2 + +*.meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0' +if ( inv_delay < 100ps ) + let delay_chk = 1 +else + let delay_chk = 0 +end +echo delay_chk = "$&delay_chk" + +meas tran skew when v(out)=0.6 +let skew_meas = 0.5 +meas tran skew2 when v(out)=skew_meas +meas tran skew3 when v(out)=skew_meas fall=2 +meas tran skew4 when v(out)=skew_meas fall=LAST +meas tran skew5 FIND v(out) AT=2n +let dfall = 100p +let period = 1n +let delta = dfall+period +meas tran v0_min min i(v0) from=dfall to=delta +meas tran i_v0_min min_at i(v0) from=dfall to=delta +meas tran v0_avg avg i(v0) from = dfall to = delta +meas tran v0_integ integ i(v0) from=dfall to=delta +meas tran v0_rms rms i(v0) from=dfall to=delta +rusage all +plot v(in) v(out) +.endc + +.end + diff --git a/Windows/spice/examples/measure/inv-meas-tran.sp b/Windows/spice/examples/measure/inv-meas-tran.sp new file mode 100644 index 00000000..0a4077ea --- /dev/null +++ b/Windows/spice/examples/measure/inv-meas-tran.sp @@ -0,0 +1,104 @@ +Inverter example circuit +* This netlist demonstrates the following: +* global nodes (vdd, gnd) +* autostop (.tran defines simulation end as 4ns but simulation stops at +* 142.5ps when .measure statements are evaluated) +* scale (all device units are in microns) +* model binning (look in device.values file for which bin chosen) +* +* m.x1.mn: +* model = nch.2 +* +* m.x1.mp: +* model = pch.2 +* +* parameters +* parameterized subckt +* vsrc with repeat +* .measure statements for delay and an example ternary operator +* device listing and parameter listing +* You can run the example circuit with this command: +* +* ngspice inverter3.sp + + +* global nodes +.global vdd gnd + +* autostop -- stop simulation early if .measure statements done +* scale -- define scale factor for mosfet device parameters (l,w,area,perimeter) +*.option autostop +.option scale = 1e-6 + +* model binning +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) +.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) + +* parameters +.param vp = 1.0v +.param lmin = 0.10 +.param wmin = 0.12 +.param plmin = 'lmin' +.param nlmin = 'lmin' +.param wpmin = 'wmin' +.param wnmin = 'wmin' +.param drise = 400ps +.param dfall = 100ps +.param trise = 100ps +.param tfall = 100ps +.param period = 1ns +.param skew_meas = 'vp/2' + +* parameterized subckt +.subckt inv in out pw='wpmin' pl='plmin' nw='wnmin' nl='nlmin' +mp out in vdd vdd pch w='pw' l='pl' +mn out in gnd gnd nch w='nw' l='nl' +.ends + +v0 vdd gnd 'vp' + +* vsrc with repeat +v1 in gnd pwl ++ 0ns 'vp' ++ 'dfall-0.8*tfall' 'vp' ++ 'dfall-0.4*tfall' '0.9*vp' ++ 'dfall+0.4*tfall' '0.1*vp' ++ 'dfall+0.8*tfall' 0v ++ 'drise-0.8*trise' 0v ++ 'drise-0.4*trise' '0.1*vp' ++ 'drise+0.4*trise' '0.9*vp' ++ 'drise+0.8*trise' 'vp' ++ 'period+dfall-0.8*tfall' 'vp' ++ r='dfall-0.8*tfall' + +x1 in out inv pw=60 nw=20 +c1 out gnd 220fF + +.tran 1ps 4ns + +.meas tran inv_delay trig v(in) val='vp/2' fall=1 targ v(out) val='vp/2' rise=1 +.meas tran inv_delay2 trig v(in) val='vp/2' td=1n fall=1 targ v(out) val='vp/2' rise=1 +.meas tran test_data1 trig AT = 1n targ v(out) val='vp/2' rise=3 +.meas tran out_slew trig v(out) val='0.2*vp' rise=2 targ v(out) val='0.8*vp' rise=2 +.meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0' +.meas tran skew when v(out)=0.6 +.meas tran skew2 when v(out)=skew_meas +.meas tran skew3 when v(out)=skew_meas fall=2 +.meas tran skew4 when v(out)=skew_meas fall=LAST +.meas tran skew5 FIND v(out) AT=2n +.meas tran v0_min min i(v0) from='dfall' to='dfall+period' +.meas tran i_v0_min min_at i(v0) from='dfall' to='dfall+period' +.meas tran v0_avg avg i(v0) from='dfall' to='dfall+period' +.meas tran v0_integ integ i(v0) from='dfall' to='dfall+period' +.meas tran v0_rms rms i(v0) from='dfall' to='dfall+period' + +.control +run +rusage all +plot v(in) v(out) +.endc + +.end + diff --git a/Windows/spice/examples/measure/inv-meas-tran_oc.sp b/Windows/spice/examples/measure/inv-meas-tran_oc.sp new file mode 100644 index 00000000..98077b80 --- /dev/null +++ b/Windows/spice/examples/measure/inv-meas-tran_oc.sp @@ -0,0 +1,98 @@ +Inverter example circuit +* This netlist demonstrates the following: +* global nodes (vdd, gnd) +* autostop (.tran defines simulation end as 4ns but simulation stops at +* 142.5ps when .measure statements are evaluated) +* scale (all device units are in microns) +* model binning (look in device.values file for which bin chosen) +* +* m.x1.mn: +* model = nch.2 +* +* m.x1.mp: +* model = pch.2 +* +* parameters +* parameterized subckt +* vsrc with repeat +* .measure statements for delay and an example ternary operator +* device listing and parameter listing +* You can run the example circuit with this command: +* +* ngspice inverter3.sp + + +* global nodes +.global vdd gnd + +* autostop -- stop simulation early if .measure statements done +* scale -- define scale factor for mosfet device parameters (l,w,area,perimeter) +*.option autostop +.option scale = 1e-6 + +* model binning +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) +.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) + +* parameters +.param vp = 1.0v +.param lmin = 0.10 +.param wmin = 0.12 +.param plmin = 'lmin' +.param nlmin = 'lmin' +.param wpmin = 'wmin' +.param wnmin = 'wmin' +.param drise = 400ps +.param dfall = 100ps +.param trise = 100ps +.param tfall = 100ps +.param period = 1ns +.param skew_meas = 'vp/2' + +* parameterized subckt +.subckt inv in out pw='wpmin' pl='plmin' nw='wnmin' nl='nlmin' +mp out in vdd vdd pch w='pw' l='pl' +mn out in gnd gnd nch w='nw' l='nl' +.ends + +v0 vdd gnd 'vp' + +* vsrc with repeat +v1 in gnd pwl ++ 0ns 'vp' ++ 'dfall-0.8*tfall' 'vp' ++ 'dfall-0.4*tfall' '0.9*vp' ++ 'dfall+0.4*tfall' '0.1*vp' ++ 'dfall+0.8*tfall' 0v ++ 'drise-0.8*trise' 0v ++ 'drise-0.4*trise' '0.1*vp' ++ 'drise+0.4*trise' '0.9*vp' ++ 'drise+0.8*trise' 'vp' ++ 'period+dfall-0.8*tfall' 'vp' ++ r='dfall-0.8*tfall' + +x1 in out inv pw=60 nw=20 +c1 out gnd 220fF + +.tran 1ps 4ns + +.meas tran inv_delay trig v(in) val='vp/2' fall=1 targ v(out) val='vp/2' rise=1 +.meas tran inv_delay2 trig v(in) val='vp/2' td=1n fall=1 targ v(out) val='vp/2' rise=1 +.meas tran test_data1 trig AT = 1n targ v(out) val='vp/2' rise=3 +.meas tran out_slew trig v(out) val='0.2*vp' rise=2 targ v(out) val='0.8*vp' rise=2 +.meas tran delay_chk param='(inv_delay < 100ps) ? 1 : 0' +.meas tran skew when v(out)=0.6 +.meas tran skew2 when v(out)=skew_meas +.meas tran skew3 when v(out)=skew_meas fall=2 +.meas tran skew4 when v(out)=skew_meas fall=LAST +.meas tran skew5 FIND v(out) AT=2n +.meas tran v0_min min i(v0) from='dfall' to='dfall+period' +.meas tran i_v0_min min_at i(v0) from='dfall' to='dfall+period' +.meas tran v0_avg avg i(v0) from='dfall' to='dfall+period' +.meas tran v0_integ integ i(v0) from='dfall' to='dfall+period' +.meas tran v0_rms rms i(v0) from='dfall' to='dfall+period' + +.end + diff --git a/Windows/spice/examples/measure/mos-meas-dc-control.sp b/Windows/spice/examples/measure/mos-meas-dc-control.sp new file mode 100644 index 00000000..9869cf60 --- /dev/null +++ b/Windows/spice/examples/measure/mos-meas-dc-control.sp @@ -0,0 +1,49 @@ +***** Single NMOS Transistor .measure (Id-Vd) *** +* Altering device witdth leads to select new model due to binning limits. +* New model has artificially thick gate oxide (changed from default 3n to 4n) +* to demonstrate the effect. +m1 d g s b nch L=0.6u W=9.99u ; W is slightly below binning limit + +vgs g 0 3.5 +vds d 0 3.5 +vs s 0 dc 0 +vb b 0 dc 0 + +* model binning +* uses default parameters, except toxe +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u toxe=3n ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u toxe=4n) + +.control +dc vds 0 3.5 0.05 vgs 3.5 0.5 -0.5 +meas dc is_at FIND i(vs) AT=1 +meas dc is_max max i(vs) +meas dc vds_at2 when i(vs)=10m +* starting with branches in descending order of vgs +* trig ist the first branch which crosses 5mA +* Targ is the first branch crossing 10mA +meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1 +* trig ist the first branch which crosses 5mA +* Targ is the second branch crossing 10mA +meas dc vd_diff2 trig i(vs) val=0.005 rise=2 targ i(vs) val=0.01 rise=2 +alter @m1[w]=10.01u ; W is slightly above binning limit +dc vds 0 3.5 0.05 vgs 3.5 0.5 -0.5 +meas dc is_at FIND i(vs) AT=1 +meas dc is_max max i(vs) +meas dc vds_at2 when i(vs)=10m +meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1 +* there is only one branch crossing 10mA, so this second meas fails with targ out of interval +echo +echo The next one will fail (no two branches crossing 10 mA): +meas dc vd_diff2 trig i(vs) val=0.005 rise=2 targ i(vs) val=0.01 rise=2 +*rusage all +plot dc1.i(vs) i(vs) +.endc + + +.end + + + + + diff --git a/Windows/spice/examples/measure/mos-meas-dc.sp b/Windows/spice/examples/measure/mos-meas-dc.sp new file mode 100644 index 00000000..eb3892db --- /dev/null +++ b/Windows/spice/examples/measure/mos-meas-dc.sp @@ -0,0 +1,37 @@ +***** Single NMOS Transistor .measure (Id-Vd) *** +m1 d g s b nch L=0.6u W=10.0u + +vgs g 0 3.5 +vds d 0 3.5 +vs s 0 dc 0 +vb b 0 dc 0 + +.dc vds 0 3.5 0.05 vgs 0.5 3.5 0.5 + +.print dc v(1) i(vs) + +* model binning +.model nch.1 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model nch.2 nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) +.model pch.1 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch.2 pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=10u wmax=100u ) + +.meas dc is_at FIND i(vs) AT=1 +.meas dc is_max max i(vs) from=0 to=3.5 +.meas dc vds_at2 when i(vs)=10m +.meas dc vd_diff1 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=1 +.meas dc vd_diff2 trig i(vs) val=0.005 rise=1 targ i(vs) val=0.01 rise=2 + +.control +run +*rusage all +plot i(vs) +.endc + + +.end + + + + + diff --git a/Windows/spice/examples/measure/rc-meas-ac-control.sp b/Windows/spice/examples/measure/rc-meas-ac-control.sp new file mode 100644 index 00000000..9b57929d --- /dev/null +++ b/Windows/spice/examples/measure/rc-meas-ac-control.sp @@ -0,0 +1,64 @@ +RC band pass example circuit +* This netlist demonstrates the following: +* global nodes (vdd, gnd) + +* .measure statements for delay and an example ternary operator + +* You can run the example circuit with this command: +* +* ngspice rc-meas-ac.sp + + +* global nodes +.global vdd gnd + +* autostop -- stop simulation early if .measure statements done +*.option autostop + +vin in gnd dc 0 ac 1 + +R1 in mid1 1k +c1 mid1 gnd 1n +C2 mid1 out 500p +R2 out gnd 1k + + +.control +ac DEC 10 1k 10MEG +meas ac vout_at FIND v(out) AT=1MEG +meas ac vout_atr FIND vr(out) AT=1MEG +meas ac vout_ati FIND vi(out) AT=1MEG +meas ac vout_atm FIND vm(out) AT=1MEG +meas ac vout_atp FIND vp(out) AT=1MEG +meas ac vout_atd FIND vdb(out) AT=1MEG +meas ac vout_max max v(out) from=1k to=10MEG +meas ac freq_at when v(out)=0.1 +meas ac vout_diff trig v(out) val=0.1 rise=1 targ v(out) val=0.1 fall=1 +meas ac fixed_diff trig AT = 10k targ v(out) val=0.1 rise=1 +meas ac vout_avg avg v(out) from=10k to=1MEG +meas ac vout_integ integ v(out) from=20k to=500k +meas ac freq_at2 when v(out)=0.1 fall=LAST +*meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0' +if (vout_diff < 100k) + let bw_chk = 1 +else + let bw_chk = 0 +end +echo bw_chk = "$&bw_chk" +*meas ac bw_chk2 param='(vout_diff > 500k) ? 1 : 0' +if (vout_diff > 500k) + let bw_chk2 = 1 +else + let bw_chk2 = 0 +end +echo bw_chk2 = "$&bw_chk2" +meas ac vout_rms rms v(out) from=10 to=1G +*rusage all +plot v(out) +plot ph(v(out)) +plot mag(v(out)) +plot db(v(out)) +.endc + +.end + diff --git a/Windows/spice/examples/measure/rc-meas-ac.sp b/Windows/spice/examples/measure/rc-meas-ac.sp new file mode 100644 index 00000000..2d464ba5 --- /dev/null +++ b/Windows/spice/examples/measure/rc-meas-ac.sp @@ -0,0 +1,54 @@ +RC band pass example circuit +* This netlist demonstrates the following: +* global nodes (vdd, gnd) + +* .measure statements for delay and an example ternary operator + +* You can run the example circuit with this command: +* +* ngspice rc-meas-ac.sp + + +* global nodes +.global vdd gnd + +* autostop -- stop simulation early if .measure statements done +*.option autostop + +vin in gnd dc 0 ac 1 + +R1 in mid1 1k +c1 mid1 gnd 1n +C2 mid1 out 500p +R2 out gnd 1k + +.ac DEC 10 1k 10MEG + +.meas ac vout_at FIND v(out) AT=1MEG +.meas ac vout_atr FIND vr(out) AT=1MEG +.meas ac vout_ati FIND vi(out) AT=1MEG +.meas ac vout_atm FIND vm(out) AT=1MEG +.meas ac vout_atp FIND vp(out) AT=1MEG +.meas ac vout_atd FIND vdb(out) AT=1MEG +.meas ac vout_max max v(out) from=1k to=10MEG +.meas ac freq_at when v(out)=0.1 +.meas ac vout_diff trig v(out) val=0.1 rise=1 targ v(out) val=0.1 fall=1 +.meas ac fixed_diff trig AT = 10k targ v(out) val=0.1 rise=1 +.meas ac vout_avg avg v(out) from=10k to=1MEG +.meas ac vout_integ integ v(out) from=20k to=500k +.meas ac freq_at2 when v(out)=0.1 fall=LAST +.meas ac bw_chk param='(vout_diff < 100k) ? 1 : 0' +.meas ac bw_chk2 param='(vout_diff > 500k) ? 1 : 0' +.meas ac vout_rms rms v(out) from=10 to=1G + +.control +run +*rusage all +plot v(out) +plot ph(v(out)) +plot mag(v(out)) +plot db(v(out)) +.endc + +.end + diff --git a/Windows/spice/examples/measure/simple-meas-tran.sp b/Windows/spice/examples/measure/simple-meas-tran.sp new file mode 100644 index 00000000..0279c73f --- /dev/null +++ b/Windows/spice/examples/measure/simple-meas-tran.sp @@ -0,0 +1,57 @@ +File: simple-meas-tran.sp +* Simple .measurement examples +* transient simulation of two sine signals with different frequencies +vac1 1 0 DC 0 sin(0 1 1k 0 0) +R1 1 0 100k +vac2 2 0 DC 0 sin(0 1.2 0.9k 0 0) +.tran 10u 5m +* +.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2 +.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3 +.measure tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1 +.measure tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3 +.measure tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1 +.measure tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3 +.measure tran teval WHEN v(2)=0.7 CROSS=LAST +.measure tran teval WHEN v(2)=v(1) FALL=LAST +.measure tran teval WHEN v(1)=v(2) CROSS=LAST +.measure tran yeval FIND v(2) WHEN v(1)=0.2 FALL=2 +.measure tran yeval FIND v(2) AT=2m +.measure tran ymax MAX v(2) from=2m to=3m +.measure tran tymax MAX_AT v(2) from=2m to=3m +.measure tran ypp PP v(1) from=2m to=4m +.measure tran yrms RMS v(1) from=2m to=3.5m +.measure tran yavg AVG v(1) from=2m to=4m +.measure tran yint INTEG v(2) from=2m to=3m +.param fval=5 +.measure tran yadd param='fval + 7' +.param vout_diff=50k +.meas tran bw_chk param='(vout_diff < 100k) ? 1 : 0' +.measure tran vtest find par('v(2)*v(1)') AT=2.3m +* +.control +run +plot v(1) v(2) +gnuplot ttt i(vac1) +meas tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=2 +meas tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 RISE=3 +meas tran tdiff TRIG v(1) VAL=0.5 RISE=1 TARG v(1) VAL=0.5 FALL=1 +meas tran tdiff TRIG v(1) VAL=0 FALL=3 TARG v(2) VAL=0 FALL=3 +meas tran tdiff TRIG v(1) VAL=-0.6 CROSS=1 TARG v(2) VAL=-0.8 CROSS=1 +meas tran tdiff TRIG AT=1m TARG v(2) VAL=-0.8 CROSS=3 +meas tran teval WHEN v(2)=0.7 CROSS=LAST +meas tran teval WHEN v(2)=v(1) FALL=LAST +meas tran teval WHEN v(1)=v(2) CROSS=LAST +meas tran yeval FIND v(2) WHEN v(1)=0.2 FALL=2 +meas tran yeval FIND v(2) AT=2m +meas tran ymax MAX v(2) from=2m to=3m +meas tran tymax MAX_AT v(2) from=2m to=3m +meas tran ypp PP v(1) from=2m to=4m +meas tran yrms RMS v(1) from=2m to=3.5m +meas tran yavg AVG v(1) from=2m to=4m +meas tran yint INTEG v(2) from=2m to=3m +meas tran ymax MAX v(2) from=2m to=3m +meas tran tmax WHEN v(2)=YMAX from=1m to=2m $ from..to.. not recognized! + +.endc +.end diff --git a/Windows/spice/examples/memristor/memristor.sp b/Windows/spice/examples/memristor/memristor.sp new file mode 100644 index 00000000..fdb9488a --- /dev/null +++ b/Windows/spice/examples/memristor/memristor.sp @@ -0,0 +1,65 @@ +Memristor with threshold +* Y. V. Pershin, M. Di Ventra: "SPICE model of memristive devices with threshold", +* arXiv:1204.2600v1 [physics.comp-ph] 12 Apr 2012, +* http://arxiv.org/pdf/1204.2600.pdf + +* Parameter selection and plotting by +* Holger Vogt 2012 + +.param stime=10n +.param vmax = 3 + +* send parameters to the .control section +.csparam stime={stime} +.csparam vmax={vmax} + +Xmem 1 0 memristor +* triangular sweep (you have to adapt the parameters to 'alter' command in the .control section) +*V1 1 0 DC 0 PWL(0 0 '0.25*stime' 'vmax' '0.5*stime' 0 '0.75*stime' '-vmax' 'stime' 0) +* sinusoidal sweep +V1 0 1 DC 0 sin(0 'vmax' '1/stime') + +* memristor model with limits and threshold +* "artificial" parameters alpha, beta, and vt. beta and vt adapted to basic programming frequency +* just to obtain nice results! +* You have to care for the physics and set real values! +.subckt memristor plus minus PARAMS: Ron=1K Roff=10K Rinit=7.0K alpha=0 beta=20e3/stime Vt=1.6 +Bx 0 x I='((f1(V(plus)-V(minus))> 0) && (V(x) < Roff)) ? {f1(V(plus)-V(minus))}: ((((f1(V(plus)-V(minus)) < 0) && (V(x)>Ron)) ? {f1(V(plus)-V(minus))}: 0)) ' +Vx x x1 dc 0 +Cx x1 0 1 IC={Rinit} +Rmem plus minus r={V(x)} +.func f1(y)={beta*y+0.5*(alpha-beta)*(abs(y+Vt)-abs(y-Vt))} +.ends + +* transient simulation same programming voltage but rising frequencies +.control +*** first simulation *** +* approx. 100 simulation points +let deltime = stime/100 +tran $&deltime $&stime uic +* plot i(v1) vs v(1) +*** you may just stop here *** +* raise the frequency +let newfreq = 1.1/stime +let newstime = stime/1.1 +let deltime = newstime/100 +alter @V1[sin] [ 0 $&vmax $&newfreq ] +tran $&deltime $&newstime uic +* raise the frequency even more +let newfreq = 1.4/stime +let newstime = stime/1.4 +let deltime = newstime/100 +alter @V1[sin] [ 0 $&vmax $&newfreq ] +tran $&deltime $&newstime uic +* the 'programming' currents +plot tran1.alli tran2.alli alli title 'Memristor with threshold: Internal Programming currents' +* resistance versus time plot +settype impedance xmem.x1 tran1.xmem.x1 tran2.xmem.x1 +plot xmem.x1 tran1.xmem.x1 tran2.xmem.x1 title 'Memristor with threshold: resistance' +* resistance versus voltage (change occurs only above threshold!) +plot xmem.x1 vs v(1) tran1.xmem.x1 vs tran1.v(1) tran2.xmem.x1 vs tran2.v(1) title 'Memristor with threshold: resistance' +* current through resistor for all plots versus voltage +plot i(v1) vs v(1) tran1.i(v1) vs tran1.v(1) tran2.i(v1) vs tran2.v(1) title 'Memristor with threshold: external current loops' +.endc + +.end diff --git a/Windows/spice/examples/memristor/memristor_x.sp b/Windows/spice/examples/memristor/memristor_x.sp new file mode 100644 index 00000000..1c283e73 --- /dev/null +++ b/Windows/spice/examples/memristor/memristor_x.sp @@ -0,0 +1,83 @@ +Memristor with threshold as XSPICE code model +* Y. V. Pershin, M. Di Ventra: "SPICE model of memristive devices with threshold", +* arXiv:1204.2600v1 [physics.comp-ph] 12 Apr 2012, +* http://arxiv.org/pdf/1204.2600.pdf + +* XSPICE code model, parameter selection and plotting by +* Holger Vogt 2012 + +* ac and op (dc) simulation just use start resistance rinit! + +.param stime=10n +.param vmax = 4.2 + +* send parameters to the .control section +.csparam stime={stime} +.csparam vmax={vmax} + +*Xmem 1 0 memristor +* triangular sweep (you have to adapt the parameters to 'alter' command in the .control section) +*V1 1 0 DC 0 PWL(0 0 '0.25*stime' 'vmax' '0.5*stime' 0 '0.75*stime' '-vmax' 'stime' 0) +* sinusoidal sweep for transient, dc for op, ac +V1 0 1 DC 0.1 ac 1 sin(0 'vmax' '1/stime') + +Rl 1 11 1k + +* memristor model with limits and threshold +* "artificial" parameters alpha, beta, and vt. beta and vt adapted to basic programming frequency +* just to obtain nice results! +* You have to care for the physics and set real values! +amen 11 2 memr +.model memr memristor (rmin=1k rmax=10k rinit=7k alpha=0 beta='20e3/stime' vt=1.6) + +vgnd 2 0 dc 0 + +* This is the original subcircuit model +.subckt memristor plus minus PARAMS: Ron=1K Roff=10K Rinit=7.0K alpha=0 beta=20e3/stime Vt=1.6 +Bx 0 x I='((f1(V(plus)-V(minus))> 0) && (V(x) < Roff)) ? {f1(V(plus)-V(minus))}: ((((f1(V(plus)-V(minus)) < 0) && (V(x)>Ron)) ? {f1(V(plus)-V(minus))}: 0)) ' +Vx x x1 dc 0 +Cx x1 0 1 IC={Rinit} +Rmem plus minus r={V(x)} +.func f1(y)={beta*y+0.5*(alpha-beta)*(abs(y+Vt)-abs(y-Vt))} +.ends + +* transient simulation same programming voltage but rising frequencies +.control +*** first simulation *** +op +print all +ac lin 101 1 100k +plot v(11) +* approx. 100 simulation points +let deltime = stime/100 +tran $&deltime $&stime uic +* plot i(v1) vs v(1) +*** you may just stop here *** +* raise the frequency +let newfreq = 1.2/stime +let newstime = stime/1.2 +let deltime = newstime/100 +alter @V1[sin] [ 0 $&vmax $&newfreq ] +tran $&deltime $&newstime uic +* raise the frequency even more +let newfreq = 1.4/stime +let newstime = stime/1.4 +let deltime = newstime/100 +alter @V1[sin] [ 0 $&vmax $&newfreq ] +tran $&deltime $&newstime uic +* the resistor currents +plot tran1.alli tran2.alli alli title 'Memristor with threshold: currents' +* calculate resistance (avoid dividing by zero) +let res = v(1)/(I(v1) + 1e-16) +let res1 = tran1.v(1)/(tran1.I(v1) + 1e-16) +let res2 = tran2.v(1)/(tran2.I(v1) + 1e-16) +* resistance versus time plot +settype impedance res res1 res2 +plot res vs time res1 vs tran1.time res2 vs tran2.time title 'Memristor with threshold: resistance' +* resistance versus voltage (change occurs only above threshold!) +plot res vs v(1) res1 vs tran1.v(1) res2 vs tran2.v(1) title 'Memristor with threshold: resistance' +* current through resistor for all plots versus voltage +plot i(v1) vs v(1) tran1.i(v1) vs tran1.v(1) tran2.i(v1) vs tran2.v(1) title 'Memristor with threshold: external current loops' +.endc + +.end diff --git a/Windows/spice/examples/numparam/example.cir b/Windows/spice/examples/numparam/example.cir new file mode 100644 index 00000000..6e13bc06 --- /dev/null +++ b/Windows/spice/examples/numparam/example.cir @@ -0,0 +1,16 @@ +* Param-example +.param amplitude= 1V + +.subckt myfilter in out rval=100k cval=100nF +Ra in p1 {2*rval} +Rb p1 out {2*rval} +C1 p1 0 {2*cval} +Ca in p2 {cval} +Cb p2 out {cval} +R1 p2 0 {rval} +.ends myfilter + +X1 input output myfilter rval=1k cval=1n +V1 input 0 AC {amplitude} + +.end diff --git a/Windows/spice/examples/numparam/pin.mod b/Windows/spice/examples/numparam/pin.mod new file mode 100644 index 00000000..b035cd2f --- /dev/null +++ b/Windows/spice/examples/numparam/pin.mod @@ -0,0 +1,33 @@ +* PIN model +* line 2 +* line 3 +* -- Summary ------------------------------- +* This is a simple spice model of a PIN diode. +* +* -- Description --------------------------- +* It is a three node device; one input node (relative to ground) and two +* output nodes (cathode and anode) +* + +* -- Model ---------------------------------- +.subckt SIMPLE_PIN input cathode anode resp=0.5 + +* Input photocurrent is modled by a voltage +* This generates a current using a linear voltage-controlled current source +Gin dk da input 0 {resp} +Rin input 0 1G +Cin input 0 {resp} + +* The pn-junction that generates this photocurrent in the real device is modelled +* here by a simple diode +Dpn da dk pndiode + +* terminal resistances +Ra anode da 0.001ohm +Rk cathode dk 0.001ohm + +* subsircuit models: +.MODEL pndiode D IS=0.974p RS=0.1 N=1.986196 BV=7.1 IBV=0.1n ++ CJO=99.2p VJ=0.455536 M=0.418717 TT=500n + +.ends diff --git a/Windows/spice/examples/numparam/pintest.cir b/Windows/spice/examples/numparam/pintest.cir new file mode 100644 index 00000000..80702e14 --- /dev/null +++ b/Windows/spice/examples/numparam/pintest.cir @@ -0,0 +1,32 @@ +* Test circuit for pin.mod + +*.include C:\Spice\tests\numparam\pin.mod +.include pin.mod + +* Photodiode supply +Vbias psu 0 10V + +* Light input is modeled by a voltage source that we can vary +Vlight input 0 2mW + +* The pin diode +Xpin input cathode anode SIMPLE_PIN resp=0.7 + +* monitor resistor +Rmon anode 0 1ohm + +* Quench restistor +Rq psu cathode 1k + +*.dc vlight 0 5mW 0.01mW + +.dc vlight 0 10mW 0.01mW + +.control +dc vlight 0 10mW 0.01mW +*write pintest.raw all +plot V(anode) +.endc + +.end + diff --git a/Windows/spice/examples/pss/colpitt_osc_pss.cir b/Windows/spice/examples/pss/colpitt_osc_pss.cir new file mode 100644 index 00000000..8d0583ae --- /dev/null +++ b/Windows/spice/examples/pss/colpitt_osc_pss.cir @@ -0,0 +1,22 @@ +Colpitt's Oscillator Circuit +* Colpitt is an harmonic oscillator (LC based) which use +* a capacitive partition of resonator to feed the single +* active device. +* Predicted frequency is about 3.30435e+06 Hz. + +* Models: +.model qnl npn(level=1 bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf cjc=2pf va=50) + +r1 1 0 1 +q1 2 1 3 qnl +vcc 4 0 5 +rl 4 2 750 +c1 2 3 500p +c2 4 3 4500p +l1 4 2 5uH +re 3 6 4.65k +vee 6 0 dc -10 pwl 0 0 1e-9 -10 + +*.tran 30n 12u +.pss 3.1e6 500e-6 3 256 10 50 5e-3 + diff --git a/Windows/spice/examples/pss/compl_cross_quad_osc_pss.cir b/Windows/spice/examples/pss/compl_cross_quad_osc_pss.cir new file mode 100644 index 00000000..b45e730d --- /dev/null +++ b/Windows/spice/examples/pss/compl_cross_quad_osc_pss.cir @@ -0,0 +1,35 @@ +Complimentary Cross Quad CMOS Oscillator +* Predicted frequency is 5.61224e+08 Hz. +* +* PLOT i1 + +* Supply +vdd vdd gnd 1.2 pwl 0 1.2 1e-9 1.2 +rdd vdd vdd_ana 70m +rgnd gnd gnd_ana 70m + +* Cross quad +mpsx v_plus v_minus vdd_ana vdd_ana pch w=10u l=0.1u +mnsx v_plus v_minus gnd_ana gnd_ana nch w=10u l=0.1u +mpdx v_minus v_plus vdd_ana vdd_ana pch w=10u l=0.1u +mndx v_minus v_plus gnd_ana gnd_ana nch w=10u l=0.1u + +* Lumped elements model of real inductor +ls v_plus i1 19.462n ic=0.06 +rs i1 v_minus 7.789 +cs v_plus v_minus 443f +coxs v_plus is 2.178p +coxd v_minus id 2.178p +rsis is gnd_ana 308 +rsid id gnd_ana 308 +csis is gnd_ana 51f +csid id gnd_ana 51f + +* Parallel capacitor to determine leading resonance +cp v_plus v_minus 3.4p + +.model nch nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) + +*.tran 0.05n 1u uic +.pss 500e6 1u 1 1024 10 10 5e-3 uic diff --git a/Windows/spice/examples/pss/hartley_osc_pss.cir b/Windows/spice/examples/pss/hartley_osc_pss.cir new file mode 100644 index 00000000..bd1eef3d --- /dev/null +++ b/Windows/spice/examples/pss/hartley_osc_pss.cir @@ -0,0 +1,21 @@ +Hartley's Oscillator Circuit +* Hartley is an harmonic oscillator (LC based) which use +* an inductive partition of resonator to feed the single +* active device. Output is taken on node 2. +* Prediceted frequency is about 121.176 Hz. +* +* PLOT V(3) + +* Models: +.model qnl npn(level=1 bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf cjc=2pf va=50) + +vcc 1 0 5 pwl 0 0 1e-5 5 +r1 1 2 0.2k +q1 2 3 0 qnl +c1 3 4 633n +l1 3 0 1.5 +l2 0 4 500m +r2 4 2 100 + +*.tran 300n 50m +.pss 50 200e-3 2 1024 11 10 5e-3 uic diff --git a/Windows/spice/examples/pss/ring_osc_pss.cir b/Windows/spice/examples/pss/ring_osc_pss.cir new file mode 100644 index 00000000..d2649605 --- /dev/null +++ b/Windows/spice/examples/pss/ring_osc_pss.cir @@ -0,0 +1,29 @@ +Ring CMOS Oscillator +* Oscillation is taken on node "bout". +* Predicted frequency is 3.8e+09 Hz. +* +* PLOT bout + +* Supply +vdd vdd gnd 1.2 pwl 0 1.2 1e-9 1.2 +rdd vdd vdd_ana 70m +rgnd gnd gnd_ana 70m + +* Inverter +mp1 inv1 inv3 vdd_ana vdd_ana pch w=10u l=0.18u +mn1 inv1 inv3 gnd_ana gnd_ana nch w=10u l=0.18u +mp2 inv2 inv1 vdd_ana vdd_ana pch w=10u l=0.18u +mn2 inv2 inv1 gnd_ana gnd_ana nch w=10u l=0.18u +mp3 inv3 inv2 vdd_ana vdd_ana pch w=10u l=0.18u +mn3 inv3 inv2 gnd_ana gnd_ana nch w=10u l=0.18u + +* Buffer out +mp4 bout inv3 vdd_ana vdd_ana pch w=10u l=0.18u +mn4 bout inv3 gnd_ana gnd_ana nch w=10u l=0.18u + +.model nch nmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) +.model pch pmos ( version=4.4 level=54 lmin=0.1u lmax=20u wmin=0.1u wmax=10u ) + +*.tran 0.005n 100n +*.plot tran v(4) +.pss 624e6 500n 1 1024 10 5 5e-3 uic diff --git a/Windows/spice/examples/pss/vackar_osc_pss.cir b/Windows/spice/examples/pss/vackar_osc_pss.cir new file mode 100644 index 00000000..13ce1a12 --- /dev/null +++ b/Windows/spice/examples/pss/vackar_osc_pss.cir @@ -0,0 +1,21 @@ +Vackar's Oscillator Circuit +* Vackar is a derivation of Colpitt's oscillator (LC based). +* Oscillation is taken on node 4. +* Predicted frequency is 1.91803e+06Hz. + +* Models: +.model qnl npn(level=1 bf=80 rb=100 ccs=2pf tf=0.3ns tr=6ns cje=3pf cjc=2pf va=50) + +vcc 1 0 5 pwl 0 10 1e-9 5 +lrfc 1 2 100u +cdec 2 0 7n +q1 3 2 0 qnl +rb 3 0 4700 +c1 3 4 100p +c2 3 0 600p +c0 4 0 1n +l1 4 1 6.2u + +*.tran 30n 12u +*.plot tran v(4) +.pss 1e6 10e-6 4 1024 10 50 5e-3 uic diff --git a/Windows/spice/examples/pss/vdp_osc_pss.cir b/Windows/spice/examples/pss/vdp_osc_pss.cir new file mode 100644 index 00000000..f4e66815 --- /dev/null +++ b/Windows/spice/examples/pss/vdp_osc_pss.cir @@ -0,0 +1,17 @@ +Van Der Pol Oscillator +* Prediceted frequency is about 4.54167e+06 Hz. + +* Third harmonic is high as the first one +Ba gib 0 I=-1e-2*v(gib,0)+1e-2*v(gib,0)^3 +* Q is about 10 +La gib 0 1.2e-6 +Ra gib 0 158.113 +Ca gib 0 1e-9 ic=0.5 +*La gib 0 1e-9 +*Ra gib 0 474.6 +*Ca gib 0 1e-9 ic=0.5 +* Ghost node... Test for my PSS! +Rb bad 0 1k + +*.tran 1e-9 150e-6 uic +.pss 0.8e6 130e-6 1 50 10 50 5e-3 uic diff --git a/Windows/spice/examples/snapshot/adder_mos.cir b/Windows/spice/examples/snapshot/adder_mos.cir new file mode 100644 index 00000000..603f1f11 --- /dev/null +++ b/Windows/spice/examples/snapshot/adder_mos.cir @@ -0,0 +1,26 @@ + Example: snsave +* load a circuit (including transistor models and .tran command) +* starts transient simulation until stop point +* store intermediate data to file +* begin with editing the file location +* to be run with 'ngspice adder_mos.cir' + +.include adder_mos_circ.cir + +.control +*cd to where all files are located +cd D:\Spice_general\ngspice\examples\snapshot +set noaskquit +unset ngdebug +set noinit +save vcc#branch 10 +iplot v(10) +*interrupt condition for the simulation +stop when time > 500n +* simulate +run +* store snapshot to file +snsave adder500.snap +.endc + +.END diff --git a/Windows/spice/examples/snapshot/adder_mos_circ.cir b/Windows/spice/examples/snapshot/adder_mos_circ.cir new file mode 100644 index 00000000..b0a591e4 --- /dev/null +++ b/Windows/spice/examples/snapshot/adder_mos_circ.cir @@ -0,0 +1,61 @@ +* ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER + +*** SUBCIRCUIT DEFINITIONS +.SUBCKT NAND in1 in2 out VDD +* NODES: INPUT(2), OUTPUT, VCC +M1 out in2 Vdd Vdd p1 W=3u L=1u +M2 net.1 in2 0 0 n1 W=3u L=2u +M3 out in1 Vdd Vdd p1 W=3u L=1u +M4 out in1 net.1 0 n1 W=3u L=2u +.ENDS NAND + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 NAND +X2 1 7 8 6 NAND +X3 2 7 9 6 NAND +X4 8 9 10 6 NAND +X5 3 10 11 6 NAND +X6 3 11 12 6 NAND +X7 10 11 13 6 NAND +X8 12 13 4 6 NAND +X9 11 7 5 6 NAND +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** DEFINE NOMINAL CIRCUIT +VCC 99 0 DC 3.3V +VIN1A 1 0 PULSE(0 3 0 10NS 10NS 10NS 50NS) +VIN1B 2 0 PULSE(0 3 0 10NS 10NS 20NS 100NS) +VIN2A 3 0 PULSE(0 3 0 10NS 10NS 40NS 200NS) +VIN2B 4 0 PULSE(0 3 0 10NS 10NS 80NS 400NS) +VIN3A 5 0 PULSE(0 3 0 10NS 10NS 160NS 800NS) +VIN3B 6 0 PULSE(0 3 0 10NS 10NS 320NS 1600NS) +VIN4A 7 0 PULSE(0 3 0 10NS 10NS 640NS 3200NS) +VIN4B 8 0 PULSE(0 3 0 10NS 10NS 1280NS 6400NS) +X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT +*RBIT0 9 0 100K +*RBIT1 10 0 100K +*RBIT2 11 0 100K +*RBIT3 12 0 100K +*RCOUT 13 0 100K + +.TRAN 1NS 1000NS + +.model n1 nmos level=8 version=3.3.0 +.model p1 pmos level=8 version=3.3.0 + +.END diff --git a/Windows/spice/examples/snapshot/adder_snload.script b/Windows/spice/examples/snapshot/adder_snload.script new file mode 100644 index 00000000..f5556347 --- /dev/null +++ b/Windows/spice/examples/snapshot/adder_snload.script @@ -0,0 +1,15 @@ +* SCRIPT: ADDER - 4 BIT BINARY +* script to reload circuit and continue the simulation +* begin with editing the file location +* to be started with 'ngspice adder_snload.script' + +.control +* cd to where all files are located +cd D:\Spice_general\ngspice\examples\snapshot +* load circuit and snpashot file +snload adder_mos_circ.cir adder500.snap +* continue simulation +resume +* plot some node voltages +plot v(10) v(11) v(12) +.endc diff --git a/Windows/spice/examples/transient-noise/README b/Windows/spice/examples/transient-noise/README new file mode 100644 index 00000000..ce9d4105 --- /dev/null +++ b/Windows/spice/examples/transient-noise/README @@ -0,0 +1,15 @@ +* noi-ring51-demo +ring oszillator with one noisy inverter +(requires 45min on a i7 860) + +* noi-sc-tr +noise source sampled + +* noise_vnoi +just a few 1/f and white noise sources + +* shot_ng +emulation of shot noise in a diode + +* rts-1.cir +random telegraph signals noise diff --git a/Windows/spice/examples/transient-noise/modelcard.nmos b/Windows/spice/examples/transient-noise/modelcard.nmos new file mode 100644 index 00000000..83ca9849 --- /dev/null +++ b/Windows/spice/examples/transient-noise/modelcard.nmos @@ -0,0 +1,41 @@ +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS ++Level= 8 version=3.3.0 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + + + + + + diff --git a/Windows/spice/examples/transient-noise/modelcard.pmos b/Windows/spice/examples/transient-noise/modelcard.pmos new file mode 100644 index 00000000..f50fe0a6 --- /dev/null +++ b/Windows/spice/examples/transient-noise/modelcard.pmos @@ -0,0 +1,31 @@ +.model P1 PMOS ++Level= 8 version=3.3.0 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + + + + diff --git a/Windows/spice/examples/transient-noise/noi-ring51-demo.cir b/Windows/spice/examples/transient-noise/noi-ring51-demo.cir new file mode 100644 index 00000000..8bc6f6ed --- /dev/null +++ b/Windows/spice/examples/transient-noise/noi-ring51-demo.cir @@ -0,0 +1,59 @@ +* 51 stage Ring-Osc. BSIM3, transient noise +* will need 45 min on a i7 860 with 4 threads + +* closes the loop between inverters xinv1 and xinv5 +vin in out dc 0.5 pulse 0.5 0 0.1n 5n 1 1 1 + +vdd dd 0 dc 0 pulse 0 2.2 0 1n 1 1 1 + +vss ss 0 dc 0 +ve sub 0 dc 0 + +vpe well 0 2.2 + +* noisy inverters +xiinv2 dd ss sub well out25 out50 inv253 +xiinv1 dd ss sub well in out25 inv253 + +*very noisy inverter +xiinv5 dd ss sub well out50 out inv1_2 +*output amplifier +xiinv11 dd ss sub well out25 bufout inv1 +cout bufout ss 0.2pF + +.option itl1=500 gmin=1e-15 itl4=10 noacct + +* .dc vdd 0 2 0.01 +.tran 0.01n 500n + +.save in bufout v(t1) + +.include modelcard.nmos +.include modelcard.pmos + +.include noilib-demo.h + +.control +unset ngdebug +* first run +save bufout $ needed for restricting memory usage +rusage +tran 8p 10000n +rusage +plot bufout xlimit 90n 95n +linearize +fft bufout +* next run +reset +save bufout +alter @v.xiinv5.vn1[trnoise] = [ 0 0 0 0 ] $ no noise +tran 8p 10000n +rusage +plot bufout xlimit 90n 95n +linearize +fft bufout +plot mag(bufout) mag(sp2.bufout) xlimit 0 2G ylimit 1e-11 0.1 ylog +.endc + + +.end diff --git a/Windows/spice/examples/transient-noise/noi-sc-tr.cir b/Windows/spice/examples/transient-noise/noi-sc-tr.cir new file mode 100644 index 00000000..19c738b7 --- /dev/null +++ b/Windows/spice/examples/transient-noise/noi-sc-tr.cir @@ -0,0 +1,53 @@ +* simple sample & hold, transient noise + +* switch control +* PULSE(V1 V2 TD TR TF PW PER) +vgate1 ga1 0 dc 0 pulse (0 1 0 10n 10n 90n 200n) + +Switch1 1 2 ga1 0 smodel1 + +* noisy input +* rms value white, time step, exponent < 2, rms value 1/f +vin 1 0 dc 0 trnoise 0.1m 0.2n 1 0.1m +*vin 1 0 dc 0 trnoise 0.1m 0.2n 0 0.1m + +* output +c2 2 0 10p + +* second S&H +vgate2 ga2 0 dc 0 pulse (0 1 140n 10n 10n 30n 200n) +*Buffer EXXXXXXX N+ N- NC+ NC- VALUE +e1 4 0 2 0 1 +Switch2 4 3 ga2 0 smodel2 +c3 3 0 10p + +.option itl1=500 gmin=1e-15 itl4=10 acct + +.model smodel1 sw vt=0.5 ron=100 +.model smodel2 sw vt=0.5 ron=100 + +.tran 0.4n 100u + + +.control +unset ngdebug +set filetype=ascii +rusage +run +rusage all +write noi_test.out v(1) +plot v(2) v(3) xlimit 4u 5u +plot v(ga1) v(ga2) xlimit 4u 5u +linearize +*rms v(1) +fft v(3) +plot mag(v(3)) loglog xlimit 1e4 1e8 ylimit 1e-10 1e-4 +setplot tran1 +linearize +psd 101 v(3) +plot mag(v(3)) xlimit 0 3e7 ylimit 0 10u + +.endc + + +.end diff --git a/Windows/spice/examples/transient-noise/noilib-demo.h b/Windows/spice/examples/transient-noise/noilib-demo.h new file mode 100644 index 00000000..84e119d3 --- /dev/null +++ b/Windows/spice/examples/transient-noise/noilib-demo.h @@ -0,0 +1,56 @@ + +* standard inverter made noisy +*.subckt inv1 dd ss sub well in out +*vn1 out outi dc 0 noise 0.1 0.3n 1.0 0.1 +*mn1 outi in ss sub n1 w=2u l=0.25u AS=3p AD=3p PS=4u PD=4u +*mp1 outi in dd well p1 w=4u l=0.25u AS=7p AD=7p PS=6u PD=6u +*.ends inv1 + +* standard inverter +.subckt inv1 dd ss sub well in out +mn1 out in ss sub n1 w=2u l=0.25u AS=3p AD=3p PS=4u PD=4u +mp1 out in dd well p1 w=4u l=0.25u AS=7p AD=7p PS=6u PD=6u +.ends inv1 + +* very noisy inverter (noise on vdd and well) +.subckt inv1_1 dd ss sub well in out +vn1 dd idd dc 0 trnoise 0.05 0.05n 1 0.05 +vn2 well iwell dc 0 trnoise 0.05 0.05n 1 0.05 +mn1 out in ss sub n1 w=2u l=0.25u AS=3p AD=3p PS=4u PD=4u +mp1 out in idd iwell p1 w=4u l=0.25u AS=7p AD=7p PS=6u PD=6u +*Cout out 0 0.1p +.ends inv1_1 + + +* another very noisy inverter +.subckt inv1_2 dd ss sub well in out +vn1 out outi dc 0 trnoise 0.05 8p 1.0 0.001 +mn1 outi in ss sub n1 w=2u l=0.25u AS=3p AD=3p PS=4u PD=4u +mp1 outi in dd well p1 w=4u l=0.25u AS=7p AD=7p PS=6u PD=6u +*Cout out 0 0.1p +.ends inv1_2 + +* another very noisy inverter with current souces parallel to transistor +.subckt inv13 dd ss sub well in outi +in1 ss outi dc 0 noise 200u 0.05n 1.0 50u +mn1 outi in ss sub n1 w=2u l=0.25u AS=3p AD=3p PS=4u PD=4u +in2 dd outi dc 0 noise 200u 0.05n 1.0 50u +mp1 outi in dd well p1 w=4u l=0.25u AS=7p AD=7p PS=6u PD=6u +*Cout out 0 0.1p +.ends inv13 + +.subckt inv53 dd ss sub well in out +xinv1 dd ss sub well in 1 inv1 +xinv2 dd ss sub well 1 2 inv1 +xinv3 dd ss sub well 2 3 inv1 +xinv4 dd ss sub well 3 4 inv1 +xinv5 dd ss sub well 4 out inv1 +.ends inv53 + +.subckt inv253 dd ss sub well in out +xinv1 dd ss sub well in 1 inv53 +xinv2 dd ss sub well 1 2 inv53 +xinv3 dd ss sub well 2 3 inv53 +xinv4 dd ss sub well 3 4 inv53 +xinv5 dd ss sub well 4 out inv53 +.ends inv253 diff --git a/Windows/spice/examples/transient-noise/noise_vnoi.cir b/Windows/spice/examples/transient-noise/noise_vnoi.cir new file mode 100644 index 00000000..a589d1a0 --- /dev/null +++ b/Windows/spice/examples/transient-noise/noise_vnoi.cir @@ -0,0 +1,31 @@ +* Random noise test +* internal noise source + +* one over f +VNOI1 1 0 DC 0 TRNOISE(0n 1n 1.7 1n) +VNOI2 2 0 DC 0 TRNOISE(0n 1n 1.4 1n) +VNOI3 3 0 DC 0 TRNOISE(0n 1n 1.0 1n) +VNOI4 4 0 DC 0 TRNOISE(0n 1n 0.5 1n) +* white +VNOI5 5 0 DC 0 TRNOISE(1n 1n 0 0) +* both +VNOI6 6 0 DC 0 TRNOISE(1n 1n 1 1n) + +* 250000 sample points +.tran 1n 250u + +.control +run +plot v(1) v(2) v(3) v(4) v(5) v(6) +plot v(1) v(2) v(3) v(4) v(5) v(6) xlimit 102.0u 102.01u ylimit -3n 3n +linearize +meas tran vavg5 AVG v(5) from=0 to=250u +meas tran vpp5 PP v(5) from=0 to=250u +meas tran vrms5 RMS v(5) from=0 to=250u +fft v(1) v(2) v(3) v(4) v(5) v(6) +plot mag(v(1)) mag(v(2)) mag(v(3)) mag(v(4)) mag(v(5)) loglog xlimit 1e3 1e9 +plot mag(v(6)) loglog xlimit 1e3 1e9 +.endc + +.end + diff --git a/Windows/spice/examples/transient-noise/rts-1.cir b/Windows/spice/examples/transient-noise/rts-1.cir new file mode 100644 index 00000000..f35256dc --- /dev/null +++ b/Windows/spice/examples/transient-noise/rts-1.cir @@ -0,0 +1,29 @@ +* white noise, 1/f noise, RTS noise + +* voltage source +VRTS2 13 12 DC 0 trnoise(0 0 0 0 5m 18u 30u) +VRTS3 11 0 DC 0 trnoise(0 0 0 0 10m 20u 40u) +VALL 12 11 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) + +VW1of 21 0 DC trnoise(1m 1u 1.0 0.1m) + +* current source +IRTS2 10 0 DC 0 trnoise(0 0 0 0 5m 18u 30u) +IRTS3 10 0 DC 0 trnoise(0 0 0 0 10m 20u 40u) +IALL 10 0 DC 0 trnoise(1m 1u 1.0 0.1m 15m 22u 50u) +R10 10 0 1 + +IW1of 9 0 DC trnoise(1m 1u 1.0 0.1m) +Rall 9 0 1 + +* 500000 sample points +.tran 1u 500u + +.control +run +plot v(13) v(21) +plot v(10) v(9) +.endc + +.end + diff --git a/Windows/spice/examples/transient-noise/shot_ng.cir b/Windows/spice/examples/transient-noise/shot_ng.cir new file mode 100644 index 00000000..ed06c81c --- /dev/null +++ b/Windows/spice/examples/transient-noise/shot_ng.cir @@ -0,0 +1,27 @@ +* Shot noise test with B source, diode +* voltage on device (diode, forward) +Vdev out 0 DC 0 PULSE(0.4 0.45 10u) +* diode, forward direction, to be modeled with noise +D1 mess 0 DMOD +.model DMOD D IS=1e-14 N=1 +X1 0 mess out ishot +* device between 1 and 2 +* new output terminals of device including noise: 1 and 3 +.subckt ishot 1 2 3 +* white noise source with rms 1V +VNG 0 11 DC 0 TRNOISE(1 1n 0 0) +*measure the current i(v1) +V1 2 3 DC 0 +* calculate the shot noise +* sqrt(2*current*q*bandwidth) +BI 1 3 I=sqrt(2*abs(i(v1))*1.6e-19*1e7)*v(11) +.ends ishot +* 20000 sample points +.tran 1n 20u +.control +run +plot (-1)*i(vdev) +meas tran vdev_rms avg i(vdev) from=0u to=9.9u +meas tran vdev_rms avg i(vdev) from=10.1u to=20u +.endc +.end diff --git a/Windows/spice/examples/various/FFT_Leakage.cir b/Windows/spice/examples/various/FFT_Leakage.cir new file mode 100644 index 00000000..b2bcfb7d --- /dev/null +++ b/Windows/spice/examples/various/FFT_Leakage.cir @@ -0,0 +1,53 @@ +FFT_Leakage_tests http://www.idea2ic.com/ +*=========Create_Signal================== +VTime VTime 0 DC 0 PWL( 0 0 1 1) +Vfreq Vfreq 0 DC 5.5k +BVAC IN 0 V = sin( 6.283185307179586*V(VFreq)*V(VTime)) +.control +*TRAN TSTEP TSTOP TSTART TMAX ?UIC? +tran 1u .999m 0 1u +set pensize = 2 +linearize +let numb2 = length(in) +print numb2 + +*=========Do_FFT_and_Plot_As_dB_Freq================== +let ac = in +j(0) +let ac_fft=fft(ac) +let numb_f2 = (numb2)/2 -1 +compose freq start = 1 stop = $&numb_f2 step =1 +compose vreal start = 1 stop = $&numb_f2 step =1 +compose vimag start = 1 stop = $&numb_f2 step =1 +let j = 0 +repeat $&numb_f2 +let freq[j] = freq[j] +let vreal[j] = 2*real(ac_fft[j+1]) +let vimag[j] = 2*imag(ac_fft[j+1]) +let j = j +1 +end +plot dB(abs(vreal+1f)) dB(abs(vimag+1f)) vs freq xlog + +*=========Extract_Error_Signal========================= +let funBin = 5k/1000 +let unvect = unitvec(numb2) +let fundspec = unvect*0 +j(0) +let fundspec[funBin] = real(ac_fft[funBin]) +j(imag(ac_fft[funBin] )) +let fundspec[numb2-funBin] = real(ac_fft[numb2-funBin]) +j(imag(ac_fft[numb2-funBin] )) +let fund = ifft(fundspec) +let dc_ofset = real(ac_fft[0]) +let thdspec = ac_fft +let thdspec[0] = 0 +j(0) +let thdspec[funBin] = 0 +j(0) +let thdspec[numb2-funBin] = 0 +j(0) +let thd = ifft(thdspec) +plot norm(in) norm(fund) norm(thd)/2 + +*=========Calc_Values========================= +let rms_Fund = sqrt(mean(fund*fund)) +let rms_THD = sqrt(mean(thd*thd)) +let THD_percent = 100*rms_THD/rms_Fund +let FREQ_Hz = VFreq[0] +echo "Freq_Hz=$&FREQ_Hz THD_percent=$&THD_percent Fund_rms=$&rms_Fund THD_rms=$&rms_THD " + +.endc +.end diff --git a/Windows/spice/examples/various/FFT_tests.cir b/Windows/spice/examples/various/FFT_tests.cir new file mode 100644 index 00000000..e7ede5ec --- /dev/null +++ b/Windows/spice/examples/various/FFT_tests.cir @@ -0,0 +1,123 @@ +FFT_tests http://www.idea2ic.com/ +.control +set units=degrees +let a = vector(16) +*plot a vs a +set pensize = 2 +*=========Need_a_complex_input==================== +let ac = a+j(0) +print a ac +*plot fft(a) vs a +*plot real(fft(ac)) imag(fft(ac)) vs a +* fft(a) fft(ac) + +*=========DC_Works==================== +let b = unitvec(16) +let bc = b+j(0) +*plot fft(b) vs a title DC_WORKS +*print fft(b) fft(bc) + +*=========DC_Plus_cos_Remove_AC==================== +let numb = length(b) +print numb + +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title DC_Plus_COS + +let fftac[2]=(0,0) +let fftac[14]=(0,0) +let ifftac = ifft(fftac) +plot ifftac ac vs a title COS_REMOVED + +*=========DC_Plus_cos_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifftac ac vs a title COS_With_DC_REMOVED + +*=========DC_Plus_sin_Remove_AC==================== +let indx = 0 +repeat $&numb +let ac[indx]= sin(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title DC_Plus_SIN + +let fftac[2]=(0,0) +let fftac[14]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title SIN_REMOVED + +*=========DC_Plus_sin_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= sin(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title SIN_With_DC_REMOVED + +*=========DC_Plus_cos_Nyqusit_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/2)+1 +j(0) +let indx = indx +1 +end + +plot ac vs a title Nyq_COS + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title Nyq_FREQ_COS +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title COS_With_DC_REMOVED +*=========DC_Plus_sin_Nyqusit_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= sin(indx*360/2)+1 +j(0) +let indx = indx +1 +end + +plot ac vs a title Nyq_SIN + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title Nyq_FREQ_SIN +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title COS_With_DC_REMOVED + +*=========DC_Plus_COS_Remove_One_BIN==================== +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +let fftac[2]=(0,0) +plot real(fftac) imag(fftac) vs a title DC_Plus_Cos + +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title ONE_BIN_REMOVED + +plot real(ifft(fftac)) imag(ifft(fftac)) vs a title ONE_BIN_REMOVED + +.endc +.end diff --git a/Windows/spice/examples/various/adder_mos.cir b/Windows/spice/examples/various/adder_mos.cir new file mode 100644 index 00000000..9b85e093 --- /dev/null +++ b/Windows/spice/examples/various/adder_mos.cir @@ -0,0 +1,79 @@ + ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER + +*** SUBCIRCUIT DEFINITIONS +.SUBCKT NAND in1 in2 out VDD +* NODES: INPUT(2), OUTPUT, VCC +M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +.ENDS NAND + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 NAND +X2 1 7 8 6 NAND +X3 2 7 9 6 NAND +X4 8 9 10 6 NAND +X5 3 10 11 6 NAND +X6 3 11 12 6 NAND +X7 10 11 13 6 NAND +X8 12 13 4 6 NAND +X9 11 7 5 6 NAND +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** POWER +VCC 99 0 DC 3.3V + +*** ALL INPUTS +VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) +VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) +VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) +VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) +VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) +VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) +VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) +VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) + +*** DEFINE NOMINAL CIRCUIT +X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT + +.option noinit acct +.TRAN 500p 6400NS +* save inputs +.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) + +* use BSIM3 model with default parameters +.model n1 nmos level=49 version=3.3.0 +.model p1 pmos level=49 version=3.3.0 +*.include ./Modelcards/modelcard32.nmos +*.include ./Modelcards/modelcard32.pmos + +.control +pre_set strict_errorhandling +unset ngdebug +*save outputs and specials +save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) +run +display +* plot the inputs, use offset to plot on top of each other +plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 +* plot the outputs, use offset to plot on top of each other +plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 +.endc + +.END diff --git a/Windows/spice/examples/various/agauss_test.cir b/Windows/spice/examples/various/agauss_test.cir new file mode 100644 index 00000000..c2532751 --- /dev/null +++ b/Windows/spice/examples/various/agauss_test.cir @@ -0,0 +1,48 @@ +* agauss test in ngspice +* generate a sequence of gaussian distributed random numbers. +* test the distribution by sorting the numbers into +* a histogram (buckets) +* chapt. 17.8.6 +.control + define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) + let mc_runs = 200 + let run = 0 + let no_buck = 8 $ number of buckets + let bucket = unitvec(no_buck) $ each element contains 1 + let delta = 3e-11 $ width of each bucket, depends + $ on avar and sig + let lolimit = 1e-09 - 3*delta + let hilimit = 1e-09 + 3*delta + + dowhile run < mc_runs + let val = agauss(1e-09, 1e-10, 3) $ get the random number + if (val < lolimit) + let bucket[0] = bucket[0] + 1 $ 'lowest' bucket + end + let part = 1 + dowhile part < (no_buck - 1) + if ((val < (lolimit + part*delta)) & ++ (val > (lolimit + (part-1)*delta))) + let bucket[part] = bucket[part] + 1 + break + end + let part = part + 1 + end + if (val > hilimit) +* 'highest' bucket + let bucket[no_buck - 1] = bucket[no_buck - 1] + 1 + end + let run = run + 1 + end + + let part = 0 + dowhile part < no_buck + let value = bucket[part] - 1 + set value = "$&value" +* print the buckets' contents + echo $value + let part = part + 1 + end + +.endc +.end diff --git a/Windows/spice/examples/various/gain_stage.cir b/Windows/spice/examples/various/gain_stage.cir new file mode 100644 index 00000000..adc22bfb --- /dev/null +++ b/Windows/spice/examples/various/gain_stage.cir @@ -0,0 +1,34 @@ +** MOSFET Gain Stage (AC): Benchmarking Implementation of BSIM4.0.0 +** by Weidong Liu 5/16/2000. +** output redirection into file +** chapter 17.8.8 + +M1 3 2 0 0 N1 L=1u W=4u +Rsource 1 2 100k +Rload 3 vdd 25k +Vdd vdd 0 1.8 +Vin 1 0 1.2 ac 0.1 + +.control +ac dec 10 100 1000Meg +plot v(2) v(3) +let flen = length(frequency) $ length of the vector +let loopcounter = 0 +echo output test > text.txt $ start new file test.txt +* loop +while loopcounter lt flen + let vout2 = v(2)[loopcounter] $ generate a single point complex vector + let vout2re = real(vout2) $ generate a single point real vector + let vout2im = imag(vout2) $ generate a single point imaginary vector + let vout3 = v(3)[loopcounter] $ generate a single point complex vector + let vout3re = real(vout3) $ generate a single point real vector + let vout3im = imag(vout3) $ generate a single point imaginary vector + let freq = frequency[loopcounter] $ generate a single point vector + echo bbb "$&freq" "$&vout2re" "$&vout2im" "$&vout3re" "$&vout3im" >> ++text.txt $ append text and data to file (continued fromm line above) + let loopcounter = loopcounter + 1 +end +.endc + +.MODEL N1 NMOS LEVEL=14 VERSION=4.3.0 TNOM=27 +.end diff --git a/Windows/spice/examples/various/modelcard.nmos b/Windows/spice/examples/various/modelcard.nmos new file mode 100644 index 00000000..9a9bd56c --- /dev/null +++ b/Windows/spice/examples/various/modelcard.nmos @@ -0,0 +1,34 @@ +.model N1 NMOS ++Level= 8 version=3.3.0 ++Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++Lw = 0 Lwl = 0 Lln = .316394 ++Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 ++vgs_max=4 vds_max=4 vbs_max=4 diff --git a/Windows/spice/examples/various/modelcard.pmos b/Windows/spice/examples/various/modelcard.pmos new file mode 100644 index 00000000..1f67f274 --- /dev/null +++ b/Windows/spice/examples/various/modelcard.pmos @@ -0,0 +1,29 @@ +.model P1 PMOS ++Level= 8 version=3.3.0 ++Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 ++vgs_max=4 vds_max=4 vbs_max=4 diff --git a/Windows/spice/examples/various/nic_soa.cir b/Windows/spice/examples/various/nic_soa.cir new file mode 100644 index 00000000..5752d99d --- /dev/null +++ b/Windows/spice/examples/various/nic_soa.cir @@ -0,0 +1,39 @@ +CMOS NIC +* +.subckt osc_cmos ib_osz lc ra vdd vss +m16 ib_osz ib_osz vss vss n1 w=20u l=1u m=8 +m15 ra ib_osz vss vss n1 w=20u l=1u m=2 +m8 net99 net95 ra ra n1 w=20u l=1u m=2 +m1 net95 net95 net93 net93 n1 w=20u l=1u m=2 +m25 net99 net99 vdd vdd p1 w=3.3u l=0.5u m=1 +m5 net99 net99 vdd vdd p1 w=20u l=1u m=5 +m4 net95 net99 vdd vdd p1 w=20u l=1u m=5 +r23 net99 vss r=38K +r18 net93 lc r=10 +.ends osc_cmos +* +.subckt psens LC +R1 LC P001 40K +L1 LC P002 14.9u +R2 P002 0 0.55 +L2 P001 0 1.4m +.ends psens +* +xi36 bias lc ra vdd 0 osc_cmos +v39 vdd 0 dc=3.5 pulse ( 0 3.5 10u 10n 10n 1 2 ) +r4 ra 0 3.972K +c23 lc 0 1.8n +i37 vdd bias dc=1u +* +xi18 lc psens +* +.option warn=1 +.control +tran 1u 1m 0 50n +plot v(LC) +.endc +* +.include modelcard.nmos +.include modelcard.pmos +* +.end diff --git a/Windows/spice/examples/various/param_sweep.cir b/Windows/spice/examples/various/param_sweep.cir new file mode 100644 index 00000000..79d5869e --- /dev/null +++ b/Windows/spice/examples/various/param_sweep.cir @@ -0,0 +1,29 @@ +parameter sweep +* resistive divider, R1 swept from start_r to stop_r +* replaces .STEP R1 1k 10k 1k +* chapter 16.13.4.2 + +R1 1 2 1k +R2 2 0 1k + +VDD 1 0 DC 1 +.dc VDD 0 1 .1 + +.control +let start_r = 1k +let stop_r = 10k +let delta_r = 1k +let r_act = start_r +* loop +while r_act le stop_r + alter r1 r_act + run + write dc-sweep.out v(2) + set appendwrite + let r_act = r_act + delta_r +end +plot dc1.v(2) dc2.v(2) dc3.v(2) dc4.v(2) dc5.v(2) ++ dc6.v(2) dc7.v(2) dc8.v(2) dc9.v(2) dc10.v(2) +.endc + +.end diff --git a/Windows/spice/examples/xspice/analog_models1_transient.sp b/Windows/spice/examples/xspice/analog_models1_transient.sp new file mode 100644 index 00000000..a74bd6ca --- /dev/null +++ b/Windows/spice/examples/xspice/analog_models1_transient.sp @@ -0,0 +1,65 @@ +Code Model Test - Transient: gain, summer, mult, divide, pwl +* +* +*** analysis type *** +.control +tran .1s 10s +plot v(1) v(10) v(20) v(30) v(40) v(50) +.endc +* +*** input sources *** +* +v1 1 0 DC PWL(0 0 10 10) +* +v2 2 0 DC 2 +* +*** gain block *** +a1 1 10 gain1 +.model gain1 gain (in_offset=0.0 gain=2.0 out_offset=0.0) +* +* +*** summer block *** +a2 [1 2] 20 summer1 +.model summer1 summer (in_offset=[0.0 0.0] in_gain=[1.0 1.0] ++ out_gain=1.0 out_offset=0.0) +* +* +*** mult block *** +a3 [1 1] 30 mult1 +.model mult1 mult (in_offset=[0.0 0.0] in_gain=[1.0 1.0] ++ out_gain=0.1 out_offset=0.0) +* +* +*** divider block *** +a4 2 1 40 divide1 +.model divide1 divide (num_offset=0.0 num_gain=1.0 den_offset=0.0 den_gain=1.0 ++ den_lower_limit=0.1 den_domain=1.0e-16 ++ fraction=false out_gain=1.0 out_offset=0.0) +* +* +*** pwl block *** +a5 1 50 pwl1 +.model pwl1 pwl (x_array=[-1.0 0.0 1.0 2.0 3.0 4.0 5.0] ++ y_array=[ 0.0 0.0 1.0 4.0 4.5 5.0 5.0] ++ input_domain=0.01 fraction=TRUE) +* +* +*** resistors to ground *** +r1 1 0 1k +r2 2 0 1k +r3 3 0 1k +* +r10 10 0 1k +r20 20 0 1k +r30 30 0 1k +r40 40 0 1k +r50 50 0 1k +* +* +.end + + + + + + diff --git a/Windows/spice/examples/xspice/delta-sigma/README b/Windows/spice/examples/xspice/delta-sigma/README new file mode 100644 index 00000000..3ce6ce63 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/README @@ -0,0 +1,25 @@ +A simple delta sigma converter using XSPICE +according to +Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005 +Fig. 2.13, p. 31; Fig. 2.27, p.58 + + +delta-sigma-1.cir +converter complete, tested against sine input + +mod1-ct.cir +first order modulator +consists of analog continuous time integrator and +digitally latched comparator + +count-latch-dac.cir +contains subcircuits of +10 bit digital latch +10 bit counter, non-revolving, saturating +simple 10 bit DAC with analog B source + +mod1-ct-test.cir +test of modulator with sine input, shows noise shaping 20dB/decade + +counter-test.cir +simple test with reset diff --git a/Windows/spice/examples/xspice/delta-sigma/count-latch-dac.cir b/Windows/spice/examples/xspice/delta-sigma/count-latch-dac.cir new file mode 100644 index 00000000..7a8c7d90 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/count-latch-dac.cir @@ -0,0 +1,81 @@ +* counter, latch DAC + +* 10 bit synchronous digital counter +* inhibit at overflow, no revolving +.subckt count10 din dinb dclk drs dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 + +* j k clk set reset out nout +ajk1 din dinb diclk ds1 drs dout1 dnout1 jkflop +ajk2 dout1 dout1 diclk ds2 drs dout2 dnout2 jkflop +ajk3 djk3 djk3 diclk ds3 drs dout3 dnout3 jkflop +ajk4 djk4 djk4 diclk ds4 drs dout4 dnout4 jkflop +ajk5 djk5 djk5 diclk ds1 drs dout5 dnout5 jkflop +ajk6 djk6 djk6 diclk ds2 drs dout6 dnout6 jkflop +ajk7 djk7 djk7 diclk ds3 drs dout7 dnout8 jkflop +ajk8 djk8 djk8 diclk ds4 drs dout8 dnout8 jkflop +ajk9 djk9 djk9 diclk ds3 drs dout9 dnout9 jkflop +ajk10 djk10 djk10 diclk ds4 drs dout10 dnout10 jkflop + +aand1 [dout1 dout2] djk3 and1 +aand2 [dout1 dout2 dout3] djk4 and1 +aand3 [dout1 dout2 dout3 dout4] djk5 and1 +aand4 [dout1 dout2 dout3 dout4 dout5] djk6 and1 +aand5 [dout1 dout2 dout3 dout4 dout5 dout6] djk7 and1 +aand6 [dout1 dout2 dout3 dout4 dout5 dout6 dout7] djk8 and1 +aand7 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8] djk9 and1 +aand8 [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9] djk10 and1 + +* inhibit revolving of counter, just let it saturate +* (footnote p. 57) +aand_all [dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10] dinhibit nand1 +aandclk [dclk dinhibit] diclk and1 + + +.model nand1 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 ++ input_load = 0.5e-12) + +.model and1 d_and(rise_delay = 1e-9 fall_delay = 1e-9 ++ input_load = 0.5e-12) + +.model jkflop d_jkff(clk_delay = 1.0e-9 set_delay = 1e-9 ++ reset_delay = 1e-9 ic = 0 rise_delay = 1.0e-9 ++ fall_delay = 1e-9) + +.ends count 10 + +** 10 bit edge triggered latch +.subckt latch10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10 ++ dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 dclk + +*data clk set reset out nout +aff1 din1 dclk dzero dzero dout1 dnout1 flop1 +aff2 din2 dclk dzero dzero dout2 dnout2 flop1 +aff3 din3 dclk dzero dzero dout3 dnout3 flop1 +aff4 din4 dclk dzero dzero dout4 dnout4 flop1 +aff5 din5 dclk dzero dzero dout5 dnout5 flop1 +aff6 din6 dclk dzero dzero dout6 dnout6 flop1 +aff7 din7 dclk dzero dzero dout7 dnout7 flop1 +aff8 din8 dclk dzero dzero dout8 dnout8 flop1 +aff9 din9 dclk dzero dzero dout9 dnout9 flop1 +aff10 din10 dclk dzero dzero dout10 dnout10 flop1 + +.model flop1 d_dff(clk_delay = 1e-9 set_delay = 0 ++ reset_delay = 0 ic = 0 rise_delay = 1e-9 ++ fall_delay = 1e-9) + +.ends latch10 + +** emulation of 10 bit DAC +.subckt dac10 din1 din2 din3 din4 din5 din6 din7 din8 din9 din10 aout +.param vref=1 +abridge1 [din1 din2 din3 din4 din5 din6 din7 din8 din9 din10] ++ [ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10] dac1 +BVout aout 0 V = 'vref'*(v(ain10)/2 + v(ain9)/4 + v(ain8)/8 + v(ain7)/16 + v(ain6)/32 + ++ v(ain5)/64 + v(ain4)/128 + v(ain3)/256 + v(ain2)/512 + v(ain1)/1024) + +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-9 ++ t_fall = 1e-9) + +.ends dac10 + diff --git a/Windows/spice/examples/xspice/delta-sigma/counter-test.cir b/Windows/spice/examples/xspice/delta-sigma/counter-test.cir new file mode 100644 index 00000000..8bf2baf6 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/counter-test.cir @@ -0,0 +1,42 @@ +* 10 bit synchronous digital counter +* inhibit at overflow, no revolving +* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005 +* Fig. 2.27, p. 58 + +* clock generation +* PULSE(V1 V2 TD TR TF PW PER) +vclk aclk 0 dc 0 pulse(0 1 1u 2n 2n 1u 2u) + +* reset generation +* single pulse, actual value stored in latch and read by DAC +vres ars 0 dc 0 pulse(0 1 1.1m 2n 2n 1u 2.2m) + +vone aone 0 dc 1 +vzero azero 0 dc 0 + +* digital one +* digital zero +abridge1 [aone azero] [done dzero] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +* digital clock +* digital reset +abridge2 [aclk ars] [dclk dreset] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +XCounter done done dclk dreset dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10 +Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 ++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 dreset ++ latch10 +Xdac dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adacout dac10 + +.include count-latch-dac.cir + +.control +tran 1u 2.5m +eprint dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 > digi4b.txt +eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 >> digi4b.txt +plot adacout +.endc + +.end diff --git a/Windows/spice/examples/xspice/delta-sigma/delta-sigma-1.cir b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-1.cir new file mode 100644 index 00000000..08322260 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-1.cir @@ -0,0 +1,106 @@ +* delta sigma A/D converter 9 bit +* first-order continuous time delta sigma modulator +* sinc filter with counter +* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005 +* Fig. 2.13, p. 31; Fig. 2.27, p.58 + +** sine input signal parameters +.param infreq=500 inampl=0.5 +** clock +.param clkfreq=5Meg +** simulation time +.param simtime = 2m +.csparam simtime = 'simtime' +** sample clock cycles +.param samples=500 + +.global dzero done + +** input signal +* SIN(VO VA FREQ TD THETA) +vin inp inm dc 0 sin(0 'inampl' 'infreq' 0 0) +* steps from -0.5 to 0.4 +*vin inp inm dc 0 pwl(0 -0.5 0.2m -0.5 0.201m -0.4 0.4m -0.4 0.401m -0.3 0.6m -0.3 +*+ 0.601m -0.2 0.8m -0.2 0.801m -0.1 1.0m -0.1 1.001m 0.0 1.2m 0.0 1.201m 0.1 1.4m 0.1 +*+ 1.401m 0.2 1.6m 0.2 1.601m 0.3 1.8m 0.3 1.801m 0.4 2m 0.4) + +** clock and constant logic levels +* PULSE(V1 V2 TD TR TF PW PER) +vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq') + +* digital one +* digital zero +vone aone 0 dc 1 +vzero azero 0 dc 0 +abridge1 [aone azero] [done dzero] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +* digital clock +abridge2 [aclk] [dclk] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +****** delta-sigma converter**************************************************************** +* modulator +* inp inm: analog in + - +* dclk digital clock in +* dv, dvb: modulator non-inverting/inverting out +Xmod inp inm dclk dv dvb mod1 +* sinc filter, decimator +* dlout1 ..dlout10: converter 10 bit digital out +xsinc dv dvb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 sinc1 +******************************************************************************************** + +** DACs for measuring and plotting +* converter output +Xdac_latch dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adaclout dac10 +* counter inside of sinc filter +Xdac_counter xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5 ++ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 adaccout dac10 + +* load modulator mod1 subcircuit +.include mod1-ct.cir + +* load counter, d-latch and 10 bit DAC +.include count-latch-dac.cir + +** sinc filter 1st order subcircuit +.subckt sinc1 din dinb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 +XCounter din dinb dclk ddivndel2 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10 +Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 ++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 ddivndel1 ++ latch10 + +* digital divider dclk/samples +adivn dclk ddivn divider +.model divider d_fdiv(div_factor = 'samples' high_cycles = 1 ++ i_count = 0 rise_delay = 1e-9 fall_delay = 1e-9) + +* clock delays +adelay ddivn ddivndel1 buff1 ; set latch +adelay2 ddivndel1 ddivndel2 buff1 ; reset counter +.model buff1 d_buffer(rise_delay = '1/clkfreq/8' fall_delay = '1/clkfreq/8' ++ input_load = 0.5e-12) + +.ends sinc1 + +** for plotting +abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-9 ++ t_fall = 1e-9) + + +.control +save inp inm adaclout adaccout ; save memory space +tran 0.1u $&simtime +* analog out, scaled 'manually'; sinc filter counter; analog differential in +plot 4.1*(adaclout-0.486) adaccout v(inp)-v(inm) ylimit -0.6 0.6 +* modulator dig out +* eprint dv > digi1.txt +* +*eprint dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 +*+ xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5 +*+ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 > digi4b.txt +.endc + +.end diff --git a/Windows/spice/examples/xspice/delta-sigma/delta-sigma-oc.cir b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-oc.cir new file mode 100644 index 00000000..a0418197 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/delta-sigma-oc.cir @@ -0,0 +1,95 @@ +* delta sigma A/D converter 9 bit +* first-order continuous time delta sigma modulator +* sinc filter with counter +* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005 +* Fig. 2.13, p. 31; Fig. 2.27, p.58 + +** sine input signal parameters +.param infreq=500 inampl=0.5 +** clock +.param clkfreq=5Meg +** simulation time +.param simtime = 2m +.csparam simtime = 'simtime' +** sample clock cycles +.param samples=500 + +.global dzero done + +** input signal +* SIN(VO VA FREQ TD THETA) +vin inp inm dc 0 sin(0 'inampl' 'infreq' 0 0) +* steps from -0.5 to 0.4 +*vin inp inm dc 0 pwl(0 -0.5 0.2m -0.5 0.201m -0.4 0.4m -0.4 0.401m -0.3 0.6m -0.3 +*+ 0.601m -0.2 0.8m -0.2 0.801m -0.1 1.0m -0.1 1.001m 0.0 1.2m 0.0 1.201m 0.1 1.4m 0.1 +*+ 1.401m 0.2 1.6m 0.2 1.601m 0.3 1.8m 0.3 1.801m 0.4 2m 0.4) + +** clock and constant logic levels +* PULSE(V1 V2 TD TR TF PW PER) +vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq') + +* digital one +* digital zero +vone aone 0 dc 1 +vzero azero 0 dc 0 +abridge1 [aone azero] [done dzero] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +* digital clock +abridge2 [aclk] [dclk] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +****** delta-sigma converter**************************************************************** +* modulator +* inp inm: analog in + - +* dclk digital clock in +* dv, dvb: modulator non-inverting/inverting out +Xmod inp inm dclk dv dvb mod1 +* sinc filter, decimator +* dlout1 ..dlout10: converter 10 bit digital out +xsinc dv dvb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 sinc1 +******************************************************************************************** + +** DACs for measuring and plotting +* converter output +Xdac_latch dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 adaclout dac10 +* counter inside of sinc filter +Xdac_counter xsinc.dout1 xsinc.dout2 xsinc.dout3 xsinc.dout4 xsinc.dout5 ++ xsinc.dout6 xsinc.dout7 xsinc.dout8 xsinc.dout9 xsinc.dout10 adaccout dac10 + +* load modulator mod1 subcircuit +.include mod1-ct.cir + +* load counter, d-latch and 10 bit DAC +.include count-latch-dac.cir + +** sinc filter 1st order subcircuit +.subckt sinc1 din dinb dclk dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 +XCounter din dinb dclk ddivndel2 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 count10 +Xlatch dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 ++ dlout1 dlout2 dlout3 dlout4 dlout5 dlout6 dlout7 dlout8 dlout9 dlout10 ddivndel1 ++ latch10 + +* digital divider dclk/samples +adivn dclk ddivn divider +.model divider d_fdiv(div_factor = 'samples' high_cycles = 1 ++ i_count = 0 rise_delay = 1e-9 fall_delay = 1e-9) + +* clock delays +adelay ddivn ddivndel1 buff1 ; set latch +adelay2 ddivndel1 ddivndel2 buff1 ; reset counter +.model buff1 d_buffer(rise_delay = '1/clkfreq/8' fall_delay = '1/clkfreq/8' ++ input_load = 0.5e-12) + +.ends sinc1 + +** for plotting +abridge22 [dclk xsinc.ddivndel1 xsinc.ddivndel2 dv] [acclk acset acres acin] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-9 ++ t_fall = 1e-9) + +.save inp inm adaclout adaccout ; save memory space +.tran 0.1u 2m + +.end diff --git a/Windows/spice/examples/xspice/delta-sigma/mod1-ct-test.cir b/Windows/spice/examples/xspice/delta-sigma/mod1-ct-test.cir new file mode 100644 index 00000000..7ce7b0d3 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/mod1-ct-test.cir @@ -0,0 +1,52 @@ +* first-order delta sigma modulator +* continuous time +* according to Schreier, Temes: Understanding Delta-Sigma Data Converters, 2005 +* Fig. 2.13, p. 31 + +** signal +.param infreq=13k inampl=0.3 +** clock +.param clkfreq=5Meg +** simulation time +.param simtime = 5m +.csparam simtime = 'simtime' + +** input signal +*SIN(VO VA FREQ TD THETA) +vin in+ in- dc 0 sin(0 'inampl' 'infreq' 0 0) + +* clock generation +* PULSE(V1 V2 TD TR TF PW PER) +vclk aclk 0 dc 0 pulse(0 1 0.1u 2n 2n '1/clkfreq/2' '1/clkfreq') + +* digital one +* digital zero +vone aone 0 dc 1 +vzero azero 0 dc 0 +abridge1 [aone azero] [done dzero] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +* digital clock +abridge2 [aclk] [dclk] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) + +Xmod in+ in- dclk dv dvb mod1 + +* load mod1 subcircuit +.include mod1-ct.cir + +.control +save xmod.adffq in+ in- xmod.outintp xmod.outintn +tran 0.01u $&simtime +* digit density vs input +plot xmod.adffq "v(in+) - v(in-)" xlimit 0.1m 0.2m +* modulator integrator out, digital out +plot xmod.outintp-xmod.outintn xmod.adffq xlimit 0.140m 0.148m +*eprint dv dclk > digi1.txt +linearize xmod.adffq +fft xmod.adffq +* noise shaping 20dB/decade +plot db(xmod.adffq) xlimit 10k 1Meg xlog ylimit -20 -120 +.endc + +.end diff --git a/Windows/spice/examples/xspice/delta-sigma/mod1-ct.cir b/Windows/spice/examples/xspice/delta-sigma/mod1-ct.cir new file mode 100644 index 00000000..bf3129b7 --- /dev/null +++ b/Windows/spice/examples/xspice/delta-sigma/mod1-ct.cir @@ -0,0 +1,46 @@ +* delta sigma modulator +* first order, continuous time + +.subckt mod1 ainp ainn dclk ddffq ddffqb +* integrator and summer +Ri1 ainn inintn 500 +Rf1 adffq inintn 500 +Cint1 outintp inintn 1n +.IC v(outintp) = 0 v(inintp) = 0 +* +Rshunt1 outintp 0 100Meg +Rshunt2 initn 0 100Meg +* +Ri2 ainp inintp 500 +Rf2 adffqb inintp 500 +Cint2 outintn inintp 1n +.IC v(outintn) = 0 v(inintn) = 0 +* +Rshunt3 outintn 0 100Meg +Rshunt4 inintp 0 100Meg +* +aint %vd(inintp inintn) %vd(outintp outintn) amp +.model amp gain ( in_offset =0.0 gain =100000 ++ out_offset = 0) + +* latched comparator (code model or B source, analog in, digital out) +*acomp %vd(outintp outintn) acompout limit5 +*.model limit5 limit(in_offset=0 gain=100000 out_lower_limit=-1.0 +*+ out_upper_limit=1.0 limit_range=0.10 fraction=FALSE) +* +BComp acompout 0 V = (V(outintp) - V(outintn)) >= 0 ? 1 : -1 +* +abridge2 [acompout] [dcompout] adc_buff +.model adc_buff adc_bridge(in_low = 0 in_high = 0) +* +* D flip flop: data clk set reset out nout +adff1 dcompout dclk ds drs ddffq ddffqb flop2 +.model flop2 d_dff(clk_delay = 1e-9 set_delay = 1.0e-9 ++ reset_delay = 1.0e-9 ic = 0 rise_delay = 1.0e-9 ++ fall_delay = 1e-9) + +abridge1 [ddffq ddffqb dclk] [adffq adffqb aclk] dac1 +.model dac1 dac_bridge(out_low = -1 out_high = 1 out_undef = 0 ++ input_load = 5.0e-12 + +.ends mod1 diff --git a/Windows/spice/examples/xspice/fstest.sp b/Windows/spice/examples/xspice/fstest.sp new file mode 100644 index 00000000..f0f552a8 --- /dev/null +++ b/Windows/spice/examples/xspice/fstest.sp @@ -0,0 +1,26 @@ +* filesource Test + +* two differential ports 1 0 and 3 0 are used, so your input file +* has to have three columns (time, port_value 1, portvalue 2) + +AFILESRC %vd([1 0 3 0]) filesrc +.model filesrc filesource (file="sine.m" amploffset=[0 0] amplscale=[1 1] timerelative=false amplstep=false) + +V2 2 0 0.0 SIN(0 1 1MEG 0 0 0.0) +V4 4 0 0.0 SIN(0 1 1MEG 0 0 90.0) + +.tran 1n 1.0u + +.control +run +*listing param +wrdata vspice V(1) V(2) V(3) V(4) + + +plot V(1) V(2) V(3) V(4) + +* error between interpolation and sine source +* should be less than 1mV up to 1us +plot V(1,2) V(3,4) +.endc +.end diff --git a/Windows/spice/examples/xspice/pll/README b/Windows/spice/examples/xspice/pll/README new file mode 100644 index 00000000..f5c38b39 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/README @@ -0,0 +1,39 @@ +This directory contains a mixed mode pll, combining +ngspice and XSPICE circuit blocks. +The pll consists of the following blocks: + +** voltage controlled oscillator: +vco_sub.cir + 7 stage ring oscillator with gain cells, CMOS devices +or +vco_sub_new.cir + vco made from code model d_osc, cntl_array/freq_array data + are gained by running test-vco.cir with vco_sub.cir + +** digital divider and frequency reference: +pll-xspice.cir + +** phase frequency detector: +f-p-det-d-sub.cir + +** loop filter: +loop-filter.cir + switched current sources as charge pump, 2nd order + passive RC filter +or +loop-filter-2.cir + transistors as switches for charge pump, 2nd or 3rd + order passive RC filters + +** main simulation control: +pll-xspice.cir + +Two test files are included: +test-vco.cir simulates vco frequency versus control voltage +test-f-p-det.cir simulates the phase frequency detector and the loop filter. + +The main building blocks are organised as subcircuits. + +main simulation control with three reference frequencies: +pll-xspice-fstep.cir + simulates two steps of the reference in one simulation run diff --git a/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir b/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir new file mode 100644 index 00000000..cdd5af9e --- /dev/null +++ b/Windows/spice/examples/xspice/pll/f-p-det-d-sub.cir @@ -0,0 +1,16 @@ +* frequency-phase detector according to +* http://www.uwe-kerwien.de/pll/pll-phasenvergleich.htm + +.subckt f-p-det d_R d_V d_U d_U_ d_D d_D_ + +aa1 [d_U d_D] d_rset and1 +.model and1 d_and(rise_delay = 1e-10 fall_delay = 0.1e-9 ++ input_load = 0.5e-12) + +ad1 d_d1 d_R d_d0 d_rset d_U d_U_ flop1 +ad2 d_d1 d_V d_d0 d_rset d_D d_D_ flop1 +.model flop1 d_dff(clk_delay = 1.0e-10 set_delay = 1.0e-10 ++ reset_delay = 1.0e-10 ic = 2 rise_delay = 1.0e-10 ++ fall_delay = 1e-10) + +.ends f-p-det diff --git a/Windows/spice/examples/xspice/pll/loop-filter-2.cir b/Windows/spice/examples/xspice/pll/loop-filter-2.cir new file mode 100644 index 00000000..3d093167 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/loop-filter-2.cir @@ -0,0 +1,50 @@ +* loop filter for pll +* in: d_up d_down digital data +* out: vout, vco control voltage +* using transistors to switch current +* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm +* digital input d_Un d_D +* anlog output vout + + +.subckt loopf d_Un d_D vout + +.param initcond=2.5 + +vdd dd 0 dc 'vcc' +vss ss 0 dc 0 + +* "driver" circuit, digital in, analog out +abridge-f1 [d_Un d_D] [u1n d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 'vcc' out_undef = 'vcc/2' ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +* uses BSIM3 model parameters from pll-xspice_2.cir +* transistors as switches +mnd dra d1 ss ss n1 w=12u l=0.35u AS=24p AD=24p PS=28u PD=28u +mpd dra u1n dd dd p1 w=24u l=0.35u AS=48p AD=48p PS=52u PD=52u + +*** passive filter elements *** +*third order filter +*parameters absolutely _not_ optimised +*better check +* http://www.national.com/assets/en/boards/deansbook4.pdf +*to do so +.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(int1)='initcond' v(u1n)='vcc' v(d1)=0 +R1 dra int1 300 +R2 int1 c1 200 +C1 c1 0 10n +C2 int1 0 5n +R3 int1 vout 50 +C3 vout 0 0.5n + +*second order filter +*parameters not optimized +*.ic v(vout)='initcond' v(c1)='initcond' v(dra)='initcond' v(u1n)='vcc' v(d1)=0 +*R1 dra vout 300 +*R2 vout c1 200 +*C1 c1 0 10n +*C2 vout 0 5n + +.ends loopf diff --git a/Windows/spice/examples/xspice/pll/loop-filter.cir b/Windows/spice/examples/xspice/pll/loop-filter.cir new file mode 100644 index 00000000..a83ebb7a --- /dev/null +++ b/Windows/spice/examples/xspice/pll/loop-filter.cir @@ -0,0 +1,31 @@ +* loop filter for pll +* in: d_up d_down digital data +* out: vout, vco control voltage +* according to http://www.uwe-kerwien.de/pll/pll-schleifenfilter.htm + +.subckt loopfe d_U d_D vout + +.param loadcur=5m +.param initcond=2.5 + +v1 vtop 0 1 +v2 vbot 0 -1 + +abridge-f1 [d_U d_D] [u1 d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +*top switched current source +Gtop vtop vout cur='loadcur*v(u1)' +*bottom switched current source +Gbot vout vbot cur='loadcur*v(d1)' + +*passive filter elements +.ic v(vout)='initcond' v(c1)='initcond' +R2 vout c1 200 +C1 c1 0 5n +C2 vout 0 5n +Rshunt vout 0 10000k + +.ends diff --git a/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir b/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir new file mode 100644 index 00000000..5c79e152 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/pll-xspice-fstep.cir @@ -0,0 +1,165 @@ +* pll circuit using xspice code models +* three frequencies generate steps in control voltage v(cont) + +.param vcc=3.3 +.param divisor=40 +.param fref=10e6 +.param fref2=9e6 +.param fref3=11e6 +.csparam simtime=45u +.csparam f2='fref2' +.csparam f3='fref3' + +* digital zero and one +.global d_d0 d_d1 + +vdd dd 0 dc 'vcc' + +* 10 MHz reference frequency +* PULSE(V1 V2 TD TR TF PW PER) +vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') +abridgeref [ref] [d_ref] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5) + +*digital zero +vzero z 0 dc 0 +abridgev3 [z] [d_d0] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +*digital one +ainv1 d_d0 d_d1 invd1 +.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) + +* vco +* buf: analog out +* d_digout: digital out +* cont: analog control voltage +* dd: analog supply voltage +*.include vco_sub.cir +*xvco buf d_digout cont dd ro_vco +.include vco_sub_new.cir +xvco buf d_digout cont dd d_osc_vco + +* digital divider +adiv1 d_digout d_divout divider +.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2' ++ i_count = 4 rise_delay = 1e-10 ++ fall_delay = 1e-10) + +* frequency phase detector +.include f-p-det-d-sub.cir +Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det + +* loop filter +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe + +* d to a for plotting +abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1 d1] dac1 ; change to d_u or d_Un +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +.control +save cont s1 s2 u1 d1 +iplot cont +* calculate breakpoint for switching frequency +let t1_3 = simtime/3 +set ti1_3 ="$&t1_3" +let t2_3 = simtime/3*2 +set ti2_3 ="$&t2_3" +stop when time=$ti1_3 +stop when time=$ti2_3 +* calculate new periods for f2 +let per2=1/f2 +let pw2 = per2/2 +let per3=1/f3 +let pw3 = per3/2 +*simulate +tran 0.1n $&simtime uic +*change frequency after stopping +* first pair of [] without spaces, second pair with spaces +alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw2 $&per2 ] +resume +*another change after second stop +alter @vref[pulse] = [ 0 3.3 10n 1n 1n $&pw3 $&per3 ] +resume +rusage +plot cont s1 s2+1.2 u1+2.4 d1+3.6 xlimit 15u 16u +*plot cont +.endc + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + + +.end diff --git a/Windows/spice/examples/xspice/pll/pll-xspice.cir b/Windows/spice/examples/xspice/pll/pll-xspice.cir new file mode 100644 index 00000000..1d14368d --- /dev/null +++ b/Windows/spice/examples/xspice/pll/pll-xspice.cir @@ -0,0 +1,144 @@ +* pll circuit using xspice code models +* output frequency 400 MHz +* locked to a 1 or 10 MHz reference + +.param vcc=3.3 +.param divisor=40 +.param fref=10e6 +.csparam simtime=25u + +.global d_d0 d_d1 + +vdd dd 0 dc 'vcc' +*vco cont 0 dc 1.9 + +*PULSE(V1 V2 TD TR TF PW PER) +* reference frequency selected by param fref +* PULSE(V1 V2 TD TR TF PW PER) +vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') +abridgeref [ref] [d_ref] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5) + +*digital zero +vzero z 0 dc 0 +abridgev3 [z] [d_d0] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +*digital one +ainv1 d_d0 d_d1 invd1 +.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) + +* vco +* buf: analog out +* d_digout: digital out +* cont: analog control voltage +* dd: analog supply voltage +*.include vco_sub.cir +*xvco buf d_digout cont dd ro_vco +.include vco_sub_new.cir +xvco buf d_digout cont dd d_osc_vco + +* digital divider +adiv1 d_digout d_divout divider +.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2' ++ i_count = 4 rise_delay = 1e-10 ++ fall_delay = 1e-10) + +* frequency phase detector +.include f-p-det-d-sub.cir +Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det + +* loop filters +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe + +* d to a for plotting +abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +.control +save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory +iplot cont +tran 0.1n $&simtime uic +rusage +plot cont s1 s2+1.2 u1n+2.4 d1+3.6 xlimit 4u 5u +plot v.xlf.vdd#branch xlimit 4u 5u ylimit -8m 2m +*plot cont +.endc + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + + +.end diff --git a/Windows/spice/examples/xspice/pll/pll-xspice_oc.cir b/Windows/spice/examples/xspice/pll/pll-xspice_oc.cir new file mode 100644 index 00000000..f2d235c3 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/pll-xspice_oc.cir @@ -0,0 +1,142 @@ +* pll circuit using xspice code models +* output frequency 400 MHz +* locked to a 1 or 10 MHz reference + +.param vcc=3.3 +.param divisor=40 +.param fref=10e6 +.csparam simtime=25u + +.control +pre_unset ngdebug +set noinit +.endc + +.global d_d0 d_d1 + +vdd dd 0 dc 'vcc' +*vco cont 0 dc 1.9 + +*PULSE(V1 V2 TD TR TF PW PER) +* reference frequency selected by param fref +* PULSE(V1 V2 TD TR TF PW PER) +vref ref 0 dc 0 pulse(0 'vcc' 10n 1n 1n '1/fref/2' '1/fref') +abridgeref [ref] [d_ref] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 0.5 in_high = 0.5) + +*digital zero +vzero z 0 dc 0 +abridgev3 [z] [d_d0] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +*digital one +ainv1 d_d0 d_d1 invd1 +.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) + +* vco +* buf: analog out +* d_digout: digital out +* cont: analog control voltage +* dd: analog supply voltage +*.include vco_sub.cir +*xvco buf d_digout cont dd ro_vco +.include vco_sub_new.cir +xvco buf d_digout cont dd d_osc_vco + +* digital divider +adiv1 d_digout d_divout divider +.model divider d_fdiv(div_factor = 'divisor' high_cycles = 'divisor/2' ++ i_count = 4 rise_delay = 1e-10 ++ fall_delay = 1e-10) + +* frequency phase detector +.include f-p-det-d-sub.cir +Xfpdet d_divout d_ref d_U d_Un d_D d_Dn f-p-det + +* loop filters +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe + +* d to a for plotting +abridge-w1 [d_divout d_ref d_Un d_D] [s1 s2 u1n d1] dac1 ; change to d_u or d_Un +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +.save cont s1 s2 u1n d1 v.xlf.vdd#branch; to save memory +.tran 0.1n 10u uic + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + + +.end diff --git a/Windows/spice/examples/xspice/pll/test-f-p-det.cir b/Windows/spice/examples/xspice/pll/test-f-p-det.cir new file mode 100644 index 00000000..16060b9b --- /dev/null +++ b/Windows/spice/examples/xspice/pll/test-f-p-det.cir @@ -0,0 +1,114 @@ +* test frequency-phase detector similar to 12040 + +.param vcc=3.3 +.global d_d0 d_d1 + +*PULSE(V1 V2 TD TR TF PW PER) +v1 1 0 dc 0 pulse(0 'vcc' 10n 1n 1n 10n 20n) +v2 2 0 dc 0 pulse(0 'vcc' 8n 1n 1n 10n 20n) + +*digital zero +v3 3 0 dc 0 +abridgev1 [1 2 3] [d_sig1 d_sig2 d_d0] adc_vbuf +.model adc_vbuf adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +*digital one +ainv1 d_d0 d_d1 invd1 +.model invd1 d_inverter(rise_delay = 1e-10 fall_delay = 1e-10) + +Xfpdet d_sig1 d_sig2 d_U d_Un d_D d_Dn f-p-det + +*.include f-p-det-sub.cir +.include f-p-det-d-sub.cir + +* d to a for plotting +abridge-w1 [d_sig1 d_sig2 d_U d_D] [s1 s2 u1 d1] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +* loop filters +*2nd or 3rd order, transistors as switches +.include loop-filter-2.cir +Xlf d_Un d_D cont loopf +* 2nd order, Exxxx voltage controlled current sources as 'switches' +* loop filter current sources as charge pump +*.include loop-filter.cir +*Xlf d_U d_D cont loopfe + +.control +set xtrtol=2 +tran 0.1n 1000n +plot s1 s2+1.2 u1+2.4 d1+3.6 xlimit 140n 200n +.endc + + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + + +.end diff --git a/Windows/spice/examples/xspice/pll/test_vco.cir b/Windows/spice/examples/xspice/pll/test_vco.cir new file mode 100644 index 00000000..522eac00 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/test_vco.cir @@ -0,0 +1,158 @@ +* Test of VCO: frequency versus control voltage +* 7 stage Ring-Osc. made of gain cells BSIM3 +* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495 +* alternatively use d_osc code model +* measure frequency of R.O. by fft + +.param vcc=3.3 +.csparam simtime=500n + +vdd dd 0 dc 'vcc' +vco cont 0 dc 2.5 + +* vco +* buf: analog out +* d_digout: digital out +* cont: analog control voltage +* dd: analog supply voltage +*.include vco_sub.cir +*xvco buf d_digout cont dd ro_vco +.include vco_sub_new.cir +xvco buf d_digout cont dd d_osc_vco + +.option noacct + +.control +set xtrtol=2 +set dt = $curplot +set curplot = new +set curplottitle = "Frequency versus voltage" +set freq_volt = $curplot $ store its name to 'freq_volt' +setplot $freq_volt +let vcovec=vector(5) +let foscvec=vector(5) +setplot $dt +alter vco 0.5 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[0]=v(cont) +linearize buf +fft buf +* start meas at freq > 0 to skip large dc part +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[0]=fosc +plot d_digout xlimit 140n 160n +reset +alter vco 1 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[1]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[1]=fosc +plot d_digout xlimit 140n 160n +reset +alter vco 1.5 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[2]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[2]=fosc +plot d_digout xlimit 140n 160n +reset +alter vco 2 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[3]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[3]=fosc +plot d_digout xlimit 140n 160n +reset +alter vco 2.5 +tran 0.1n $&simtime 0 +let {$freq_volt}.vcovec[4]=v(cont) +linearize buf +fft buf +meas sp fosc MAX_AT buf from=1e3 to=1e9 +let {$freq_volt}.foscvec[4]=fosc +plot d_digout xlimit 140n 160n +plot tran1.buf tran3.buf tran5.buf tran7.buf tran9.buf xlimit 140n 160n +plot mag(sp2.buf) mag(sp4.buf) mag(sp6.buf) mag(sp8.buf) mag(sp10.buf) xlimit 100e6 1100e6 +setplot $freq_volt +settype frequency foscvec +settype voltage vcovec +plot foscvec vs vcovec +print vcovec foscvec +rusage +.endc + +*model = bsim3v3 +*Berkeley Spice Compatibility +* Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 +.model N1 NMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++ Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++ Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++ Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++ Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++ Lw = 0 Lwl = 0 Lln = .316394 ++ Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 + +.model P1 PMOS +*+version = 3.2.4 ++version = 3.3.0 ++Level= 8 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++ Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++ Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 + +.end diff --git a/Windows/spice/examples/xspice/pll/vco_sub.cir b/Windows/spice/examples/xspice/pll/vco_sub.cir new file mode 100644 index 00000000..77f87360 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/vco_sub.cir @@ -0,0 +1,67 @@ +* VCO: 7 stage Ring-Osc. made of gain cells BSIM3 +* P.-H. Hsieh, J. Maxey, C.-K. K. Yang, IEEE JSSC, Sept. 2009, pp. 2488 - 2495 +* 150 MHz to 900 MHz with control voltage 2.5 to 0.5 V at 3.3 V supply +* BSIM 3 model data for transistors in main file pll-xspice.cir + +***** ring oscillator as voltage controlled oscillator *************** +* name: ro_vco +* aout analog out +* dout digital out +* cont control voltage +* dd supply voltage + +.subckt ro_vco aout dout cont dd +* ignition circuit (not needed) +* feedback between in and out, pulse to help start oscillation +vin inm1 outp7 dc 0 +*vin inm1 outp7 dc 2.5 pulse 2.5 0 0.1n 5n 1 1 1 + +*vin2 inp1 outp7 dc -0.5 pulse -0.5 0 0.1n 5n 1 1 1 +vin2 inp1 outm7 dc 0 + + +vss ss 0 dc 0 +ve sub 0 dc 0 +vpe well 0 dc 3.3 + + +* gain cell +.subckt gaincell dd ss sub well co in- in+ out- out+ +mn1 out- in+ ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mn2 out- out+ ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mn3 out+ out- ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mn4 out+ in- ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mp1 out- co dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u +mp2 out+ co dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u +.ends gaincell + +* inverter +.subckt inv2 dd ss sub well in out +mn1 out in ss sub n1 w=6u l=0.35u AS=12p AD=12p PS=16u PD=16u +mp1 out in dd well p1 w=12u l=0.35u AS=24p AD=24p PS=28u PD=28u +.ends inv2 + +* inverter +.subckt inv1 dd ss sub well in out +mn1 out in ss sub n1 w=2u l=0.35u AS=3p AD=3p PS=4u PD=4u +mp1 out in dd well p1 w=4u l=0.35u AS=7p AD=7p PS=6u PD=6u +.ends inv1 + +* chain of 25 inverters + output buffer +xinv1 dd ss sub well cont inm1 inp1 outm1 outp1 gaincell +xinv2 dd ss sub well cont outp1 outm1 outm2 outp2 gaincell +xinv3 dd ss sub well cont outp2 outm2 outm3 outp3 gaincell +xinv4 dd ss sub well cont outp3 outm3 outm4 outp4 gaincell +xinv5 dd ss sub well cont outp4 outm4 outm5 outp5 gaincell +xinv6 dd ss sub well cont outp5 outm5 outm6 outp6 gaincell +xinv7 dd ss sub well cont outp6 outm6 outm7 outp7 gaincell +* analog out (two stage buffer) +xinv11 dd 0 sub well outm1 outm2 inv1 +xinv12 dd 0 sub well outm2 aout inv2 +cout aout 0 0.2pF +*digital out +abridge1 [aout] [dout] adc_buff +.model adc_buff adc_bridge(in_low = 'vcc*0.5' in_high = 'vcc*0.5') +.ends ro_vco +****************************************************************** + diff --git a/Windows/spice/examples/xspice/pll/vco_sub_new.cir b/Windows/spice/examples/xspice/pll/vco_sub_new.cir new file mode 100644 index 00000000..229ccf84 --- /dev/null +++ b/Windows/spice/examples/xspice/pll/vco_sub_new.cir @@ -0,0 +1,30 @@ +***** XSPICE digital controlled oscillator d_osc as vco *************** +* 150 MHz to 900 MHz +* name: d_osc_vco +* aout analog out +* dout digital out +* cont control voltage +* dd supply voltage + +.subckt d_osc_vco aout dout cont dd +* curve fitting to ro_vco 'measured' data +Bfit fitted 0 v = (-58256685.71*v(cont)*v(cont) - 186386142.9*v(cont) + 988722980)/10. + +*a5 fitted dout var_clock +*.model var_clock d_osc(cntl_array = [1.0e7 5.0e7 9.0e7] +*+ freq_array = [1.0e8 5.0e8 9.0e8] + +* linear interpolation, input data from measured ro vco +a5 cont dout var_clock +.model var_clock d_osc(cntl_array = [0.5 1 1.5 2 2.5] ++ freq_array = [8.790820e+008 7.472197e+008 5.799500e+008 3.772727e+008 1.611650e+008] ++ duty_cycle = 0.5 init_phase = 180.0 ++ rise_delay = 1e-10 fall_delay=1e-10) + +*generate an analog output for plotting +abridge-fit [dout] [aout] dac1 +.model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 ++ input_load = 5.0e-12 t_rise = 1e-10 ++ t_fall = 1e-10) + +.ends d_osc_vco diff --git a/Windows/spice/examples/xspice/sine.m b/Windows/spice/examples/xspice/sine.m new file mode 100644 index 00000000..c01fbe9a --- /dev/null +++ b/Windows/spice/examples/xspice/sine.m @@ -0,0 +1,264 @@ +# Created by Octave 3.4.0, Mon Jun 06 10:16:19 2011 CEST <sailer@xbox360.hq.axsem.com> +# name: x +# type: matrix +# rows: 257 +# columns: 3 + 0 0 1 + 3.90625e-09 0.02454122852291229 0.9996988186962042 + 7.8125e-09 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9.882812499999999e-07 -0.07356456359966741 0.9972904566786902 + 9.921875e-07 -0.04906767432741809 0.9987954562051724 + 9.960937499999999e-07 -0.02454122852291245 0.9996988186962042 + 1e-06 -2.449293598294706e-16 1 + + diff --git a/Windows/spice/examples/xspice/xspice_c1.cir b/Windows/spice/examples/xspice/xspice_c1.cir new file mode 100644 index 00000000..022d9138 --- /dev/null +++ b/Windows/spice/examples/xspice/xspice_c1.cir @@ -0,0 +1,22 @@ +A Berkeley SPICE3 compatible circuit +* +* This circuit contains only Berkeley SPICE3 components. +* +* The circuit is an AC coupled transistor amplifier with +* a sinewave input at node "1", a gain of approximately -3.9, +* and output on node "coll". +* +.tran 1e-5 2e-3 +* +vcc vcc 0 12.0 +vin 1 0 0.0 ac 1.0 sin(0 1 1k) +ccouple 1 base 10uF +rbias1 vcc base 100k +rbias2 base 0 24k +q1 coll base emit generic +rcollector vcc coll 3.9k +remitter emit 0 1k +* +.model generic npn +* +.end diff --git a/Windows/spice/examples/xspice/xspice_c2.cir b/Windows/spice/examples/xspice/xspice_c2.cir new file mode 100644 index 00000000..5c66bdd1 --- /dev/null +++ b/Windows/spice/examples/xspice/xspice_c2.cir @@ -0,0 +1,16 @@ +A transistor amplifier circuit +* +.tran 1e-5 2e-3 +* +vin 1 0 0.0 ac 1.0 sin(0 1 1k) +* +ccouple 1 in 10uF +rzin in 0 19.35k +* +aamp in aout gain_block +.model gain_block gain (gain = -3.9 out_offset = 7.003) +* +rzout aout coll 3.9k +rbig coll 0 1e12 +* +.end diff --git a/Windows/spice/examples/xspice/xspice_c3.cir b/Windows/spice/examples/xspice/xspice_c3.cir new file mode 100644 index 00000000..4c536293 --- /dev/null +++ b/Windows/spice/examples/xspice/xspice_c3.cir @@ -0,0 +1,97 @@ +Mixed IO types +* This circuit contains a mixture of IO types, including +* analog, digital, user-defined (real), and 'null'. +* +* The circuit demonstrates the use of the digital and +* user-defined node capability to model system-level designs +* such as sampled-data filters. The simulated circuit +* contains a digital oscillator enabled after 100us. The +* square wave oscillator output is divided by 8 with a +* ripple counter. The result is passed through a digital +* filter to convert it to a sine wave. +* +.tran 1e-5 1e-3 +.save all +* +v1 1 0 0.0 pulse(0 1 1e-4 1e-6) +r1 1 0 1k +* +abridge1 [1] [enable] atod +.model atod adc_bridge +* +aclk [enable clk] clk nand +.model nand d_nand (rise_delay=1e-5 fall_delay=1e-5) +* +adiv2 div2_out clk NULL NULL NULL div2_out dff +adiv4 div4_out div2_out NULL NULL NULL div4_out dff +adiv8 div8_out div4_out NULL NULL NULL div8_out dff +.model dff d_dff +* +abridge2 div8_out enable filt_in node_bridge2 +.model node_bridge2 d_to_real (zero=-1 one=1) +* +xfilter filt_in clk filt_out dig_filter +* +abridge3 filt_out a_out node_bridge3 +.model node_bridge3 real_to_v +* +rlpf1 a_out oa_minus 10k +* +xlpf 0 oa_minus lpf_out opamp +* +rlpf2 oa_minus lpf_out 10k +clpf lpf_out oa_minus 0.01uF +* +* +.subckt dig_filter filt_in clk filt_out +* +.model n0 real_gain (gain=1.0) +.model n1 real_gain (gain=2.0) +.model n2 real_gain (gain=1.0) +.model g1 real_gain (gain=0.125) +.model zm1 real_delay +.model d0a real_gain (gain=-0.75) +.model d1a real_gain (gain=0.5625) +.model d0b real_gain (gain=-0.3438) +.model d1b real_gain (gain=1.0) +* +an0a filt_in x0a n0 +an1a filt_in x1a n1 +an2a filt_in x2a n2 +* +az0a x0a clk x1a zm1 +az1a x1a clk x2a zm1 +* +ad0a x2a x0a d0a +ad1a x2a x1a d1a +* +az2a x2a filt1_out g1 +az3a filt1_out clk filt2_in zm1 +* +an0b filt2_in x0b n0 +an1b filt2_in x1b n1 +an2b filt2_in x2b n2 +* +az0b x0b clk x1b zm1 +az1b x1b clk x2b zm1 +* +ad0 x2b x0b d0b +ad1 x2b x1b d1b +* +az2b x2b clk filt_out zm1 +* +.ends dig_filter +* +* +.subckt opamp plus minus out +* +r1 plus minus 300k +a1 %vd (plus minus) outint lim +.model lim limit (out_lower_limit = -12 out_upper_limit = 12 ++ fraction = true limit_range = 0.2 gain=300e3) +r3 outint out 50.0 +r2 out 0 1e12 +* +.ends opamp +* +.end |