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-rw-r--r--Windows/spice/examples/vdmos/IXTH80N20L-IXTH48P20P-quasisat.cir67
-rw-r--r--Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir18
-rw-r--r--Windows/spice/examples/vdmos/IXTP6N100D2-n-weak-inv.cir28
-rw-r--r--Windows/spice/examples/vdmos/VDMOS-DIO-AC.cir25
-rw-r--r--Windows/spice/examples/vdmos/VDMOS-DIO.cir27
-rw-r--r--Windows/spice/examples/vdmos/inv_vdmos.cir24
-rw-r--r--Windows/spice/examples/vdmos/inv_vdmos_dc.cir25
-rw-r--r--Windows/spice/examples/vdmos/mtriode_nch.sp13
-rw-r--r--Windows/spice/examples/vdmos/ro_11_vdmos.cir34
-rw-r--r--Windows/spice/examples/vdmos/theta_nch.sp13
-rw-r--r--Windows/spice/examples/vdmos/vdmos-out.cir18
-rw-r--r--Windows/spice/examples/vdmos/vdmos-out_ir.cir18
-rw-r--r--Windows/spice/examples/vdmos/vdmos-out_ir_mtr.cir26
-rw-r--r--Windows/spice/examples/vdmos/vdmosp-out-mtr.cir26
-rw-r--r--Windows/spice/examples/vdmos/vdmosp-out.cir17
15 files changed, 0 insertions, 379 deletions
diff --git a/Windows/spice/examples/vdmos/IXTH80N20L-IXTH48P20P-quasisat.cir b/Windows/spice/examples/vdmos/IXTH80N20L-IXTH48P20P-quasisat.cir
deleted file mode 100644
index 3f529ea8..00000000
--- a/Windows/spice/examples/vdmos/IXTH80N20L-IXTH48P20P-quasisat.cir
+++ /dev/null
@@ -1,67 +0,0 @@
-VDMOS Test of quasi saturation IXTH80N20L IXTH48P20P
-* Original VDMOS model parameters taken from David Zan,
-* http://www.diyaudio.com/forums/software-tools/266655-power-mosfet-models-ltspice-post5300643.html
-* The Quasi-saturation is added for demonstration only, it is not aligned with the data sheets
-* and is for sure exaggerated, at least for the IXTH80N20L
-
-mn1 d1 g1 s1 IXTH80N20L
-
-vd1 d1 0 1
-vg1 g1 0 1
-vs1 s1 0 0
-
-mp2 d2 g2 s2 IXTH48P20P
-
-vd2 d2 0 1
-vg2 g2 0 1
-vs2 s2 0 0
-
-.control
-dc vd1 -1 100 0.05 vg1 3 10 1
-altermod mn1 rq=0
-altermod mn1 Lambda=2m
-dc vd1 -1 100 0.05 vg1 3 10 1
-plot dc1.vs1#branch vs1#branch
-
-dc vd2 1 -100 -0.05 vg2 -3 -10 -1
-altermod mp2 rq=0
-altermod mp2 Lambda=5m
-dc vd2 1 -100 -0.05 vg2 -3 -10 -1
-plot dc3.vs2#branch vs2#branch
-
-.endc
-
-* David Zan, (c) 2017/03/02 Preliminary
-.MODEL IXTH80N20L VDMOS Nchan Vds=200
-+ VTO=4 KP=15
-+ Lambda=3m $ will be reset by altermod to original 2m
-+ Mtriode=0.4
-+ subslope=120m
-+ subshift=160m
-+ Rs=5m Rd=10m Rds=200e6
-+ Cgdmax=9000p Cgdmin=300p A=0.25
-+ Cgs=5500p Cjo=11000p
-+ Is=10e-6 Rb=8m
-+ BV=200 IBV=250e-6
-+ NBV=4
-+ TT=250e-9
-+ vq=100
-+ rq=0.5 $ will be reset by altermod to original 0
-
-* David Zan, (c) 2017/03/02 Preliminary
-.MODEL IXTH48P20P VDMOS Pchan Vds=200
-+ VTO=-4 KP=10
-+ Lambda=7m $ will be reset by altermod to original 5m
-+ Mtriode=0.3
-+ Ksubthres=120m
-+ Rs=10m Rd=20m Rds=200e6
-+ Cgdmax=6000p Cgdmin=100p A=0.25
-+ Cgs=5000p Cjo=9000p
-+ Is=2e-6 Rb=20m
-+ BV=200 IBV=250e-6
-+ NBV=4
-+ TT=260e-9
-+ vq=100
-+ rq=0.5 $ will be reset by altermod to original 0
-
-.end \ No newline at end of file
diff --git a/Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir b/Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir
deleted file mode 100644
index de49a542..00000000
--- a/Windows/spice/examples/vdmos/IXTP6N100D2-cap.cir
+++ /dev/null
@@ -1,18 +0,0 @@
-Test of VDMOS gate-source and gate-drain capacitance
-
-m1 d g s IXTP6N100D2
-
-.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1)
-
-vd d 0 dc 5
-vg g 0 pwl (0 -3 1 3)
-vs s 0 0
-
-.control
-save all @m1[cgd] @m1[cgs]
-tran 1m 1
-plot vs#branch
-plot @m1[cgd] @m1[cgs]
-.endc
-
-.end \ No newline at end of file
diff --git a/Windows/spice/examples/vdmos/IXTP6N100D2-n-weak-inv.cir b/Windows/spice/examples/vdmos/IXTP6N100D2-n-weak-inv.cir
deleted file mode 100644
index 5f2e6f8f..00000000
--- a/Windows/spice/examples/vdmos/IXTP6N100D2-n-weak-inv.cir
+++ /dev/null
@@ -1,28 +0,0 @@
-VDMOS output
-
-m1 d g s IXTP6N100D2
-m2 d g s2 IXTP6N100D2_2
-
-* LTSPICE model parameters
-*.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 *Vj=0.1 Cjo=3200pF ksubthres=0.1)
-
-* equivalent ngspice model parameters
-.MODEL IXTP6N100D2_2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=39m)
-
-* equivalent ngspice model parameters, trying to make output similar to data sheet Fig. 2
-.MODEL IXTP6N100D2 VDMOS(KP=6 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.007 CGDMAX=3000p CGDMIN=2p CGS=2915p TT=1371n a=1 IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=39m rq=4 vq=200 mtriode=0.1)
-
-vd d 0 -0.6
-vg g 0 -2.3
-vs s 0 0
-vs2 s2 0 0
-
-.control
-dc vg -3.1 -2.1 0.01 vd 0.2 1 0.2
-plot vs#branch
-plot vs#branch ylog
-dc vd 0 60 0.1 vg -3 5 1
-plot vs#branch vs2#branch xlimit 0 60 ylimit 0 14
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/VDMOS-DIO-AC.cir b/Windows/spice/examples/vdmos/VDMOS-DIO-AC.cir
deleted file mode 100644
index 682d1c12..00000000
--- a/Windows/spice/examples/vdmos/VDMOS-DIO-AC.cir
+++ /dev/null
@@ -1,25 +0,0 @@
-Capacitance and current comparison between models d and bulk diode in vdmos
-
-D1 ad kd dio
-.model dio d TT=1371n IS=2.13E-08 N=1.564 RS=0.0038 m=0.548 Vj=0.1 Cjo=3200pF
-
-Va ad 0 DC 0.5 AC 1 $ DC -20
-Vk kd 0 0
-
-m1 d g s IXTP6N100D2
-.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1 subslope=43m subshift=-25m)
-
-Vd d 0 DC -0.5 AC 1 $ DC 20
-Vg g 0 -5 $ transistor is off
-Vs s 0 0
-
-.ac dec 10 1 100K
-
-.control
-save @d1[id] @m1[id] all
-run
-plot mag(i(Vs)) mag (i(Vk))
-plot ph(i(Vs)) ph(i(Vk))
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/VDMOS-DIO.cir b/Windows/spice/examples/vdmos/VDMOS-DIO.cir
deleted file mode 100644
index 9b9d4e17..00000000
--- a/Windows/spice/examples/vdmos/VDMOS-DIO.cir
+++ /dev/null
@@ -1,27 +0,0 @@
-Capacitance and current comparison between models d and bulk diode in vdmos
-
-D1 ad kd dio
-.model dio d TT=1371n IS=2.13E-08 N=1.564 RS=0.0038 m=0.548 Vj=0.1 Cjo=3200pF
-
-Va ad 0 dc 0 pwl(0 -2 2.5 0.5)
-Vk kd 0 0
-
-m1 d g s IXTP6N100D2
-.MODEL IXTP6N100D2 VDMOS(KP=2.9 RS=0.1 RD=1.3 RG=1 VTO=-2.7 LAMBDA=0.03 CGDMAX=3000p CGDMIN=2p CGS=2915p a=1 TT=1371n IS=2.13E-08 N=1.564 RB=0.0038 m=0.548 Vj=0.1 Cjo=3200pF ksubthres=0.1)
-
-Vd d 0 dc 0 pwl(0 2 2.5 -0.5)
-Vg g 0 -5 $ transistor is off
-Vs s 0 0
-
-.tran 10m 2.5
-
-.control
-save @d1[cd] @m1[cds] all
-run
-plot abs(i(Vk)) abs(i(Vs)) ylog
-plot @d1[cd] @m1[cds]
-*plot abs(i(Vk)) - abs(i(Vs))
-*plot @d1[cd] - @m1[cds]
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/inv_vdmos.cir b/Windows/spice/examples/vdmos/inv_vdmos.cir
deleted file mode 100644
index 1fa247c8..00000000
--- a/Windows/spice/examples/vdmos/inv_vdmos.cir
+++ /dev/null
@@ -1,24 +0,0 @@
-*****************==== Inverter ====*******************
-*********** VDMOS ****************************
-vdd 1 0 5
-
-.subckt inv out in vdd vss
-mp1 out in vdd p1
-mn1 out in vss n1
-.ends
-
-xinv 3 2 1 0 inv
-
-Vin 2 0 Pulse (0 5 10n 10n 10n 140n 300n)
-
-.tran 1n 1u
-
-.control
-run
-* current and output in a single plot
-plot v(2) v(3)
-.endc
-
-.model N1 vdmos cgdmin=0.2p cgdmax=1p a=2 cgs=0.5p rg=5k rb=1e9 cjo=0.1p
-.model P1 vdmos cgdmin=0.2p cgdmax=1p a=2 cgs=0.5p rg=5k rb=1e9 cjo=0.1p pchan
-.end
diff --git a/Windows/spice/examples/vdmos/inv_vdmos_dc.cir b/Windows/spice/examples/vdmos/inv_vdmos_dc.cir
deleted file mode 100644
index d81d8f54..00000000
--- a/Windows/spice/examples/vdmos/inv_vdmos_dc.cir
+++ /dev/null
@@ -1,25 +0,0 @@
-*****************==== Inverter ====*******************
-*********** VDMOS inverter dc ****************************
-vdd 1 0 5
-vss 4 0 0
-
-.subckt inv out in vdd vss
-mp1 out in vdd p1
-mn1 out in vss n1
-.ends
-
-xinv 3 2 1 4 inv
-
-Vin 2 0 0
-
-.dc Vin 0 5 0.05
-
-.control
-run
-* current and output in a single plot
-plot v(2) v(3) vss#branch
-.endc
-
-.model N1 vdmos cgdmin=0.2p cgdmax=1p a=2 cgs=0.5p rg=5k
-.model P1 vdmos cgdmin=0.2p cgdmax=1p a=2 cgs=0.5p rg=5k pchan
-.end
diff --git a/Windows/spice/examples/vdmos/mtriode_nch.sp b/Windows/spice/examples/vdmos/mtriode_nch.sp
deleted file mode 100644
index 463b84c6..00000000
--- a/Windows/spice/examples/vdmos/mtriode_nch.sp
+++ /dev/null
@@ -1,13 +0,0 @@
-VDMOS Mtriode Test
-M1 D G 0 IRFP240
-VG G 0 1V
-VD D 0 0.1V
-.control
-foreach myMTRIODE 0.5 1.0 1.5
- altermod @IRFP240[MTRIODE]=$myMTRIODE
- dc vd 0 30 0.1 vg 4 10 1
-end
-plot abs(dc1.vd#branch) abs(dc2.vd#branch) abs(dc3.vd#branch)
-.endc
-.model IRFP240 VDMOS(Rg=3 Vto=4 Rd=72m Rs=18m Rb=36m Kp=4.9 Lambda=.03 Cgdmax=1.34n Cgdmin=.1n Cgs=1.25n Cjo=1.25n Is=67p ksubthres=.1 Vds=200 Ron=180m Qg=70n)
-.end
diff --git a/Windows/spice/examples/vdmos/ro_11_vdmos.cir b/Windows/spice/examples/vdmos/ro_11_vdmos.cir
deleted file mode 100644
index 322567f1..00000000
--- a/Windows/spice/examples/vdmos/ro_11_vdmos.cir
+++ /dev/null
@@ -1,34 +0,0 @@
-*****************==== 11-Stage CMOS RO ====*******************
-*********** MOS1 or VDMOS ************************************
-vdd 1 0 5.0
-
-.subckt inv out in vdd vss
-mp1 out in vdd p1 l=2u w=20u
-mn1 out in vss n1 l=2u w=10u
-c1 out vss 0.2p
-.ends
-
-xinv1 3 2 1 0 inv
-xinv2 4 3 1 0 inv
-xinv3 5 4 1 0 inv
-xinv4 6 5 1 0 inv
-xinv5 7 6 1 0 inv
-xinv6 8 7 1 0 inv
-xinv7 9 8 1 0 inv
-xinv8 10 9 1 0 inv
-xinv9 2 10 1 0 inv
-
-.model N1 vdmos cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-5 rb=1e7 cjo=1n subslope=0.2
-.model P1 vdmos cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-5 rb=1e7 cjo=1n pchan subslope=0.2
-
-.tran 0.1n 1u
-
-.control
-
-run
-rusage
-* current and output in a single plot
-plot v(6) 1000*(-I(vdd)) ylimit -1 6
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/theta_nch.sp b/Windows/spice/examples/vdmos/theta_nch.sp
deleted file mode 100644
index 77317298..00000000
--- a/Windows/spice/examples/vdmos/theta_nch.sp
+++ /dev/null
@@ -1,13 +0,0 @@
-VDMOS Mobility Reduction
-M1 D G 0 IRFP240
-VG G 0 9V
-VD D 0 1V
-.control
-foreach myTHETA 0.1 0.2 0.3 0.4 0.5
- altermod @IRFP240[THETA]=$myTHETA
- dc VG 2 9 0.1
-end
-plot abs(dc1.vd#branch) abs(dc2.vd#branch) abs(dc3.vd#branch) abs(dc4.vd#branch) abs(dc5.vd#branch)
-.endc
-.model IRFP240 VDMOS(Rg=3 Vto=4 Rd=72m Rs=18m Rb=36m Kp=4.9 Lambda=.03 Cgdmax=1.34n Cgdmin=.1n Cgs=1.25n Cjo=1.25n Is=67p ksubthres=.1 Vds=200 Ron=180m Qg=70n)
-.end
diff --git a/Windows/spice/examples/vdmos/vdmos-out.cir b/Windows/spice/examples/vdmos/vdmos-out.cir
deleted file mode 100644
index e0433db1..00000000
--- a/Windows/spice/examples/vdmos/vdmos-out.cir
+++ /dev/null
@@ -1,18 +0,0 @@
-VDMOS output
-
-m1 d g s n1
-*.model n1 vdmos rb=0.05 is=10n kp=2 bv=12 rd=0.1
-.model N1 vdmos vto=1 cgdmin=0.05p cgdmax=0.2p a=1.2 cgs=0.15p rg=10 kp=2e-4 rb=1e4 is=1e-9 bv=12 cjo=1p subslope=0.1
-
-vd d 0 1
-vg g 0 1
-vs s 0 0
-
-.control
-dc vd -2 15 0.05 vg 0 5 1
-plot vs#branch
-dc vg 0 5 0.05 vd 0.5 2.5 0.5
-plot vs#branch ylog
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/vdmos-out_ir.cir b/Windows/spice/examples/vdmos/vdmos-out_ir.cir
deleted file mode 100644
index f3e141c1..00000000
--- a/Windows/spice/examples/vdmos/vdmos-out_ir.cir
+++ /dev/null
@@ -1,18 +0,0 @@
-VDMOS output
-
-m1 d g s IRFZ48Z
-
-.model IRFZ48Z VDMOS (Rg = 1.77 Vto=4 Rd=1.85m Rs=0.0m Rb=3.75m Kp=25 Cgdmax=2.1n Cgdmin=0.05n Cgs=1.8n Cjo=0.55n Is=2.5p tt=20n mfg=International_Rectifier Vds=55 Ron=8.6m Qg=43n)
-
-vd d 0 1
-vg g 0 1
-vs s 0 0
-
-.dc vd -1 15 0.05 vg 3 7 1
-
-.control
-run
-plot vs#branch
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/vdmos-out_ir_mtr.cir b/Windows/spice/examples/vdmos/vdmos-out_ir_mtr.cir
deleted file mode 100644
index e1f324f2..00000000
--- a/Windows/spice/examples/vdmos/vdmos-out_ir_mtr.cir
+++ /dev/null
@@ -1,26 +0,0 @@
-VDMOS output
-
-*m1 d g s IRFZ48Z
-m1 d g s SQ7002K
-
-m2 d g s2 SQ7002K_2
-
-*.model IRFZ48Z VDMOS (Rg = 1.77 Vto=4 Rd=1.85m Rs=0.0m Rb=3.75m Kp=25 Cgdmax=2.1n Cgdmin=0.05n Cgs=1.8n Cjo=0.55n Is=2.5p tt=20n mfg=International_Rectifier Vds=55 Ron=8.6m Qg=43n)
-
-.MODEL SQ7002K VDMOS(KP=0.46 RS=0.8751 RG=150 VTO=1.8 rds=50Meg LAMBDA=60m CGDMAX=20p CGDMIN=2p CGS=17p TT=500n a=0.47 IS=3.25n N=1.744 RB=0.118608 m=0.348 Vj=0.23 Cjo=14pF mtriode=1 Vds=60 Ron=1 Qg=0.9n mfg=VISHAY)
-
-.MODEL SQ7002K_2 VDMOS(KP=0.46 RS=0.8751 RG=150 VTO=1.8 rds=50Meg LAMBDA=60m CGDMAX=20p CGDMIN=2p CGS=17p TT=500n a=0.47 IS=3.25n N=1.744 RB=0.118608 m=0.348 Vj=0.23 Cjo=14pF mtriode=2 Vds=60 Ron=1 Qg=0.9n mfg=VISHAY)
-
-vd d 0 1
-vg g 0 1
-vs s 0 0
-vs2 s2 0 0
-
-.dc vd -1 7 0.05 vg 3 7 1
-
-.control
-run
-plot vs#branch vs2#branch
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/vdmosp-out-mtr.cir b/Windows/spice/examples/vdmos/vdmosp-out-mtr.cir
deleted file mode 100644
index a8c1e342..00000000
--- a/Windows/spice/examples/vdmos/vdmosp-out-mtr.cir
+++ /dev/null
@@ -1,26 +0,0 @@
-VDMOS p channel output
-
-m1 d g s IRF7233
-.model IRF7233 VDMOS(pchan Rg=3 Rd=8m Rs=6m Vto=-1 Kp=70 Cgdmax=2n Cgdmin=.25n Cgs=3.3n Cjo=.98n Is=98p Rb=10m mfg=International_Rectifier Vds=-12 Ron=20m Qg=49n)
-
-m2 d g s2 IRF7233_2
-.model IRF7233_2 VDMOS(pchan mtriode=2 Rg=3 Rd=8m Rs=6m Vto=-1 Kp=70 Cgdmax=2n Cgdmin=.25n Cgs=3.3n Cjo=.98n Is=98p Rb=10m mfg=International_Rectifier Vds=-12 Ron=20m Qg=49n)
-
-m3 d g s3 IRF7233_3
-.model IRF7233_3 VDMOS(pchan mtriode=2 Rg=3 Rd=8m Rs=6m Vto=-1 Kp=70 Cgdmax=2n Cgdmin=.25n Cgs=3.3n Cjo=.98n Is=98p Rb=10m mfg=International_Rectifier Vds=-12 Ron=20m Qg=49n ksubthres=0.1)
-
-vd d 0 -5
-vg g 0 -5
-vs s 0 0
-vs2 s2 0 0
-vs3 s3 0 0
-
-.control
-dc vd -12 1 0.05 vg 0 -5 -1
-plot vs#branch vs2#branch vs3#branch
-dc vg 0 -4 -0.05 vd -1 -12 -2
-plot vs#branch vs2#branch vs3#branch
-plot log(-vs#branch) log(-vs2#branch) log(-vs3#branch)
-.endc
-
-.end
diff --git a/Windows/spice/examples/vdmos/vdmosp-out.cir b/Windows/spice/examples/vdmos/vdmosp-out.cir
deleted file mode 100644
index 799ba04a..00000000
--- a/Windows/spice/examples/vdmos/vdmosp-out.cir
+++ /dev/null
@@ -1,17 +0,0 @@
-VDMOS p channel output
-
-m1 d g s p1
-.model p1 vdmos pchan vto=-1.2 is=10n kp=2 bv=-12 rb=1k
-
-vd d 0 -5
-vg g 0 -5
-vs s 0 0
-
-.dc vd -15 1 0.1 vg 0 -5 -1
-
-.control
-run
-plot vs#branch
-.endc
-
-.end
generated by cgit (git 2.34.1) at 2024-12-20 04:13:51 +0000