diff options
Diffstat (limited to 'Windows/spice/examples/various')
| -rw-r--r-- | Windows/spice/examples/various/FFT_Leakage.cir | 53 | ||||
| -rw-r--r-- | Windows/spice/examples/various/FFT_tests.cir | 123 | ||||
| -rw-r--r-- | Windows/spice/examples/various/adder_mos.cir | 79 | ||||
| -rw-r--r-- | Windows/spice/examples/various/agauss_test.cir | 48 | ||||
| -rw-r--r-- | Windows/spice/examples/various/gain_stage.cir | 34 | ||||
| -rw-r--r-- | Windows/spice/examples/various/modelcard.nmos | 34 | ||||
| -rw-r--r-- | Windows/spice/examples/various/modelcard.pmos | 29 | ||||
| -rw-r--r-- | Windows/spice/examples/various/nic_soa.cir | 39 | ||||
| -rw-r--r-- | Windows/spice/examples/various/param_sweep.cir | 29 |
9 files changed, 468 insertions, 0 deletions
diff --git a/Windows/spice/examples/various/FFT_Leakage.cir b/Windows/spice/examples/various/FFT_Leakage.cir new file mode 100644 index 00000000..b2bcfb7d --- /dev/null +++ b/Windows/spice/examples/various/FFT_Leakage.cir @@ -0,0 +1,53 @@ +FFT_Leakage_tests http://www.idea2ic.com/ +*=========Create_Signal================== +VTime VTime 0 DC 0 PWL( 0 0 1 1) +Vfreq Vfreq 0 DC 5.5k +BVAC IN 0 V = sin( 6.283185307179586*V(VFreq)*V(VTime)) +.control +*TRAN TSTEP TSTOP TSTART TMAX ?UIC? +tran 1u .999m 0 1u +set pensize = 2 +linearize +let numb2 = length(in) +print numb2 + +*=========Do_FFT_and_Plot_As_dB_Freq================== +let ac = in +j(0) +let ac_fft=fft(ac) +let numb_f2 = (numb2)/2 -1 +compose freq start = 1 stop = $&numb_f2 step =1 +compose vreal start = 1 stop = $&numb_f2 step =1 +compose vimag start = 1 stop = $&numb_f2 step =1 +let j = 0 +repeat $&numb_f2 +let freq[j] = freq[j] +let vreal[j] = 2*real(ac_fft[j+1]) +let vimag[j] = 2*imag(ac_fft[j+1]) +let j = j +1 +end +plot dB(abs(vreal+1f)) dB(abs(vimag+1f)) vs freq xlog + +*=========Extract_Error_Signal========================= +let funBin = 5k/1000 +let unvect = unitvec(numb2) +let fundspec = unvect*0 +j(0) +let fundspec[funBin] = real(ac_fft[funBin]) +j(imag(ac_fft[funBin] )) +let fundspec[numb2-funBin] = real(ac_fft[numb2-funBin]) +j(imag(ac_fft[numb2-funBin] )) +let fund = ifft(fundspec) +let dc_ofset = real(ac_fft[0]) +let thdspec = ac_fft +let thdspec[0] = 0 +j(0) +let thdspec[funBin] = 0 +j(0) +let thdspec[numb2-funBin] = 0 +j(0) +let thd = ifft(thdspec) +plot norm(in) norm(fund) norm(thd)/2 + +*=========Calc_Values========================= +let rms_Fund = sqrt(mean(fund*fund)) +let rms_THD = sqrt(mean(thd*thd)) +let THD_percent = 100*rms_THD/rms_Fund +let FREQ_Hz = VFreq[0] +echo "Freq_Hz=$&FREQ_Hz THD_percent=$&THD_percent Fund_rms=$&rms_Fund THD_rms=$&rms_THD " + +.endc +.end diff --git a/Windows/spice/examples/various/FFT_tests.cir b/Windows/spice/examples/various/FFT_tests.cir new file mode 100644 index 00000000..e7ede5ec --- /dev/null +++ b/Windows/spice/examples/various/FFT_tests.cir @@ -0,0 +1,123 @@ +FFT_tests http://www.idea2ic.com/ +.control +set units=degrees +let a = vector(16) +*plot a vs a +set pensize = 2 +*=========Need_a_complex_input==================== +let ac = a+j(0) +print a ac +*plot fft(a) vs a +*plot real(fft(ac)) imag(fft(ac)) vs a +* fft(a) fft(ac) + +*=========DC_Works==================== +let b = unitvec(16) +let bc = b+j(0) +*plot fft(b) vs a title DC_WORKS +*print fft(b) fft(bc) + +*=========DC_Plus_cos_Remove_AC==================== +let numb = length(b) +print numb + +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title DC_Plus_COS + +let fftac[2]=(0,0) +let fftac[14]=(0,0) +let ifftac = ifft(fftac) +plot ifftac ac vs a title COS_REMOVED + +*=========DC_Plus_cos_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifftac ac vs a title COS_With_DC_REMOVED + +*=========DC_Plus_sin_Remove_AC==================== +let indx = 0 +repeat $&numb +let ac[indx]= sin(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title DC_Plus_SIN + +let fftac[2]=(0,0) +let fftac[14]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title SIN_REMOVED + +*=========DC_Plus_sin_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= sin(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title SIN_With_DC_REMOVED + +*=========DC_Plus_cos_Nyqusit_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/2)+1 +j(0) +let indx = indx +1 +end + +plot ac vs a title Nyq_COS + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title Nyq_FREQ_COS +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title COS_With_DC_REMOVED +*=========DC_Plus_sin_Nyqusit_Remove_DC==================== +let indx = 0 +repeat $&numb +let ac[indx]= sin(indx*360/2)+1 +j(0) +let indx = indx +1 +end + +plot ac vs a title Nyq_SIN + +let fftac=fft(ac) +plot real(fftac) imag(fftac) vs a title Nyq_FREQ_SIN +let fftac[0]=(0,0) +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title COS_With_DC_REMOVED + +*=========DC_Plus_COS_Remove_One_BIN==================== +let indx = 0 +repeat $&numb +let ac[indx]= cos(indx*360/8)+1 +j(0) +let indx = indx +1 +end + +let fftac=fft(ac) +let fftac[2]=(0,0) +plot real(fftac) imag(fftac) vs a title DC_Plus_Cos + +let ifftac = ifft(fftac) +plot ifft(fftac) ac vs a title ONE_BIN_REMOVED + +plot real(ifft(fftac)) imag(ifft(fftac)) vs a title ONE_BIN_REMOVED + +.endc +.end diff --git a/Windows/spice/examples/various/adder_mos.cir b/Windows/spice/examples/various/adder_mos.cir new file mode 100644 index 00000000..9b85e093 --- /dev/null +++ b/Windows/spice/examples/various/adder_mos.cir @@ -0,0 +1,79 @@ + ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER + +*** SUBCIRCUIT DEFINITIONS +.SUBCKT NAND in1 in2 out VDD +* NODES: INPUT(2), OUTPUT, VCC +M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +.ENDS NAND + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 NAND +X2 1 7 8 6 NAND +X3 2 7 9 6 NAND +X4 8 9 10 6 NAND +X5 3 10 11 6 NAND +X6 3 11 12 6 NAND +X7 10 11 13 6 NAND +X8 12 13 4 6 NAND +X9 11 7 5 6 NAND +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** POWER +VCC 99 0 DC 3.3V + +*** ALL INPUTS +VIN1A 1 0 DC 0 PULSE(0 3 0 5NS 5NS 20NS 50NS) +VIN1B 2 0 DC 0 PULSE(0 3 0 5NS 5NS 30NS 100NS) +VIN2A 3 0 DC 0 PULSE(0 3 0 5NS 5NS 50NS 200NS) +VIN2B 4 0 DC 0 PULSE(0 3 0 5NS 5NS 90NS 400NS) +VIN3A 5 0 DC 0 PULSE(0 3 0 5NS 5NS 170NS 800NS) +VIN3B 6 0 DC 0 PULSE(0 3 0 5NS 5NS 330NS 1600NS) +VIN4A 7 0 DC 0 PULSE(0 3 0 5NS 5NS 650NS 3200NS) +VIN4B 8 0 DC 0 PULSE(0 3 0 5NS 5NS 1290NS 6400NS) + +*** DEFINE NOMINAL CIRCUIT +X1 1 2 3 4 5 6 7 8 9 10 11 12 0 13 99 FOURBIT + +.option noinit acct +.TRAN 500p 6400NS +* save inputs +.save V(1) V(2) V(3) V(4) V(5) V(6) V(7) V(8) + +* use BSIM3 model with default parameters +.model n1 nmos level=49 version=3.3.0 +.model p1 pmos level=49 version=3.3.0 +*.include ./Modelcards/modelcard32.nmos +*.include ./Modelcards/modelcard32.pmos + +.control +pre_set strict_errorhandling +unset ngdebug +*save outputs and specials +save x1.x1.x1.7 V(9) V(10) V(11) V(12) V(13) +run +display +* plot the inputs, use offset to plot on top of each other +plot v(1) v(2)+4 v(3)+8 v(4)+12 v(5)+16 v(6)+20 v(7)+24 v(8)+28 +* plot the outputs, use offset to plot on top of each other +plot v(9) v(10)+4 v(11)+8 v(12)+12 v(13)+16 +.endc + +.END diff --git a/Windows/spice/examples/various/agauss_test.cir b/Windows/spice/examples/various/agauss_test.cir new file mode 100644 index 00000000..c2532751 --- /dev/null +++ b/Windows/spice/examples/various/agauss_test.cir @@ -0,0 +1,48 @@ +* agauss test in ngspice +* generate a sequence of gaussian distributed random numbers. +* test the distribution by sorting the numbers into +* a histogram (buckets) +* chapt. 17.8.6 +.control + define agauss(nom, avar, sig) (nom + avar/sig * sgauss(0)) + let mc_runs = 200 + let run = 0 + let no_buck = 8 $ number of buckets + let bucket = unitvec(no_buck) $ each element contains 1 + let delta = 3e-11 $ width of each bucket, depends + $ on avar and sig + let lolimit = 1e-09 - 3*delta + let hilimit = 1e-09 + 3*delta + + dowhile run < mc_runs + let val = agauss(1e-09, 1e-10, 3) $ get the random number + if (val < lolimit) + let bucket[0] = bucket[0] + 1 $ 'lowest' bucket + end + let part = 1 + dowhile part < (no_buck - 1) + if ((val < (lolimit + part*delta)) & ++ (val > (lolimit + (part-1)*delta))) + let bucket[part] = bucket[part] + 1 + break + end + let part = part + 1 + end + if (val > hilimit) +* 'highest' bucket + let bucket[no_buck - 1] = bucket[no_buck - 1] + 1 + end + let run = run + 1 + end + + let part = 0 + dowhile part < no_buck + let value = bucket[part] - 1 + set value = "$&value" +* print the buckets' contents + echo $value + let part = part + 1 + end + +.endc +.end diff --git a/Windows/spice/examples/various/gain_stage.cir b/Windows/spice/examples/various/gain_stage.cir new file mode 100644 index 00000000..adc22bfb --- /dev/null +++ b/Windows/spice/examples/various/gain_stage.cir @@ -0,0 +1,34 @@ +** MOSFET Gain Stage (AC): Benchmarking Implementation of BSIM4.0.0 +** by Weidong Liu 5/16/2000. +** output redirection into file +** chapter 17.8.8 + +M1 3 2 0 0 N1 L=1u W=4u +Rsource 1 2 100k +Rload 3 vdd 25k +Vdd vdd 0 1.8 +Vin 1 0 1.2 ac 0.1 + +.control +ac dec 10 100 1000Meg +plot v(2) v(3) +let flen = length(frequency) $ length of the vector +let loopcounter = 0 +echo output test > text.txt $ start new file test.txt +* loop +while loopcounter lt flen + let vout2 = v(2)[loopcounter] $ generate a single point complex vector + let vout2re = real(vout2) $ generate a single point real vector + let vout2im = imag(vout2) $ generate a single point imaginary vector + let vout3 = v(3)[loopcounter] $ generate a single point complex vector + let vout3re = real(vout3) $ generate a single point real vector + let vout3im = imag(vout3) $ generate a single point imaginary vector + let freq = frequency[loopcounter] $ generate a single point vector + echo bbb "$&freq" "$&vout2re" "$&vout2im" "$&vout3re" "$&vout3im" >> ++text.txt $ append text and data to file (continued fromm line above) + let loopcounter = loopcounter + 1 +end +.endc + +.MODEL N1 NMOS LEVEL=14 VERSION=4.3.0 TNOM=27 +.end diff --git a/Windows/spice/examples/various/modelcard.nmos b/Windows/spice/examples/various/modelcard.nmos new file mode 100644 index 00000000..9a9bd56c --- /dev/null +++ b/Windows/spice/examples/various/modelcard.nmos @@ -0,0 +1,34 @@ +.model N1 NMOS ++Level= 8 version=3.3.0 ++Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 ++Tnom=27.0 ++Nch= 2.498E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=9.36e-8 Wint=1.47e-7 ++Vth0= .6322 K1= .756 K2= -3.83e-2 K3= -2.612 ++Dvt0= 2.812 Dvt1= 0.462 Dvt2=-9.17e-2 ++Nlx= 3.52291E-08 W0= 1.163e-6 ++K3b= 2.233 ++Vsat= 86301.58 Ua= 6.47e-9 Ub= 4.23e-18 Uc=-4.706281E-11 ++Rdsw= 650 U0= 388.3203 wr=1 ++A0= .3496967 Ags=.1 B0=0.546 B1= 1 ++Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = -.213 ++Keta=-3.605872E-02 A1= 2.778747E-02 A2= .9 ++Voff=-6.735529E-02 NFactor= 1.139926 Cit= 1.622527E-04 ++Cdsc=-2.147181E-05 ++Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 ++Cdscd = 0 Prwg = 0 ++Eta0= 1.0281729E-02 Etab=-5.042203E-03 ++Dsub= .31871233 ++Pclm= 1.114846 Pdiblc1= 2.45357E-03 Pdiblc2= 6.406289E-03 ++Drout= .31871233 Pscbe1= 5000000 Pscbe2= 5E-09 Pdiblcb = -.234 ++Pvag= 0 delta=0.01 ++Wl = 0 Ww = -1.420242E-09 Wwl = 0 ++Wln = 0 Wwn = .2613948 Ll = 1.300902E-10 ++Lw = 0 Lwl = 0 Lln = .316394 ++Lwn = 0 ++kt1=-.3 kt2=-.051 ++At= 22400 ++Ute=-1.48 ++Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 ++Kt1l=0 Prt=764.3 ++vgs_max=4 vds_max=4 vbs_max=4 diff --git a/Windows/spice/examples/various/modelcard.pmos b/Windows/spice/examples/various/modelcard.pmos new file mode 100644 index 00000000..1f67f274 --- /dev/null +++ b/Windows/spice/examples/various/modelcard.pmos @@ -0,0 +1,29 @@ +.model P1 PMOS ++Level= 8 version=3.3.0 ++Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 ++Tnom=27.0 ++Nch= 3.533024E+17 Tox=9E-09 Xj=1.00000E-07 ++Lint=6.23e-8 Wint=1.22e-7 ++Vth0=-.6732829 K1= .8362093 K2=-8.606622E-02 K3= 1.82 ++Dvt0= 1.903801 Dvt1= .5333922 Dvt2=-.1862677 ++Nlx= 1.28e-8 W0= 2.1e-6 ++K3b= -0.24 Prwg=-0.001 Prwb=-0.323 ++Vsat= 103503.2 Ua= 1.39995E-09 Ub= 1.e-19 Uc=-2.73e-11 ++Rdsw= 460 U0= 138.7609 ++A0= .4716551 Ags=0.12 ++Keta=-1.871516E-03 A1= .3417965 A2= 0.83 ++Voff=-.074182 NFactor= 1.54389 Cit=-1.015667E-03 ++Cdsc= 8.937517E-04 ++Cdscb= 1.45e-4 Cdscd=1.04e-4 ++Dvt0w=0.232 Dvt1w=4.5e6 Dvt2w=-0.0023 ++Eta0= 6.024776E-02 Etab=-4.64593E-03 ++Dsub= .23222404 ++Pclm= .989 Pdiblc1= 2.07418E-02 Pdiblc2= 1.33813E-3 ++Drout= .3222404 Pscbe1= 118000 Pscbe2= 1E-09 ++Pvag= 0 ++kt1= -0.25 kt2= -0.032 prt=64.5 ++At= 33000 ++Ute= -1.5 ++Ua1= 4.312e-9 Ub1= 6.65e-19 Uc1= 0 ++Kt1l=0 ++vgs_max=4 vds_max=4 vbs_max=4 diff --git a/Windows/spice/examples/various/nic_soa.cir b/Windows/spice/examples/various/nic_soa.cir new file mode 100644 index 00000000..5752d99d --- /dev/null +++ b/Windows/spice/examples/various/nic_soa.cir @@ -0,0 +1,39 @@ +CMOS NIC +* +.subckt osc_cmos ib_osz lc ra vdd vss +m16 ib_osz ib_osz vss vss n1 w=20u l=1u m=8 +m15 ra ib_osz vss vss n1 w=20u l=1u m=2 +m8 net99 net95 ra ra n1 w=20u l=1u m=2 +m1 net95 net95 net93 net93 n1 w=20u l=1u m=2 +m25 net99 net99 vdd vdd p1 w=3.3u l=0.5u m=1 +m5 net99 net99 vdd vdd p1 w=20u l=1u m=5 +m4 net95 net99 vdd vdd p1 w=20u l=1u m=5 +r23 net99 vss r=38K +r18 net93 lc r=10 +.ends osc_cmos +* +.subckt psens LC +R1 LC P001 40K +L1 LC P002 14.9u +R2 P002 0 0.55 +L2 P001 0 1.4m +.ends psens +* +xi36 bias lc ra vdd 0 osc_cmos +v39 vdd 0 dc=3.5 pulse ( 0 3.5 10u 10n 10n 1 2 ) +r4 ra 0 3.972K +c23 lc 0 1.8n +i37 vdd bias dc=1u +* +xi18 lc psens +* +.option warn=1 +.control +tran 1u 1m 0 50n +plot v(LC) +.endc +* +.include modelcard.nmos +.include modelcard.pmos +* +.end diff --git a/Windows/spice/examples/various/param_sweep.cir b/Windows/spice/examples/various/param_sweep.cir new file mode 100644 index 00000000..79d5869e --- /dev/null +++ b/Windows/spice/examples/various/param_sweep.cir @@ -0,0 +1,29 @@ +parameter sweep +* resistive divider, R1 swept from start_r to stop_r +* replaces .STEP R1 1k 10k 1k +* chapter 16.13.4.2 + +R1 1 2 1k +R2 2 0 1k + +VDD 1 0 DC 1 +.dc VDD 0 1 .1 + +.control +let start_r = 1k +let stop_r = 10k +let delta_r = 1k +let r_act = start_r +* loop +while r_act le stop_r + alter r1 r_act + run + write dc-sweep.out v(2) + set appendwrite + let r_act = r_act + delta_r +end +plot dc1.v(2) dc2.v(2) dc3.v(2) dc4.v(2) dc5.v(2) ++ dc6.v(2) dc7.v(2) dc8.v(2) dc9.v(2) dc10.v(2) +.endc + +.end |