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-rw-r--r--Windows/spice/examples/soi/Inv_chain.sp36
-rw-r--r--Windows/spice/examples/soi/bsim4soi/nmos4p0.mod99
-rw-r--r--Windows/spice/examples/soi/bsim4soi/pmos4p0.mod95
-rw-r--r--Windows/spice/examples/soi/inv_dc.sp25
-rw-r--r--Windows/spice/examples/soi/inv_tr.sp32
-rw-r--r--Windows/spice/examples/soi/ring51_40.sp60
6 files changed, 0 insertions, 347 deletions
diff --git a/Windows/spice/examples/soi/Inv_chain.sp b/Windows/spice/examples/soi/Inv_chain.sp
deleted file mode 100644
index 6cd43c78..00000000
--- a/Windows/spice/examples/soi/Inv_chain.sp
+++ /dev/null
@@ -1,36 +0,0 @@
-Mx Drain in Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
-
-.include ./bsim4soi/nmos4p0.mod
-.include ./bsim4soi/pmos4p0.mod
-*.option TEMP=27C ITL4=100 RELTOL=.01 GMINSTEPS=200 ABSTOL=1N VNTOL=1M
-
-Vpower VD 0 1.5
-Vgnd VS 0 0
-
-Vgate in VS PULSE(0v 1.5v 100ps 50ps 50ps 200ps 500ps)
-
-*drain gate source substrate body contact
-MN0 out0 in VS VS VS N1 W=5u L=0.18u
-MP0 out0 in VD VS VD P1 W=10u L=0.18u
-MN1 out1 Out0 VS VS VS N1 W=5u L=0.18u
-MP1 out1 Out0 VD VS VD P1 W=10u L=0.18u
-MN2 out2 Out1 VS VS VS N1 W=5u L=0.18u
-MP2 out2 Out1 VD VS VD P1 W=10u L=0.18u
-MN3 out3 Out2 VS VS VS N1 W=5u L=0.18u
-MP3 out3 Out2 VD VS VD P1 W=10u L=0.18u
-MN4 out4 Out3 VS VS VS N1 W=5u L=0.18u
-MP4 out4 Out3 VD VS VD P1 W=10u L=0.18u
-
-.tran 6p 600p
-.print tran v(in) v(out4)
-
-.control
-if $?batchmode
-* do nothing
-else
- run
- plot in out4
-endif
-.endc
-
-.END
diff --git a/Windows/spice/examples/soi/bsim4soi/nmos4p0.mod b/Windows/spice/examples/soi/bsim4soi/nmos4p0.mod
deleted file mode 100644
index 553fcace..00000000
--- a/Windows/spice/examples/soi/bsim4soi/nmos4p0.mod
+++ /dev/null
@@ -1,99 +0,0 @@
-* BSIMSOI4.0 example modelcard
-.Model N1 NMOS Level= 10
-
-+MOBMOD = 2 SHMOD = 1 CAPMOD = 2
-+SOIMOD = 0 IGBMOD = 1 IGCMOD = 1
-+RDSMOD = 0
-
-+TNOM = 25 TOX = 3.e-9 TSI = 41e-9
-+TBOX = 100e-9 TOXM = 3.e-9 VTH0 = 0.29
-+NCH = 4e17 NSUB = 1e16
-+RBODY = 0 RBSH = 0
-
-+LINT = 0 LLN = 1 LW = 0
-+LWN = 0 LWL = 0
-+WINT = 0 WLN = 1 WW = 0
-+WWN = 1 WWL = 0
-
-+CDSC = 1.3 CDSCB = 0.004 CDSCD = 0.1
-+CIT = 0.00007 NFACTOR = .9 XJ = 5E-08
-+VSAT = 86000 AT = 28000
-+A0 = 1.8 AGS = -0.175 A1 = 0
-+A2 = 0.99 KETA = 0.25 KETAS = 0.23
-+NGATE = 0
-+K1 = .59 KT1 = -.28 KT1L = 8e-9
-+KT2 = -.0646 K2 = 0 K3 = -3.5
-+K3B = 0 W0 = 0
-+LPE0 = 6.3E-8 DVT0 = 200 DVT1 = 3.72
-+DVT2 = 0.19 DVT0W = 0 DVT1W = 0
-+DVT2W = 0 DROUT = 3.617 DSUB = 1.12
-
-+UA = 8E-11 UA1 = 3.37e-10 UB = 2.2e-18
-+UB1 = -3.12e-18 UC = -5e-10 UC1 = -6.1e-10
-+U0 = 268 UTE = -1.6
-
-+VOFF = -.13 DELTA = 0.01 PRT = 10
-+RDSW = 175 PRWG = 0 PRWB = -0.0176
-+ETA0 = 0.31 ETAB = -.1605 PCLM = 1.8804
-+PDIBLC1 = 20 PDIBLC2 = 0 PDIBLCB = -0.05
-+PVAG = -0.07
-+WR = 1 DWG = 0 DWB = 0
-+B0 = 0 B1 = 10
-
-+NDIODE = 1.00 NRECF0 = 2.20 NRECR0 = 7.7
-+NDIODED = 1.00 NRECF0D = 2.20 NRECR0D = 7.7
-+NTUN = 25 ISDIF = 2e-6 ISREC = 13
-+NTUND = 25 IDDIF = 2e-6 IDREC = 13
-+ISTUN = 1e-5 VREC0 = 2.8 VTUN0 = 1
-+IDTUN = 1e-5 VREC0D = 2.8 VTUN0D = 1
-+IDBJT = 1e-5 AHLID = 1.5e-10
-+ISBJT = 4e-3 LBJT0 = 8e-8 VABJT = -0.4
-+AELY = 5.5e7 AHLI = 1.5e-10 NBJT = .6
-+FBJTII = 0.06 LN = .00001
-+NTRECF = 0.60 NTRECR = 1.2 XDIF = 1.15
-+XBJT = 1.08 XREC = 0.95 XTUN = 0
-+ALPHA0 = 1E-08 BETA0 = 0 BETA1 = .028
-+BETA2 = .067 TII = -0.7 SII0 = 3.4
-+SII1 = .8 SII2 = .08 SIID = 0.08
-+ESATII = 1.7e6 VDSATII0 = 0.55 LII = 3e-9
-+AGIDL = 0
-
-+RTH0 = .01 CTH0 = 1.46e-5
-
-+CLC = 1e-7 CLE = 0.6 XPART = 0.0
-+DWC = -0.0217e-6 DLC = 0.0120e-6 DELVT = -0.131
-+CGSO = 1.44e-10 CGDO = 1.44e-10 CGSL = 1.634e-10
-+CF = 0 CGDL = 1.634e-10 CKAPPA = 2
-+CJSWG = 3.79e-10 MJSWG = 0.675 PBSWG = 1.004
-+CJSWGD = 3.79e-10 MJSWGD = 0.675 PBSWGD = 1.004
-+TCJSWG = 6.5e-4 NDIF = -1 TT = 2.4e-10
-+DLBG = 0.105e-6 LDIF0 = 5e-3
-+KB1 = 1 CSDMIN = 0
-
-+TOXQM = 1.045E-9 TOXREF = 1.67e-9 NTOX = 1
-+EBG = 1.6 VEVB = 0.075 ALPHAGB1 = 0.465
-+BETAGB1 = 0.07 VGB1 = 40 VGB2 = 24
-+VECB = 0.018 ALPHAGB2 = 0.425 BETAGB2 = 0.055
-
-+AIGC = 0.043 BIGC = 0.0054 CIGC = 0.0075
-+AIGSD = 0.043 BIGSD = 0.0054 CIGSD = 0.0075
-+DLCIG = 2e-8 NIGC = 1 PIGCD = 1.0
-+POXEDGE = 1
-
-+FNOIMOD = 1 TNOIMOD = 1 TNOIA = 1
-+TNOIB = 2.5 RNOIA = 0.577 RNOIB = 0.37
-+NTNOI = 1.0 EM = 41000000 AF = 1
-+EF = 1 KF = 1 NOIF = 2.0
-
-+SAREF = 5E-6 SBREF = 5E-6 WLOD = 2E-6
-+KU0 = -4E-6 KVSAT = 0.2 KVTH0 = 0.0
-+TKU0 = 0.0 LLODKU0 = 1.1 WLODKU0 = 1.1
-+LLODVTH = 1.0 WLODVTH = 1.0 LKU0 = 1E-6
-+WKU0 = 1E-6 PKU0 = 0.0 LKVTH0 = 1.1E-6
-+WKVTH0 = 1.1E-6 PKVTH0 = 0.0 STK2 = 0.0
-+LODK2 = 1.0 STETA0 = 0.0 LODETA0 = 1.0
-
-+RGATEMOD= 0 RSHG = 1.1 XRCRG1 = 1
-+XRCRG2 = 1
-
-+RBODYMOD= 0 RBDB = 10 RBSB = 50
diff --git a/Windows/spice/examples/soi/bsim4soi/pmos4p0.mod b/Windows/spice/examples/soi/bsim4soi/pmos4p0.mod
deleted file mode 100644
index 48877bae..00000000
--- a/Windows/spice/examples/soi/bsim4soi/pmos4p0.mod
+++ /dev/null
@@ -1,95 +0,0 @@
-*BSIMSOI4.0 example modelcard
-.Model P1 PMOS Level= 10
-
-+MOBMOD = 2 SHMOD = 1 CAPMOD = 2
-+SOIMOD = 0 IGBMOD = 1 IGCMOD = 1
-+RDSMOD = 0
-
-+TNOM = 25 TOX = 3e-9 TOXM = 3e-9
-+TBOX = 4e-7 TSI = 41e-9 VTH0 = -0.15
-+NCH = 1.5e18 NSUB = 1e16
-+RBODY = 0 RBSH = 0
-
-+LINT = 0 LLN = 1 LW = 0
-+LWN = 0 LWL = 0
-+WINT = 0 WLN = 1 WW = 0
-+WWN = 1 WWL = 0
-
-+CDSC = .1835 CDSCB = 0.073 CDSCD = .1376
-+CIT = .00000918 NFACTOR = .8258 XJ = 5E-08
-+VSAT = 101362 AT = 6264
-+A0 = 1.5 AGS = 1.0 A1 = 0.145
-+A2 = 0.7 KETA = 0.1 KETAS = 0.07
-+NGATE = 0
-+K1 = .52 KT1 = -.18 KT1L = 6e-9
-+KT2 = -.02 K2 = 0 K3 = -1
-+K3B = 0 W0 = 0
-+LPE0 = 1.75E-07 DVT0 = 130 DVT1 = 2.4325
-+DVT2 = 0.07 DVT0W = 0 DVT1W = 0
-+DVT2W = 0
-+DROUT = 3.09 DSUB = 2.004
-
-+UA = 3E-10 UA1 = 4.36E-10 UB = 1.3067E-18
-+UB1 = -1.188E-18 UC = -6.5395E-10 UC1 = 1.537E-10
-+U0 = .0097 UTE = -.75
-+VOFF = -.15 DELTA = .04
-+RDSW = 340 PRWG = 0 PRWB = 0
-+PRT = 30
-+ETA0 = 5 ETAB = -.04 PCLM = .634584
-+PDIBLC1 = 10 PDIBLC2 = .0172 PDIBLCB = 1.12E-08
-+PVAG = -.15
-+WR = 1 DWG = 0 DWB = 0
-+B0 = 0 B1 = 0
-
-+NDIODE = 1.10 NRECF0 = 1.6 NRECR0 = 7.5
-+NDIODED = 1.10 NRECF0D = 1.6 NRECR0D = 7.5
-+NTUN = 2.05 ISDIF = 1.5e-4 ISREC = 1.8e-2
-+NTUND = 2.05 IDDIF = 1.5e-4 IDREC = 1.8e-2
-+ISTUN = 1.7e-5 VREC0 = 1.6 VTUN0 = 1.40
-+IDTUN = 1.7e-5 VREC0D = 1.6 VTUN0D = 1.40
-+ISBJT = .13 LBJT0 = 1e-8 VABJT = -0.9
-+IDBJT = .13 AHLID = 0.7E-09
-+AELY = 2E+07 AHLI = 0.7E-09 NBJT = .9
-+FBJTII = 0 LN = .00001
-+NTRECF = .05 NTRECR = 0.03 XDIF = 1.00
-+XBJT = 1.15 XREC = 0.85 XTUN = 0.0
-+ALPHA0 = 1E-08 BETA0 = 0 BETA1 = .034
-+BETA2 = .065 TII = -.5 SII0 = 3
-+SII1 = .7 SII2 = .08 SIID = -.4
-+ESATII = 3200000 LII = 0 VDSATII0 = 0.74
-+AGIDL = 0
-
-+RTH0 = .04 CTH0 = 1.46e-5
-
-+CLC = 1e-7 CLE = 0.6 XPART = 0
-+DWC = -0.029e-6 DLC = 0.021e-6 DELVT = -0.0686
-+CGSO = 0.38e-10 CGDO = 0.38e-10 CKAPPA = 4
-+CGSL = 2.3e-10 CGDL = 2.3e-10 CF = 0
-+CJSWG = 4.04e-10 MJSWG = 0.61275 PBSWG = 1.0363
-+CJSWGD = 4.04e-10 MJSWGD = 0.61275 PBSWGD = 1.0363
-+CJSWG =0.0 CJSWGD = 0.0
-+TCJSWG = 1.11e-3 TT = 2.0e-13 NDIF = -1
-+LDIF0 = 1 KB1 = 1 CSDMIN = 1e-20
-
-+TOXQM = 1.045E-9 TOXREF = 1.67e-9 NTOX = 1
-+EBG = 1.6 VEVB = 0.075 ALPHAGB1 = 0.465
-+BETAGB1 = 0.07 VGB1 = 40 VGB2 = 24
-+VECB = 0.018 ALPHAGB2 = 0.425 BETAGB2 = 0.055
-
-+AIGC = 0.043 BIGC = 0.0054 CIGC = 0.0075
-+AIGSD = 0.043 BIGSD = 0.0054 CIGSD = 0.0075
-+DLCIG = 2e-8 NIGC = 1 PIGCD = 1.0
-+POXEDGE = 1
-
-+SAREF = 5E-6 SBREF = 5E-6 WLOD = 2E-6
-+KU0 = 4E-6 KVSAT = 0.2 KVTH0 = 0.0
-+TKU0 = 0.0 LLODKU0 = 1.1 WLODKU0 = 1.1
-+LLODVTH = 1.0 WLODVTH = 1.0 LKU0 = 1E-6
-+WKU0 = 1E-6 PKU0 = 0.0 LKVTH0 = 1.1E-6
-+WKVTH0 = 1.1E-6 PKVTH0 = 0.0 STK2 = 0.0
-+LODK2 = 1.0 STETA0 = 0.0 LODETA0 = 1.0
-
-+RGATEMOD= 0 RSHG = 2.1 XRCRG1 = 12
-+XRCRG2 = 1
-
-+RBODYMOD= 0 RBDB = 10 RBSB = 50
diff --git a/Windows/spice/examples/soi/inv_dc.sp b/Windows/spice/examples/soi/inv_dc.sp
deleted file mode 100644
index 97fbcaea..00000000
--- a/Windows/spice/examples/soi/inv_dc.sp
+++ /dev/null
@@ -1,25 +0,0 @@
- Mx Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
-
-.include ./bsim4soi/nmos4p0.mod
-.include ./bsim4soi/pmos4p0.mod
-.option TEMP=27C
-
-Vpower VD 0 1.5
-Vgnd VS 0 0
-Vgate Gate 0 0.0
-MN0 Out Gate VS VS VS N1 W=10u L=0.18u
-MP0 Out Gate VD VS VD P1 W=20u L=0.18u
-.dc Vgate 0 1.5 0.05
-.print dc v(out)
-
-.control
-if $?batchmode
-* do nothing
-else
- run
- plot out
- plot Vgnd#branch
-endif
-.endc
-
-.END
diff --git a/Windows/spice/examples/soi/inv_tr.sp b/Windows/spice/examples/soi/inv_tr.sp
deleted file mode 100644
index b486374b..00000000
--- a/Windows/spice/examples/soi/inv_tr.sp
+++ /dev/null
@@ -1,32 +0,0 @@
-SOI Inverter
-* Mx Drain Gate Source Back-gate(substrate) Body Tx W L (body ommitted for FB)
-
-.include ./bsim4soi/nmos4p0.mod
-.include ./bsim4soi/pmos4p0.mod
-.option TEMP=27C
-
-Vpower VD 0 1.5
-Vgnd VS 0 0
-
-Vgate Gate VS DC 0 PULSE(0v 1.5v 100ps 50ps 50ps 200ps 500ps)
-
-*MN0 Out Gate VS VS VS N1 W=10u L=0.18u debug=1
-*MP0 Out Gate VD VS VD P1 W=20u L=0.18u debug=1
-
-MN0 Out Gate VS VS N1 W=10u L=0.18u Pd=11u Ps=11u
-MP0 Out Gate VD VS P1 W=20u L=0.18u Pd=11u Ps=11u
-
-.tran 3p 600ps
-.print tran v(gate) v(out)
-
-.control
-if $?batchmode
-* do nothing
-else
- run
- plot Vgnd#branch
- plot gate out
-endif
-.endc
-
-.END
diff --git a/Windows/spice/examples/soi/ring51_40.sp b/Windows/spice/examples/soi/ring51_40.sp
deleted file mode 100644
index 0c833466..00000000
--- a/Windows/spice/examples/soi/ring51_40.sp
+++ /dev/null
@@ -1,60 +0,0 @@
-* 51 stage Ring-Osc.
-
-vin in out 2 pulse 2 0 0.1n 5n 1 1 1
-vdd dd 0 dc 0 pulse 0 1.5 0 1n 1 1 1
-vss ss 0 dc 0
-ve sub 0 dc 0
-vn n1 0 0
-
-xinv1 dd ss sub in out25 inv25
-xinv2 dd ss sub out25 out50 inv25
-xinv5 dd ss sub out50 out inv1
-xinv11 dd ss sub out buf inv1
-cout buf ss 1pF
-
-* this is needed
-.option reltol=1e-4
-
-.tran 0.2n 16n
-.print tran v(out25) v(out50)
-.include ./bsim4soi/nmos4p0.mod
-.include ./bsim4soi/pmos4p0.mod
-
-
-.subckt inv1 dd ss sub in out
-mn1 out in ss sub n1 w=4u l=0.15u AS=6p AD=6p PS=7u PD=7u pdbcp=0u
-mp1 out in dd sub p1 w=10u l=0.15u AS=15p AD=15p PS=13u PD=13u pdbcp=0u
-.ends inv1
-
-.subckt inv5 dd ss sub in out
-xinv1 dd ss sub in 1 inv1
-xinv2 dd ss sub 1 2 inv1
-xinv3 dd ss sub 2 3 inv1
-xinv4 dd ss sub 3 4 inv1
-xinv5 dd ss sub 4 out inv1
-.ends inv5
-
-.subckt inv25 dd ss sub in out
-xinv1 dd ss sub in 1 inv5
-xinv2 dd ss sub 1 2 inv5
-xinv3 dd ss sub 2 3 inv5
-xinv4 dd ss sub 3 4 inv5
-xinv5 dd ss sub 4 out inv5
-.ends inv25
-
-.control
-if $?batchmode
-* do nothing
-else
- save out25 out50
- run
- plot out25 out50
- let lin-tstart = 4n $ skip the start-up phase
- let lin-tstop = 14n $ end earlier(just for demonstration)
- let lin-tstep = 5p
- linearize out25 out50
- plot out25 out50
-endif
-.endc
-
-.end
generated by cgit (git 2.34.1) at 2024-12-20 01:29:08 +0000