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Diffstat (limited to 'Windows/spice/examples/TransImpedanceAmp/output.net')
| -rw-r--r-- | Windows/spice/examples/TransImpedanceAmp/output.net | 464 |
1 files changed, 0 insertions, 464 deletions
diff --git a/Windows/spice/examples/TransImpedanceAmp/output.net b/Windows/spice/examples/TransImpedanceAmp/output.net deleted file mode 100644 index c56f3206..00000000 --- a/Windows/spice/examples/TransImpedanceAmp/output.net +++ /dev/null @@ -1,464 +0,0 @@ -********************************************************* -* Spice file generated by gnetlist * -* spice-SDB version 3.30.2003 by SDB -- * -* provides advanced spice netlisting capability. * -* Documentation at http://www.brorson.com/gEDA/SPICE/ * -********************************************************* - -* Batch command -* ngspice -b -o output.log output.net -* will generate a nice printer plot in output.log -* (remember the old times !) - -* Interactive commands for usage: -* run -* plot vout1 vout2 - -* Command stuff -.options gmin=1e-9 -.options method=gear -.options abstol=1e-11 -* .ac dec 10 10MegHz 10 Ghz -* Remainder of file -R112 0 6 1Meg -R111 0 8 10Meg -R110 0 7 1Meg -Rref2in 11 VU780out 25000 -Rref2fb VU2bias+ 11 33 -C201 0 9 1uF -C202 10 0 1uF -XU200 0 11 10 9 VU2bias+ OP177A -R202 10 +5V 22 -R201 -5V 9 22 -Rref1in VU100in- VU780out 9130 -Rref1fb VU1bias+ VU100in- 33 -XU101 +5V 7 0 6 VU780out 8 AD780A -* AD780A SPICE Macromodel 5/93, Rev. A -* AAG / PMI -* -* This version of the AD780 voltage reference model simulates the worst case -* parameters of the 'A' grade. The worst case parameters used -* correspond to those in the data sheet. -* -* Copyright 1993 by Analog Devices, Inc. -* -* Refer to "README.DOC" file for License Statement. Use of this model -* indicates your acceptance with the terms and provisions in the License Statement. -* -* NODE NUMBERS -* VIN -* | TEMP -* | | GND -* | | | TRIM -* | | | | VOUT -* | | | | | RANGE -* | | | | | | -.SUBCKT AD780A 2 3 4 5 6 8 -* -* BANDGAP REFERENCE -* -I1 4 40 DC 1.21174E-3 -R1 40 4 1E3 TC=7E-6 -EN 10 40 42 0 1 -G1 4 10 2 4 4.85668E-9 -F1 4 10 POLY(2) VS1 VS2 (0,2.42834E-5,3.8E-5) -Q1 2 10 11 QT -I2 11 4 DC 12.84E-6 -R2 11 3 1E3 -I3 3 4 DC 0 -* -* NOISE VOLTAGE GENERATOR -* -VN1 41 0 DC 2 -DN1 41 42 DEN -DN2 42 43 DEN -VN2 0 43 DC 2 -* -* INTERNAL OP AMP -* -G2 4 12 10 20 1.93522E-4 -R3 12 4 2.5837E9 -C1 12 4 6.8444E-11 -D1 12 13 DX -V1 2 13 DC 1.2 -* -* SECONDARY POLE @ 508 kHz -* -G3 4 14 12 4 1E-6 -R4 14 4 1E6 -C2 14 4 3.1831E-13 -* -* OUTPUT STAGE -* -ISY 2 4 6.8282E-4 -FSY 2 4 V1 -1 -RSY 2 4 500E3 -* -G4 4 15 14 4 25E-6 -R5 15 4 40E3 -Q2 4 15 16 QP -I4 2 16 DC 100E-6 -Q3 4 16 18 QP -R6 18 23 15 -R7 16 21 150E3 -R8 2 17 34.6 -Q4 17 16 19 QN -R9 21 20 6.46E3 -R10 20 4 6.1E3 -R11 20 5 53E3 -R12 20 8 15.6E3 -I5 5 4 DC 0 -I6 8 4 DC 0 -VS1 21 19 DC 0 -VS2 23 21 DC 0 -L1 21 6 1E-7 -* -* OUTPUT CURRENT LIMIT -* -FSC 15 4 VSC 1 -VSC 2 22 DC 0 -QSC 22 2 17 QN -* -.MODEL QT NPN(level=1 IS=1.68E-16 BF=1E4) -.MODEL QN NPN(level=1 IS=1E-15 BF=1E3) -.MODEL QP PNP(level=1 IS=1E-15 BF=1E3) -.MODEL DX D(IS=1E-15) -.MODEL DEN D(IS=1E-12 RS=2.425E+05 AF=1 KF=6.969E-16) -.ENDS AD780A -C101 0 U100V- 1uF -C102 U100V+ 0 1uF -XU100 0 VU100in- U100V+ U100V- VU1bias+ OP177A -* OP177A SPICE Macro-model 12/90, Rev. B -* JCB / PMI -* -* Revision History: -* REV. B -* Re-ordered subcircuit call out nodes to put the -* output node last. -* Changed Ios from 1E-9 to 0.5E-9 -* Added F1 and F2 to fix short circuit current limit. -* -* -* This version of the OP-177 model simulates the worst case -* parameters of the 'A' grade. The worst case parameters -* used correspond to those in the data book. -* -* -* Copyright 1990 by Analog Devices, Inc. -* -* Refer to "README.DOC" file for License Statement. Use of this model -* indicates your acceptance with the terms and provisions in the License Statement. -* -* Node assignments -* non-inverting input -* | inverting input -* | | positive supply -* | | | negative supply -* | | | | output -* | | | | | -.SUBCKT OP177A 1 2 99 50 39 -* -* INPUT STAGE & POLE AT 6 MHZ -* -R1 2 3 5E11 -R2 1 3 5E11 -R3 5 97 0.0606 -R4 6 97 0.0606 -CIN 1 2 4E-12 -C2 5 6 218.9E-9 -I1 4 51 1 -IOS 1 2 0.5E-9 -EOS 9 10 POLY(1) 30 33 10E-6 1 -Q1 5 2 7 QX -Q2 6 9 8 QX -R5 7 4 0.009 -R6 8 4 0.009 -D1 2 1 DX -D2 1 2 DX -EN 10 1 12 0 1 -GN1 0 2 15 0 1 -GN2 0 1 18 0 1 -* -EREF 98 0 33 0 1 -EPLUS 97 0 99 0 1 -ENEG 51 0 50 0 1 -* -* VOLTAGE NOISE SOURCE WITH FLICKER NOISE -* -DN1 11 12 DEN -DN2 12 13 DEN -VN1 11 0 DC 2 -VN2 0 13 DC 2 -* -* CURRENT NOISE SOURCE WITH FLICKER NOISE -* -DN3 14 15 DIN -DN4 15 16 DIN -VN3 14 0 DC 2 -VN4 0 16 DC 2 -* -* SECOND CURRENT NOISE SOURCE -* -DN5 17 18 DIN -DN6 18 19 DIN -VN5 17 0 DC 2 -VN6 0 19 DC 2 -* -* FIRST GAIN STAGE -* -R7 20 98 1 -G1 98 20 5 6 119.8 -D3 20 21 DX -D4 22 20 DX -E1 97 21 POLY(1) 97 33 -2.4 1 -E2 22 51 POLY(1) 33 51 -2.4 1 -* -* GAIN STAGE & DOMINANT POLE AT 0.127 HZ -* -R8 23 98 1.253E9 -C3 23 98 1E-9 -G2 98 23 20 33 33.3E-6 -V1 97 24 1.8 -V2 25 51 1.8 -D5 23 24 DX -D6 25 23 DX -* -* NEGATIVE ZERO AT -4MHZ -* -R9 26 27 1 -C4 26 27 -39.75E-9 -R10 27 98 1E-6 -E3 26 98 23 33 1E6 -* -* COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ -* -R13 30 31 1 -L2 31 98 2.52E-3 -G4 98 30 3 33 0.316E-6 -D7 30 97 DX -D8 51 30 DX -* -* POLE AT 2 MHZ -* -R14 32 98 1 -C5 32 98 79.5E-9 -G5 98 32 27 33 1 -* -* OUTPUT STAGE -* -R15 33 97 1 -R16 33 51 1 -GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 -F1 34 0 V3 1 -F2 0 34 V4 1 -R17 34 99 400 -R18 34 50 400 -L3 34 39 2E-7 -G6 37 50 32 34 2.5E-3 -G7 38 50 34 32 2.5E-3 -G8 34 99 99 32 2.5E-3 -G9 50 34 32 50 2.5E-3 -V3 35 34 6.8 -V4 34 36 4.4 -D9 32 35 DX -D10 36 32 DX -D11 99 37 DX -D12 99 38 DX -D13 50 37 DY -D14 50 38 DY -* -* MODELS USED -* -.MODEL QX NPN(level=1 BF=333.3E6) -.MODEL DX D(IS=1E-15) -.MODEL DY D(IS=1E-15 BV=50) -.MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) -.MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) -.ENDS -R102 U100V+ +5V 22 -R101 -5V U100V- 22 -R98 0 VU2bias+ 1K -R99 0 VU1bias+ 1K -C95 VU2bias+ 0 100pF -* C96 0 5 1uF -* C97 4 0 1uF -Cphotodiode 0 Vinput 0.9pF -C99 0 VU1bias+ 100pF -R25 Vout2 2 250 -C24 Vout1 VU1in- 1pF -R24 VU1in- 1 150 -* C21 0 3 1uF -Cc Vout2 VU2in- 1pF -Rc Vout1 VU2in- 10 -RL 0 Vout2 50 -.TEMP 0 25 50 75 100 -C12 2 0 1.5pF -C11 0 V2- .01uF -C10 V2+ 0 .01uF -R13 +5V V2+ 5 -R12 V2- -5V 5 -R26 2 VU2in- 150 -R11 Vout2 VU2in- 180 -XU2 VU2bias+ VU2in- V2+ V2- Vout2 AD8009an -XU1 VU1bias+ VU1in- V1+ V1- Vout1 AD8009an -***** AD8009 SPICE model Rev B SMR/ADI 8-21-97 - -* Copyright 1997 by Analog Devices, Inc. - -* Refer to "README.DOC" file for License Statement. Use of this model -* indicates your acceptance with the terms and provisions in the License Statement. - -* rev B of this model corrects a problem in the output stage that would not -* correctly reflect the output current to the voltage supplies - -* This model will give typical performance characteristics -* for the following parameters; - -* closed loop gain and phase vs bandwidth -* output current and voltage limiting -* offset voltage (is static, will not vary with vcm) -* ibias (again, is static, will not vary with vcm) -* slew rate and step response performance -* (slew rate is based on 10-90% of step response) -* current on output will be reflected to the supplies -* vnoise, referred to the input -* inoise, referred to the input - -* distortion is not characterized - -* Node assignments -* non-inverting input -* | inverting input -* | | positive supply -* | | | negative supply -* | | | | output -* | | | | | -.SUBCKT AD8009an 1 2 99 50 28 - -* input stage * - -q1 50 3 5 qp1 -q2 99 5 4 qn1 -q3 99 3 6 qn2 -q4 50 6 4 qp2 -i1 99 5 1.625e-3 -i2 6 50 1.625e-3 -cin1 1 98 2.6e-12 -cin2 2 98 1e-12 -v1 4 2 0 - -* input error sources * - -eos 3 1 poly(1) 20 98 2e-3 1 -fbn 2 98 poly(1) vnoise3 50e-6 1e-3 -fbp 1 98 poly(1) vnoise3 50e-6 1e-3 - -* slew limiting stage * - -fsl 98 16 v1 1 -dsl1 98 16 d1 -dsl2 16 98 d1 -dsl3 16 17 d1 -dsl4 17 16 d1 -rsl 17 18 0.22 -vsl 18 98 0 - -* gain stage * - -f1 98 7 vsl 2 -rgain 7 98 2.5e5 -cgain 7 98 1.25e-12 -dcl1 7 8 d1 -dcl2 9 7 d1 -vcl1 99 8 1.83 -vcl2 9 50 1.83 - -gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5 - -* second pole * - -epole 14 98 7 98 1 -rpole 14 15 1 -cpole 15 98 2e-10 - -* reference stage * - -eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 - -ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5 - -* vnoise stage * - -rnoise1 19 98 4.6e-3 -vnoise1 19 98 0 -vnoise2 21 98 0.53 -dnoise1 21 19 dn - -fnoise1 20 98 vnoise1 1 -rnoise2 20 98 1 - -* inoise stage * - -rnoise3 22 98 8.18e-6 -vnoise3 22 98 0 -vnoise4 24 98 0.575 -dnoise2 24 22 dn - -fnoise2 23 98 vnoise3 1 -rnoise4 23 98 1 - -* buffer stage * - -gbuf 98 13 15 98 1e-2 -rbuf 98 13 1e2 - -* output current reflected to supplies * - -fcurr 98 40 voc 1 -vcur1 26 98 0 -vcur2 98 27 0 -dcur1 40 26 d1 -dcur2 27 40 d1 - -* output stage * - -vo1 99 90 0 -vo2 91 50 0 -fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1 -fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1 -gout1 90 10 13 99 0.5 -gout2 91 10 13 50 0.5 -rout1 10 90 2 -rout2 10 91 2 -voc 10 28 0 -rout3 28 98 1e6 -dcl3 13 11 d1 -dcl4 12 13 d1 -vcl3 11 10 -0.445 -vcl4 10 12 -0.445 - -.model qp1 pnp(level=1) -.model qp2 pnp(level=1) -.model qn1 npn(level=1) -.model qn2 npn(level=1) -.model d1 d() -.model dn d(af=1 kf=1e-8) -.ends -R6 1 Vout1 250 -C3 1 0 1.5pF -V3 VU1in- Vinput DC 0V -* .INCLUDE /home/sdb/OpticalReceiver/Simulation.cmd -R5 -5V Vout1 1K -I1 0 Vinput AC 1 PWL (0ns 0mA 1nS 0mA 1.01nS 1mA 10nS 1mA 10.01nS 0mA 20nS 0mA 20.01nS .1mA 30nS .1mA 30.01nS 0mA) -R4 V1- -5V 5 -C2 0 V1- .01uF -V2 -5V 0 DC -5V -R2 VU1in- Vout1 180 -V1 +5V 0 DC 5V -C1 V1+ 0 .01uF -R1 +5V V1+ 5 -* When run, this SPICE file should output a square waveform -* with a little overshoot -.tran 0.05ns 40ns -.plot tran Vout2 -.END |