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diff --git a/Examples/d_ram_TestCircuit/d_ram_TestCircuit.cir.out b/Examples/d_ram_TestCircuit/d_ram_TestCircuit.cir.out
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+* /home/mallikarjuna/esim-workspace/d_ram_testcircuit/d_ram_testcircuit.cir
+
+* u5  net-_u4-pad5_ net-_u4-pad6_ net-_u4-pad7_ net-_u4-pad8_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ net-_u5-pad9_ net-_u5-pad10_ net-_u5-pad11_ net-_u5-pad12_ net-_u5-pad13_ net-_u5-pad14_ net-_u5-pad15_ net-_u5-pad16_ net-_u10-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_ram
+v4 a1 gnd  dc 0
+v6 a2 gnd  dc 0
+v8 a3 gnd  dc 0
+v10 a4 gnd  dc 0
+v12 a5 gnd  dc 5
+v13 a6 gnd  dc 5
+v14 a7 gnd  dc 5
+v15 a8 gnd  dc 5
+* u8  a8 a7 a6 a5 a4 a3 a2 a1 net-_u5-pad16_ net-_u5-pad15_ net-_u5-pad14_ net-_u5-pad13_ net-_u5-pad12_ net-_u5-pad11_ net-_u5-pad10_ net-_u5-pad9_ adc_bridge_8
+* u4  di1 di2 di3 di4 net-_u4-pad5_ net-_u4-pad6_ net-_u4-pad7_ net-_u4-pad8_ adc_bridge_4
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ adc_bridge_3
+* u10  wr_en net-_u10-pad2_ adc_bridge_1
+v3 net-_u1-pad3_ gnd  dc 5
+v2 net-_u1-pad2_ gnd  dc 5
+v1 net-_u1-pad1_ gnd  dc 0
+* u9  net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ do1 do2 do3 do4 dac_bridge_4
+* u12  do1 plot_v1
+* u13  do2 plot_v1
+* u14  do3 plot_v1
+* u15  do4 plot_v1
+v16  net-_r1-pad2_ gnd pwl(0 0 1.9999m 0 2m 5 3.9999m 5 4m 0 5.9999m 0 6m 5 7.9999m 5 8m 0)
+r1  wr_en net-_r1-pad2_ 1
+v5  di1 gnd pwl(0 5 1.9999m 5 2m 5 3.9999m 5 4m 0 5.9999m 0 6m 0 7.9999m 0 8m 5)
+v7  di2 gnd pwl(0 0 1.9999m 0 2m 0 3.9999m 0 4m 5 5.9999m 5 6m 5 7.9999m 5 8m 0)
+v9  di3 gnd pwl(0 5 1.9999m 5 2m 5 3.9999m 5 4m 0 5.9999m 0 6m 0 7.9999m 0 8m 5)
+v11  di4 gnd pwl(0 0 1.9999m 0 2m 0 3.9999m 0 4m 5 5.9999m 5 6m 5 7.9999m 5 8m 0)
+* u2  di1 plot_v1
+* u3  di2 plot_v1
+* u7  di3 plot_v1
+* u6  di4 plot_v1
+* u11  wr_en plot_v1
+a1 [net-_u4-pad5_ net-_u4-pad6_ net-_u4-pad7_ net-_u4-pad8_ ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] [net-_u5-pad9_ net-_u5-pad10_ net-_u5-pad11_ net-_u5-pad12_ net-_u5-pad13_ net-_u5-pad14_ net-_u5-pad15_ net-_u5-pad16_ ] net-_u10-pad2_ [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ] u5
+a2 [a8 a7 a6 a5 a4 a3 a2 a1 ] [net-_u5-pad16_ net-_u5-pad15_ net-_u5-pad14_ net-_u5-pad13_ net-_u5-pad12_ net-_u5-pad11_ net-_u5-pad10_ net-_u5-pad9_ ] u8
+a3 [di1 di2 di3 di4 ] [net-_u4-pad5_ net-_u4-pad6_ net-_u4-pad7_ net-_u4-pad8_ ] u4
+a4 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ] u1
+a5 [wr_en ] [net-_u10-pad2_ ] u10
+a6 [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] [do1 do2 do3 do4 ] u9
+* Schematic Name: d_ram, NgSpice Name: d_ram
+.model u5 d_ram(ic=2 select_value=6 read_delay=100.0e-9 data_load=1.0e-12 select_load=1.0e-12 address_load=1.0e-12 enable_load=1.0e-12 ) 
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u8 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u10 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
+.tran 10e-06 10e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(do1)
+plot v(do2)
+plot v(do3)
+plot v(do4)
+plot v(di1)
+plot v(di2)
+plot v(di3)
+plot v(di4)
+plot v(wr_en)
+.endc
+.end