diff options
Diffstat (limited to 'Examples/NGHDL_Examples')
57 files changed, 4693 insertions, 0 deletions
diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter-cache.lib b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter-cache.lib new file mode 100644 index 00000000..c6733b19 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# inverter +# +DEF inverter U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "inverter" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2550 2100 3150 1700 0 1 0 N +X in1 1 2350 1900 200 R 50 50 1 1 I +X out1 2 3350 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir new file mode 100644 index 00000000..7736c9d0 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir @@ -0,0 +1,26 @@ +* /home/saurabh/eSim-Workspace/Cmosinvertor/Cmosinvertor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Nov 27 14:17:36 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 out1 plot_v1 +X1 out7 out1 INVCMOS +X2 out1 out2 INVCMOS +X3 out2 out3 INVCMOS +U3 out2 plot_v1 +U4 out3 plot_v1 +X4 out3 out4 INVCMOS +U5 out4 plot_v1 +X5 out4 out5 INVCMOS +U6 out5 plot_v1 +X6 out5 out6 INVCMOS +U7 out6 plot_v1 +U8 out7 plot_v1 +U9 out6 Net-_U1-Pad1_ adc_bridge_1 +U10 Net-_U1-Pad2_ out7 dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ inverter + +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir.out b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir.out new file mode 100644 index 00000000..9cebe968 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir.out @@ -0,0 +1,45 @@ +* /home/saurabh/esim-workspace/cmosinvertor/cmosinvertor.cir + +.include INVCMOS.sub +* u2 out1 plot_v1 +x1 out7 out1 INVCMOS +x2 out1 out2 INVCMOS +x3 out2 out3 INVCMOS +* u3 out2 plot_v1 +* u4 out3 plot_v1 +x4 out3 out4 INVCMOS +* u5 out4 plot_v1 +x5 out4 out5 INVCMOS +* u6 out5 plot_v1 +x6 out5 out6 INVCMOS +* u7 out6 plot_v1 +* u8 out7 plot_v1 +* u9 out6 net-_u1-pad1_ adc_bridge_1 +* u10 net-_u1-pad2_ out7 dac_bridge_1 +* u1 net-_u1-pad1_ net-_u1-pad2_ inverter +a1 [out6 ] [net-_u1-pad1_ ] u9 +a2 [net-_u1-pad2_ ] [out7 ] u10 +a3 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-6 in_high=2.0 rise_delay=1.0e-6 in_low=1.0 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-6 t_fall=1.0e-6 input_load=1.0e-12 ) +* Schematic Name: inverter, NgSpice Name: inverter +.model u1 inverter(fall_delay=1.0e-6 input_load=1.0e-12 rise_delay=1.0e-6 instance_id=1 ) +.tran 1e-03 200e-03 0e-00 + +* Control Statements +.control +option noopalter +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out1) +plot v(out2) +plot v(out3) +plot v(out4) +plot v(out5) +plot v(out6) +plot v(out7) +.endc +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.pro b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.pro new file mode 100644 index 00000000..cb9e3c98 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.pro @@ -0,0 +1,74 @@ +update=Wed Nov 27 14:17:05 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName40=eSim_Nghdl + diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.proj b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.proj new file mode 100644 index 00000000..851b8737 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.proj @@ -0,0 +1 @@ +schematicFile Cmosinvertor.sch diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.sch b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.sch new file mode 100644 index 00000000..7abedbb2 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.sch @@ -0,0 +1,303 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:Cmosinvertor-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L plot_v1 U2 +U 1 1 5D6266E9 +P 4350 1950 +F 0 "U2" H 4350 2450 60 0000 C CNN +F 1 "plot_v1" H 4550 2300 60 0000 C CNN +F 2 "" H 4350 1950 60 0000 C CNN +F 3 "" H 4350 1950 60 0000 C CNN + 1 4350 1950 + 1 0 0 -1 +$EndComp +Text GLabel 4350 2100 3 60 Input ~ 0 +out1 +$Comp +L INVCMOS X1 +U 1 1 5D626E20 +P 3200 1850 +F 0 "X1" H 3200 1850 60 0000 C CNN +F 1 "INVCMOS" H 2750 2000 60 0000 C CNN +F 2 "" H 3200 1850 60 0001 C CNN +F 3 "" H 3200 1850 60 0001 C CNN + 1 3200 1850 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X2 +U 1 1 5D626E52 +P 5400 1850 +F 0 "X2" H 5400 1850 60 0000 C CNN +F 1 "INVCMOS" H 4950 2000 60 0000 C CNN +F 2 "" H 5400 1850 60 0001 C CNN +F 3 "" H 5400 1850 60 0001 C CNN + 1 5400 1850 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X3 +U 1 1 5D626EC9 +P 7000 1850 +F 0 "X3" H 7000 1850 60 0000 C CNN +F 1 "INVCMOS" H 6550 2000 60 0000 C CNN +F 2 "" H 7000 1850 60 0001 C CNN +F 3 "" H 7000 1850 60 0001 C CNN + 1 7000 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5D626F62 +P 6200 1950 +F 0 "U3" H 6200 2450 60 0000 C CNN +F 1 "plot_v1" H 6400 2300 60 0000 C CNN +F 2 "" H 6200 1950 60 0000 C CNN +F 3 "" H 6200 1950 60 0000 C CNN + 1 6200 1950 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5D626FB9 +P 8000 1950 +F 0 "U4" H 8000 2450 60 0000 C CNN +F 1 "plot_v1" H 8200 2300 60 0000 C CNN +F 2 "" H 8000 1950 60 0000 C CNN +F 3 "" H 8000 1950 60 0000 C CNN + 1 8000 1950 + 1 0 0 -1 +$EndComp +Text GLabel 6200 2150 3 60 Input ~ 0 +out2 +Text GLabel 8000 2150 3 60 Input ~ 0 +out3 +$Comp +L INVCMOS X4 +U 1 1 5D627966 +P 9050 1850 +F 0 "X4" H 9050 1850 60 0000 C CNN +F 1 "INVCMOS" H 8600 2000 60 0000 C CNN +F 2 "" H 9050 1850 60 0001 C CNN +F 3 "" H 9050 1850 60 0001 C CNN + 1 9050 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5D627A26 +P 9950 1950 +F 0 "U5" H 9950 2450 60 0000 C CNN +F 1 "plot_v1" H 10150 2300 60 0000 C CNN +F 2 "" H 9950 1950 60 0000 C CNN +F 3 "" H 9950 1950 60 0000 C CNN + 1 9950 1950 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X5 +U 1 1 5D628061 +P 8200 3100 +F 0 "X5" H 8200 3100 60 0000 C CNN +F 1 "INVCMOS" H 7750 3250 60 0000 C CNN +F 2 "" H 8200 3100 60 0001 C CNN +F 3 "" H 8200 3100 60 0001 C CNN + 1 8200 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5D628068 +P 9200 3200 +F 0 "U6" H 9200 3700 60 0000 C CNN +F 1 "plot_v1" H 9400 3550 60 0000 C CNN +F 2 "" H 9200 3200 60 0000 C CNN +F 3 "" H 9200 3200 60 0000 C CNN + 1 9200 3200 + 1 0 0 -1 +$EndComp +Text GLabel 9200 3400 3 60 Input ~ 0 +out5 +$Comp +L INVCMOS X6 +U 1 1 5D628071 +P 10250 3100 +F 0 "X6" H 10250 3100 60 0000 C CNN +F 1 "INVCMOS" H 9800 3250 60 0000 C CNN +F 2 "" H 10250 3100 60 0001 C CNN +F 3 "" H 10250 3100 60 0001 C CNN + 1 10250 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 5D628079 +P 11150 3200 +F 0 "U7" H 11150 3700 60 0000 C CNN +F 1 "plot_v1" H 11350 3550 60 0000 C CNN +F 2 "" H 11150 3200 60 0000 C CNN +F 3 "" H 11150 3200 60 0000 C CNN + 1 11150 3200 + 1 0 0 -1 +$EndComp +Text GLabel 11150 3400 3 60 Input ~ 0 +out6 +Text GLabel 9950 2100 3 60 Input ~ 0 +out4 +$Comp +L plot_v1 U8 +U 1 1 5D636DDC +P 14550 4000 +F 0 "U8" H 14550 4500 60 0000 C CNN +F 1 "plot_v1" H 14750 4350 60 0000 C CNN +F 2 "" H 14550 4000 60 0000 C CNN +F 3 "" H 14550 4000 60 0000 C CNN + 1 14550 4000 + 0 -1 -1 0 +$EndComp +Text GLabel 14750 4000 2 60 Input ~ 0 +out7 +$Comp +L adc_bridge_1 U9 +U 1 1 5D67A9F3 +P 12300 3150 +F 0 "U9" H 12300 3150 60 0000 C CNN +F 1 "adc_bridge_1" H 12300 3300 60 0000 C CNN +F 2 "" H 12300 3150 60 0000 C CNN +F 3 "" H 12300 3150 60 0000 C CNN + 1 12300 3150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 5D67AA64 +P 14400 3000 +F 0 "U10" H 14400 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 14400 3150 60 0000 C CNN +F 2 "" H 14400 3000 60 0000 C CNN +F 3 "" H 14400 3000 60 0000 C CNN + 1 14400 3000 + 0 1 1 0 +$EndComp +Wire Wire Line + 3900 1850 4950 1850 +Connection ~ 2550 1850 +Connection ~ 4350 1850 +Wire Wire Line + 6100 1850 6550 1850 +Wire Wire Line + 4350 1750 4350 2100 +Wire Wire Line + 6200 1750 6200 2150 +Connection ~ 6200 1850 +Wire Wire Line + 8000 1750 8000 2150 +Connection ~ 8000 1850 +Wire Wire Line + 7700 1850 8600 1850 +Connection ~ 9950 1850 +Wire Wire Line + 9950 1750 9950 2100 +Wire Wire Line + 7200 3100 7750 3100 +Wire Wire Line + 9200 3000 9200 3400 +Connection ~ 9200 3100 +Wire Wire Line + 8900 3100 9800 3100 +Wire Wire Line + 10950 3100 11700 3100 +Connection ~ 11150 3100 +Wire Wire Line + 11150 3000 11150 3400 +Wire Wire Line + 9750 1850 10400 1850 +Wire Wire Line + 10400 1850 10400 2500 +Wire Wire Line + 10400 2500 7200 2500 +Wire Wire Line + 7200 2500 7200 3100 +Wire Wire Line + 14350 4000 14750 4000 +Wire Wire Line + 14450 4950 14450 3550 +Connection ~ 14450 4000 +Wire Wire Line + 2550 4950 14450 4950 +Wire Wire Line + 2550 4950 2550 1850 +Wire Wire Line + 2550 1850 2750 1850 +Wire Wire Line + 13850 3100 14150 3100 +Wire Wire Line + 14150 3100 14150 2400 +Wire Wire Line + 14150 2400 14450 2400 +$Comp +L inverter U1 +U 1 1 5DDE38F5 +P 10500 5000 +F 0 "U1" H 13350 6800 60 0000 C CNN +F 1 "inverter" H 13350 7000 60 0000 C CNN +F 2 "" H 13350 6950 60 0000 C CNN +F 3 "" H 13350 6950 60 0000 C CNN + 1 10500 5000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter_Previous_Values.xml b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter_Previous_Values.xml new file mode 100644 index 00000000..a1a22d60 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v1 name="Source type">pwl<field1 name="Enter in pwl format">0m 0 0.5m 5 50m 5 50.5m 0 100m 0 100.5m 5 150m 5 150.5m 0 200m 0</field1></v1><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model><u9 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field1><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field3><field4 name="Enter value for in_low (default=1.0)" /></u9><u10 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u10><u1 name="type">inverter<field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field11><field12 name="Enter Input Load (default=1.0e-12)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Instance ID (Between 0-99)" /><field15 name="Enter the stop time to end the simulation (default=90e-9)" /></u1><u1 name="type">d_inverter<field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field11><field12 name="Enter Input Load (default=1.0e-12)" /><field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field13></u1><u27 name="type">inverter<field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-3</field11><field12 name="Enter Input Load (default=1.0e-12)" /><field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field13><field14 name="Enter Instance ID (Between 0-99)" /><field15 name="Enter the stop time to end the simulation (default=90e-9)">200e-3</field15></u27><u35 name="type">inverter<field16 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field16><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field18><field19 name="Enter Instance ID (Between 0-99)" /><field20 name="Enter the stop time to end the simulation (default=90e-9)">50e-3</field20></u35><u26 name="type">inverter<field21 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field21><field22 name="Enter Input Load (default=1.0e-12)" /><field23 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field23><field24 name="Enter Instance ID (Between 0-99)" /><field25 name="Enter the stop time to end the simulation (default=90e-9)">50e-3</field25></u26><u19 name="type">inverter<field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field26><field27 name="Enter Input Load (default=1.0e-12)" /><field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field28><field29 name="Enter Instance ID (Between 0-99)" /><field30 name="Enter the stop time to end the simulation (default=90e-9)">50e-3</field30></u19><u13 name="type">inverter<field31 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field31><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field33><field34 name="Enter Instance ID (Between 0-99)" /><field35 name="Enter the stop time to end the simulation (default=90e-9)" /></u13><u11 name="type">adc_bridge<field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field41><field42 name="Enter value for in_high (default=2.0)" /><field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field43><field44 name="Enter value for in_low (default=1.0)" /></u11><u14 name="type">dac_bridge<field45 name="Enter value for input load (default=1.0e-12)" /><field46 name="Enter value for out_low (default=0.0)" /><field47 name="Enter value for out_high (default=5.0)" /><field48 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field48><field49 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field49><field50 name="Enter value for out_undef (default=0.5)" /></u14><u16 name="type">adc_bridge<field51 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field51><field52 name="Enter value for in_high (default=2.0)" /><field53 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field53><field54 name="Enter value for in_low (default=1.0)" /></u16><u20 name="type">dac_bridge<field55 name="Enter value for input load (default=1.0e-12)" /><field56 name="Enter value for out_low (default=0.0)" /><field57 name="Enter value for out_high (default=5.0)" /><field58 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field58><field59 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field59><field60 name="Enter value for out_undef (default=0.5)" /></u20><u22 name="type">adc_bridge<field61 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field61><field62 name="Enter value for in_high (default=2.0)" /><field63 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field63><field64 name="Enter value for in_low (default=1.0)" /></u22><u28 name="type">dac_bridge<field65 name="Enter value for input load (default=1.0e-12)" /><field66 name="Enter value for out_low (default=0.0)" /><field67 name="Enter value for out_high (default=5.0)" /><field68 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field68><field69 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field69><field70 name="Enter value for out_undef (default=0.5)" /></u28><u23 name="type">adc_bridge<field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field71><field72 name="Enter value for in_high (default=2.0)" /><field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field73><field74 name="Enter value for in_low (default=1.0)" /></u23><u18 name="type">dac_bridge<field75 name="Enter value for input load (default=1.0e-12)" /><field76 name="Enter value for out_low (default=0.0)" /><field77 name="Enter value for out_high (default=5.0)" /><field78 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field78><field79 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field79><field80 name="Enter value for out_undef (default=0.5)" /></u18><u31 name="type">adc_bridge<field81 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field81><field82 name="Enter value for in_high (default=2.0)" /><field83 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field83><field84 name="Enter value for in_low (default=1.0)" /></u31><u33 name="type">dac_bridge<field85 name="Enter value for input load (default=1.0e-12)" /><field86 name="Enter value for out_low (default=0.0)" /><field87 name="Enter value for out_high (default=5.0)" /><field88 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field88><field89 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field89><field90 name="Enter value for out_undef (default=0.5)" /></u33><u32 name="type">adc_bridge<field91 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field91><field92 name="Enter value for in_high (default=2.0)" /><field93 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field93><field94 name="Enter value for in_low (default=1.0)" /></u32><u29 name="type">dac_bridge<field95 name="Enter value for input load (default=1.0e-12)" /><field96 name="Enter value for out_low (default=0.0)" /><field97 name="Enter value for out_high (default=5.0)" /><field98 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field98><field99 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field99><field100 name="Enter value for out_undef (default=0.5)" /></u29><u25 name="type">test<field101 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field101><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Instance ID (Between 0-99)" /><field105 name="Enter the stop time to end the simulation (default=90e-9)" /></u25></model><devicemodel /><subcircuit><x2><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x2><x3><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x3><x1><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x1><x6><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x6><x4><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x4><x5><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x5></subcircuit><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">true</field2><field3 name="Oct">false</field3><field4 name="Start Frequency">0</field4><field5 name="Stop Frequency">5k</field5><field6 name="No. of points">500</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">200</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS-cache.lib b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir.out b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.pro b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.pro new file mode 100644 index 00000000..b3f410b6 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.pro @@ -0,0 +1,73 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sch b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sub b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS_Previous_Values.xml b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/NMOS-180nm.lib b/Examples/NGHDL_Examples/Cmosinverter/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/Examples/NGHDL_Examples/Cmosinverter/PMOS-180nm.lib b/Examples/NGHDL_Examples/Cmosinverter/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/Examples/NGHDL_Examples/Cmosinverter/analysis b/Examples/NGHDL_Examples/Cmosinverter/analysis new file mode 100644 index 00000000..a8e9dce2 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/analysis @@ -0,0 +1 @@ +.tran 10e-03 200e-03 0e-00
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/plot_data_i.tx b/Examples/NGHDL_Examples/Cmosinverter/plot_data_i.tx new file mode 100644 index 00000000..15d7dd62 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/plot_data_i.tx @@ -0,0 +1,60 @@ + *for invcmos with delay 62000 nanosec, so cap should be 1nf + Transient Analysis Wed Oct 23 08:51:15 2019 +-------------------------------------------------------------------------------- +Index time a2#branch_1_0 v.x1.v1#branch v.x2.v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -8.10296e-12 -1.44365e-11 +1 1.000000e-09 -2.81078e-17 -8.10285e-12 -1.44365e-11 +2 1.002200e-09 2.173939e-01 -1.15227e-01 -2.74526e-05 +3 1.006600e-09 2.162815e-01 -1.13448e-01 -7.48490e-05 +4 1.010243e-09 2.184120e-01 -1.13038e-01 -1.11758e-04 +5 1.013853e-09 2.172991e-01 -1.11472e-01 -1.50114e-04 +6 1.021072e-09 2.204125e-01 -1.10247e-01 -2.25851e-04 +7 1.029746e-09 2.209561e-01 -1.07578e-01 -3.19174e-04 +8 1.037077e-09 2.251083e-01 -1.06654e-01 -4.00503e-04 +9 1.044524e-09 2.264092e-01 -1.04663e-01 -4.87674e-04 +10 1.052725e-09 2.323633e-01 -1.04138e-01 -5.90750e-04 +11 1.060435e-09 2.354511e-01 -1.02773e-01 -6.95387e-04 +12 1.069658e-09 2.439113e-01 -1.02939e-01 -8.29368e-04 +13 1.080335e-09 2.510799e-01 -1.02271e-01 -9.94574e-04 +14 1.094923e-09 2.663147e-01 -1.03510e-01 -1.23319e-03 +15 1.114447e-09 2.843269e-01 -1.04606e-01 -1.56812e-03 +16 1.144395e-09 3.179442e-01 -1.09102e-01 -2.10007e-03 +17 1.190797e-09 3.663899e-01 -1.15973e-01 -2.93245e-03 +18 1.283601e-09 5.487499e-01 -1.31536e-01 -4.33032e-03 +19 1.367572e-09 6.869171e-01 -1.43008e-01 -5.18245e-03 +20 1.468572e-09 6.638993e-01 -1.53553e-01 -5.94693e-03 +21 1.575043e-09 7.087558e-01 -1.61684e-01 -6.60929e-03 +22 1.744449e-09 7.155756e-01 -1.69761e-01 -7.32968e-03 +23 1.995252e-09 7.377316e-01 -1.76018e-01 -7.92003e-03 +24 2.000000e-09 7.498134e-01 -1.76074e-01 -7.92665e-03 +25 2.000968e-09 6.032277e-01 -1.20805e-01 -7.90845e-03 +26 2.002904e-09 5.301496e-01 -1.20018e-01 -7.87685e-03 +27 2.006775e-09 4.946923e-01 -1.18388e-01 -7.82068e-03 +28 2.014518e-09 4.093856e-01 -1.15275e-01 -7.72364e-03 +29 2.029459e-09 3.783576e-01 -1.09456e-01 -7.56518e-03 +30 2.047840e-09 3.325140e-01 -1.02789e-01 -7.38462e-03 +31 2.079088e-09 3.288911e-01 -9.24054e-02 -7.06326e-03 +32 2.128139e-09 2.842254e-01 -7.83721e-02 -6.48629e-03 +33 2.183865e-09 2.371959e-01 -6.50659e-02 -5.82424e-03 +34 2.248107e-09 1.818877e-01 -5.26591e-02 -5.10705e-03 +35 2.326304e-09 1.364069e-01 -4.06836e-02 -4.32089e-03 +36 2.396878e-09 9.925243e-02 -3.22625e-02 -3.68610e-03 +37 2.474793e-09 7.365848e-02 -2.49854e-02 -3.03297e-03 +38 2.547274e-09 4.389135e-02 -1.96751e-02 -2.45002e-03 +39 2.554737e-09 3.366325e-02 -1.91978e-02 -2.40654e-03 +40 2.565922e-09 4.044917e-02 -1.85142e-02 -2.34368e-03 +41 2.578642e-09 2.998465e-02 -1.77577e-02 -2.27518e-03 +42 2.604081e-09 3.565078e-02 -1.63497e-02 -2.14457e-03 +43 2.635687e-09 2.374005e-02 -1.47438e-02 -1.99289e-03 +44 2.690358e-09 2.761452e-02 -1.23454e-02 -1.75395e-03 +45 2.777848e-09 1.285724e-02 -9.27836e-03 -1.42710e-03 +46 2.952828e-09 1.360492e-02 -5.25991e-03 -9.35047e-04 +47 3.302787e-09 -2.04270e-03 -1.67270e-03 -3.75480e-04 +48 3.710524e-09 4.745747e-03 -7.00511e-04 -1.15819e-04 +49 4.291175e-09 -4.33351e-03 -4.91850e-04 -4.79768e-06 +50 4.826620e-09 4.345034e-03 -4.94953e-04 1.274213e-05 +51 5.608149e-09 -4.33393e-03 -4.92033e-04 1.737270e-05 +52 6.602216e-09 4.344829e-03 -4.94930e-04 1.719331e-05 +53 8.590352e-09 -4.33400e-03 -4.91980e-04 1.743737e-05 +54 1.256662e-08 4.344672e-03 -4.94826e-04 1.720508e-05 diff --git a/Examples/NGHDL_Examples/PWM_Decremental/NPN.lib b/Examples/NGHDL_Examples/PWM_Decremental/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PNP.lib b/Examples/NGHDL_Examples/PWM_Decremental/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental-cache.lib b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental-cache.lib new file mode 100644 index 00000000..68c7bb26 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental-cache.lib @@ -0,0 +1,169 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pwmdecrement +# +DEF pwmdecrement U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "pwmdecrement" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2550 2100 3150 1600 0 1 0 N +X in1 1 2350 1900 200 R 50 50 1 1 I +X in2 2 2350 1800 200 R 50 50 1 1 I +X out1 3 3350 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.cir b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.cir new file mode 100644 index 00000000..e4ef6256 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.cir @@ -0,0 +1,26 @@ +* /home/saurabh/eSim-Workspace/PWM_Decremental/PWM_Decremental.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Nov 14 23:21:31 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v2 Net-_X1-Pad7_ GND 9v +U3 D plot_v1 +X1 ? rc1 pwl_IN Net-_X1-Pad4_ ? D Net-_X1-Pad7_ ? lm_741 +R1 Q rc1 1k +U7 rc1 plot_v1 +C1 GND rc1 1u +U8 Net-_U2-Pad3_ Q dac_bridge_1 +U9 Q plot_v1 +U6 clk plot_v1 +v4 Net-_U4-Pad1_ GND pulse +U5 D Net-_U2-Pad2_ adc_bridge_1 +U4 Net-_U4-Pad1_ clk adc_bridge_1 +v3 Net-_X1-Pad4_ GND -9v +U1 pwl_IN plot_v1 +v1 pwl_IN GND 3 +U2 clk Net-_U2-Pad2_ Net-_U2-Pad3_ pwmdecrement + +.end diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.cir.out b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.cir.out new file mode 100644 index 00000000..0f70a899 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.cir.out @@ -0,0 +1,45 @@ +* /home/saurabh/esim-workspace/pwm_decremental/pwm_decremental.cir + +.include lm_741.sub +v2 net-_x1-pad7_ gnd 9v +* u3 d plot_v1 +x1 ? rc1 pwl_in net-_x1-pad4_ ? d net-_x1-pad7_ ? lm_741 +r1 q rc1 1k +* u7 rc1 plot_v1 +c1 gnd rc1 0.1u +* u8 net-_u2-pad3_ q dac_bridge_1 +* u9 q plot_v1 +* u6 clk plot_v1 +v4 net-_u4-pad1_ gnd pulse(0 5 10u 10u 20u 0.5m 1m) +* u5 d net-_u2-pad2_ adc_bridge_1 +* u4 net-_u4-pad1_ clk adc_bridge_1 +v3 net-_x1-pad4_ gnd -9v +* u1 pwl_in plot_v1 +v1 pwl_in gnd 3 +* u2 clk net-_u2-pad2_ net-_u2-pad3_ pwmdecrement +a1 [net-_u2-pad3_ ] [q ] u8 +a2 [d ] [net-_u2-pad2_ ] u5 +a3 [net-_u4-pad1_ ] [clk ] u4 +a4 [clk ] [net-_u2-pad2_ ] [net-_u2-pad3_ ] u2 +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: pwmdecrement, NgSpice Name: pwmdecrement +.model u2 pwmdecrement(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 instance_id=1 stop_time=240e-3 ) +.tran 1e-03 240e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(d) +plot v(rc1) +plot v(q) +plot v(clk) +plot v(pwl_in) +.endc +.end diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.pro b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.pro new file mode 100644 index 00000000..584970ee --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.pro @@ -0,0 +1,73 @@ +update=Thu Nov 14 23:19:57 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=switches +LibName4=relays +LibName5=motors +LibName6=transistors +LibName7=conn +LibName8=linear +LibName9=regul +LibName10=74xx +LibName11=cmos4000 +LibName12=adc-dac +LibName13=memory +LibName14=xilinx +LibName15=microcontrollers +LibName16=dsp +LibName17=microchip +LibName18=analog_switches +LibName19=motorola +LibName20=texas +LibName21=intel +LibName22=audio +LibName23=interface +LibName24=digital-audio +LibName25=philips +LibName26=display +LibName27=cypress +LibName28=siliconi +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/saurabh/eSim_kicad diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.proj b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.proj new file mode 100644 index 00000000..1dbaf32b --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.proj @@ -0,0 +1 @@ +schematicFile PWM_Decremental.sch diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.sch b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.sch new file mode 100644 index 00000000..0b75c70c --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:switches +LIBS:relays +LIBS:motors +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_kicad +LIBS:PWM_Incremental-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L DC v2 +U 1 1 5DCD9463 +P 3250 3200 +F 0 "v2" H 3050 3300 60 0000 C CNN +F 1 "9v" H 3050 3150 60 0000 C CNN +F 2 "R1" H 2950 3200 60 0000 C CNN +F 3 "" H 3250 3200 60 0000 C CNN + 1 3250 3200 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5DCD9464 +P 5400 4200 +F 0 "U3" H 5400 4700 60 0000 C CNN +F 1 "plot_v1" H 5600 4550 60 0000 C CNN +F 2 "" H 5400 4200 60 0000 C CNN +F 3 "" H 5400 4200 60 0000 C CNN + 1 5400 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR3 +U 1 1 5DCD9465 +P 3300 5150 +F 0 "#PWR3" H 3300 4900 50 0001 C CNN +F 1 "eSim_GND" H 3300 5000 50 0000 C CNN +F 2 "" H 3300 5150 50 0001 C CNN +F 3 "" H 3300 5150 50 0001 C CNN + 1 3300 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR2 +U 1 1 5DCD9466 +P 2700 3300 +F 0 "#PWR2" H 2700 3050 50 0001 C CNN +F 1 "eSim_GND" H 2700 3150 50 0000 C CNN +F 2 "" H 2700 3300 50 0001 C CNN +F 3 "" H 2700 3300 50 0001 C CNN + 1 2700 3300 + 1 0 0 -1 +$EndComp +Text GLabel 5550 4300 2 60 Input ~ 0 +D +$Comp +L lm_741 X1 +U 1 1 5DCD9467 +P 4450 4150 +F 0 "X1" H 4250 4150 60 0000 C CNN +F 1 "lm_741" H 4350 3900 60 0000 C CNN +F 2 "" H 4450 4150 60 0000 C CNN +F 3 "" H 4450 4150 60 0000 C CNN + 1 4450 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR1 +U 1 1 5DCD9468 +P 1600 3900 +F 0 "#PWR1" H 1600 3650 50 0001 C CNN +F 1 "eSim_GND" H 1600 3750 50 0000 C CNN +F 2 "" H 1600 3900 50 0001 C CNN +F 3 "" H 1600 3900 50 0001 C CNN + 1 1600 3900 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5DCD9469 +P 6400 4450 +F 0 "R1" V 6480 4450 50 0000 C CNN +F 1 "1k" V 6400 4450 50 0000 C CNN +F 2 "" V 6330 4450 50 0001 C CNN +F 3 "" H 6400 4450 50 0001 C CNN + 1 6400 4450 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 5DCD946A +P 7050 4400 +F 0 "U7" H 7050 4900 60 0000 C CNN +F 1 "plot_v1" H 7250 4750 60 0000 C CNN +F 2 "" H 7050 4400 60 0000 C CNN +F 3 "" H 7050 4400 60 0000 C CNN + 1 7050 4400 + 1 0 0 -1 +$EndComp +Text GLabel 7300 4450 2 60 Input ~ 0 +rc1 +NoConn ~ 4400 3750 +NoConn ~ 4500 3800 +$Comp +L C C1 +U 1 1 5DCD946B +P 6850 4800 +F 0 "C1" H 6875 4900 50 0000 L CNN +F 1 "1u" H 6875 4700 50 0000 L CNN +F 2 "" H 6888 4650 50 0001 C CNN +F 3 "" H 6850 4800 50 0001 C CNN + 1 6850 4800 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U8 +U 1 1 5DCD946C +P 8350 1900 +F 0 "U8" H 8350 1900 60 0000 C CNN +F 1 "dac_bridge_1" H 8350 2050 60 0000 C CNN +F 2 "" H 8350 1900 60 0000 C CNN +F 3 "" H 8350 1900 60 0000 C CNN + 1 8350 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR4 +U 1 1 5DCD946D +P 4500 3150 +F 0 "#PWR4" H 4500 2900 50 0001 C CNN +F 1 "eSim_GND" H 4500 3000 50 0000 C CNN +F 2 "" H 4500 3150 50 0001 C CNN +F 3 "" H 4500 3150 50 0001 C CNN + 1 4500 3150 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 5DCD946E +P 9300 2050 +F 0 "U9" H 9300 2550 60 0000 C CNN +F 1 "plot_v1" H 9500 2400 60 0000 C CNN +F 2 "" H 9300 2050 60 0000 C CNN +F 3 "" H 9300 2050 60 0000 C CNN + 1 9300 2050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5DCD946F +P 6250 2350 +F 0 "U6" H 6250 2850 60 0000 C CNN +F 1 "plot_v1" H 6450 2700 60 0000 C CNN +F 2 "" H 6250 2350 60 0000 C CNN +F 3 "" H 6250 2350 60 0000 C CNN + 1 6250 2350 + -1 0 0 1 +$EndComp +Text GLabel 9250 2350 2 60 Input ~ 0 +Q +Text GLabel 6500 2500 2 60 Input ~ 0 +clk +$Comp +L eSim_GND #PWR5 +U 1 1 5DCD9470 +P 6850 5450 +F 0 "#PWR5" H 6850 5200 50 0001 C CNN +F 1 "eSim_GND" H 6850 5300 50 0000 C CNN +F 2 "" H 6850 5450 50 0001 C CNN +F 3 "" H 6850 5450 50 0001 C CNN + 1 6850 5450 + 1 0 0 -1 +$EndComp +$Comp +L pulse v4 +U 1 1 5DCD9471 +P 4500 2700 +F 0 "v4" H 4300 2800 60 0000 C CNN +F 1 "pulse" H 4300 2650 60 0000 C CNN +F 2 "R1" H 4200 2700 60 0000 C CNN +F 3 "" H 4500 2700 60 0000 C CNN + 1 4500 2700 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U5 +U 1 1 5DCD9472 +P 5600 2250 +F 0 "U5" H 5600 2250 60 0000 C CNN +F 1 "adc_bridge_1" H 5600 2400 60 0000 C CNN +F 2 "" H 5600 2250 60 0000 C CNN +F 3 "" H 5600 2250 60 0000 C CNN + 1 5600 2250 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U4 +U 1 1 5DCD9473 +P 5550 1900 +F 0 "U4" H 5550 1900 60 0000 C CNN +F 1 "adc_bridge_1" H 5550 2050 60 0000 C CNN +F 2 "" H 5550 1900 60 0000 C CNN +F 3 "" H 5550 1900 60 0000 C CNN + 1 5550 1900 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 5DCD9474 +P 3750 5150 +F 0 "v3" H 3550 5250 60 0000 C CNN +F 1 "-9v" H 3550 5100 60 0000 C CNN +F 2 "R1" H 3450 5150 60 0000 C CNN +F 3 "" H 3750 5150 60 0000 C CNN + 1 3750 5150 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5DCD9475 +P 2800 4100 +F 0 "U1" H 2800 4600 60 0000 C CNN +F 1 "plot_v1" H 3000 4450 60 0000 C CNN +F 2 "" H 2800 4100 60 0000 C CNN +F 3 "" H 2800 4100 60 0000 C CNN + 1 2800 4100 + 1 0 0 -1 +$EndComp +Text GLabel 2800 3900 3 60 Input ~ 0 +pwl_IN +$Comp +L DC v1 +U 1 1 5DCD9476 +P 2050 3900 +F 0 "v1" H 1850 4000 60 0000 C CNN +F 1 "3" H 1850 3850 60 0000 C CNN +F 2 "R1" H 1750 3900 60 0000 C CNN +F 3 "" H 2050 3900 60 0000 C CNN + 1 2050 3900 + 0 1 1 0 +$EndComp +Wire Wire Line + 3700 3200 4300 3200 +Wire Wire Line + 4300 3200 4300 3700 +Wire Wire Line + 4300 4600 4300 5150 +Wire Wire Line + 5000 4150 5150 4150 +Wire Wire Line + 5400 4000 5400 4600 +Wire Wire Line + 5550 4300 5400 4300 +Connection ~ 5400 4300 +Connection ~ 2800 3900 +Wire Wire Line + 2500 3900 3050 3900 +Wire Wire Line + 3050 3900 3050 4400 +Wire Wire Line + 2700 3300 2700 3200 +Wire Wire Line + 2700 3200 2800 3200 +Connection ~ 4300 5150 +Wire Wire Line + 3150 4250 3900 4250 +Wire Wire Line + 3550 4000 3900 4000 +Wire Wire Line + 6550 4450 6850 4450 +Wire Wire Line + 6850 4450 6850 4650 +Wire Wire Line + 6250 4600 6250 4450 +Wire Wire Line + 7050 4500 7050 4200 +Wire Wire Line + 6850 4500 9300 4500 +Connection ~ 6850 4500 +Wire Wire Line + 7300 4450 7050 4450 +Wire Wire Line + 4300 5150 4200 5150 +Wire Wire Line + 8900 1850 9300 1850 +Wire Wire Line + 9050 1850 9050 3050 +Connection ~ 9050 1850 +Connection ~ 6100 4600 +Connection ~ 5150 4150 +Wire Wire Line + 6250 1850 6250 2550 +Connection ~ 6250 2200 +Wire Wire Line + 9250 2350 9200 2350 +Wire Wire Line + 9200 2350 9200 1850 +Connection ~ 9200 1850 +Wire Wire Line + 6500 2500 6250 2500 +Connection ~ 6250 2500 +Wire Wire Line + 6100 1850 6400 1850 +Connection ~ 6250 1850 +Wire Wire Line + 6400 1950 6150 1950 +Wire Wire Line + 6150 1950 6150 2200 +Wire Notes Line + 1200 5750 4850 5750 +Wire Notes Line + 1200 5750 1200 2450 +Wire Notes Line + 1200 2450 4150 2450 +Wire Notes Line + 4150 2450 4150 3150 +Wire Notes Line + 4150 3150 4850 3150 +Wire Notes Line + 4850 3150 4850 5750 +Wire Notes Line + 5950 3900 5950 5300 +Wire Notes Line + 5950 5300 8050 5300 +Wire Notes Line + 8050 5300 8050 3600 +Wire Notes Line + 8050 3600 5900 3600 +Wire Notes Line + 5900 3600 5900 3950 +Wire Notes Line + 5900 3950 5950 3950 +Wire Wire Line + 3150 4250 3150 4400 +Wire Wire Line + 3150 4400 3050 4400 +Wire Wire Line + 6850 4950 6850 5450 +Wire Wire Line + 2650 3700 3550 3700 +Wire Wire Line + 3550 3700 3550 4000 +Wire Wire Line + 2650 3750 2650 3700 +Wire Wire Line + 5150 2450 5150 4600 +Wire Wire Line + 2550 6400 9300 6400 +Wire Wire Line + 2550 6400 2550 3750 +Wire Wire Line + 9050 3050 6100 3050 +Wire Wire Line + 4500 1850 4950 1850 +Wire Wire Line + 4750 2200 5000 2200 +Wire Wire Line + 4750 2450 4750 2200 +Wire Wire Line + 5150 2450 4750 2450 +Wire Wire Line + 4500 1850 4500 2250 +Wire Wire Line + 5150 4600 5400 4600 +Wire Wire Line + 6100 3050 6100 4600 +Wire Wire Line + 6100 4600 6250 4600 +Wire Wire Line + 2550 3750 2650 3750 +Connection ~ 7050 4450 +Connection ~ 7050 4500 +Wire Wire Line + 7400 1850 7750 1850 +Wire Wire Line + 9300 6400 9300 4500 +$Comp +L pwmdecrement U2 +U 1 1 5DCD94AF +P 4050 3750 +F 0 "U2" H 6900 5550 60 0000 C CNN +F 1 "pwmdecrement" H 6900 5750 60 0000 C CNN +F 2 "" H 6900 5700 60 0000 C CNN +F 3 "" H 6900 5700 60 0000 C CNN + 1 4050 3750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental_Previous_Values.xml b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental_Previous_Values.xml new file mode 100644 index 00000000..0d1719aa --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/PWM_Decremental_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">80</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v2 name="Source type">9v</v2><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">10u</field3><field4 name="Rise Time">10u</field4><field5 name="Fall Time">20u</field5><field5 name="Pulse width">0.5m</field5><field5 name="Period">1m</field5></v4><v3 name="Source type">-9v</v3><v1 name="Source type">3</v1></source><model><u8 name="type">dac_bridge<field1 name="Enter value for input load (default=1.0e-12)" /><field2 name="Enter value for out_low (default=0.0)" /><field3 name="Enter value for out_high (default=5.0)" /><field4 name="Enter the Rise Time (default=1.0e-9)" /><field5 name="Enter the Fall Time (default=1.0e-9)" /><field6 name="Enter value for out_undef (default=0.5)" /></u8><u5 name="type">adc_bridge<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter value for in_high (default=2.0)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter value for in_low (default=1.0)" /></u5><u4 name="type">adc_bridge<field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter value for in_low (default=1.0)" /></u4><u2 name="type">pwmdecrement<field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Instance ID (Between 0-99)" /><field19 name="Enter the stop time to end the simulation (default=90e-9)">80e-3</field19></u2></model><devicemodel /><subcircuit><x1><field>/home/saurabh/Downloads/eSim-rahulp13-eSim/src/SubcircuitLibrary/lm_741</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Decremental/analysis b/Examples/NGHDL_Examples/PWM_Decremental/analysis new file mode 100644 index 00000000..c4435fb9 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/analysis @@ -0,0 +1 @@ +.tran 1e-03 80e-03 0e-00
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741-cache.lib b/Examples/NGHDL_Examples/PWM_Decremental/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741.cir b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741.cir.out b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741.pro b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.pro new file mode 100644 index 00000000..cbe83f35 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.pro @@ -0,0 +1,45 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741.sch b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 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50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN 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3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741.sub b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Decremental/lm_741_Previous_Values.xml b/Examples/NGHDL_Examples/PWM_Decremental/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Decremental/npn_1.lib b/Examples/NGHDL_Examples/PWM_Decremental/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Decremental/pnp_1.lib b/Examples/NGHDL_Examples/PWM_Decremental/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Decremental/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Incremental/NPN.lib b/Examples/NGHDL_Examples/PWM_Incremental/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PNP.lib b/Examples/NGHDL_Examples/PWM_Incremental/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental-cache.lib b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental-cache.lib new file mode 100644 index 00000000..96aae32d --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental-cache.lib @@ -0,0 +1,169 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pwmincrement +# +DEF pwmincrement U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "pwmincrement" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2550 2100 3150 1600 0 1 0 N +X in1 1 2350 1900 200 R 50 50 1 1 I +X in2 2 2350 1800 200 R 50 50 1 1 I +X out1 3 3350 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir new file mode 100644 index 00000000..e04c64f0 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir @@ -0,0 +1,26 @@ +* /home/saurabh/eSim-Workspace/PWM_Incremental/PWM_Incremental.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Nov 14 23:08:06 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v2 Net-_X1-Pad7_ GND 9v +U3 D plot_v1 +X1 ? rc1 pwl_IN Net-_X1-Pad4_ ? D Net-_X1-Pad7_ ? lm_741 +R1 Q rc1 1k +U7 rc1 plot_v1 +C1 GND rc1 1u +U8 Net-_U2-Pad3_ Q dac_bridge_1 +U9 Q plot_v1 +U6 clk plot_v1 +v4 Net-_U4-Pad1_ GND pulse +U5 D Net-_U2-Pad2_ adc_bridge_1 +U4 Net-_U4-Pad1_ clk adc_bridge_1 +v3 Net-_X1-Pad4_ GND -9v +U1 pwl_IN plot_v1 +v1 pwl_IN GND 3 +U2 clk Net-_U2-Pad2_ Net-_U2-Pad3_ pwmincrement + +.end diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir.out b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir.out new file mode 100644 index 00000000..4d222d7b --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir.out @@ -0,0 +1,45 @@ +* /home/saurabh/esim-workspace/pwm_incremental/pwm_incremental.cir + +.include lm_741.sub +v2 net-_x1-pad7_ gnd 9v +* u3 d plot_v1 +x1 ? rc1 pwl_in net-_x1-pad4_ ? d net-_x1-pad7_ ? lm_741 +r1 q rc1 1k +* u7 rc1 plot_v1 +c1 gnd rc1 1u +* u8 net-_u2-pad3_ q dac_bridge_1 +* u9 q plot_v1 +* u6 clk plot_v1 +v4 net-_u4-pad1_ gnd pulse(0 5 10u 10u 20u 0.5m 1m) +* u5 d net-_u2-pad2_ adc_bridge_1 +* u4 net-_u4-pad1_ clk adc_bridge_1 +v3 net-_x1-pad4_ gnd -9v +* u1 pwl_in plot_v1 +v1 pwl_in gnd 3 +* u2 clk net-_u2-pad2_ net-_u2-pad3_ pwmincrement +a1 [net-_u2-pad3_ ] [q ] u8 +a2 [d ] [net-_u2-pad2_ ] u5 +a3 [net-_u4-pad1_ ] [clk ] u4 +a4 [clk ] [net-_u2-pad2_ ] [net-_u2-pad3_ ] u2 +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: pwmincrement, NgSpice Name: pwmincrement +.model u2 pwmincrement(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 instance_id=1 stop_time=100e-3 ) +.tran 1e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(d) +plot v(rc1) +plot v(q) +plot v(clk) +plot v(pwl_in) +.endc +.end diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.pro b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.pro new file mode 100644 index 00000000..31e63107 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.pro @@ -0,0 +1,73 @@ +update=Thu Nov 14 23:00:31 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=switches +LibName4=relays +LibName5=motors +LibName6=transistors +LibName7=conn +LibName8=linear +LibName9=regul +LibName10=74xx +LibName11=cmos4000 +LibName12=adc-dac +LibName13=memory +LibName14=xilinx +LibName15=microcontrollers +LibName16=dsp +LibName17=microchip +LibName18=analog_switches +LibName19=motorola +LibName20=texas +LibName21=intel +LibName22=audio +LibName23=interface +LibName24=digital-audio +LibName25=philips +LibName26=display +LibName27=cypress +LibName28=siliconi +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/saurabh/eSim_kicad diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.proj b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.proj new file mode 100644 index 00000000..5bb660af --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.proj @@ -0,0 +1 @@ +schematicFile PWM_Incremental.sch diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.sch b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.sch new file mode 100644 index 00000000..dbb48d87 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:switches +LIBS:relays +LIBS:motors +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_kicad +LIBS:PWM_Incremental-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L DC v2 +U 1 1 5DCD8FFA +P 3250 3200 +F 0 "v2" H 3050 3300 60 0000 C CNN +F 1 "9v" H 3050 3150 60 0000 C CNN +F 2 "R1" H 2950 3200 60 0000 C CNN +F 3 "" H 3250 3200 60 0000 C CNN + 1 3250 3200 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5DCD8FFB +P 5400 4200 +F 0 "U3" H 5400 4700 60 0000 C CNN +F 1 "plot_v1" H 5600 4550 60 0000 C CNN +F 2 "" H 5400 4200 60 0000 C CNN +F 3 "" H 5400 4200 60 0000 C CNN + 1 5400 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR3 +U 1 1 5DCD8FFC +P 3300 5150 +F 0 "#PWR3" H 3300 4900 50 0001 C CNN +F 1 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5DCD9189 +P 4050 3750 +F 0 "U2" H 6900 5550 60 0000 C CNN +F 1 "pwmincrement" H 6900 5750 60 0000 C CNN +F 2 "" H 6900 5700 60 0000 C CNN +F 3 "" H 6900 5700 60 0000 C CNN + 1 4050 3750 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental_Previous_Values.xml b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental_Previous_Values.xml new file mode 100644 index 00000000..bd749bf9 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1m</field2><field3 name="Stop Time">100m</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source><v2 name="Source type">9v</v2><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">10u</field3><field4 name="Rise Time">10u</field4><field5 name="Fall Time">20u</field5><field5 name="Pulse width">0.5m</field5><field5 name="Period">1m</field5></v4><v3 name="Source type">-9v</v3><v1 name="Source type">3</v1></source><model><u8 name="type">dac_bridge<field1 name="Enter value for input load (default=1.0e-12)" /><field2 name="Enter value for out_low (default=0.0)" /><field3 name="Enter value for out_high (default=5.0)" /><field4 name="Enter the Rise Time (default=1.0e-9)" /><field5 name="Enter the Fall Time (default=1.0e-9)" /><field6 name="Enter value for out_undef (default=0.5)" /></u8><u5 name="type">adc_bridge<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter value for in_high (default=2.0)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter value for in_low (default=1.0)" /></u5><u4 name="type">adc_bridge<field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter value for in_low (default=1.0)" /></u4><u2 name="type">pwmincrement<field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Instance ID (Between 0-99)" /><field19 name="Enter the stop time to end the simulation (default=90e-9)">100e-3</field19></u2></model><devicemodel /><subcircuit><x1><field>/home/saurabh/Downloads/eSim-rahulp13-eSim/src/SubcircuitLibrary/lm_741</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Incremental/analysis b/Examples/NGHDL_Examples/PWM_Incremental/analysis new file mode 100644 index 00000000..93ae8d31 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/analysis @@ -0,0 +1 @@ +.tran 1me-00 100me-00 0e-03
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741-cache.lib b/Examples/NGHDL_Examples/PWM_Incremental/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir.out b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.pro b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.pro new file mode 100644 index 00000000..cbe83f35 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.pro @@ -0,0 +1,45 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sch b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 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9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sub b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741_Previous_Values.xml b/Examples/NGHDL_Examples/PWM_Incremental/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Incremental/npn_1.lib b/Examples/NGHDL_Examples/PWM_Incremental/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/PWM_Incremental/pnp_1.lib b/Examples/NGHDL_Examples/PWM_Incremental/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/Examples/NGHDL_Examples/PWM_Incremental/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/README.md b/Examples/NGHDL_Examples/README.md new file mode 100644 index 00000000..0842f75e --- /dev/null +++ b/Examples/NGHDL_Examples/README.md @@ -0,0 +1,13 @@ +Instructions on how to use the following examples provided in this directory: + +These examples are supported by the NGHDL feature. +In order to simulate the examples listed above, follow the below instructions. + (Note that NGHDL feature is only for Ubuntu Linux OS users as of on 27th November 2019) +1. Go to eSim main window -> Click on NGHDL icon from the left toolbar, click on the 'browse' button, go to ../nghdl/Example/ and locate which example you wish to simulate. +2. After opening the directory of desired example, locate the vhdl file , click on the "Open" button at the bottom of "Open File" window. +3. Click on 'upload' button in the NGHDL pop-up window. File will be processed in the backend for few seconds. Now exit the NGHDL window. +4. Open the desired example under eSim/Examples/NGHDL_Examples/ using the Open Project button, double click on the project when the project is loaded in the "Projects" window. +5. Click on the "Simulation" button on eSim Main window. + +More examples will be added by eSim team along the way. +If you have a good command on VHDL and electronics, please feel free to contribute. |