15 files changed, 0 insertions, 784 deletions
diff --git a/Examples/Integrator/D.lib b/Examples/Integrator/D.lib
deleted file mode 100644
index ef18bb50..00000000
--- a/Examples/Integrator/D.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL D1N750 D(
-+  Vj=.75
-+  Nbvl=14.976
-+  Cjo=175p
-+  Rs=.25
-+  Isr=1.859n
-+  Eg=1.11
-+  M=.5516
-+  Nbv=1.6989
-+  N=1
-+  Tbv1=-21.277u
-+  Bv=8.1
-+  Fc=.5
-+  Ikf=0
-+  Nr=2
-+  Ibv=20.245m
-+  Is=880.5E-18
-+  Xti=3
-+  Ibvl=1.9556m
-)
-\ No newline at end of file
diff --git a/Examples/Integrator/Integrator-cache.lib b/Examples/Integrator/Integrator-cache.lib
deleted file mode 100644
index 259458aa..00000000
--- a/Examples/Integrator/Integrator-cache.lib
+++ /dev/null
@@ -1,105 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND
-#
-DEF GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# UA741
-#
-DEF UA741 X 0 40 Y Y 1 F N
-F0 "X" 150 0 60 H V C CNN
-F1 "UA741" 250 -150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 4 0 1 0 0 150 0 -150 350 0 0 150 N
-X + 1 -200 100 200 R 50 50 1 1 I
-X - 2 -200 -100 200 R 50 50 1 1 I
-X ~ 3 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS capacitor
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 -50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-ALIAS resistor
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# plot_v1
-#
-DEF plot_v1 U 0 40 Y Y 1 F N
-F0 "U" 0 500 60 H V C CNN
-F1 "plot_v1" 200 350 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 500 100 0 1 0 N
-X ~ ~ 0 200 200 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# pwl
-#
-DEF pwl v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "pwl" -250 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50
-A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50
-A -75 -700 750 919 880 0 1 0 N -100 50 -50 50
-A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50
-A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 0 1 1 I
-X - 2 0 -450 300 U 50 0 1 1 I
-ENDDRAW
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-#
-#End Library
diff --git a/Examples/Integrator/Integrator.cir b/Examples/Integrator/Integrator.cir
deleted file mode 100644
index b7b0164b..00000000
--- a/Examples/Integrator/Integrator.cir
+++ /dev/null
@@ -1,19 +0,0 @@
-* /home/saurabh/Desktop/eSim/Examples/Integrator/Integrator.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Mar 11 16:27:08 2020
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_R2-Pad1_ Net-_C1-Pad2_ out UA741		
-v1  in GND pwl		
-U1  in plot_v1		
-U2  out plot_v1		
-R1  in Net-_C1-Pad2_ 10k		
-R2  Net-_R2-Pad1_ GND 1k		
-R3  out Net-_C1-Pad2_ 100k		
-C1  out Net-_C1-Pad2_ 100n		
-R4  GND out 1k		
-
-.end
diff --git a/Examples/Integrator/Integrator.cir.out b/Examples/Integrator/Integrator.cir.out
deleted file mode 100644
index 9db03242..00000000
--- a/Examples/Integrator/Integrator.cir.out
+++ /dev/null
@@ -1,23 +0,0 @@
-* /home/saurabh/desktop/esim/examples/integrator/integrator.cir
-
-.include ua741.sub
-x1 net-_r2-pad1_ net-_c1-pad2_ out ua741
-v1  in gnd pwl(0m 0 0.5m 5 25m 5 25.5m -5 50m -5 50.5m 5 75m 5 75.5m -5 100m -5)
-* u1  in plot_v1
-* u2  out plot_v1
-r1  in net-_c1-pad2_ 10k
-r2  net-_r2-pad1_ gnd 1k
-r3  out net-_c1-pad2_ 100k
-c1  out net-_c1-pad2_ 100n
-r4  gnd out 1k
-.tran 1e-03 100e-03 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-plot v(in)
-plot v(out)
-.endc
-.end
diff --git a/Examples/Integrator/Integrator.pro b/Examples/Integrator/Integrator.pro
deleted file mode 100644
index 0922f7b5..00000000
--- a/Examples/Integrator/Integrator.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Mar 18 18:52:14 2020
-version=1
-last_client=eeschema
-[general]
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-[pcbnew]
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-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_Subckt
-LibName10=eSim_User
-LibName11=adc-dac
-LibName12=memory
-LibName13=xilinx
-LibName14=microcontrollers
-LibName15=dsp
-LibName16=microchip
-LibName17=analog_switches
-LibName18=motorola
-LibName19=texas
-LibName20=intel
-LibName21=audio
-LibName22=interface
-LibName23=digital-audio
-LibName24=philips
-LibName25=display
-LibName26=cypress
-LibName27=siliconi
-LibName28=opto
-LibName29=atmel
-LibName30=contrib
-LibName31=power
-LibName32=transistors
-LibName33=conn
-LibName34=regul
-LibName35=74xx
-LibName36=cmos4000
diff --git a/Examples/Integrator/Integrator.proj b/Examples/Integrator/Integrator.proj
deleted file mode 100644
index 731ea735..00000000
--- a/Examples/Integrator/Integrator.proj
+++ /dev/null
@@ -1 +0,0 @@
-schematicFile Integrator.sch
diff --git a/Examples/Integrator/Integrator.sch b/Examples/Integrator/Integrator.sch
deleted file mode 100644
index d73bd6be..00000000
--- a/Examples/Integrator/Integrator.sch
+++ /dev/null
@@ -1,234 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:transistors
-LIBS:conn
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-Date ""
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-Comment4 ""
-$EndDescr
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-U 1 1 56A9B5FD
-P 5950 3200
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-F 2 "" H 5950 3200 60  0000 C CNN
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-	1    5950 3200
-	1    0    0    1   
-$EndComp
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-	5300 3100 5750 3100
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-$Comp
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-U 1 1 56A9B75D
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-F 3 "" H 5450 3600 50  0000 C CNN
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-$EndComp
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-F 2 "" H 4800 4000 50  0000 C CNN
-F 3 "" H 4800 4000 50  0000 C CNN
-	1    4800 4000
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-$EndComp
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-L GND #PWR3
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-F 2 "" H 6900 3500 50  0000 C CNN
-F 3 "" H 6900 3500 50  0000 C CNN
-	1    6900 3500
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-$EndComp
-Wire Wire Line
-	5000 3100 4800 3100
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-	6250 2700 6650 2700
-Connection ~ 6650 3200
-Text GLabel 4800 2950 0    60   Input ~ 0
-in
-Text GLabel 6850 3050 2    60   Input ~ 0
-out
-Wire Wire Line
-	4800 2950 4850 2950
-Wire Wire Line
-	4850 2850 4850 3100
-Connection ~ 4850 3100
-Wire Wire Line
-	6850 3050 6800 3050
-Wire Wire Line
-	6800 3000 6800 3200
-Connection ~ 6800 3200
-Wire Wire Line
-	5600 2350 5600 3100
-Wire Wire Line
-	6650 2350 6650 3200
-Wire Wire Line
-	5950 2350 5600 2350
-Connection ~ 5600 2700
-Wire Wire Line
-	6250 2350 6650 2350
-Connection ~ 6650 2700
-$Comp
-L pwl v1
-U 1 1 56B835AC
-P 4800 3550
-F 0 "v1" H 4600 3650 60  0000 C CNN
-F 1 "pwl" H 4550 3500 60  0000 C CNN
-F 2 "R1" H 4500 3550 60  0000 C CNN
-F 3 "" H 4800 3550 60  0000 C CNN
-	1    4800 3550
-	1    0    0    -1  
-$EndComp
-$Comp
-L plot_v1 U1
-U 1 1 56D45D76
-P 4850 3050
-F 0 "U1" H 4850 3550 60  0000 C CNN
-F 1 "plot_v1" H 5050 3400 60  0000 C CNN
-F 2 "" H 4850 3050 60  0000 C CNN
-F 3 "" H 4850 3050 60  0000 C CNN
-	1    4850 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L plot_v1 U2
-U 1 1 56D45DCF
-P 6800 3200
-F 0 "U2" H 6800 3700 60  0000 C CNN
-F 1 "plot_v1" H 7000 3550 60  0000 C CNN
-F 2 "" H 6800 3200 60  0000 C CNN
-F 3 "" H 6800 3200 60  0000 C CNN
-	1    6800 3200
-	1    0    0    -1  
-$EndComp
-Connection ~ 4850 2950
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-Text Notes 5050 2900 0    60   ~ 0
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-Text Notes 5250 3700 0    60   ~ 0
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-Text Notes 6300 2600 0    60   ~ 0
-100n
-Text Notes 5950 2150 0    60   ~ 0
-100k\n
-Text Notes 7100 3350 0    60   ~ 0
-1k
-$Comp
-L resistor R1
-U 1 1 5E68C500
-P 5100 3150
-F 0 "R1" H 5150 3280 50  0000 C CNN
-F 1 "10k" H 5150 3100 50  0000 C CNN
-F 2 "" H 5150 3130 30  0000 C CNN
-F 3 "" V 5150 3200 30  0000 C CNN
-	1    5100 3150
-	1    0    0    -1  
-$EndComp
-$Comp
-L resistor R2
-U 1 1 5E68C560
-P 5400 3400
-F 0 "R2" H 5450 3530 50  0000 C CNN
-F 1 "1k" H 5450 3350 50  0000 C CNN
-F 2 "" H 5450 3380 30  0000 C CNN
-F 3 "" V 5450 3450 30  0000 C CNN
-	1    5400 3400
-	0    1    1    0   
-$EndComp
-$Comp
-L resistor R3
-U 1 1 5E68C5B3
-P 6150 2300
-F 0 "R3" H 6200 2430 50  0000 C CNN
-F 1 "100k" H 6200 2250 50  0000 C CNN
-F 2 "" H 6200 2280 30  0000 C CNN
-F 3 "" V 6200 2350 30  0000 C CNN
-	1    6150 2300
-	-1   0    0    1   
-$EndComp
-$Comp
-L capacitor C1
-U 1 1 5E68C612
-P 6100 2700
-F 0 "C1" H 6125 2800 50  0000 L CNN
-F 1 "100n" H 6125 2600 50  0000 L CNN
-F 2 "" H 6138 2550 30  0000 C CNN
-F 3 "" H 6100 2700 60  0000 C CNN
-	1    6100 2700
-	0    1    1    0   
-$EndComp
-$Comp
-L resistor R4
-U 1 1 5E68C664
-P 6950 3400
-F 0 "R4" H 7000 3530 50  0000 C CNN
-F 1 "1k" H 7000 3350 50  0000 C CNN
-F 2 "" H 7000 3380 30  0000 C CNN
-F 3 "" V 7000 3450 30  0000 C CNN
-	1    6950 3400
-	0    -1   -1   0   
-$EndComp
-$EndSCHEMATC
diff --git a/Examples/Integrator/Integrator_Previous_Values.xml b/Examples/Integrator/Integrator_Previous_Values.xml
deleted file mode 100644
index 2079752b..00000000
--- a/Examples/Integrator/Integrator_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v1 name="Source type">pwl<field1 name="Enter in pwl format">0m 0 0.5m 5 25m 5 25.5m -5 50m -5 50.5m 5 75m 5 75.5m -5 100m -5</field1></v1></source><model /><devicemodel /><subcircuit><x1><field>/home/saurabh/Desktop/eSim-2.0/library/SubcircuitLibrary/ua741</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
-\ No newline at end of file
diff --git a/Examples/Integrator/PowerDiode.lib b/Examples/Integrator/PowerDiode.lib
deleted file mode 100644
index a2f61dce..00000000
--- a/Examples/Integrator/PowerDiode.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-)
-\ No newline at end of file
diff --git a/Examples/Integrator/analysis b/Examples/Integrator/analysis
deleted file mode 100644
index f496aec4..00000000
--- a/Examples/Integrator/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 1e-03 100e-03 0e-00
-\ No newline at end of file
diff --git a/Examples/Integrator/ua741.cir b/Examples/Integrator/ua741.cir
deleted file mode 100644
index de797429..00000000
--- a/Examples/Integrator/ua741.cir
+++ /dev/null
@@ -1,15 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U1  6 7 3 PORT		
-Rout1  3 2 75		
-Eout1  2 0 1 0 1		
-Cbw1  1 0 31.85e-9		
-Rbw1  1 4 0.5e6		
-Ein1  4 0 7 6 100e3		
-Rin1  7 6 2e6		
-
-.end
diff --git a/Examples/Integrator/ua741.cir.out b/Examples/Integrator/ua741.cir.out
deleted file mode 100644
index 72e68514..00000000
--- a/Examples/Integrator/ua741.cir.out
+++ /dev/null
@@ -1,18 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
-
-* u1  6 7 3 port
-rout1  3 2 75
-eout1  2 0 1 0 1
-cbw1  1 0 31.85e-9
-rbw1  1 4 0.5e6
-ein1  4 0 7 6 100e3
-rin1  7 6 2e6
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/Integrator/ua741.pro b/Examples/Integrator/ua741.pro
deleted file mode 100644
index c7b1d67b..00000000
--- a/Examples/Integrator/ua741.pro
+++ /dev/null
@@ -1,17 +0,0 @@
-update=Wed Mar 18 14:21:29 2020
-last_client=eeschema
-[eeschema]
-version=1
-LibDir=/home/yogesh/FreeEDA/library
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Devices
-LibName3=eSim_User
-LibName4=eSim_Subckt
-LibName5=eSim_Sources
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-LibName7=eSim_Plot
-LibName8=eSim_Miscellaneous
-LibName9=eSim_Hybrid
-LibName10=eSim_Digital
-LibName11=eSim_Analog
diff --git a/Examples/Integrator/ua741.sch b/Examples/Integrator/ua741.sch
deleted file mode 100644
index b06dcc17..00000000
--- a/Examples/Integrator/ua741.sch
+++ /dev/null
@@ -1,229 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Devices
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:eSim_Sources
-LIBS:eSim_Power
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-LIBS:eSim_Miscellaneous
-LIBS:eSim_Hybrid
-LIBS:eSim_Digital
-LIBS:eSim_Analog
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-Date "19 dec 2012"
-Rev ""
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-Text Notes 5800 2500 0    60   ~ 0
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-Text Notes 2750 3100 0    60   ~ 0
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-Text Notes 2700 2600 0    60   ~ 0
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-$Comp
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-F 3 "" H 6250 2500 60  0001 C CNN
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-	2    2300 3100
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-$EndComp
-$Comp
-L PORT U1
-U 3 1 5082C00B
-P 2250 2600
-F 0 "U1" H 2250 2550 30  0000 C CNN
-F 1 "PORT" H 2250 2600 30  0000 C CNN
-F 2 "" H 2250 2600 60  0001 C CNN
-F 3 "" H 2250 2600 60  0001 C CNN
-	3    2250 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PWR_FLAG #FLG1
-U 1 1 508152A0
-P 3450 3200
-F 0 "#FLG1" H 3450 3470 30  0001 C CNN
-F 1 "PWR_FLAG" H 3450 3430 30  0000 C CNN
-F 2 "" H 3450 3200 60  0001 C CNN
-F 3 "" H 3450 3200 60  0001 C CNN
-	1    3450 3200
-	1    0    0    -1  
-$EndComp
-$Comp
-L VCVS Eout1
-U 1 1 50813F0F
-P 5200 2900
-F 0 "Eout1" H 5000 3000 50  0000 C CNN
-F 1 "1" H 5000 2850 50  0000 C CNN
-F 2 "" H 5200 2900 60  0001 C CNN
-F 3 "" H 5200 2900 60  0001 C CNN
-	1    5200 2900
-	0    1    1    0   
-$EndComp
-$Comp
-L GND #PWR1
-U 1 1 50813E0D
-P 3700 3400
-F 0 "#PWR1" H 3700 3400 30  0001 C CNN
-F 1 "GND" H 3700 3330 30  0001 C CNN
-F 2 "" H 3700 3400 60  0001 C CNN
-F 3 "" H 3700 3400 60  0001 C CNN
-	1    3700 3400
-	1    0    0    -1  
-$EndComp
-$Comp
-L VCVS Ein1
-U 1 1 50813D7C
-P 3650 2850
-F 0 "Ein1" H 3450 2950 50  0000 C CNN
-F 1 "100e3" H 3450 2800 50  0000 C CNN
-F 2 "" H 3650 2850 60  0001 C CNN
-F 3 "" H 3650 2850 60  0001 C CNN
-	1    3650 2850
-	0    1    1    0   
-$EndComp
-Text Notes 2600 2900 0    60   ~ 0
-2e6\n
-Connection ~ 3700 3200
-Wire Wire Line
-	3450 3200 3700 3200
-Connection ~ 5000 3300
-Wire Wire Line
-	3700 3300 5250 3300
-Wire Wire Line
-	5250 3300 5250 3200
-Connection ~ 4550 3300
-Wire Wire Line
-	5000 3300 5000 2950
-Connection ~ 3700 3300
-Wire Wire Line
-	4550 3000 4550 3300
-Wire Wire Line
-	3900 2500 3700 2500
-Wire Wire Line
-	3700 2500 3700 2550
-Wire Wire Line
-	3450 2900 3300 2900
-Wire Wire Line
-	3300 2900 3300 3200
-Wire Wire Line
-	3300 3200 2950 3200
-Connection ~ 2950 3100
-Wire Wire Line
-	2950 3200 2950 3100
-Wire Wire Line
-	3000 2600 2500 2600
-Wire Wire Line
-	2550 3100 3000 3100
-Wire Wire Line
-	2950 2600 2950 2500
-Connection ~ 2950 2600
-Wire Wire Line
-	2950 2500 3300 2500
-Wire Wire Line
-	3300 2500 3300 2800
-Wire Wire Line
-	3300 2800 3450 2800
-Wire Wire Line
-	3700 3150 3700 3400
-Wire Wire Line
-	4550 2500 4550 2700
-Wire Wire Line
-	4400 2500 5000 2500
-Wire Wire Line
-	5000 2500 5000 2850
-Connection ~ 4550 2500
-Wire Wire Line
-	5250 2600 5250 2500
-Wire Wire Line
-	5250 2500 5400 2500
-Wire Wire Line
-	5700 2500 6000 2500
-$Comp
-L resistor Rin1
-U 1 1 5E71E232
-P 2950 2900
-F 0 "Rin1" H 3000 3030 50  0000 C CNN
-F 1 "2e6" H 3000 2850 50  0000 C CNN
-F 2 "" H 3000 2880 30  0000 C CNN
-F 3 "" V 3000 2950 30  0000 C CNN
-	1    2950 2900
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	3000 2600 3000 2800
-$Comp
-L resistor Rbw1
-U 1 1 5E71E326
-P 4050 2100
-F 0 "Rbw1" H 4100 2230 50  0000 C CNN
-F 1 "0.5e6" H 4100 2050 50  0000 C CNN
-F 2 "" H 4100 2080 30  0000 C CNN
-F 3 "" V 4100 2150 30  0000 C CNN
-	1    4050 2100
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	3900 2500 3900 2050
-Wire Wire Line
-	3900 2050 3950 2050
-Wire Wire Line
-	4250 2050 4400 2050
-Wire Wire Line
-	4400 2050 4400 2500
-$Comp
-L capacitor Cbw1
-U 1 1 5E71E45C
-P 4550 2850
-F 0 "Cbw1" H 4575 2950 50  0000 L CNN
-F 1 "31.85e-9" H 4575 2750 50  0000 L CNN
-F 2 "" H 4588 2700 30  0000 C CNN
-F 3 "" H 4550 2850 60  0000 C CNN
-	1    4550 2850
-	1    0    0    -1  
-$EndComp
-$Comp
-L resistor Rout1
-U 1 1 5E71E59C
-P 5500 2250
-F 0 "Rout1" H 5550 2380 50  0000 C CNN
-F 1 "75" H 5550 2200 50  0000 C CNN
-F 2 "" H 5550 2230 30  0000 C CNN
-F 3 "" V 5550 2300 30  0000 C CNN
-	1    5500 2250
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	5400 2500 5400 2200
-Wire Wire Line
-	5700 2200 5700 2500
-$EndSCHEMATC
diff --git a/Examples/Integrator/ua741.sub b/Examples/Integrator/ua741.sub
deleted file mode 100644
index ad26c001..00000000
--- a/Examples/Integrator/ua741.sub
+++ /dev/null
@@ -1,12 +0,0 @@
-* Subcircuit ua741
-.subckt ua741 6 7 3 
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
-rout1  3 2 75
-eout1  2 0 1 0 1
-cbw1  1 0 31.85e-9
-rbw1  1 4 0.5e6
-ein1  4 0 7 6 100e3
-rin1  7 6 2e6
-* Control Statements
-
-.ends ua741
-\ No newline at end of file