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-rw-r--r--Examples/Half_Adder/Half_Adder-cache.lib20
-rw-r--r--Examples/Half_Adder/Half_Adder.bak51
-rw-r--r--Examples/Half_Adder/Half_Adder.cir16
-rw-r--r--Examples/Half_Adder/Half_Adder.cir.out16
-rw-r--r--Examples/Half_Adder/Half_Adder.pro78
-rw-r--r--Examples/Half_Adder/Half_Adder.sch88
-rw-r--r--Examples/Half_Adder/Half_Adder_Previous_Values.xml2
-rw-r--r--Examples/Half_Adder/_saved_half_adder.sch154
-rwxr-xr-x[-rw-r--r--]Examples/Half_Adder/half_adder-cache.lib0
-rwxr-xr-xExamples/Half_Adder/half_adder.bak152
-rwxr-xr-x[-rw-r--r--]Examples/Half_Adder/half_adder.cir0
-rwxr-xr-x[-rw-r--r--]Examples/Half_Adder/half_adder.cir.out0
-rwxr-xr-x[-rw-r--r--]Examples/Half_Adder/half_adder.pro76
-rw-r--r--Examples/Half_Adder/half_adder.sch16
-rwxr-xr-x[-rw-r--r--]Examples/Half_Adder/half_adder.sub0
-rwxr-xr-x[-rw-r--r--]Examples/Half_Adder/half_adder_Previous_Values.xml2
-rw-r--r--Examples/Half_Adder/plot_data_i.txt8
-rw-r--r--Examples/Half_Adder/plot_data_v.txt8
18 files changed, 482 insertions, 205 deletions
diff --git a/Examples/Half_Adder/Half_Adder-cache.lib b/Examples/Half_Adder/Half_Adder-cache.lib
index 7b3ea0a8..6fec114a 100644
--- a/Examples/Half_Adder/Half_Adder-cache.lib
+++ b/Examples/Half_Adder/Half_Adder-cache.lib
@@ -18,11 +18,11 @@ X - 2 0 -450 300 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
-# GND
+# GND-RESCUE-Half_Adder
#
-DEF ~GND #PWR 0 0 Y Y 1 F P
+DEF ~GND-RESCUE-Half_Adder #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND" 0 -70 30 H I C CNN
+F1 "GND-RESCUE-Half_Adder" 0 -70 30 H I C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
@@ -47,18 +47,18 @@ ENDDEF
# R
#
DEF R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
-F2 "" -70 0 30 V V C CNN
-F3 "" 0 0 30 H V C CNN
+F0 "R" 50 130 50 H V C CNN
+F1 "R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
-S -40 -100 40 100 0 1 10 N
-X ~ 1 0 150 50 D 60 60 1 1 P
-X ~ 2 0 -150 50 U 60 60 1 1 P
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
ENDDRAW
ENDDEF
#
diff --git a/Examples/Half_Adder/Half_Adder.bak b/Examples/Half_Adder/Half_Adder.bak
index dcfb27c4..21c1e742 100644
--- a/Examples/Half_Adder/Half_Adder.bak
+++ b/Examples/Half_Adder/Half_Adder.bak
@@ -1,4 +1,13 @@
EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:Half_Adder-rescue
LIBS:power
LIBS:device
LIBS:transistors
@@ -10,7 +19,6 @@ LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
-LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
@@ -29,12 +37,7 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
+LIBS:Half_Adder-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
@@ -105,7 +108,7 @@ F 3 "" H 3450 3800 60 0000 C CNN
0 1 1 0
$EndComp
$Comp
-L GND #PWR01
+L GND-RESCUE-Half_Adder #PWR01
U 1 1 558A93BB
P 2950 4000
F 0 "#PWR01" H 2950 4000 30 0001 C CNN
@@ -116,7 +119,7 @@ F 3 "" H 2950 4000 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L GND #PWR02
+L GND-RESCUE-Half_Adder #PWR02
U 1 1 558A93D7
P 2950 3250
F 0 "#PWR02" H 2950 3250 30 0001 C CNN
@@ -149,7 +152,7 @@ F 3 "" H 7850 3550 30 0000 C CNN
0 1 1 0
$EndComp
$Comp
-L GND #PWR03
+L GND-RESCUE-Half_Adder #PWR03
U 1 1 558A9480
P 8350 3650
F 0 "#PWR03" H 8350 3650 30 0001 C CNN
@@ -236,14 +239,6 @@ Text GLabel 4050 3150 2 60 Input ~ 0
A
Text GLabel 4100 3750 2 60 Input ~ 0
B
-Text GLabel 5200 3250 0 60 Input ~ 0
-1
-Text GLabel 5200 3700 0 60 Input ~ 0
-2
-Text GLabel 6550 3250 2 60 Input ~ 0
-3
-Text GLabel 6550 3650 2 60 Input ~ 0
-4
Wire Wire Line
4050 3150 4050 3250
Wire Wire Line
@@ -253,25 +248,13 @@ Wire Wire Line
4100 3750 3950 3750
Connection ~ 3950 3750
Wire Wire Line
- 5200 3700 5300 3700
-Connection ~ 5300 3700
-Wire Wire Line
- 5200 3250 5250 3250
-Wire Wire Line
- 5250 3250 5250 3450
-Connection ~ 5250 3450
-Wire Wire Line
- 6550 3250 6450 3250
-Connection ~ 6450 3250
-Wire Wire Line
- 6550 3650 6450 3650
-Connection ~ 6450 3650
-Wire Wire Line
7600 3750 7650 3750
Wire Wire Line
7650 3750 7650 3550
Connection ~ 7650 3550
Wire Wire Line
- 7600 3150 7600 3350
-Connection ~ 7600 3350
+ 7600 3150 7650 3150
+Wire Wire Line
+ 7650 3150 7650 3300
+Connection ~ 7650 3300
$EndSCHEMATC
diff --git a/Examples/Half_Adder/Half_Adder.cir b/Examples/Half_Adder/Half_Adder.cir
index 750f7d56..c12e1d5e 100644
--- a/Examples/Half_Adder/Half_Adder.cir
+++ b/Examples/Half_Adder/Half_Adder.cir
@@ -1,15 +1,17 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 15:44:17 2015
+* /home/fossee/Downloads/eSim-master/Examples/Half_Adder/Half_Adder.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Aug 19 15:02:03 2015
* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-*Sheet Name:/
-X1 1 2 3 4 half_adder
-U1 A B 1 2 adc_bridge_2
-U2 3 4 sum cout dac_bridge_2
+* Sheet Name: /
+X1 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder
+U1 A B Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2
v1 A GND DC
v2 B GND DC
-R1 GND sum 1k
-R2 GND cout 1k
+R1 sum GND 1k
+R2 cout GND 1k
.end
diff --git a/Examples/Half_Adder/Half_Adder.cir.out b/Examples/Half_Adder/Half_Adder.cir.out
index 5d7165f1..26968c36 100644
--- a/Examples/Half_Adder/Half_Adder.cir.out
+++ b/Examples/Half_Adder/Half_Adder.cir.out
@@ -1,15 +1,15 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015
+* /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir
.include half_adder.sub
-x1 1 2 3 4 half_adder
-* u1 a b 1 2 adc_bridge_2
-* u2 3 4 sum cout dac_bridge_2
+x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
+* u1 a b net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+* u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
v1 a gnd dc 5
v2 b gnd dc 0
-r1 gnd sum 1k
-r2 gnd cout 1k
-a1 [a b ] [1 2 ] u1
-a2 [3 4 ] [sum cout ] u2
+r1 sum gnd 1k
+r2 cout gnd 1k
+a1 [a b ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
diff --git a/Examples/Half_Adder/Half_Adder.pro b/Examples/Half_Adder/Half_Adder.pro
index 7d91e5b9..a1d14873 100644
--- a/Examples/Half_Adder/Half_Adder.pro
+++ b/Examples/Half_Adder/Half_Adder.pro
@@ -1,4 +1,4 @@
-update=Wed Jul 1 11:26:18 2015
+update=Wed Aug 19 14:41:14 2015
version=1
last_client=eeschema
[general]
@@ -31,40 +31,42 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
-LibName1=Half_Adder-rescue
-LibName2=power
-LibName3=device
-LibName4=transistors
-LibName5=conn
-LibName6=linear
-LibName7=regul
-LibName8=74xx
-LibName9=cmos4000
-LibName10=adc-dac
-LibName11=memory
-LibName12=xilinx
-LibName13=special
-LibName14=microcontrollers
-LibName15=dsp
-LibName16=microchip
-LibName17=analog_switches
-LibName18=motorola
-LibName19=texas
-LibName20=intel
-LibName21=audio
-LibName22=interface
-LibName23=digital-audio
-LibName24=philips
-LibName25=display
-LibName26=cypress
-LibName27=siliconi
-LibName28=opto
-LibName29=atmel
-LibName30=contrib
-LibName31=valves
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName37=/home/gaurav/Desktop/eSim Library/eSim_Subckt
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Sources
+LibName7=eSim_Subckt
+LibName8=eSim_User
+LibName9=Half_Adder-rescue
+LibName10=power
+LibName11=device
+LibName12=transistors
+LibName13=conn
+LibName14=linear
+LibName15=regul
+LibName16=74xx
+LibName17=cmos4000
+LibName18=adc-dac
+LibName19=memory
+LibName20=xilinx
+LibName21=special
+LibName22=microcontrollers
+LibName23=dsp
+LibName24=microchip
+LibName25=analog_switches
+LibName26=motorola
+LibName27=texas
+LibName28=intel
+LibName29=audio
+LibName30=interface
+LibName31=digital-audio
+LibName32=philips
+LibName33=display
+LibName34=cypress
+LibName35=siliconi
+LibName36=opto
+LibName37=atmel
+LibName38=contrib
+LibName39=valves
diff --git a/Examples/Half_Adder/Half_Adder.sch b/Examples/Half_Adder/Half_Adder.sch
index d291f9cc..a40cbbbd 100644
--- a/Examples/Half_Adder/Half_Adder.sch
+++ b/Examples/Half_Adder/Half_Adder.sch
@@ -1,4 +1,13 @@
EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:Half_Adder-rescue
LIBS:power
LIBS:device
LIBS:transistors
@@ -10,7 +19,6 @@ LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
-LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
@@ -29,12 +37,6 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
LIBS:Half_Adder-cache
EELAYER 25 0
EELAYER END
@@ -106,7 +108,7 @@ F 3 "" H 3450 3800 60 0000 C CNN
0 1 1 0
$EndComp
$Comp
-L GND #PWR01
+L GND-RESCUE-Half_Adder #PWR01
U 1 1 558A93BB
P 2950 4000
F 0 "#PWR01" H 2950 4000 30 0001 C CNN
@@ -117,7 +119,7 @@ F 3 "" H 2950 4000 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L GND #PWR02
+L GND-RESCUE-Half_Adder #PWR02
U 1 1 558A93D7
P 2950 3250
F 0 "#PWR02" H 2950 3250 30 0001 C CNN
@@ -128,29 +130,7 @@ F 3 "" H 2950 3250 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
-L R R1
-U 1 1 558A940C
-P 7850 3300
-F 0 "R1" V 7930 3300 50 0000 C CNN
-F 1 "1k" V 7850 3300 50 0000 C CNN
-F 2 "" V 7780 3300 30 0000 C CNN
-F 3 "" H 7850 3300 30 0000 C CNN
- 1 7850 3300
- 0 1 1 0
-$EndComp
-$Comp
-L R R2
-U 1 1 558A945B
-P 7850 3550
-F 0 "R2" V 7930 3550 50 0000 C CNN
-F 1 "1k" V 7850 3550 50 0000 C CNN
-F 2 "" V 7780 3550 30 0000 C CNN
-F 3 "" H 7850 3550 30 0000 C CNN
- 1 7850 3550
- 0 1 1 0
-$EndComp
-$Comp
-L GND #PWR03
+L GND-RESCUE-Half_Adder #PWR03
U 1 1 558A9480
P 8350 3650
F 0 "#PWR03" H 8350 3650 30 0001 C CNN
@@ -237,14 +217,6 @@ Text GLabel 4050 3150 2 60 Input ~ 0
A
Text GLabel 4100 3750 2 60 Input ~ 0
B
-Text GLabel 5200 3250 0 60 Input ~ 0
-1
-Text GLabel 5200 3700 0 60 Input ~ 0
-2
-Text GLabel 6550 3250 2 60 Input ~ 0
-3
-Text GLabel 6550 3650 2 60 Input ~ 0
-4
Wire Wire Line
4050 3150 4050 3250
Wire Wire Line
@@ -254,20 +226,6 @@ Wire Wire Line
4100 3750 3950 3750
Connection ~ 3950 3750
Wire Wire Line
- 5200 3700 5300 3700
-Connection ~ 5300 3700
-Wire Wire Line
- 5200 3250 5250 3250
-Wire Wire Line
- 5250 3250 5250 3450
-Connection ~ 5250 3450
-Wire Wire Line
- 6550 3250 6450 3250
-Connection ~ 6450 3250
-Wire Wire Line
- 6550 3650 6450 3650
-Connection ~ 6450 3650
-Wire Wire Line
7600 3750 7650 3750
Wire Wire Line
7650 3750 7650 3550
@@ -277,4 +235,26 @@ Wire Wire Line
Wire Wire Line
7650 3150 7650 3300
Connection ~ 7650 3300
+$Comp
+L R R1
+U 1 1 55D44B20
+P 7800 3350
+F 0 "R1" H 7850 3480 50 0000 C CNN
+F 1 "1k" H 7850 3400 50 0000 C CNN
+F 2 "" H 7850 3330 30 0000 C CNN
+F 3 "" V 7850 3400 30 0000 C CNN
+ 1 7800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L R R2
+U 1 1 55D44B67
+P 7800 3600
+F 0 "R2" H 7850 3730 50 0000 C CNN
+F 1 "1k" H 7850 3650 50 0000 C CNN
+F 2 "" H 7850 3580 30 0000 C CNN
+F 3 "" V 7850 3650 30 0000 C CNN
+ 1 7800 3600
+ 1 0 0 -1
+$EndComp
$EndSCHEMATC
diff --git a/Examples/Half_Adder/Half_Adder_Previous_Values.xml b/Examples/Half_Adder/Half_Adder_Previous_Values.xml
index 8622e049..45cec8d6 100644
--- a/Examples/Half_Adder/Half_Adder_Previous_Values.xml
+++ b/Examples/Half_Adder/Half_Adder_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><subcircuit><x1><field>/opt/eSim/src/SubcircuitLibrary/half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/Examples/Half_Adder/_saved_half_adder.sch b/Examples/Half_Adder/_saved_half_adder.sch
new file mode 100644
index 00000000..d66359c5
--- /dev/null
+++ b/Examples/Half_Adder/_saved_half_adder.sch
@@ -0,0 +1,154 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:half_adder-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U2
+U 1 1 558A946A
+P 5650 3050
+F 0 "U2" H 5650 3050 60 0000 C CNN
+F 1 "d_xor" H 5700 3150 47 0000 C CNN
+F 2 "" H 5650 3050 60 0000 C CNN
+F 3 "" H 5650 3050 60 0000 C CNN
+ 1 5650 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 558A94D5
+P 5700 3800
+F 0 "U3" H 5700 3800 60 0000 C CNN
+F 1 "d_and" H 5750 3900 60 0000 C CNN
+F 2 "" H 5700 3800 60 0000 C CNN
+F 3 "" H 5700 3800 60 0000 C CNN
+ 1 5700 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 558A94F6
+P 4150 3000
+F 0 "U1" H 4200 3100 30 0000 C CNN
+F 1 "PORT" H 4150 3000 30 0000 C CNN
+F 2 "" H 4150 3000 60 0000 C CNN
+F 3 "" H 4150 3000 60 0000 C CNN
+ 1 4150 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 558A9543
+P 4150 3450
+F 0 "U1" H 4200 3550 30 0000 C CNN
+F 1 "PORT" H 4150 3450 30 0000 C CNN
+F 2 "" H 4150 3450 60 0000 C CNN
+F 3 "" H 4150 3450 60 0000 C CNN
+ 2 4150 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 558A9573
+P 6650 3000
+F 0 "U1" H 6700 3100 30 0000 C CNN
+F 1 "PORT" H 6650 3000 30 0000 C CNN
+F 2 "" H 6650 3000 60 0000 C CNN
+F 3 "" H 6650 3000 60 0000 C CNN
+ 3 6650 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 558A9606
+P 6700 3750
+F 0 "U1" H 6750 3850 30 0000 C CNN
+F 1 "PORT" H 6700 3750 30 0000 C CNN
+F 2 "" H 6700 3750 60 0000 C CNN
+F 3 "" H 6700 3750 60 0000 C CNN
+ 4 6700 3750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 5200 2950 4450 2950
+Wire Wire Line
+ 4450 2950 4450 3000
+Wire Wire Line
+ 4450 3000 4400 3000
+Wire Wire Line
+ 4400 3450 4550 3450
+Wire Wire Line
+ 4550 3450 4550 3050
+Wire Wire Line
+ 4550 3050 5200 3050
+Wire Wire Line
+ 5250 3700 5000 3700
+Wire Wire Line
+ 5000 3700 5000 2950
+Connection ~ 5000 2950
+Wire Wire Line
+ 5250 3800 4850 3800
+Wire Wire Line
+ 4850 3800 4850 3050
+Connection ~ 4850 3050
+Wire Wire Line
+ 6100 3000 6400 3000
+Wire Wire Line
+ 6150 3750 6450 3750
+Text Notes 4550 2950 0 60 ~ 0
+IN1\n\n
+Text Notes 4600 3150 0 60 ~ 0
+IN2
+Text Notes 6200 2950 0 60 ~ 0
+SUM\n
+Text Notes 6200 3650 0 60 ~ 0
+COUT\n
+$EndSCHEMATC
diff --git a/Examples/Half_Adder/half_adder-cache.lib b/Examples/Half_Adder/half_adder-cache.lib
index 68785220..68785220 100644..100755
--- a/Examples/Half_Adder/half_adder-cache.lib
+++ b/Examples/Half_Adder/half_adder-cache.lib
diff --git a/Examples/Half_Adder/half_adder.bak b/Examples/Half_Adder/half_adder.bak
new file mode 100755
index 00000000..bf9bcbf0
--- /dev/null
+++ b/Examples/Half_Adder/half_adder.bak
@@ -0,0 +1,152 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U2
+U 1 1 558A946A
+P 5650 3050
+F 0 "U2" H 5650 3050 60 0000 C CNN
+F 1 "d_xor" H 5700 3150 47 0000 C CNN
+F 2 "" H 5650 3050 60 0000 C CNN
+F 3 "" H 5650 3050 60 0000 C CNN
+ 1 5650 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 558A94D5
+P 5700 3800
+F 0 "U3" H 5700 3800 60 0000 C CNN
+F 1 "d_and" H 5750 3900 60 0000 C CNN
+F 2 "" H 5700 3800 60 0000 C CNN
+F 3 "" H 5700 3800 60 0000 C CNN
+ 1 5700 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 558A94F6
+P 4150 3000
+F 0 "U1" H 4200 3100 30 0000 C CNN
+F 1 "PORT" H 4150 3000 30 0000 C CNN
+F 2 "" H 4150 3000 60 0000 C CNN
+F 3 "" H 4150 3000 60 0000 C CNN
+ 1 4150 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 558A9543
+P 4150 3450
+F 0 "U1" H 4200 3550 30 0000 C CNN
+F 1 "PORT" H 4150 3450 30 0000 C CNN
+F 2 "" H 4150 3450 60 0000 C CNN
+F 3 "" H 4150 3450 60 0000 C CNN
+ 2 4150 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 558A9573
+P 6650 3000
+F 0 "U1" H 6700 3100 30 0000 C CNN
+F 1 "PORT" H 6650 3000 30 0000 C CNN
+F 2 "" H 6650 3000 60 0000 C CNN
+F 3 "" H 6650 3000 60 0000 C CNN
+ 3 6650 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 558A9606
+P 6700 3750
+F 0 "U1" H 6750 3850 30 0000 C CNN
+F 1 "PORT" H 6700 3750 30 0000 C CNN
+F 2 "" H 6700 3750 60 0000 C CNN
+F 3 "" H 6700 3750 60 0000 C CNN
+ 4 6700 3750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 5200 2950 4450 2950
+Wire Wire Line
+ 4450 2950 4450 3000
+Wire Wire Line
+ 4450 3000 4400 3000
+Wire Wire Line
+ 4400 3450 4550 3450
+Wire Wire Line
+ 4550 3450 4550 3050
+Wire Wire Line
+ 4550 3050 5200 3050
+Wire Wire Line
+ 5250 3700 5000 3700
+Wire Wire Line
+ 5000 3700 5000 2950
+Connection ~ 5000 2950
+Wire Wire Line
+ 5250 3800 4850 3800
+Wire Wire Line
+ 4850 3800 4850 3050
+Connection ~ 4850 3050
+Wire Wire Line
+ 6100 3000 6400 3000
+Wire Wire Line
+ 6150 3750 6450 3750
+Text Notes 4550 2950 0 60 ~ 0
+IN1\n\n
+Text Notes 4600 3150 0 60 ~ 0
+IN2
+Text Notes 6200 2950 0 60 ~ 0
+SUM\n
+Text Notes 6200 3650 0 60 ~ 0
+COUT\n
+$EndSCHEMATC
diff --git a/Examples/Half_Adder/half_adder.cir b/Examples/Half_Adder/half_adder.cir
index 8b2e7e06..8b2e7e06 100644..100755
--- a/Examples/Half_Adder/half_adder.cir
+++ b/Examples/Half_Adder/half_adder.cir
diff --git a/Examples/Half_Adder/half_adder.cir.out b/Examples/Half_Adder/half_adder.cir.out
index b1b6b1e7..b1b6b1e7 100644..100755
--- a/Examples/Half_Adder/half_adder.cir.out
+++ b/Examples/Half_Adder/half_adder.cir.out
diff --git a/Examples/Half_Adder/half_adder.pro b/Examples/Half_Adder/half_adder.pro
index 695ae0f6..aebb8b7e 100644..100755
--- a/Examples/Half_Adder/half_adder.pro
+++ b/Examples/Half_Adder/half_adder.pro
@@ -1,4 +1,4 @@
-update=Wed Jun 24 11:27:22 2015
+update=Tue Aug 18 14:39:23 2015
version=1
last_client=eeschema
[general]
@@ -31,39 +31,41 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
-LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
-LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
-LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
-LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
-LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Sources
+LibName7=eSim_Subckt
+LibName8=eSim_User
+LibName9=power
+LibName10=device
+LibName11=transistors
+LibName12=conn
+LibName13=linear
+LibName14=regul
+LibName15=74xx
+LibName16=cmos4000
+LibName17=adc-dac
+LibName18=memory
+LibName19=xilinx
+LibName20=special
+LibName21=microcontrollers
+LibName22=dsp
+LibName23=microchip
+LibName24=analog_switches
+LibName25=motorola
+LibName26=texas
+LibName27=intel
+LibName28=audio
+LibName29=interface
+LibName30=digital-audio
+LibName31=philips
+LibName32=display
+LibName33=cypress
+LibName34=siliconi
+LibName35=opto
+LibName36=atmel
+LibName37=contrib
+LibName38=valves
diff --git a/Examples/Half_Adder/half_adder.sch b/Examples/Half_Adder/half_adder.sch
index bf9bcbf0..d66359c5 100644
--- a/Examples/Half_Adder/half_adder.sch
+++ b/Examples/Half_Adder/half_adder.sch
@@ -1,4 +1,12 @@
EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
LIBS:power
LIBS:device
LIBS:transistors
@@ -10,7 +18,6 @@ LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
-LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
@@ -29,12 +36,7 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
+LIBS:half_adder-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
diff --git a/Examples/Half_Adder/half_adder.sub b/Examples/Half_Adder/half_adder.sub
index e9f92223..e9f92223 100644..100755
--- a/Examples/Half_Adder/half_adder.sub
+++ b/Examples/Half_Adder/half_adder.sub
diff --git a/Examples/Half_Adder/half_adder_Previous_Values.xml b/Examples/Half_Adder/half_adder_Previous_Values.xml
index b915f0da..d1f05f93 100644..100755
--- a/Examples/Half_Adder/half_adder_Previous_Values.xml
+++ b/Examples/Half_Adder/half_adder_Previous_Values.xml
@@ -1 +1 @@
-<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice> \ No newline at end of file
+<KicadtoNgspice><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">GHz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/Examples/Half_Adder/plot_data_i.txt b/Examples/Half_Adder/plot_data_i.txt
index b212bde0..3a0df31d 100644
--- a/Examples/Half_Adder/plot_data_i.txt
+++ b/Examples/Half_Adder/plot_data_i.txt
@@ -1,5 +1,5 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015
-Transient Analysis Wed Jul 1 11:38:38 2015
+ * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir
+ Transient Analysis Wed Aug 19 15:40:43 2015
--------------------------------------------------------------------------------
Index time a2#branch_1_0 a2#branch_1_1 v1#branch
--------------------------------------------------------------------------------
@@ -66,8 +66,8 @@ Index time a2#branch_1_0 a2#branch_1_1 v1#branch
57 9.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00
58 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015
-Transient Analysis Wed Jul 1 11:38:38 2015
+ * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir
+ Transient Analysis Wed Aug 19 15:40:43 2015
--------------------------------------------------------------------------------
Index time v2#branch
--------------------------------------------------------------------------------
diff --git a/Examples/Half_Adder/plot_data_v.txt b/Examples/Half_Adder/plot_data_v.txt
index 89095baa..d612ba01 100644
--- a/Examples/Half_Adder/plot_data_v.txt
+++ b/Examples/Half_Adder/plot_data_v.txt
@@ -1,5 +1,5 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015
-Transient Analysis Wed Jul 1 11:38:38 2015
+ * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir
+ Transient Analysis Wed Aug 19 15:40:43 2015
--------------------------------------------------------------------------------
Index time a b cout
--------------------------------------------------------------------------------
@@ -66,8 +66,8 @@ Index time a b cout
57 9.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00
58 1.000000e-01 5.000000e+00 0.000000e+00 0.000000e+00
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 15:44:17 2015
-Transient Analysis Wed Jul 1 11:38:38 2015
+ * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir
+ Transient Analysis Wed Aug 19 15:40:43 2015
--------------------------------------------------------------------------------
Index time sum
--------------------------------------------------------------------------------
generated by cgit (git 2.34.1) at 2024-12-22 11:15:16 +0000