diff options
Diffstat (limited to 'Examples/Half_Adder')
| -rw-r--r-- | Examples/Half_Adder/Half_Adder-cache.lib | 19 | ||||
| -rw-r--r-- | Examples/Half_Adder/Half_Adder.bak | 44 | ||||
| -rw-r--r-- | Examples/Half_Adder/Half_Adder.cir | 14 | ||||
| -rw-r--r-- | Examples/Half_Adder/Half_Adder.cir.out | 18 | ||||
| -rw-r--r-- | Examples/Half_Adder/Half_Adder.pro | 72 | ||||
| -rw-r--r-- | Examples/Half_Adder/Half_Adder.sch | 141 | ||||
| -rw-r--r-- | Examples/Half_Adder/Half_Adder_Previous_Values.xml | 2 | ||||
| -rw-r--r--[-rwxr-xr-x] | Examples/Half_Adder/half_adder-cache.lib | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | Examples/Half_Adder/half_adder.cir | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | Examples/Half_Adder/half_adder.cir.out | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | Examples/Half_Adder/half_adder.pro | 76 | ||||
| -rw-r--r-- | Examples/Half_Adder/half_adder.sch | 16 | ||||
| -rw-r--r--[-rwxr-xr-x] | Examples/Half_Adder/half_adder.sub | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | Examples/Half_Adder/half_adder_Previous_Values.xml | 2 | ||||
| -rw-r--r-- | Examples/Half_Adder/plot_data_i.txt | 8 | ||||
| -rw-r--r-- | Examples/Half_Adder/plot_data_v.txt | 130 |
16 files changed, 309 insertions, 233 deletions
diff --git a/Examples/Half_Adder/Half_Adder-cache.lib b/Examples/Half_Adder/Half_Adder-cache.lib index 6fec114a..fb78fe0e 100644 --- a/Examples/Half_Adder/Half_Adder-cache.lib +++ b/Examples/Half_Adder/Half_Adder-cache.lib @@ -36,10 +36,10 @@ ENDDEF DEF PWR_FLAG #FLG 0 0 N N 1 F P F0 "#FLG" 0 95 50 H I C CNN F1 "PWR_FLAG" 0 180 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN DRAW -X pwr 1 0 0 0 U 20 20 0 0 w +X pwr 1 0 0 0 U 50 50 0 0 w P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N ENDDRAW ENDDEF @@ -110,4 +110,17 @@ X COUT 4 1450 100 200 L 50 50 1 1 O ENDDRAW ENDDEF # +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# #End Library diff --git a/Examples/Half_Adder/Half_Adder.bak b/Examples/Half_Adder/Half_Adder.bak index 21c1e742..a40cbbbd 100644 --- a/Examples/Half_Adder/Half_Adder.bak +++ b/Examples/Half_Adder/Half_Adder.bak @@ -130,28 +130,6 @@ F 3 "" H 2950 3250 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L R R1 -U 1 1 558A940C -P 7850 3300 -F 0 "R1" V 7930 3300 50 0000 C CNN -F 1 "1k" V 7850 3300 50 0000 C CNN -F 2 "" V 7780 3300 30 0000 C CNN -F 3 "" H 7850 3300 30 0000 C CNN - 1 7850 3300 - 0 1 1 0 -$EndComp -$Comp -L R R2 -U 1 1 558A945B -P 7850 3550 -F 0 "R2" V 7930 3550 50 0000 C CNN -F 1 "1k" V 7850 3550 50 0000 C CNN -F 2 "" V 7780 3550 30 0000 C CNN -F 3 "" H 7850 3550 30 0000 C CNN - 1 7850 3550 - 0 1 1 0 -$EndComp -$Comp L GND-RESCUE-Half_Adder #PWR03 U 1 1 558A9480 P 8350 3650 @@ -257,4 +235,26 @@ Wire Wire Line Wire Wire Line 7650 3150 7650 3300 Connection ~ 7650 3300 +$Comp +L R R1 +U 1 1 55D44B20 +P 7800 3350 +F 0 "R1" H 7850 3480 50 0000 C CNN +F 1 "1k" H 7850 3400 50 0000 C CNN +F 2 "" H 7850 3330 30 0000 C CNN +F 3 "" V 7850 3400 30 0000 C CNN + 1 7800 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 55D44B67 +P 7800 3600 +F 0 "R2" H 7850 3730 50 0000 C CNN +F 1 "1k" H 7850 3650 50 0000 C CNN +F 2 "" H 7850 3580 30 0000 C CNN +F 3 "" V 7850 3650 30 0000 C CNN + 1 7800 3600 + 1 0 0 -1 +$EndComp $EndSCHEMATC diff --git a/Examples/Half_Adder/Half_Adder.cir b/Examples/Half_Adder/Half_Adder.cir index c12e1d5e..4658c5cb 100644 --- a/Examples/Half_Adder/Half_Adder.cir +++ b/Examples/Half_Adder/Half_Adder.cir @@ -1,17 +1,21 @@ -* /home/fossee/Downloads/eSim-master/Examples/Half_Adder/Half_Adder.cir +* /home/fossee/UpdatedExamples/Half_Adder/Half_Adder.cir -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Aug 19 15:02:03 2015 +* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar 3 21:35:33 2016 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 * Sheet Name: / X1 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder -U1 A B Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2 +U1 IN1 IN2 Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2 U2 Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2 -v1 A GND DC -v2 B GND DC +v1 IN1 GND DC +v2 IN2 GND DC R1 sum GND 1k R2 cout GND 1k +U3 IN1 plot_v1 +U4 IN2 plot_v1 +U5 sum plot_v1 +U6 cout plot_v1 .end diff --git a/Examples/Half_Adder/Half_Adder.cir.out b/Examples/Half_Adder/Half_Adder.cir.out index 26968c36..96066fff 100644 --- a/Examples/Half_Adder/Half_Adder.cir.out +++ b/Examples/Half_Adder/Half_Adder.cir.out @@ -1,14 +1,18 @@ -* /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir +* /home/fossee/updatedexamples/half_adder/half_adder.cir .include half_adder.sub x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder -* u1 a b net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2 +* u1 in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2 * u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2 -v1 a gnd dc 5 -v2 b gnd dc 0 +v1 in1 gnd dc 5 +v2 in2 gnd dc 0 r1 sum gnd 1k r2 cout gnd 1k -a1 [a b ] [net-_u1-pad3_ net-_u1-pad4_ ] u1 +* u3 in1 plot_v1 +* u4 in2 plot_v1 +* u5 sum plot_v1 +* u6 cout plot_v1 +a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1 a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2 * Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge .model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) @@ -21,5 +25,9 @@ a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2 run print allv > plot_data_v.txt print alli > plot_data_i.txt +plot v(in1) +plot v(in2) +plot v(sum) +plot v(cout) .endc .end diff --git a/Examples/Half_Adder/Half_Adder.pro b/Examples/Half_Adder/Half_Adder.pro index a1d14873..ed30ac59 100644 --- a/Examples/Half_Adder/Half_Adder.pro +++ b/Examples/Half_Adder/Half_Adder.pro @@ -1,4 +1,4 @@ -update=Wed Aug 19 14:41:14 2015 +update=Thu Mar 3 21:34:08 2016 version=1 last_client=eeschema [general] @@ -36,37 +36,39 @@ LibName2=eSim_Devices LibName3=eSim_Digital LibName4=eSim_Hybrid LibName5=eSim_Miscellaneous -LibName6=eSim_Sources -LibName7=eSim_Subckt -LibName8=eSim_User -LibName9=Half_Adder-rescue -LibName10=power -LibName11=device -LibName12=transistors -LibName13=conn -LibName14=linear -LibName15=regul -LibName16=74xx -LibName17=cmos4000 -LibName18=adc-dac -LibName19=memory -LibName20=xilinx -LibName21=special -LibName22=microcontrollers -LibName23=dsp -LibName24=microchip -LibName25=analog_switches -LibName26=motorola -LibName27=texas -LibName28=intel -LibName29=audio -LibName30=interface -LibName31=digital-audio -LibName32=philips -LibName33=display -LibName34=cypress -LibName35=siliconi -LibName36=opto -LibName37=atmel -LibName38=contrib -LibName39=valves +LibName6=eSim_Plot +LibName7=eSim_Sources +LibName8=eSim_Subckt +LibName9=eSim_User +LibName10=Half_Adder-rescue +LibName11=power +LibName12=device +LibName13=transistors +LibName14=conn +LibName15=linear +LibName16=regul +LibName17=74xx +LibName18=cmos4000 +LibName19=adc-dac +LibName20=memory +LibName21=xilinx +LibName22=special +LibName23=microcontrollers +LibName24=dsp +LibName25=microchip +LibName26=analog_switches +LibName27=motorola +LibName28=texas +LibName29=intel +LibName30=audio +LibName31=interface +LibName32=digital-audio +LibName33=philips +LibName34=display +LibName35=cypress +LibName36=siliconi +LibName37=opto +LibName38=atmel +LibName39=contrib +LibName40=valves +LibName41=eSim_Power diff --git a/Examples/Half_Adder/Half_Adder.sch b/Examples/Half_Adder/Half_Adder.sch index a40cbbbd..fa25e435 100644 --- a/Examples/Half_Adder/Half_Adder.sch +++ b/Examples/Half_Adder/Half_Adder.sch @@ -4,6 +4,7 @@ LIBS:eSim_Devices LIBS:eSim_Digital LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous +LIBS:eSim_Plot LIBS:eSim_Sources LIBS:eSim_Subckt LIBS:eSim_User @@ -37,6 +38,7 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves +LIBS:eSim_Power LIBS:Half_Adder-cache EELAYER 25 0 EELAYER END @@ -140,6 +142,91 @@ F 3 "" H 8350 3650 60 0000 C CNN 1 8350 3650 1 0 0 -1 $EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 558A96D4 +P 2850 3850 +F 0 "#FLG04" H 2850 3945 50 0001 C CNN +F 1 "PWR_FLAG" H 2850 4030 50 0000 C CNN +F 2 "" H 2850 3850 60 0000 C CNN +F 3 "" H 2850 3850 60 0000 C CNN + 1 2850 3850 + 1 0 0 -1 +$EndComp +Text GLabel 7600 3150 0 60 Input ~ 0 +sum +Text GLabel 7600 3750 0 60 Input ~ 0 +cout +Text GLabel 4050 3150 2 60 Input ~ 0 +IN1 +Text GLabel 4100 3750 2 60 Input ~ 0 +IN2 +$Comp +L R R1 +U 1 1 55D44B20 +P 7800 3350 +F 0 "R1" H 7850 3480 50 0000 C CNN +F 1 "1k" H 7850 3400 50 0000 C CNN +F 2 "" H 7850 3330 30 0000 C CNN +F 3 "" V 7850 3400 30 0000 C CNN + 1 7800 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 55D44B67 +P 7800 3600 +F 0 "R2" H 7850 3730 50 0000 C CNN +F 1 "1k" H 7850 3650 50 0000 C CNN +F 2 "" H 7850 3580 30 0000 C CNN +F 3 "" V 7850 3650 30 0000 C CNN + 1 7800 3600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 56D860CB +P 3900 3300 +F 0 "U3" H 3900 3800 60 0000 C CNN +F 1 "plot_v1" H 4100 3650 60 0000 C CNN +F 2 "" H 3900 3300 60 0000 C CNN +F 3 "" H 3900 3300 60 0000 C CNN + 1 3900 3300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 56D8619C +P 3900 3750 +F 0 "U4" H 3900 4250 60 0000 C CNN +F 1 "plot_v1" H 4100 4100 60 0000 C CNN +F 2 "" H 3900 3750 60 0000 C CNN +F 3 "" H 3900 3750 60 0000 C CNN + 1 3900 3750 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 56D8629D +P 7650 3250 +F 0 "U5" H 7650 3750 60 0000 C CNN +F 1 "plot_v1" H 7850 3600 60 0000 C CNN +F 2 "" H 7650 3250 60 0000 C CNN +F 3 "" H 7650 3250 60 0000 C CNN + 1 7650 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 56D86375 +P 7650 3650 +F 0 "U6" H 7650 4150 60 0000 C CNN +F 1 "plot_v1" H 7850 4000 60 0000 C CNN +F 2 "" H 7650 3650 60 0000 C CNN +F 3 "" H 7650 3650 60 0000 C CNN + 1 7650 3650 + -1 0 0 1 +$EndComp Wire Wire Line 3000 3150 2950 3150 Wire Wire Line @@ -153,7 +240,7 @@ Wire Wire Line Wire Wire Line 3950 3800 3950 3550 Wire Wire Line - 3950 3450 3950 3150 + 3950 3100 3950 3450 Wire Wire Line 3950 3150 3900 3150 Wire Wire Line @@ -193,30 +280,11 @@ Wire Wire Line Wire Wire Line 8350 3550 8350 3500 Connection ~ 8350 3500 -$Comp -L PWR_FLAG #FLG04 -U 1 1 558A96D4 -P 2850 3850 -F 0 "#FLG04" H 2850 3945 50 0001 C CNN -F 1 "PWR_FLAG" H 2850 4030 50 0000 C CNN -F 2 "" H 2850 3850 60 0000 C CNN -F 3 "" H 2850 3850 60 0000 C CNN - 1 2850 3850 - 1 0 0 -1 -$EndComp Wire Wire Line 2850 3850 2850 3900 Wire Wire Line 2850 3900 2950 3900 Connection ~ 2950 3900 -Text GLabel 7600 3150 0 60 Input ~ 0 -sum -Text GLabel 7600 3750 0 60 Input ~ 0 -cout -Text GLabel 4050 3150 2 60 Input ~ 0 -A -Text GLabel 4100 3750 2 60 Input ~ 0 -B Wire Wire Line 4050 3150 4050 3250 Wire Wire Line @@ -228,33 +296,18 @@ Connection ~ 3950 3750 Wire Wire Line 7600 3750 7650 3750 Wire Wire Line - 7650 3750 7650 3550 + 7650 3550 7650 3850 Connection ~ 7650 3550 Wire Wire Line 7600 3150 7650 3150 Wire Wire Line - 7650 3150 7650 3300 + 7650 3050 7650 3300 Connection ~ 7650 3300 -$Comp -L R R1 -U 1 1 55D44B20 -P 7800 3350 -F 0 "R1" H 7850 3480 50 0000 C CNN -F 1 "1k" H 7850 3400 50 0000 C CNN -F 2 "" H 7850 3330 30 0000 C CNN -F 3 "" V 7850 3400 30 0000 C CNN - 1 7800 3350 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 55D44B67 -P 7800 3600 -F 0 "R2" H 7850 3730 50 0000 C CNN -F 1 "1k" H 7850 3650 50 0000 C CNN -F 2 "" H 7850 3580 30 0000 C CNN -F 3 "" V 7850 3650 30 0000 C CNN - 1 7800 3600 - 1 0 0 -1 -$EndComp +Connection ~ 7650 3750 +Connection ~ 7650 3150 +Wire Wire Line + 3950 3100 3900 3100 +Connection ~ 3950 3150 +Wire Wire Line + 3900 3950 3900 3800 $EndSCHEMATC diff --git a/Examples/Half_Adder/Half_Adder_Previous_Values.xml b/Examples/Half_Adder/Half_Adder_Previous_Values.xml index 45cec8d6..ca482668 100644 --- a/Examples/Half_Adder/Half_Adder_Previous_Values.xml +++ b/Examples/Half_Adder/Half_Adder_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><subcircuit><x1><field>/opt/eSim/src/SubcircuitLibrary/half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/fossee/esim-updated/eSim/src/SubcircuitLibrary/half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Half_Adder/half_adder-cache.lib b/Examples/Half_Adder/half_adder-cache.lib index 68785220..68785220 100755..100644 --- a/Examples/Half_Adder/half_adder-cache.lib +++ b/Examples/Half_Adder/half_adder-cache.lib diff --git a/Examples/Half_Adder/half_adder.cir b/Examples/Half_Adder/half_adder.cir index 8b2e7e06..8b2e7e06 100755..100644 --- a/Examples/Half_Adder/half_adder.cir +++ b/Examples/Half_Adder/half_adder.cir diff --git a/Examples/Half_Adder/half_adder.cir.out b/Examples/Half_Adder/half_adder.cir.out index b1b6b1e7..b1b6b1e7 100755..100644 --- a/Examples/Half_Adder/half_adder.cir.out +++ b/Examples/Half_Adder/half_adder.cir.out diff --git a/Examples/Half_Adder/half_adder.pro b/Examples/Half_Adder/half_adder.pro index aebb8b7e..695ae0f6 100755..100644 --- a/Examples/Half_Adder/half_adder.pro +++ b/Examples/Half_Adder/half_adder.pro @@ -1,4 +1,4 @@ -update=Tue Aug 18 14:39:23 2015 +update=Wed Jun 24 11:27:22 2015 version=1 last_client=eeschema [general] @@ -31,41 +31,39 @@ NetIExt=net version=1 LibDir= [eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Sources -LibName7=eSim_Subckt -LibName8=eSim_User -LibName9=power -LibName10=device -LibName11=transistors -LibName12=conn -LibName13=linear -LibName14=regul -LibName15=74xx -LibName16=cmos4000 -LibName17=adc-dac -LibName18=memory -LibName19=xilinx -LibName20=special -LibName21=microcontrollers -LibName22=dsp -LibName23=microchip -LibName24=analog_switches -LibName25=motorola -LibName26=texas -LibName27=intel -LibName28=audio -LibName29=interface -LibName30=digital-audio -LibName31=philips -LibName32=display -LibName33=cypress -LibName34=siliconi -LibName35=opto -LibName36=atmel -LibName37=contrib -LibName38=valves +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/Half_Adder/half_adder.sch b/Examples/Half_Adder/half_adder.sch index d66359c5..bf9bcbf0 100644 --- a/Examples/Half_Adder/half_adder.sch +++ b/Examples/Half_Adder/half_adder.sch @@ -1,12 +1,4 @@ EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User LIBS:power LIBS:device LIBS:transistors @@ -18,6 +10,7 @@ LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx +LIBS:special LIBS:microcontrollers LIBS:dsp LIBS:microchip @@ -36,7 +29,12 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves -LIBS:half_adder-cache +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt EELAYER 25 0 EELAYER END $Descr A4 11693 8268 diff --git a/Examples/Half_Adder/half_adder.sub b/Examples/Half_Adder/half_adder.sub index e9f92223..e9f92223 100755..100644 --- a/Examples/Half_Adder/half_adder.sub +++ b/Examples/Half_Adder/half_adder.sub diff --git a/Examples/Half_Adder/half_adder_Previous_Values.xml b/Examples/Half_Adder/half_adder_Previous_Values.xml index d1f05f93..b915f0da 100755..100644 --- a/Examples/Half_Adder/half_adder_Previous_Values.xml +++ b/Examples/Half_Adder/half_adder_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">GHz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Half_Adder/plot_data_i.txt b/Examples/Half_Adder/plot_data_i.txt index 3a0df31d..772acd21 100644 --- a/Examples/Half_Adder/plot_data_i.txt +++ b/Examples/Half_Adder/plot_data_i.txt @@ -1,5 +1,5 @@ - * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir - Transient Analysis Wed Aug 19 15:40:43 2015 + * /home/fossee/updatedexamples/half_adder/half_adder.cir + Transient Analysis Thu Mar 3 21:35:49 2016 -------------------------------------------------------------------------------- Index time a2#branch_1_0 a2#branch_1_1 v1#branch -------------------------------------------------------------------------------- @@ -66,8 +66,8 @@ Index time a2#branch_1_0 a2#branch_1_1 v1#branch 57 9.856000e-02 -5.00000e-03 0.000000e+00 0.000000e+00 58 1.000000e-01 -5.00000e-03 0.000000e+00 0.000000e+00 - * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir - Transient Analysis Wed Aug 19 15:40:43 2015 + * /home/fossee/updatedexamples/half_adder/half_adder.cir + Transient Analysis Thu Mar 3 21:35:49 2016 -------------------------------------------------------------------------------- Index time v2#branch -------------------------------------------------------------------------------- diff --git a/Examples/Half_Adder/plot_data_v.txt b/Examples/Half_Adder/plot_data_v.txt index d612ba01..f970ecba 100644 --- a/Examples/Half_Adder/plot_data_v.txt +++ b/Examples/Half_Adder/plot_data_v.txt @@ -1,73 +1,73 @@ - * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir - Transient Analysis Wed Aug 19 15:40:43 2015 + * /home/fossee/updatedexamples/half_adder/half_adder.cir + Transient Analysis Thu Mar 3 21:35:49 2016 -------------------------------------------------------------------------------- -Index time a b cout +Index time cout in1 in2 -------------------------------------------------------------------------------- -0 0.000000e+00 5.000000e+00 0.000000e+00 0.000000e+00 -1 1.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 -2 2.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 -3 4.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 -4 8.000000e-05 5.000000e+00 0.000000e+00 0.000000e+00 -5 1.600000e-04 5.000000e+00 0.000000e+00 0.000000e+00 -6 3.200000e-04 5.000000e+00 0.000000e+00 0.000000e+00 -7 6.400000e-04 5.000000e+00 0.000000e+00 0.000000e+00 -8 1.280000e-03 5.000000e+00 0.000000e+00 0.000000e+00 -9 2.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 -10 4.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 -11 6.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 -12 8.560000e-03 5.000000e+00 0.000000e+00 0.000000e+00 -13 1.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -14 1.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -15 1.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -16 1.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -17 1.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -18 2.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -19 2.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -20 2.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -21 2.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -22 2.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -23 3.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -24 3.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -25 3.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -26 3.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -27 3.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -28 4.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -29 4.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -30 4.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -31 4.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -32 4.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -33 5.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -34 5.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -35 5.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -36 5.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -37 5.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -38 6.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -39 6.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -40 6.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -41 6.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -42 6.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -43 7.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -44 7.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -45 7.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -46 7.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -47 7.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -48 8.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -49 8.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -50 8.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -51 8.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -52 8.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -53 9.056000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -54 9.256000e-02 5.000000e+00 0.000000e+00 0.000000e+00 +0 0.000000e+00 0.000000e+00 5.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 5.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 5.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 5.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 5.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 5.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 5.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 5.000000e+00 0.000000e+00 -Index time a b cout +Index time cout in1 in2 -------------------------------------------------------------------------------- -55 9.456000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -56 9.656000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -57 9.856000e-02 5.000000e+00 0.000000e+00 0.000000e+00 -58 1.000000e-01 5.000000e+00 0.000000e+00 0.000000e+00 +55 9.456000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 5.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 5.000000e+00 0.000000e+00 - * /home/fossee/downloads/esim-master/examples/half_adder/half_adder.cir - Transient Analysis Wed Aug 19 15:40:43 2015 + * /home/fossee/updatedexamples/half_adder/half_adder.cir + Transient Analysis Thu Mar 3 21:35:49 2016 -------------------------------------------------------------------------------- Index time sum -------------------------------------------------------------------------------- |