15 files changed, 0 insertions, 1122 deletions
diff --git a/Examples/HalfAdder/HalfAdder-cache.lib b/Examples/HalfAdder/HalfAdder-cache.lib
deleted file mode 100644
index e9fd9411..00000000
--- a/Examples/HalfAdder/HalfAdder-cache.lib
+++ /dev/null
@@ -1,126 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# DC
-#
-DEF DC v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "DC" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# GND-RESCUE-HalfAdder
-#
-DEF ~GND-RESCUE-HalfAdder #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND-RESCUE-HalfAdder" 0 -70 30 H I C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
-F3 "" 0 0 50 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 50 50 0 0 w
-P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# adc_bridge_2
-#
-DEF adc_bridge_2 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "adc_bridge_2" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -400 200 350 -100 0 1 0 N
-X IN1 1 -600 50 200 R 50 50 1 1 I
-X IN2 2 -600 -50 200 R 50 50 1 1 I
-X OUT1 3 550 50 200 L 50 50 1 1 O
-X OUT2 4 550 -50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# dac_bridge_2
-#
-DEF dac_bridge_2 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "dac_bridge_2" 50 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -250 200 350 -100 0 1 0 N
-X IN1 1 -450 50 200 R 50 50 1 1 I
-X IN2 2 -450 -50 200 R 50 50 1 1 I
-X OUT1 3 550 50 200 L 50 50 1 1 O
-X OUT4 4 550 -50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# plot_v1
-#
-DEF plot_v1 U 0 40 Y Y 1 F N
-F0 "U" 0 500 60 H V C CNN
-F1 "plot_v1" 200 350 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 500 100 0 1 0 N
-X ~ ~ 0 200 200 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/HalfAdder/HalfAdder-rescue.lib b/Examples/HalfAdder/HalfAdder-rescue.lib
deleted file mode 100644
index 8a92f392..00000000
--- a/Examples/HalfAdder/HalfAdder-rescue.lib
+++ /dev/null
@@ -1,17 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# GND-RESCUE-HalfAdder
-#
-DEF ~GND-RESCUE-HalfAdder #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND-RESCUE-HalfAdder" 0 -70 30 H I C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/HalfAdder/HalfAdder.cir b/Examples/HalfAdder/HalfAdder.cir
deleted file mode 100644
index 51b78f4e..00000000
--- a/Examples/HalfAdder/HalfAdder.cir
+++ /dev/null
@@ -1,21 +0,0 @@
-* /home/fossee/UpdatedExamples/HalfAdder/HalfAdder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar  3 21:35:33 2016
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder		
-U1  IN1 IN2 Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2		
-U2  Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2		
-v1  IN1 GND DC		
-v2  IN2 GND DC		
-R1  sum GND 1k		
-R2  cout GND 1k		
-U3  IN1 plot_v1		
-U4  IN2 plot_v1		
-U5  sum plot_v1		
-U6  cout plot_v1		
-
-.end
diff --git a/Examples/HalfAdder/HalfAdder.cir.out b/Examples/HalfAdder/HalfAdder.cir.out
deleted file mode 100644
index 96066fff..00000000
--- a/Examples/HalfAdder/HalfAdder.cir.out
+++ /dev/null
@@ -1,33 +0,0 @@
-* /home/fossee/updatedexamples/half_adder/half_adder.cir
-
-.include half_adder.sub
-x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
-* u1  in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
-* u2  net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
-v1 in1 gnd  dc 5
-v2 in2 gnd  dc 0
-r1  sum gnd 1k
-r2  cout gnd 1k
-* u3  in1 plot_v1
-* u4  in2 plot_v1
-* u5  sum plot_v1
-* u6  cout plot_v1
-a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
-a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
-* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
-.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
-* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
-.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-plot v(in1)
-plot v(in2)
-plot v(sum)
-plot v(cout)
-.endc
-.end
diff --git a/Examples/HalfAdder/HalfAdder.pro b/Examples/HalfAdder/HalfAdder.pro
deleted file mode 100644
index 8d317673..00000000
--- a/Examples/HalfAdder/HalfAdder.pro
+++ /dev/null
@@ -1,74 +0,0 @@
-update=Thu Mar  3 21:34:08 2016
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Sources
-LibName8=eSim_Subckt
-LibName9=eSim_User
-LibName10=HalfAdder-rescue
-LibName11=power
-LibName12=device
-LibName13=transistors
-LibName14=conn
-LibName15=linear
-LibName16=regul
-LibName17=74xx
-LibName18=cmos4000
-LibName19=adc-dac
-LibName20=memory
-LibName21=xilinx
-LibName22=special
-LibName23=microcontrollers
-LibName24=dsp
-LibName25=microchip
-LibName26=analog_switches
-LibName27=motorola
-LibName28=texas
-LibName29=intel
-LibName30=audio
-LibName31=interface
-LibName32=digital-audio
-LibName33=philips
-LibName34=display
-LibName35=cypress
-LibName36=siliconi
-LibName37=opto
-LibName38=atmel
-LibName39=contrib
-LibName40=valves
-LibName41=eSim_Power
diff --git a/Examples/HalfAdder/HalfAdder.proj b/Examples/HalfAdder/HalfAdder.proj
deleted file mode 100644
index a6ecda7d..00000000
--- a/Examples/HalfAdder/HalfAdder.proj
+++ /dev/null
@@ -1 +0,0 @@
-schematicFile HalfAdder.sch
diff --git a/Examples/HalfAdder/HalfAdder.sch b/Examples/HalfAdder/HalfAdder.sch
deleted file mode 100644
index 604b4dcc..00000000
--- a/Examples/HalfAdder/HalfAdder.sch
+++ /dev/null
@@ -1,313 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:HalfAdder-rescue
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Power
-LIBS:HalfAdder-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L half_adder X1
-U 1 1 558A91C8
-P 5000 3900
-F 0 "X1" H 5900 4400 60  0000 C CNN
-F 1 "half_adder" H 5900 4300 60  0000 C CNN
-F 2 "" H 5000 3900 60  0000 C CNN
-F 3 "" H 5000 3900 60  0000 C CNN
-	1    5000 3900
-	1    0    0    -1  
-$EndComp
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-U 1 1 558A92C9
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-F 0 "U1" H 4550 3500 60  0000 C CNN
-F 1 "adc_bridge_2" H 4550 3650 60  0000 C CNN
-F 2 "" H 4550 3500 60  0000 C CNN
-F 3 "" H 4550 3500 60  0000 C CNN
-	1    4550 3500
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-$EndComp
-$Comp
-L dac_bridge_2 U2
-U 1 1 558A9300
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-F 0 "U2" H 6950 3450 60  0000 C CNN
-F 1 "dac_bridge_2" H 7000 3600 60  0000 C CNN
-F 2 "" H 6950 3450 60  0000 C CNN
-F 3 "" H 6950 3450 60  0000 C CNN
-	1    6950 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L DC v1
-U 1 1 558A9345
-P 3450 3150
-F 0 "v1" H 3250 3250 60  0000 C CNN
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-F 2 "R1" H 3150 3150 60  0000 C CNN
-F 3 "" H 3450 3150 60  0000 C CNN
-	1    3450 3150
-	0    1    1    0   
-$EndComp
-$Comp
-L DC v2
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-F 2 "R1" H 3150 3800 60  0000 C CNN
-F 3 "" H 3450 3800 60  0000 C CNN
-	1    3450 3800
-	0    1    1    0   
-$EndComp
-$Comp
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-U 1 1 558A93BB
-P 2950 4000
-F 0 "#PWR01" H 2950 4000 30  0001 C CNN
-F 1 "GND" H 2950 3930 30  0001 C CNN
-F 2 "" H 2950 4000 60  0000 C CNN
-F 3 "" H 2950 4000 60  0000 C CNN
-	1    2950 4000
-	1    0    0    -1  
-$EndComp
-$Comp
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-U 1 1 558A93D7
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-F 1 "GND" H 2950 3180 30  0001 C CNN
-F 2 "" H 2950 3250 60  0000 C CNN
-F 3 "" H 2950 3250 60  0000 C CNN
-	1    2950 3250
-	1    0    0    -1  
-$EndComp
-$Comp
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-U 1 1 558A9480
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-F 1 "GND" H 8350 3580 30  0001 C CNN
-F 2 "" H 8350 3650 60  0000 C CNN
-F 3 "" H 8350 3650 60  0000 C CNN
-	1    8350 3650
-	1    0    0    -1  
-$EndComp
-$Comp
-L PWR_FLAG #FLG04
-U 1 1 558A96D4
-P 2850 3850
-F 0 "#FLG04" H 2850 3945 50  0001 C CNN
-F 1 "PWR_FLAG" H 2850 4030 50  0000 C CNN
-F 2 "" H 2850 3850 60  0000 C CNN
-F 3 "" H 2850 3850 60  0000 C CNN
-	1    2850 3850
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-$EndComp
-Text GLabel 7600 3150 0    60   Input ~ 0
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-Text GLabel 7600 3750 0    60   Input ~ 0
-cout
-Text GLabel 4050 3150 2    60   Input ~ 0
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-Text GLabel 4100 3750 2    60   Input ~ 0
-IN2
-$Comp
-L R R1
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-F 2 "" H 7850 3330 30  0000 C CNN
-F 3 "" V 7850 3400 30  0000 C CNN
-	1    7800 3350
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R2
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-F 0 "R2" H 7850 3730 50  0000 C CNN
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-F 2 "" H 7850 3580 30  0000 C CNN
-F 3 "" V 7850 3650 30  0000 C CNN
-	1    7800 3600
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-$EndComp
-$Comp
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-F 2 "" H 3900 3300 60  0000 C CNN
-F 3 "" H 3900 3300 60  0000 C CNN
-	1    3900 3300
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-$EndComp
-$Comp
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-F 1 "plot_v1" H 4100 4100 60  0000 C CNN
-F 2 "" H 3900 3750 60  0000 C CNN
-F 3 "" H 3900 3750 60  0000 C CNN
-	1    3900 3750
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-$EndComp
-$Comp
-L plot_v1 U5
-U 1 1 56D8629D
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-F 0 "U5" H 7650 3750 60  0000 C CNN
-F 1 "plot_v1" H 7850 3600 60  0000 C CNN
-F 2 "" H 7650 3250 60  0000 C CNN
-F 3 "" H 7650 3250 60  0000 C CNN
-	1    7650 3250
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-$EndComp
-$Comp
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-U 1 1 56D86375
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-F 0 "U6" H 7650 4150 60  0000 C CNN
-F 1 "plot_v1" H 7850 4000 60  0000 C CNN
-F 2 "" H 7650 3650 60  0000 C CNN
-F 3 "" H 7650 3650 60  0000 C CNN
-	1    7650 3650
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-$EndComp
-Wire Wire Line
-	3000 3150 2950 3150
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-Wire Wire Line
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-	3950 3100 3950 3450
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-	3950 3150 3900 3150
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-	5300 3450 5300 3200
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-	6450 3400 6500 3400
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-	6450 3500 6450 3800
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-	7500 3400 7600 3400
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-Connection ~ 8350 3500
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-	4050 3150 4050 3250
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-	4100 3750 3950 3750
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-	7600 3750 7650 3750
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-Connection ~ 3950 3150
-Wire Wire Line
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diff --git a/Examples/HalfAdder/analysis b/Examples/HalfAdder/analysis
deleted file mode 100644
index 660a46cc..00000000
--- a/Examples/HalfAdder/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.tran 10e-03 100e-03 0e-03
-\ No newline at end of file
diff --git a/Examples/HalfAdder/half_adder.cir b/Examples/HalfAdder/half_adder.cir
deleted file mode 100644
index 8b2e7e06..00000000
--- a/Examples/HalfAdder/half_adder.cir
+++ /dev/null
@@ -1,11 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U2  1 4 3 d_xor		
-U3  1 4 2 d_and		
-U1  1 4 3 2 PORT		
-
-.end
diff --git a/Examples/HalfAdder/half_adder.cir.out b/Examples/HalfAdder/half_adder.cir.out
deleted file mode 100644
index b1b6b1e7..00000000
--- a/Examples/HalfAdder/half_adder.cir.out
+++ /dev/null
@@ -1,20 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-* u1  1 4 3 2 port
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.ac lin 0 0Hz 0Hz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/HalfAdder/half_adder.pro b/Examples/HalfAdder/half_adder.pro
deleted file mode 100644
index 30094fb9..00000000
--- a/Examples/HalfAdder/half_adder.pro
+++ /dev/null
@@ -1,69 +0,0 @@
-update=Wed Jun 24 11:27:22 2015
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=eSim_Analog
-LibName32=eSim_Devices
-LibName33=eSim_Digital
-LibName34=eSim_Hybrid
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
diff --git a/Examples/HalfAdder/half_adder.sch b/Examples/HalfAdder/half_adder.sch
deleted file mode 100644
index bf9bcbf0..00000000
--- a/Examples/HalfAdder/half_adder.sch
+++ /dev/null
@@ -1,152 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_xor U2
-U 1 1 558A946A
-P 5650 3050
-F 0 "U2" H 5650 3050 60  0000 C CNN
-F 1 "d_xor" H 5700 3150 47  0000 C CNN
-F 2 "" H 5650 3050 60  0000 C CNN
-F 3 "" H 5650 3050 60  0000 C CNN
-	1    5650 3050
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 558A94D5
-P 5700 3800
-F 0 "U3" H 5700 3800 60  0000 C CNN
-F 1 "d_and" H 5750 3900 60  0000 C CNN
-F 2 "" H 5700 3800 60  0000 C CNN
-F 3 "" H 5700 3800 60  0000 C CNN
-	1    5700 3800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 558A94F6
-P 4150 3000
-F 0 "U1" H 4200 3100 30  0000 C CNN
-F 1 "PORT" H 4150 3000 30  0000 C CNN
-F 2 "" H 4150 3000 60  0000 C CNN
-F 3 "" H 4150 3000 60  0000 C CNN
-	1    4150 3000
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 558A9543
-P 4150 3450
-F 0 "U1" H 4200 3550 30  0000 C CNN
-F 1 "PORT" H 4150 3450 30  0000 C CNN
-F 2 "" H 4150 3450 60  0000 C CNN
-F 3 "" H 4150 3450 60  0000 C CNN
-	2    4150 3450
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 558A9573
-P 6650 3000
-F 0 "U1" H 6700 3100 30  0000 C CNN
-F 1 "PORT" H 6650 3000 30  0000 C CNN
-F 2 "" H 6650 3000 60  0000 C CNN
-F 3 "" H 6650 3000 60  0000 C CNN
-	3    6650 3000
-	-1   0    0    1   
-$EndComp
-$Comp
-L PORT U1
-U 4 1 558A9606
-P 6700 3750
-F 0 "U1" H 6750 3850 30  0000 C CNN
-F 1 "PORT" H 6700 3750 30  0000 C CNN
-F 2 "" H 6700 3750 60  0000 C CNN
-F 3 "" H 6700 3750 60  0000 C CNN
-	4    6700 3750
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5200 2950 4450 2950
-Wire Wire Line
-	4450 2950 4450 3000
-Wire Wire Line
-	4450 3000 4400 3000
-Wire Wire Line
-	4400 3450 4550 3450
-Wire Wire Line
-	4550 3450 4550 3050
-Wire Wire Line
-	4550 3050 5200 3050
-Wire Wire Line
-	5250 3700 5000 3700
-Wire Wire Line
-	5000 3700 5000 2950
-Connection ~ 5000 2950
-Wire Wire Line
-	5250 3800 4850 3800
-Wire Wire Line
-	4850 3800 4850 3050
-Connection ~ 4850 3050
-Wire Wire Line
-	6100 3000 6400 3000
-Wire Wire Line
-	6150 3750 6450 3750
-Text Notes 4550 2950 0    60   ~ 0
-IN1\n\n
-Text Notes 4600 3150 0    60   ~ 0
-IN2
-Text Notes 6200 2950 0    60   ~ 0
-SUM\n
-Text Notes 6200 3650 0    60   ~ 0
-COUT\n
-$EndSCHEMATC
diff --git a/Examples/HalfAdder/half_adder.sub b/Examples/HalfAdder/half_adder.sub
deleted file mode 100644
index e9f92223..00000000
--- a/Examples/HalfAdder/half_adder.sub
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit half_adder
-.subckt half_adder 1 4 3 2 
-* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
-* u2  1 4 3 d_xor
-* u3  1 4 2 d_and
-a1 [1 4 ] 3 u2
-a2 [1 4 ] 2 u3
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends half_adder
-\ No newline at end of file
diff --git a/Examples/HalfAdder/plot_data_i.txt b/Examples/HalfAdder/plot_data_i.txt
deleted file mode 100644
index 9c89652a..00000000
--- a/Examples/HalfAdder/plot_data_i.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-            * /home/fossee/updatedexamples/half_adder/half_adder.cir
-            Transient Analysis  Tue Aug 29 19:58:36  2017
---------------------------------------------------------------------------------
-Index   time            a2#branch_1_0   a2#branch_1_1   v1#branch       
---------------------------------------------------------------------------------
-0	0.000000e+00	-5.00000e-03	0.000000e+00	0.000000e+00	
-1	1.000000e-05	-5.00000e-03	0.000000e+00	0.000000e+00	
-2	2.000000e-05	-5.00000e-03	0.000000e+00	0.000000e+00	
-3	4.000000e-05	-5.00000e-03	0.000000e+00	0.000000e+00	
-4	8.000000e-05	-5.00000e-03	0.000000e+00	0.000000e+00	
-5	1.600000e-04	-5.00000e-03	0.000000e+00	0.000000e+00	
-6	3.200000e-04	-5.00000e-03	0.000000e+00	0.000000e+00	
-7	6.400000e-04	-5.00000e-03	0.000000e+00	0.000000e+00	
-8	1.280000e-03	-5.00000e-03	0.000000e+00	0.000000e+00	
-9	2.560000e-03	-5.00000e-03	0.000000e+00	0.000000e+00	
-10	4.560000e-03	-5.00000e-03	0.000000e+00	0.000000e+00	
-11	6.560000e-03	-5.00000e-03	0.000000e+00	0.000000e+00	
-12	8.560000e-03	-5.00000e-03	0.000000e+00	0.000000e+00	
-13	1.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-14	1.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-15	1.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-16	1.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-17	1.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-18	2.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-19	2.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-20	2.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-21	2.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-22	2.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-23	3.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-24	3.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-25	3.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-26	3.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-27	3.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-28	4.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-29	4.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-30	4.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-31	4.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-32	4.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-33	5.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-34	5.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-35	5.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-36	5.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-37	5.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-38	6.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-39	6.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-40	6.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-41	6.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-42	6.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-43	7.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-44	7.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-45	7.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-46	7.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-47	7.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-48	8.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-49	8.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-50	8.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-51	8.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-52	8.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-53	9.056000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-54	9.256000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-
-Index   time            a2#branch_1_0   a2#branch_1_1   v1#branch       
---------------------------------------------------------------------------------
-55	9.456000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-56	9.656000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-57	9.856000e-02	-5.00000e-03	0.000000e+00	0.000000e+00	
-58	1.000000e-01	-5.00000e-03	0.000000e+00	0.000000e+00	
-
-            * /home/fossee/updatedexamples/half_adder/half_adder.cir
-            Transient Analysis  Tue Aug 29 19:58:36  2017
---------------------------------------------------------------------------------
-Index   time            v2#branch       
---------------------------------------------------------------------------------
-0	0.000000e+00	0.000000e+00	
-1	1.000000e-05	0.000000e+00	
-2	2.000000e-05	0.000000e+00	
-3	4.000000e-05	0.000000e+00	
-4	8.000000e-05	0.000000e+00	
-5	1.600000e-04	0.000000e+00	
-6	3.200000e-04	0.000000e+00	
-7	6.400000e-04	0.000000e+00	
-8	1.280000e-03	0.000000e+00	
-9	2.560000e-03	0.000000e+00	
-10	4.560000e-03	0.000000e+00	
-11	6.560000e-03	0.000000e+00	
-12	8.560000e-03	0.000000e+00	
-13	1.056000e-02	0.000000e+00	
-14	1.256000e-02	0.000000e+00	
-15	1.456000e-02	0.000000e+00	
-16	1.656000e-02	0.000000e+00	
-17	1.856000e-02	0.000000e+00	
-18	2.056000e-02	0.000000e+00	
-19	2.256000e-02	0.000000e+00	
-20	2.456000e-02	0.000000e+00	
-21	2.656000e-02	0.000000e+00	
-22	2.856000e-02	0.000000e+00	
-23	3.056000e-02	0.000000e+00	
-24	3.256000e-02	0.000000e+00	
-25	3.456000e-02	0.000000e+00	
-26	3.656000e-02	0.000000e+00	
-27	3.856000e-02	0.000000e+00	
-28	4.056000e-02	0.000000e+00	
-29	4.256000e-02	0.000000e+00	
-30	4.456000e-02	0.000000e+00	
-31	4.656000e-02	0.000000e+00	
-32	4.856000e-02	0.000000e+00	
-33	5.056000e-02	0.000000e+00	
-34	5.256000e-02	0.000000e+00	
-35	5.456000e-02	0.000000e+00	
-36	5.656000e-02	0.000000e+00	
-37	5.856000e-02	0.000000e+00	
-38	6.056000e-02	0.000000e+00	
-39	6.256000e-02	0.000000e+00	
-40	6.456000e-02	0.000000e+00	
-41	6.656000e-02	0.000000e+00	
-42	6.856000e-02	0.000000e+00	
-43	7.056000e-02	0.000000e+00	
-44	7.256000e-02	0.000000e+00	
-45	7.456000e-02	0.000000e+00	
-46	7.656000e-02	0.000000e+00	
-47	7.856000e-02	0.000000e+00	
-48	8.056000e-02	0.000000e+00	
-49	8.256000e-02	0.000000e+00	
-50	8.456000e-02	0.000000e+00	
-51	8.656000e-02	0.000000e+00	
-52	8.856000e-02	0.000000e+00	
-53	9.056000e-02	0.000000e+00	
-54	9.256000e-02	0.000000e+00	
-
-Index   time            v2#branch       
---------------------------------------------------------------------------------
-55	9.456000e-02	0.000000e+00	
-56	9.656000e-02	0.000000e+00	
-57	9.856000e-02	0.000000e+00	
-58	1.000000e-01	0.000000e+00	
diff --git a/Examples/HalfAdder/plot_data_v.txt b/Examples/HalfAdder/plot_data_v.txt
deleted file mode 100644
index ae3453b9..00000000
--- a/Examples/HalfAdder/plot_data_v.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-            * /home/fossee/updatedexamples/half_adder/half_adder.cir
-            Transient Analysis  Tue Aug 29 19:58:36  2017
---------------------------------------------------------------------------------
-Index   time            cout            in1             in2             
---------------------------------------------------------------------------------
-0	0.000000e+00	0.000000e+00	5.000000e+00	0.000000e+00	
-1	1.000000e-05	0.000000e+00	5.000000e+00	0.000000e+00	
-2	2.000000e-05	0.000000e+00	5.000000e+00	0.000000e+00	
-3	4.000000e-05	0.000000e+00	5.000000e+00	0.000000e+00	
-4	8.000000e-05	0.000000e+00	5.000000e+00	0.000000e+00	
-5	1.600000e-04	0.000000e+00	5.000000e+00	0.000000e+00	
-6	3.200000e-04	0.000000e+00	5.000000e+00	0.000000e+00	
-7	6.400000e-04	0.000000e+00	5.000000e+00	0.000000e+00	
-8	1.280000e-03	0.000000e+00	5.000000e+00	0.000000e+00	
-9	2.560000e-03	0.000000e+00	5.000000e+00	0.000000e+00	
-10	4.560000e-03	0.000000e+00	5.000000e+00	0.000000e+00	
-11	6.560000e-03	0.000000e+00	5.000000e+00	0.000000e+00	
-12	8.560000e-03	0.000000e+00	5.000000e+00	0.000000e+00	
-13	1.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-14	1.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-15	1.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-16	1.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-17	1.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-18	2.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-19	2.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-20	2.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-21	2.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-22	2.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-23	3.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-24	3.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-25	3.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-26	3.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-27	3.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-28	4.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-29	4.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-30	4.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-31	4.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-32	4.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-33	5.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-34	5.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-35	5.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-36	5.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-37	5.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-38	6.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-39	6.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-40	6.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-41	6.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-42	6.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-43	7.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-44	7.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-45	7.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-46	7.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-47	7.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-48	8.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-49	8.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-50	8.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-51	8.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-52	8.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-53	9.056000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-54	9.256000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-
-Index   time            cout            in1             in2             
---------------------------------------------------------------------------------
-55	9.456000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-56	9.656000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-57	9.856000e-02	0.000000e+00	5.000000e+00	0.000000e+00	
-58	1.000000e-01	0.000000e+00	5.000000e+00	0.000000e+00	
-
-            * /home/fossee/updatedexamples/half_adder/half_adder.cir
-            Transient Analysis  Tue Aug 29 19:58:36  2017
---------------------------------------------------------------------------------
-Index   time            sum             
---------------------------------------------------------------------------------
-0	0.000000e+00	5.000000e+00	
-1	1.000000e-05	5.000000e+00	
-2	2.000000e-05	5.000000e+00	
-3	4.000000e-05	5.000000e+00	
-4	8.000000e-05	5.000000e+00	
-5	1.600000e-04	5.000000e+00	
-6	3.200000e-04	5.000000e+00	
-7	6.400000e-04	5.000000e+00	
-8	1.280000e-03	5.000000e+00	
-9	2.560000e-03	5.000000e+00	
-10	4.560000e-03	5.000000e+00	
-11	6.560000e-03	5.000000e+00	
-12	8.560000e-03	5.000000e+00	
-13	1.056000e-02	5.000000e+00	
-14	1.256000e-02	5.000000e+00	
-15	1.456000e-02	5.000000e+00	
-16	1.656000e-02	5.000000e+00	
-17	1.856000e-02	5.000000e+00	
-18	2.056000e-02	5.000000e+00	
-19	2.256000e-02	5.000000e+00	
-20	2.456000e-02	5.000000e+00	
-21	2.656000e-02	5.000000e+00	
-22	2.856000e-02	5.000000e+00	
-23	3.056000e-02	5.000000e+00	
-24	3.256000e-02	5.000000e+00	
-25	3.456000e-02	5.000000e+00	
-26	3.656000e-02	5.000000e+00	
-27	3.856000e-02	5.000000e+00	
-28	4.056000e-02	5.000000e+00	
-29	4.256000e-02	5.000000e+00	
-30	4.456000e-02	5.000000e+00	
-31	4.656000e-02	5.000000e+00	
-32	4.856000e-02	5.000000e+00	
-33	5.056000e-02	5.000000e+00	
-34	5.256000e-02	5.000000e+00	
-35	5.456000e-02	5.000000e+00	
-36	5.656000e-02	5.000000e+00	
-37	5.856000e-02	5.000000e+00	
-38	6.056000e-02	5.000000e+00	
-39	6.256000e-02	5.000000e+00	
-40	6.456000e-02	5.000000e+00	
-41	6.656000e-02	5.000000e+00	
-42	6.856000e-02	5.000000e+00	
-43	7.056000e-02	5.000000e+00	
-44	7.256000e-02	5.000000e+00	
-45	7.456000e-02	5.000000e+00	
-46	7.656000e-02	5.000000e+00	
-47	7.856000e-02	5.000000e+00	
-48	8.056000e-02	5.000000e+00	
-49	8.256000e-02	5.000000e+00	
-50	8.456000e-02	5.000000e+00	
-51	8.656000e-02	5.000000e+00	
-52	8.856000e-02	5.000000e+00	
-53	9.056000e-02	5.000000e+00	
-54	9.256000e-02	5.000000e+00	
-
-Index   time            sum             
---------------------------------------------------------------------------------
-55	9.456000e-02	5.000000e+00	
-56	9.656000e-02	5.000000e+00	
-57	9.856000e-02	5.000000e+00	
-58	1.000000e-01	5.000000e+00