11 files changed, 3 insertions, 792 deletions
diff --git a/Examples/FullwaveRectifier_SCR/D.lib b/Examples/FullwaveRectifier_SCR/D.lib
deleted file mode 100755
index ef18bb50..00000000
--- a/Examples/FullwaveRectifier_SCR/D.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL D1N750 D(
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-)
-\ No newline at end of file
diff --git a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR-cache.lib b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR-cache.lib
deleted file mode 100644
index b4195e35..00000000
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diff --git a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.bak b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.bak
deleted file mode 100644
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diff --git a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out
index 2bc6d6d7..46179b0f 100644
--- a/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out
+++ b/Examples/FullwaveRectifier_SCR/FullwaveRectifier_SCR.cir.out
@@ -1,7 +1,7 @@
 * /home/fossee/updatedexamples/fullwaverectifier_scr/fullwaverectifier_scr.cir
 
 .include scr.sub
-.include D.lib
+.include userDiode.lib
 x1 gnd pulse out2 scr
 v1  in1 in2 sine(0 200 100 0 0)
 v2  pulse gnd pulse(0 5 2m 0 0 1m 5m)
diff --git a/Examples/FullwaveRectifier_SCR/PowerDiode.lib b/Examples/FullwaveRectifier_SCR/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/Examples/FullwaveRectifier_SCR/PowerDiode.lib
+++ b/Examples/FullwaveRectifier_SCR/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
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-)
-\ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/FullwaveRectifier_SCR/scr.bak b/Examples/FullwaveRectifier_SCR/scr.bak
deleted file mode 100644
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-	1    0    0    -1  
-$EndComp
-$Comp
-L aswitch U1
-U 1 1 565DC87E
-P 6400 2100
-F 0 "U1" H 6850 2400 60  0000 C CNN
-F 1 "aswitch" H 6850 2300 60  0000 C CNN
-F 2 "" H 6850 2200 60  0000 C CNN
-F 3 "" H 6850 2200 60  0000 C CNN
-	1    6400 2100
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
-	5950 2000 6650 2000
-$EndSCHEMATC
diff --git a/Examples/FullwaveRectifier_SCR/scr.cir.ckt b/Examples/FullwaveRectifier_SCR/scr.cir.ckt
deleted file mode 100644
index b0e218fd..00000000
--- a/Examples/FullwaveRectifier_SCR/scr.cir.ckt
+++ /dev/null
@@ -1,19 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22
-.include diode.lib
-
-u2  5 8 1 port
-* f2
-* Analog Switch analogswitch
-d1  4 2 diode
-v2  3 4 dc 0
-c1  5 6 10u
-r2  5 6 1
-* f1
-v1  9 7 dc 0
-r1  8 9 50
-Vf2 2 5 0
-f2 5 6 Vf2 100
-Vf1 7 5 0
-f1 5 6 Vf1 10
-a1 6 (1 3) u1
-.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/Examples/FullwaveRectifier_SCR/scr.cir.out~ b/Examples/FullwaveRectifier_SCR/scr.cir.out~
deleted file mode 100644
index d600f25d..00000000
--- a/Examples/FullwaveRectifier_SCR/scr.cir.out~
+++ /dev/null
@@ -1,29 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-
-.include PowerDiode.lib
-* u2  3 7 1 port
-* f2
-d1 5 2 PowerDiode
-c1  3 9 10u
-* f1
-v1 8 4  dc 0
-v2 6 5  dc 0
-* u1  9 1 6 aswitch
-r1  7 8 50
-r2  3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 (1 6)  u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) 
-.tran 0e-12 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/FullwaveRectifier_SCR/scr.sub~ b/Examples/FullwaveRectifier_SCR/scr.sub~
deleted file mode 100644
index 0fdddbf4..00000000
--- a/Examples/FullwaveRectifier_SCR/scr.sub~
+++ /dev/null
@@ -1,23 +0,0 @@
-* Subcircuit scr
-.subckt scr 3 7 1 
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1  3 9 10u
-* f1
-v1 8 4  dc 0
-v2 6 5  dc 0
-* u1  9 1 6 aswitch
-r1  7 8 50
-r2  3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr
-\ No newline at end of file
diff --git a/Examples/FullwaveRectifier_SCR/scr_Previous_Values.xml b/Examples/FullwaveRectifier_SCR/scr_Previous_Values.xml
deleted file mode 100644
index 8ff6e8d3..00000000
--- a/Examples/FullwaveRectifier_SCR/scr_Previous_Values.xml
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
-\ No newline at end of file
diff --git a/Examples/FullwaveRectifier_SCR/userDiode.lib b/Examples/FullwaveRectifier_SCR/userDiode.lib
new file mode 100644
index 00000000..89b96f4a
--- /dev/null
+++ b/Examples/FullwaveRectifier_SCR/userDiode.lib
@@ -0,0 +1 @@
+.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m )