diff options
Diffstat (limited to 'Examples/BasicGates')
-rw-r--r-- | Examples/BasicGates/$savepcb.brd | 84 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates-cache.bak | 324 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates-cache.lib | 207 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.bak | 347 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.cir | 21 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.cir (copy).out | 66 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.cir.ckt | 59 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.cir.out | 48 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.cmp | 101 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.net | 112 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.pro | 41 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.proj | 1 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates.sch | 407 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates_Previous_Values.xml | 1 | ||||
-rw-r--r-- | Examples/BasicGates/BasicGates_last_input.txt | 20 | ||||
-rw-r--r-- | Examples/BasicGates/analysis | 1 | ||||
-rw-r--r-- | Examples/BasicGates/plot_data_i.txt | 335 | ||||
-rw-r--r-- | Examples/BasicGates/plot_data_v.txt | 335 |
18 files changed, 2510 insertions, 0 deletions
diff --git a/Examples/BasicGates/$savepcb.brd b/Examples/BasicGates/$savepcb.brd new file mode 100644 index 00000000..c5b62f89 --- /dev/null +++ b/Examples/BasicGates/$savepcb.brd @@ -0,0 +1,84 @@ +PCBNEW-BOARD Version 1 date 6/7/2013 11:31:39 AM
+
+# Created by Pcbnew(2011-04-29 BZR 2986)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 0
+NoConn 0
+Di 0 0 117000 82670
+Ndraw 0
+Ntrack 0
+Nzone 0
+BoardThickness 630
+Nmodule 0
+Nnets 1
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "7 jun 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 80
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
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+MicroViasAllowed 0
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+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 80
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+$EndNCLASS
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/Examples/BasicGates/BasicGates-cache.bak b/Examples/BasicGates/BasicGates-cache.bak new file mode 100644 index 00000000..ba5e5f27 --- /dev/null +++ b/Examples/BasicGates/BasicGates-cache.bak @@ -0,0 +1,324 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 09 December 2012 08:00:09 AM IST +#encoding utf-8 +# +# 74HCT04 +# +DEF 74HCT04 U 0 30 Y Y 6 F N +F0 "U" 150 100 40 H V C CNN +F1 "74HCT04" 200 -100 40 H V C CNN +ALIAS 74HC14 74HC04 74LS14 +DRAW +P 4 0 0 0 -150 150 -150 -150 150 0 -150 150 N +X GND 7 -50 -100 0 U 30 20 0 0 W N +X VCC 14 -50 100 0 D 30 20 0 0 W N +X ~ 1 -450 0 300 R 60 60 1 1 I +X ~ 2 450 0 300 L 60 60 1 1 O I +X ~ 3 -450 0 300 R 60 60 2 1 I +X ~ 4 450 0 300 L 60 60 2 1 O I +X ~ 5 -450 0 300 R 60 60 3 1 I +X ~ 6 450 0 300 L 60 60 3 1 O I +X ~ 8 450 0 300 L 60 60 4 1 O I +X ~ 9 -450 0 300 R 60 60 4 1 I +X ~ 10 450 0 300 L 60 60 5 1 O I +X ~ 11 -450 0 300 R 60 60 5 1 I +X ~ 12 450 0 300 L 60 60 6 1 O I +X ~ 13 -450 0 300 R 60 60 6 1 I +X ~ 1 -450 0 300 R 60 60 1 2 I I +X ~ 2 450 0 300 L 60 60 1 2 O +X ~ 3 -450 0 300 R 60 60 2 2 I I +X ~ 4 450 0 300 L 60 60 2 2 O +X ~ 5 -450 0 300 R 60 60 3 2 I I +X ~ 6 450 0 300 L 60 60 3 2 O +X ~ 8 450 0 300 L 60 60 4 2 O +X ~ 9 -450 0 300 R 60 60 4 2 I I +X ~ 10 450 0 300 L 60 60 5 2 O +X ~ 11 -450 0 300 R 60 60 5 2 I I +X ~ 12 450 0 300 L 60 60 6 2 O +X ~ 13 -450 0 300 R 60 60 6 2 I I +ENDDRAW +ENDDEF +# +# 74LS00 +# +DEF 74LS00 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS00" 0 -100 60 H V C CNN +ALIAS 74LS37 7400 74HCT00 74HC00 +$FPLIST + 14DIP300* + SO14* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A 100 0 200 -899 899 0 1 0 N 100 -200 100 200 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O I +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O I +X ~ 8 600 0 300 L 60 60 3 1 O I +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O I +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -465 0 259 504 -504 0 2 0 N -300 200 -300 -200 +A -11 143 343 -881 -246 0 2 0 N 0 -200 300 0 +A -10 -141 340 244 883 0 2 0 N 300 0 0 200 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O +X ~ 8 600 0 300 L 60 60 3 2 O +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS02 +# +DEF 74LS02 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS02" 50 -50 60 H V C CNN +ALIAS 74HC02 74HCT02 7402 74LS28 +$FPLIST + SO14* + 14DIP* +$ENDFPLIST +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A -470 0 262 496 -496 0 1 8 N -300 200 -300 -200 +A -1 -127 327 898 228 0 1 8 N 0 200 300 0 +A -1 128 327 -230 -898 0 1 8 N 300 0 0 -200 +P 2 0 1 8 -300 -200 0 -200 N +P 2 0 1 8 -300 200 0 200 N +X ~ 1 600 0 300 L 60 60 1 1 O I +X ~ 2 -600 100 370 R 60 60 1 1 I +X ~ 3 -600 -100 370 R 60 60 1 1 I +X ~ 4 600 0 300 L 60 60 2 1 O I +X ~ 5 -600 100 370 R 60 60 2 1 I +X ~ 6 -600 -100 370 R 60 60 2 1 I +X ~ 8 -600 100 370 R 60 60 3 1 I +X ~ 9 -600 -100 370 R 60 60 3 1 I +X ~ 10 600 0 300 L 60 60 3 1 O I +X ~ 11 -600 100 370 R 60 60 4 1 I +X ~ 12 -600 -100 370 R 60 60 4 1 I +X ~ 13 600 0 300 L 60 60 4 1 O I +A 100 0 200 896 -896 0 2 8 N 101 200 101 -199 +P 4 0 2 8 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 600 0 300 L 60 60 1 2 O +X ~ 2 -600 100 300 R 60 60 1 2 I I +X ~ 3 -600 -100 300 R 60 60 1 2 I I +X ~ 4 600 0 300 L 60 60 2 2 O +X ~ 5 -600 100 300 R 60 60 2 2 I I +X ~ 6 -600 -100 300 R 60 60 2 2 I I +X ~ 8 -600 100 300 R 60 60 3 2 I I +X ~ 9 -600 -100 300 R 60 60 3 2 I I +X ~ 10 600 0 300 L 60 60 3 2 O +X ~ 11 -600 100 300 R 60 60 4 2 I I +X ~ 12 -600 -100 300 R 60 60 4 2 I I +X ~ 13 600 0 300 L 60 60 4 2 O +ENDDRAW +ENDDEF +# +# 74LS08 +# +DEF 74LS08 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS08" 0 -50 60 H V C CNN +ALIAS 74LS09 +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 U 40 40 0 0 W N +A 100 0 200 896 -896 0 1 0 N 101 200 101 -199 +P 4 0 1 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 1 I +X ~ 2 -600 -100 300 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O +X ~ 4 -600 100 300 R 60 60 2 1 I +X ~ 5 -600 -100 300 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O +X ~ 8 600 0 300 L 60 60 3 1 O +X ~ 9 -600 100 300 R 60 60 3 1 I +X ~ 10 -600 -100 300 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O +X ~ 12 -600 100 300 R 60 60 4 1 I +X ~ 13 -600 -100 300 R 60 60 4 1 I +A -470 0 262 495 -495 0 2 0 N -300 199 -300 -198 +A -2 126 326 -897 -225 0 2 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 2 0 N 2 200 300 0 +P 2 0 2 0 -300 -200 0 -200 N +P 2 0 2 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 2 I I +X ~ 2 -600 -100 370 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O I +X ~ 4 -600 100 370 R 60 60 2 2 I I +X ~ 5 -600 -100 370 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O I +X ~ 8 600 0 300 L 60 60 3 2 O I +X ~ 9 -600 100 370 R 60 60 3 2 I I +X ~ 10 -600 -100 370 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O I +X ~ 12 -600 100 370 R 60 60 4 2 I I +X ~ 13 -600 -100 370 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS32 +# +DEF 74LS32 U 0 30 Y Y 4 F N +F0 "U" 0 50 60 H V C CNN +F1 "74LS32" 0 -50 60 H V C CNN +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 U 40 40 0 0 W N +A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198 +A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 1 0 N 2 200 300 0 +P 2 0 1 0 -300 -200 0 -200 N +P 2 0 1 0 -300 200 0 200 N +X ~ 1 -600 100 370 R 60 60 1 1 I +X ~ 2 -600 -100 370 R 60 60 1 1 I +X ~ 3 600 0 300 L 60 60 1 1 O +X ~ 4 -600 100 370 R 60 60 2 1 I +X ~ 5 -600 -100 370 R 60 60 2 1 I +X ~ 6 600 0 300 L 60 60 2 1 O +X ~ 8 600 0 300 L 60 60 3 1 O +X ~ 9 -600 100 370 R 60 60 3 1 I +X ~ 10 -600 -100 370 R 60 60 3 1 I +X ~ 11 600 0 300 L 60 60 4 1 O +X ~ 12 -600 100 370 R 60 60 4 1 I +X ~ 13 -600 -100 370 R 60 60 4 1 I +A 100 0 200 896 -896 0 2 0 N 101 200 101 -199 +P 4 0 2 0 100 200 -300 200 -300 -200 100 -200 N +X ~ 1 -600 100 300 R 60 60 1 2 I I +X ~ 2 -600 -100 300 R 60 60 1 2 I I +X ~ 3 600 0 300 L 60 60 1 2 O I +X ~ 4 -600 100 300 R 60 60 2 2 I I +X ~ 5 -600 -100 300 R 60 60 2 2 I I +X ~ 6 600 0 300 L 60 60 2 2 O I +X ~ 8 600 0 300 L 60 60 3 2 O I +X ~ 9 -600 100 300 R 60 60 3 2 I I +X ~ 10 -600 -100 300 R 60 60 3 2 I I +X ~ 11 600 0 300 L 60 60 4 2 O I +X ~ 12 -600 100 300 R 60 60 4 2 I I +X ~ 13 -600 -100 300 R 60 60 4 2 I I +ENDDRAW +ENDDEF +# +# 74LS86 +# +DEF 74LS86 U 0 30 Y N 4 F N +F0 "U" 50 50 50 H V C CNN +F1 "74LS86" 50 -50 40 H V C CNN +ALIAS 74HC86 +DRAW +X GND 7 -200 -200 0 U 40 40 0 0 W N +X VCC 14 -200 200 0 D 40 40 0 0 W N +A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198 +A -396 -2 281 457 -451 0 1 0 N -200 199 -198 -200 +A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2 +A 4 -120 320 906 221 0 1 0 N 2 200 300 0 +P 2 0 1 0 -200 -200 0 -200 N +P 2 0 1 0 -200 200 0 200 N +X IN1 1 -600 100 370 R 60 60 1 1 I +X IN2 2 -600 -100 370 R 60 60 1 1 I +X OUT 3 600 0 300 L 60 60 1 1 O +X IN1 4 -600 100 370 R 60 60 2 1 I +X IN2 5 -600 -100 370 R 60 60 2 1 I +X OUT 6 600 0 300 L 60 60 2 1 O +X OUT 8 600 0 300 L 60 60 3 1 O +X IN1 9 -600 100 370 R 60 60 3 1 I +X IN2 10 -600 -100 370 R 60 60 3 1 I +X OUT 11 600 0 300 L 60 60 4 1 O +X IN1 12 -600 100 370 R 60 60 4 1 I +X IN2 13 -600 -100 370 R 60 60 4 1 I +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot1 +# +DEF vplot1 U 0 40 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/BasicGates/BasicGates-cache.lib b/Examples/BasicGates/BasicGates-cache.lib new file mode 100644 index 00000000..f71daa19 --- /dev/null +++ b/Examples/BasicGates/BasicGates-cache.lib @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/BasicGates/BasicGates.bak b/Examples/BasicGates/BasicGates.bak new file mode 100644 index 00000000..050f6d4a --- /dev/null +++ b/Examples/BasicGates/BasicGates.bak @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 date Sunday 09 December 2012 08:37:05 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:BasicGates-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VPLOT8_1 U1 +U 3 1 50C3FFE2 +P 9700 2500 +F 0 "U1" H 9550 2600 50 0000 C CNN +F 1 "VPLOT8_1" H 9850 2600 50 0000 C CNN + 3 9700 2500 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 2 1 50C3FFDB +P 2400 3300 +F 0 "U1" H 2250 3400 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 3400 50 0000 C CNN + 2 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L VPLOT8_1 U1 +U 1 1 50C3FFD3 +P 2400 1250 +F 0 "U1" H 2250 1350 50 0000 C CNN +F 1 "VPLOT8_1" H 2550 1350 50 0000 C CNN + 1 2400 1250 + 1 0 0 -1 +$EndComp +Connection ~ 9700 3000 +Wire Wire Line + 9700 3000 9700 2800 +Wire Wire Line + 9900 3100 9900 3000 +Wire Wire Line + 9900 3000 9100 3000 +Wire Wire Line + 1700 3800 3750 3800 +Wire Wire Line + 7900 3100 7850 3100 +Wire Wire Line + 7850 3100 7850 3400 +Wire Wire Line + 7850 3400 7750 3400 +Connection ~ 5300 2300 +Wire Wire Line + 5300 2300 5300 3300 +Wire Wire Line + 5300 3300 5500 3300 +Wire Wire Line + 5100 3500 5500 3500 +Wire Wire Line + 7900 2900 7350 2900 +Wire Wire Line + 7350 2900 7350 2400 +Wire Wire Line + 7350 2400 7000 2400 +Connection ~ 3750 2200 +Wire Wire Line + 3900 3400 3750 3400 +Wire Wire Line + 3750 3400 3750 2200 +Wire Wire Line + 3850 2200 3650 2200 +Wire Wire Line + 3650 2200 3650 1700 +Connection ~ 2400 1700 +Wire Wire Line + 2400 1700 2400 1550 +Connection ~ 2250 1700 +Connection ~ 2000 2900 +Wire Wire Line + 2000 2900 2000 2700 +Wire Wire Line + 2250 3800 2250 4150 +Wire Wire Line + 1700 3800 1700 3950 +Wire Wire Line + 2250 2500 2250 2900 +Wire Wire Line + 2250 2900 1750 2900 +Connection ~ 1700 5050 +Wire Wire Line + 1700 5050 2250 5050 +Wire Wire Line + 2250 5050 2250 4650 +Wire Wire Line + 1700 4850 1700 5200 +Wire Wire Line + 1750 1800 1750 1700 +Wire Wire Line + 2250 1700 2250 2000 +Wire Wire Line + 1750 3150 1750 2700 +Connection ~ 1750 2900 +Connection ~ 2250 3800 +Wire Wire Line + 2400 3800 2400 3600 +Connection ~ 2400 3800 +Wire Wire Line + 3900 3600 3750 3600 +Wire Wire Line + 3750 3600 3750 3800 +Wire Wire Line + 3500 3800 3500 2400 +Wire Wire Line + 3500 2400 3850 2400 +Connection ~ 3500 3800 +Wire Wire Line + 5050 2300 5800 2300 +Wire Wire Line + 6200 2200 6200 1900 +Wire Wire Line + 5800 2500 5200 2500 +Wire Wire Line + 5200 2500 5200 3500 +Connection ~ 5200 3500 +Wire Wire Line + 6700 3400 6850 3400 +Wire Wire Line + 1750 1700 3650 1700 +Wire Wire Line + 9900 3600 9900 3900 +Text Notes 9150 2850 0 60 ~ 0 +~A.B +Text Notes 9050 2850 0 60 ~ 0 ++ +Text Notes 8900 2850 0 60 ~ 0 +A.B +Text Notes 8000 2300 0 60 ~ 0 +~B +Text Notes 7900 2300 0 60 ~ 0 ++ +Text Notes 7750 2300 0 60 ~ 0 +=~A +Text Notes 7900 3650 0 60 ~ 0 +=A+B +Text Notes 7850 3500 0 60 ~ 0 +A.B+A+B +Text Notes 6450 3600 0 60 ~ 0 +~((A.B)+(A+B)) +Text Notes 7100 2300 0 60 ~ 0 +~((A.B).(A+B)) +$Comp +L 74HC86 U12 +U 1 1 507253B2 +P 8500 3000 +F 0 "U12" H 8550 3050 50 0000 C CNN +F 1 "74HC86" H 8550 2950 40 0000 C CNN + 1 8500 3000 + 1 0 0 -1 +$EndComp +Text Notes 5150 3650 0 60 ~ 0 +A+B +Text Notes 5100 2250 0 60 ~ 0 +A.B +Text Notes 3600 3950 0 60 ~ 0 +B +Text Notes 3500 1650 0 60 ~ 0 +A +$Comp +L 74LS32 U8 +U 1 1 50725446 +P 4500 3500 +F 0 "U8" H 4500 3550 60 0000 C CNN +F 1 "74LS32" H 4500 3450 60 0000 C CNN + 1 4500 3500 + 1 0 0 -1 +$EndComp +$Comp +L 74LS08 U7 +U 1 1 50725428 +P 4450 2300 +F 0 "U7" H 4450 2350 60 0000 C CNN +F 1 "74LS08" H 4450 2250 60 0000 C CNN + 1 4450 2300 + 1 0 0 -1 +$EndComp +$Comp +L 74HC02 U9 +U 1 1 50725415 +P 6100 3400 +F 0 "U9" H 6100 3450 60 0000 C CNN +F 1 "74HC02" H 6150 3350 60 0000 C CNN + 1 6100 3400 + 1 0 0 -1 +$EndComp +$Comp +L 74HC04 U11 +U 1 1 507253DF +P 7300 3400 +F 0 "U11" H 7450 3500 40 0000 C CNN +F 1 "74HC04" H 7500 3300 40 0000 C CNN + 1 7300 3400 + 1 0 0 -1 +$EndComp +$Comp +L 7400 U10 +U 1 1 5072539F +P 6400 2400 +F 0 "U10" H 6400 2450 60 0000 C CNN +F 1 "7400" H 6400 2300 60 0000 C CNN + 1 6400 2400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5072534B +P 9900 3900 +F 0 "#PWR01" H 9900 3900 30 0001 C CNN +F 1 "GND" H 9900 3830 30 0001 C CNN + 1 9900 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 507251F2 +P 2000 2700 +F 0 "#FLG02" H 2000 2970 30 0001 C CNN +F 1 "PWR_FLAG" H 2000 2930 30 0000 C CNN + 1 2000 2700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 507251E5 +P 1750 3150 +F 0 "#PWR03" H 1750 3150 30 0001 C CNN +F 1 "GND" H 1750 3080 30 0001 C CNN + 1 1750 3150 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 507251A7 +P 2250 2250 +F 0 "R3" V 2330 2250 50 0000 C CNN +F 1 "1000" V 2250 2250 50 0000 C CNN + 1 2250 2250 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v2 +U 1 1 50725192 +P 1750 2250 +F 0 "v2" H 1550 2350 60 0000 C CNN +F 1 "PULSE" H 1550 2200 60 0000 C CNN + 1 1750 2250 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 50653022 +P 6200 1900 +F 0 "#FLG04" H 6200 2170 30 0001 C CNN +F 1 "PWR_FLAG" H 6200 2130 30 0000 C CNN + 1 6200 1900 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 9900 3350 +F 0 "R2" V 9980 3350 50 0000 C CNN +F 1 "1000" V 9900 3350 50 0000 C CNN + 1 9900 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 2250 4400 +F 0 "R1" V 2330 4400 50 0000 C CNN +F 1 "1000" V 2250 4400 50 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 505C9EE8 +P 1700 5200 +F 0 "#PWR05" H 1700 5200 30 0001 C CNN +F 1 "GND" H 1700 5130 30 0001 C CNN + 1 1700 5200 + 1 0 0 -1 +$EndComp +$Comp +L PULSE v1 +U 1 1 505C9ECF +P 1700 4400 +F 0 "v1" H 1500 4500 60 0000 C CNN +F 1 "PULSE" H 1500 4350 60 0000 C CNN + 1 1700 4400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/BasicGates/BasicGates.cir b/Examples/BasicGates/BasicGates.cir new file mode 100644 index 00000000..fbfc4755 --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir @@ -0,0 +1,21 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 8 14:38:19 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R3 8 0 1000 +R2 3 0 1000 +R1 7 0 1000 +U2 12 6 5 d_and +U3 12 6 10 d_or +U4 5 10 1 d_nor +U5 5 10 9 d_nand +U6 1 11 d_inverter +U7 9 11 4 d_xor +U8 4 3 dac_bridge_1 +U1 8 7 12 6 adc_bridge_2 +v2 8 0 pulse +v1 7 0 pulse + +.end diff --git a/Examples/BasicGates/BasicGates.cir (copy).out b/Examples/BasicGates/BasicGates.cir (copy).out new file mode 100644 index 00000000..4c57b83b --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir (copy).out @@ -0,0 +1,66 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 29 december 2014 04:59:08 pm utc + +* Plotting option vplot8_1 +* 74hc86 +* 74ls32 +* 74ls08 +* 74hc02 +* 74hc04 +* 7400 +r3 8 0 1000 +v2 8 0 pulse(0 5 0 0 0 2 20) +r2 9 0 1000 +r1 4 0 1000 +v1 4 0 pulse(5 0 0 0 0 2 20) +a1 [5] [5_in] u12adc +a2 [6] [6_in] u12adc +a3 [5_in 6_in] 9_out u12 +a4 [9_out] [9] u12dac +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a5 [8] [8_in] u8adc +a6 [4] [4_in] u8adc +a7 [8_in 4_in] 10_out u8 +a8 [10_out] [10] u8dac +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a9 [8] [8_in] u7adc +a10 [4] [4_in] u7adc +a11 [8_in 4_in] 2_out u7 +a12 [2_out] [2] u7dac +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a13 [2] [2_in] u9adc +a14 [10] [10_in] u9adc +a15 [2_in 10_in] 7_out u9 +a16 [7_out] [7] u9dac +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a17 [7] [7_in] u11adc +a18 7_in 6_out u11 +a19 [6_out] [6] u11dac +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a20 [2] [2_in] u10adc +a21 [10] [10_in] u10adc +a22 [2_in 10_in] 5_out u10 +a23 [5_out] [5] u10dac +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 + +* Control Statements +.control +run +plot v(8) v(4) v(9) +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/BasicGates/BasicGates.cir.ckt b/Examples/BasicGates/BasicGates.cir.ckt new file mode 100644 index 00000000..59b85ffa --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir.ckt @@ -0,0 +1,59 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 29 december 2014 04:59:08 pm utc + +* Plotting option vplot8_1 +* 74hc86 +* 74ls32 +* 74ls08 +* 74hc02 +* 74hc04 +* 7400 +r3 8 0 1000 +v2 8 0 pulse(0 5 0 0 0 2 20) +r2 9 0 1000 +r1 4 0 1000 +v1 4 0 pulse(5 0 0 0 0 2 20) +a1 [5] [5_in] u12adc +a2 [6] [6_in] u12adc +a3 [5_in 6_in] 9_out u12 +a4 [9_out] [9] u12dac +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a5 [8] [8_in] u8adc +a6 [4] [4_in] u8adc +a7 [8_in 4_in] 10_out u8 +a8 [10_out] [10] u8dac +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a9 [8] [8_in] u7adc +a10 [4] [4_in] u7adc +a11 [8_in 4_in] 2_out u7 +a12 [2_out] [2] u7dac +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a13 [2] [2_in] u9adc +a14 [10] [10_in] u9adc +a15 [2_in 10_in] 7_out u9 +a16 [7_out] [7] u9dac +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a17 [7] [7_in] u11adc +a18 7_in 6_out u11 +a19 [6_out] [6] u11dac +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +a20 [2] [2_in] u10adc +a21 [10] [10_in] u10adc +a22 [2_in 10_in] 5_out u10 +a23 [5_out] [5] u10dac +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.tran 10e-09 1e-06 0e-00 +.plot v(8) v(4) v(9) +.end diff --git a/Examples/BasicGates/BasicGates.cir.out b/Examples/BasicGates/BasicGates.cir.out new file mode 100644 index 00000000..69c4d9ee --- /dev/null +++ b/Examples/BasicGates/BasicGates.cir.out @@ -0,0 +1,48 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015 + +r3 8 0 1000 +r2 3 0 1000 +r1 7 0 1000 +* u2 12 6 5 d_and +* u3 12 6 10 d_or +* u4 5 10 1 d_nor +* u5 5 10 9 d_nand +* u6 1 11 d_inverter +* u7 9 11 4 d_xor +* u8 4 3 dac_bridge_1 +* u1 8 7 12 6 adc_bridge_2 +v2 8 0 pulse(0 5 0.1u 0.1u 0.1u 2u 20u) +v1 7 0 pulse(5 0 0.1u 0.1u 0.1u 2u 20u) +a1 [12 6 ] 5 u2 +a2 [12 6 ] 10 u3 +a3 [5 10 ] 1 u4 +a4 [5 10 ] 9 u5 +a5 1 11 u6 +a6 [9 11 ] 4 u7 +a7 [4 ] [3 ] u8 +a8 [8 7 ] [12 6 ] u1 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +.tran 10e-06 30e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/BasicGates/BasicGates.cmp b/Examples/BasicGates/BasicGates.cmp new file mode 100644 index 00000000..70877a7f --- /dev/null +++ b/Examples/BasicGates/BasicGates.cmp @@ -0,0 +1,101 @@ +Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 05:06:15 PM IST + +BeginCmp +TimeStamp = /505C9F25; +Reference = R1; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /50652FB6; +Reference = R2; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /507251A7; +Reference = R3; +ValeurCmp = 1000; +IdModule = R3; +EndCmp + +BeginCmp +TimeStamp = /505FD8A0; +Reference = U3; +ValeurCmp = ADC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /505FDC21; +Reference = U4; +ValeurCmp = DAC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725212; +Reference = U6; +ValeurCmp = ADC; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725428; +Reference = U7; +ValeurCmp = 74LS08; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725446; +Reference = U8; +ValeurCmp = 74LS32; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725415; +Reference = U9; +ValeurCmp = 74HC02; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /5072539F; +Reference = U10; +ValeurCmp = 7400; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /507253DF; +Reference = U11; +ValeurCmp = 74HC04; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /507253B2; +Reference = U12; +ValeurCmp = 74HC86; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /505C9ECF; +Reference = v1; +ValeurCmp = PULSE; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /50725192; +Reference = v2; +ValeurCmp = PULSE; +IdModule = ; +EndCmp + +EndListe diff --git a/Examples/BasicGates/BasicGates.net b/Examples/BasicGates/BasicGates.net new file mode 100644 index 00000000..e5b57d39 --- /dev/null +++ b/Examples/BasicGates/BasicGates.net @@ -0,0 +1,112 @@ +# EESchema Netlist Version 1.1 created Monday 22 October 2012 05:06:15 PM IST +( + ( /505C9F25 R3 R1 1000 + ( 1 N-000006 ) + ( 2 GND ) + ) + ( /50652FB6 R3 R2 1000 + ( 1 N-000007 ) + ( 2 GND ) + ) + ( /507251A7 R3 R3 1000 + ( 1 N-000009 ) + ( 2 GND ) + ) + ( /505FD8A0 $noname$ U3 ADC + ( 1 N-000006 ) + ( 2 N-000005 ) + ) + ( /505FDC21 $noname$ U4 DAC + ( 1 N-000008 ) + ( 2 N-000007 ) + ) + ( /50725212 $noname$ U6 ADC + ( 1 N-000009 ) + ( 2 N-000011 ) + ) + ( /50725428 $noname$ U7 74LS08 + ( 1 N-000011 ) + ( 2 N-000005 ) + ( 3 N-000003 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /50725446 $noname$ U8 74LS32 + ( 1 N-000011 ) + ( 2 N-000005 ) + ( 3 N-000013 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /50725415 $noname$ U9 74HC02 + ( 1 N-000004 ) + ( 2 N-000003 ) + ( 3 N-000013 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /5072539F $noname$ U10 7400 + ( 1 N-000003 ) + ( 2 N-000013 ) + ( 3 N-000010 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /507253DF $noname$ U11 74HC04 + ( 1 N-000004 ) + ( 2 N-000012 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /507253B2 $noname$ U12 74HC86 + ( 1 N-000010 ) + ( 2 N-000012 ) + ( 3 N-000008 ) + ( 7 GND ) + ( 14 VCC ) + ) + ( /505C9ECF $noname$ v1 PULSE + ( 1 N-000006 ) + ( 2 GND ) + ) + ( /50725192 $noname$ v2 PULSE + ( 1 N-000009 ) + ( 2 GND ) + ) +) +* +{ Allowed footprints by component: +$component R1 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R2 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R3 + R? + SM0603 + SM0805 + R?-* +$endlist +$component U9 + SO14* + 14DIP* +$endlist +$component U10 + 14DIP300* + SO14* +$endlist +$component v1 + 1_pin +$endlist +$component v2 + 1_pin +$endlist +$endfootprintlist +} diff --git a/Examples/BasicGates/BasicGates.pro b/Examples/BasicGates/BasicGates.pro new file mode 100644 index 00000000..32036155 --- /dev/null +++ b/Examples/BasicGates/BasicGates.pro @@ -0,0 +1,41 @@ +update=Mon Jun 8 14:03:30 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources diff --git a/Examples/BasicGates/BasicGates.proj b/Examples/BasicGates/BasicGates.proj new file mode 100644 index 00000000..f8a0441b --- /dev/null +++ b/Examples/BasicGates/BasicGates.proj @@ -0,0 +1 @@ +schematicFile BasicGates.sch diff --git a/Examples/BasicGates/BasicGates.sch b/Examples/BasicGates/BasicGates.sch new file mode 100644 index 00000000..0b7634cd --- /dev/null +++ b/Examples/BasicGates/BasicGates.sch @@ -0,0 +1,407 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:BasicGates-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "9 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 9150 2850 0 60 ~ 0 +~A.B +Text Notes 9050 2850 0 60 ~ 0 ++ +Text Notes 8900 2850 0 60 ~ 0 +A.B +Text Notes 8000 2300 0 60 ~ 0 +~B +Text Notes 7900 2300 0 60 ~ 0 ++ +Text Notes 7750 2300 0 60 ~ 0 +=~A +Text Notes 7900 3650 0 60 ~ 0 +=A+B +Text Notes 7850 3500 0 60 ~ 0 +A.B+A+B +Text Notes 6450 3600 0 60 ~ 0 +~((A.B)+(A+B)) +Text Notes 7100 2300 0 60 ~ 0 +~((A.B).(A+B)) +Text Notes 5150 3650 0 60 ~ 0 +A+B +Text Notes 5100 2250 0 60 ~ 0 +A.B +Text Notes 3600 3950 0 60 ~ 0 +B +Text Notes 3500 1650 0 60 ~ 0 +A +$Comp +L GND #PWR01 +U 1 1 5072534B +P 10850 3900 +F 0 "#PWR01" H 10850 3900 30 0001 C CNN +F 1 "GND" H 10850 3830 30 0001 C CNN +F 2 "" H 10850 3900 60 0001 C CNN +F 3 "" H 10850 3900 60 0001 C CNN + 1 10850 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 507251F2 +P 1800 1700 +F 0 "#FLG02" H 1800 1970 30 0001 C CNN +F 1 "PWR_FLAG" H 1800 1930 30 0000 C CNN +F 2 "" H 1800 1700 60 0001 C CNN +F 3 "" H 1800 1700 60 0001 C CNN + 1 1800 1700 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 507251E5 +P 2050 1250 +F 0 "#PWR03" H 2050 1250 30 0001 C CNN +F 1 "GND" H 2050 1180 30 0001 C CNN +F 2 "" H 2050 1250 60 0001 C CNN +F 3 "" H 2050 1250 60 0001 C CNN + 1 2050 1250 + -1 0 0 1 +$EndComp +$Comp +L R R3 +U 1 1 507251A7 +P 1400 2200 +F 0 "R3" V 1480 2200 50 0000 C CNN +F 1 "1000" V 1400 2200 50 0000 C CNN +F 2 "" H 1400 2200 60 0001 C CNN +F 3 "" H 1400 2200 60 0001 C CNN + 1 1400 2200 + -1 0 0 1 +$EndComp +$Comp +L R R2 +U 1 1 50652FB6 +P 10850 3350 +F 0 "R2" V 10930 3350 50 0000 C CNN +F 1 "1000" V 10850 3350 50 0000 C CNN +F 2 "" H 10850 3350 60 0001 C CNN +F 3 "" H 10850 3350 60 0001 C CNN + 1 10850 3350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 505C9F25 +P 2200 5100 +F 0 "R1" V 2280 5100 50 0000 C CNN +F 1 "1000" V 2200 5100 50 0000 C CNN +F 2 "" H 2200 5100 60 0001 C CNN +F 3 "" H 2200 5100 60 0001 C CNN + 1 2200 5100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 505C9EE8 +P 1650 5900 +F 0 "#PWR04" H 1650 5900 30 0001 C CNN +F 1 "GND" H 1650 5830 30 0001 C CNN +F 2 "" H 1650 5900 60 0001 C CNN +F 3 "" H 1650 5900 60 0001 C CNN + 1 1650 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5575A2C1 +P 4450 2350 +F 0 "U2" H 4450 2350 60 0000 C CNN +F 1 "d_and" H 4500 2450 60 0000 C CNN +F 2 "" H 4450 2350 60 0000 C CNN +F 3 "" H 4450 2350 60 0000 C CNN + 1 4450 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5575A328 +P 4550 3550 +F 0 "U3" H 4550 3550 60 0000 C CNN +F 1 "d_or" H 4550 3650 60 0000 C CNN +F 2 "" H 4550 3550 60 0000 C CNN +F 3 "" H 4550 3550 60 0000 C CNN + 1 4550 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 5575A38D +P 6200 3450 +F 0 "U4" H 6200 3450 60 0000 C CNN +F 1 "d_nor" H 6250 3550 60 0000 C CNN +F 2 "" H 6200 3450 60 0000 C CNN +F 3 "" H 6200 3450 60 0000 C CNN + 1 6200 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 5575A3E6 +P 6450 2450 +F 0 "U5" H 6450 2450 60 0000 C CNN +F 1 "d_nand" H 6500 2550 60 0000 C CNN +F 2 "" H 6450 2450 60 0000 C CNN +F 3 "" H 6450 2450 60 0000 C CNN + 1 6450 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5575A56B +P 7400 3400 +F 0 "U6" H 7400 3300 60 0000 C CNN +F 1 "d_inverter" H 7400 3550 60 0000 C CNN +F 2 "" H 7450 3350 60 0000 C CNN +F 3 "" H 7450 3350 60 0000 C CNN + 1 7400 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 5575A5B8 +P 8600 3050 +F 0 "U7" H 8600 3050 60 0000 C CNN +F 1 "d_xor" H 8650 3150 47 0000 C CNN +F 2 "" H 8600 3050 60 0000 C CNN +F 3 "" H 8600 3050 60 0000 C CNN + 1 8600 3050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U8 +U 1 1 5575A633 +P 9800 3050 +F 0 "U8" H 9800 3050 60 0000 C CNN +F 1 "dac_bridge_1" H 9800 3200 60 0000 C CNN +F 2 "" H 9800 3050 60 0000 C CNN +F 3 "" H 9800 3050 60 0000 C CNN + 1 9800 3050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U1 +U 1 1 5575A8EB +P 2850 3200 +F 0 "U1" H 2850 3200 60 0000 C CNN +F 1 "adc_bridge_2" H 2850 3350 60 0000 C CNN +F 2 "" H 2850 3200 60 0000 C CNN +F 3 "" H 2850 3200 60 0000 C CNN + 1 2850 3200 + 1 0 0 -1 +$EndComp +$Comp +L pulse v2 +U 1 1 5575AD50 +P 2050 2150 +F 0 "v2" H 1850 2250 60 0000 C CNN +F 1 "pulse" H 1850 2100 60 0000 C CNN +F 2 "R1" H 1750 2150 60 0000 C CNN +F 3 "" H 2050 2150 60 0000 C CNN + 1 2050 2150 + -1 0 0 1 +$EndComp +$Comp +L pulse v1 +U 1 1 5575AE1A +P 1650 5100 +F 0 "v1" H 1450 5200 60 0000 C CNN +F 1 "pulse" H 1450 5050 60 0000 C CNN +F 2 "R1" H 1350 5100 60 0000 C CNN +F 3 "" H 1650 5100 60 0000 C CNN + 1 1650 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1650 4500 2200 4500 +Wire Wire Line + 3500 3800 3750 3800 +Wire Wire Line + 7900 3100 7850 3100 +Wire Wire Line + 7850 3100 7850 3400 +Wire Wire Line + 7850 3400 7700 3400 +Connection ~ 5300 2300 +Wire Wire Line + 5300 2300 5300 3300 +Wire Wire Line + 5300 3300 5500 3300 +Wire Wire Line + 5000 3500 5500 3500 +Wire Wire Line + 7900 2900 7350 2900 +Wire Wire Line + 7350 2900 7350 2400 +Wire Wire Line + 7350 2400 6900 2400 +Connection ~ 3750 2200 +Wire Wire Line + 3900 3400 3750 3400 +Wire Wire Line + 3750 3400 3750 2200 +Wire Wire Line + 3650 2200 3850 2200 +Wire Wire Line + 3650 1700 3650 2200 +Connection ~ 1400 2750 +Connection ~ 1800 1500 +Wire Wire Line + 1800 1500 1800 1700 +Wire Wire Line + 2200 4500 2200 4950 +Wire Wire Line + 1650 4500 1650 4650 +Wire Wire Line + 1400 1500 1400 2050 +Wire Wire Line + 1400 1500 2050 1500 +Connection ~ 1650 5750 +Wire Wire Line + 2200 5750 1650 5750 +Wire Wire Line + 2200 5250 2200 5750 +Wire Wire Line + 1650 5550 1650 5900 +Wire Wire Line + 2050 2600 2050 3150 +Wire Wire Line + 1400 2350 1400 2750 +Wire Wire Line + 2050 1700 2050 1250 +Connection ~ 2050 1500 +Wire Wire Line + 3900 3600 3750 3600 +Wire Wire Line + 3750 3600 3750 3800 +Wire Wire Line + 3600 2350 3600 3800 +Wire Wire Line + 4900 2300 5800 2300 +Wire Wire Line + 5800 2500 5200 2500 +Wire Wire Line + 5200 2500 5200 3500 +Connection ~ 5200 3500 +Wire Wire Line + 6650 3400 7100 3400 +Wire Wire Line + 10850 3500 10850 3900 +Connection ~ 3600 3800 +Wire Wire Line + 3400 3250 3500 3250 +Wire Wire Line + 3500 3250 3500 3800 +Wire Wire Line + 3500 3150 3400 3150 +Wire Wire Line + 3500 1700 3500 3150 +Wire Wire Line + 3500 1700 3650 1700 +Wire Wire Line + 2050 3150 2250 3150 +Wire Wire Line + 1400 2750 2050 2750 +Connection ~ 2050 2750 +Wire Wire Line + 2250 3250 2050 3250 +Wire Wire Line + 2050 3250 2050 4500 +Connection ~ 2050 4500 +Wire Wire Line + 3850 2200 3850 2250 +Wire Wire Line + 3850 2250 4000 2250 +Wire Wire Line + 4000 2350 3600 2350 +Wire Wire Line + 3900 3400 3900 3450 +Wire Wire Line + 3900 3450 4100 3450 +Wire Wire Line + 3900 3600 3900 3550 +Wire Wire Line + 3900 3550 4100 3550 +Wire Wire Line + 5800 2300 5800 2350 +Wire Wire Line + 5800 2350 6000 2350 +Wire Wire Line + 5800 2500 5800 2450 +Wire Wire Line + 5800 2450 6000 2450 +Wire Wire Line + 5500 3300 5500 3350 +Wire Wire Line + 5500 3350 5750 3350 +Wire Wire Line + 5500 3500 5500 3450 +Wire Wire Line + 5500 3450 5750 3450 +Wire Wire Line + 7900 2900 7900 2950 +Wire Wire Line + 7900 2950 8150 2950 +Wire Wire Line + 7900 3100 7900 3050 +Wire Wire Line + 7900 3050 8150 3050 +Wire Wire Line + 9050 3000 9200 3000 +Wire Wire Line + 10350 3000 10850 3000 +Wire Wire Line + 10850 3000 10850 3200 +$EndSCHEMATC diff --git a/Examples/BasicGates/BasicGates_Previous_Values.xml b/Examples/BasicGates/BasicGates_Previous_Values.xml new file mode 100644 index 00000000..b26b64e5 --- /dev/null +++ b/Examples/BasicGates/BasicGates_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0.1u</field3><field4 name="Rise Time">0.1u</field4><field5 name="Fall Time">0.1u</field5><field5 name="Pulse width">2u</field5><field5 name="Period">20u</field5></v2><v1 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">0</field2><field3 name="Delay Time">0.1u</field3><field4 name="Rise Time">0.1u</field4><field5 name="Fall Time">0.1u</field5><field5 name="Pulse width">2u</field5><field5 name="Period">20u</field5></v1></source><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_nand<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">dac_bridge<field19 name="Enter value for input load (default=1.0e-12)" /><field20 name="Enter value for out_low (default=0.0)" /><field21 name="Enter value for out_high (default=5.0)" /><field22 name="Enter the Rise Time (default=1.0e-9)" /><field23 name="Enter the Fall Time (default=1.0e-9)" /><field24 name="Enter value for out_undef (default=0.5)" /></u8><u1 name="type">adc_bridge<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter value for in_high (default=2.0)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter value for in_low (default=1.0)" /></u1></model><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">30</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/BasicGates/BasicGates_last_input.txt b/Examples/BasicGates/BasicGates_last_input.txt new file mode 100644 index 00000000..5d6f4aa4 --- /dev/null +++ b/Examples/BasicGates/BasicGates_last_input.txt @@ -0,0 +1,20 @@ +v2 8 0 pulse(0 5 0 0 0 2 20) +v1 4 0 pulse(5 0 0 0 0 2 20) +.model u12 d_xor +.model u12adc adc_bridge(in_low=0.8 in_high=2.0) +.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u8 d_or +.model u8adc adc_bridge(in_low=0.8 in_high=2.0) +.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u7 d_and +.model u7adc adc_bridge(in_low=0.8 in_high=2.0) +.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u9 d_nor +.model u9adc adc_bridge(in_low=0.8 in_high=2.0) +.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u11 d_inverter +.model u11adc adc_bridge(in_low=0.8 in_high=2.0) +.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) +.model u10 d_nand +.model u10adc adc_bridge(in_low=0.8 in_high=2.0) +.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) diff --git a/Examples/BasicGates/analysis b/Examples/BasicGates/analysis new file mode 100644 index 00000000..2acaeed9 --- /dev/null +++ b/Examples/BasicGates/analysis @@ -0,0 +1 @@ +.tran 10e-06 30e-06 0e-00
\ No newline at end of file diff --git a/Examples/BasicGates/plot_data_i.txt b/Examples/BasicGates/plot_data_i.txt new file mode 100644 index 00000000..dfea4f20 --- /dev/null +++ b/Examples/BasicGates/plot_data_i.txt @@ -0,0 +1,335 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015 +Transient Analysis Fri Jun 26 11:22:20 2015 +-------------------------------------------------------------------------------- +Index time a7#branch_1_0 v1#branch v2#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +1 1.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +2 2.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +3 4.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +4 8.000000e-09 0.000000e+00 -5.00000e-03 0.000000e+00 +5 1.600000e-08 0.000000e+00 -5.00000e-03 0.000000e+00 +6 3.200000e-08 0.000000e+00 -5.00000e-03 0.000000e+00 +7 6.400000e-08 0.000000e+00 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-3.58300e-04 +280 2.229287e-05 -1.50000e-04 -4.64370e-03 -3.56300e-04 +281 2.229290e-05 0.000000e+00 -4.64520e-03 -3.54800e-04 +282 2.229291e-05 0.000000e+00 -4.64560e-03 -3.54400e-04 +283 2.229293e-05 0.000000e+00 -4.64640e-03 -3.53600e-04 +284 2.229296e-05 0.000000e+00 -4.64800e-03 -3.52000e-04 +285 2.229302e-05 0.000000e+00 -4.65120e-03 -3.48800e-04 +286 2.229315e-05 0.000000e+00 -4.65760e-03 -3.42400e-04 + +Index time a7#branch_1_0 v1#branch v2#branch +-------------------------------------------------------------------------------- +287 2.229341e-05 0.000000e+00 -4.67040e-03 -3.29600e-04 +288 2.229392e-05 0.000000e+00 -4.69600e-03 -3.04000e-04 +289 2.229494e-05 0.000000e+00 -4.74720e-03 -2.52800e-04 +290 2.229699e-05 0.000000e+00 -4.84960e-03 -1.50400e-04 +291 2.230000e-05 0.000000e+00 -5.00000e-03 -2.66454e-17 +292 2.230041e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +293 2.230123e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +294 2.230287e-05 0.000000e+00 -5.00000e-03 0.000000e+00 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-5.00000e-03 0.000000e+00 +313 2.973845e-05 0.000000e+00 -5.00000e-03 0.000000e+00 +314 3.000000e-05 0.000000e+00 -5.00000e-03 0.000000e+00 diff --git a/Examples/BasicGates/plot_data_v.txt b/Examples/BasicGates/plot_data_v.txt new file mode 100644 index 00000000..99290538 --- /dev/null +++ b/Examples/BasicGates/plot_data_v.txt @@ -0,0 +1,335 @@ +* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015 +Transient Analysis Fri Jun 26 11:22:20 2015 +-------------------------------------------------------------------------------- +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 5.000000e+00 0.000000e+00 +1 1.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +2 2.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +3 4.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +4 8.000000e-09 0.000000e+00 5.000000e+00 0.000000e+00 +5 1.600000e-08 0.000000e+00 5.000000e+00 0.000000e+00 +6 3.200000e-08 0.000000e+00 5.000000e+00 0.000000e+00 +7 6.400000e-08 0.000000e+00 5.000000e+00 0.000000e+00 +8 1.000000e-07 0.000000e+00 5.000000e+00 0.000000e+00 +9 1.064000e-07 0.000000e+00 4.680000e+00 3.200000e-01 +10 1.192000e-07 0.000000e+00 4.040000e+00 9.600000e-01 +11 1.448000e-07 0.000000e+00 2.760000e+00 2.240000e+00 +12 1.488000e-07 0.000000e+00 2.560000e+00 2.440000e+00 +13 1.489000e-07 5.000000e-01 2.555000e+00 2.445000e+00 +14 1.491000e-07 1.500000e+00 2.545000e+00 2.455000e+00 +15 1.495000e-07 3.500000e+00 2.525000e+00 2.475000e+00 +16 1.498000e-07 5.000000e+00 2.510000e+00 2.490000e+00 +17 1.498800e-07 5.000000e+00 2.506000e+00 2.494000e+00 +18 1.500400e-07 5.000000e+00 2.498000e+00 2.502000e+00 +19 1.503600e-07 5.000000e+00 2.482000e+00 2.518000e+00 +20 1.510000e-07 5.000000e+00 2.450000e+00 2.550000e+00 +21 1.522800e-07 5.000000e+00 2.386000e+00 2.614000e+00 +22 1.548400e-07 5.000000e+00 2.258000e+00 2.742000e+00 +23 1.599600e-07 5.000000e+00 2.002000e+00 2.998000e+00 +24 1.702000e-07 5.000000e+00 1.490000e+00 3.510000e+00 +25 1.742000e-07 5.000000e+00 1.290000e+00 3.710000e+00 +26 1.742900e-07 4.550000e+00 1.285500e+00 3.714500e+00 +27 1.744700e-07 3.650000e+00 1.276500e+00 3.723500e+00 +28 1.748300e-07 1.850000e+00 1.258500e+00 3.741500e+00 +29 1.751000e-07 5.000000e-01 1.245000e+00 3.755000e+00 +30 1.751720e-07 5.000000e-01 1.241400e+00 3.758600e+00 +31 1.753160e-07 5.000000e-01 1.234200e+00 3.765800e+00 +32 1.756040e-07 5.000000e-01 1.219800e+00 3.780200e+00 +33 1.761800e-07 5.000000e-01 1.191000e+00 3.809000e+00 +34 1.773320e-07 5.000000e-01 1.133400e+00 3.866600e+00 +35 1.796360e-07 5.000000e-01 1.018200e+00 3.981800e+00 +36 1.842440e-07 5.000000e-01 7.878000e-01 4.212200e+00 +37 1.882440e-07 5.000000e-01 5.878000e-01 4.412200e+00 +38 1.882540e-07 4.500000e-01 5.873000e-01 4.412700e+00 +39 1.882740e-07 3.500000e-01 5.863000e-01 4.413700e+00 +40 1.883140e-07 1.500000e-01 5.843000e-01 4.415700e+00 +41 1.883440e-07 0.000000e+00 5.828000e-01 4.417200e+00 +42 1.883520e-07 0.000000e+00 5.824000e-01 4.417600e+00 +43 1.883680e-07 0.000000e+00 5.816000e-01 4.418400e+00 +44 1.884000e-07 0.000000e+00 5.800000e-01 4.420000e+00 +45 1.884640e-07 0.000000e+00 5.768000e-01 4.423200e+00 +46 1.885920e-07 0.000000e+00 5.704000e-01 4.429600e+00 +47 1.888480e-07 0.000000e+00 5.576000e-01 4.442400e+00 +48 1.893600e-07 0.000000e+00 5.320000e-01 4.468000e+00 +49 1.903840e-07 0.000000e+00 4.808000e-01 4.519200e+00 +50 1.924320e-07 0.000000e+00 3.784000e-01 4.621600e+00 +51 1.965280e-07 0.000000e+00 1.736000e-01 4.826400e+00 +52 2.000000e-07 0.000000e+00 0.000000e+00 5.000000e+00 +53 2.008192e-07 0.000000e+00 0.000000e+00 5.000000e+00 +54 2.024576e-07 0.000000e+00 0.000000e+00 5.000000e+00 + +Index time V(3) V(7) V(8) +-------------------------------------------------------------------------------- +55 2.057344e-07 0.000000e+00 0.000000e+00 5.000000e+00 +56 2.122880e-07 0.000000e+00 0.000000e+00 5.000000e+00 +57 2.253952e-07 0.000000e+00 0.000000e+00 5.000000e+00 +58 2.516096e-07 0.000000e+00 0.000000e+00 5.000000e+00 +59 3.040384e-07 0.000000e+00 0.000000e+00 5.000000e+00 +60 4.088960e-07 0.000000e+00 0.000000e+00 5.000000e+00 +61 6.186112e-07 0.000000e+00 0.000000e+00 5.000000e+00 +62 1.038042e-06 0.000000e+00 0.000000e+00 5.000000e+00 +63 1.638042e-06 0.000000e+00 0.000000e+00 5.000000e+00 +64 2.200000e-06 0.000000e+00 2.117582e-14 5.000000e+00 +65 2.210000e-06 0.000000e+00 5.000000e-01 4.500000e+00 +66 2.230000e-06 0.000000e+00 1.500000e+00 3.500000e+00 +67 2.234000e-06 0.000000e+00 1.700000e+00 3.300000e+00 +68 2.234010e-06 5.000000e-02 1.700500e+00 3.299500e+00 +69 2.234030e-06 1.500000e-01 1.701500e+00 3.298500e+00 +70 2.234070e-06 3.500000e-01 1.703500e+00 3.296500e+00 +71 2.234100e-06 5.000000e-01 1.705000e+00 3.295000e+00 +72 2.234108e-06 5.000000e-01 1.705400e+00 3.294600e+00 +73 2.234124e-06 5.000000e-01 1.706200e+00 3.293800e+00 +74 2.234156e-06 5.000000e-01 1.707800e+00 3.292200e+00 +75 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0.000000e+00 +126 2.306144e-06 0.000000e+00 5.000000e+00 0.000000e+00 +127 2.312698e-06 0.000000e+00 5.000000e+00 0.000000e+00 +128 2.325805e-06 0.000000e+00 5.000000e+00 0.000000e+00 +129 2.352019e-06 0.000000e+00 5.000000e+00 0.000000e+00 +130 2.404448e-06 0.000000e+00 5.000000e+00 0.000000e+00 +131 2.509306e-06 0.000000e+00 5.000000e+00 0.000000e+00 +132 2.719021e-06 0.000000e+00 5.000000e+00 0.000000e+00 +133 3.138451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +134 3.738451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +135 4.338451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +136 4.938451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +137 5.538451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +138 6.138451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +139 6.738451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +140 7.338451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +141 7.938451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +142 8.538451e-06 0.000000e+00 5.000000e+00 0.000000e+00 +143 9.138451e-06 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