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-rw-r--r--Examples/BasicGates/BasicGates-cache.bak324
-rw-r--r--Examples/BasicGates/BasicGates.bak422
-rw-r--r--Examples/BasicGates/BasicGates.cir.ckt59
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-Wire Wire Line
- 5200 2500 5200 3500
-Connection ~ 5200 3500
-Wire Wire Line
- 6650 3400 7100 3400
-Wire Wire Line
- 10850 3500 10850 3900
-Connection ~ 3600 3800
-Wire Wire Line
- 3400 3250 3500 3250
-Wire Wire Line
- 3500 3250 3500 3800
-Wire Wire Line
- 3500 3150 3400 3150
-Wire Wire Line
- 3500 1700 3500 3150
-Wire Wire Line
- 3500 1700 3650 1700
-Wire Wire Line
- 2050 3150 2250 3150
-Wire Wire Line
- 1400 2750 2050 2750
-Connection ~ 2050 2750
-Wire Wire Line
- 2250 3250 2050 3250
-Wire Wire Line
- 2050 3250 2050 4500
-Connection ~ 2050 4500
-Wire Wire Line
- 3850 2200 3850 2250
-Wire Wire Line
- 3850 2250 4000 2250
-Wire Wire Line
- 4000 2350 3600 2350
-Wire Wire Line
- 3900 3400 3900 3450
-Wire Wire Line
- 3900 3450 4100 3450
-Wire Wire Line
- 3900 3600 3900 3550
-Wire Wire Line
- 3900 3550 4100 3550
-Wire Wire Line
- 5800 2300 5800 2350
-Wire Wire Line
- 5800 2350 6000 2350
-Wire Wire Line
- 5800 2500 5800 2450
-Wire Wire Line
- 5800 2450 6000 2450
-Wire Wire Line
- 5500 3300 5500 3350
-Wire Wire Line
- 5500 3350 5750 3350
-Wire Wire Line
- 5500 3500 5500 3450
-Wire Wire Line
- 5500 3450 5750 3450
-Wire Wire Line
- 7900 2900 7900 2950
-Wire Wire Line
- 7900 2950 8150 2950
-Wire Wire Line
- 7900 3100 7900 3050
-Wire Wire Line
- 7900 3050 8150 3050
-Wire Wire Line
- 9050 3000 9200 3000
-Wire Wire Line
- 10350 3000 10850 3000
-Wire Wire Line
- 10850 3000 10850 3200
-Wire Wire Line
- 2200 2950 2050 2950
-Connection ~ 2050 2950
-Wire Wire Line
- 2250 3450 2050 3450
-Connection ~ 2050 3450
-Text GLabel 10700 2800 1 60 Input ~ 0
-OUT
-Wire Wire Line
- 10700 2800 10700 3000
-Connection ~ 10700 3000
-$EndSCHEMATC
diff --git a/Examples/BasicGates/BasicGates.cir.ckt b/Examples/BasicGates/BasicGates.cir.ckt
deleted file mode 100644
index 59b85ffa..00000000
--- a/Examples/BasicGates/BasicGates.cir.ckt
+++ /dev/null
@@ -1,59 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 29 december 2014 04:59:08 pm utc
-
-* Plotting option vplot8_1
-* 74hc86
-* 74ls32
-* 74ls08
-* 74hc02
-* 74hc04
-* 7400
-r3 8 0 1000
-v2 8 0 pulse(0 5 0 0 0 2 20)
-r2 9 0 1000
-r1 4 0 1000
-v1 4 0 pulse(5 0 0 0 0 2 20)
-a1 [5] [5_in] u12adc
-a2 [6] [6_in] u12adc
-a3 [5_in 6_in] 9_out u12
-a4 [9_out] [9] u12dac
-.model u12 d_xor
-.model u12adc adc_bridge(in_low=0.8 in_high=2.0)
-.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-a5 [8] [8_in] u8adc
-a6 [4] [4_in] u8adc
-a7 [8_in 4_in] 10_out u8
-a8 [10_out] [10] u8dac
-.model u8 d_or
-.model u8adc adc_bridge(in_low=0.8 in_high=2.0)
-.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-a9 [8] [8_in] u7adc
-a10 [4] [4_in] u7adc
-a11 [8_in 4_in] 2_out u7
-a12 [2_out] [2] u7dac
-.model u7 d_and
-.model u7adc adc_bridge(in_low=0.8 in_high=2.0)
-.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-a13 [2] [2_in] u9adc
-a14 [10] [10_in] u9adc
-a15 [2_in 10_in] 7_out u9
-a16 [7_out] [7] u9dac
-.model u9 d_nor
-.model u9adc adc_bridge(in_low=0.8 in_high=2.0)
-.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-a17 [7] [7_in] u11adc
-a18 7_in 6_out u11
-a19 [6_out] [6] u11dac
-.model u11 d_inverter
-.model u11adc adc_bridge(in_low=0.8 in_high=2.0)
-.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-a20 [2] [2_in] u10adc
-a21 [10] [10_in] u10adc
-a22 [2_in 10_in] 5_out u10
-a23 [5_out] [5] u10dac
-.model u10 d_nand
-.model u10adc adc_bridge(in_low=0.8 in_high=2.0)
-.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
-
-.tran 10e-09 1e-06 0e-00
-.plot v(8) v(4) v(9)
-.end