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+* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015
+
+r3 8 0 1000
+r2 3 0 1000
+r1 7 0 1000
+* u2 12 6 5 d_and
+* u3 12 6 10 d_or
+* u4 5 10 1 d_nor
+* u5 5 10 9 d_nand
+* u6 1 11 d_inverter
+* u7 9 11 4 d_xor
+* u8 4 3 dac_bridge_1
+* u1 8 7 12 6 adc_bridge_2
+v2 8 0 pulse(0 5 0.1u 0.1u 0.1u 2u 20u)
+v1 7 0 pulse(5 0 0.1u 0.1u 0.1u 2u 20u)
+a1 [12 6 ] 5 u2
+a2 [12 6 ] 10 u3
+a3 [5 10 ] 1 u4
+a4 [5 10 ] 9 u5
+a5 1 11 u6
+a6 [9 11 ] 4 u7
+a7 [4 ] [3 ] u8
+a8 [8 7 ] [12 6 ] u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+.tran 10e-06 30e-06 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end