diff options
Diffstat (limited to 'Examples/4_Input_OR_Characteristics')
17 files changed, 1915 insertions, 0 deletions
diff --git a/Examples/4_Input_OR_Characteristics/4072-cache.lib b/Examples/4_Input_OR_Characteristics/4072-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/4_Input_OR_Characteristics/4072.cir b/Examples/4_Input_OR_Characteristics/4072.cir new file mode 100644 index 00000000..0f2e56f0 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4072\4072.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 10:17:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_or
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_or
+
+.end
diff --git a/Examples/4_Input_OR_Characteristics/4072.cir.out b/Examples/4_Input_OR_Characteristics/4072.cir.out new file mode 100644 index 00000000..61e8e949 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
+
+* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
+a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/4_Input_OR_Characteristics/4072.pro b/Examples/4_Input_OR_Characteristics/4072.pro new file mode 100644 index 00000000..64662931 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072.pro @@ -0,0 +1,45 @@ +update=05/31/19 10:11:54
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/Examples/4_Input_OR_Characteristics/4072.sch b/Examples/4_Input_OR_Characteristics/4072.sch new file mode 100644 index 00000000..782d3e69 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072.sch @@ -0,0 +1,334 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:4002-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
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+Comment4 ""
+$EndDescr
+$Comp
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+F 2 "" H 4750 2900 60 0000 C CNN
+F 3 "" H 4750 2900 60 0000 C CNN
+ 1 4750 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
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+F 2 "" H 4750 3450 60 0000 C CNN
+F 3 "" H 4750 3450 60 0000 C CNN
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 5650 6000 6050 6000
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+NoConn ~ 5650 5550
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+NoConn ~ 5650 6000
+$Comp
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+F 1 "PORT" H 3850 2800 30 0000 C CNN
+F 2 "" H 3850 2800 60 0000 C CNN
+F 3 "" H 3850 2800 60 0000 C CNN
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+F 2 "" H 3900 3050 60 0000 C CNN
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+F 1 "PORT" H 6950 3050 30 0000 C CNN
+F 2 "" H 6950 3050 60 0000 C CNN
+F 3 "" H 6950 3050 60 0000 C CNN
+ 1 6950 3050
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+$EndComp
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+Wire Wire Line
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+F 2 "" H 4900 4100 60 0000 C CNN
+F 3 "" H 4900 4100 60 0000 C CNN
+ 1 4900 4100
+ 1 0 0 -1
+$EndComp
+$Comp
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+F 3 "" H 4900 4650 60 0000 C CNN
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+ 9 4000 4000
+ 1 0 0 -1
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+F 2 "" H 4050 4250 60 0000 C CNN
+F 3 "" H 4050 4250 60 0000 C CNN
+ 10 4050 4250
+ 1 0 0 -1
+$EndComp
+$Comp
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+F 2 "" H 4050 4450 60 0000 C CNN
+F 3 "" H 4050 4450 60 0000 C CNN
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+$EndComp
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+F 2 "" H 4050 4750 60 0000 C CNN
+F 3 "" H 4050 4750 60 0000 C CNN
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 6300 5350 60 0000 C CNN
+F 3 "" H 6300 5350 60 0000 C CNN
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+F 3 "" H 6300 6000 60 0000 C CNN
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+$Comp
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+U 1 1 5CF0D6D2
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+F 0 "U6" H 6000 3100 60 0000 C CNN
+F 1 "d_or" H 6000 3200 60 0000 C CNN
+F 2 "" H 6000 3100 60 0000 C CNN
+F 3 "" H 6000 3100 60 0000 C CNN
+ 1 6000 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U7
+U 1 1 5CF0D73F
+P 6150 4300
+F 0 "U7" H 6150 4300 60 0000 C CNN
+F 1 "d_or" H 6150 4400 60 0000 C CNN
+F 2 "" H 6150 4300 60 0000 C CNN
+F 3 "" H 6150 4300 60 0000 C CNN
+ 1 6150 4300
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diff --git a/Examples/4_Input_OR_Characteristics/4072.sub b/Examples/4_Input_OR_Characteristics/4072.sub new file mode 100644 index 00000000..174ea00d --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072.sub @@ -0,0 +1,30 @@ +* Subcircuit 4072
+.subckt 4072 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
+* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
+a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4072
\ No newline at end of file diff --git a/Examples/4_Input_OR_Characteristics/4072_Previous_Values.xml b/Examples/4_Input_OR_Characteristics/4072_Previous_Values.xml new file mode 100644 index 00000000..0ccd120c --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4072_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_or<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics-cache.lib b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics-cache.lib new file mode 100644 index 00000000..ec807bec --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics-cache.lib @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# IC_4072 +# +DEF IC_4072 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4072" 0 -100 60 V V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -300 400 200 -450 0 1 0 N +X 1Y 1 -500 300 200 R 50 50 1 1 O +X 1A 2 -500 200 200 R 50 50 1 1 I +X 1B 3 -500 100 200 R 50 50 1 1 I +X 1C 4 -500 0 200 R 50 50 1 1 I +X 1D 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 I +X GND 7 -500 -300 200 R 50 50 1 1 I +X NC 8 400 -300 200 L 50 50 1 1 I +X 2A 9 400 -200 200 L 50 50 1 1 I +X 2B 10 400 -100 200 L 50 50 1 1 I +X 2C 11 400 0 200 L 50 50 1 1 I +X 2D 12 400 100 200 L 50 50 1 1 I +X 2Y 13 400 200 200 L 50 50 1 1 O +X VCC 14 400 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir new file mode 100644 index 00000000..de9c73e3 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir @@ -0,0 +1,34 @@ +* /home/bhargav/eSim-Workspace/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jul 2 12:55:29 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 v1 v2 v3 v4 Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ adc_bridge_4 +U7 v8 v7 v6 v5 Net-_U7-Pad5_ Net-_U7-Pad6_ Net-_U7-Pad7_ Net-_U7-Pad8_ adc_bridge_4 +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ out1 out2 dac_bridge_2 +R1 out1 GND 1k +R2 out2 GND 1k +U9 out1 plot_v1 +U8 out2 plot_v1 +U13 v8 plot_v1 +U10 v7 plot_v1 +U11 v6 plot_v1 +U12 v5 plot_v1 +v7 v7 GND DC +v8 v8 GND DC +v5 v5 GND DC +v6 v6 GND DC +U4 v4 plot_v1 +U1 v3 plot_v1 +U3 v2 plot_v1 +U2 v1 plot_v1 +v4 v4 GND DC +v3 v3 GND DC +v2 v2 GND DC +v1 v1 GND DC +X1 Net-_U6-Pad1_ Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ ? ? ? Net-_U7-Pad5_ Net-_U7-Pad6_ Net-_U7-Pad7_ Net-_U7-Pad8_ Net-_U6-Pad2_ ? IC_4072 + +.end diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir.out b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir.out new file mode 100644 index 00000000..1ede879a --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.cir.out @@ -0,0 +1,55 @@ +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir + +.include 4072.sub +* u5 v1 v2 v3 v4 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4 +* u7 v8 v7 v6 v5 net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ adc_bridge_4 +* u6 net-_u6-pad1_ net-_u6-pad2_ out1 out2 dac_bridge_2 +r1 out1 gnd 1k +r2 out2 gnd 1k +* u9 out1 plot_v1 +* u8 out2 plot_v1 +* u13 v8 plot_v1 +* u10 v7 plot_v1 +* u11 v6 plot_v1 +* u12 v5 plot_v1 +v7 v7 gnd dc 0 +v8 v8 gnd dc 0 +v5 v5 gnd dc 0 +v6 v6 gnd dc 0 +* u4 v4 plot_v1 +* u1 v3 plot_v1 +* u3 v2 plot_v1 +* u2 v1 plot_v1 +v4 v4 gnd dc 0 +v3 v3 gnd dc 0 +v2 v2 gnd dc 0 +v1 v1 gnd dc 0 +x1 net-_u6-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ net-_u6-pad2_ ? 4072 +a1 [v1 v2 v3 v4 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5 +a2 [v8 v7 v6 v5 ] [net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ ] u7 +a3 [net-_u6-pad1_ net-_u6-pad2_ ] [out1 out2 ] u6 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u7 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 1e-03 10e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out1) +plot v(out2) +plot v(v8) +plot v(v7) +plot v(v6) +plot v(v5) +plot v(v4) +plot v(v3) +plot v(v2) +plot v(v1) +.endc +.end diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.pro b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.pro new file mode 100644 index 00000000..148e9ed5 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice + diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.proj b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.proj new file mode 100644 index 00000000..a541a01e --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.proj @@ -0,0 +1 @@ +schematicFile 4_Input_OR_Characteristics.sch diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.sch b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.sch new file mode 100644 index 00000000..ab03f735 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics.sch @@ -0,0 +1,542 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:4_Input_OR_Characteristics-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L adc_bridge_4 U5 +U 1 1 5D1B0791 +P 4350 3450 +F 0 "U5" H 4350 3450 60 0000 C CNN +F 1 "adc_bridge_4" H 4350 3750 60 0000 C CNN +F 2 "" H 4350 3450 60 0000 C CNN +F 3 "" H 4350 3450 60 0000 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U7 +U 1 1 5D1B0792 +P 6650 3450 +F 0 "U7" H 6650 3450 60 0000 C CNN +F 1 "adc_bridge_4" H 6650 3750 60 0000 C CNN +F 2 "" H 6650 3450 60 0000 C CNN +F 3 "" H 6650 3450 60 0000 C CNN + 1 6650 3450 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_2 U6 +U 1 1 5D1B0793 +P 6200 2350 +F 0 "U6" H 6200 2350 60 0000 C CNN +F 1 "dac_bridge_2" H 6250 2500 60 0000 C CNN +F 2 "" H 6200 2350 60 0000 C CNN +F 3 "" H 6200 2350 60 0000 C CNN + 1 6200 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5D1B0794 +P 7000 2350 +F 0 "R1" H 7050 2480 50 0000 C CNN +F 1 "1k" H 7050 2400 50 0000 C CNN +F 2 "" H 7050 2330 30 0000 C CNN +F 3 "" V 7050 2400 30 0000 C CNN + 1 7000 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5D1B0795 +P 7000 2450 +F 0 "R2" H 7050 2580 50 0000 C CNN +F 1 "1k" H 7050 2500 50 0000 C CNN +F 2 "" H 7050 2430 30 0000 C CNN +F 3 "" V 7050 2500 30 0000 C CNN + 1 7000 2450 + 1 0 0 -1 +$EndComp +NoConn ~ 5050 3750 +NoConn ~ 5050 3650 +NoConn ~ 5950 3750 +NoConn ~ 5950 3150 +$Comp +L plot_v1 U9 +U 1 1 5D1B0796 +P 6800 2300 +F 0 "U9" H 6800 2800 60 0000 C CNN +F 1 "plot_v1" H 7000 2650 60 0000 C CNN +F 2 "" H 6800 2300 60 0000 C CNN +F 3 "" H 6800 2300 60 0000 C CNN + 1 6800 2300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 5D1B0797 +P 6750 2350 +F 0 "U8" H 6750 2850 60 0000 C CNN +F 1 "plot_v1" H 6950 2700 60 0000 C CNN +F 2 "" H 6750 2350 60 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 1 6750 2350 + -1 0 0 1 +$EndComp +Text GLabel 6950 2150 2 60 Input ~ 0 +out1 +Text GLabel 6850 2500 2 60 Input ~ 0 +out2 +Wire Wire Line + 3150 3250 3800 3250 +Wire Wire Line + 3150 3350 3800 3350 +Wire Wire Line + 3200 3450 3800 3450 +Wire Wire Line + 3200 3550 3800 3550 +Wire Wire Line + 6100 3350 5950 3350 +Wire Wire Line + 6100 3450 5950 3450 +Wire Wire Line + 6100 3550 5950 3550 +Wire Wire Line + 6100 3650 5950 3650 +Wire Wire Line + 7200 3350 7750 3350 +Wire Wire Line + 7200 3450 7750 3450 +Wire Wire Line + 7200 3550 7750 3550 +Wire Wire Line + 7200 3650 7750 3650 +Wire Wire Line + 8700 4050 8700 2350 +Wire Wire Line + 4900 3250 5050 3250 +Wire Wire Line + 4900 3350 5050 3350 +Wire Wire Line + 4900 3450 5050 3450 +Wire Wire Line + 4900 3550 5050 3550 +Wire Wire Line + 5050 3150 4950 3150 +Wire Wire Line + 4950 3150 4950 2300 +Wire Wire Line + 4950 2300 5750 2300 +Wire Wire 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3600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5D1B079D +P 7700 3500 +F 0 "U12" H 7700 4000 60 0000 C CNN +F 1 "plot_v1" H 7900 3850 60 0000 C CNN +F 2 "" H 7700 3500 60 0000 C CNN +F 3 "" H 7700 3500 60 0000 C CNN + 1 7700 3500 + 1 0 0 -1 +$EndComp +$Comp +L DC v7 +U 1 1 5D1B079E +P 8200 3550 +F 0 "v7" H 8000 3650 60 0000 C CNN +F 1 "DC" H 8000 3500 60 0000 C CNN +F 2 "R1" H 7900 3550 60 0000 C CNN +F 3 "" H 8200 3550 60 0000 C CNN + 1 8200 3550 + 0 -1 1 0 +$EndComp +$Comp +L DC v8 +U 1 1 5D1B079F +P 8200 3650 +F 0 "v8" H 8000 3750 60 0000 C CNN +F 1 "DC" H 8000 3600 60 0000 C CNN +F 2 "R1" H 7900 3650 60 0000 C CNN +F 3 "" H 8200 3650 60 0000 C CNN + 1 8200 3650 + 0 -1 1 0 +$EndComp +$Comp +L DC v5 +U 1 1 5D1B07A0 +P 8200 3350 +F 0 "v5" H 8000 3450 60 0000 C CNN +F 1 "DC" H 8000 3300 60 0000 C CNN +F 2 "R1" H 7900 3350 60 0000 C CNN +F 3 "" H 8200 3350 60 0000 C CNN + 1 8200 3350 + 0 -1 1 0 +$EndComp +$Comp +L DC v6 +U 1 1 5D1B07A1 +P 8200 3450 +F 0 "v6" H 8000 3550 60 0000 C CNN +F 1 "DC" H 8000 3400 60 0000 C CNN +F 2 "R1" H 7900 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 1 8200 3450 + 0 -1 1 0 +$EndComp +Connection ~ 3300 3350 +Wire Wire Line + 3300 3150 3300 3350 +Wire Wire Line + 3100 3150 3300 3150 +Connection ~ 3350 3250 +Wire Wire Line + 3350 3100 3350 3250 +Wire Wire Line + 3500 3100 3350 3100 +Connection ~ 3400 3600 +Wire Wire Line + 3500 3600 3400 3600 +Wire Wire Line + 3500 3750 3500 3600 +Connection ~ 3250 3700 +Wire Wire Line + 3050 3700 3250 3700 +Wire Wire Line + 3250 3600 3250 3850 +Connection ~ 3400 3550 +Wire Wire Line + 3400 3550 3400 3650 +Connection ~ 2200 3550 +Wire Wire Line + 3250 3600 3200 3450 +Connection ~ 3250 3350 +Wire Wire Line + 3250 3300 3250 3350 +Connection ~ 3200 3250 +Wire Wire Line + 3200 3200 3200 3250 +Connection ~ 2200 3350 +Wire Wire Line + 2250 3350 2200 3350 +Connection ~ 2200 3450 +Wire Wire Line + 2300 3450 2200 3450 +Wire Wire Line + 2050 3550 2300 3550 +Wire Wire Line + 2200 3250 2200 3550 +Wire Wire Line + 2250 3250 2200 3250 +Text GLabel 3500 3750 2 60 Input ~ 0 +v4 +Text GLabel 3050 3700 0 60 Input ~ 0 +v3 +Text GLabel 3100 3150 0 60 Input ~ 0 +v2 +Text GLabel 3500 3100 2 60 Input ~ 0 +v1 +$Comp +L plot_v1 U4 +U 1 1 5D1B07A2 +P 3400 3450 +F 0 "U4" H 3400 3950 60 0000 C CNN +F 1 "plot_v1" H 3600 3800 60 0000 C CNN +F 2 "" H 3400 3450 60 0000 C CNN +F 3 "" H 3400 3450 60 0000 C CNN + 1 3400 3450 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5D1B07A3 +P 3050 3850 +F 0 "U1" H 3050 4350 60 0000 C CNN +F 1 "plot_v1" H 3250 4200 60 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 1 3050 3850 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5D1B07A4 +P 3250 3500 +F 0 "U3" H 3250 4000 60 0000 C CNN +F 1 "plot_v1" H 3450 3850 60 0000 C CNN +F 2 "" H 3250 3500 60 0000 C CNN +F 3 "" H 3250 3500 60 0000 C CNN + 1 3250 3500 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5D1B07A5 +P 3200 3400 +F 0 "U2" H 3200 3900 60 0000 C CNN +F 1 "plot_v1" H 3400 3750 60 0000 C CNN +F 2 "" H 3200 3400 60 0000 C CNN +F 3 "" H 3200 3400 60 0000 C CNN + 1 3200 3400 + 1 0 0 -1 +$EndComp +$Comp +L DC v4 +U 1 1 5D1B07A6 +P 2750 3550 +F 0 "v4" H 2550 3650 60 0000 C CNN +F 1 "DC" H 2550 3500 60 0000 C CNN +F 2 "R1" H 2450 3550 60 0000 C CNN +F 3 "" H 2750 3550 60 0000 C CNN + 1 2750 3550 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5D1B07A7 +P 2750 3450 +F 0 "v3" H 2550 3550 60 0000 C CNN +F 1 "DC" H 2550 3400 60 0000 C CNN +F 2 "R1" H 2450 3450 60 0000 C CNN +F 3 "" H 2750 3450 60 0000 C CNN + 1 2750 3450 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 5D1B07A8 +P 2700 3350 +F 0 "v2" H 2500 3450 60 0000 C CNN +F 1 "DC" H 2500 3300 60 0000 C CNN +F 2 "R1" H 2400 3350 60 0000 C CNN +F 3 "" H 2700 3350 60 0000 C CNN + 1 2700 3350 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5D1B07A9 +P 2700 3250 +F 0 "v1" H 2500 3350 60 0000 C CNN +F 1 "DC" H 2500 3200 60 0000 C CNN +F 2 "R1" H 2400 3250 60 0000 C CNN +F 3 "" H 2700 3250 60 0000 C CNN + 1 2700 3250 + 0 1 1 0 +$EndComp +Connection ~ 6800 2300 +Wire Wire Line + 6750 2450 6800 2450 +Wire Wire Line + 6800 2450 6800 2400 +Connection ~ 6800 2400 +$Comp +L IC_4072 X1 +U 1 1 5D1B07AA +P 5550 3450 +F 0 "X1" H 5550 3600 60 0000 C CNN +F 1 "IC_4072" V 5550 3350 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5550 3450 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics_Previous_Values.xml b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics_Previous_Values.xml new file mode 100644 index 00000000..8ffe0e91 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/4_Input_OR_Characteristics_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model><u5 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u5><u7 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u7><u6 name="type">dac_bridge<field9 name="Enter value for input load (default=1.0e-12)" /><field10 name="Enter value for out_low (default=0.0)" /><field11 name="Enter value for out_high (default=5.0)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /><field14 name="Enter value for out_undef (default=0.5)" /></u6></model><devicemodel /><subcircuit><x1><field>/home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4072</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/4_Input_OR_Characteristics/analysis b/Examples/4_Input_OR_Characteristics/analysis new file mode 100644 index 00000000..63cae415 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/analysis @@ -0,0 +1 @@ +.tran 1e-03 10e-03 0e-03
\ No newline at end of file diff --git a/Examples/4_Input_OR_Characteristics/plot_data_i.txt b/Examples/4_Input_OR_Characteristics/plot_data_i.txt new file mode 100644 index 00000000..99ed8606 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/plot_data_i.txt @@ -0,0 +1,271 @@ +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir +Transient Analysis Tue Jul 2 12:56:05 2019 +-------------------------------------------------------------------------------- +Index time a3#branch_1_0 a3#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time a3#branch_1_0 a3#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +55 9.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir +Transient Analysis Tue Jul 2 12:56:05 2019 +-------------------------------------------------------------------------------- +Index time v2#branch v3#branch v4#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time v2#branch v3#branch v4#branch +-------------------------------------------------------------------------------- +55 9.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir +Transient Analysis Tue Jul 2 12:56:05 2019 +-------------------------------------------------------------------------------- +Index time v5#branch v6#branch v7#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-03 0.000000e+00 0.000000e+00 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0.000000e+00 +1 1.000000e-06 0.000000e+00 +2 2.000000e-06 0.000000e+00 +3 4.000000e-06 0.000000e+00 +4 8.000000e-06 0.000000e+00 +5 1.600000e-05 0.000000e+00 +6 3.200000e-05 0.000000e+00 +7 6.400000e-05 0.000000e+00 +8 1.280000e-04 0.000000e+00 +9 2.560000e-04 0.000000e+00 +10 4.560000e-04 0.000000e+00 +11 6.560000e-04 0.000000e+00 +12 8.560000e-04 0.000000e+00 +13 1.056000e-03 0.000000e+00 +14 1.256000e-03 0.000000e+00 +15 1.456000e-03 0.000000e+00 +16 1.656000e-03 0.000000e+00 +17 1.856000e-03 0.000000e+00 +18 2.056000e-03 0.000000e+00 +19 2.256000e-03 0.000000e+00 +20 2.456000e-03 0.000000e+00 +21 2.656000e-03 0.000000e+00 +22 2.856000e-03 0.000000e+00 +23 3.056000e-03 0.000000e+00 +24 3.256000e-03 0.000000e+00 +25 3.456000e-03 0.000000e+00 +26 3.656000e-03 0.000000e+00 +27 3.856000e-03 0.000000e+00 +28 4.056000e-03 0.000000e+00 +29 4.256000e-03 0.000000e+00 +30 4.456000e-03 0.000000e+00 +31 4.656000e-03 0.000000e+00 +32 4.856000e-03 0.000000e+00 +33 5.056000e-03 0.000000e+00 +34 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00000000..8c1a87b7 --- /dev/null +++ b/Examples/4_Input_OR_Characteristics/plot_data_v.txt @@ -0,0 +1,271 @@ +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir +Transient Analysis Tue Jul 2 12:56:05 2019 +-------------------------------------------------------------------------------- +Index time out1 out2 v1 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-06 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-04 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4.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time out1 out2 v1 +-------------------------------------------------------------------------------- +55 9.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir +Transient Analysis Tue Jul 2 12:56:05 2019 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8.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-03 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time v2 v3 v4 +-------------------------------------------------------------------------------- +55 9.456000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir +Transient Analysis Tue Jul 2 12:56:05 2019 +-------------------------------------------------------------------------------- +Index time v5 v6 v7 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-06 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