summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--library/SubcircuitLibrary/sn7445/analysis1
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445-cache.lib106
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.cir53
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.cir.out180
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.pro73
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.sch968
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445.sub174
-rw-r--r--library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml1
8 files changed, 1556 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/sn7445/analysis b/library/SubcircuitLibrary/sn7445/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/sn7445/sn7445-cache.lib b/library/SubcircuitLibrary/sn7445/sn7445-cache.lib
new file mode 100644
index 00000000..227513a4
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445-cache.lib
@@ -0,0 +1,106 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.cir b/library/SubcircuitLibrary/sn7445/sn7445.cir
new file mode 100644
index 00000000..853355c0
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.cir
@@ -0,0 +1,53 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\sn7445\sn7445.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 11/06/2024 7:04:06 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U34 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad1_ d_nand
+U35 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ d_nand
+U36 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U1-Pad3_ d_nand
+U43 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U1-Pad10_ d_nand
+U37 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U1-Pad4_ d_nand
+U38 Net-_U20-Pad3_ Net-_U25-Pad3_ Net-_U1-Pad5_ d_nand
+U39 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U1-Pad6_ d_nand
+U40 Net-_U26-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad7_ d_nand
+U41 Net-_U31-Pad3_ Net-_U27-Pad3_ Net-_U1-Pad8_ d_nand
+U42 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad9_ d_nand
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and
+U16 Net-_U10-Pad2_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and
+U17 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U17-Pad3_ d_and
+U18 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U18-Pad3_ d_and
+U19 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U19-Pad3_ d_and
+U23 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_and
+U24 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad3_ d_and
+U20 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U20-Pad3_ d_and
+U25 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U25-Pad3_ d_and
+U21 Net-_U10-Pad2_ Net-_U14-Pad2_ Net-_U21-Pad3_ d_and
+U22 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U22-Pad3_ d_and
+U26 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U26-Pad3_ d_and
+U30 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U30-Pad3_ d_and
+U31 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U31-Pad3_ d_and
+U27 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U27-Pad3_ d_and
+U28 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U28-Pad3_ d_and
+U29 Net-_U15-Pad1_ Net-_U12-Pad2_ Net-_U29-Pad3_ d_and
+U32 Net-_U10-Pad2_ Net-_U14-Pad2_ Net-_U32-Pad3_ d_and
+U33 Net-_U15-Pad1_ Net-_U12-Pad2_ Net-_U33-Pad3_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_buffer
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_buffer
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_buffer
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_buffer
+U8 Net-_U15-Pad2_ Net-_U12-Pad1_ d_inverter
+U5 Net-_U1-Pad11_ Net-_U15-Pad2_ d_inverter
+U9 Net-_U15-Pad1_ Net-_U13-Pad1_ d_inverter
+U4 Net-_U1-Pad12_ Net-_U15-Pad1_ d_inverter
+U7 Net-_U14-Pad2_ Net-_U11-Pad1_ d_inverter
+U3 Net-_U1-Pad13_ Net-_U14-Pad2_ d_inverter
+U6 Net-_U14-Pad1_ Net-_U10-Pad1_ d_inverter
+U2 Net-_U1-Pad14_ Net-_U14-Pad1_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.cir.out b/library/SubcircuitLibrary/sn7445/sn7445.cir.out
new file mode 100644
index 00000000..e53a66ee
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.cir.out
@@ -0,0 +1,180 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7445\sn7445.cir
+
+* u34 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad1_ d_nand
+* u35 net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ d_nand
+* u36 net-_u18-pad3_ net-_u19-pad3_ net-_u1-pad3_ d_nand
+* u43 net-_u32-pad3_ net-_u33-pad3_ net-_u1-pad10_ d_nand
+* u37 net-_u23-pad3_ net-_u24-pad3_ net-_u1-pad4_ d_nand
+* u38 net-_u20-pad3_ net-_u25-pad3_ net-_u1-pad5_ d_nand
+* u39 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad6_ d_nand
+* u40 net-_u26-pad3_ net-_u30-pad3_ net-_u1-pad7_ d_nand
+* u41 net-_u31-pad3_ net-_u27-pad3_ net-_u1-pad8_ d_nand
+* u42 net-_u28-pad3_ net-_u29-pad3_ net-_u1-pad9_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u10-pad2_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u15-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u14-pad1_ net-_u11-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u15-pad1_ net-_u15-pad2_ net-_u19-pad3_ d_and
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u15-pad1_ net-_u15-pad2_ net-_u24-pad3_ d_and
+* u20 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_and
+* u21 net-_u10-pad2_ net-_u14-pad2_ net-_u21-pad3_ d_and
+* u22 net-_u13-pad2_ net-_u15-pad2_ net-_u22-pad3_ d_and
+* u26 net-_u14-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_and
+* u30 net-_u13-pad2_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u31 net-_u10-pad2_ net-_u11-pad2_ net-_u31-pad3_ d_and
+* u27 net-_u13-pad2_ net-_u15-pad2_ net-_u27-pad3_ d_and
+* u28 net-_u14-pad1_ net-_u14-pad2_ net-_u28-pad3_ d_and
+* u29 net-_u15-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_and
+* u32 net-_u10-pad2_ net-_u14-pad2_ net-_u32-pad3_ d_and
+* u33 net-_u15-pad1_ net-_u12-pad2_ net-_u33-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_buffer
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_buffer
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u8 net-_u15-pad2_ net-_u12-pad1_ d_inverter
+* u5 net-_u1-pad11_ net-_u15-pad2_ d_inverter
+* u9 net-_u15-pad1_ net-_u13-pad1_ d_inverter
+* u4 net-_u1-pad12_ net-_u15-pad1_ d_inverter
+* u7 net-_u14-pad2_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u6 net-_u14-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad14_ net-_u14-pad1_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u1-pad1_ u34
+a2 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u1-pad2_ u35
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u1-pad3_ u36
+a4 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u1-pad10_ u43
+a5 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u1-pad4_ u37
+a6 [net-_u20-pad3_ net-_u25-pad3_ ] net-_u1-pad5_ u38
+a7 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad6_ u39
+a8 [net-_u26-pad3_ net-_u30-pad3_ ] net-_u1-pad7_ u40
+a9 [net-_u31-pad3_ net-_u27-pad3_ ] net-_u1-pad8_ u41
+a10 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u1-pad9_ u42
+a11 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a14 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u18-pad3_ u18
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u19-pad3_ u19
+a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a18 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20
+a20 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a21 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u21-pad3_ u21
+a22 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u22-pad3_ u22
+a23 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u26-pad3_ u26
+a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u31-pad3_ u31
+a26 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u27-pad3_ u27
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u28-pad3_ u28
+a28 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29
+a29 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u32-pad3_ u32
+a30 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u33-pad3_ u33
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u11-pad1_ net-_u11-pad2_ u11
+a33 net-_u13-pad1_ net-_u13-pad2_ u13
+a34 net-_u12-pad1_ net-_u12-pad2_ u12
+a35 net-_u15-pad2_ net-_u12-pad1_ u8
+a36 net-_u1-pad11_ net-_u15-pad2_ u5
+a37 net-_u15-pad1_ net-_u13-pad1_ u9
+a38 net-_u1-pad12_ net-_u15-pad1_ u4
+a39 net-_u14-pad2_ net-_u11-pad1_ u7
+a40 net-_u1-pad13_ net-_u14-pad2_ u3
+a41 net-_u14-pad1_ net-_u10-pad1_ u6
+a42 net-_u1-pad14_ net-_u14-pad1_ u2
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.pro b/library/SubcircuitLibrary/sn7445/sn7445.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.sch b/library/SubcircuitLibrary/sn7445/sn7445.sch
new file mode 100644
index 00000000..1c4acf18
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.sch
@@ -0,0 +1,968 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:7445-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 17000 15748
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U34
+U 1 1 666834D5
+P 10400 3850
+F 0 "U34" H 10400 3850 60 0000 C CNN
+F 1 "d_nand" H 10450 3950 60 0000 C CNN
+F 2 "" H 10400 3850 60 0000 C CNN
+F 3 "" H 10400 3850 60 0000 C CNN
+ 1 10400 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U35
+U 1 1 666834D6
+P 10450 4500
+F 0 "U35" H 10450 4500 60 0000 C CNN
+F 1 "d_nand" H 10500 4600 60 0000 C CNN
+F 2 "" H 10450 4500 60 0000 C CNN
+F 3 "" H 10450 4500 60 0000 C CNN
+ 1 10450 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U36
+U 1 1 666834D7
+P 10450 5200
+F 0 "U36" H 10450 5200 60 0000 C CNN
+F 1 "d_nand" H 10500 5300 60 0000 C CNN
+F 2 "" H 10450 5200 60 0000 C CNN
+F 3 "" H 10450 5200 60 0000 C CNN
+ 1 10450 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U43
+U 1 1 666834D8
+P 10450 9800
+F 0 "U43" H 10450 9800 60 0000 C CNN
+F 1 "d_nand" H 10500 9900 60 0000 C CNN
+F 2 "" H 10450 9800 60 0000 C CNN
+F 3 "" H 10450 9800 60 0000 C CNN
+ 1 10450 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U37
+U 1 1 666834D9
+P 10450 5900
+F 0 "U37" H 10450 5900 60 0000 C CNN
+F 1 "d_nand" H 10500 6000 60 0000 C CNN
+F 2 "" H 10450 5900 60 0000 C CNN
+F 3 "" H 10450 5900 60 0000 C CNN
+ 1 10450 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U38
+U 1 1 666834DA
+P 10450 6550
+F 0 "U38" H 10450 6550 60 0000 C CNN
+F 1 "d_nand" H 10500 6650 60 0000 C CNN
+F 2 "" H 10450 6550 60 0000 C CNN
+F 3 "" H 10450 6550 60 0000 C CNN
+ 1 10450 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U39
+U 1 1 666834DB
+P 10450 7200
+F 0 "U39" H 10450 7200 60 0000 C CNN
+F 1 "d_nand" H 10500 7300 60 0000 C CNN
+F 2 "" H 10450 7200 60 0000 C CNN
+F 3 "" H 10450 7200 60 0000 C CNN
+ 1 10450 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U40
+U 1 1 666834DC
+P 10450 7850
+F 0 "U40" H 10450 7850 60 0000 C CNN
+F 1 "d_nand" H 10500 7950 60 0000 C CNN
+F 2 "" H 10450 7850 60 0000 C CNN
+F 3 "" H 10450 7850 60 0000 C CNN
+ 1 10450 7850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U41
+U 1 1 666834DD
+P 10450 8500
+F 0 "U41" H 10450 8500 60 0000 C CNN
+F 1 "d_nand" H 10500 8600 60 0000 C CNN
+F 2 "" H 10450 8500 60 0000 C CNN
+F 3 "" H 10450 8500 60 0000 C CNN
+ 1 10450 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U42
+U 1 1 666834DE
+P 10450 9150
+F 0 "U42" H 10450 9150 60 0000 C CNN
+F 1 "d_nand" H 10500 9250 60 0000 C CNN
+F 2 "" H 10450 9150 60 0000 C CNN
+F 3 "" H 10450 9150 60 0000 C CNN
+ 1 10450 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 666834DF
+P 9400 3650
+F 0 "U14" H 9400 3650 60 0000 C CNN
+F 1 "d_and" H 9450 3750 60 0000 C CNN
+F 2 "" H 9400 3650 60 0000 C CNN
+F 3 "" H 9400 3650 60 0000 C CNN
+ 1 9400 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U15
+U 1 1 666834E0
+P 9400 4000
+F 0 "U15" H 9400 4000 60 0000 C CNN
+F 1 "d_and" H 9450 4100 60 0000 C CNN
+F 2 "" H 9400 4000 60 0000 C CNN
+F 3 "" H 9400 4000 60 0000 C CNN
+ 1 9400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 666834E1
+P 9400 4350
+F 0 "U16" H 9400 4350 60 0000 C CNN
+F 1 "d_and" H 9450 4450 60 0000 C CNN
+F 2 "" H 9400 4350 60 0000 C CNN
+F 3 "" H 9400 4350 60 0000 C CNN
+ 1 9400 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 666834E2
+P 9400 4650
+F 0 "U17" H 9400 4650 60 0000 C CNN
+F 1 "d_and" H 9450 4750 60 0000 C CNN
+F 2 "" H 9400 4650 60 0000 C CNN
+F 3 "" H 9400 4650 60 0000 C CNN
+ 1 9400 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 666834E3
+P 9450 5050
+F 0 "U18" H 9450 5050 60 0000 C CNN
+F 1 "d_and" H 9500 5150 60 0000 C CNN
+F 2 "" H 9450 5050 60 0000 C CNN
+F 3 "" H 9450 5050 60 0000 C CNN
+ 1 9450 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 666834E4
+P 9450 5350
+F 0 "U19" H 9450 5350 60 0000 C CNN
+F 1 "d_and" H 9500 5450 60 0000 C CNN
+F 2 "" H 9450 5350 60 0000 C CNN
+F 3 "" H 9450 5350 60 0000 C CNN
+ 1 9450 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U23
+U 1 1 666834E5
+P 9500 5750
+F 0 "U23" H 9500 5750 60 0000 C CNN
+F 1 "d_and" H 9550 5850 60 0000 C CNN
+F 2 "" H 9500 5750 60 0000 C CNN
+F 3 "" H 9500 5750 60 0000 C CNN
+ 1 9500 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U24
+U 1 1 666834E6
+P 9500 6050
+F 0 "U24" H 9500 6050 60 0000 C CNN
+F 1 "d_and" H 9550 6150 60 0000 C CNN
+F 2 "" H 9500 6050 60 0000 C CNN
+F 3 "" H 9500 6050 60 0000 C CNN
+ 1 9500 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 666834E7
+P 9450 6400
+F 0 "U20" H 9450 6400 60 0000 C CNN
+F 1 "d_and" H 9500 6500 60 0000 C CNN
+F 2 "" H 9450 6400 60 0000 C CNN
+F 3 "" H 9450 6400 60 0000 C CNN
+ 1 9450 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U25
+U 1 1 666834E8
+P 9500 6700
+F 0 "U25" H 9500 6700 60 0000 C CNN
+F 1 "d_and" H 9550 6800 60 0000 C CNN
+F 2 "" H 9500 6700 60 0000 C CNN
+F 3 "" H 9500 6700 60 0000 C CNN
+ 1 9500 6700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 666834E9
+P 9450 7050
+F 0 "U21" H 9450 7050 60 0000 C CNN
+F 1 "d_and" H 9500 7150 60 0000 C CNN
+F 2 "" H 9450 7050 60 0000 C CNN
+F 3 "" H 9450 7050 60 0000 C CNN
+ 1 9450 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U22
+U 1 1 666834EA
+P 9450 7350
+F 0 "U22" H 9450 7350 60 0000 C CNN
+F 1 "d_and" H 9500 7450 60 0000 C CNN
+F 2 "" H 9450 7350 60 0000 C CNN
+F 3 "" H 9450 7350 60 0000 C CNN
+ 1 9450 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U26
+U 1 1 666834EB
+P 9500 7700
+F 0 "U26" H 9500 7700 60 0000 C CNN
+F 1 "d_and" H 9550 7800 60 0000 C CNN
+F 2 "" H 9500 7700 60 0000 C CNN
+F 3 "" H 9500 7700 60 0000 C CNN
+ 1 9500 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 666834EC
+P 9550 8050
+F 0 "U30" H 9550 8050 60 0000 C CNN
+F 1 "d_and" H 9600 8150 60 0000 C CNN
+F 2 "" H 9550 8050 60 0000 C CNN
+F 3 "" H 9550 8050 60 0000 C CNN
+ 1 9550 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U31
+U 1 1 666834ED
+P 9550 8350
+F 0 "U31" H 9550 8350 60 0000 C CNN
+F 1 "d_and" H 9600 8450 60 0000 C CNN
+F 2 "" H 9550 8350 60 0000 C CNN
+F 3 "" H 9550 8350 60 0000 C CNN
+ 1 9550 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U27
+U 1 1 666834EE
+P 9500 8650
+F 0 "U27" H 9500 8650 60 0000 C CNN
+F 1 "d_and" H 9550 8750 60 0000 C CNN
+F 2 "" H 9500 8650 60 0000 C CNN
+F 3 "" H 9500 8650 60 0000 C CNN
+ 1 9500 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U28
+U 1 1 666834EF
+P 9500 9000
+F 0 "U28" H 9500 9000 60 0000 C CNN
+F 1 "d_and" H 9550 9100 60 0000 C CNN
+F 2 "" H 9500 9000 60 0000 C CNN
+F 3 "" H 9500 9000 60 0000 C CNN
+ 1 9500 9000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U29
+U 1 1 666834F0
+P 9500 9300
+F 0 "U29" H 9500 9300 60 0000 C CNN
+F 1 "d_and" H 9550 9400 60 0000 C CNN
+F 2 "" H 9500 9300 60 0000 C CNN
+F 3 "" H 9500 9300 60 0000 C CNN
+ 1 9500 9300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U32
+U 1 1 666834F1
+P 9550 9650
+F 0 "U32" H 9550 9650 60 0000 C CNN
+F 1 "d_and" H 9600 9750 60 0000 C CNN
+F 2 "" H 9550 9650 60 0000 C CNN
+F 3 "" H 9550 9650 60 0000 C CNN
+ 1 9550 9650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U33
+U 1 1 666834F2
+P 9550 9950
+F 0 "U33" H 9550 9950 60 0000 C CNN
+F 1 "d_and" H 9600 10050 60 0000 C CNN
+F 2 "" H 9550 9950 60 0000 C CNN
+F 3 "" H 9550 9950 60 0000 C CNN
+ 1 9550 9950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U10
+U 1 1 666834F3
+P 6000 4800
+F 0 "U10" H 6000 4750 60 0000 C CNN
+F 1 "d_buffer" H 6000 4850 60 0000 C CNN
+F 2 "" H 6000 4800 60 0000 C CNN
+F 3 "" H 6000 4800 60 0000 C CNN
+ 1 6000 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U11
+U 1 1 666834F4
+P 6000 6600
+F 0 "U11" H 6000 6550 60 0000 C CNN
+F 1 "d_buffer" H 6000 6650 60 0000 C CNN
+F 2 "" H 6000 6600 60 0000 C CNN
+F 3 "" H 6000 6600 60 0000 C CNN
+ 1 6000 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U13
+U 1 1 666834F5
+P 6250 7950
+F 0 "U13" H 6250 7900 60 0000 C CNN
+F 1 "d_buffer" H 6250 8000 60 0000 C CNN
+F 2 "" H 6250 7950 60 0000 C CNN
+F 3 "" H 6250 7950 60 0000 C CNN
+ 1 6250 7950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U12
+U 1 1 666834F6
+P 6200 9300
+F 0 "U12" H 6200 9250 60 0000 C CNN
+F 1 "d_buffer" H 6200 9350 60 0000 C CNN
+F 2 "" H 6200 9300 60 0000 C CNN
+F 3 "" H 6200 9300 60 0000 C CNN
+ 1 6200 9300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 666834F7
+P 5200 9300
+F 0 "U8" H 5200 9200 60 0000 C CNN
+F 1 "d_inverter" H 5200 9450 60 0000 C CNN
+F 2 "" H 5250 9250 60 0000 C CNN
+F 3 "" H 5250 9250 60 0000 C CNN
+ 1 5200 9300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 666834F8
+P 4350 8650
+F 0 "U5" H 4350 8550 60 0000 C CNN
+F 1 "d_inverter" H 4350 8800 60 0000 C CNN
+F 2 "" H 4400 8600 60 0000 C CNN
+F 3 "" H 4400 8600 60 0000 C CNN
+ 1 4350 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 666834F9
+P 5250 7950
+F 0 "U9" H 5250 7850 60 0000 C CNN
+F 1 "d_inverter" H 5250 8100 60 0000 C CNN
+F 2 "" H 5300 7900 60 0000 C CNN
+F 3 "" H 5300 7900 60 0000 C CNN
+ 1 5250 7950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 666834FA
+P 4250 7350
+F 0 "U4" H 4250 7250 60 0000 C CNN
+F 1 "d_inverter" H 4250 7500 60 0000 C CNN
+F 2 "" H 4300 7300 60 0000 C CNN
+F 3 "" H 4300 7300 60 0000 C CNN
+ 1 4250 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 666834FB
+P 5100 6600
+F 0 "U7" H 5100 6500 60 0000 C CNN
+F 1 "d_inverter" H 5100 6750 60 0000 C CNN
+F 2 "" H 5150 6550 60 0000 C CNN
+F 3 "" H 5150 6550 60 0000 C CNN
+ 1 5100 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 666834FC
+P 4200 5950
+F 0 "U3" H 4200 5850 60 0000 C CNN
+F 1 "d_inverter" H 4200 6100 60 0000 C CNN
+F 2 "" H 4250 5900 60 0000 C CNN
+F 3 "" H 4250 5900 60 0000 C CNN
+ 1 4200 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 666834FD
+P 5050 4800
+F 0 "U6" H 5050 4700 60 0000 C CNN
+F 1 "d_inverter" H 5050 4950 60 0000 C CNN
+F 2 "" H 5100 4750 60 0000 C CNN
+F 3 "" H 5100 4750 60 0000 C CNN
+ 1 5050 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 666834FE
+P 4200 3900
+F 0 "U2" H 4200 3800 60 0000 C CNN
+F 1 "d_inverter" H 4200 4050 60 0000 C CNN
+F 2 "" H 4250 3850 60 0000 C CNN
+F 3 "" H 4250 3850 60 0000 C CNN
+ 1 4200 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9850 3600 9950 3600
+Wire Wire Line
+ 9950 3600 9950 3750
+Wire Wire Line
+ 9950 3850 9950 3950
+Wire Wire Line
+ 9950 3950 9850 3950
+Wire Wire Line
+ 9850 4300 10000 4300
+Wire Wire Line
+ 10000 4300 10000 4400
+Wire Wire Line
+ 10000 4500 10000 4600
+Wire Wire Line
+ 10000 4600 9850 4600
+Wire Wire Line
+ 9900 5000 10000 5000
+Wire Wire Line
+ 10000 5000 10000 5100
+Wire Wire Line
+ 10000 5200 10000 5300
+Wire Wire Line
+ 10000 5300 9900 5300
+Wire Wire Line
+ 9950 5700 10000 5700
+Wire Wire Line
+ 10000 5700 10000 5800
+Wire Wire Line
+ 10000 5900 10000 6000
+Wire Wire Line
+ 10000 6000 9950 6000
+Wire Wire Line
+ 9900 6350 10000 6350
+Wire Wire Line
+ 10000 6350 10000 6450
+Wire Wire Line
+ 10000 6550 10000 6650
+Wire Wire Line
+ 10000 6650 9950 6650
+Wire Wire Line
+ 9900 7000 10000 7000
+Wire Wire Line
+ 10000 7000 10000 7100
+Wire Wire Line
+ 10000 7200 10000 7300
+Wire Wire Line
+ 10000 7300 9900 7300
+Wire Wire Line
+ 9950 7650 10000 7650
+Wire Wire Line
+ 10000 7650 10000 7750
+Wire Wire Line
+ 10000 7850 10000 8000
+Wire Wire Line
+ 10000 8300 10000 8400
+Wire Wire Line
+ 10000 8500 10000 8600
+Wire Wire Line
+ 10000 8600 9950 8600
+Wire Wire Line
+ 9950 8950 10000 8950
+Wire Wire Line
+ 10000 8950 10000 9050
+Wire Wire Line
+ 10000 9150 10000 9250
+Wire Wire Line
+ 10000 9250 9950 9250
+Wire Wire Line
+ 10000 9600 10000 9700
+Wire Wire Line
+ 10000 9800 10000 9900
+Wire Wire Line
+ 8950 4000 8700 4000
+Wire Wire Line
+ 8700 4000 8700 8650
+Wire Wire Line
+ 4650 8650 9050 8650
+Wire Wire Line
+ 9100 8050 8700 8050
+Connection ~ 8700 8050
+Wire Wire Line
+ 9000 7350 8700 7350
+Connection ~ 8700 7350
+Wire Wire Line
+ 9050 6700 8700 6700
+Connection ~ 8700 6700
+Wire Wire Line
+ 9050 6050 8700 6050
+Connection ~ 8700 6050
+Wire Wire Line
+ 9000 5350 8700 5350
+Connection ~ 8700 5350
+Wire Wire Line
+ 8950 4650 8700 4650
+Connection ~ 8700 4650
+Wire Wire Line
+ 8950 3900 8400 3900
+Wire Wire Line
+ 8400 3900 8400 9850
+Wire Wire Line
+ 8400 9850 9100 9850
+Wire Wire Line
+ 8950 4550 8400 4550
+Connection ~ 8400 4550
+Wire Wire Line
+ 9000 5250 8400 5250
+Connection ~ 8400 5250
+Wire Wire Line
+ 9050 5950 8400 5950
+Connection ~ 8400 5950
+Wire Wire Line
+ 9050 9200 8400 9200
+Connection ~ 8400 9200
+Wire Wire Line
+ 8950 3650 8100 3650
+Wire Wire Line
+ 8100 3650 8100 9650
+Wire Wire Line
+ 8100 9650 9100 9650
+Wire Wire Line
+ 9050 9000 8100 9000
+Connection ~ 8100 9000
+Wire Wire Line
+ 8950 4350 8100 4350
+Connection ~ 8100 4350
+Wire Wire Line
+ 9000 6400 8100 6400
+Connection ~ 8100 6400
+Wire Wire Line
+ 9000 7050 8100 7050
+Connection ~ 8100 7050
+Wire Wire Line
+ 8950 3550 7800 3550
+Wire Wire Line
+ 7800 3550 7800 8900
+Wire Wire Line
+ 7800 8900 9050 8900
+Wire Wire Line
+ 9000 4950 7800 4950
+Connection ~ 7800 4950
+Wire Wire Line
+ 9000 6300 7800 6300
+Connection ~ 7800 6300
+Wire Wire Line
+ 9050 7600 7800 7600
+Connection ~ 7800 7600
+Wire Wire Line
+ 8950 4250 7400 4250
+Wire Wire Line
+ 7400 4250 7400 9550
+Wire Wire Line
+ 7400 9550 9100 9550
+Wire Wire Line
+ 9050 5650 7400 5650
+Connection ~ 7400 5650
+Wire Wire Line
+ 9000 6950 7400 6950
+Connection ~ 7400 6950
+Wire Wire Line
+ 9100 8250 7400 8250
+Connection ~ 7400 8250
+Wire Wire Line
+ 9000 5050 7950 5050
+Wire Wire Line
+ 7950 5050 7950 8350
+Wire Wire Line
+ 7950 8350 9100 8350
+Wire Wire Line
+ 9050 5750 7950 5750
+Connection ~ 7950 5750
+Wire Wire Line
+ 9050 7700 7950 7700
+Connection ~ 7950 7700
+Wire Wire Line
+ 9050 6600 8250 6600
+Wire Wire Line
+ 8250 6600 8250 8550
+Wire Wire Line
+ 8250 8550 9050 8550
+Wire Wire Line
+ 9000 7250 8250 7250
+Connection ~ 8250 7250
+Wire Wire Line
+ 6900 7950 9100 7950
+Connection ~ 8250 7950
+Connection ~ 8700 8650
+Wire Wire Line
+ 9050 9300 6850 9300
+Wire Wire Line
+ 9100 9950 8900 9950
+Wire Wire Line
+ 8900 9950 8900 9300
+Connection ~ 8900 9300
+Wire Wire Line
+ 4550 7350 8400 7350
+Connection ~ 8400 7350
+Wire Wire Line
+ 4500 3900 7800 3900
+Connection ~ 7800 3900
+Wire Wire Line
+ 7400 4800 6650 4800
+Connection ~ 7400 4800
+Wire Wire Line
+ 4500 5950 8100 5950
+Connection ~ 8100 5950
+Wire Wire Line
+ 7950 6600 6650 6600
+Connection ~ 7950 6600
+Wire Wire Line
+ 5350 4800 5500 4800
+Wire Wire Line
+ 4750 4800 4550 4800
+Wire Wire Line
+ 4550 4800 4550 3900
+Connection ~ 4550 3900
+Wire Wire Line
+ 5400 6600 5500 6600
+Wire Wire Line
+ 4800 6600 4600 6600
+Wire Wire Line
+ 4600 6600 4600 5950
+Connection ~ 4600 5950
+Wire Wire Line
+ 4950 7950 4650 7950
+Wire Wire Line
+ 4650 7950 4650 7350
+Connection ~ 4650 7350
+Wire Wire Line
+ 5550 7950 5750 7950
+Wire Wire Line
+ 5500 9300 5700 9300
+Wire Wire Line
+ 4900 9300 4700 9300
+Wire Wire Line
+ 4700 9300 4700 8650
+Connection ~ 4700 8650
+Wire Wire Line
+ 3700 3900 3900 3900
+Wire Wire Line
+ 3700 8650 4050 8650
+Wire Wire Line
+ 10900 9750 11900 9750
+Wire Wire Line
+ 11900 9750 11900 8200
+Wire Wire Line
+ 10900 9100 11700 9100
+Wire Wire Line
+ 11700 9100 11700 8100
+Wire Wire Line
+ 11700 8100 11900 8100
+Wire Wire Line
+ 10900 8450 11300 8450
+Wire Wire Line
+ 11300 8450 11300 8000
+Wire Wire Line
+ 11300 8000 11900 8000
+Wire Wire Line
+ 11900 7900 11300 7900
+Wire Wire Line
+ 11300 7900 11300 7800
+Wire Wire Line
+ 11300 7800 10900 7800
+Wire Wire Line
+ 11900 7800 11600 7800
+Wire Wire Line
+ 11600 7800 11600 7150
+Wire Wire Line
+ 11600 7150 10900 7150
+Wire Wire Line
+ 10900 6500 11800 6500
+Wire Wire Line
+ 11800 6500 11800 5200
+Wire Wire Line
+ 10900 5850 11650 5850
+Wire Wire Line
+ 11650 5850 11650 5100
+Wire Wire Line
+ 11650 5100 11800 5100
+Wire Wire Line
+ 10900 5150 11350 5150
+Wire Wire Line
+ 11350 5150 11350 5000
+Wire Wire Line
+ 11350 5000 11800 5000
+Wire Wire Line
+ 11300 4900 11800 4900
+Wire Wire Line
+ 11300 4450 11300 4900
+Wire Wire Line
+ 11300 4450 10900 4450
+Wire Wire Line
+ 11800 4800 11800 3800
+Wire Wire Line
+ 11800 3800 10850 3800
+$Comp
+L PORT U1
+U 5 1 66689C57
+P 12050 5200
+F 0 "U1" H 12100 5300 30 0000 C CNN
+F 1 "PORT" H 12050 5200 30 0000 C CNN
+F 2 "" H 12050 5200 60 0000 C CNN
+F 3 "" H 12050 5200 60 0000 C CNN
+ 5 12050 5200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 66689F05
+P 12150 7800
+F 0 "U1" H 12200 7900 30 0000 C CNN
+F 1 "PORT" H 12150 7800 30 0000 C CNN
+F 2 "" H 12150 7800 60 0000 C CNN
+F 3 "" H 12150 7800 60 0000 C CNN
+ 6 12150 7800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6668A02A
+P 12150 7900
+F 0 "U1" H 12200 8000 30 0000 C CNN
+F 1 "PORT" H 12150 7900 30 0000 C CNN
+F 2 "" H 12150 7900 60 0000 C CNN
+F 3 "" H 12150 7900 60 0000 C CNN
+ 7 12150 7900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6668A141
+P 12150 8000
+F 0 "U1" H 12200 8100 30 0000 C CNN
+F 1 "PORT" H 12150 8000 30 0000 C CNN
+F 2 "" H 12150 8000 60 0000 C CNN
+F 3 "" H 12150 8000 60 0000 C CNN
+ 8 12150 8000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6668A238
+P 12150 8100
+F 0 "U1" H 12200 8200 30 0000 C CNN
+F 1 "PORT" H 12150 8100 30 0000 C CNN
+F 2 "" H 12150 8100 60 0000 C CNN
+F 3 "" H 12150 8100 60 0000 C CNN
+ 9 12150 8100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6668B175
+P 12150 8200
+F 0 "U1" H 12200 8300 30 0000 C CNN
+F 1 "PORT" H 12150 8200 30 0000 C CNN
+F 2 "" H 12150 8200 60 0000 C CNN
+F 3 "" H 12150 8200 60 0000 C CNN
+ 10 12150 8200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6668B274
+P 3450 8650
+F 0 "U1" H 3500 8750 30 0000 C CNN
+F 1 "PORT" H 3450 8650 30 0000 C CNN
+F 2 "" H 3450 8650 60 0000 C CNN
+F 3 "" H 3450 8650 60 0000 C CNN
+ 11 3450 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6668BCDE
+P 3650 5950
+F 0 "U1" H 3700 6050 30 0000 C CNN
+F 1 "PORT" H 3650 5950 30 0000 C CNN
+F 2 "" H 3650 5950 60 0000 C CNN
+F 3 "" H 3650 5950 60 0000 C CNN
+ 13 3650 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6668BDDD
+P 3450 3900
+F 0 "U1" H 3500 4000 30 0000 C CNN
+F 1 "PORT" H 3450 3900 30 0000 C CNN
+F 2 "" H 3450 3900 60 0000 C CNN
+F 3 "" H 3450 3900 60 0000 C CNN
+ 14 3450 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6668BEE6
+P 12050 4900
+F 0 "U1" H 12100 5000 30 0000 C CNN
+F 1 "PORT" H 12050 4900 30 0000 C CNN
+F 2 "" H 12050 4900 60 0000 C CNN
+F 3 "" H 12050 4900 60 0000 C CNN
+ 2 12050 4900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6668E223
+P 12050 5100
+F 0 "U1" H 12100 5200 30 0000 C CNN
+F 1 "PORT" H 12050 5100 30 0000 C CNN
+F 2 "" H 12050 5100 60 0000 C CNN
+F 3 "" H 12050 5100 60 0000 C CNN
+ 4 12050 5100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6668E423
+P 12050 5000
+F 0 "U1" H 12100 5100 30 0000 C CNN
+F 1 "PORT" H 12050 5000 30 0000 C CNN
+F 2 "" H 12050 5000 60 0000 C CNN
+F 3 "" H 12050 5000 60 0000 C CNN
+ 3 12050 5000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6668E4E0
+P 12050 4800
+F 0 "U1" H 12100 4900 30 0000 C CNN
+F 1 "PORT" H 12050 4800 30 0000 C CNN
+F 2 "" H 12050 4800 60 0000 C CNN
+F 3 "" H 12050 4800 60 0000 C CNN
+ 1 12050 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 66694CAC
+P 3700 7350
+F 0 "U1" H 3750 7450 30 0000 C CNN
+F 1 "PORT" H 3700 7350 30 0000 C CNN
+F 2 "" H 3700 7350 60 0000 C CNN
+F 3 "" H 3700 7350 60 0000 C CNN
+ 12 3700 7350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/sn7445/sn7445.sub b/library/SubcircuitLibrary/sn7445/sn7445.sub
new file mode 100644
index 00000000..d413e1fa
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445.sub
@@ -0,0 +1,174 @@
+* Subcircuit sn7445
+.subckt sn7445 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\fossee\esim\library\subcircuitlibrary\sn7445\sn7445.cir
+* u34 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad1_ d_nand
+* u35 net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ d_nand
+* u36 net-_u18-pad3_ net-_u19-pad3_ net-_u1-pad3_ d_nand
+* u43 net-_u32-pad3_ net-_u33-pad3_ net-_u1-pad10_ d_nand
+* u37 net-_u23-pad3_ net-_u24-pad3_ net-_u1-pad4_ d_nand
+* u38 net-_u20-pad3_ net-_u25-pad3_ net-_u1-pad5_ d_nand
+* u39 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad6_ d_nand
+* u40 net-_u26-pad3_ net-_u30-pad3_ net-_u1-pad7_ d_nand
+* u41 net-_u31-pad3_ net-_u27-pad3_ net-_u1-pad8_ d_nand
+* u42 net-_u28-pad3_ net-_u29-pad3_ net-_u1-pad9_ d_nand
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u10-pad2_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u15-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u14-pad1_ net-_u11-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u15-pad1_ net-_u15-pad2_ net-_u19-pad3_ d_and
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u15-pad1_ net-_u15-pad2_ net-_u24-pad3_ d_and
+* u20 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_and
+* u21 net-_u10-pad2_ net-_u14-pad2_ net-_u21-pad3_ d_and
+* u22 net-_u13-pad2_ net-_u15-pad2_ net-_u22-pad3_ d_and
+* u26 net-_u14-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_and
+* u30 net-_u13-pad2_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u31 net-_u10-pad2_ net-_u11-pad2_ net-_u31-pad3_ d_and
+* u27 net-_u13-pad2_ net-_u15-pad2_ net-_u27-pad3_ d_and
+* u28 net-_u14-pad1_ net-_u14-pad2_ net-_u28-pad3_ d_and
+* u29 net-_u15-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_and
+* u32 net-_u10-pad2_ net-_u14-pad2_ net-_u32-pad3_ d_and
+* u33 net-_u15-pad1_ net-_u12-pad2_ net-_u33-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_buffer
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_buffer
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u8 net-_u15-pad2_ net-_u12-pad1_ d_inverter
+* u5 net-_u1-pad11_ net-_u15-pad2_ d_inverter
+* u9 net-_u15-pad1_ net-_u13-pad1_ d_inverter
+* u4 net-_u1-pad12_ net-_u15-pad1_ d_inverter
+* u7 net-_u14-pad2_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u6 net-_u14-pad1_ net-_u10-pad1_ d_inverter
+* u2 net-_u1-pad14_ net-_u14-pad1_ d_inverter
+a1 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u1-pad1_ u34
+a2 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u1-pad2_ u35
+a3 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u1-pad3_ u36
+a4 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u1-pad10_ u43
+a5 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u1-pad4_ u37
+a6 [net-_u20-pad3_ net-_u25-pad3_ ] net-_u1-pad5_ u38
+a7 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad6_ u39
+a8 [net-_u26-pad3_ net-_u30-pad3_ ] net-_u1-pad7_ u40
+a9 [net-_u31-pad3_ net-_u27-pad3_ ] net-_u1-pad8_ u41
+a10 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u1-pad9_ u42
+a11 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a14 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17
+a15 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u18-pad3_ u18
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u19-pad3_ u19
+a17 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a18 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u24-pad3_ u24
+a19 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad3_ u20
+a20 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a21 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u21-pad3_ u21
+a22 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u22-pad3_ u22
+a23 [net-_u14-pad1_ net-_u11-pad2_ ] net-_u26-pad3_ u26
+a24 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u31-pad3_ u31
+a26 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u27-pad3_ u27
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u28-pad3_ u28
+a28 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29
+a29 [net-_u10-pad2_ net-_u14-pad2_ ] net-_u32-pad3_ u32
+a30 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u33-pad3_ u33
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u11-pad1_ net-_u11-pad2_ u11
+a33 net-_u13-pad1_ net-_u13-pad2_ u13
+a34 net-_u12-pad1_ net-_u12-pad2_ u12
+a35 net-_u15-pad2_ net-_u12-pad1_ u8
+a36 net-_u1-pad11_ net-_u15-pad2_ u5
+a37 net-_u15-pad1_ net-_u13-pad1_ u9
+a38 net-_u1-pad12_ net-_u15-pad1_ u4
+a39 net-_u14-pad2_ net-_u11-pad1_ u7
+a40 net-_u1-pad13_ net-_u14-pad2_ u3
+a41 net-_u14-pad1_ net-_u10-pad1_ u6
+a42 net-_u1-pad14_ net-_u14-pad1_ u2
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends sn7445 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml b/library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml
new file mode 100644
index 00000000..e375ff77
--- /dev/null
+++ b/library/SubcircuitLibrary/sn7445/sn7445_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u34 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field1><field2 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field2><field3 name="Enter Input Load (default=1.0e-12)">1.0e-12</field3></u34><u35 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field4><field5 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field5><field6 name="Enter Input Load (default=1.0e-12)">1.0e-12</field6></u35><u36 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field7><field8 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field8><field9 name="Enter Input Load (default=1.0e-12)">1.0e-12</field9></u36><u43 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field10><field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field11><field12 name="Enter Input Load (default=1.0e-12)">1.0e-12</field12></u43><u37 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field13><field14 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field14><field15 name="Enter Input Load (default=1.0e-12)">1.0e-12</field15></u37><u38 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field16><field17 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field17><field18 name="Enter Input Load (default=1.0e-12)">1.0e-12</field18></u38><u39 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field19><field20 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field20><field21 name="Enter Input Load (default=1.0e-12)">1.0e-12</field21></u39><u40 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field22><field23 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field23><field24 name="Enter Input Load (default=1.0e-12)">1.0e-12</field24></u40><u41 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field25><field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field26><field27 name="Enter Input Load (default=1.0e-12)">1.0e-12</field27></u41><u42 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field28><field29 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field29><field30 name="Enter Input Load (default=1.0e-12)">1.0e-12</field30></u42><u14 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field31><field32 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field32><field33 name="Enter Input Load (default=1.0e-12)">1.0e-12</field33></u14><u15 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field34><field35 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field35><field36 name="Enter Input Load (default=1.0e-12)">1.0e-12</field36></u15><u16 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field37><field38 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field38><field39 name="Enter Input Load (default=1.0e-12)">1.0e-12</field39></u16><u17 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field40><field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field41><field42 name="Enter Input Load (default=1.0e-12)">1.0e-12</field42></u17><u18 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field43><field44 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field44><field45 name="Enter Input Load (default=1.0e-12)">1.0e-12</field45></u18><u19 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field46><field47 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field47><field48 name="Enter Input Load (default=1.0e-12)">1.0e-12</field48></u19><u23 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field49><field50 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field50><field51 name="Enter Input Load (default=1.0e-12)">1.0e-12</field51></u23><u24 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field52><field53 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field53><field54 name="Enter Input Load (default=1.0e-12)">1.0e-12</field54></u24><u20 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field55><field56 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field56><field57 name="Enter Input Load (default=1.0e-12)">1.0e-12</field57></u20><u25 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field58><field59 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field59><field60 name="Enter Input Load (default=1.0e-12)">1.0e-12</field60></u25><u21 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field61><field62 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field62><field63 name="Enter Input Load (default=1.0e-12)">1.0e-12</field63></u21><u22 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field64><field65 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field65><field66 name="Enter Input Load (default=1.0e-12)">1.0e-12</field66></u22><u26 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field67><field68 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field68><field69 name="Enter Input Load (default=1.0e-12)">1.0e-12</field69></u26><u30 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field70><field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field71><field72 name="Enter Input Load (default=1.0e-12)">1.0e-12</field72></u30><u31 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field73><field74 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field74><field75 name="Enter Input Load (default=1.0e-12)">1.0e-12</field75></u31><u27 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field76><field77 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field77><field78 name="Enter Input Load (default=1.0e-12)">1.0e-12</field78></u27><u28 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field79><field80 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field80><field81 name="Enter Input Load (default=1.0e-12)">1.0e-12</field81></u28><u29 name="type">d_and<field82 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field82><field83 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field83><field84 name="Enter Input Load (default=1.0e-12)">1.0e-12</field84></u29><u32 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field85><field86 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field86><field87 name="Enter Input Load (default=1.0e-12)">1.0e-12</field87></u32><u33 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field88><field89 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field89><field90 name="Enter Input Load (default=1.0e-12)">1.0e-12</field90></u33><u10 name="type">d_buffer<field91 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field91><field92 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field92><field93 name="Enter Input Load (default=1.0e-12)">1.0e-12</field93></u10><u11 name="type">d_buffer<field94 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field94><field95 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field95><field96 name="Enter Input Load (default=1.0e-12)">1.0e-12</field96></u11><u13 name="type">d_buffer<field97 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field97><field98 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field98><field99 name="Enter Input Load (default=1.0e-12)">1.0e-12</field99></u13><u12 name="type">d_buffer<field100 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field100><field101 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field101><field102 name="Enter Input Load (default=1.0e-12)">1.0e-12</field102></u12><u8 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field103><field104 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field104><field105 name="Enter Input Load (default=1.0e-12)">1.0e-12</field105></u8><u5 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field106><field107 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field107><field108 name="Enter Input Load (default=1.0e-12)">1.0e-12</field108></u5><u9 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field109><field110 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field110><field111 name="Enter Input Load (default=1.0e-12)">1.0e-12</field111></u9><u4 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field112><field113 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field113><field114 name="Enter Input Load (default=1.0e-12)">1.0e-12</field114></u4><u7 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field115><field116 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field116><field117 name="Enter Input Load (default=1.0e-12)">1.0e-12</field117></u7><u3 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field118><field119 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field119><field120 name="Enter Input Load (default=1.0e-12)">1.0e-12</field120></u3><u6 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field121><field122 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field122><field123 name="Enter Input Load (default=1.0e-12)">1.0e-12</field123></u6><u2 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field124><field125 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field125><field126 name="Enter Input Load (default=1.0e-12)">1.0e-12</field126></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-19 14:48:28 +0000