diff options
109 files changed, 10990 insertions, 12 deletions
@@ -39,7 +39,7 @@ Table of contents -2. eSim installation in Windows OS +2. eSim 2.4 installation in Windows OS i. Download eSim for Windows OS from "https://esim.fossee.in/". Disable the antivirus (if any). @@ -15,8 +15,8 @@ It is an integrated tool build using open source softwares such as KiCad, Ngspic ## Releases and Installation eSim is released for the following distributions (operating systems): -* Ubuntu 18.04 and 20.04 LTS versions. -* Microsoft Windows 8 and 10. +* Ubuntu 18.04, 20.04 LTS versions. +* Microsoft Windows 8, 10 and 11. To use eSim on your machine having above distributions, please refer to link [here](https://esim.fossee.in/downloads) for installation and other guidelines. @@ -39,7 +39,7 @@ To use eSim on your machine having above distributions, please refer to link [he * [SkyWater SKY130 PDK](https://skywater-pdk.rtfd.io/) ## eSim Manual -To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.3.pdf) +To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.4.pdf) ## Contact For any queries regarding eSim please write us on at this [email address](mailto:contact-esim@fossee.in). @@ -1 +1 @@ -2.3 +2.4 @@ -25,9 +25,9 @@ copyright = u'2022, FOSSEE' author = u'FOSSEE, IIT Bombay' # The short X.Y version -version = u'2.2' +version = u'2.4' # The full version, including alpha/beta/rc tags -release = u'2.2.0' +release = u'2.4.0' # -- General configuration --------------------------------------------------- diff --git a/library/SubcircuitLibrary/74F350/3_and-cache.lib b/library/SubcircuitLibrary/74F350/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/3_and.cir b/library/SubcircuitLibrary/74F350/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.cir.out b/library/SubcircuitLibrary/74F350/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.pro b/library/SubcircuitLibrary/74F350/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/3_and.sch b/library/SubcircuitLibrary/74F350/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/3_and.sub b/library/SubcircuitLibrary/74F350/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350-cache.lib b/library/SubcircuitLibrary/74F350/74F350-cache.lib new file mode 100644 index 00000000..8256d8a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350-cache.lib @@ -0,0 +1,112 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/74F350.cir b/library/SubcircuitLibrary/74F350/74F350.cir new file mode 100644 index 00000000..87560c28 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir @@ -0,0 +1,48 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\74F350\74F350.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:58:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X16 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad7_ Net-_U16-Pad1_ 3_and +X15 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U16-Pad2_ 3_and +X14 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad5_ Net-_U13-Pad1_ 3_and +X13 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U13-Pad2_ 3_and +X12 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U12-Pad1_ 3_and +X11 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U12-Pad2_ 3_and +X10 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U9-Pad1_ 3_and +X9 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U9-Pad2_ 3_and +X8 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U8-Pad1_ 3_and +X7 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U8-Pad2_ 3_and +X6 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U6-Pad1_ 3_and +X5 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U6-Pad2_ 3_and +X4 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad1_ 3_and +X3 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad2_ 3_and +X2 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U2-Pad1_ 3_and +X1 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad1_ Net-_U2-Pad2_ 3_and +U26 Net-_U1-Pad13_ Net-_U10-Pad1_ d_inverter +U24 Net-_U1-Pad10_ Net-_U24-Pad2_ d_inverter +U22 Net-_U1-Pad9_ Net-_U22-Pad2_ d_inverter +U25 Net-_U24-Pad2_ Net-_U25-Pad2_ d_inverter +U23 Net-_U22-Pad2_ Net-_U23-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U20 Net-_U10-Pad1_ Net-_U14-Pad3_ Net-_U1-Pad15_ d_and +U15 Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U1-Pad14_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad12_ d_and +U5 Net-_U10-Pad1_ Net-_U3-Pad3_ Net-_U1-Pad11_ d_and +U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U7 Net-_U7-Pad1_ Net-_U6-Pad3_ Net-_U10-Pad2_ d_or +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U14-Pad1_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U11-Pad2_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U7-Pad1_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ d_or +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_or +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.cir.out b/library/SubcircuitLibrary/74F350/74F350.cir.out new file mode 100644 index 00000000..b90caa5e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir.out @@ -0,0 +1,113 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir + +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.pro b/library/SubcircuitLibrary/74F350/74F350.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/74F350.sch b/library/SubcircuitLibrary/74F350/74F350.sch new file mode 100644 index 00000000..989985a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sch @@ -0,0 +1,1000 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:74F350-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X16 +U 1 1 679DB336 +P 15400 7400 +F 0 "X16" H 15500 7350 60 0000 C CNN +F 1 "3_and" H 15550 7550 60 0000 C CNN +F 2 "" H 15400 7400 60 0000 C CNN +F 3 "" H 15400 7400 60 0000 C CNN + 1 15400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X15 +U 1 1 679DB473 +P 14650 7400 +F 0 "X15" H 14750 7350 60 0000 C CNN +F 1 "3_and" H 14800 7550 60 0000 C CNN +F 2 "" H 14650 7400 60 0000 C CNN +F 3 "" H 14650 7400 60 0000 C CNN + 1 14650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X14 +U 1 1 679DB4EB +P 14050 7400 +F 0 "X14" H 14150 7350 60 0000 C CNN +F 1 "3_and" H 14200 7550 60 0000 C CNN +F 2 "" H 14050 7400 60 0000 C CNN +F 3 "" H 14050 7400 60 0000 C CNN + 1 14050 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X13 +U 1 1 679DB4F1 +P 13300 7400 +F 0 "X13" H 13400 7350 60 0000 C CNN +F 1 "3_and" H 13450 7550 60 0000 C CNN +F 2 "" H 13300 7400 60 0000 C CNN +F 3 "" H 13300 7400 60 0000 C CNN + 1 13300 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X12 +U 1 1 679DB5C3 +P 12750 7400 +F 0 "X12" H 12850 7350 60 0000 C CNN +F 1 "3_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12750 7400 60 0000 C CNN +F 3 "" H 12750 7400 60 0000 C CNN + 1 12750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X11 +U 1 1 679DB5C9 +P 12000 7400 +F 0 "X11" H 12100 7350 60 0000 C CNN +F 1 "3_and" H 12150 7550 60 0000 C CNN +F 2 "" H 12000 7400 60 0000 C CNN +F 3 "" H 12000 7400 60 0000 C CNN + 1 12000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X10 +U 1 1 679DB5CF +P 11400 7400 +F 0 "X10" H 11500 7350 60 0000 C CNN +F 1 "3_and" H 11550 7550 60 0000 C CNN +F 2 "" H 11400 7400 60 0000 C CNN +F 3 "" H 11400 7400 60 0000 C CNN + 1 11400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X9 +U 1 1 679DB5D5 +P 10650 7400 +F 0 "X9" H 10750 7350 60 0000 C CNN +F 1 "3_and" H 10800 7550 60 0000 C CNN +F 2 "" H 10650 7400 60 0000 C CNN +F 3 "" H 10650 7400 60 0000 C CNN + 1 10650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X8 +U 1 1 679DB885 +P 10100 7400 +F 0 "X8" H 10200 7350 60 0000 C CNN +F 1 "3_and" H 10250 7550 60 0000 C CNN +F 2 "" H 10100 7400 60 0000 C CNN +F 3 "" H 10100 7400 60 0000 C CNN + 1 10100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X7 +U 1 1 679DB88B +P 9350 7400 +F 0 "X7" H 9450 7350 60 0000 C CNN +F 1 "3_and" H 9500 7550 60 0000 C CNN +F 2 "" H 9350 7400 60 0000 C CNN +F 3 "" H 9350 7400 60 0000 C CNN + 1 9350 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X6 +U 1 1 679DB891 +P 8750 7400 +F 0 "X6" H 8850 7350 60 0000 C CNN +F 1 "3_and" H 8900 7550 60 0000 C CNN +F 2 "" H 8750 7400 60 0000 C CNN +F 3 "" H 8750 7400 60 0000 C CNN + 1 8750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X5 +U 1 1 679DB897 +P 8000 7400 +F 0 "X5" H 8100 7350 60 0000 C CNN +F 1 "3_and" H 8150 7550 60 0000 C CNN +F 2 "" H 8000 7400 60 0000 C CNN +F 3 "" H 8000 7400 60 0000 C CNN + 1 8000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X4 +U 1 1 679DB89D +P 7450 7400 +F 0 "X4" H 7550 7350 60 0000 C CNN +F 1 "3_and" H 7600 7550 60 0000 C CNN +F 2 "" H 7450 7400 60 0000 C CNN +F 3 "" H 7450 7400 60 0000 C CNN + 1 7450 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X3 +U 1 1 679DB8A3 +P 6700 7400 +F 0 "X3" H 6800 7350 60 0000 C CNN +F 1 "3_and" H 6850 7550 60 0000 C CNN +F 2 "" H 6700 7400 60 0000 C CNN +F 3 "" H 6700 7400 60 0000 C CNN + 1 6700 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X2 +U 1 1 679DB8A9 +P 6100 7400 +F 0 "X2" H 6200 7350 60 0000 C CNN +F 1 "3_and" H 6250 7550 60 0000 C CNN +F 2 "" H 6100 7400 60 0000 C CNN +F 3 "" H 6100 7400 60 0000 C CNN + 1 6100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 679DB8AF +P 5350 7400 +F 0 "X1" H 5450 7350 60 0000 C CNN +F 1 "3_and" H 5500 7550 60 0000 C CNN +F 2 "" H 5350 7400 60 0000 C CNN +F 3 "" H 5350 7400 60 0000 C CNN + 1 5350 7400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U26 +U 1 1 679DBBC7 +P 17700 3200 +F 0 "U26" H 17700 3100 60 0000 C CNN +F 1 "d_inverter" H 17700 3350 60 0000 C CNN +F 2 "" H 17750 3150 60 0000 C CNN +F 3 "" H 17750 3150 60 0000 C CNN + 1 17700 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 679DBC88 +P 16900 3200 +F 0 "U24" H 16900 3100 60 0000 C CNN +F 1 "d_inverter" H 16900 3350 60 0000 C CNN +F 2 "" H 16950 3150 60 0000 C CNN +F 3 "" H 16950 3150 60 0000 C CNN + 1 16900 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U22 +U 1 1 679DBCDF +P 16150 3200 +F 0 "U22" H 16150 3100 60 0000 C CNN +F 1 "d_inverter" H 16150 3350 60 0000 C CNN +F 2 "" H 16200 3150 60 0000 C CNN +F 3 "" H 16200 3150 60 0000 C CNN + 1 16150 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U25 +U 1 1 679DBD6D +P 16900 4200 +F 0 "U25" H 16900 4100 60 0000 C CNN +F 1 "d_inverter" H 16900 4350 60 0000 C CNN +F 2 "" H 16950 4150 60 0000 C CNN +F 3 "" H 16950 4150 60 0000 C CNN + 1 16900 4200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U23 +U 1 1 679DBD73 +P 16150 4200 +F 0 "U23" H 16150 4100 60 0000 C CNN +F 1 "d_inverter" H 16150 4350 60 0000 C CNN +F 2 "" H 16200 4150 60 0000 C CNN +F 3 "" H 16200 4150 60 0000 C CNN + 1 16150 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 679EA80D +P 17700 2050 +F 0 "U1" H 17750 2150 30 0000 C CNN +F 1 "PORT" H 17700 2050 30 0000 C CNN +F 2 "" H 17700 2050 60 0000 C CNN +F 3 "" H 17700 2050 60 0000 C CNN + 13 17700 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 679EAA26 +P 16900 2050 +F 0 "U1" H 16950 2150 30 0000 C CNN +F 1 "PORT" H 16900 2050 30 0000 C CNN +F 2 "" H 16900 2050 60 0000 C CNN +F 3 "" H 16900 2050 60 0000 C CNN + 10 16900 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679EAAAF +P 16150 2100 +F 0 "U1" H 16200 2200 30 0000 C CNN +F 1 "PORT" H 16150 2100 30 0000 C CNN +F 2 "" H 16150 2100 60 0000 C CNN +F 3 "" H 16150 2100 60 0000 C CNN + 9 16150 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 679EAB54 +P 15350 2150 +F 0 "U1" H 15400 2250 30 0000 C CNN +F 1 "PORT" H 15350 2150 30 0000 C CNN +F 2 "" H 15350 2150 60 0000 C CNN +F 3 "" H 15350 2150 60 0000 C CNN + 7 15350 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 679EAD32 +P 14600 2150 +F 0 "U1" H 14650 2250 30 0000 C CNN +F 1 "PORT" H 14600 2150 30 0000 C CNN +F 2 "" H 14600 2150 60 0000 C CNN +F 3 "" H 14600 2150 60 0000 C CNN + 6 14600 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 679EAD38 +P 14000 2150 +F 0 "U1" H 14050 2250 30 0000 C CNN +F 1 "PORT" H 14000 2150 30 0000 C CNN +F 2 "" H 14000 2150 60 0000 C CNN +F 3 "" H 14000 2150 60 0000 C CNN + 5 14000 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 679EAD3E +P 13250 2150 +F 0 "U1" H 13300 2250 30 0000 C CNN +F 1 "PORT" H 13250 2150 30 0000 C CNN +F 2 "" H 13250 2150 60 0000 C CNN +F 3 "" H 13250 2150 60 0000 C CNN + 4 13250 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 679EB065 +P 10600 2300 +F 0 "U1" H 10650 2400 30 0000 C CNN +F 1 "PORT" H 10600 2300 30 0000 C CNN +F 2 "" H 10600 2300 60 0000 C CNN +F 3 "" H 10600 2300 60 0000 C CNN + 3 10600 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 679EB06B +P 7950 2200 +F 0 "U1" H 8000 2300 30 0000 C CNN +F 1 "PORT" H 7950 2200 30 0000 C CNN +F 2 "" H 7950 2200 60 0000 C CNN +F 3 "" H 7950 2200 60 0000 C CNN + 2 7950 2200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 679EB071 +P 5300 2250 +F 0 "U1" H 5350 2350 30 0000 C CNN +F 1 "PORT" H 5300 2250 30 0000 C CNN +F 2 "" H 5300 2250 60 0000 C CNN +F 3 "" H 5300 2250 60 0000 C CNN + 1 5300 2250 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 679E10AA +P 19450 7550 +F 0 "U1" H 19500 7650 30 0000 C CNN +F 1 "PORT" H 19450 7550 30 0000 C CNN +F 2 "" H 19450 7550 60 0000 C CNN +F 3 "" H 19450 7550 60 0000 C CNN + 8 19450 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 679E1213 +P 19450 7800 +F 0 "U1" H 19500 7900 30 0000 C CNN +F 1 "PORT" H 19450 7800 30 0000 C CNN +F 2 "" H 19450 7800 60 0000 C CNN +F 3 "" H 19450 7800 60 0000 C CNN + 16 19450 7800 + 1 0 0 -1 +$EndComp +NoConn ~ 19700 7550 +NoConn ~ 19700 7800 +Wire Wire Line + 17700 2300 17700 2900 +Wire Wire Line + 16900 2300 16900 2900 +Wire Wire Line + 16150 2350 16150 2900 +Wire Wire Line + 16900 3500 16900 3900 +Wire Wire Line + 16150 3500 16150 3900 +Wire Wire Line + 16900 6750 16900 4500 +Wire Wire Line + 5500 6750 16900 6750 +Wire Wire Line + 14800 6750 14800 7050 +Wire Wire Line + 13450 6750 13450 7050 +Connection ~ 14800 6750 +Wire Wire Line + 12150 6750 12150 7050 +Connection ~ 13450 6750 +Wire Wire Line + 10800 6750 10800 7050 +Connection ~ 12150 6750 +Wire Wire Line + 9500 6750 9500 7050 +Connection ~ 10800 6750 +Wire Wire Line + 8150 6750 8150 7050 +Connection ~ 9500 6750 +Wire Wire Line + 6850 6750 6850 7050 +Connection ~ 8150 6750 +Wire Wire Line + 5500 6750 5500 7050 +Connection ~ 6850 6750 +Wire Wire Line + 16900 3750 16550 3750 +Wire Wire Line + 16550 3750 16550 6550 +Wire Wire Line + 16550 6550 6250 6550 +Wire Wire Line + 15550 6550 15550 7050 +Connection ~ 16900 3750 +Wire Wire Line + 14200 6550 14200 7050 +Connection ~ 15550 6550 +Wire Wire Line + 12900 6550 12900 7050 +Connection ~ 14200 6550 +Wire Wire Line + 11550 6550 11550 7050 +Connection ~ 12900 6550 +Wire Wire Line + 10250 6550 10250 7050 +Connection ~ 11550 6550 +Wire Wire Line + 8900 6550 8900 7050 +Connection ~ 10250 6550 +Wire Wire Line + 7600 6550 7600 7050 +Connection ~ 8900 6550 +Wire Wire Line + 6250 6550 6250 7050 +Connection ~ 7600 6550 +Wire Wire Line + 16150 6350 16150 4500 +Wire Wire Line + 5400 6350 16150 6350 +Wire Wire Line + 14100 6350 14100 7050 +Wire Wire Line + 13350 6350 13350 7050 +Connection ~ 14100 6350 +Wire Wire Line + 11450 6350 11450 7050 +Connection ~ 13350 6350 +Wire Wire Line + 10700 6350 10700 7050 +Connection ~ 11450 6350 +Wire Wire Line + 8800 6350 8800 7050 +Connection ~ 10700 6350 +Wire Wire Line + 8050 6350 8050 7050 +Connection ~ 8800 6350 +Wire Wire Line + 6150 6350 6150 7050 +Connection ~ 8050 6350 +Wire Wire Line + 5400 6350 5400 7050 +Connection ~ 6150 6350 +Wire Wire Line + 16150 3750 15750 3750 +Wire Wire Line + 15750 3750 15750 6150 +Wire Wire Line + 15750 6150 6750 6150 +Wire Wire Line + 15450 6150 15450 7050 +Connection ~ 16150 3750 +Wire Wire Line + 14700 6150 14700 7050 +Connection ~ 15450 6150 +Wire Wire Line + 12800 6150 12800 7050 +Connection ~ 14700 6150 +Wire Wire Line + 12050 6150 12050 7050 +Connection ~ 12800 6150 +Wire Wire Line + 10150 6150 10150 7050 +Connection ~ 12050 6150 +Wire Wire Line + 9400 6150 9400 7050 +Connection ~ 10150 6150 +Wire Wire Line + 7500 6150 7500 7050 +Connection ~ 9400 6150 +Wire Wire Line + 6750 6150 6750 7050 +Connection ~ 7500 6150 +Wire Wire Line + 15350 2400 15350 7050 +Wire Wire Line + 14600 2400 14600 7050 +Wire Wire Line + 14000 2400 14000 7050 +Wire Wire Line + 13250 2400 13250 7050 +Wire Wire Line + 5300 2500 5300 7050 +Wire Wire Line + 7950 2450 7950 7050 +Wire Wire Line + 10600 2550 10600 7050 +Wire Wire Line + 12700 7050 12700 4400 +Wire Wire Line + 12700 4400 14600 4400 +Connection ~ 14600 4400 +Wire Wire Line + 11950 7050 11950 4600 +Wire Wire Line + 10050 4600 14000 4600 +Connection ~ 14000 4600 +Wire Wire Line + 11350 7050 11350 4850 +Wire Wire Line + 7400 4850 13250 4850 +Connection ~ 13250 4850 +Wire Wire Line + 10050 7050 10050 4600 +Connection ~ 11950 4600 +Wire Wire Line + 9300 7050 9300 4850 +Connection ~ 11350 4850 +Wire Wire Line + 8700 7050 8700 4200 +Wire Wire Line + 6650 4200 10600 4200 +Connection ~ 10600 4200 +Wire Wire Line + 7400 4850 7400 7050 +Connection ~ 9300 4850 +Wire Wire Line + 6050 7050 6050 5100 +Wire Wire Line + 6050 5100 7950 5100 +Connection ~ 7950 5100 +Wire Wire Line + 6650 7050 6650 4200 +Connection ~ 8700 4200 +Wire Wire Line + 15450 7900 15450 8250 +Wire Wire Line + 15450 8250 15250 8250 +Wire Wire Line + 15250 8250 15250 8500 +Wire Wire Line + 15150 8500 15150 8250 +Wire Wire Line + 15150 8250 14700 8250 +Wire Wire Line + 14700 8250 14700 7900 +Wire Wire Line + 14100 7900 14100 8150 +Wire Wire Line + 14100 8150 13800 8150 +Wire Wire Line + 13800 8150 13800 8500 +Wire Wire Line + 13700 8200 13700 8500 +Wire Wire Line + 13700 8200 13350 8200 +Wire Wire Line + 13350 8200 13350 7900 +Wire Wire Line + 12800 7900 12800 8200 +Wire Wire Line + 12800 8200 12600 8200 +Wire Wire Line + 12600 8200 12600 8500 +Wire Wire Line + 12500 8500 12500 8250 +Wire Wire Line + 12500 8250 12050 8250 +Wire Wire Line + 12050 8250 12050 7900 +Wire Wire Line + 11450 7900 11450 8100 +Wire Wire Line + 11450 8100 11150 8100 +Wire Wire Line + 11150 8100 11150 8500 +Wire Wire Line + 11000 8500 11000 8250 +Wire Wire Line + 11000 8250 10700 8250 +Wire Wire Line + 10700 8250 10700 7900 +Wire Wire Line + 11000 8500 11050 8500 +Wire Wire Line + 10150 7900 10150 8150 +Wire Wire Line + 10150 8150 9900 8150 +Wire Wire Line + 9900 8150 9900 8600 +Wire Wire Line + 9800 8600 9800 8150 +Wire Wire Line + 9800 8150 9400 8150 +Wire Wire Line + 9400 8150 9400 7900 +Wire Wire Line + 8800 7900 8800 8200 +Wire Wire Line + 8800 8200 8450 8200 +Wire Wire Line + 8450 8200 8450 8600 +Wire Wire Line + 8350 8250 8350 8600 +Wire Wire Line + 8350 8250 8050 8250 +Wire Wire Line + 8050 8250 8050 7900 +Wire Wire Line + 7500 7900 7500 8200 +Wire Wire Line + 7500 8200 7250 8200 +Wire Wire Line + 7250 8200 7250 8600 +Wire Wire Line + 7150 8600 7150 8300 +Wire Wire Line + 7150 8300 6750 8300 +Wire Wire Line + 6750 8300 6750 7900 +Wire Wire Line + 6150 7900 6150 8150 +Wire Wire Line + 6150 8150 5800 8150 +Wire Wire Line + 5800 8150 5800 8600 +Wire Wire Line + 5700 8600 5700 8150 +Wire Wire Line + 5700 8150 5400 8150 +Wire Wire Line + 5400 8150 5400 7900 +Wire Wire Line + 15200 9400 15200 9600 +Wire Wire Line + 15200 9600 14600 9600 +Wire Wire Line + 14600 9600 14600 9900 +Wire Wire Line + 14500 9650 14500 9900 +Wire Wire Line + 14500 9650 13750 9650 +Wire Wire Line + 13750 9650 13750 9400 +Wire Wire Line + 12550 9400 12550 9550 +Wire Wire Line + 12550 9550 11950 9550 +Wire Wire Line + 11950 9550 11950 9900 +Wire Wire Line + 11850 9600 11850 9900 +Wire Wire Line + 11850 9600 11100 9600 +Wire Wire Line + 11100 9600 11100 9400 +Wire Wire Line + 9850 9500 9850 9700 +Wire Wire Line + 9850 9700 9250 9700 +Wire Wire Line + 9250 9700 9250 10000 +Wire Wire Line + 9150 10000 9150 9750 +Wire Wire Line + 9150 9750 8400 9750 +Wire Wire Line + 8400 9750 8400 9500 +Wire Wire Line + 7200 9500 7200 9750 +Wire Wire Line + 7200 9750 6600 9750 +Wire Wire Line + 6600 9750 6600 10000 +Wire Wire Line + 6500 9750 6500 10000 +Wire Wire Line + 6500 9750 5750 9750 +Wire Wire Line + 5750 9750 5750 9500 +Wire Wire Line + 17700 11300 17700 3500 +Wire Wire Line + 14600 12500 14600 12850 +Wire Wire Line + 11950 12500 11950 12800 +$Comp +L PORT U1 +U 15 1 679DE2A7 +P 14600 13100 +F 0 "U1" H 14650 13200 30 0000 C CNN +F 1 "PORT" H 14600 13100 30 0000 C CNN +F 2 "" H 14600 13100 60 0000 C CNN +F 3 "" H 14600 13100 60 0000 C CNN + 15 14600 13100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 679DE336 +P 11950 13050 +F 0 "U1" H 12000 13150 30 0000 C CNN +F 1 "PORT" H 11950 13050 30 0000 C CNN +F 2 "" H 11950 13050 60 0000 C CNN +F 3 "" H 11950 13050 60 0000 C CNN + 14 11950 13050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 679DE476 +P 9250 12950 +F 0 "U1" H 9300 13050 30 0000 C CNN +F 1 "PORT" H 9250 12950 30 0000 C CNN +F 2 "" H 9250 12950 60 0000 C CNN +F 3 "" H 9250 12950 60 0000 C CNN + 12 9250 12950 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 679DE565 +P 6600 13000 +F 0 "U1" H 6650 13100 30 0000 C CNN +F 1 "PORT" H 6600 13000 30 0000 C CNN +F 2 "" H 6600 13000 60 0000 C CNN +F 3 "" H 6600 13000 60 0000 C CNN + 11 6600 13000 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6550 10900 6550 11750 +Wire Wire Line + 9200 10900 9200 11750 +Wire Wire Line + 11900 10800 11900 11600 +Wire Wire Line + 14550 10800 14550 11600 +$Comp +L d_and U20 +U 1 1 679EFE6B +P 14550 12050 +F 0 "U20" H 14550 12050 60 0000 C CNN +F 1 "d_and" H 14600 12150 60 0000 C CNN +F 2 "" H 14550 12050 60 0000 C CNN +F 3 "" H 14550 12050 60 0000 C CNN + 1 14550 12050 + 0 1 1 0 +$EndComp +$Comp +L d_and U15 +U 1 1 679EFF83 +P 11900 12050 +F 0 "U15" H 11900 12050 60 0000 C CNN +F 1 "d_and" H 11950 12150 60 0000 C CNN +F 2 "" H 11900 12050 60 0000 C CNN +F 3 "" H 11900 12050 60 0000 C CNN + 1 11900 12050 + 0 1 1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 679F0140 +P 9200 12200 +F 0 "U10" H 9200 12200 60 0000 C CNN +F 1 "d_and" H 9250 12300 60 0000 C CNN +F 2 "" H 9200 12200 60 0000 C CNN +F 3 "" H 9200 12200 60 0000 C CNN + 1 9200 12200 + 0 1 1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 679F01D7 +P 6550 12200 +F 0 "U5" H 6550 12200 60 0000 C CNN +F 1 "d_and" H 6600 12300 60 0000 C CNN +F 2 "" H 6550 12200 60 0000 C CNN +F 3 "" H 6550 12200 60 0000 C CNN + 1 6550 12200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6600 12750 6600 12650 +Wire Wire Line + 9250 12700 9250 12650 +Wire Wire Line + 17700 11300 15050 11300 +Wire Wire Line + 15050 10850 15050 11600 +Wire Wire Line + 15050 11600 14650 11600 +Wire Wire Line + 7100 10850 15050 10850 +Wire Wire Line + 12300 11600 12000 11600 +Connection ~ 15050 11300 +Wire Wire Line + 9950 11750 9300 11750 +Connection ~ 12300 10850 +Wire Wire Line + 7100 11750 6650 11750 +Connection ~ 9950 10850 +$Comp +L d_or U14 +U 1 1 67A37333 +P 14500 10350 +F 0 "U14" H 14500 10350 60 0000 C CNN +F 1 "d_or" H 14500 10450 60 0000 C CNN +F 2 "" H 14500 10350 60 0000 C CNN +F 3 "" H 14500 10350 60 0000 C CNN + 1 14500 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U11 +U 1 1 67A375DC +P 11850 10350 +F 0 "U11" H 11850 10350 60 0000 C CNN +F 1 "d_or" H 11850 10450 60 0000 C CNN +F 2 "" H 11850 10350 60 0000 C CNN +F 3 "" H 11850 10350 60 0000 C CNN + 1 11850 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U7 +U 1 1 67A376D5 +P 9150 10450 +F 0 "U7" H 9150 10450 60 0000 C CNN +F 1 "d_or" H 9150 10550 60 0000 C CNN +F 2 "" H 9150 10450 60 0000 C CNN +F 3 "" H 9150 10450 60 0000 C CNN + 1 9150 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U3 +U 1 1 67A377D6 +P 6500 10450 +F 0 "U3" H 6500 10450 60 0000 C CNN +F 1 "d_or" H 6500 10550 60 0000 C CNN +F 2 "" H 6500 10450 60 0000 C CNN +F 3 "" H 6500 10450 60 0000 C CNN + 1 6500 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U16 +U 1 1 67A37A21 +P 15150 8950 +F 0 "U16" H 15150 8950 60 0000 C CNN +F 1 "d_or" H 15150 9050 60 0000 C CNN +F 2 "" H 15150 8950 60 0000 C CNN +F 3 "" H 15150 8950 60 0000 C CNN + 1 15150 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U13 +U 1 1 67A37ADA +P 13700 8950 +F 0 "U13" H 13700 8950 60 0000 C CNN +F 1 "d_or" H 13700 9050 60 0000 C CNN +F 2 "" H 13700 8950 60 0000 C CNN +F 3 "" H 13700 8950 60 0000 C CNN + 1 13700 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U12 +U 1 1 67A37C7D +P 12500 8950 +F 0 "U12" H 12500 8950 60 0000 C CNN +F 1 "d_or" H 12500 9050 60 0000 C CNN +F 2 "" H 12500 8950 60 0000 C CNN +F 3 "" H 12500 8950 60 0000 C CNN + 1 12500 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U9 +U 1 1 67A37CFE +P 11050 8950 +F 0 "U9" H 11050 8950 60 0000 C CNN +F 1 "d_or" H 11050 9050 60 0000 C CNN +F 2 "" H 11050 8950 60 0000 C CNN +F 3 "" H 11050 8950 60 0000 C CNN + 1 11050 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U8 +U 1 1 67A37DF9 +P 9800 9050 +F 0 "U8" H 9800 9050 60 0000 C CNN +F 1 "d_or" H 9800 9150 60 0000 C CNN +F 2 "" H 9800 9050 60 0000 C CNN +F 3 "" H 9800 9050 60 0000 C CNN + 1 9800 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U6 +U 1 1 67A37FCE +P 8350 9050 +F 0 "U6" H 8350 9050 60 0000 C CNN +F 1 "d_or" H 8350 9150 60 0000 C CNN +F 2 "" H 8350 9050 60 0000 C CNN +F 3 "" H 8350 9050 60 0000 C CNN + 1 8350 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U4 +U 1 1 67A38059 +P 7150 9050 +F 0 "U4" H 7150 9050 60 0000 C CNN +F 1 "d_or" H 7150 9150 60 0000 C CNN +F 2 "" H 7150 9050 60 0000 C CNN +F 3 "" H 7150 9050 60 0000 C CNN + 1 7150 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U2 +U 1 1 67A38154 +P 5700 9050 +F 0 "U2" H 5700 9050 60 0000 C CNN +F 1 "d_or" H 5700 9150 60 0000 C CNN +F 2 "" H 5700 9050 60 0000 C CNN +F 3 "" H 5700 9050 60 0000 C CNN + 1 5700 9050 + 0 1 1 0 +$EndComp +Wire Wire Line + 12300 11600 12300 10850 +Wire Wire Line + 9950 11750 9950 10850 +Wire Wire Line + 7100 10850 7100 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/74F350.sub b/library/SubcircuitLibrary/74F350/74F350.sub new file mode 100644 index 00000000..39ba9abb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sub @@ -0,0 +1,107 @@ +* Subcircuit 74F350 +.subckt 74F350 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74F350
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml new file mode 100644 index 00000000..bc7f0ee5 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u26 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u26><u24 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u25><u23 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u21 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u12 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u11><u7 name="type">d_nor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_nor<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u6><u2 name="type">d_nor<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nor<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u3><u20 name="type">d_tristate<field52 name="Enter Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Enable Load (default=1.0e-12)" /></u20><u15 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u15><u10 name="type">d_tristate<field58 name="Enter Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Enable Load (default=1.0e-12)" /></u10><u5 name="type">d_tristate<field61 name="Enter Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Enable Load (default=1.0e-12)" /></u5><u4 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u14><u19 name="type">d_inverter<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u19><u10 name="type">d_nand<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_nand<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_nand<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u4><u20 name="type">d_and<field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u20><u15 name="type">d_and<field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u10><u5 name="type">d_and<field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u5><u14 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u11 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u11><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u3 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u16 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u16><u13 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u13><u12 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u12><u9 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u8 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u8><u6 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_or<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x10><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x15><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x16></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/analysis b/library/SubcircuitLibrary/74F350/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and-cache.lib b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir b/library/SubcircuitLibrary/CD4532B/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir.out b/library/SubcircuitLibrary/CD4532B/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.pro b/library/SubcircuitLibrary/CD4532B/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sch b/library/SubcircuitLibrary/CD4532B/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sub b/library/SubcircuitLibrary/CD4532B/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir b/library/SubcircuitLibrary/CD4532B/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir.out b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.pro b/library/SubcircuitLibrary/CD4532B/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sch b/library/SubcircuitLibrary/CD4532B/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sub b/library/SubcircuitLibrary/CD4532B/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and-cache.lib b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir b/library/SubcircuitLibrary/CD4532B/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir.out b/library/SubcircuitLibrary/CD4532B/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.pro b/library/SubcircuitLibrary/CD4532B/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sch b/library/SubcircuitLibrary/CD4532B/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sub b/library/SubcircuitLibrary/CD4532B/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib new file mode 100644 index 00000000..fbb8d926 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir b/library/SubcircuitLibrary/CD4532B/CD4532B.cir new file mode 100644 index 00000000..cd581690 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir @@ -0,0 +1,54 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\CD4532B\CD4532B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/10/25 20:14:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad11_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U4 Net-_U1-Pad13_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U1-Pad2_ Net-_U12-Pad1_ d_inverter +U8 Net-_U1-Pad3_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad4_ Net-_U6-Pad2_ d_inverter +U9 Net-_U1-Pad5_ Net-_U14-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +X1 Net-_U2-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_X1-Pad5_ 4_OR +X2 Net-_U13-Pad2_ Net-_U11-Pad2_ Net-_U4-Pad2_ ? Net-_X2-Pad5_ 4_OR +X3 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X3-Pad5_ 4_OR +X4 Net-_U4-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X4-Pad5_ 4_OR +U22 Net-_U22-Pad1_ Net-_U16-Pad1_ d_inverter +U23 Net-_U23-Pad1_ Net-_U15-Pad1_ d_inverter +U24 Net-_U16-Pad1_ Net-_U15-Pad1_ Net-_U24-Pad3_ d_nand +X5 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U19-Pad3_ Net-_U6-Pad2_ Net-_U25-Pad1_ 4_and +X6 Net-_X3-Pad5_ Net-_X4-Pad5_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U27-Pad1_ 4_and +X7 Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U26-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U29 Net-_U25-Pad2_ Net-_U14-Pad2_ Net-_U29-Pad3_ d_nand +U30 Net-_U27-Pad2_ Net-_U14-Pad2_ Net-_U30-Pad3_ d_nand +U31 Net-_U26-Pad2_ Net-_U14-Pad2_ Net-_U31-Pad3_ d_nand +U32 Net-_U24-Pad3_ Net-_U1-Pad5_ Net-_U32-Pad3_ d_nand +U34 Net-_U29-Pad3_ Net-_U1-Pad9_ d_inverter +U33 Net-_U30-Pad3_ Net-_U1-Pad7_ d_inverter +U36 Net-_U31-Pad3_ Net-_U1-Pad6_ d_inverter +U37 Net-_U32-Pad3_ Net-_U1-Pad14_ d_inverter +U35 Net-_U20-Pad3_ Net-_U1-Pad15_ d_inverter +U19 Net-_U13-Pad2_ Net-_U12-Pad1_ Net-_U19-Pad3_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U22-Pad1_ 4_OR +X9 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U23-Pad1_ 4_OR +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U1-Pad5_ Net-_U17-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U18 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_or +U20 Net-_U18-Pad3_ Net-_U17-Pad2_ Net-_U20-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out new file mode 100644 index 00000000..40e32465 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out @@ -0,0 +1,159 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.pro b/library/SubcircuitLibrary/CD4532B/CD4532B.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sch b/library/SubcircuitLibrary/CD4532B/CD4532B.sch new file mode 100644 index 00000000..626b76df --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sch @@ -0,0 +1,1074 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:CD4532B-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 67A4FD25 +P 7050 4200 +F 0 "U2" H 7050 4100 60 0000 C CNN +F 1 "d_inverter" H 7050 4350 60 0000 C CNN +F 2 "" H 7100 4150 60 0000 C CNN +F 3 "" H 7100 4150 60 0000 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67A4FD58 +P 7050 4850 +F 0 "U3" H 7050 4750 60 0000 C CNN +F 1 "d_inverter" H 7050 5000 60 0000 C CNN +F 2 "" H 7100 4800 60 0000 C CNN +F 3 "" H 7100 4800 60 0000 C CNN + 1 7050 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67A4FD79 +P 7050 6350 +F 0 "U4" H 7050 6250 60 0000 C CNN +F 1 "d_inverter" H 7050 6500 60 0000 C CNN +F 2 "" H 7100 6300 60 0000 C CNN +F 3 "" H 7100 6300 60 0000 C CNN + 1 7050 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67A4FDA4 +P 7050 7350 +F 0 "U5" H 7050 7250 60 0000 C CNN +F 1 "d_inverter" H 7050 7500 60 0000 C CNN +F 2 "" H 7100 7300 60 0000 C CNN +F 3 "" H 7100 7300 60 0000 C CNN + 1 7050 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 67A4FE34 +P 7100 8050 +F 0 "U7" H 7100 7950 60 0000 C CNN +F 1 "d_inverter" H 7100 8200 60 0000 C CNN +F 2 "" H 7150 8000 60 0000 C CNN +F 3 "" H 7150 8000 60 0000 C CNN + 1 7100 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 67A4FE3A +P 7100 8700 +F 0 "U8" H 7100 8600 60 0000 C CNN +F 1 "d_inverter" H 7100 8850 60 0000 C CNN +F 2 "" H 7150 8650 60 0000 C CNN +F 3 "" H 7150 8650 60 0000 C CNN + 1 7100 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 67A4FE40 +P 7050 9300 +F 0 "U6" H 7050 9200 60 0000 C CNN +F 1 "d_inverter" H 7050 9450 60 0000 C CNN +F 2 "" H 7100 9250 60 0000 C CNN +F 3 "" H 7100 9250 60 0000 C CNN + 1 7050 9300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67A4FE4F +P 7150 11450 +F 0 "U9" H 7150 11350 60 0000 C CNN +F 1 "d_inverter" H 7150 11600 60 0000 C CNN +F 2 "" H 7200 11400 60 0000 C CNN +F 3 "" H 7200 11400 60 0000 C CNN + 1 7150 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 67A4FF04 +P 8400 4850 +F 0 "U10" H 8400 4750 60 0000 C CNN +F 1 "d_inverter" H 8400 5000 60 0000 C CNN +F 2 "" H 8450 4800 60 0000 C CNN +F 3 "" H 8450 4800 60 0000 C CNN + 1 8400 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 67A4FF41 +P 8400 7350 +F 0 "U11" H 8400 7250 60 0000 C CNN +F 1 "d_inverter" H 8400 7500 60 0000 C CNN +F 2 "" H 8450 7300 60 0000 C CNN +F 3 "" H 8450 7300 60 0000 C CNN + 1 8400 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 67A4FF6C +P 8400 8050 +F 0 "U12" H 8400 7950 60 0000 C CNN +F 1 "d_inverter" H 8400 8200 60 0000 C CNN +F 2 "" H 8450 8000 60 0000 C CNN +F 3 "" H 8450 8000 60 0000 C CNN + 1 8400 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 67A4FF9D +P 8400 8700 +F 0 "U13" H 8400 8600 60 0000 C CNN +F 1 "d_inverter" H 8400 8850 60 0000 C CNN +F 2 "" H 8450 8650 60 0000 C CNN +F 3 "" H 8450 8650 60 0000 C CNN + 1 8400 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 67A4FFE2 +P 8550 11450 +F 0 "U14" H 8550 11350 60 0000 C CNN +F 1 "d_inverter" H 8550 11600 60 0000 C CNN +F 2 "" H 8600 11400 60 0000 C CNN +F 3 "" H 8600 11400 60 0000 C CNN + 1 8550 11450 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X1 +U 1 1 67A500F9 +P 10400 4300 +F 0 "X1" H 10550 4200 60 0000 C CNN +F 1 "4_OR" H 10550 4400 60 0000 C CNN +F 2 "" H 10400 4300 60 0000 C CNN +F 3 "" H 10400 4300 60 0000 C CNN + 1 10400 4300 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67A5B522 +P 10400 5150 +F 0 "X2" H 10550 5050 60 0000 C CNN +F 1 "4_OR" H 10550 5250 60 0000 C CNN +F 2 "" H 10400 5150 60 0000 C CNN +F 3 "" H 10400 5150 60 0000 C CNN + 1 10400 5150 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 67A5B8C6 +P 10400 7350 +F 0 "X3" H 10550 7250 60 0000 C CNN +F 1 "4_OR" H 10550 7450 60 0000 C CNN +F 2 "" H 10400 7350 60 0000 C CNN +F 3 "" H 10400 7350 60 0000 C CNN + 1 10400 7350 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X4 +U 1 1 67A5B911 +P 10400 8400 +F 0 "X4" H 10550 8300 60 0000 C CNN +F 1 "4_OR" H 10550 8500 60 0000 C CNN +F 2 "" H 10400 8400 60 0000 C CNN +F 3 "" H 10400 8400 60 0000 C CNN + 1 10400 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 67A5BD44 +P 11550 9600 +F 0 "U22" H 11550 9500 60 0000 C CNN +F 1 "d_inverter" H 11550 9750 60 0000 C CNN +F 2 "" H 11600 9550 60 0000 C CNN +F 3 "" H 11600 9550 60 0000 C CNN + 1 11550 9600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 67A5BDD7 +P 11650 10300 +F 0 "U23" H 11650 10200 60 0000 C CNN +F 1 "d_inverter" H 11650 10450 60 0000 C CNN +F 2 "" H 11700 10250 60 0000 C CNN +F 3 "" H 11700 10250 60 0000 C CNN + 1 11650 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 67A5BEDF +P 13350 9650 +F 0 "U24" H 13350 9650 60 0000 C CNN +F 1 "d_nand" H 13400 9750 60 0000 C CNN +F 2 "" H 13350 9650 60 0000 C CNN +F 3 "" H 13350 9650 60 0000 C CNN + 1 13350 9650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 67A5BF59 +P 12500 4600 +F 0 "X5" H 12550 4550 60 0000 C CNN +F 1 "4_and" H 12600 4700 60 0000 C CNN +F 2 "" H 12500 4600 60 0000 C CNN +F 3 "" H 12500 4600 60 0000 C CNN + 1 12500 4600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 67A5BFC2 +P 12550 6050 +F 0 "X6" H 12600 6000 60 0000 C CNN +F 1 "4_and" H 12650 6150 60 0000 C CNN +F 2 "" H 12550 6050 60 0000 C CNN +F 3 "" H 12550 6050 60 0000 C CNN + 1 12550 6050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 67A5C035 +P 12550 7900 +F 0 "X7" H 12600 7850 60 0000 C CNN +F 1 "4_and" H 12650 8000 60 0000 C CNN +F 2 "" H 12550 7900 60 0000 C CNN +F 3 "" H 12550 7900 60 0000 C CNN + 1 12550 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 67A5C183 +P 13500 4600 +F 0 "U25" H 13500 4500 60 0000 C CNN +F 1 "d_inverter" H 13500 4750 60 0000 C CNN +F 2 "" H 13550 4550 60 0000 C CNN +F 3 "" H 13550 4550 60 0000 C CNN + 1 13500 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 67A5C189 +P 13650 6050 +F 0 "U27" H 13650 5950 60 0000 C CNN +F 1 "d_inverter" H 13650 6200 60 0000 C CNN +F 2 "" H 13700 6000 60 0000 C CNN +F 3 "" H 13700 6000 60 0000 C CNN + 1 13650 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 67A5C18F +P 13600 7900 +F 0 "U26" H 13600 7800 60 0000 C CNN +F 1 "d_inverter" H 13600 8050 60 0000 C CNN +F 2 "" H 13650 7850 60 0000 C CNN +F 3 "" H 13650 7850 60 0000 C CNN + 1 13600 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U29 +U 1 1 67A5C873 +P 15300 4900 +F 0 "U29" H 15300 4900 60 0000 C CNN +F 1 "d_nand" H 15350 5000 60 0000 C CNN +F 2 "" H 15300 4900 60 0000 C CNN +F 3 "" H 15300 4900 60 0000 C CNN + 1 15300 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U30 +U 1 1 67A5C90C +P 15300 6800 +F 0 "U30" H 15300 6800 60 0000 C CNN +F 1 "d_nand" H 15350 6900 60 0000 C CNN +F 2 "" H 15300 6800 60 0000 C CNN +F 3 "" H 15300 6800 60 0000 C CNN + 1 15300 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U31 +U 1 1 67A5C99B +P 15350 8550 +F 0 "U31" H 15350 8550 60 0000 C CNN +F 1 "d_nand" H 15400 8650 60 0000 C CNN +F 2 "" H 15350 8550 60 0000 C CNN +F 3 "" H 15350 8550 60 0000 C CNN + 1 15350 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U32 +U 1 1 67A5CA32 +P 15400 10350 +F 0 "U32" H 15400 10350 60 0000 C CNN +F 1 "d_nand" H 15450 10450 60 0000 C CNN +F 2 "" H 15400 10350 60 0000 C CNN +F 3 "" H 15400 10350 60 0000 C CNN + 1 15400 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 67A5CB45 +P 16750 4850 +F 0 "U34" H 16750 4750 60 0000 C CNN +F 1 "d_inverter" H 16750 5000 60 0000 C CNN +F 2 "" H 16800 4800 60 0000 C CNN +F 3 "" H 16800 4800 60 0000 C CNN + 1 16750 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 67A5CB4B +P 16700 6750 +F 0 "U33" H 16700 6650 60 0000 C CNN +F 1 "d_inverter" H 16700 6900 60 0000 C CNN +F 2 "" H 16750 6700 60 0000 C CNN +F 3 "" H 16750 6700 60 0000 C CNN + 1 16700 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 67A5CB51 +P 16800 8500 +F 0 "U36" H 16800 8400 60 0000 C CNN +F 1 "d_inverter" H 16800 8650 60 0000 C CNN +F 2 "" H 16850 8450 60 0000 C CNN +F 3 "" H 16850 8450 60 0000 C CNN + 1 16800 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 67A5CB57 +P 16800 10300 +F 0 "U37" H 16800 10200 60 0000 C CNN +F 1 "d_inverter" H 16800 10450 60 0000 C CNN +F 2 "" H 16850 10250 60 0000 C CNN +F 3 "" H 16850 10250 60 0000 C CNN + 1 16800 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 67A5CB5D +P 16750 10900 +F 0 "U35" H 16750 10800 60 0000 C CNN +F 1 "d_inverter" H 16750 11050 60 0000 C CNN +F 2 "" H 16800 10850 60 0000 C CNN +F 3 "" H 16800 10850 60 0000 C CNN + 1 16750 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 67A5EBCA +P 10650 6200 +F 0 "U19" H 10650 6200 60 0000 C CNN +F 1 "d_or" H 10650 6300 60 0000 C CNN +F 2 "" H 10650 6200 60 0000 C CNN +F 3 "" H 10650 6200 60 0000 C CNN + 1 10650 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 4200 4450 4200 +Wire Wire Line + 6750 4850 4400 4850 +Wire Wire Line + 6750 6350 4350 6350 +Wire Wire Line + 6750 7350 4300 7350 +Wire Wire Line + 6800 8050 4200 8050 +Wire Wire Line + 6800 8700 4200 8700 +Wire Wire Line + 6750 9300 4200 9300 +Wire Wire Line + 6850 11450 3450 11450 +Wire Wire Line + 7450 11450 8250 11450 +Wire Wire Line + 7350 4200 7450 4200 +Wire Wire Line + 7450 4200 7450 4150 +Wire Wire Line + 7450 4150 10050 4150 +Wire Wire Line + 7350 4850 8100 4850 +Wire Wire Line + 8700 4850 9000 4850 +Wire Wire Line + 9000 4850 9000 4250 +Wire Wire Line + 9000 4250 10050 4250 +Wire Wire Line + 10050 4450 9800 4450 +Wire Wire Line + 9800 4450 9800 6900 +Wire Wire Line + 9800 5000 10050 5000 +Wire Wire Line + 9150 4350 10050 4350 +Wire Wire Line + 9800 6100 10200 6100 +Connection ~ 9800 5000 +Wire Wire Line + 9150 7300 10050 7300 +Wire Wire Line + 7850 4850 7850 5350 +Wire Wire Line + 7850 5350 9400 5350 +Wire Wire Line + 9400 5350 9400 7200 +Wire Wire Line + 9400 7200 10050 7200 +Connection ~ 7850 4850 +Wire Wire Line + 7350 6350 9250 6350 +Wire Wire Line + 9250 5200 9250 7600 +Wire Wire Line + 9250 7600 9850 7600 +Wire Wire Line + 9850 7600 9850 8250 +Wire Wire Line + 9850 8250 10050 8250 +Wire Wire Line + 9250 5200 10050 5200 +Connection ~ 9250 6350 +Wire Wire Line + 7350 7350 8100 7350 +Wire Wire Line + 7400 8050 8100 8050 +Wire Wire Line + 8100 8700 7400 8700 +Wire Wire Line + 8700 7350 9150 7350 +Wire Wire Line + 9150 4350 9150 7700 +Wire Wire Line + 9150 7700 9750 7700 +Wire Wire Line + 9750 7700 9750 8350 +Wire Wire Line + 9750 8350 10050 8350 +Connection ~ 9150 7350 +Wire Wire Line + 10050 5100 9150 5100 +Connection ~ 9150 5100 +Connection ~ 9150 7300 +Wire Wire Line + 7800 7350 7800 7800 +Wire Wire Line + 7800 7800 11450 7800 +Wire Wire Line + 11450 7800 11450 7750 +Wire Wire Line + 11450 7750 12150 7750 +Connection ~ 7800 7350 +Wire Wire Line + 8700 8050 9650 8050 +Wire Wire Line + 9650 7400 9650 8450 +Wire Wire Line + 9650 8450 10050 8450 +Wire Wire Line + 9650 7400 10050 7400 +Connection ~ 9650 8050 +Wire Wire Line + 7800 8050 7800 8250 +Wire Wire Line + 7800 8250 9500 8250 +Wire Wire Line + 9500 8250 9500 6200 +Wire Wire Line + 9500 6200 10200 6200 +Connection ~ 7800 8050 +Wire Wire Line + 9500 7900 11550 7900 +Wire Wire Line + 11550 7900 11550 7850 +Wire Wire Line + 11550 7850 12150 7850 +Connection ~ 9500 7900 +Wire Wire Line + 9800 6900 9300 6900 +Wire Wire Line + 9300 6900 9300 8700 +Wire Wire Line + 9300 8700 8700 8700 +Connection ~ 9800 6100 +Wire Wire Line + 7850 8700 7850 8900 +Wire Wire Line + 7850 8900 11800 8900 +Wire Wire Line + 11800 8900 11800 6100 +Wire Wire Line + 11800 7950 12150 7950 +Connection ~ 7850 8700 +Wire Wire Line + 11800 6100 12150 6100 +Connection ~ 11800 7950 +Wire Wire Line + 13050 6050 13350 6050 +Wire Wire Line + 13300 7900 13050 7900 +Wire Wire Line + 7350 9300 7650 9300 +Wire Wire Line + 7650 9300 7650 9000 +Wire Wire Line + 7650 9000 11950 9000 +Wire Wire Line + 11950 9000 11950 4750 +Wire Wire Line + 11950 8050 12150 8050 +Wire Wire Line + 11950 6200 12150 6200 +Connection ~ 11950 8050 +Wire Wire Line + 11950 4750 12100 4750 +Connection ~ 11950 6200 +Wire Wire Line + 6600 9300 6600 9500 +Wire Wire Line + 6600 9500 7750 9500 +Wire Wire Line + 7750 9500 7750 9450 +Wire Wire Line + 7750 9450 10200 9450 +Connection ~ 6600 9300 +Wire Wire Line + 6400 8700 6400 9600 +Wire Wire Line + 6400 9600 9750 9600 +Wire Wire Line + 9750 9600 9750 9550 +Wire Wire Line + 9750 9550 10200 9550 +Connection ~ 6400 8700 +Wire Wire Line + 6200 8050 6200 9700 +Wire Wire Line + 6200 9700 10200 9700 +Connection ~ 6200 8050 +Wire Wire Line + 6000 9800 10200 9800 +Wire Wire Line + 6000 9800 6000 7350 +Connection ~ 6000 7350 +Wire Wire Line + 5700 6350 5700 10150 +Wire Wire Line + 5700 10150 10250 10150 +Connection ~ 5700 6350 +Wire Wire Line + 5500 10250 10250 10250 +Wire Wire Line + 5500 10250 5500 4850 +Connection ~ 5500 4850 +Wire Wire Line + 10100 10400 5300 10400 +Wire Wire Line + 5300 10400 5300 4200 +Connection ~ 5300 4200 +Wire Wire Line + 3650 10500 10250 10500 +Connection ~ 6400 11450 +Wire Wire Line + 14650 10900 16450 10900 +Wire Wire Line + 8850 11450 14700 11450 +Wire Wire Line + 14700 11450 14700 4900 +Wire Wire Line + 14700 4900 14850 4900 +Wire Wire Line + 14850 6800 14700 6800 +Connection ~ 14700 6800 +Wire Wire Line + 14900 8550 14700 8550 +Connection ~ 14700 8550 +Wire Wire Line + 13800 9600 14300 9600 +Wire Wire Line + 14300 9600 14300 10250 +Wire Wire Line + 14300 10250 14950 10250 +Wire Wire Line + 15850 10300 16500 10300 +Wire Wire Line + 10950 4300 11850 4300 +Wire Wire Line + 11850 4300 11850 4450 +Wire Wire Line + 11850 4450 12100 4450 +Wire Wire Line + 10950 5150 11150 5150 +Wire Wire Line + 11150 5150 11150 4550 +Wire Wire Line + 11150 4550 12100 4550 +Wire Wire Line + 11100 6150 11450 6150 +Wire Wire Line + 11450 6150 11450 4650 +Wire Wire Line + 11450 4650 12100 4650 +Wire Wire Line + 10950 7350 11600 7350 +Wire Wire Line + 11600 7350 11600 5900 +Wire Wire Line + 11600 5900 12150 5900 +Wire Wire Line + 10950 8400 11700 8400 +Wire Wire Line + 11700 8400 11700 6000 +Wire Wire Line + 11700 6000 12150 6000 +Wire Wire Line + 13200 4600 13000 4600 +Wire Wire Line + 13800 4600 14400 4600 +Wire Wire Line + 14400 4600 14400 4800 +Wire Wire Line + 14400 4800 14850 4800 +Wire Wire Line + 13950 6050 14350 6050 +Wire Wire Line + 14350 6050 14350 6700 +Wire Wire Line + 14350 6700 14850 6700 +Wire Wire Line + 13900 7900 14400 7900 +Wire Wire Line + 14400 7900 14400 8450 +Wire Wire Line + 14400 8450 14900 8450 +Wire Wire Line + 15750 4850 16450 4850 +Wire Wire Line + 15750 6750 16400 6750 +Wire Wire Line + 16500 8500 15800 8500 +Wire Wire Line + 17050 4850 17950 4850 +Wire Wire Line + 17000 6750 18500 6750 +Wire Wire Line + 17100 8500 18550 8500 +Wire Wire Line + 17100 10300 18600 10300 +Wire Wire Line + 17050 10900 18600 10900 +$Comp +L PORT U1 +U 11 1 67A67004 +P 4200 4200 +F 0 "U1" H 4250 4300 30 0000 C CNN +F 1 "PORT" H 4200 4200 30 0000 C CNN +F 2 "" H 4200 4200 60 0000 C CNN +F 3 "" H 4200 4200 60 0000 C CNN + 11 4200 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67A671AB +P 4150 4850 +F 0 "U1" H 4200 4950 30 0000 C CNN +F 1 "PORT" H 4150 4850 30 0000 C CNN +F 2 "" H 4150 4850 60 0000 C CNN +F 3 "" H 4150 4850 60 0000 C CNN + 12 4150 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67A673CE +P 4100 6350 +F 0 "U1" H 4150 6450 30 0000 C CNN +F 1 "PORT" H 4100 6350 30 0000 C CNN +F 2 "" H 4100 6350 60 0000 C CNN +F 3 "" H 4100 6350 60 0000 C CNN + 13 4100 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67A675BD +P 4050 7350 +F 0 "U1" H 4100 7450 30 0000 C CNN +F 1 "PORT" H 4050 7350 30 0000 C CNN +F 2 "" H 4050 7350 60 0000 C CNN +F 3 "" H 4050 7350 60 0000 C CNN + 1 4050 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67A67752 +P 3950 8050 +F 0 "U1" H 4000 8150 30 0000 C CNN +F 1 "PORT" H 3950 8050 30 0000 C CNN +F 2 "" H 3950 8050 60 0000 C CNN +F 3 "" H 3950 8050 60 0000 C CNN + 2 3950 8050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67A67986 +P 3950 8700 +F 0 "U1" H 4000 8800 30 0000 C CNN +F 1 "PORT" H 3950 8700 30 0000 C CNN +F 2 "" H 3950 8700 60 0000 C CNN +F 3 "" H 3950 8700 60 0000 C CNN + 3 3950 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67A67BC3 +P 3950 9300 +F 0 "U1" H 4000 9400 30 0000 C CNN +F 1 "PORT" H 3950 9300 30 0000 C CNN +F 2 "" H 3950 9300 60 0000 C CNN +F 3 "" H 3950 9300 60 0000 C CNN + 4 3950 9300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67A67DDA +P 3400 10500 +F 0 "U1" H 3450 10600 30 0000 C CNN +F 1 "PORT" H 3400 10500 30 0000 C CNN +F 2 "" H 3400 10500 60 0000 C CNN +F 3 "" H 3400 10500 60 0000 C CNN + 10 3400 10500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67A67EF9 +P 3200 11450 +F 0 "U1" H 3250 11550 30 0000 C CNN +F 1 "PORT" H 3200 11450 30 0000 C CNN +F 2 "" H 3200 11450 60 0000 C CNN +F 3 "" H 3200 11450 60 0000 C CNN + 5 3200 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67A681F4 +P 18200 4850 +F 0 "U1" H 18250 4950 30 0000 C CNN +F 1 "PORT" H 18200 4850 30 0000 C CNN +F 2 "" H 18200 4850 60 0000 C CNN +F 3 "" H 18200 4850 60 0000 C CNN + 9 18200 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 67A68454 +P 18750 6750 +F 0 "U1" H 18800 6850 30 0000 C CNN +F 1 "PORT" H 18750 6750 30 0000 C CNN +F 2 "" H 18750 6750 60 0000 C CNN +F 3 "" H 18750 6750 60 0000 C CNN + 7 18750 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 67A68779 +P 18800 8500 +F 0 "U1" H 18850 8600 30 0000 C CNN +F 1 "PORT" H 18800 8500 30 0000 C CNN +F 2 "" H 18800 8500 60 0000 C CNN +F 3 "" H 18800 8500 60 0000 C CNN + 6 18800 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 67A68A78 +P 18850 10300 +F 0 "U1" H 18900 10400 30 0000 C CNN +F 1 "PORT" H 18850 10300 30 0000 C CNN +F 2 "" H 18850 10300 60 0000 C CNN +F 3 "" H 18850 10300 60 0000 C CNN + 14 18850 10300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 67A68BEF +P 18850 10900 +F 0 "U1" H 18900 11000 30 0000 C CNN +F 1 "PORT" H 18850 10900 30 0000 C CNN +F 2 "" H 18850 10900 60 0000 C CNN +F 3 "" H 18850 10900 60 0000 C CNN + 15 18850 10900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67A68CDF +P 18650 9150 +F 0 "U1" H 18700 9250 30 0000 C CNN +F 1 "PORT" H 18650 9150 30 0000 C CNN +F 2 "" H 18650 9150 60 0000 C CNN +F 3 "" H 18650 9150 60 0000 C CNN + 8 18650 9150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67A68D6C +P 18650 9350 +F 0 "U1" H 18700 9450 30 0000 C CNN +F 1 "PORT" H 18650 9350 30 0000 C CNN +F 2 "" H 18650 9350 60 0000 C CNN +F 3 "" H 18650 9350 60 0000 C CNN + 16 18650 9350 + 1 0 0 -1 +$EndComp +NoConn ~ 18900 9150 +NoConn ~ 18900 9350 +$Comp +L 4_OR X8 +U 1 1 67AA119F +P 10550 9600 +F 0 "X8" H 10700 9500 60 0000 C CNN +F 1 "4_OR" H 10700 9700 60 0000 C CNN +F 2 "" H 10550 9600 60 0000 C CNN +F 3 "" H 10550 9600 60 0000 C CNN + 1 10550 9600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 9700 10200 9650 +Wire Wire Line + 10200 9800 10200 9750 +$Comp +L 4_OR X9 +U 1 1 67AA15F9 +P 10600 10300 +F 0 "X9" H 10750 10200 60 0000 C CNN +F 1 "4_OR" H 10750 10400 60 0000 C CNN +F 2 "" H 10600 10300 60 0000 C CNN +F 3 "" H 10600 10300 60 0000 C CNN + 1 10600 10300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10250 10350 10100 10350 +Wire Wire Line + 10100 10350 10100 10400 +Wire Wire Line + 10250 10500 10250 10450 +Wire Wire Line + 11250 9600 11100 9600 +Wire Wire Line + 11350 10300 11150 10300 +$Comp +L d_inverter U16 +U 1 1 67AA23A3 +P 12750 10700 +F 0 "U16" H 12750 10600 60 0000 C CNN +F 1 "d_inverter" H 12750 10850 60 0000 C CNN +F 2 "" H 12800 10650 60 0000 C CNN +F 3 "" H 12800 10650 60 0000 C CNN + 1 12750 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 67AA2430 +P 12750 11050 +F 0 "U17" H 12750 10950 60 0000 C CNN +F 1 "d_inverter" H 12750 11200 60 0000 C CNN +F 2 "" H 12800 11000 60 0000 C CNN +F 3 "" H 12800 11000 60 0000 C CNN + 1 12750 11050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 67AA24BF +P 12750 10350 +F 0 "U15" H 12750 10250 60 0000 C CNN +F 1 "d_inverter" H 12750 10500 60 0000 C CNN +F 2 "" H 12800 10300 60 0000 C CNN +F 3 "" H 12800 10300 60 0000 C CNN + 1 12750 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 67AA2582 +P 13650 10500 +F 0 "U18" H 13650 10500 60 0000 C CNN +F 1 "d_or" H 13650 10600 60 0000 C CNN +F 2 "" H 13650 10500 60 0000 C CNN +F 3 "" H 13650 10500 60 0000 C CNN + 1 13650 10500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67AA2694 +P 14200 10950 +F 0 "U20" H 14200 10950 60 0000 C CNN +F 1 "d_or" H 14200 11050 60 0000 C CNN +F 2 "" H 14200 10950 60 0000 C CNN +F 3 "" H 14200 10950 60 0000 C CNN + 1 14200 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14100 10450 14200 10450 +Wire Wire Line + 14200 10450 14200 10700 +Wire Wire Line + 14200 10700 13650 10700 +Wire Wire Line + 13650 10700 13650 10850 +Wire Wire Line + 13650 10850 13750 10850 +Wire Wire Line + 13050 10350 13200 10350 +Wire Wire Line + 13200 10350 13200 10400 +Wire Wire Line + 13200 10500 13200 10700 +Wire Wire Line + 13200 10700 13050 10700 +Wire Wire Line + 13050 11050 13650 11050 +Wire Wire Line + 13650 11050 13650 10950 +Wire Wire Line + 13650 10950 13750 10950 +Wire Wire Line + 6400 11050 12450 11050 +Wire Wire Line + 6400 11050 6400 11450 +Wire Wire Line + 11950 11050 11950 11250 +Wire Wire Line + 11950 11250 14800 11250 +Connection ~ 11950 11050 +Wire Wire Line + 14950 10350 14800 10350 +Wire Wire Line + 14800 10350 14800 11250 +Wire Wire Line + 11850 9600 12300 9600 +Wire Wire Line + 12300 9600 12300 9550 +Wire Wire Line + 12300 9550 12900 9550 +Wire Wire Line + 11950 10300 12250 10300 +Wire Wire Line + 12250 9950 12250 10350 +Wire Wire Line + 12250 9950 12650 9950 +Wire Wire Line + 12650 9950 12650 9650 +Wire Wire Line + 12650 9650 12900 9650 +Wire Wire Line + 12250 10350 12450 10350 +Connection ~ 12250 10300 +Wire Wire Line + 12100 9600 12100 10700 +Wire Wire Line + 12100 10700 12450 10700 +Connection ~ 12100 9600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sub b/library/SubcircuitLibrary/CD4532B/CD4532B.sub new file mode 100644 index 00000000..4f812629 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sub @@ -0,0 +1,153 @@ +* Subcircuit CD4532B +.subckt CD4532B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends CD4532B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml new file mode 100644 index 00000000..cd7a8a8d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u22 name="type">d_inverter<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u22><u17 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u23 name="type">d_inverter<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u27 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u26><u28 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_nand<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u32><u34 name="type">d_inverter<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u34><u33 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u33><u36 name="type">d_inverter<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u36><u37 name="type">d_inverter<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u37><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u35><u19 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_or<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u38 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u16 name="type">d_inverter<field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_inverter<field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u17><u15 name="type">d_inverter<field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x8><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x4><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x9><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/analysis b/library/SubcircuitLibrary/CD4532B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir new file mode 100644 index 00000000..e0c1478f --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\HD74LS152\HD74LS152.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/18/25 21:34:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U1-Pad5_ Net-_U12-Pad2_ Net-_U24-Pad1_ d_and +U9 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U24-Pad2_ d_and +U10 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and +U15 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and +U16 Net-_U1-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_and +U17 Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U18 Net-_U1-Pad13_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U19 Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U1-Pad12_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U23 Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U23-Pad3_ d_and +U32 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_or +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U25 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U25-Pad3_ d_and +U26 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U26-Pad3_ d_and +U27 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U27-Pad3_ d_and +U28 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U28-Pad3_ d_and +U29 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U29-Pad3_ d_and +U30 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U30-Pad3_ d_and +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_and +U33 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_or +U35 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_or +U34 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ d_or +U36 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U36-Pad3_ d_or +U37 Net-_U35-Pad3_ Net-_U34-Pad3_ Net-_U37-Pad3_ d_or +U38 Net-_U36-Pad3_ Net-_U37-Pad3_ Net-_U38-Pad3_ d_or +U39 Net-_U38-Pad3_ Net-_U1-Pad6_ d_inverter +U4 Net-_U1-Pad10_ Net-_U12-Pad2_ d_inverter +U7 Net-_U12-Pad2_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad9_ Net-_U11-Pad1_ d_inverter +U5 Net-_U11-Pad1_ Net-_U13-Pad1_ d_inverter +U3 Net-_U1-Pad8_ Net-_U11-Pad2_ d_inverter +U6 Net-_U11-Pad2_ Net-_U17-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out new file mode 100644 index 00000000..db09e46d --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out @@ -0,0 +1,164 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir + +* u8 net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and +* u9 net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and +* u10 net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u16 net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and +* u17 net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u18 net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and +* u20 net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and +* u21 net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u23 net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and +* u25 net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and +* u26 net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and +* u27 net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and +* u28 net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and +* u29 net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and +* u30 net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and +* u31 net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or +* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or +* u36 net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or +* u37 net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or +* u38 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or +* u39 net-_u38-pad3_ net-_u1-pad6_ d_inverter +* u4 net-_u1-pad10_ net-_u12-pad2_ d_inverter +* u7 net-_u12-pad2_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u11-pad1_ d_inverter +* u5 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad2_ d_inverter +* u6 net-_u11-pad2_ net-_u17-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9 +a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19 +a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23 +a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27 +a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28 +a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30 +a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31 +a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34 +a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36 +a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37 +a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38 +a32 net-_u38-pad3_ net-_u1-pad6_ u39 +a33 net-_u1-pad10_ net-_u12-pad2_ u4 +a34 net-_u12-pad2_ net-_u10-pad2_ u7 +a35 net-_u1-pad9_ net-_u11-pad1_ u2 +a36 net-_u11-pad1_ net-_u13-pad1_ u5 +a37 net-_u1-pad8_ net-_u11-pad2_ u3 +a38 net-_u11-pad2_ net-_u17-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch new file mode 100644 index 00000000..70c27f62 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch @@ -0,0 +1,904 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:HD74LS152-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 678A887C +P 11800 5150 +F 0 "U8" H 11800 5150 60 0000 C CNN +F 1 "d_and" H 11850 5250 60 0000 C CNN +F 2 "" H 11800 5150 60 0000 C CNN +F 3 "" H 11800 5150 60 0000 C CNN + 1 11800 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 678A889E +P 11800 5400 +F 0 "U9" H 11800 5400 60 0000 C CNN +F 1 "d_and" H 11850 5500 60 0000 C CNN +F 2 "" H 11800 5400 60 0000 C CNN +F 3 "" H 11800 5400 60 0000 C CNN + 1 11800 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 678A88F4 +P 11800 5850 +F 0 "U10" H 11800 5850 60 0000 C CNN +F 1 "d_and" H 11850 5950 60 0000 C CNN +F 2 "" H 11800 5850 60 0000 C CNN +F 3 "" H 11800 5850 60 0000 C CNN + 1 11800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 678A88FA +P 11800 6100 +F 0 "U11" H 11800 6100 60 0000 C CNN +F 1 "d_and" H 11850 6200 60 0000 C CNN +F 2 "" H 11800 6100 60 0000 C CNN +F 3 "" H 11800 6100 60 0000 C CNN + 1 11800 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 678A8C48 +P 11800 6600 +F 0 "U12" H 11800 6600 60 0000 C CNN +F 1 "d_and" H 11850 6700 60 0000 C CNN +F 2 "" H 11800 6600 60 0000 C CNN +F 3 "" H 11800 6600 60 0000 C CNN + 1 11800 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 678A8C4E +P 11800 6850 +F 0 "U13" H 11800 6850 60 0000 C CNN +F 1 "d_and" H 11850 6950 60 0000 C CNN +F 2 "" H 11800 6850 60 0000 C CNN +F 3 "" H 11800 6850 60 0000 C CNN + 1 11800 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 678A8C54 +P 11800 7300 +F 0 "U14" H 11800 7300 60 0000 C CNN +F 1 "d_and" H 11850 7400 60 0000 C CNN +F 2 "" H 11800 7300 60 0000 C CNN +F 3 "" H 11800 7300 60 0000 C CNN + 1 11800 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 678A8C5A +P 11800 7550 +F 0 "U15" H 11800 7550 60 0000 C CNN +F 1 "d_and" H 11850 7650 60 0000 C CNN +F 2 "" H 11800 7550 60 0000 C CNN +F 3 "" H 11800 7550 60 0000 C CNN + 1 11800 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 678A8D88 +P 11800 8000 +F 0 "U16" H 11800 8000 60 0000 C CNN +F 1 "d_and" H 11850 8100 60 0000 C CNN +F 2 "" H 11800 8000 60 0000 C CNN +F 3 "" H 11800 8000 60 0000 C CNN + 1 11800 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 678A8D8E +P 11800 8250 +F 0 "U17" H 11800 8250 60 0000 C CNN +F 1 "d_and" H 11850 8350 60 0000 C CNN +F 2 "" H 11800 8250 60 0000 C CNN +F 3 "" H 11800 8250 60 0000 C CNN + 1 11800 8250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 678A8D94 +P 11800 8700 +F 0 "U18" H 11800 8700 60 0000 C CNN +F 1 "d_and" H 11850 8800 60 0000 C CNN +F 2 "" H 11800 8700 60 0000 C CNN +F 3 "" H 11800 8700 60 0000 C CNN + 1 11800 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 678A8D9A +P 11800 8950 +F 0 "U19" H 11800 8950 60 0000 C CNN +F 1 "d_and" H 11850 9050 60 0000 C CNN +F 2 "" H 11800 8950 60 0000 C CNN +F 3 "" H 11800 8950 60 0000 C CNN + 1 11800 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 678A8DA0 +P 11800 9450 +F 0 "U20" H 11800 9450 60 0000 C CNN +F 1 "d_and" H 11850 9550 60 0000 C CNN +F 2 "" H 11800 9450 60 0000 C CNN +F 3 "" H 11800 9450 60 0000 C CNN + 1 11800 9450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 678A8DA6 +P 11800 9700 +F 0 "U21" H 11800 9700 60 0000 C CNN +F 1 "d_and" H 11850 9800 60 0000 C CNN +F 2 "" H 11800 9700 60 0000 C CNN +F 3 "" H 11800 9700 60 0000 C CNN + 1 11800 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 678A8DAC +P 11800 10150 +F 0 "U22" H 11800 10150 60 0000 C CNN +F 1 "d_and" H 11850 10250 60 0000 C CNN +F 2 "" H 11800 10150 60 0000 C CNN +F 3 "" H 11800 10150 60 0000 C CNN + 1 11800 10150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 678A8DB2 +P 11800 10400 +F 0 "U23" H 11800 10400 60 0000 C CNN +F 1 "d_and" H 11850 10500 60 0000 C CNN +F 2 "" H 11800 10400 60 0000 C CNN +F 3 "" H 11800 10400 60 0000 C CNN + 1 11800 10400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 678A8DCA +P 14800 5700 +F 0 "U32" H 14800 5700 60 0000 C CNN +F 1 "d_or" H 14800 5800 60 0000 C CNN +F 2 "" H 14800 5700 60 0000 C CNN +F 3 "" H 14800 5700 60 0000 C CNN + 1 14800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 678A8E8A +P 12850 5300 +F 0 "U24" H 12850 5300 60 0000 C CNN +F 1 "d_and" H 12900 5400 60 0000 C CNN +F 2 "" H 12850 5300 60 0000 C CNN +F 3 "" H 12850 5300 60 0000 C CNN + 1 12850 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 678A8FC4 +P 12850 6000 +F 0 "U25" H 12850 6000 60 0000 C CNN +F 1 "d_and" H 12900 6100 60 0000 C CNN +F 2 "" H 12850 6000 60 0000 C CNN +F 3 "" H 12850 6000 60 0000 C CNN + 1 12850 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 678A920D +P 12850 6750 +F 0 "U26" H 12850 6750 60 0000 C CNN +F 1 "d_and" H 12900 6850 60 0000 C CNN +F 2 "" H 12850 6750 60 0000 C CNN +F 3 "" H 12850 6750 60 0000 C CNN + 1 12850 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 678A94C5 +P 12850 7450 +F 0 "U27" H 12850 7450 60 0000 C CNN +F 1 "d_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12850 7450 60 0000 C CNN +F 3 "" H 12850 7450 60 0000 C CNN + 1 12850 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 678A94CB +P 12850 8200 +F 0 "U28" H 12850 8200 60 0000 C CNN +F 1 "d_and" H 12900 8300 60 0000 C CNN +F 2 "" H 12850 8200 60 0000 C CNN +F 3 "" H 12850 8200 60 0000 C CNN + 1 12850 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 678A98CF +P 12850 8850 +F 0 "U29" H 12850 8850 60 0000 C CNN +F 1 "d_and" H 12900 8950 60 0000 C CNN +F 2 "" H 12850 8850 60 0000 C CNN +F 3 "" H 12850 8850 60 0000 C CNN + 1 12850 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U30 +U 1 1 678A98D5 +P 12850 9550 +F 0 "U30" H 12850 9550 60 0000 C CNN +F 1 "d_and" H 12900 9650 60 0000 C CNN +F 2 "" H 12850 9550 60 0000 C CNN +F 3 "" H 12850 9550 60 0000 C CNN + 1 12850 9550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U31 +U 1 1 678A98DB +P 12850 10300 +F 0 "U31" H 12850 10300 60 0000 C CNN +F 1 "d_and" H 12900 10400 60 0000 C CNN +F 2 "" H 12850 10300 60 0000 C CNN +F 3 "" H 12850 10300 60 0000 C CNN + 1 12850 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 678A9B5E +P 14850 7100 +F 0 "U33" H 14850 7100 60 0000 C CNN +F 1 "d_or" H 14850 7200 60 0000 C CNN +F 2 "" H 14850 7100 60 0000 C CNN +F 3 "" H 14850 7100 60 0000 C CNN + 1 14850 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U35 +U 1 1 678A9BE6 +P 14900 8450 +F 0 "U35" H 14900 8450 60 0000 C CNN +F 1 "d_or" H 14900 8550 60 0000 C CNN +F 2 "" H 14900 8450 60 0000 C CNN +F 3 "" H 14900 8450 60 0000 C CNN + 1 14900 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U34 +U 1 1 678A9CC3 +P 14850 9750 +F 0 "U34" H 14850 9750 60 0000 C CNN +F 1 "d_or" H 14850 9850 60 0000 C CNN +F 2 "" H 14850 9750 60 0000 C CNN +F 3 "" H 14850 9750 60 0000 C CNN + 1 14850 9750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U36 +U 1 1 678A9D59 +P 16150 6650 +F 0 "U36" H 16150 6650 60 0000 C CNN +F 1 "d_or" H 16150 6750 60 0000 C CNN +F 2 "" H 16150 6650 60 0000 C CNN +F 3 "" H 16150 6650 60 0000 C CNN + 1 16150 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_or U37 +U 1 1 678A9DEC +P 16200 9200 +F 0 "U37" H 16200 9200 60 0000 C CNN +F 1 "d_or" H 16200 9300 60 0000 C CNN +F 2 "" H 16200 9200 60 0000 C CNN +F 3 "" H 16200 9200 60 0000 C CNN + 1 16200 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U38 +U 1 1 678A9E94 +P 17350 7850 +F 0 "U38" H 17350 7850 60 0000 C CNN +F 1 "d_or" H 17350 7950 60 0000 C CNN +F 2 "" H 17350 7850 60 0000 C CNN +F 3 "" H 17350 7850 60 0000 C CNN + 1 17350 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 678A9F5D +P 18300 7800 +F 0 "U39" H 18300 7700 60 0000 C CNN +F 1 "d_inverter" H 18300 7950 60 0000 C CNN +F 2 "" H 18350 7750 60 0000 C CNN +F 3 "" H 18350 7750 60 0000 C CNN + 1 18300 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 678AABC1 +P 6750 11250 +F 0 "U4" H 6750 11150 60 0000 C CNN +F 1 "d_inverter" H 6750 11400 60 0000 C CNN +F 2 "" H 6800 11200 60 0000 C CNN +F 3 "" H 6800 11200 60 0000 C CNN + 1 6750 11250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 678AACCC +P 8500 11250 +F 0 "U7" H 8500 11150 60 0000 C CNN +F 1 "d_inverter" H 8500 11400 60 0000 C CNN +F 2 "" H 8550 11200 60 0000 C CNN +F 3 "" H 8550 11200 60 0000 C CNN + 1 8500 11250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 678AADA6 +P 6700 11950 +F 0 "U2" H 6700 11850 60 0000 C CNN +F 1 "d_inverter" H 6700 12100 60 0000 C CNN +F 2 "" H 6750 11900 60 0000 C CNN +F 3 "" H 6750 11900 60 0000 C CNN + 1 6700 11950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 678AADAC +P 8450 11950 +F 0 "U5" H 8450 11850 60 0000 C CNN +F 1 "d_inverter" H 8450 12100 60 0000 C CNN +F 2 "" H 8500 11900 60 0000 C CNN +F 3 "" H 8500 11900 60 0000 C CNN + 1 8450 11950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 678AAE38 +P 6700 12700 +F 0 "U3" H 6700 12600 60 0000 C CNN +F 1 "d_inverter" H 6700 12850 60 0000 C CNN +F 2 "" H 6750 12650 60 0000 C CNN +F 3 "" H 6750 12650 60 0000 C CNN + 1 6700 12700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 678AAE3E +P 8450 12700 +F 0 "U6" H 8450 12600 60 0000 C CNN +F 1 "d_inverter" H 8450 12850 60 0000 C CNN +F 2 "" H 8500 12650 60 0000 C CNN +F 3 "" H 8500 12650 60 0000 C CNN + 1 8450 12700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7000 12700 8150 12700 +Wire Wire Line + 8150 11950 7000 11950 +Wire Wire Line + 7050 11250 8200 11250 +Wire Wire Line + 7900 11250 7900 10750 +Wire Wire Line + 7900 10750 10300 10750 +Wire Wire Line + 10300 10750 10300 5150 +Wire Wire Line + 10300 9450 11350 9450 +Connection ~ 7900 11250 +Wire Wire Line + 10300 8000 11350 8000 +Connection ~ 10300 9450 +Wire Wire Line + 10300 6600 11350 6600 +Connection ~ 10300 8000 +Wire Wire Line + 10300 5150 11350 5150 +Connection ~ 10300 6600 +Wire Wire Line + 10500 11250 8800 11250 +Wire Wire Line + 10500 5850 10500 11250 +Wire Wire Line + 10500 10150 11350 10150 +Wire Wire Line + 10500 8700 11350 8700 +Connection ~ 10500 10150 +Wire Wire Line + 10500 7300 11350 7300 +Connection ~ 10500 8700 +Wire Wire Line + 10500 5850 11350 5850 +Connection ~ 10500 7300 +Wire Wire Line + 7900 11550 7900 11950 +Connection ~ 7900 11950 +Wire Wire Line + 10650 11550 7900 11550 +Wire Wire Line + 10650 5300 10650 11550 +Wire Wire Line + 10650 8850 11350 8850 +Wire Wire Line + 10650 8150 11350 8150 +Connection ~ 10650 8850 +Wire Wire Line + 10650 6000 11350 6000 +Connection ~ 10650 8150 +Wire Wire Line + 10650 5300 11350 5300 +Connection ~ 10650 6000 +Wire Wire Line + 10800 11950 8750 11950 +Wire Wire Line + 10800 6750 10800 11950 +Wire Wire Line + 10800 10300 11350 10300 +Wire Wire Line + 10800 9600 11350 9600 +Connection ~ 10800 10300 +Wire Wire Line + 10800 7450 11350 7450 +Connection ~ 10800 9600 +Wire Wire Line + 10800 6750 11350 6750 +Connection ~ 10800 7450 +Wire Wire Line + 7900 12700 7900 12300 +Wire Wire Line + 7900 12300 10950 12300 +Wire Wire Line + 10950 12300 10950 5400 +Wire Wire Line + 10950 5400 11350 5400 +Connection ~ 7900 12700 +Wire Wire Line + 11350 6100 10950 6100 +Connection ~ 10950 6100 +Wire Wire Line + 11350 6850 10950 6850 +Connection ~ 10950 6850 +Wire Wire Line + 11350 7550 10950 7550 +Connection ~ 10950 7550 +Wire Wire Line + 11100 12700 8750 12700 +Wire Wire Line + 11100 8250 11100 12700 +Wire Wire Line + 11100 10400 11350 10400 +Wire Wire Line + 11100 9700 11350 9700 +Connection ~ 11100 10400 +Wire Wire Line + 11100 8950 11350 8950 +Connection ~ 11100 9700 +Wire Wire Line + 11100 8250 11350 8250 +Connection ~ 11100 8950 +Wire Wire Line + 12250 10350 12400 10350 +Wire Wire Line + 12400 10350 12400 10300 +Wire Wire Line + 12400 10200 12400 10100 +Wire Wire Line + 12400 10100 12250 10100 +Wire Wire Line + 12400 9550 12400 9650 +Wire Wire Line + 12400 9650 12250 9650 +Wire Wire Line + 12400 9450 12400 9400 +Wire Wire Line + 12400 9400 12250 9400 +Wire Wire Line + 12250 8900 12400 8900 +Wire Wire Line + 12400 8900 12400 8850 +Wire Wire Line + 12400 8750 12400 8650 +Wire Wire Line + 12400 8650 12250 8650 +Wire Wire Line + 12250 7950 12400 7950 +Wire Wire Line + 12400 7950 12400 8100 +Wire Wire Line + 12250 8200 12400 8200 +Wire Wire Line + 12250 7250 12400 7250 +Wire Wire Line + 12400 7250 12400 7350 +Wire Wire Line + 12400 7450 12400 7500 +Wire Wire Line + 12400 7500 12250 7500 +Wire Wire Line + 12250 5800 12400 5800 +Wire Wire Line + 12400 5800 12400 5900 +Wire Wire Line + 12400 6000 12400 6050 +Wire Wire Line + 12400 6050 12250 6050 +Wire Wire Line + 12250 6550 12400 6550 +Wire Wire Line + 12400 6550 12400 6650 +Wire Wire Line + 12400 6750 12400 6800 +Wire Wire Line + 12400 6800 12250 6800 +Wire Wire Line + 12250 5100 12400 5100 +Wire Wire Line + 12400 5100 12400 5200 +Wire Wire Line + 12400 5300 12400 5350 +Wire Wire Line + 12400 5350 12250 5350 +Wire Wire Line + 11350 10050 6600 10050 +Wire Wire Line + 6600 9350 11350 9350 +Wire Wire Line + 11350 8600 6750 8600 +Wire Wire Line + 11350 7900 6700 7900 +Wire Wire Line + 11350 7200 6700 7200 +Wire Wire Line + 11350 6500 6700 6500 +Wire Wire Line + 11350 5750 6700 5750 +Wire Wire Line + 11350 5050 6750 5050 +Wire Wire Line + 13300 6700 14200 6700 +Wire Wire Line + 14200 6700 14200 7000 +Wire Wire Line + 14200 7000 14400 7000 +Wire Wire Line + 14400 7100 14200 7100 +Wire Wire Line + 14200 7100 14200 7400 +Wire Wire Line + 14200 7400 13300 7400 +Wire Wire Line + 13300 8150 14200 8150 +Wire Wire Line + 14200 8150 14200 8350 +Wire Wire Line + 14200 8350 14450 8350 +Wire Wire Line + 14450 8450 14200 8450 +Wire Wire Line + 14200 8450 14200 8800 +Wire Wire Line + 14200 8800 13300 8800 +Wire Wire Line + 13300 9500 14050 9500 +Wire Wire Line + 14050 9500 14050 9650 +Wire Wire Line + 14050 9650 14400 9650 +Wire Wire Line + 14400 9750 14050 9750 +Wire Wire Line + 14050 9750 14050 10250 +Wire Wire Line + 14050 10250 13300 10250 +Wire Wire Line + 13300 5250 13700 5250 +Wire Wire Line + 13700 5250 13700 5600 +Wire Wire Line + 13700 5600 14350 5600 +Wire Wire Line + 14350 5700 13700 5700 +Wire Wire Line + 13700 5700 13700 5950 +Wire Wire Line + 13700 5950 13300 5950 +Wire Wire Line + 15250 5650 15450 5650 +Wire Wire Line + 15450 5650 15450 6550 +Wire Wire Line + 15450 6550 15700 6550 +Wire Wire Line + 15700 6650 15500 6650 +Wire Wire Line + 15500 6650 15500 7050 +Wire Wire Line + 15500 7050 15300 7050 +Wire Wire Line + 15350 8400 15550 8400 +Wire Wire Line + 15550 8400 15550 9100 +Wire Wire Line + 15550 9100 15750 9100 +Wire Wire Line + 15750 9200 15550 9200 +Wire Wire Line + 15550 9200 15550 9700 +Wire Wire Line + 15550 9700 15300 9700 +Wire Wire Line + 16600 6600 16800 6600 +Wire Wire Line + 16800 6600 16800 7750 +Wire Wire Line + 16800 7750 16900 7750 +Wire Wire Line + 16900 7850 16800 7850 +Wire Wire Line + 16800 7850 16800 9150 +Wire Wire Line + 16800 9150 16650 9150 +Wire Wire Line + 17800 7800 18000 7800 +Wire Wire Line + 18600 7800 18950 7800 +Wire Wire Line + 6450 11250 6100 11250 +Wire Wire Line + 6400 11950 6100 11950 +Wire Wire Line + 6400 12700 6100 12700 +$Comp +L PORT U1 +U 6 1 678BA160 +P 19200 7800 +F 0 "U1" H 19250 7900 30 0000 C CNN +F 1 "PORT" H 19200 7800 30 0000 C CNN +F 2 "" H 19200 7800 60 0000 C CNN +F 3 "" H 19200 7800 60 0000 C CNN + 6 19200 7800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 678BA3D2 +P 6500 5050 +F 0 "U1" H 6550 5150 30 0000 C CNN +F 1 "PORT" H 6500 5050 30 0000 C CNN +F 2 "" H 6500 5050 60 0000 C CNN +F 3 "" H 6500 5050 60 0000 C CNN + 5 6500 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 678BA4DF +P 6450 5750 +F 0 "U1" H 6500 5850 30 0000 C CNN +F 1 "PORT" H 6450 5750 30 0000 C CNN +F 2 "" H 6450 5750 60 0000 C CNN +F 3 "" H 6450 5750 60 0000 C CNN + 4 6450 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 678BA54C +P 6450 6500 +F 0 "U1" H 6500 6600 30 0000 C CNN +F 1 "PORT" H 6450 6500 30 0000 C CNN +F 2 "" H 6450 6500 60 0000 C CNN +F 3 "" H 6450 6500 60 0000 C CNN + 3 6450 6500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 678BA63F +P 6450 7200 +F 0 "U1" H 6500 7300 30 0000 C CNN +F 1 "PORT" H 6450 7200 30 0000 C CNN +F 2 "" H 6450 7200 60 0000 C CNN +F 3 "" H 6450 7200 60 0000 C CNN + 2 6450 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 678BA760 +P 6450 7900 +F 0 "U1" H 6500 8000 30 0000 C CNN +F 1 "PORT" H 6450 7900 30 0000 C CNN +F 2 "" H 6450 7900 60 0000 C CNN +F 3 "" H 6450 7900 60 0000 C CNN + 1 6450 7900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 678BAA39 +P 6500 8600 +F 0 "U1" H 6550 8700 30 0000 C CNN +F 1 "PORT" H 6500 8600 30 0000 C CNN +F 2 "" H 6500 8600 60 0000 C CNN +F 3 "" H 6500 8600 60 0000 C CNN + 13 6500 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 678BAAB4 +P 6350 9350 +F 0 "U1" H 6400 9450 30 0000 C CNN +F 1 "PORT" H 6350 9350 30 0000 C CNN +F 2 "" H 6350 9350 60 0000 C CNN +F 3 "" H 6350 9350 60 0000 C CNN + 12 6350 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 678BAB2F +P 6350 10050 +F 0 "U1" H 6400 10150 30 0000 C CNN +F 1 "PORT" H 6350 10050 30 0000 C CNN +F 2 "" H 6350 10050 60 0000 C CNN +F 3 "" H 6350 10050 60 0000 C CNN + 11 6350 10050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 678BAD20 +P 5850 11250 +F 0 "U1" H 5900 11350 30 0000 C CNN +F 1 "PORT" H 5850 11250 30 0000 C CNN +F 2 "" H 5850 11250 60 0000 C CNN +F 3 "" H 5850 11250 60 0000 C CNN + 10 5850 11250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 678BAD9B +P 5850 11950 +F 0 "U1" H 5900 12050 30 0000 C CNN +F 1 "PORT" H 5850 11950 30 0000 C CNN +F 2 "" H 5850 11950 60 0000 C CNN +F 3 "" H 5850 11950 60 0000 C CNN + 9 5850 11950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 678BB0C4 +P 5850 12700 +F 0 "U1" H 5900 12800 30 0000 C CNN +F 1 "PORT" H 5850 12700 30 0000 C CNN +F 2 "" H 5850 12700 60 0000 C CNN +F 3 "" H 5850 12700 60 0000 C CNN + 8 5850 12700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 678BB437 +P 13400 11500 +F 0 "U1" H 13450 11600 30 0000 C CNN +F 1 "PORT" H 13400 11500 30 0000 C CNN +F 2 "" H 13400 11500 60 0000 C CNN +F 3 "" H 13400 11500 60 0000 C CNN + 7 13400 11500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 678BB54B +P 13400 11750 +F 0 "U1" H 13450 11850 30 0000 C CNN +F 1 "PORT" H 13400 11750 30 0000 C CNN +F 2 "" H 13400 11750 60 0000 C CNN +F 3 "" H 13400 11750 60 0000 C CNN + 14 13400 11750 + 1 0 0 -1 +$EndComp +NoConn ~ 13650 11500 +NoConn ~ 13650 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub new file mode 100644 index 00000000..3604a713 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub @@ -0,0 +1,158 @@ +* Subcircuit HD74LS152 +.subckt HD74LS152 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir +* u8 net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and +* u9 net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and +* u10 net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u16 net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and +* u17 net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u18 net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and +* u20 net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and +* u21 net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u23 net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and +* u25 net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and +* u26 net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and +* u27 net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and +* u28 net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and +* u29 net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and +* u30 net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and +* u31 net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or +* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or +* u36 net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or +* u37 net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or +* u38 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or +* u39 net-_u38-pad3_ net-_u1-pad6_ d_inverter +* u4 net-_u1-pad10_ net-_u12-pad2_ d_inverter +* u7 net-_u12-pad2_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u11-pad1_ d_inverter +* u5 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad2_ d_inverter +* u6 net-_u11-pad2_ net-_u17-pad2_ d_inverter +a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9 +a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19 +a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23 +a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27 +a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28 +a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30 +a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31 +a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34 +a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36 +a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37 +a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38 +a32 net-_u38-pad3_ net-_u1-pad6_ u39 +a33 net-_u1-pad10_ net-_u12-pad2_ u4 +a34 net-_u12-pad2_ net-_u10-pad2_ u7 +a35 net-_u1-pad9_ net-_u11-pad1_ u2 +a36 net-_u11-pad1_ net-_u13-pad1_ u5 +a37 net-_u1-pad8_ net-_u11-pad2_ u3 +a38 net-_u11-pad2_ net-_u17-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends HD74LS152
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml new file mode 100644 index 00000000..044e3a73 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u21><u22 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /></u22><u23 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /></u23><u32 name="type">d_or<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /></u32><u24 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /></u24><u25 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /></u25><u26 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u26><u27 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /></u27><u28 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /></u28><u29 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u29><u30 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /></u30><u31 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /></u33><u35 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /></u35><u34 name="type">d_or<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /></u34><u36 name="type">d_or<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /></u36><u37 name="type">d_or<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u37><u38 name="type">d_or<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u39><u4 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /></u4><u7 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /></u7><u2 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u2><u5 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u5><u3 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/analysis b/library/SubcircuitLibrary/HD74LS152/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/SN54180-cache.lib b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib new file mode 100644 index 00000000..27b0f7f2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir b/library/SubcircuitLibrary/SN54180/SN54180.cir new file mode 100644 index 00000000..89146f7f --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54180\SN54180.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/07/25 23:03:34 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U2-Pad3_ d_xnor +U3 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U3-Pad3_ d_xnor +U4 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad3_ d_xnor +U5 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_xnor +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_xnor +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_xor +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_xor +U9 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad3_ d_and +U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad5_ d_nor +U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir.out b/library/SubcircuitLibrary/SN54180/SN54180.cir.out new file mode 100644 index 00000000..18993e8b --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.cir.out @@ -0,0 +1,68 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir + +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54180/SN54180.pro b/library/SubcircuitLibrary/SN54180/SN54180.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sch b/library/SubcircuitLibrary/SN54180/SN54180.sch new file mode 100644 index 00000000..1534f8b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sch @@ -0,0 +1,499 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN54180-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xnor U2 +U 1 1 677290B0 +P 6050 7300 +F 0 "U2" H 6050 7300 60 0000 C CNN +F 1 "d_xnor" H 6100 7400 47 0000 C CNN +F 2 "" H 6050 7300 60 0000 C CNN +F 3 "" H 6050 7300 60 0000 C CNN + 1 6050 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U3 +U 1 1 677290E7 +P 6050 7750 +F 0 "U3" H 6050 7750 60 0000 C CNN +F 1 "d_xnor" H 6100 7850 47 0000 C CNN +F 2 "" H 6050 7750 60 0000 C CNN +F 3 "" H 6050 7750 60 0000 C CNN + 1 6050 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U4 +U 1 1 67729137 +P 6050 8200 +F 0 "U4" H 6050 8200 60 0000 C CNN +F 1 "d_xnor" H 6100 8300 47 0000 C CNN +F 2 "" H 6050 8200 60 0000 C CNN +F 3 "" H 6050 8200 60 0000 C CNN + 1 6050 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U5 +U 1 1 6772913D +P 6050 8650 +F 0 "U5" H 6050 8650 60 0000 C CNN +F 1 "d_xnor" H 6100 8750 47 0000 C CNN +F 2 "" H 6050 8650 60 0000 C CNN +F 3 "" H 6050 8650 60 0000 C CNN + 1 6050 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U8 +U 1 1 6772915D +P 8600 7950 +F 0 "U8" H 8600 7950 60 0000 C CNN +F 1 "d_xnor" H 8650 8050 47 0000 C CNN +F 2 "" H 8600 7950 60 0000 C CNN +F 3 "" H 8600 7950 60 0000 C CNN + 1 8600 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 677291A8 +P 7350 7500 +F 0 "U6" H 7350 7500 60 0000 C CNN +F 1 "d_xor" H 7400 7600 47 0000 C CNN +F 2 "" H 7350 7500 60 0000 C CNN +F 3 "" H 7350 7500 60 0000 C CNN + 1 7350 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 677291CD +P 7350 8400 +F 0 "U7" H 7350 8400 60 0000 C CNN +F 1 "d_xor" H 7400 8500 47 0000 C CNN +F 2 "" H 7350 8400 60 0000 C CNN +F 3 "" H 7350 8400 60 0000 C CNN + 1 7350 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67729482 +P 9800 7900 +F 0 "U9" H 9800 7800 60 0000 C CNN +F 1 "d_inverter" H 9800 8050 60 0000 C CNN +F 2 "" H 9850 7850 60 0000 C CNN +F 3 "" H 9850 7850 60 0000 C CNN + 1 9800 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 67729715 +P 11450 7250 +F 0 "U10" H 11450 7250 60 0000 C CNN +F 1 "d_and" H 11500 7350 60 0000 C CNN +F 2 "" H 11450 7250 60 0000 C CNN +F 3 "" H 11450 7250 60 0000 C CNN + 1 11450 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6772978A +P 11450 7750 +F 0 "U11" H 11450 7750 60 0000 C CNN +F 1 "d_and" H 11500 7850 60 0000 C CNN +F 2 "" H 11450 7750 60 0000 C CNN +F 3 "" H 11450 7750 60 0000 C CNN + 1 11450 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 677297EE +P 11450 8200 +F 0 "U12" H 11450 8200 60 0000 C CNN +F 1 "d_and" H 11500 8300 60 0000 C CNN +F 2 "" H 11450 8200 60 0000 C CNN +F 3 "" H 11450 8200 60 0000 C CNN + 1 11450 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 677297F4 +P 11450 8700 +F 0 "U13" H 11450 8700 60 0000 C CNN +F 1 "d_and" H 11500 8800 60 0000 C CNN +F 2 "" H 11450 8700 60 0000 C CNN +F 3 "" H 11450 8700 60 0000 C CNN + 1 11450 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 67729834 +P 13400 7550 +F 0 "U14" H 13400 7550 60 0000 C CNN +F 1 "d_nor" H 13450 7650 60 0000 C CNN +F 2 "" H 13400 7550 60 0000 C CNN +F 3 "" H 13400 7550 60 0000 C CNN + 1 13400 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 677299D9 +P 13400 8450 +F 0 "U15" H 13400 8450 60 0000 C CNN +F 1 "d_nor" H 13450 8550 60 0000 C CNN +F 2 "" H 13400 8450 60 0000 C CNN +F 3 "" H 13400 8450 60 0000 C CNN + 1 13400 8450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 7200 4850 7200 +Wire Wire Line + 5600 7300 4850 7300 +Wire Wire Line + 5600 7650 4850 7650 +Wire Wire Line + 5600 7750 4850 7750 +Wire Wire Line + 5600 8100 4850 8100 +Wire Wire Line + 5600 8200 4850 8200 +Wire Wire Line + 5600 8550 4850 8550 +Wire Wire Line + 5600 8650 4850 8650 +Wire Wire Line + 6500 7250 6750 7250 +Wire Wire Line + 6750 7250 6750 7400 +Wire Wire Line + 6750 7400 6900 7400 +Wire Wire Line + 6900 7500 6750 7500 +Wire Wire Line + 6750 7500 6750 7700 +Wire Wire Line + 6750 7700 6500 7700 +Wire Wire Line + 6500 8150 6700 8150 +Wire Wire Line + 6700 8150 6700 8300 +Wire Wire Line + 6700 8300 6900 8300 +Wire Wire Line + 6900 8400 6700 8400 +Wire Wire Line + 6700 8400 6700 8600 +Wire Wire Line + 6700 8600 6500 8600 +Wire Wire Line + 7800 7450 8000 7450 +Wire Wire Line + 8000 7450 8000 7850 +Wire Wire Line + 8000 7850 8150 7850 +Wire Wire Line + 8150 7950 8000 7950 +Wire Wire Line + 8000 7950 8000 8350 +Wire Wire Line + 8000 8350 7800 8350 +Wire Wire Line + 9050 7900 9500 7900 +Wire Wire Line + 11000 7150 9300 7150 +Wire Wire Line + 9300 7150 9300 8200 +Connection ~ 9300 7900 +Wire Wire Line + 9300 8200 11000 8200 +Wire Wire Line + 10350 7250 11000 7250 +Wire Wire Line + 10350 7250 10350 9350 +Wire Wire Line + 10350 8700 11000 8700 +Wire Wire Line + 11000 7650 10550 7650 +Wire Wire Line + 10550 7650 10550 8600 +Wire Wire Line + 10550 8600 11000 8600 +Wire Wire Line + 11000 7750 10800 7750 +Wire Wire Line + 10800 7750 10800 9550 +Wire Wire Line + 10800 8100 11000 8100 +Wire Wire Line + 10100 7900 10550 7900 +Connection ~ 10550 7900 +Wire Wire Line + 10350 9350 4850 9350 +Connection ~ 10350 8700 +Wire Wire Line + 10800 9550 4850 9550 +Connection ~ 10800 8100 +Wire Wire Line + 11900 7200 12500 7200 +Wire Wire Line + 12500 7200 12500 7450 +Wire Wire Line + 12500 7450 12950 7450 +Wire Wire Line + 12500 7550 12950 7550 +Wire Wire Line + 12500 7550 12500 7700 +Wire Wire Line + 12500 7700 11900 7700 +Wire Wire Line + 11900 8150 12500 8150 +Wire Wire Line + 12500 8150 12500 8350 +Wire Wire Line + 12500 8350 12950 8350 +Wire Wire Line + 12950 8450 12500 8450 +Wire Wire Line + 12500 8450 12500 8650 +Wire Wire Line + 12500 8650 11900 8650 +Wire Wire Line + 13850 7500 14550 7500 +Wire Wire Line + 13850 8400 14550 8400 +$Comp +L PORT U1 +U 1 1 677964E3 +P 4600 8550 +F 0 "U1" H 4650 8650 30 0000 C CNN +F 1 "PORT" H 4600 8550 30 0000 C CNN +F 2 "" H 4600 8550 60 0000 C CNN +F 3 "" H 4600 8550 60 0000 C CNN + 1 4600 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 677965B0 +P 4600 8750 +F 0 "U1" H 4650 8850 30 0000 C CNN +F 1 "PORT" H 4600 8750 30 0000 C CNN +F 2 "" H 4600 8750 60 0000 C CNN +F 3 "" H 4600 8750 60 0000 C CNN + 2 4600 8750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 8650 4850 8750 +$Comp +L PORT U1 +U 3 1 6779664F +P 4600 9550 +F 0 "U1" H 4650 9650 30 0000 C CNN +F 1 "PORT" H 4600 9550 30 0000 C CNN +F 2 "" H 4600 9550 60 0000 C CNN +F 3 "" H 4600 9550 60 0000 C CNN + 3 4600 9550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67796694 +P 4600 9350 +F 0 "U1" H 4650 9450 30 0000 C CNN +F 1 "PORT" H 4600 9350 30 0000 C CNN +F 2 "" H 4600 9350 60 0000 C CNN +F 3 "" H 4600 9350 60 0000 C CNN + 4 4600 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 677975B7 +P 14800 7500 +F 0 "U1" H 14850 7600 30 0000 C CNN +F 1 "PORT" H 14800 7500 30 0000 C CNN +F 2 "" H 14800 7500 60 0000 C CNN +F 3 "" H 14800 7500 60 0000 C CNN + 5 14800 7500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6779764E +P 14800 8400 +F 0 "U1" H 14850 8500 30 0000 C CNN +F 1 "PORT" H 14800 8400 30 0000 C CNN +F 2 "" H 14800 8400 60 0000 C CNN +F 3 "" H 14800 8400 60 0000 C CNN + 6 14800 8400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67798A6F +P 4600 7200 +F 0 "U1" H 4650 7300 30 0000 C CNN +F 1 "PORT" H 4600 7200 30 0000 C CNN +F 2 "" H 4600 7200 60 0000 C CNN +F 3 "" H 4600 7200 60 0000 C CNN + 8 4600 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67798ABE +P 4600 7400 +F 0 "U1" H 4650 7500 30 0000 C CNN +F 1 "PORT" H 4600 7400 30 0000 C CNN +F 2 "" H 4600 7400 60 0000 C CNN +F 3 "" H 4600 7400 60 0000 C CNN + 9 4600 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67798B09 +P 4200 7550 +F 0 "U1" H 4250 7650 30 0000 C CNN +F 1 "PORT" H 4200 7550 30 0000 C CNN +F 2 "" H 4200 7550 60 0000 C CNN +F 3 "" H 4200 7550 60 0000 C CNN + 10 4200 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67798B62 +P 4200 7800 +F 0 "U1" H 4250 7900 30 0000 C CNN +F 1 "PORT" H 4200 7800 30 0000 C CNN +F 2 "" H 4200 7800 60 0000 C CNN +F 3 "" H 4200 7800 60 0000 C CNN + 11 4200 7800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67798BAD +P 4450 8000 +F 0 "U1" H 4500 8100 30 0000 C CNN +F 1 "PORT" H 4450 8000 30 0000 C CNN +F 2 "" H 4450 8000 60 0000 C CNN +F 3 "" H 4450 8000 60 0000 C CNN + 12 4450 8000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67798BFE +P 4450 8250 +F 0 "U1" H 4500 8350 30 0000 C CNN +F 1 "PORT" H 4450 8250 30 0000 C CNN +F 2 "" H 4450 8250 60 0000 C CNN +F 3 "" H 4450 8250 60 0000 C CNN + 13 4450 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 7550 4850 7550 +Wire Wire Line + 4850 7550 4850 7650 +Wire Wire Line + 4450 7800 4850 7800 +Wire Wire Line + 4850 7800 4850 7750 +Wire Wire Line + 4850 7300 4850 7400 +Wire Wire Line + 4700 8000 4850 8000 +Wire Wire Line + 4850 8000 4850 8100 +Wire Wire Line + 4700 8250 4850 8250 +Wire Wire Line + 4850 8250 4850 8200 +$Comp +L PORT U1 +U 7 1 677A3419 +P 5650 10400 +F 0 "U1" H 5700 10500 30 0000 C CNN +F 1 "PORT" H 5650 10400 30 0000 C CNN +F 2 "" H 5650 10400 60 0000 C CNN +F 3 "" H 5650 10400 60 0000 C CNN + 7 5650 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 677A353F +P 5650 10650 +F 0 "U1" H 5700 10750 30 0000 C CNN +F 1 "PORT" H 5650 10650 30 0000 C CNN +F 2 "" H 5650 10650 60 0000 C CNN +F 3 "" H 5650 10650 60 0000 C CNN + 14 5650 10650 + 1 0 0 -1 +$EndComp +NoConn ~ 5900 10400 +NoConn ~ 5900 10650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sub b/library/SubcircuitLibrary/SN54180/SN54180.sub new file mode 100644 index 00000000..34693793 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sub @@ -0,0 +1,62 @@ +* Subcircuit SN54180 +.subckt SN54180 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54180
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml new file mode 100644 index 00000000..a66526b3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u5><u8 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u8><u6 name="type">d_xor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/analysis b/library/SubcircuitLibrary/SN54180/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib b/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro b/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro new file mode 100644 index 00000000..81bd9ad4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro @@ -0,0 +1,70 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Subckt +LibName23=transistors +LibName24=conn +LibName25=eSim_Plot +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User + diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib b/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib b/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib b/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib new file mode 100644 index 00000000..3e8d471c --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir new file mode 100644 index 00000000..f00d5bd3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54LS183\SN54LS183.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/10/25 22:53:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad2_ Net-_U18-Pad2_ Net-_U20-Pad2_ d_and +U4 Net-_U2-Pad1_ Net-_U18-Pad2_ Net-_U28-Pad2_ d_and +U5 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U16-Pad1_ d_and +U16 Net-_U16-Pad1_ Net-_U1-Pad1_ Net-_U16-Pad3_ d_and +U6 Net-_U2-Pad1_ Net-_U1-Pad3_ Net-_U17-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U1-Pad1_ Net-_U17-Pad3_ d_and +U7 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U18-Pad1_ d_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U19-Pad1_ d_and +U19 Net-_U19-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +U9 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U25-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad11_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U21 Net-_U12-Pad3_ Net-_U1-Pad13_ Net-_U21-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U13-Pad3_ d_and +U22 Net-_U13-Pad3_ Net-_U1-Pad13_ Net-_U22-Pad3_ d_and +U25 Net-_U25-Pad1_ Net-_U10-Pad3_ Net-_U25-Pad3_ d_nor +U31 Net-_U25-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad10_ d_nor +U29 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U29-Pad3_ d_nor +U30 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U30-Pad3_ d_nor +U33 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad8_ d_nor +U14 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U14-Pad3_ d_and +U23 Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_and +U15 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U15-Pad3_ d_and +U24 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_and +U1 Net-_U1-Pad1_ ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ ? Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U35 Net-_U1-Pad4_ Net-_U2-Pad1_ d_inverter +U34 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U36 Net-_U1-Pad1_ Net-_U18-Pad2_ d_inverter +U38 Net-_U1-Pad11_ Net-_U11-Pad1_ d_inverter +U37 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U39 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U20 Net-_U2-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or +U28 Net-_U20-Pad3_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_or +U40 Net-_U28-Pad3_ Net-_U1-Pad5_ d_inverter +U41 Net-_U32-Pad3_ Net-_U1-Pad6_ d_inverter +U26 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_or +U27 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_or +U32 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U32-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out new file mode 100644 index 00000000..198578d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out @@ -0,0 +1,172 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54ls183\sn54ls183.cir + +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad2_ net-_u18-pad2_ net-_u20-pad2_ d_and +* u4 net-_u2-pad1_ net-_u18-pad2_ net-_u28-pad2_ d_and +* u5 net-_u1-pad4_ net-_u2-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u1-pad1_ net-_u16-pad3_ d_and +* u6 net-_u2-pad1_ net-_u1-pad3_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u1-pad1_ net-_u17-pad3_ d_and +* u7 net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad4_ net-_u1-pad3_ net-_u19-pad1_ d_and +* u19 net-_u19-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad1_ net-_u25-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad11_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u21 net-_u12-pad3_ net-_u1-pad13_ net-_u21-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad12_ net-_u13-pad3_ d_and +* u22 net-_u13-pad3_ net-_u1-pad13_ net-_u22-pad3_ d_and +* u25 net-_u25-pad1_ net-_u10-pad3_ net-_u25-pad3_ d_nor +* u31 net-_u25-pad3_ net-_u11-pad3_ net-_u1-pad10_ d_nor +* u29 net-_u21-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nor +* u33 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad8_ d_nor +* u14 net-_u11-pad1_ net-_u10-pad1_ net-_u14-pad3_ d_and +* u23 net-_u14-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_and +* u15 net-_u1-pad11_ net-_u1-pad12_ net-_u15-pad3_ d_and +* u24 net-_u15-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_and +* u1 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u35 net-_u1-pad4_ net-_u2-pad1_ d_inverter +* u34 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u36 net-_u1-pad1_ net-_u18-pad2_ d_inverter +* u38 net-_u1-pad11_ net-_u11-pad1_ d_inverter +* u37 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u39 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u20 net-_u2-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u28 net-_u20-pad3_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u40 net-_u28-pad3_ net-_u1-pad5_ d_inverter +* u41 net-_u32-pad3_ net-_u1-pad6_ d_inverter +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_or +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_or +* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_or +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad2_ net-_u18-pad2_ ] net-_u20-pad2_ u3 +a3 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u28-pad2_ u4 +a4 [net-_u1-pad4_ net-_u2-pad2_ ] net-_u16-pad1_ u5 +a5 [net-_u16-pad1_ net-_u1-pad1_ ] net-_u16-pad3_ u16 +a6 [net-_u2-pad1_ net-_u1-pad3_ ] net-_u17-pad1_ u6 +a7 [net-_u17-pad1_ net-_u1-pad1_ ] net-_u17-pad3_ u17 +a8 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u18-pad1_ u7 +a9 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u19-pad1_ u8 +a11 [net-_u19-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a12 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u25-pad1_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a16 [net-_u12-pad3_ net-_u1-pad13_ ] net-_u21-pad3_ u21 +a17 [net-_u11-pad1_ net-_u1-pad12_ ] net-_u13-pad3_ u13 +a18 [net-_u13-pad3_ net-_u1-pad13_ ] net-_u22-pad3_ u22 +a19 [net-_u25-pad1_ net-_u10-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u25-pad3_ net-_u11-pad3_ ] net-_u1-pad10_ u31 +a21 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad8_ u33 +a24 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +a25 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u15-pad3_ u15 +a27 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a28 net-_u1-pad4_ net-_u2-pad1_ u35 +a29 net-_u1-pad3_ net-_u2-pad2_ u34 +a30 net-_u1-pad1_ net-_u18-pad2_ u36 +a31 net-_u1-pad11_ net-_u11-pad1_ u38 +a32 net-_u1-pad12_ net-_u10-pad1_ u37 +a33 net-_u1-pad13_ net-_u10-pad2_ u39 +a34 [net-_u2-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a35 [net-_u20-pad3_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a36 net-_u28-pad3_ net-_u1-pad5_ u40 +a37 net-_u32-pad3_ net-_u1-pad6_ u41 +a38 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a39 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a40 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro b/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch new file mode 100644 index 00000000..b972d850 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch @@ -0,0 +1,993 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN54LS183-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 67812973 +P 12300 3250 +F 0 "U2" H 12300 3250 60 0000 C CNN +F 1 "d_and" H 12350 3350 60 0000 C CNN +F 2 "" H 12300 3250 60 0000 C CNN +F 3 "" H 12300 3250 60 0000 C CNN + 1 12300 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 67812A00 +P 12300 3650 +F 0 "U3" H 12300 3650 60 0000 C CNN +F 1 "d_and" H 12350 3750 60 0000 C CNN +F 2 "" H 12300 3650 60 0000 C CNN +F 3 "" H 12300 3650 60 0000 C CNN + 1 12300 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 67812A24 +P 12300 4000 +F 0 "U4" H 12300 4000 60 0000 C CNN +F 1 "d_and" H 12350 4100 60 0000 C CNN +F 2 "" H 12300 4000 60 0000 C CNN +F 3 "" H 12300 4000 60 0000 C CNN + 1 12300 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67812AC5 +P 12300 4600 +F 0 "U5" H 12300 4600 60 0000 C CNN +F 1 "d_and" H 12350 4700 60 0000 C CNN +F 2 "" H 12300 4600 60 0000 C CNN +F 3 "" H 12300 4600 60 0000 C CNN + 1 12300 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 67812ACB +P 13250 4850 +F 0 "U16" H 13250 4850 60 0000 C CNN +F 1 "d_and" H 13300 4950 60 0000 C CNN +F 2 "" H 13250 4850 60 0000 C CNN +F 3 "" H 13250 4850 60 0000 C CNN + 1 13250 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67812AD1 +P 12300 5350 +F 0 "U6" H 12300 5350 60 0000 C CNN +F 1 "d_and" H 12350 5450 60 0000 C CNN +F 2 "" H 12300 5350 60 0000 C CNN +F 3 "" H 12300 5350 60 0000 C CNN + 1 12300 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 67812AE3 +P 13250 5600 +F 0 "U17" H 13250 5600 60 0000 C CNN +F 1 "d_and" H 13300 5700 60 0000 C CNN +F 2 "" H 13250 5600 60 0000 C CNN +F 3 "" H 13250 5600 60 0000 C CNN + 1 13250 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67813298 +P 12300 6050 +F 0 "U7" H 12300 6050 60 0000 C CNN +F 1 "d_and" H 12350 6150 60 0000 C CNN +F 2 "" H 12300 6050 60 0000 C CNN +F 3 "" H 12300 6050 60 0000 C CNN + 1 12300 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 6781329E +P 13250 6300 +F 0 "U18" H 13250 6300 60 0000 C CNN +F 1 "d_and" H 13300 6400 60 0000 C CNN +F 2 "" H 13250 6300 60 0000 C CNN +F 3 "" H 13250 6300 60 0000 C CNN + 1 13250 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 678132A4 +P 12300 6800 +F 0 "U8" H 12300 6800 60 0000 C CNN +F 1 "d_and" H 12350 6900 60 0000 C CNN +F 2 "" H 12300 6800 60 0000 C CNN +F 3 "" H 12300 6800 60 0000 C CNN + 1 12300 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 678132AA +P 13250 7050 +F 0 "U19" H 13250 7050 60 0000 C CNN +F 1 "d_and" H 13300 7150 60 0000 C CNN +F 2 "" H 13250 7050 60 0000 C CNN +F 3 "" H 13250 7050 60 0000 C CNN + 1 13250 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 678150DC +P 12750 8100 +F 0 "U9" H 12750 8100 60 0000 C CNN +F 1 "d_and" H 12800 8200 60 0000 C CNN +F 2 "" H 12750 8100 60 0000 C CNN +F 3 "" H 12750 8100 60 0000 C CNN + 1 12750 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 678150E2 +P 12750 8500 +F 0 "U10" H 12750 8500 60 0000 C CNN +F 1 "d_and" H 12800 8600 60 0000 C CNN +F 2 "" H 12750 8500 60 0000 C CNN +F 3 "" H 12750 8500 60 0000 C CNN + 1 12750 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 678150E8 +P 12750 8850 +F 0 "U11" H 12750 8850 60 0000 C CNN +F 1 "d_and" H 12800 8950 60 0000 C CNN +F 2 "" H 12750 8850 60 0000 C CNN +F 3 "" H 12750 8850 60 0000 C CNN + 1 12750 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 678150EE +P 12750 9450 +F 0 "U12" H 12750 9450 60 0000 C CNN +F 1 "d_and" H 12800 9550 60 0000 C CNN +F 2 "" H 12750 9450 60 0000 C CNN +F 3 "" H 12750 9450 60 0000 C CNN + 1 12750 9450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 678150F4 +P 13700 9700 +F 0 "U21" H 13700 9700 60 0000 C CNN +F 1 "d_and" H 13750 9800 60 0000 C CNN +F 2 "" H 13700 9700 60 0000 C CNN +F 3 "" H 13700 9700 60 0000 C CNN + 1 13700 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 678150FA +P 12750 10200 +F 0 "U13" H 12750 10200 60 0000 C CNN +F 1 "d_and" H 12800 10300 60 0000 C CNN +F 2 "" H 12750 10200 60 0000 C CNN +F 3 "" H 12750 10200 60 0000 C CNN + 1 12750 10200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 67815100 +P 13700 10450 +F 0 "U22" H 13700 10450 60 0000 C CNN +F 1 "d_and" H 13750 10550 60 0000 C CNN +F 2 "" H 13700 10450 60 0000 C CNN +F 3 "" H 13700 10450 60 0000 C CNN + 1 13700 10450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U25 +U 1 1 67815106 +P 14150 8300 +F 0 "U25" H 14150 8300 60 0000 C CNN +F 1 "d_nor" H 14200 8400 60 0000 C CNN +F 2 "" H 14150 8300 60 0000 C CNN +F 3 "" H 14150 8300 60 0000 C CNN + 1 14150 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U31 +U 1 1 6781510C +P 15400 8600 +F 0 "U31" H 15400 8600 60 0000 C CNN +F 1 "d_nor" H 15450 8700 60 0000 C CNN +F 2 "" H 15400 8600 60 0000 C CNN +F 3 "" H 15400 8600 60 0000 C CNN + 1 15400 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U29 +U 1 1 67815112 +P 15150 10350 +F 0 "U29" H 15150 10350 60 0000 C CNN +F 1 "d_nor" H 15200 10450 60 0000 C CNN +F 2 "" H 15150 10350 60 0000 C CNN +F 3 "" H 15150 10350 60 0000 C CNN + 1 15150 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U30 +U 1 1 67815118 +P 15150 11100 +F 0 "U30" H 15150 11100 60 0000 C CNN +F 1 "d_nor" H 15200 11200 60 0000 C CNN +F 2 "" H 15150 11100 60 0000 C CNN +F 3 "" H 15150 11100 60 0000 C CNN + 1 15150 11100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U33 +U 1 1 6781511E +P 16350 10700 +F 0 "U33" H 16350 10700 60 0000 C CNN +F 1 "d_nor" H 16400 10800 60 0000 C CNN +F 2 "" H 16350 10700 60 0000 C CNN +F 3 "" H 16350 10700 60 0000 C CNN + 1 16350 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 67815146 +P 12750 10900 +F 0 "U14" H 12750 10900 60 0000 C CNN +F 1 "d_and" H 12800 11000 60 0000 C CNN +F 2 "" H 12750 10900 60 0000 C CNN +F 3 "" H 12750 10900 60 0000 C CNN + 1 12750 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 6781514C +P 13700 11150 +F 0 "U23" H 13700 11150 60 0000 C CNN +F 1 "d_and" H 13750 11250 60 0000 C CNN +F 2 "" H 13700 11150 60 0000 C CNN +F 3 "" H 13700 11150 60 0000 C CNN + 1 13700 11150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 67815152 +P 12750 11650 +F 0 "U15" H 12750 11650 60 0000 C CNN +F 1 "d_and" H 12800 11750 60 0000 C CNN +F 2 "" H 12750 11650 60 0000 C CNN +F 3 "" H 12750 11650 60 0000 C CNN + 1 12750 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 67815158 +P 13700 11900 +F 0 "U24" H 13700 11900 60 0000 C CNN +F 1 "d_and" H 13750 12000 60 0000 C CNN +F 2 "" H 13700 11900 60 0000 C CNN +F 3 "" H 13700 11900 60 0000 C CNN + 1 13700 11900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67815B00 +P 5250 5450 +F 0 "U1" H 5300 5550 30 0000 C CNN +F 1 "PORT" H 5250 5450 30 0000 C CNN +F 2 "" H 5250 5450 60 0000 C CNN +F 3 "" H 5250 5450 60 0000 C CNN + 1 5250 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67815B8E +P 5250 4800 +F 0 "U1" H 5300 4900 30 0000 C CNN +F 1 "PORT" H 5250 4800 30 0000 C CNN +F 2 "" H 5250 4800 60 0000 C CNN +F 3 "" H 5250 4800 60 0000 C CNN + 3 5250 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67815BF3 +P 5250 4100 +F 0 "U1" H 5300 4200 30 0000 C CNN +F 1 "PORT" H 5250 4100 30 0000 C CNN +F 2 "" H 5250 4100 60 0000 C CNN +F 3 "" H 5250 4100 60 0000 C CNN + 4 5250 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67815E4A +P 7900 13650 +F 0 "U1" H 7950 13750 30 0000 C CNN +F 1 "PORT" H 7900 13650 30 0000 C CNN +F 2 "" H 7900 13650 60 0000 C CNN +F 3 "" H 7900 13650 60 0000 C CNN + 2 7900 13650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 678161D1 +P 18000 3700 +F 0 "U1" H 18050 3800 30 0000 C CNN +F 1 "PORT" H 18000 3700 30 0000 C CNN +F 2 "" H 18000 3700 60 0000 C CNN +F 3 "" H 18000 3700 60 0000 C CNN + 5 18000 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 678163CB +P 18000 5800 +F 0 "U1" H 18050 5900 30 0000 C CNN +F 1 "PORT" H 18000 5800 30 0000 C CNN +F 2 "" H 18000 5800 60 0000 C CNN +F 3 "" H 18000 5800 60 0000 C CNN + 6 18000 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 678167B0 +P 7900 13900 +F 0 "U1" H 7950 14000 30 0000 C CNN +F 1 "PORT" H 7900 13900 30 0000 C CNN +F 2 "" H 7900 13900 60 0000 C CNN +F 3 "" H 7900 13900 60 0000 C CNN + 7 7900 13900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 67816B24 +P 18400 10650 +F 0 "U1" H 18450 10750 30 0000 C CNN +F 1 "PORT" H 18400 10650 30 0000 C CNN +F 2 "" H 18400 10650 60 0000 C CNN +F 3 "" H 18400 10650 60 0000 C CNN + 8 18400 10650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 67816D6B +P 7900 14150 +F 0 "U1" H 7950 14250 30 0000 C CNN +F 1 "PORT" H 7900 14150 30 0000 C CNN +F 2 "" H 7900 14150 60 0000 C CNN +F 3 "" H 7900 14150 60 0000 C CNN + 9 7900 14150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 678170DA +P 18350 8550 +F 0 "U1" H 18400 8650 30 0000 C CNN +F 1 "PORT" H 18350 8550 30 0000 C CNN +F 2 "" H 18350 8550 60 0000 C CNN +F 3 "" H 18350 8550 60 0000 C CNN + 10 18350 8550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 67817605 +P 5350 8950 +F 0 "U1" H 5400 9050 30 0000 C CNN +F 1 "PORT" H 5350 8950 30 0000 C CNN +F 2 "" H 5350 8950 60 0000 C CNN +F 3 "" H 5350 8950 60 0000 C CNN + 11 5350 8950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6781767E +P 5500 9650 +F 0 "U1" H 5550 9750 30 0000 C CNN +F 1 "PORT" H 5500 9650 30 0000 C CNN +F 2 "" H 5500 9650 60 0000 C CNN +F 3 "" H 5500 9650 60 0000 C CNN + 12 5500 9650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 678176FB +P 5550 10300 +F 0 "U1" H 5600 10400 30 0000 C CNN +F 1 "PORT" H 5550 10300 30 0000 C CNN +F 2 "" H 5550 10300 60 0000 C CNN +F 3 "" H 5550 10300 60 0000 C CNN + 13 5550 10300 + 1 0 0 -1 +$EndComp +NoConn ~ 8150 13650 +NoConn ~ 8150 13900 +NoConn ~ 8150 14150 +$Comp +L PORT U1 +U 14 1 6781A929 +P 7900 14400 +F 0 "U1" H 7950 14500 30 0000 C CNN +F 1 "PORT" H 7900 14400 30 0000 C CNN +F 2 "" H 7900 14400 60 0000 C CNN +F 3 "" H 7900 14400 60 0000 C CNN + 14 7900 14400 + 1 0 0 -1 +$EndComp +NoConn ~ 8150 14400 +Wire Wire Line + 12750 3200 13250 3200 +Wire Wire Line + 13250 3200 13250 3350 +Wire Wire Line + 13250 3450 13250 3600 +Wire Wire Line + 13250 3600 12750 3600 +Wire Wire Line + 14150 3400 14350 3400 +Wire Wire Line + 14350 3400 14350 3650 +Wire Wire Line + 14350 3650 14500 3650 +Wire Wire Line + 14500 3750 14350 3750 +Wire Wire Line + 14350 3750 14350 3950 +Wire Wire Line + 14350 3950 12750 3950 +Wire Wire Line + 15150 6200 15300 6200 +Wire Wire Line + 15300 6200 15300 5850 +Wire Wire Line + 15300 5850 15450 5850 +Wire Wire Line + 15450 5750 15300 5750 +Wire Wire Line + 15300 5750 15300 5450 +Wire Wire Line + 15300 5450 15150 5450 +Wire Wire Line + 12750 4550 12800 4550 +Wire Wire Line + 12800 4550 12800 4750 +Wire Wire Line + 12750 5300 12800 5300 +Wire Wire Line + 12800 5300 12800 5500 +Wire Wire Line + 12750 6000 12750 6200 +Wire Wire Line + 12750 6200 12800 6200 +Wire Wire Line + 12750 6750 12800 6750 +Wire Wire Line + 12800 6750 12800 6950 +Wire Wire Line + 13700 4800 14100 4800 +Wire Wire Line + 14100 4800 14100 5400 +Wire Wire Line + 14100 5400 14250 5400 +Wire Wire Line + 14250 5500 14100 5500 +Wire Wire Line + 14100 5500 14100 5550 +Wire Wire Line + 14100 5550 13700 5550 +Wire Wire Line + 13700 6250 14050 6250 +Wire Wire Line + 14050 6250 14050 6150 +Wire Wire Line + 14050 6150 14250 6150 +Wire Wire Line + 14250 6250 14150 6250 +Wire Wire Line + 14150 6250 14150 7000 +Wire Wire Line + 14150 7000 13700 7000 +Wire Wire Line + 11850 3150 9750 3150 +Wire Wire Line + 9750 3150 9750 5950 +Wire Wire Line + 7800 4100 9750 4100 +Wire Wire Line + 11850 3900 9750 3900 +Connection ~ 9750 3900 +Wire Wire Line + 9750 5250 11850 5250 +Connection ~ 9750 4100 +Wire Wire Line + 9750 5950 11850 5950 +Connection ~ 9750 5250 +Wire Wire Line + 11850 3250 11450 3250 +Wire Wire Line + 11450 3250 11450 6050 +Wire Wire Line + 11450 3550 11850 3550 +Wire Wire Line + 7750 4800 11450 4800 +Connection ~ 11450 3550 +Wire Wire Line + 11850 4600 11450 4600 +Connection ~ 11450 4600 +Wire Wire Line + 11450 6050 11850 6050 +Connection ~ 11450 4800 +Wire Wire Line + 11850 3650 11650 3650 +Wire Wire Line + 11650 3650 11650 7050 +Wire Wire Line + 11650 4000 11850 4000 +Wire Wire Line + 7800 5450 11650 5450 +Connection ~ 11650 4000 +Wire Wire Line + 11650 7050 12800 7050 +Connection ~ 11650 5450 +Wire Wire Line + 5500 4100 7200 4100 +Wire Wire Line + 6300 4100 6300 4350 +Wire Wire Line + 6300 4350 10800 4350 +Wire Wire Line + 10800 4350 10800 6700 +Wire Wire Line + 10800 4500 11850 4500 +Connection ~ 6300 4100 +Wire Wire Line + 10800 6700 11850 6700 +Connection ~ 10800 4500 +Wire Wire Line + 5500 4800 7150 4800 +Wire Wire Line + 6300 4800 6300 5100 +Wire Wire Line + 6300 5100 11000 5100 +Wire Wire Line + 11000 5100 11000 6800 +Wire Wire Line + 11000 5350 11850 5350 +Connection ~ 6300 4800 +Wire Wire Line + 11000 6800 11850 6800 +Connection ~ 11000 5350 +Wire Wire Line + 5500 5450 7200 5450 +Wire Wire Line + 6300 5450 6300 5800 +Wire Wire Line + 6300 5800 12050 5800 +Wire Wire Line + 12050 5800 12050 5600 +Wire Wire Line + 12050 5600 12800 5600 +Connection ~ 6300 5450 +Wire Wire Line + 12800 4850 11800 4850 +Wire Wire Line + 11800 4850 11800 4950 +Wire Wire Line + 11800 4950 10200 4950 +Wire Wire Line + 10200 4950 10200 5800 +Connection ~ 10200 5800 +Wire Wire Line + 12800 6300 11650 6300 +Connection ~ 11650 6300 +Wire Wire Line + 13200 8050 13700 8050 +Wire Wire Line + 13700 8050 13700 8200 +Wire Wire Line + 13700 8300 13700 8450 +Wire Wire Line + 13700 8450 13200 8450 +Wire Wire Line + 14600 8250 14800 8250 +Wire Wire Line + 14800 8250 14800 8500 +Wire Wire Line + 14800 8500 14950 8500 +Wire Wire Line + 14950 8600 14800 8600 +Wire Wire Line + 14800 8600 14800 8800 +Wire Wire Line + 14800 8800 13200 8800 +Wire Wire Line + 15600 11050 15750 11050 +Wire Wire Line + 15750 11050 15750 10700 +Wire Wire Line + 15750 10700 15900 10700 +Wire Wire Line + 15900 10600 15750 10600 +Wire Wire Line + 15750 10600 15750 10300 +Wire Wire Line + 15750 10300 15600 10300 +Wire Wire Line + 13200 9400 13250 9400 +Wire Wire Line + 13250 9400 13250 9600 +Wire Wire Line + 13200 10150 13250 10150 +Wire Wire Line + 13250 10150 13250 10350 +Wire Wire Line + 13200 10850 13200 11050 +Wire Wire Line + 13200 11050 13250 11050 +Wire Wire Line + 13200 11600 13250 11600 +Wire Wire Line + 13250 11600 13250 11800 +Wire Wire Line + 14150 9650 14550 9650 +Wire Wire Line + 14550 9650 14550 10250 +Wire Wire Line + 14550 10250 14700 10250 +Wire Wire Line + 14700 10350 14550 10350 +Wire Wire Line + 14550 10350 14550 10400 +Wire Wire Line + 14550 10400 14150 10400 +Wire Wire Line + 14150 11100 14500 11100 +Wire Wire Line + 14500 11100 14500 11000 +Wire Wire Line + 14500 11000 14700 11000 +Wire Wire Line + 14700 11100 14600 11100 +Wire Wire Line + 14600 11100 14600 11850 +Wire Wire Line + 14600 11850 14150 11850 +Wire Wire Line + 12300 8000 10200 8000 +Wire Wire Line + 10200 8000 10200 10800 +Wire Wire Line + 8250 8950 10200 8950 +Wire Wire Line + 12300 8750 10200 8750 +Connection ~ 10200 8750 +Wire Wire Line + 10200 10100 12300 10100 +Connection ~ 10200 8950 +Wire Wire Line + 10200 10800 12300 10800 +Connection ~ 10200 10100 +Wire Wire Line + 12300 8100 11900 8100 +Wire Wire Line + 11900 8100 11900 10900 +Wire Wire Line + 11900 8400 12300 8400 +Wire Wire Line + 8200 9650 11900 9650 +Connection ~ 11900 8400 +Wire Wire Line + 12300 9450 11900 9450 +Connection ~ 11900 9450 +Wire Wire Line + 11900 10900 12300 10900 +Connection ~ 11900 9650 +Wire Wire Line + 12300 8500 12100 8500 +Wire Wire Line + 12100 8500 12100 11900 +Wire Wire Line + 12100 8850 12300 8850 +Wire Wire Line + 8250 10300 12100 10300 +Connection ~ 12100 8850 +Wire Wire Line + 12100 11900 13250 11900 +Connection ~ 12100 10300 +Wire Wire Line + 5600 8950 7650 8950 +Wire Wire Line + 6750 9200 11250 9200 +Wire Wire Line + 11250 9200 11250 11550 +Wire Wire Line + 11250 9350 12300 9350 +Wire Wire Line + 11250 11550 12300 11550 +Connection ~ 11250 9350 +Wire Wire Line + 5750 9650 7600 9650 +Wire Wire Line + 6750 9950 11450 9950 +Wire Wire Line + 11450 9950 11450 11650 +Wire Wire Line + 11450 10200 12300 10200 +Wire Wire Line + 11450 11650 12300 11650 +Connection ~ 11450 10200 +Wire Wire Line + 5800 10300 7650 10300 +Wire Wire Line + 6750 10650 12500 10650 +Wire Wire Line + 12500 10650 12500 10450 +Wire Wire Line + 12500 10450 13250 10450 +Wire Wire Line + 13250 9700 12250 9700 +Wire Wire Line + 12250 9700 12250 9800 +Wire Wire Line + 12250 9800 10650 9800 +Wire Wire Line + 10650 9800 10650 10650 +Connection ~ 10650 10650 +Wire Wire Line + 13250 11150 12100 11150 +Connection ~ 12100 11150 +Wire Wire Line + 15850 8550 18100 8550 +Wire Wire Line + 16800 10650 18150 10650 +Wire Wire Line + 6750 10650 6750 10300 +Connection ~ 6750 10300 +Wire Wire Line + 6750 9950 6750 9650 +Connection ~ 6750 9650 +Wire Wire Line + 6750 9200 6750 8950 +Connection ~ 6750 8950 +$Comp +L d_inverter U35 +U 1 1 67815B9E +P 7500 4100 +F 0 "U35" H 7500 4000 60 0000 C CNN +F 1 "d_inverter" H 7500 4250 60 0000 C CNN +F 2 "" H 7550 4050 60 0000 C CNN +F 3 "" H 7550 4050 60 0000 C CNN + 1 7500 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 67815C4E +P 7450 4800 +F 0 "U34" H 7450 4700 60 0000 C CNN +F 1 "d_inverter" H 7450 4950 60 0000 C CNN +F 2 "" H 7500 4750 60 0000 C CNN +F 3 "" H 7500 4750 60 0000 C CNN + 1 7450 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 67815CF8 +P 7500 5450 +F 0 "U36" H 7500 5350 60 0000 C CNN +F 1 "d_inverter" H 7500 5600 60 0000 C CNN +F 2 "" H 7550 5400 60 0000 C CNN +F 3 "" H 7550 5400 60 0000 C CNN + 1 7500 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U38 +U 1 1 6781606F +P 7950 8950 +F 0 "U38" H 7950 8850 60 0000 C CNN +F 1 "d_inverter" H 7950 9100 60 0000 C CNN +F 2 "" H 8000 8900 60 0000 C CNN +F 3 "" H 8000 8900 60 0000 C CNN + 1 7950 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 6781613E +P 7900 9650 +F 0 "U37" H 7900 9550 60 0000 C CNN +F 1 "d_inverter" H 7900 9800 60 0000 C CNN +F 2 "" H 7950 9600 60 0000 C CNN +F 3 "" H 7950 9600 60 0000 C CNN + 1 7900 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 678161F7 +P 7950 10300 +F 0 "U39" H 7950 10200 60 0000 C CNN +F 1 "d_inverter" H 7950 10450 60 0000 C CNN +F 2 "" H 8000 10250 60 0000 C CNN +F 3 "" H 8000 10250 60 0000 C CNN + 1 7950 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67817C3D +P 13700 3450 +F 0 "U20" H 13700 3450 60 0000 C CNN +F 1 "d_or" H 13700 3550 60 0000 C CNN +F 2 "" H 13700 3450 60 0000 C CNN +F 3 "" H 13700 3450 60 0000 C CNN + 1 13700 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 67817CC0 +P 14950 3750 +F 0 "U28" H 14950 3750 60 0000 C CNN +F 1 "d_or" H 14950 3850 60 0000 C CNN +F 2 "" H 14950 3750 60 0000 C CNN +F 3 "" H 14950 3750 60 0000 C CNN + 1 14950 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U40 +U 1 1 67817DB5 +P 16000 3700 +F 0 "U40" H 16000 3600 60 0000 C CNN +F 1 "d_inverter" H 16000 3850 60 0000 C CNN +F 2 "" H 16050 3650 60 0000 C CNN +F 3 "" H 16050 3650 60 0000 C CNN + 1 16000 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U41 +U 1 1 67817F5D +P 16850 5800 +F 0 "U41" H 16850 5700 60 0000 C CNN +F 1 "d_inverter" H 16850 5950 60 0000 C CNN +F 2 "" H 16900 5750 60 0000 C CNN +F 3 "" H 16900 5750 60 0000 C CNN + 1 16850 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U26 +U 1 1 67818050 +P 14700 5500 +F 0 "U26" H 14700 5500 60 0000 C CNN +F 1 "d_or" H 14700 5600 60 0000 C CNN +F 2 "" H 14700 5500 60 0000 C CNN +F 3 "" H 14700 5500 60 0000 C CNN + 1 14700 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U27 +U 1 1 678180E7 +P 14700 6250 +F 0 "U27" H 14700 6250 60 0000 C CNN +F 1 "d_or" H 14700 6350 60 0000 C CNN +F 2 "" H 14700 6250 60 0000 C CNN +F 3 "" H 14700 6250 60 0000 C CNN + 1 14700 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 67818172 +P 15900 5850 +F 0 "U32" H 15900 5850 60 0000 C CNN +F 1 "d_or" H 15900 5950 60 0000 C CNN +F 2 "" H 15900 5850 60 0000 C CNN +F 3 "" H 15900 5850 60 0000 C CNN + 1 15900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16350 5800 16550 5800 +Wire Wire Line + 17150 5800 17750 5800 +Wire Wire Line + 15700 3700 15400 3700 +Wire Wire Line + 16300 3700 17750 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub new file mode 100644 index 00000000..713804f7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub @@ -0,0 +1,166 @@ +* Subcircuit SN54LS183 +.subckt SN54LS183 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54ls183\sn54ls183.cir +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad2_ net-_u18-pad2_ net-_u20-pad2_ d_and +* u4 net-_u2-pad1_ net-_u18-pad2_ net-_u28-pad2_ d_and +* u5 net-_u1-pad4_ net-_u2-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u1-pad1_ net-_u16-pad3_ d_and +* u6 net-_u2-pad1_ net-_u1-pad3_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u1-pad1_ net-_u17-pad3_ d_and +* u7 net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad4_ net-_u1-pad3_ net-_u19-pad1_ d_and +* u19 net-_u19-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad1_ net-_u25-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad11_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u21 net-_u12-pad3_ net-_u1-pad13_ net-_u21-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad12_ net-_u13-pad3_ d_and +* u22 net-_u13-pad3_ net-_u1-pad13_ net-_u22-pad3_ d_and +* u25 net-_u25-pad1_ net-_u10-pad3_ net-_u25-pad3_ d_nor +* u31 net-_u25-pad3_ net-_u11-pad3_ net-_u1-pad10_ d_nor +* u29 net-_u21-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nor +* u33 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad8_ d_nor +* u14 net-_u11-pad1_ net-_u10-pad1_ net-_u14-pad3_ d_and +* u23 net-_u14-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_and +* u15 net-_u1-pad11_ net-_u1-pad12_ net-_u15-pad3_ d_and +* u24 net-_u15-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_and +* u35 net-_u1-pad4_ net-_u2-pad1_ d_inverter +* u34 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u36 net-_u1-pad1_ net-_u18-pad2_ d_inverter +* u38 net-_u1-pad11_ net-_u11-pad1_ d_inverter +* u37 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u39 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u20 net-_u2-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u28 net-_u20-pad3_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u40 net-_u28-pad3_ net-_u1-pad5_ d_inverter +* u41 net-_u32-pad3_ net-_u1-pad6_ d_inverter +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_or +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_or +* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_or +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad2_ net-_u18-pad2_ ] net-_u20-pad2_ u3 +a3 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u28-pad2_ u4 +a4 [net-_u1-pad4_ net-_u2-pad2_ ] net-_u16-pad1_ u5 +a5 [net-_u16-pad1_ net-_u1-pad1_ ] net-_u16-pad3_ u16 +a6 [net-_u2-pad1_ net-_u1-pad3_ ] net-_u17-pad1_ u6 +a7 [net-_u17-pad1_ net-_u1-pad1_ ] net-_u17-pad3_ u17 +a8 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u18-pad1_ u7 +a9 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u19-pad1_ u8 +a11 [net-_u19-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a12 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u25-pad1_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a16 [net-_u12-pad3_ net-_u1-pad13_ ] net-_u21-pad3_ u21 +a17 [net-_u11-pad1_ net-_u1-pad12_ ] net-_u13-pad3_ u13 +a18 [net-_u13-pad3_ net-_u1-pad13_ ] net-_u22-pad3_ u22 +a19 [net-_u25-pad1_ net-_u10-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u25-pad3_ net-_u11-pad3_ ] net-_u1-pad10_ u31 +a21 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad8_ u33 +a24 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +a25 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u15-pad3_ u15 +a27 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a28 net-_u1-pad4_ net-_u2-pad1_ u35 +a29 net-_u1-pad3_ net-_u2-pad2_ u34 +a30 net-_u1-pad1_ net-_u18-pad2_ u36 +a31 net-_u1-pad11_ net-_u11-pad1_ u38 +a32 net-_u1-pad12_ net-_u10-pad1_ u37 +a33 net-_u1-pad13_ net-_u10-pad2_ u39 +a34 [net-_u2-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a35 [net-_u20-pad3_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a36 net-_u28-pad3_ net-_u1-pad5_ u40 +a37 net-_u32-pad3_ net-_u1-pad6_ u41 +a38 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a39 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a40 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54LS183
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml b/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml new file mode 100644 index 00000000..ce7d687a --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u16 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u16><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u17 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u17><u20 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u20><u28 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u26 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u26><u27 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u27><u32 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u32><u7 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u7><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u8><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u9 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u12><u21 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u22><u25 name="type">d_nor<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u25><u31 name="type">d_nor<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u31><u29 name="type">d_nor<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u29><u30 name="type">d_nor<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u30><u33 name="type">d_nor<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u14 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u14><u23 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u23><u15 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u15><u24 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u24><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34><u36 name="type">d_inverter<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u36><u38 name="type">d_inverter<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u38><u37 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u37><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u20 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u20><u28 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u28><u40 name="type">d_inverter<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u40><u41 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u41><u26 name="type">d_or<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u26><u27 name="type">d_or<field115 name="Enter Fall Delay (default=1.0e-9)" /><field116 name="Enter Input Load (default=1.0e-12)" /><field117 name="Enter Rise Delay (default=1.0e-9)" /></u27><u32 name="type">d_or<field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /></u32></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/analysis b/library/SubcircuitLibrary/SN54LS183/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and-cache.lib b/library/SubcircuitLibrary/SN74351/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir b/library/SubcircuitLibrary/SN74351/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir.out b/library/SubcircuitLibrary/SN74351/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.pro b/library/SubcircuitLibrary/SN74351/3_and.pro new file mode 100644 index 00000000..da3e199e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74351/3_and.sch b/library/SubcircuitLibrary/SN74351/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/3_and.sub b/library/SubcircuitLibrary/SN74351/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and-cache.lib b/library/SubcircuitLibrary/SN74351/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and-rescue.lib b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir b/library/SubcircuitLibrary/SN74351/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir.out b/library/SubcircuitLibrary/SN74351/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.pro b/library/SubcircuitLibrary/SN74351/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/5_and.sch b/library/SubcircuitLibrary/SN74351/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/5_and.sub b/library/SubcircuitLibrary/SN74351/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351-cache.lib b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib new file mode 100644 index 00000000..212e1ab7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir b/library/SubcircuitLibrary/SN74351/SN74351.cir new file mode 100644 index 00000000..f13d0354 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN74351\SN74351.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 22:36:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad6_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad1_ 5_and +X2 Net-_U1-Pad7_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad2_ 5_and +X3 Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad1_ 5_and +X4 Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad2_ 5_and +X5 Net-_U1-Pad14_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad1_ 5_and +X6 Net-_U1-Pad13_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad2_ 5_and +X7 Net-_U1-Pad12_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad1_ 5_and +X8 Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad2_ 5_and +X9 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad11_ Net-_U8-Pad1_ 5_and +X10 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U1-Pad12_ Net-_U8-Pad2_ 5_and +X11 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad13_ Net-_U10-Pad1_ 5_and +X12 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U10-Pad2_ 5_and +X13 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad15_ Net-_U12-Pad1_ 5_and +X14 Net-_U20-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad16_ Net-_U12-Pad2_ 5_and +X15 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad17_ Net-_U13-Pad1_ 5_and +X16 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad18_ Net-_U13-Pad2_ 5_and +U5 Net-_U1-Pad2_ Net-_U20-Pad1_ d_inverter +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad4_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad5_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad1_ d_and +U21 Net-_U20-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad19_ d_and +U18 Net-_U14-Pad3_ Net-_U16-Pad3_ Net-_U18-Pad3_ d_or +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U16-Pad1_ d_or +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U14-Pad2_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U14-Pad1_ d_or +U19 Net-_U15-Pad3_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_or +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U15-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U22 Net-_U18-Pad3_ Net-_U20-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U21-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir.out b/library/SubcircuitLibrary/SN74351/SN74351.cir.out new file mode 100644 index 00000000..07b597bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir.out @@ -0,0 +1,117 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir + +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.pro b/library/SubcircuitLibrary/SN74351/SN74351.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sch b/library/SubcircuitLibrary/SN74351/SN74351.sch new file mode 100644 index 00000000..1d50e5b0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sch @@ -0,0 +1,1192 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN74351-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 6795B96A +P 13150 2950 +F 0 "X1" H 13200 2850 60 0000 C CNN +F 1 "5_and" H 13250 3100 60 0000 C CNN +F 2 "" H 13150 2950 60 0000 C CNN +F 3 "" H 13150 2950 60 0000 C CNN + 1 13150 2950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X2 +U 1 1 6795BA47 +P 13150 3650 +F 0 "X2" H 13200 3550 60 0000 C CNN +F 1 "5_and" H 13250 3800 60 0000 C CNN +F 2 "" H 13150 3650 60 0000 C CNN +F 3 "" H 13150 3650 60 0000 C CNN + 1 13150 3650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X3 +U 1 1 6795BAAC +P 13150 4350 +F 0 "X3" H 13200 4250 60 0000 C CNN +F 1 "5_and" H 13250 4500 60 0000 C CNN +F 2 "" H 13150 4350 60 0000 C CNN +F 3 "" H 13150 4350 60 0000 C CNN + 1 13150 4350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 6795BAB2 +P 13150 5050 +F 0 "X4" H 13200 4950 60 0000 C CNN +F 1 "5_and" H 13250 5200 60 0000 C CNN +F 2 "" H 13150 5050 60 0000 C CNN +F 3 "" H 13150 5050 60 0000 C CNN + 1 13150 5050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 6795BB3C +P 13150 5750 +F 0 "X5" H 13200 5650 60 0000 C CNN +F 1 "5_and" H 13250 5900 60 0000 C CNN +F 2 "" H 13150 5750 60 0000 C CNN +F 3 "" H 13150 5750 60 0000 C CNN + 1 13150 5750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 6795BB42 +P 13150 6450 +F 0 "X6" H 13200 6350 60 0000 C CNN +F 1 "5_and" H 13250 6600 60 0000 C CNN +F 2 "" H 13150 6450 60 0000 C CNN +F 3 "" H 13150 6450 60 0000 C CNN + 1 13150 6450 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 6795BB48 +P 13150 7150 +F 0 "X7" H 13200 7050 60 0000 C CNN +F 1 "5_and" H 13250 7300 60 0000 C CNN +F 2 "" H 13150 7150 60 0000 C CNN +F 3 "" H 13150 7150 60 0000 C CNN + 1 13150 7150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 6795BB4E +P 13150 7850 +F 0 "X8" H 13200 7750 60 0000 C CNN +F 1 "5_and" H 13250 8000 60 0000 C CNN +F 2 "" H 13150 7850 60 0000 C CNN +F 3 "" H 13150 7850 60 0000 C CNN + 1 13150 7850 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 6795C4A6 +P 13200 9650 +F 0 "X9" H 13250 9550 60 0000 C CNN +F 1 "5_and" H 13300 9800 60 0000 C CNN +F 2 "" H 13200 9650 60 0000 C CNN +F 3 "" H 13200 9650 60 0000 C CNN + 1 13200 9650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 6795C4AC +P 13200 10350 +F 0 "X10" H 13250 10250 60 0000 C CNN +F 1 "5_and" H 13300 10500 60 0000 C CNN +F 2 "" H 13200 10350 60 0000 C CNN +F 3 "" H 13200 10350 60 0000 C CNN + 1 13200 10350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 6795C4B2 +P 13200 11050 +F 0 "X11" H 13250 10950 60 0000 C CNN +F 1 "5_and" H 13300 11200 60 0000 C CNN +F 2 "" H 13200 11050 60 0000 C CNN +F 3 "" H 13200 11050 60 0000 C CNN + 1 13200 11050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X12 +U 1 1 6795C4B8 +P 13200 11750 +F 0 "X12" H 13250 11650 60 0000 C CNN +F 1 "5_and" H 13300 11900 60 0000 C CNN +F 2 "" H 13200 11750 60 0000 C CNN +F 3 "" H 13200 11750 60 0000 C CNN + 1 13200 11750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 6795C4BE +P 13200 12450 +F 0 "X13" H 13250 12350 60 0000 C CNN +F 1 "5_and" H 13300 12600 60 0000 C CNN +F 2 "" H 13200 12450 60 0000 C CNN +F 3 "" H 13200 12450 60 0000 C CNN + 1 13200 12450 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X14 +U 1 1 6795C4C4 +P 13200 13150 +F 0 "X14" H 13250 13050 60 0000 C CNN +F 1 "5_and" H 13300 13300 60 0000 C CNN +F 2 "" H 13200 13150 60 0000 C CNN +F 3 "" H 13200 13150 60 0000 C CNN + 1 13200 13150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X15 +U 1 1 6795C4CA +P 13200 13850 +F 0 "X15" H 13250 13750 60 0000 C CNN +F 1 "5_and" H 13300 14000 60 0000 C CNN +F 2 "" H 13200 13850 60 0000 C CNN +F 3 "" H 13200 13850 60 0000 C CNN + 1 13200 13850 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X16 +U 1 1 6795C4D0 +P 13200 14550 +F 0 "X16" H 13250 14450 60 0000 C CNN +F 1 "5_and" H 13300 14700 60 0000 C CNN +F 2 "" H 13200 14550 60 0000 C CNN +F 3 "" H 13200 14550 60 0000 C CNN + 1 13200 14550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6795C520 +P 6700 1600 +F 0 "U5" H 6700 1500 60 0000 C CNN +F 1 "d_inverter" H 6700 1750 60 0000 C CNN +F 2 "" H 6750 1550 60 0000 C CNN +F 3 "" H 6750 1550 60 0000 C CNN + 1 6700 1600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12700 2750 5400 2750 +Wire Wire Line + 12700 3450 5400 3450 +Wire Wire Line + 12700 4150 5400 4150 +Wire Wire Line + 12700 4850 5450 4850 +Wire Wire Line + 12700 5550 5500 5550 +Wire Wire Line + 12700 6250 5450 6250 +Wire Wire Line + 12700 6950 5450 6950 +Wire Wire Line + 12700 7650 5450 7650 +Wire Wire Line + 7000 1600 17650 1600 +Wire Wire Line + 12500 1600 12500 14350 +Wire Wire Line + 12500 3150 12700 3150 +Wire Wire Line + 12500 3850 12700 3850 +Connection ~ 12500 3150 +Wire Wire Line + 12500 4550 12700 4550 +Connection ~ 12500 3850 +Wire Wire Line + 12500 5250 12700 5250 +Connection ~ 12500 4550 +Wire Wire Line + 12500 5950 12700 5950 +Connection ~ 12500 5250 +Wire Wire Line + 12500 6650 12700 6650 +Connection ~ 12500 5950 +Wire Wire Line + 12500 7350 12700 7350 +Connection ~ 12500 6650 +Wire Wire Line + 12500 8050 12700 8050 +Connection ~ 12500 7350 +Wire Wire Line + 12500 9450 12750 9450 +Connection ~ 12500 8050 +Wire Wire Line + 12500 10150 12750 10150 +Connection ~ 12500 9450 +Wire Wire Line + 12500 10850 12750 10850 +Connection ~ 12500 10150 +Wire Wire Line + 12500 11550 12750 11550 +Connection ~ 12500 10850 +Wire Wire Line + 12500 12250 12750 12250 +Connection ~ 12500 11550 +Wire Wire Line + 12500 12950 12750 12950 +Connection ~ 12500 12250 +Wire Wire Line + 12500 13650 12750 13650 +Connection ~ 12500 12950 +Wire Wire Line + 12500 14350 12750 14350 +Connection ~ 12500 13650 +$Comp +L d_inverter U2 +U 1 1 6795F60D +P 4850 8550 +F 0 "U2" H 4850 8450 60 0000 C CNN +F 1 "d_inverter" H 4850 8700 60 0000 C CNN +F 2 "" H 4900 8500 60 0000 C CNN +F 3 "" H 4900 8500 60 0000 C CNN + 1 4850 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6795F674 +P 4850 9000 +F 0 "U3" H 4850 8900 60 0000 C CNN +F 1 "d_inverter" H 4850 9150 60 0000 C CNN +F 2 "" H 4900 8950 60 0000 C CNN +F 3 "" H 4900 8950 60 0000 C CNN + 1 4850 9000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6795F6CF +P 4850 9450 +F 0 "U4" H 4850 9350 60 0000 C CNN +F 1 "d_inverter" H 4850 9600 60 0000 C CNN +F 2 "" H 4900 9400 60 0000 C CNN +F 3 "" H 4900 9400 60 0000 C CNN + 1 4850 9450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 8550 3700 8550 +Wire Wire Line + 4550 9000 3700 9000 +Wire Wire Line + 4550 9450 3700 9450 +Wire Wire Line + 4400 8550 4400 8750 +Wire Wire Line + 4400 8750 9350 8750 +Connection ~ 4400 8550 +Wire Wire Line + 4400 9000 4400 9200 +Wire Wire Line + 4400 9200 9800 9200 +Connection ~ 4400 9000 +Wire Wire Line + 4400 9450 4400 9650 +Wire Wire Line + 4400 9650 8900 9650 +Connection ~ 4400 9450 +Wire Wire Line + 7900 7650 7900 9850 +Wire Wire Line + 7900 9850 12750 9850 +Connection ~ 7900 7650 +Wire Wire Line + 12750 10550 7750 10550 +Wire Wire Line + 7750 10550 7750 6950 +Connection ~ 7750 6950 +Wire Wire Line + 12750 11250 7600 11250 +Wire Wire Line + 7600 11250 7600 6250 +Connection ~ 7600 6250 +Wire Wire Line + 12750 11950 7450 11950 +Wire Wire Line + 7450 11950 7450 5550 +Connection ~ 7450 5550 +Wire Wire Line + 9200 8550 5150 8550 +Wire Wire Line + 9200 2850 9200 14550 +Wire Wire Line + 9200 7050 12700 7050 +Wire Wire Line + 9200 5650 12700 5650 +Connection ~ 9200 7050 +Wire Wire Line + 9200 4250 12700 4250 +Connection ~ 9200 5650 +Wire Wire Line + 9200 2850 12700 2850 +Connection ~ 9200 4250 +Wire Wire Line + 9200 10450 12750 10450 +Connection ~ 9200 8550 +Wire Wire Line + 9200 11850 12750 11850 +Connection ~ 9200 10450 +Wire Wire Line + 9200 13050 12750 13050 +Connection ~ 9200 11850 +Connection ~ 9200 13050 +Wire Wire Line + 9350 3550 9350 13950 +Wire Wire Line + 9350 7750 12700 7750 +Wire Wire Line + 9350 6350 12700 6350 +Connection ~ 9350 7750 +Wire Wire Line + 9350 4950 12700 4950 +Connection ~ 9350 6350 +Wire Wire Line + 9350 3550 12700 3550 +Connection ~ 9350 4950 +Wire Wire Line + 9350 9750 12750 9750 +Connection ~ 9350 8750 +Wire Wire Line + 9350 11150 12750 11150 +Connection ~ 9350 9750 +Wire Wire Line + 9350 12550 12750 12550 +Connection ~ 9350 11150 +Wire Wire Line + 9350 13950 12750 13950 +Connection ~ 9350 12550 +Wire Wire Line + 12750 12650 5400 12650 +Wire Wire Line + 12750 13350 5500 13350 +Wire Wire Line + 12750 14050 5400 14050 +Wire Wire Line + 12750 14750 5300 14750 +Wire Wire Line + 9650 9000 5150 9000 +Wire Wire Line + 9650 2950 9650 14650 +Wire Wire Line + 9650 6450 12700 6450 +Wire Wire Line + 12700 5750 9650 5750 +Connection ~ 9650 6450 +Wire Wire Line + 9650 3650 12700 3650 +Connection ~ 9650 5750 +Wire Wire Line + 9650 2950 12700 2950 +Connection ~ 9650 3650 +Wire Wire Line + 9650 11050 12750 11050 +Connection ~ 9650 9000 +Wire Wire Line + 9650 11750 12750 11750 +Connection ~ 9650 11050 +Connection ~ 9650 11750 +Wire Wire Line + 9650 14650 12750 14650 +Wire Wire Line + 12750 13850 9650 13850 +Connection ~ 9650 13850 +Wire Wire Line + 9200 14550 12750 14550 +Wire Wire Line + 9800 4350 9800 13250 +Wire Wire Line + 9800 7850 12700 7850 +Wire Wire Line + 9800 7150 12700 7150 +Connection ~ 9800 7850 +Wire Wire Line + 9800 5050 12700 5050 +Connection ~ 9800 7150 +Wire Wire Line + 9800 4350 12700 4350 +Connection ~ 9800 5050 +Wire Wire Line + 9800 9650 12750 9650 +Connection ~ 9800 9200 +Wire Wire Line + 9800 10350 12750 10350 +Connection ~ 9800 9650 +Wire Wire Line + 9800 12450 12750 12450 +Connection ~ 9800 10350 +Wire Wire Line + 9800 13250 12750 13250 +Connection ~ 9800 12450 +Wire Wire Line + 10100 9450 5150 9450 +Wire Wire Line + 10100 3050 10100 14450 +Wire Wire Line + 10100 5150 12700 5150 +Wire Wire Line + 12700 4450 10100 4450 +Connection ~ 10100 5150 +Wire Wire Line + 12700 3750 10100 3750 +Connection ~ 10100 4450 +Wire Wire Line + 12700 3050 10100 3050 +Connection ~ 10100 3750 +Wire Wire Line + 10100 12350 12750 12350 +Connection ~ 10100 9450 +Wire Wire Line + 10100 13150 12750 13150 +Connection ~ 10100 12350 +Wire Wire Line + 10100 13750 12750 13750 +Connection ~ 10100 13150 +Wire Wire Line + 10100 14450 12750 14450 +Connection ~ 10100 13750 +Wire Wire Line + 8900 9650 8900 9550 +Wire Wire Line + 8900 9550 12750 9550 +Wire Wire Line + 10250 5850 10250 11650 +Wire Wire Line + 10250 7950 12700 7950 +Wire Wire Line + 10250 7250 12700 7250 +Connection ~ 10250 7950 +Wire Wire Line + 10250 6550 12700 6550 +Connection ~ 10250 7250 +Wire Wire Line + 10250 5850 12700 5850 +Connection ~ 10250 6550 +Connection ~ 10250 9550 +Wire Wire Line + 10250 10250 12750 10250 +Wire Wire Line + 10250 10950 12750 10950 +Connection ~ 10250 10250 +Wire Wire Line + 10250 11650 12750 11650 +Connection ~ 10250 10950 +Wire Wire Line + 13700 2950 13950 2950 +Wire Wire Line + 13950 2950 13950 3250 +Wire Wire Line + 13950 3250 14100 3250 +Wire Wire Line + 14100 3350 14000 3350 +Wire Wire Line + 14000 3350 14000 3650 +Wire Wire Line + 14000 3650 13700 3650 +Wire Wire Line + 13700 4350 13950 4350 +Wire Wire Line + 13950 4350 13950 4650 +Wire Wire Line + 13950 4650 14150 4650 +Wire Wire Line + 14150 4750 13950 4750 +Wire Wire Line + 13950 4750 13950 5050 +Wire Wire Line + 13950 5050 13700 5050 +Wire Wire Line + 13700 5750 14050 5750 +Wire Wire Line + 14050 5750 14050 6050 +Wire Wire Line + 14050 6050 14200 6050 +Wire Wire Line + 14200 6150 14050 6150 +Wire Wire Line + 14050 6150 14050 6450 +Wire Wire Line + 14050 6450 13700 6450 +Wire Wire Line + 13700 7150 13950 7150 +Wire Wire Line + 13950 7150 13950 7500 +Wire Wire Line + 13950 7500 14250 7500 +Wire Wire Line + 13950 7600 14250 7600 +Wire Wire Line + 13950 7600 13950 7850 +Wire Wire Line + 13950 7850 13700 7850 +Wire Wire Line + 13750 9650 14000 9650 +Wire Wire Line + 14000 9650 14000 9950 +Wire Wire Line + 14000 9950 14150 9950 +Wire Wire Line + 14150 10050 14000 10050 +Wire Wire Line + 14000 10050 14000 10350 +Wire Wire Line + 14000 10350 13750 10350 +Wire Wire Line + 13750 11050 14000 11050 +Wire Wire Line + 14000 11050 14000 11350 +Wire Wire Line + 14000 11350 14200 11350 +Wire Wire Line + 14200 11450 14000 11450 +Wire Wire Line + 14000 11450 14000 11750 +Wire Wire Line + 14000 11750 13750 11750 +Wire Wire Line + 13750 12450 14000 12450 +Wire Wire Line + 14000 12450 14000 12750 +Wire Wire Line + 14000 12750 14250 12750 +Wire Wire Line + 14250 12850 14050 12850 +Wire Wire Line + 14050 12850 14050 13150 +Wire Wire Line + 14050 13150 13750 13150 +Wire Wire Line + 13750 13850 14000 13850 +Wire Wire Line + 14000 13850 14000 14200 +Wire Wire Line + 14000 14200 14300 14200 +Wire Wire Line + 14300 14300 14000 14300 +Wire Wire Line + 14000 14300 14000 14550 +Wire Wire Line + 14000 14550 13750 14550 +Wire Wire Line + 15000 3300 15300 3300 +Wire Wire Line + 15300 3300 15300 3950 +Wire Wire Line + 15300 3950 15600 3950 +Wire Wire Line + 15600 4050 15300 4050 +Wire Wire Line + 15300 4050 15300 4700 +Wire Wire Line + 15300 4700 15050 4700 +Wire Wire Line + 15100 6100 15350 6100 +Wire Wire Line + 15350 6100 15350 6700 +Wire Wire Line + 15350 6700 15700 6700 +Wire Wire Line + 15700 6800 15400 6800 +Wire Wire Line + 15400 6800 15400 7550 +Wire Wire Line + 15400 7550 15150 7550 +Wire Wire Line + 16500 4000 16650 4000 +Wire Wire Line + 16650 4000 16650 5350 +Wire Wire Line + 16650 5350 16750 5350 +Wire Wire Line + 16750 5450 16650 5450 +Wire Wire Line + 16650 5450 16650 6750 +Wire Wire Line + 16650 6750 16600 6750 +Wire Wire Line + 15050 10000 15350 10000 +Wire Wire Line + 15350 10000 15350 10650 +Wire Wire Line + 15350 10650 15650 10650 +Wire Wire Line + 15650 10750 15350 10750 +Wire Wire Line + 15350 10750 15350 11400 +Wire Wire Line + 15350 11400 15100 11400 +Wire Wire Line + 15150 12800 15400 12800 +Wire Wire Line + 15400 12800 15400 13400 +Wire Wire Line + 15400 13400 15750 13400 +Wire Wire Line + 15750 13500 15450 13500 +Wire Wire Line + 15450 13500 15450 14250 +Wire Wire Line + 15450 14250 15200 14250 +Wire Wire Line + 16550 10700 16700 10700 +Wire Wire Line + 16700 10700 16700 12050 +Wire Wire Line + 16700 12050 16800 12050 +Wire Wire Line + 16800 12150 16700 12150 +Wire Wire Line + 16700 12150 16700 13450 +Wire Wire Line + 16700 13450 16650 13450 +Wire Wire Line + 12500 9100 18100 9100 +Wire Wire Line + 18100 9100 18100 12000 +Wire Wire Line + 18100 12000 18200 12000 +Connection ~ 12500 9100 +Wire Wire Line + 17650 1600 17650 5300 +Wire Wire Line + 17650 5300 17950 5300 +Connection ~ 12500 1600 +Wire Wire Line + 18850 5350 19200 5350 +Wire Wire Line + 19100 12050 19400 12050 +$Comp +L PORT U1 +U 1 1 679707E9 +P 19450 5350 +F 0 "U1" H 19500 5450 30 0000 C CNN +F 1 "PORT" H 19450 5350 30 0000 C CNN +F 2 "" H 19450 5350 60 0000 C CNN +F 3 "" H 19450 5350 60 0000 C CNN + 1 19450 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 19 1 67970C99 +P 19650 12050 +F 0 "U1" H 19700 12150 30 0000 C CNN +F 1 "PORT" H 19650 12050 30 0000 C CNN +F 2 "" H 19650 12050 60 0000 C CNN +F 3 "" H 19650 12050 60 0000 C CNN + 19 19650 12050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 67970F44 +P 5750 1600 +F 0 "U1" H 5800 1700 30 0000 C CNN +F 1 "PORT" H 5750 1600 30 0000 C CNN +F 2 "" H 5750 1600 60 0000 C CNN +F 3 "" H 5750 1600 60 0000 C CNN + 2 5750 1600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67970FD6 +P 5150 2750 +F 0 "U1" H 5200 2850 30 0000 C CNN +F 1 "PORT" H 5150 2750 30 0000 C CNN +F 2 "" H 5150 2750 60 0000 C CNN +F 3 "" H 5150 2750 60 0000 C CNN + 6 5150 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679711F9 +P 5150 3450 +F 0 "U1" H 5200 3550 30 0000 C CNN +F 1 "PORT" H 5150 3450 30 0000 C CNN +F 2 "" H 5150 3450 60 0000 C CNN +F 3 "" H 5150 3450 60 0000 C CNN + 7 5150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679713AA +P 5150 4150 +F 0 "U1" H 5200 4250 30 0000 C CNN +F 1 "PORT" H 5150 4150 30 0000 C CNN +F 2 "" H 5150 4150 60 0000 C CNN +F 3 "" H 5150 4150 60 0000 C CNN + 8 5150 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 679714E7 +P 5200 4850 +F 0 "U1" H 5250 4950 30 0000 C CNN +F 1 "PORT" H 5200 4850 30 0000 C CNN +F 2 "" H 5200 4850 60 0000 C CNN +F 3 "" H 5200 4850 60 0000 C CNN + 9 5200 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 67971606 +P 5250 5550 +F 0 "U1" H 5300 5650 30 0000 C CNN +F 1 "PORT" H 5250 5550 30 0000 C CNN +F 2 "" H 5250 5550 60 0000 C CNN +F 3 "" H 5250 5550 60 0000 C CNN + 14 5250 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67971753 +P 5200 6250 +F 0 "U1" H 5250 6350 30 0000 C CNN +F 1 "PORT" H 5200 6250 30 0000 C CNN +F 2 "" H 5200 6250 60 0000 C CNN +F 3 "" H 5200 6250 60 0000 C CNN + 13 5200 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6797187A +P 5200 6950 +F 0 "U1" H 5250 7050 30 0000 C CNN +F 1 "PORT" H 5200 6950 30 0000 C CNN +F 2 "" H 5200 6950 60 0000 C CNN +F 3 "" H 5200 6950 60 0000 C CNN + 12 5200 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 679719A5 +P 5200 7650 +F 0 "U1" H 5250 7750 30 0000 C CNN +F 1 "PORT" H 5200 7650 30 0000 C CNN +F 2 "" H 5200 7650 60 0000 C CNN +F 3 "" H 5200 7650 60 0000 C CNN + 11 5200 7650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67971B42 +P 3450 8550 +F 0 "U1" H 3500 8650 30 0000 C CNN +F 1 "PORT" H 3450 8550 30 0000 C CNN +F 2 "" H 3450 8550 60 0000 C CNN +F 3 "" H 3450 8550 60 0000 C CNN + 3 3450 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67971C7F +P 3450 9000 +F 0 "U1" H 3500 9100 30 0000 C CNN +F 1 "PORT" H 3450 9000 30 0000 C CNN +F 2 "" H 3450 9000 60 0000 C CNN +F 3 "" H 3450 9000 60 0000 C CNN + 4 3450 9000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67971DF1 +P 3450 9450 +F 0 "U1" H 3500 9550 30 0000 C CNN +F 1 "PORT" H 3450 9450 30 0000 C CNN +F 2 "" H 3450 9450 60 0000 C CNN +F 3 "" H 3450 9450 60 0000 C CNN + 5 3450 9450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6797215C +P 5150 12650 +F 0 "U1" H 5200 12750 30 0000 C CNN +F 1 "PORT" H 5150 12650 30 0000 C CNN +F 2 "" H 5150 12650 60 0000 C CNN +F 3 "" H 5150 12650 60 0000 C CNN + 15 5150 12650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 679721E9 +P 5250 13350 +F 0 "U1" H 5300 13450 30 0000 C CNN +F 1 "PORT" H 5250 13350 30 0000 C CNN +F 2 "" H 5250 13350 60 0000 C CNN +F 3 "" H 5250 13350 60 0000 C CNN + 16 5250 13350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 679723A6 +P 5150 14050 +F 0 "U1" H 5200 14150 30 0000 C CNN +F 1 "PORT" H 5150 14050 30 0000 C CNN +F 2 "" H 5150 14050 60 0000 C CNN +F 3 "" H 5150 14050 60 0000 C CNN + 17 5150 14050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 679724FF +P 5050 14750 +F 0 "U1" H 5100 14850 30 0000 C CNN +F 1 "PORT" H 5050 14750 30 0000 C CNN +F 2 "" H 5050 14750 60 0000 C CNN +F 3 "" H 5050 14750 60 0000 C CNN + 18 5050 14750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6797287E +P 19250 7400 +F 0 "U1" H 19300 7500 30 0000 C CNN +F 1 "PORT" H 19250 7400 30 0000 C CNN +F 2 "" H 19250 7400 60 0000 C CNN +F 3 "" H 19250 7400 60 0000 C CNN + 10 19250 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 67972905 +P 19250 7600 +F 0 "U1" H 19300 7700 30 0000 C CNN +F 1 "PORT" H 19250 7600 30 0000 C CNN +F 2 "" H 19250 7600 60 0000 C CNN +F 3 "" H 19250 7600 60 0000 C CNN + 20 19250 7600 + 1 0 0 -1 +$EndComp +NoConn ~ 19500 7400 +NoConn ~ 19500 7600 +Wire Wire Line + 6000 1600 6400 1600 +$Comp +L d_and U20 +U 1 1 67960926 +P 18400 5400 +F 0 "U20" H 18400 5400 60 0000 C CNN +F 1 "d_and" H 18450 5500 60 0000 C CNN +F 2 "" H 18400 5400 60 0000 C CNN +F 3 "" H 18400 5400 60 0000 C CNN + 1 18400 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 67961044 +P 18650 12100 +F 0 "U21" H 18650 12100 60 0000 C CNN +F 1 "d_and" H 18700 12200 60 0000 C CNN +F 2 "" H 18650 12100 60 0000 C CNN +F 3 "" H 18650 12100 60 0000 C CNN + 1 18650 12100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 67A37DDA +P 17200 5450 +F 0 "U18" H 17200 5450 60 0000 C CNN +F 1 "d_or" H 17200 5550 60 0000 C CNN +F 2 "" H 17200 5450 60 0000 C CNN +F 3 "" H 17200 5450 60 0000 C CNN + 1 17200 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U14 +U 1 1 67A37FBD +P 16050 4050 +F 0 "U14" H 16050 4050 60 0000 C CNN +F 1 "d_or" H 16050 4150 60 0000 C CNN +F 2 "" H 16050 4050 60 0000 C CNN +F 3 "" H 16050 4050 60 0000 C CNN + 1 16050 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U16 +U 1 1 67A380A2 +P 16150 6800 +F 0 "U16" H 16150 6800 60 0000 C CNN +F 1 "d_or" H 16150 6900 60 0000 C CNN +F 2 "" H 16150 6800 60 0000 C CNN +F 3 "" H 16150 6800 60 0000 C CNN + 1 16150 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U11 +U 1 1 67A38127 +P 14700 7600 +F 0 "U11" H 14700 7600 60 0000 C CNN +F 1 "d_or" H 14700 7700 60 0000 C CNN +F 2 "" H 14700 7600 60 0000 C CNN +F 3 "" H 14700 7600 60 0000 C CNN + 1 14700 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 67A381AE +P 14650 6150 +F 0 "U9" H 14650 6150 60 0000 C CNN +F 1 "d_or" H 14650 6250 60 0000 C CNN +F 2 "" H 14650 6150 60 0000 C CNN +F 3 "" H 14650 6150 60 0000 C CNN + 1 14650 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U7 +U 1 1 67A382B3 +P 14600 4750 +F 0 "U7" H 14600 4750 60 0000 C CNN +F 1 "d_or" H 14600 4850 60 0000 C CNN +F 2 "" H 14600 4750 60 0000 C CNN +F 3 "" H 14600 4750 60 0000 C CNN + 1 14600 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 67A3833C +P 14550 3350 +F 0 "U6" H 14550 3350 60 0000 C CNN +F 1 "d_or" H 14550 3450 60 0000 C CNN +F 2 "" H 14550 3350 60 0000 C CNN +F 3 "" H 14550 3350 60 0000 C CNN + 1 14550 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 67A3867A +P 17250 12150 +F 0 "U19" H 17250 12150 60 0000 C CNN +F 1 "d_or" H 17250 12250 60 0000 C CNN +F 2 "" H 17250 12150 60 0000 C CNN +F 3 "" H 17250 12150 60 0000 C CNN + 1 17250 12150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U17 +U 1 1 67A387A5 +P 16200 13500 +F 0 "U17" H 16200 13500 60 0000 C CNN +F 1 "d_or" H 16200 13600 60 0000 C CNN +F 2 "" H 16200 13500 60 0000 C CNN +F 3 "" H 16200 13500 60 0000 C CNN + 1 16200 13500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 67A38826 +P 16100 10750 +F 0 "U15" H 16100 10750 60 0000 C CNN +F 1 "d_or" H 16100 10850 60 0000 C CNN +F 2 "" H 16100 10750 60 0000 C CNN +F 3 "" H 16100 10750 60 0000 C CNN + 1 16100 10750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 67A38AC4 +P 14600 10050 +F 0 "U8" H 14600 10050 60 0000 C CNN +F 1 "d_or" H 14600 10150 60 0000 C CNN +F 2 "" H 14600 10050 60 0000 C CNN +F 3 "" H 14600 10050 60 0000 C CNN + 1 14600 10050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 67A38B5F +P 14650 11450 +F 0 "U10" H 14650 11450 60 0000 C CNN +F 1 "d_or" H 14650 11550 60 0000 C CNN +F 2 "" H 14650 11450 60 0000 C CNN +F 3 "" H 14650 11450 60 0000 C CNN + 1 14650 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U12 +U 1 1 67A38CFC +P 14700 12850 +F 0 "U12" H 14700 12850 60 0000 C CNN +F 1 "d_or" H 14700 12950 60 0000 C CNN +F 2 "" H 14700 12850 60 0000 C CNN +F 3 "" H 14700 12850 60 0000 C CNN + 1 14700 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U13 +U 1 1 67A38D7F +P 14750 14300 +F 0 "U13" H 14750 14300 60 0000 C CNN +F 1 "d_or" H 14750 14400 60 0000 C CNN +F 2 "" H 14750 14300 60 0000 C CNN +F 3 "" H 14750 14300 60 0000 C CNN + 1 14750 14300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 67A393F8 +P 17800 5950 +F 0 "U22" H 17800 5850 60 0000 C CNN +F 1 "d_inverter" H 17800 6100 60 0000 C CNN +F 2 "" H 17850 5900 60 0000 C CNN +F 3 "" H 17850 5900 60 0000 C CNN + 1 17800 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 67A39864 +P 17900 12500 +F 0 "U23" H 17900 12400 60 0000 C CNN +F 1 "d_inverter" H 17900 12650 60 0000 C CNN +F 2 "" H 17950 12450 60 0000 C CNN +F 3 "" H 17950 12450 60 0000 C CNN + 1 17900 12500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17700 12100 17800 12100 +Wire Wire Line + 17800 12100 17800 12250 +Wire Wire Line + 17800 12250 17500 12250 +Wire Wire Line + 17500 12250 17500 12500 +Wire Wire Line + 17500 12500 17600 12500 +Wire Wire Line + 18200 12500 18250 12500 +Wire Wire Line + 18250 12500 18250 12250 +Wire Wire Line + 18250 12250 18150 12250 +Wire Wire Line + 18150 12250 18150 12100 +Wire Wire Line + 18150 12100 18200 12100 +Wire Wire Line + 17650 5400 17700 5400 +Wire Wire Line + 17700 5400 17700 5650 +Wire Wire Line + 17700 5650 17350 5650 +Wire Wire Line + 17350 5650 17350 5950 +Wire Wire Line + 17350 5950 17500 5950 +Wire Wire Line + 18100 5950 18200 5950 +Wire Wire Line + 18200 5950 18200 5650 +Wire Wire Line + 18200 5650 17800 5650 +Wire Wire Line + 17800 5650 17800 5400 +Wire Wire Line + 17800 5400 17950 5400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sub b/library/SubcircuitLibrary/SN74351/SN74351.sub new file mode 100644 index 00000000..87054221 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sub @@ -0,0 +1,111 @@ +* Subcircuit SN74351 +.subckt SN74351 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends SN74351
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml new file mode 100644 index 00000000..77e9ef56 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u19><u5 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u18 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u16><u14 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u6><u20 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u14 name="type">d_or<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u11 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u11><u9 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u9><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u6><u19 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u19><u17 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u15 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u15><u8 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u23></model><devicemodel /><subcircuit><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x15><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x16><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x10></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/analysis b/library/SubcircuitLibrary/SN74351/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/browser/User-Manual/eSim.html b/library/browser/User-Manual/eSim.html index 79afa31e..712ecbaf 100644 --- a/library/browser/User-Manual/eSim.html +++ b/library/browser/User-Manual/eSim.html @@ -28,7 +28,7 @@ src="figures/logo-trimmed.png" alt="PIC" <span class="cmbx-12x-x-144">eSim User Manual</span><br /> <span -class="cmr-10">version 1.0.0</span><br /> +class="cmr-10">version 2.4.0</span><br /> <span class="cmbx-10">Prepared By:</span><br /> <span @@ -3565,7 +3565,8 @@ href="http://www.scilab.org/" class="url" >http://www.scilab.org/</a> [4]<span class="bibsp">   </span></span><a id="XGARUDA"></a>(2013, May). [Online]. Available: <a -href="http://scilab-test.garudaindia.in/scilab_in/,
http://scilab-test.garudaindia.in/cloud" class="url" >http://scilab-test.garudaindia.in/scilab_in/,http://scilab-test.garudaindia.in/cloud</a> +href="http://scilab-test.garudaindia.in/scilab_in/, + http://scilab-test.garudaindia.in/cloud" class="url" >http://scilab-test.garudaindia.in/scilab_in/,http://scilab-test.garudaindia.in/cloud</a> </p> <p class="bibitem" ><span class="biblabel"> [5]<span class="bibsp">   </span></span><a @@ -9,7 +9,7 @@ Needed to define the module structure, look up `Modules` for python ''' setup( name='eSim', - version='2.3.0', + version='2.4.0', author='FOSSEE', author_email='contact-esim@fossee.in', package_dir={'': 'src'}, diff --git a/src/browser/UserManual.py b/src/browser/UserManual.py index 5f12bdc0..4ac78825 100644 --- a/src/browser/UserManual.py +++ b/src/browser/UserManual.py @@ -14,7 +14,7 @@ class UserManual(QtWidgets.QWidget): self.vlayout = QtWidgets.QVBoxLayout() - manual = 'library/browser/User-Manual/eSim_Manual_2.3.pdf' + manual = 'library/browser/User-Manual/eSim_Manual_2.4.pdf' if os.name == 'nt': os.startfile(os.path.realpath(manual)) diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py index 4decf0b6..6cf8cc30 100644 --- a/src/configuration/Appconfig.py +++ b/src/configuration/Appconfig.py @@ -91,7 +91,7 @@ class Appconfig(QtWidgets.QWidget): # Application Details self._APPLICATION = 'eSim' - self._VERSION = '2.3' + self._VERSION = '2.4' self._AUTHOR = 'Fahim' self._REVISION = 'Rahul, Sumanto' |