diff options
69 files changed, 5592 insertions, 70 deletions
@@ -14,7 +14,7 @@ Table of contents i. After downloading eSim, extract it using: - $ unzip eSim-2.1.zip + $ unzip eSim-2.2.zip ii. Now change directories in to the top-level eSim directory (where this INSTALL file can be found). @@ -43,13 +43,16 @@ Table of contents i. Download eSim for Windows OS from "https://esim.fossee.in/". Disable the antivirus (if any). - ii. Now double click on eSim installer and then follow the instruction to install eSim. + ii. If MinGW and/or MSYS is already installed in your machine, then remove it from the + PATH environment variable as it may interfere with eSim and might not work as intended. - iii. To uninstall eSim and all of its components, run the uninstaller "uninst-eSim.exe" located at + iii. Now double click on eSim installer and then follow the instruction to install eSim. + + iv. To uninstall eSim and all of its components, run the uninstaller "uninst-eSim.exe" located at top-level eSim directory (where this INSTALL file can be found). Note ====== -Please report any eSim installation related issue/error at "https://forums.fossee.in/"
\ No newline at end of file +Please report any eSim installation related issue/error at "https://forums.fossee.in/" @@ -15,8 +15,8 @@ It is an integrated tool build using open source softwares such as KiCad, Ngspic ## Releases and Installation eSim is released for the following distributions (operating systems): -* Ubuntu 16.04 OS and above LTS versions. -* Microsoft Windows 7, 8 and 10. +* Ubuntu 18.04 and 20.04 LTS versions. +* Microsoft Windows 8 and 10. To use eSim on your machine having above distributions, please refer to link [here](https://esim.fossee.in/downloads) for installation and other guidelines. @@ -33,11 +33,12 @@ To use eSim on your machine having above distributions, please refer to link [he ## Open-Source Softwares Used * [Python](https://www.python.org/) -* [KiCad](https://kicad.org/) -* [NGHDL](https://github.com/fossee/nghdl) +* [KiCad](https://www.kicad.org/) +* [Makerchip](https://www.makerchip.com/) +* [NGHDL](https://github.com/fossee/nghdl/) ## eSim Manual -To know everything about eSim, how it works and it's feature please download manual [here](https://static.fossee.in/esim/manuals/eSim_Manual_2020_August.pdf) +To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.2.pdf) ## Contact For any queries regarding eSim please write us on at this [email address](mailto:contact-esim@fossee.in). @@ -1 +1 @@ -2.1 +2.2 @@ -21,13 +21,13 @@ autodoc_mock_imports = ["PyQt5", "pathmagic", "matplotlib", "numpy"] # -- Project information ----------------------------------------------------- project = u'eSim' -copyright = u'2020, FOSSEE' +copyright = u'2022, FOSSEE' author = u'FOSSEE, IIT Bombay' # The short X.Y version -version = u'2.1' +version = u'2.2' # The full version, including alpha/beta/rc tags -release = u'2.1.0' +release = u'2.2.0' # -- General configuration --------------------------------------------------- diff --git a/images/Ps2Ki.png b/images/Ps2Ki.png Binary files differindex f58756b7..f58756b7 100644..100755 --- a/images/Ps2Ki.png +++ b/images/Ps2Ki.png diff --git a/images/makerchip.png b/images/makerchip.png Binary files differnew file mode 100755 index 00000000..848b24a5 --- /dev/null +++ b/images/makerchip.png diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib new file mode 100644 index 00000000..f7dfef8a --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# summer +# +DEF summer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "summer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN1 1 -400 150 200 R 50 50 1 1 I +X IN2 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir new file mode 100644 index 00000000..7090a7d0 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir @@ -0,0 +1,32 @@ +* /home/sumanto/eSim-2.1/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Feb 7 03:24:28 2022 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 1024k +R2 Net-_R2-Pad1_ Net-_R1-Pad2_ 512k +R3 Net-_R3-Pad1_ Net-_R1-Pad2_ 256k +R4 Net-_R4-Pad1_ Net-_R1-Pad2_ 128k +R5 Net-_R5-Pad1_ Net-_R1-Pad2_ 64k +R6 Net-_R6-Pad1_ Net-_R1-Pad2_ 32k +R7 Net-_R7-Pad1_ Net-_R1-Pad2_ 16k +R9 Net-_R9-Pad1_ Net-_R1-Pad2_ 8k +R10 Net-_R10-Pad1_ Net-_R1-Pad2_ 4k +R11 Net-_R11-Pad1_ Net-_R1-Pad2_ 2k +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT +U2 Net-_R1-Pad2_ GND Net-_U1-Pad11_ summer +U3 Net-_U1-Pad1_ GND Net-_R1-Pad1_ summer +U8 Net-_U1-Pad2_ GND Net-_R2-Pad1_ summer +U4 Net-_U1-Pad3_ GND Net-_R3-Pad1_ summer +U5 Net-_U1-Pad4_ GND Net-_R4-Pad1_ summer +U9 Net-_U1-Pad5_ GND Net-_R5-Pad1_ summer +U10 Net-_U1-Pad6_ GND Net-_R6-Pad1_ summer +U6 Net-_U1-Pad7_ GND Net-_R7-Pad1_ summer +U7 Net-_U1-Pad8_ GND Net-_R9-Pad1_ summer +U12 Net-_U1-Pad9_ GND Net-_R10-Pad1_ summer +U11 Net-_U1-Pad10_ GND Net-_R11-Pad1_ summer + +.end diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out new file mode 100644 index 00000000..725a6302 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out @@ -0,0 +1,66 @@ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/10bitdac/10bitdac.cir + +r1 net-_r1-pad1_ net-_r1-pad2_ 1024k +r2 net-_r2-pad1_ net-_r1-pad2_ 512k +r3 net-_r3-pad1_ net-_r1-pad2_ 256k +r4 net-_r4-pad1_ net-_r1-pad2_ 128k +r5 net-_r5-pad1_ net-_r1-pad2_ 64k +r6 net-_r6-pad1_ net-_r1-pad2_ 32k +r7 net-_r7-pad1_ net-_r1-pad2_ 16k +r9 net-_r9-pad1_ net-_r1-pad2_ 8k +r10 net-_r10-pad1_ net-_r1-pad2_ 4k +r11 net-_r11-pad1_ net-_r1-pad2_ 2k +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +* u2 net-_r1-pad2_ gnd net-_u1-pad11_ summer +* u3 net-_u1-pad1_ gnd net-_r1-pad1_ summer +* u8 net-_u1-pad2_ gnd net-_r2-pad1_ summer +* u4 net-_u1-pad3_ gnd net-_r3-pad1_ summer +* u5 net-_u1-pad4_ gnd net-_r4-pad1_ summer +* u9 net-_u1-pad5_ gnd net-_r5-pad1_ summer +* u10 net-_u1-pad6_ gnd net-_r6-pad1_ summer +* u6 net-_u1-pad7_ gnd net-_r7-pad1_ summer +* u7 net-_u1-pad8_ gnd net-_r9-pad1_ summer +* u12 net-_u1-pad9_ gnd net-_r10-pad1_ summer +* u11 net-_u1-pad10_ gnd net-_r11-pad1_ summer +a1 [net-_r1-pad2_ gnd ] net-_u1-pad11_ u2 +a2 [net-_u1-pad1_ gnd ] net-_r1-pad1_ u3 +a3 [net-_u1-pad2_ gnd ] net-_r2-pad1_ u8 +a4 [net-_u1-pad3_ gnd ] net-_r3-pad1_ u4 +a5 [net-_u1-pad4_ gnd ] net-_r4-pad1_ u5 +a6 [net-_u1-pad5_ gnd ] net-_r5-pad1_ u9 +a7 [net-_u1-pad6_ gnd ] net-_r6-pad1_ u10 +a8 [net-_u1-pad7_ gnd ] net-_r7-pad1_ u6 +a9 [net-_u1-pad8_ gnd ] net-_r9-pad1_ u7 +a10 [net-_u1-pad9_ gnd ] net-_r10-pad1_ u12 +a11 [net-_u1-pad10_ gnd ] net-_r11-pad1_ u11 +* Schematic Name: summer, NgSpice Name: summer +.model u2 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u3 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u8 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u4 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u5 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u9 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u10 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u6 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u7 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u12 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u11 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +.tran 1e-03 10e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro b/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch new file mode 100644 index 00000000..09d81434 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch @@ -0,0 +1,555 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:10bitDAC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 61DEB37D +P 4400 2250 +F 0 "R1" H 4450 2380 50 0000 C CNN +F 1 "1024k" H 4450 2200 50 0000 C CNN +F 2 "" H 4450 2230 30 0000 C CNN +F 3 "" V 4450 2300 30 0000 C CNN + 1 4400 2250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 61DEB37E +P 4450 2550 +F 0 "R2" H 4500 2680 50 0000 C CNN +F 1 "512k" H 4500 2500 50 0000 C CNN +F 2 "" H 4500 2530 30 0000 C CNN +F 3 "" V 4500 2600 30 0000 C CNN + 1 4450 2550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 61DEB37F +P 4450 2850 +F 0 "R3" H 4500 2980 50 0000 C CNN +F 1 "256k" H 4500 2800 50 0000 C CNN +F 2 "" H 4500 2830 30 0000 C CNN +F 3 "" V 4500 2900 30 0000 C CNN + 1 4450 2850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 61DEB380 +P 4450 3200 +F 0 "R4" H 4500 3330 50 0000 C CNN +F 1 "128k" H 4500 3150 50 0000 C CNN +F 2 "" H 4500 3180 30 0000 C CNN +F 3 "" V 4500 3250 30 0000 C CNN + 1 4450 3200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 61DEB381 +P 4450 3550 +F 0 "R5" H 4500 3680 50 0000 C CNN +F 1 "64k" H 4500 3500 50 0000 C CNN +F 2 "" H 4500 3530 30 0000 C CNN +F 3 "" V 4500 3600 30 0000 C CNN + 1 4450 3550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 61DEB382 +P 4450 3900 +F 0 "R6" H 4500 4030 50 0000 C CNN +F 1 "32k" H 4500 3850 50 0000 C CNN +F 2 "" H 4500 3880 30 0000 C CNN +F 3 "" V 4500 3950 30 0000 C CNN + 1 4450 3900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 61DEB383 +P 4450 4250 +F 0 "R7" H 4500 4380 50 0000 C CNN +F 1 "16k" H 4500 4200 50 0000 C CNN +F 2 "" H 4500 4230 30 0000 C CNN +F 3 "" V 4500 4300 30 0000 C CNN + 1 4450 4250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 61DEB384 +P 4450 4600 +F 0 "R9" H 4500 4730 50 0000 C CNN +F 1 "8k" H 4500 4550 50 0000 C CNN +F 2 "" H 4500 4580 30 0000 C CNN +F 3 "" V 4500 4650 30 0000 C CNN + 1 4450 4600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 61DEB385 +P 4450 4900 +F 0 "R10" H 4500 5030 50 0000 C CNN +F 1 "4k" H 4500 4850 50 0000 C CNN +F 2 "" H 4500 4880 30 0000 C CNN +F 3 "" V 4500 4950 30 0000 C CNN + 1 4450 4900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 61DEB386 +P 4400 5200 +F 0 "R11" H 4450 5330 50 0000 C CNN +F 1 "2k" H 4450 5150 50 0000 C CNN +F 2 "" H 4450 5180 30 0000 C CNN +F 3 "" V 4450 5250 30 0000 C CNN + 1 4400 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 61DEFF7E +P 2100 6350 +F 0 "U1" H 2150 6450 30 0000 C CNN +F 1 "PORT" H 2100 6350 30 0000 C CNN +F 2 "" H 2100 6350 60 0000 C CNN +F 3 "" H 2100 6350 60 0000 C CNN + 10 2100 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 61DEFFF5 +P 2100 5800 +F 0 "U1" H 2150 5900 30 0000 C CNN +F 1 "PORT" H 2100 5800 30 0000 C CNN +F 2 "" H 2100 5800 60 0000 C CNN +F 3 "" H 2100 5800 60 0000 C CNN + 9 2100 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 61DF0058 +P 2050 5250 +F 0 "U1" H 2100 5350 30 0000 C CNN +F 1 "PORT" H 2050 5250 30 0000 C CNN +F 2 "" H 2050 5250 60 0000 C CNN +F 3 "" H 2050 5250 60 0000 C CNN + 8 2050 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 61DF00BB +P 2050 4650 +F 0 "U1" H 2100 4750 30 0000 C CNN +F 1 "PORT" H 2050 4650 30 0000 C CNN +F 2 "" H 2050 4650 60 0000 C CNN +F 3 "" H 2050 4650 60 0000 C CNN + 7 2050 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 61DF0148 +P 2100 4000 +F 0 "U1" H 2150 4100 30 0000 C CNN +F 1 "PORT" H 2100 4000 30 0000 C CNN +F 2 "" H 2100 4000 60 0000 C CNN +F 3 "" H 2100 4000 60 0000 C CNN + 6 2100 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 61DF01D7 +P 2100 3450 +F 0 "U1" H 2150 3550 30 0000 C CNN +F 1 "PORT" H 2100 3450 30 0000 C CNN +F 2 "" H 2100 3450 60 0000 C CNN +F 3 "" H 2100 3450 60 0000 C CNN + 5 2100 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 61DF026C +P 2050 2900 +F 0 "U1" H 2100 3000 30 0000 C CNN +F 1 "PORT" H 2050 2900 30 0000 C CNN +F 2 "" H 2050 2900 60 0000 C CNN +F 3 "" H 2050 2900 60 0000 C CNN + 4 2050 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 61DF0309 +P 2050 2350 +F 0 "U1" H 2100 2450 30 0000 C CNN +F 1 "PORT" H 2050 2350 30 0000 C CNN +F 2 "" H 2050 2350 60 0000 C CNN +F 3 "" H 2050 2350 60 0000 C CNN + 3 2050 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 61DF03AE +P 2100 1850 +F 0 "U1" H 2150 1950 30 0000 C CNN +F 1 "PORT" H 2100 1850 30 0000 C CNN +F 2 "" H 2100 1850 60 0000 C CNN +F 3 "" H 2100 1850 60 0000 C CNN + 2 2100 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 61DF041D +P 2050 1250 +F 0 "U1" H 2100 1350 30 0000 C CNN +F 1 "PORT" H 2050 1250 30 0000 C CNN +F 2 "" H 2050 1250 60 0000 C CNN +F 3 "" H 2050 1250 60 0000 C CNN + 1 2050 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 61DF0D04 +P 7650 5200 +F 0 "U1" H 7700 5300 30 0000 C CNN +F 1 "PORT" H 7650 5200 30 0000 C CNN +F 2 "" H 7650 5200 60 0000 C CNN +F 3 "" H 7650 5200 60 0000 C CNN + 11 7650 5200 + -1 0 0 -1 +$EndComp +$Comp +L summer U2 +U 1 1 61DEBE2F +P 6550 4000 +F 0 "U2" H 6550 3950 60 0000 C CNN +F 1 "summer" H 6550 4050 60 0000 C CNN +F 2 "" H 6550 4000 60 0000 C CNN +F 3 "" H 6550 4000 60 0000 C CNN + 1 6550 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 61DEBEC1 +P 6150 4150 +F 0 "#PWR2" H 6150 3900 50 0001 C CNN +F 1 "GND" H 6150 4000 50 0000 C CNN +F 2 "" H 6150 4150 50 0001 C CNN +F 3 "" H 6150 4150 50 0001 C CNN + 1 6150 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4850 4650 4850 +Wire Wire Line + 5100 2200 5100 5150 +Wire Wire Line + 5100 5150 4600 5150 +Wire Wire Line + 4600 2200 5100 2200 +Connection ~ 5100 4850 +Wire Wire Line + 4650 2500 5100 2500 +Connection ~ 5100 2500 +Wire Wire Line + 4650 2800 5100 2800 +Connection ~ 5100 2800 +Wire Wire Line + 4650 3150 5100 3150 +Connection ~ 5100 3150 +Wire Wire Line + 4650 3500 5100 3500 +Connection ~ 5100 3500 +Connection ~ 5100 3850 +Wire Wire Line + 4650 4200 5100 4200 +Connection ~ 5100 4200 +Wire Wire Line + 4650 4550 5100 4550 +Connection ~ 5100 4550 +Connection ~ 5750 3850 +Wire Wire Line + 7050 4000 7050 5200 +Wire Wire Line + 7050 5200 7400 5200 +Wire Wire Line + 4650 3850 6150 3850 +Wire Wire Line + 3700 2200 4300 2200 +Wire Wire Line + 3600 2500 4350 2500 +Wire Wire Line + 3500 2800 4350 2800 +Wire Wire Line + 3700 3150 4350 3150 +Wire Wire Line + 3250 3500 4350 3500 +Wire Wire Line + 3250 3850 4350 3850 +Wire Wire Line + 3200 4200 4350 4200 +Wire Wire Line + 3250 4600 4350 4600 +Wire Wire Line + 4350 4600 4350 4550 +Wire Wire Line + 3300 4850 4350 4850 +Wire Wire Line + 3700 5150 4300 5150 +Wire Wire Line + 2350 5800 2400 5800 +$Comp +L summer U3 +U 1 1 62005AB8 +P 2700 1400 +F 0 "U3" H 2700 1350 60 0000 C CNN +F 1 "summer" H 2700 1450 60 0000 C CNN +F 2 "" H 2700 1400 60 0000 C CNN +F 3 "" H 2700 1400 60 0000 C CNN + 1 2700 1400 + 1 0 0 -1 +$EndComp +$Comp +L summer U8 +U 1 1 62006578 +P 2750 2000 +F 0 "U8" H 2750 1950 60 0000 C CNN +F 1 "summer" H 2750 2050 60 0000 C CNN +F 2 "" H 2750 2000 60 0000 C CNN +F 3 "" H 2750 2000 60 0000 C CNN + 1 2750 2000 + 1 0 0 -1 +$EndComp +$Comp +L summer U4 +U 1 1 6200669E +P 2700 2500 +F 0 "U4" H 2700 2450 60 0000 C CNN +F 1 "summer" H 2700 2550 60 0000 C CNN +F 2 "" H 2700 2500 60 0000 C CNN +F 3 "" H 2700 2500 60 0000 C CNN + 1 2700 2500 + 1 0 0 -1 +$EndComp +$Comp +L summer U5 +U 1 1 620067C5 +P 2700 3050 +F 0 "U5" H 2700 3000 60 0000 C CNN +F 1 "summer" H 2700 3100 60 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L summer U9 +U 1 1 62006869 +P 2750 3600 +F 0 "U9" H 2750 3550 60 0000 C CNN +F 1 "summer" H 2750 3650 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 + 1 0 0 -1 +$EndComp +$Comp +L summer U10 +U 1 1 62006A63 +P 2750 4150 +F 0 "U10" H 2750 4100 60 0000 C CNN +F 1 "summer" H 2750 4200 60 0000 C CNN +F 2 "" H 2750 4150 60 0000 C CNN +F 3 "" H 2750 4150 60 0000 C CNN + 1 2750 4150 + 1 0 0 -1 +$EndComp +$Comp +L summer U6 +U 1 1 62006B47 +P 2700 4800 +F 0 "U6" H 2700 4750 60 0000 C CNN +F 1 "summer" H 2700 4850 60 0000 C CNN +F 2 "" H 2700 4800 60 0000 C CNN +F 3 "" H 2700 4800 60 0000 C CNN + 1 2700 4800 + 1 0 0 -1 +$EndComp +$Comp +L summer U7 +U 1 1 62006C2E +P 2700 5400 +F 0 "U7" H 2700 5350 60 0000 C CNN +F 1 "summer" H 2700 5450 60 0000 C CNN +F 2 "" H 2700 5400 60 0000 C CNN +F 3 "" H 2700 5400 60 0000 C CNN + 1 2700 5400 + 1 0 0 -1 +$EndComp +$Comp +L summer U12 +U 1 1 62006D0E +P 2800 5950 +F 0 "U12" H 2800 5900 60 0000 C CNN +F 1 "summer" H 2800 6000 60 0000 C CNN +F 2 "" H 2800 5950 60 0000 C CNN +F 3 "" H 2800 5950 60 0000 C CNN + 1 2800 5950 + 1 0 0 -1 +$EndComp +$Comp +L summer U11 +U 1 1 62006DC0 +P 2750 6500 +F 0 "U11" H 2750 6450 60 0000 C CNN +F 1 "summer" H 2750 6550 60 0000 C CNN +F 2 "" H 2750 6500 60 0000 C CNN +F 3 "" H 2750 6500 60 0000 C CNN + 1 2750 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3200 1400 3700 1400 +Wire Wire Line + 3700 1400 3700 2200 +Wire Wire Line + 3600 2500 3600 2000 +Wire Wire Line + 3600 2000 3250 2000 +Wire Wire Line + 3200 2500 3500 2500 +Wire Wire Line + 3500 2500 3500 2800 +Wire Wire Line + 3200 3050 3700 3050 +Wire Wire Line + 3700 3050 3700 3150 +Wire Wire Line + 3250 3500 3250 3600 +Wire Wire Line + 3250 3850 3250 4150 +Wire Wire Line + 3200 4200 3200 4800 +Wire Wire Line + 3250 4600 3250 5400 +Wire Wire Line + 3250 5400 3200 5400 +Wire Wire Line + 3300 4850 3300 5950 +Wire Wire Line + 3700 5150 3700 6500 +Wire Wire Line + 3700 6500 3250 6500 +$Comp +L GND #PWR1 +U 1 1 620071B7 +P 1400 6750 +F 0 "#PWR1" H 1400 6500 50 0001 C CNN +F 1 "GND" H 1400 6600 50 0000 C CNN +F 2 "" H 1400 6750 50 0001 C CNN +F 3 "" H 1400 6750 50 0001 C CNN + 1 1400 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2350 6650 1400 6650 +Wire Wire Line + 1400 6650 1400 6750 +Wire Wire Line + 2400 6100 1450 6100 +Wire Wire Line + 1450 4300 1450 6650 +Connection ~ 1450 6650 +Wire Wire Line + 2300 5550 1450 5550 +Connection ~ 1450 6100 +Wire Wire Line + 2300 4950 1450 4950 +Connection ~ 1450 5550 +Wire Wire Line + 2350 4300 1450 4300 +Connection ~ 1450 4950 +Wire Wire Line + 2350 3750 1450 3750 +Wire Wire Line + 1450 1550 1450 4350 +Connection ~ 1450 4350 +Wire Wire Line + 2300 3200 1450 3200 +Connection ~ 1450 3750 +Wire Wire Line + 2300 2650 1450 2650 +Connection ~ 1450 3200 +Wire Wire Line + 2350 2150 1450 2150 +Connection ~ 1450 2650 +Wire Wire Line + 2300 1550 1450 1550 +Connection ~ 1450 2150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub new file mode 100644 index 00000000..0a0445d9 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub @@ -0,0 +1,61 @@ +* Subcircuit 10bitDAC + +.subckt 10bitDAC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/10bitdac/10bitdac.cir +r1 net-_r1-pad1_ net-_r1-pad2_ 1024k +r2 net-_r2-pad1_ net-_r1-pad2_ 512k +r3 net-_r3-pad1_ net-_r1-pad2_ 256k +r4 net-_r4-pad1_ net-_r1-pad2_ 128k +r5 net-_r5-pad1_ net-_r1-pad2_ 64k +r6 net-_r6-pad1_ net-_r1-pad2_ 32k +r7 net-_r7-pad1_ net-_r1-pad2_ 16k +r9 net-_r9-pad1_ net-_r1-pad2_ 8k +r10 net-_r10-pad1_ net-_r1-pad2_ 4k +r11 net-_r11-pad1_ net-_r1-pad2_ 2k +* u2 net-_r1-pad2_ gnd net-_u1-pad11_ summer +* u3 net-_u1-pad1_ gnd net-_r1-pad1_ summer +* u8 net-_u1-pad2_ gnd net-_r2-pad1_ summer +* u4 net-_u1-pad3_ gnd net-_r3-pad1_ summer +* u5 net-_u1-pad4_ gnd net-_r4-pad1_ summer +* u9 net-_u1-pad5_ gnd net-_r5-pad1_ summer +* u10 net-_u1-pad6_ gnd net-_r6-pad1_ summer +* u6 net-_u1-pad7_ gnd net-_r7-pad1_ summer +* u7 net-_u1-pad8_ gnd net-_r9-pad1_ summer +* u12 net-_u1-pad9_ gnd net-_r10-pad1_ summer +* u11 net-_u1-pad10_ gnd net-_r11-pad1_ summer +a1 [net-_r1-pad2_ gnd ] net-_u1-pad11_ u2 +a2 [net-_u1-pad1_ gnd ] net-_r1-pad1_ u3 +a3 [net-_u1-pad2_ gnd ] net-_r2-pad1_ u8 +a4 [net-_u1-pad3_ gnd ] net-_r3-pad1_ u4 +a5 [net-_u1-pad4_ gnd ] net-_r4-pad1_ u5 +a6 [net-_u1-pad5_ gnd ] net-_r5-pad1_ u9 +a7 [net-_u1-pad6_ gnd ] net-_r6-pad1_ u10 +a8 [net-_u1-pad7_ gnd ] net-_r7-pad1_ u6 +a9 [net-_u1-pad8_ gnd ] net-_r9-pad1_ u7 +a10 [net-_u1-pad9_ gnd ] net-_r10-pad1_ u12 +a11 [net-_u1-pad10_ gnd ] net-_r11-pad1_ u11 +* Schematic Name: summer, NgSpice Name: summer +.model u2 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u3 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u8 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u4 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u5 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u9 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u10 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u6 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u7 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u12 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u11 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Control Statements + +.ends 10bitDAC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml b/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml new file mode 100644 index 00000000..25253eac --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1></source><model><u2 name="type">summer<field1 name="Enter offset for input (default=0.0) 1" /><field2 name="Enter offset for input (default=0.0) 2" /><field3 name="Enter gain for input(default=1.0) 1" /><field4 name="Enter gain for input(default=1.0) 2" /><field5 name="Enter gain for output (default=1.0)" /><field6 name="Enter offset for output (default=0.0)" /></u2><u12 name="type">summer<field1 name="Enter offset for input (default=0.0) 1" /><field2 name="Enter offset for input (default=0.0) 2" /><field3 name="Enter gain for input(default=1.0) 1" /><field4 name="Enter gain for input(default=1.0) 2" /><field5 name="Enter gain for output (default=1.0)" /><field6 name="Enter offset for output (default=0.0)" /></u12><u3 name="type">gain<field7 name="Enter offset for input (default=0.0)" /><field8 name="Enter gain (default=1.0) 1" /><field9 name="Enter offset for output (default=0.0)" /></u3><u4 name="type">gain<field10 name="Enter offset for input (default=0.0)" /><field11 name="Enter gain (default=1.0) 1" /><field12 name="Enter offset for output (default=0.0)" /></u4><u5 name="type">gain<field13 name="Enter offset for input (default=0.0)" /><field14 name="Enter gain (default=1.0) 1" /><field15 name="Enter offset for output (default=0.0)" /></u5><u6 name="type">gain<field16 name="Enter offset for input (default=0.0)" /><field17 name="Enter gain (default=1.0) 1" /><field18 name="Enter offset for output (default=0.0)" /></u6><u7 name="type">gain<field19 name="Enter offset for input (default=0.0)" /><field20 name="Enter gain (default=1.0) 1" /><field21 name="Enter offset for output (default=0.0)" /></u7><u8 name="type">gain<field22 name="Enter offset for input (default=0.0)" /><field23 name="Enter gain (default=1.0) 1" /><field24 name="Enter offset for output (default=0.0)" /></u8><u9 name="type">gain<field25 name="Enter offset for input (default=0.0)" /><field26 name="Enter gain (default=1.0) 1" /><field27 name="Enter offset for output (default=0.0)" /></u9><u10 name="type">gain<field28 name="Enter offset for input (default=0.0)" /><field29 name="Enter gain (default=1.0) 1" /><field30 name="Enter offset for output (default=0.0)" /></u10><u12 name="type">gain<field31 name="Enter offset for input (default=0.0)" /><field32 name="Enter gain (default=1.0) 1" /><field33 name="Enter offset for output (default=0.0)" /></u12><u11 name="type">gain<field34 name="Enter offset for input (default=0.0)" /><field35 name="Enter gain (default=1.0) 1" /><field36 name="Enter offset for output (default=0.0)" /></u11><u3 name="type">summer<field7 name="Enter offset for input (default=0.0) 1" /><field8 name="Enter offset for input (default=0.0) 2" /><field9 name="Enter gain for input(default=1.0) 1" /><field10 name="Enter gain for input(default=1.0) 2" /><field11 name="Enter gain for output (default=1.0)" /><field12 name="Enter offset for output (default=0.0)" /></u3><u8 name="type">summer<field13 name="Enter offset for input (default=0.0) 1" /><field14 name="Enter offset for input (default=0.0) 2" /><field15 name="Enter gain for input(default=1.0) 1" /><field16 name="Enter gain for input(default=1.0) 2" /><field17 name="Enter gain for output (default=1.0)" /><field18 name="Enter offset for output (default=0.0)" /></u8><u4 name="type">summer<field19 name="Enter offset for input (default=0.0) 1" /><field20 name="Enter offset for input (default=0.0) 2" /><field21 name="Enter gain for input(default=1.0) 1" /><field22 name="Enter gain for input(default=1.0) 2" /><field23 name="Enter gain for output (default=1.0)" /><field24 name="Enter offset for output (default=0.0)" /></u4><u5 name="type">summer<field25 name="Enter offset for input (default=0.0) 1" /><field26 name="Enter offset for input (default=0.0) 2" /><field27 name="Enter gain for input(default=1.0) 1" /><field28 name="Enter gain for input(default=1.0) 2" /><field29 name="Enter gain for output (default=1.0)" /><field30 name="Enter offset for output (default=0.0)" /></u5><u9 name="type">summer<field31 name="Enter offset for input (default=0.0) 1" /><field32 name="Enter offset for input (default=0.0) 2" /><field33 name="Enter gain for input(default=1.0) 1" /><field34 name="Enter gain for input(default=1.0) 2" /><field35 name="Enter gain for output (default=1.0)" /><field36 name="Enter offset for output (default=0.0)" /></u9><u10 name="type">summer<field37 name="Enter offset for input (default=0.0) 1" /><field38 name="Enter offset for input (default=0.0) 2" /><field39 name="Enter gain for input(default=1.0) 1" /><field40 name="Enter gain for input(default=1.0) 2" /><field41 name="Enter gain for output (default=1.0)" /><field42 name="Enter offset for output (default=0.0)" /></u10><u6 name="type">summer<field43 name="Enter offset for input (default=0.0) 1" /><field44 name="Enter offset for input (default=0.0) 2" /><field45 name="Enter gain for input(default=1.0) 1" /><field46 name="Enter gain for input(default=1.0) 2" /><field47 name="Enter gain for output (default=1.0)" /><field48 name="Enter offset for output (default=0.0)" /></u6><u7 name="type">summer<field49 name="Enter offset for input (default=0.0) 1" /><field50 name="Enter offset for input (default=0.0) 2" /><field51 name="Enter gain for input(default=1.0) 1" /><field52 name="Enter gain for input(default=1.0) 2" /><field53 name="Enter gain for output (default=1.0)" /><field54 name="Enter offset for output (default=0.0)" /></u7><u11 name="type">summer<field61 name="Enter offset for input (default=0.0) 1" /><field62 name="Enter offset for input (default=0.0) 2" /><field63 name="Enter gain for input(default=1.0) 1" /><field64 name="Enter gain for input(default=1.0) 2" /><field65 name="Enter gain for output (default=1.0)" /><field66 name="Enter offset for output (default=0.0)" /></u11></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/10bitDAC/analysis b/library/SubcircuitLibrary/10bitDAC/analysis new file mode 100644 index 00000000..14b93089 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/analysis @@ -0,0 +1 @@ +.tran 1e-03 10e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator-cache.lib b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator-cache.lib new file mode 100644 index 00000000..3b31c94c --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir new file mode 100644 index 00000000..3abc6d22 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir @@ -0,0 +1,14 @@ +* /home/sumanto/eSim-2.1/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jan 12 16:16:30 2022 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 Net-_R3-Pad1_ GND 1k +C2 Net-_C2-Pad1_ GND 0.01u +X1 GND Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_U1-Pad1_ Net-_C2-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ LM555N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_U1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir.out b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir.out new file mode 100644 index 00000000..3ca86ff5 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir.out @@ -0,0 +1,16 @@ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/clock_pulse_generator/clock_pulse_generator.cir + +.include lm555n.sub +r3 net-_r3-pad1_ gnd 1k +c2 net-_c2-pad1_ gnd 0.01u +x1 gnd net-_u1-pad3_ net-_r3-pad1_ net-_u1-pad1_ net-_c2-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ lm555n +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_r3-pad1_ port +.tran 1e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.pro b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sch b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sch new file mode 100644 index 00000000..55c5c45f --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sch @@ -0,0 +1,206 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:Clock_pulse_generator-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 61DEABA3 +P 6950 4150 +F 0 "R3" H 7000 4280 50 0000 C CNN +F 1 "1k" H 7000 4100 50 0000 C CNN +F 2 "" H 7000 4130 30 0000 C CNN +F 3 "" V 7000 4200 30 0000 C CNN + 1 6950 4150 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C2 +U 1 1 61DEABA9 +P 4850 4600 +F 0 "C2" H 4875 4700 50 0000 L CNN +F 1 "0.01u" H 4875 4500 50 0000 L CNN +F 2 "" H 4888 4450 30 0000 C CNN +F 3 "" H 4850 4600 60 0000 C CNN + 1 4850 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 61DEABAA +P 5650 4950 +F 0 "#PWR1" H 5650 4700 50 0001 C CNN +F 1 "GND" H 5650 4800 50 0000 C CNN +F 2 "" H 5650 4950 50 0001 C CNN +F 3 "" H 5650 4950 50 0001 C CNN + 1 5650 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 4000 6500 4000 +Wire Wire Line + 6500 4000 6500 3350 +Wire Wire Line + 6500 3350 4500 3350 +Wire Wire Line + 4500 3350 4500 3800 +Wire Wire Line + 4500 3800 4250 3800 +Wire Wire Line + 5100 4250 4650 4250 +Wire Wire Line + 4650 4250 4650 3100 +Wire Wire Line + 3400 3100 5650 3100 +Wire Wire Line + 5650 3100 5650 3400 +Connection ~ 4650 3100 +Wire Wire Line + 6200 4250 6450 4250 +Wire Wire Line + 6450 4250 6450 5200 +Wire Wire Line + 6450 5200 4550 5200 +Wire Wire Line + 4550 5200 4550 3750 +Wire Wire Line + 4550 3750 5100 3750 +Connection ~ 4550 4350 +Wire Wire Line + 4850 4450 4850 4000 +Wire Wire Line + 4850 4000 5100 4000 +Wire Wire Line + 4850 4850 7000 4850 +Wire Wire Line + 5650 4600 5650 4950 +Wire Wire Line + 6200 3750 7000 3750 +Wire Wire Line + 7000 3750 7000 4050 +Wire Wire Line + 7000 4850 7000 4350 +Connection ~ 5650 4850 +$Comp +L LM555N X1 +U 1 1 61DEABAD +P 5650 4000 +F 0 "X1" H 5650 3950 60 0000 C CNN +F 1 "LM555N" H 5650 4100 60 0000 C CNN +F 2 "" H 5600 4000 60 0000 C CNN +F 3 "" H 5600 4000 60 0000 C CNN + 1 5650 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 4350 4250 4350 +$Comp +L PORT U1 +U 1 1 61DEAE73 +P 3150 3100 +F 0 "U1" H 3200 3200 30 0000 C CNN +F 1 "PORT" H 3150 3100 30 0000 C CNN +F 2 "" H 3150 3100 60 0000 C CNN +F 3 "" H 3150 3100 60 0000 C CNN + 1 3150 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 4850 4850 4750 +$Comp +L PORT U1 +U 2 1 61DEB4B4 +P 4000 3800 +F 0 "U1" H 4050 3900 30 0000 C CNN +F 1 "PORT" H 4000 3800 30 0000 C CNN +F 2 "" H 4000 3800 60 0000 C CNN +F 3 "" H 4000 3800 60 0000 C CNN + 2 4000 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 61DEB51D +P 4000 4350 +F 0 "U1" H 4050 4450 30 0000 C CNN +F 1 "PORT" H 4000 4350 30 0000 C CNN +F 2 "" H 4000 4350 60 0000 C CNN +F 3 "" H 4000 4350 60 0000 C CNN + 3 4000 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 61DEB688 +P 7250 3750 +F 0 "U1" H 7300 3850 30 0000 C CNN +F 1 "PORT" H 7250 3750 30 0000 C CNN +F 2 "" H 7250 3750 60 0000 C CNN +F 3 "" H 7250 3750 60 0000 C CNN + 4 7250 3750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 61DEB2E9 +P 4100 4500 +F 0 "U1" H 4150 4600 30 0000 C CNN +F 1 "PORT" H 4100 4500 30 0000 C CNN +F 2 "" H 4100 4500 60 0000 C CNN +F 3 "" H 4100 4500 60 0000 C CNN + 5 4100 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4500 4550 4500 +Connection ~ 4550 4500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sub b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sub new file mode 100644 index 00000000..6c5c8a10 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sub @@ -0,0 +1,11 @@ +* Subcircuit Clock_pulse_generator +.include lm555n.sub + +.subckt Clock_pulse_generator net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_r3-pad1_ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/clock_pulse_generator/clock_pulse_generator.cir +r3 net-_r3-pad1_ gnd 1k +c2 net-_c2-pad1_ gnd 0.01u +x1 gnd net-_u1-pad3_ net-_r3-pad1_ net-_u1-pad1_ net-_c2-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ lm555n +* Control Statements + +.ends Clock_pulse_generator
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator_Previous_Values.xml b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator_Previous_Values.xml new file mode 100644 index 00000000..2f8011a8 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>/home/sumanto/eSim-2.1/library/SubcircuitLibrary/lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/NPN.lib b/library/SubcircuitLibrary/Clock_pulse_generator/NPN.lib new file mode 100755 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/analysis b/library/SubcircuitLibrary/Clock_pulse_generator/analysis new file mode 100644 index 00000000..f496aec4 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/analysis @@ -0,0 +1 @@ +.tran 1e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-cache.lib b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-cache.lib new file mode 100755 index 00000000..824af11e --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-cache.lib @@ -0,0 +1,205 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND-RESCUE-lm555n +# +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R-RESCUE-lm555n +# +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-rescue.lib b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-rescue.lib new file mode 100755 index 00000000..fffeca36 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-rescue.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir new file mode 100755 index 00000000..682d4945 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir @@ -0,0 +1,31 @@ +* /home/ash98/Downloads/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +E2 Net-_E2-Pad1_ GND /c /d 10000 +U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad3_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 +U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit +U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit +U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir.out b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir.out new file mode 100755 index 00000000..a81070a1 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir.out @@ -0,0 +1,42 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +.include npn_1.lib +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.pro b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.pro new file mode 100755 index 00000000..662ea66d --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.pro @@ -0,0 +1,44 @@ +update=Wed Mar 18 14:16:41 2020 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=lm555n-rescue +LibName2=power +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=microcontrollers +LibName12=dsp +LibName13=microchip +LibName14=analog_switches +LibName15=motorola +LibName16=texas +LibName17=intel +LibName18=audio +LibName19=interface +LibName20=digital-audio +LibName21=philips +LibName22=display +LibName23=cypress +LibName24=siliconi +LibName25=opto +LibName26=atmel +LibName27=contrib +LibName28=valves +LibName29=eSim_User +LibName30=eSim_Subckt +LibName31=eSim_Sources +LibName32=eSim_Power +LibName33=eSim_Plot +LibName34=eSim_Miscellaneous +LibName35=eSim_Hybrid +LibName36=eSim_Digital +LibName37=eSim_Devices +LibName38=eSim_Analog diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sch b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sch new file mode 100755 index 00000000..28110b13 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sch @@ -0,0 +1,518 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3700 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 2650 3000 2850 3000 +Wire Wire Line + 2650 4750 2650 4650 +Connection ~ 2350 3550 +Connection ~ 2350 4900 +Wire Wire Line + 2350 4100 2350 4200 +Wire Wire Line + 9100 4900 9100 4800 +Wire Wire Line + 8500 4600 8500 4250 +Wire Wire Line + 3350 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 3750 +Wire Wire Line + 3500 4350 3500 4500 +Wire Wire Line + 3650 3550 4200 3550 +Wire Wire Line + 3850 3250 4200 3250 +Wire Wire Line + 3150 3550 3150 3700 +Wire Wire Line + 3150 3700 3500 3700 +Wire Wire Line + 3500 3700 3500 3750 +Connection ~ 3500 4450 +Wire Wire Line + 3700 4450 3700 4400 +Wire Wire Line + 3050 4350 3050 4450 +Wire Wire Line + 3050 4450 3700 4450 +Wire Wire Line + 9100 4250 9000 4250 +Wire Wire Line + 9100 4400 9100 4350 +Wire Wire Line + 9100 4350 9200 4350 +Wire Wire Line + 10100 2950 10350 2950 +Wire Wire Line + 2350 4900 2350 4700 +Wire Wire Line + 2350 3500 2350 3600 +Wire Wire Line + 2250 3000 2350 3000 +Wire Wire Line + 2350 4150 2650 4150 +Connection ~ 2350 4150 +Wire Wire Line + 2250 3550 2650 3550 +Wire Wire Line + 2650 3550 2650 3500 +Wire Wire Line + 4300 4750 4300 4650 +Text Label 2800 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 3000 4050 +F 0 "E2" H 2800 4150 50 0000 C CNN +F 1 "10000" H 2800 4000 50 0000 C CNN +F 2 "" H 3000 4050 60 0001 C CNN +F 3 "" H 3000 4050 60 0001 C CNN + 1 3000 4050 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 3700 4400 +F 0 "#FLG01" H 3700 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 3700 4630 30 0000 C CNN +F 2 "" H 3700 4400 60 0001 C CNN +F 3 "" H 3700 4400 60 0001 C CNN + 1 3700 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 2000 3550 +F 0 "U1" H 2000 3500 30 0000 C CNN +F 1 "PORT" H 2000 3550 30 0000 C CNN +F 2 "" H 2000 3550 60 0001 C CNN +F 3 "" H 2000 3550 60 0001 C CNN + 5 2000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 2000 4900 +F 0 "U1" H 2000 4850 30 0000 C CNN +F 1 "PORT" H 2000 4900 30 0000 C CNN +F 2 "" H 2000 4900 60 0001 C CNN +F 3 "" H 2000 4900 60 0001 C CNN + 1 2000 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 2650 5000 +F 0 "U1" H 2650 4950 30 0000 C CNN +F 1 "PORT" H 2650 5000 30 0000 C CNN +F 2 "" H 2650 5000 60 0001 C CNN +F 3 "" H 2650 5000 60 0001 C CNN + 2 2650 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 4300 5000 +F 0 "U1" H 4300 4950 30 0000 C CNN +F 1 "PORT" H 4300 5000 30 0000 C CNN +F 2 "" H 4300 5000 60 0001 C CNN +F 3 "" H 4300 5000 60 0001 C CNN + 4 4300 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 9450 4350 +F 0 "U1" H 9450 4300 30 0000 C CNN +F 1 "PORT" H 9450 4350 30 0000 C CNN +F 2 "" H 9450 4350 60 0001 C CNN +F 3 "" H 9450 4350 60 0001 C CNN + 7 9450 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 10600 2950 +F 0 "U1" H 10600 2900 30 0000 C CNN +F 1 "PORT" H 10600 2950 30 0000 C CNN +F 2 "" H 10600 2950 60 0001 C CNN +F 3 "" H 10600 2950 60 0001 C CNN + 3 10600 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 3100 3000 +F 0 "U1" H 3100 2950 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0001 C CNN +F 3 "" H 3100 3000 60 0001 C CNN + 6 3100 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 2000 3000 +F 0 "U1" H 2000 2950 30 0000 C CNN +F 1 "PORT" H 2000 3000 30 0000 C CNN +F 2 "" H 2000 3000 60 0001 C CNN +F 3 "" H 2000 3000 60 0001 C CNN + 8 2000 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 8750 4250 +F 0 "R8" V 8830 4250 50 0000 C CNN +F 1 "1500" V 8750 4250 50 0000 C CNN +F 2 "" H 8750 4250 60 0001 C CNN +F 3 "" H 8750 4250 60 0001 C CNN + 1 8750 4250 + 0 1 1 0 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 3500 4500 +F 0 "#PWR02" H 3500 4500 30 0001 C CNN +F 1 "GND" H 3500 4430 30 0001 C CNN +F 2 "" H 3500 4500 60 0001 C CNN +F 3 "" H 3500 4500 60 0001 C CNN + 1 3500 4500 + 1 0 0 -1 +$EndComp +Text Label 2800 4000 0 60 ~ 0 +c +Text Label 2650 4650 0 60 ~ 0 +d +Text Label 2650 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 3600 3250 +F 0 "R7" V 3680 3250 50 0000 C CNN +F 1 "25" V 3600 3250 50 0000 C CNN +F 2 "" H 3600 3250 60 0001 C CNN +F 3 "" H 3600 3250 60 0001 C CNN + 1 3600 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 3400 3550 +F 0 "R6" V 3480 3550 50 0000 C CNN +F 1 "25" V 3400 3550 50 0000 C CNN +F 2 "" H 3400 3550 60 0001 C CNN +F 3 "" H 3400 3550 60 0001 C CNN + 1 3400 3550 + 0 -1 -1 0 +$EndComp +Text Label 3250 4000 0 60 ~ 0 +b +Text Label 3250 4100 0 60 ~ 0 +a +Text Label 2650 3000 0 60 ~ 0 +b +Text Label 2650 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 3450 4050 +F 0 "E1" H 3250 4150 50 0000 C CNN +F 1 "10000" H 3250 4000 50 0000 C CNN +F 2 "" H 3450 4050 60 0001 C CNN +F 3 "" H 3450 4050 60 0001 C CNN + 1 3450 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 2650 3250 +F 0 "R4" V 2730 3250 50 0000 C CNN +F 1 "2E6" V 2650 3250 50 0000 C CNN +F 2 "" H 2650 3250 60 0001 C CNN +F 3 "" H 2650 3250 60 0001 C CNN + 1 2650 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 2650 4400 +F 0 "R5" V 2730 4400 50 0000 C CNN +F 1 "2E6" V 2650 4400 50 0000 C CNN +F 2 "" H 2650 4400 60 0001 C CNN +F 3 "" H 2650 4400 60 0001 C CNN + 1 2650 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 2350 4450 +F 0 "R3" V 2430 4450 50 0000 C CNN +F 1 "5000" V 2350 4450 50 0000 C CNN +F 2 "" H 2350 4450 60 0001 C CNN +F 3 "" H 2350 4450 60 0001 C CNN + 1 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 2350 3850 +F 0 "R2" V 2430 3850 50 0000 C CNN +F 1 "5000" V 2350 3850 50 0000 C CNN +F 2 "" H 2350 3850 60 0001 C CNN +F 3 "" H 2350 3850 60 0001 C CNN + 1 2350 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 2350 3250 +F 0 "R1" V 2430 3250 50 0000 C CNN +F 1 "5000" V 2350 3250 50 0000 C CNN +F 2 "" H 2350 3250 60 0001 C CNN +F 3 "" H 2350 3250 60 0001 C CNN + 1 2350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_srlatch U8 +U 1 1 5E01E563 +P 8000 3350 +F 0 "U8" H 8000 3350 60 0000 C CNN +F 1 "d_srlatch" H 8050 3500 60 0000 C CNN +F 2 "" H 8000 3350 60 0000 C CNN +F 3 "" H 8000 3350 60 0000 C CNN + 1 8000 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5E01F10F +P 7450 4400 +F 0 "U7" H 7450 4300 60 0000 C CNN +F 1 "d_inverter" H 7450 4550 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 4400 8150 4400 +Wire Wire Line + 8000 4400 8000 4150 +$Comp +L adc_bridge_1 U5 +U 1 1 5E01F2C7 +P 6350 3400 +F 0 "U5" H 6350 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 1 6350 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3350 7200 3350 +Wire Wire Line + 4300 4650 5600 4650 +Wire Wire Line + 5600 4650 5600 3350 +Wire Wire Line + 5600 3350 5750 3350 +$Comp +L adc_bridge_1 U4 +U 1 1 5E01F3F2 +P 6350 3000 +F 0 "U4" H 6350 3000 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN +F 2 "" H 6350 3000 60 0000 C CNN +F 3 "" H 6350 3000 60 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U6 +U 1 1 5E01F469 +P 6350 3850 +F 0 "U6" H 6350 3850 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN +F 2 "" H 6350 3850 60 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3800 7200 3800 +Wire Wire Line + 7200 2950 6900 2950 +$Comp +L limit U3 +U 1 1 5E01F5DC +P 4900 2950 +F 0 "U3" H 4950 2900 60 0000 C CNN +F 1 "limit" H 4950 3000 60 0000 C CNN +F 2 "" H 4900 3000 60 0000 C CNN +F 3 "" H 4900 3000 60 0000 C CNN + 1 4900 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2950 5750 2950 +Wire Wire Line + 4200 3250 4200 2950 +Wire Wire Line + 4200 2950 4500 2950 +$Comp +L limit U2 +U 1 1 5E01F79D +P 4800 3800 +F 0 "U2" H 4850 3750 60 0000 C CNN +F 1 "limit" H 4850 3850 60 0000 C CNN +F 2 "" H 4800 3850 60 0000 C CNN +F 3 "" H 4800 3850 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3800 5750 3800 +Wire Wire Line + 4200 3550 4200 3800 +Wire Wire Line + 4200 3800 4400 3800 +Wire Wire Line + 7050 3350 7050 4400 +Wire Wire Line + 7050 4400 7150 4400 +Connection ~ 7050 3350 +Wire Wire Line + 8000 2600 8150 2600 +Wire Wire Line + 8150 2600 8150 4400 +Connection ~ 8000 4400 +$Comp +L dac_bridge_1 U9 +U 1 1 5E01FCD2 +P 9550 3000 +F 0 "U9" H 9550 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN +F 2 "" H 9550 3000 60 0000 C CNN +F 3 "" H 9550 3000 60 0000 C CNN + 1 9550 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2950 8950 2950 +$Comp +L dac_bridge_1 U10 +U 1 1 5E01FE8E +P 9600 3850 +F 0 "U10" H 9600 3850 60 0000 C CNN +F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN +F 2 "" H 9600 3850 60 0000 C CNN +F 3 "" H 9600 3850 60 0000 C CNN + 1 9600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3800 8800 3800 +Wire Wire Line + 9100 4000 9100 4250 +Wire Wire Line + 9100 4000 10300 4000 +Wire Wire Line + 10300 4000 10300 3800 +Wire Wire Line + 10300 3800 10150 3800 +$Comp +L eSim_NPN Q1 +U 1 1 5E01E782 +P 9000 4600 +F 0 "Q1" H 8900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN +F 2 "" H 9200 4700 29 0000 C CNN +F 3 "" H 9000 4600 60 0000 C CNN + 1 9000 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 4600 8500 4600 +Wire Wire Line + 2250 4900 9100 4900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sub b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sub new file mode 100755 index 00000000..b524f5c6 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sub @@ -0,0 +1,39 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements + +.ends lm555n diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n_Previous_Values.xml b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n_Previous_Values.xml new file mode 100755 index 00000000..58d33ec5 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/npn_1.lib b/library/SubcircuitLibrary/Clock_pulse_generator/npn_1.lib new file mode 100755 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/browser/welcome.html b/library/browser/welcome.html index c438194e..8a93a730 100644 --- a/library/browser/welcome.html +++ b/library/browser/welcome.html @@ -39,15 +39,15 @@ <center><img src="../../images/logo.png" alt="eSim logo" height="100" width="100"></center> <br/> <p> - <b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source softwares such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>), Ngspice (<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>) and GHDL (<a href=http://ghdl.free.fr>http://ghdl.free.fr</a>). eSim source is released under <b>GNU General Public License.</b> + <b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source softwares such as KiCad (<a href="https://www.kicad.org">https://www.kicad.org/</a>), Makerchip IDE (<a href="https://www.makerchip.com/">https://www.makerchip.com/</a>), Ngspice (<a href="http://ngspice.sourceforge.net">http://ngspice.sourceforge.net</a>), GHDL (<a href="http://ghdl.free.fr">http://ghdl.free.fr</a>) and Verilator (<a href="https://www.veripool.org/verilator/">https://www.veripool.org/verilator/</a>). eSim source is released under <b>GNU General Public License.</b> </p> <br/> <p> - This tool is developed by the <b>FOSSEE team at IIT Bombay</b>. To know more about eSim, please visit: <a href=http://esim.fossee.in>http://esim.fossee.in</a>. + This tool is developed by the <b>FOSSEE team at IIT Bombay</b>. To know more about eSim, please visit: <a href="https://esim.fossee.in">https://esim.fossee.in</a>. </p> <br/> <p> - To discuss more about eSim, please visit: <a href=http://forums.fossee.in>http://forums.fossee.in</a> + To discuss more about eSim, please visit: <a href="https://forums.fossee.in">https://forums.fossee.in</a> </p> <br/> </body> diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Ngveri.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Ngveri.lib new file mode 100644 index 00000000..1f3f0695 --- /dev/null +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Ngveri.lib @@ -0,0 +1,3 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 + diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index cc4c57db..ce0c8f05 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -1,6 +1,45 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# # 2BITMUL # DEF 2BITMUL X 0 40 Y Y 1 F N diff --git a/library/kicadLibrary/template/kicad.pro b/library/kicadLibrary/template/kicad.pro index 0d4f13cb..d7f78c3b 100644 --- a/library/kicadLibrary/template/kicad.pro +++ b/library/kicadLibrary/template/kicad.pro @@ -68,3 +68,4 @@ LibName34=eSim_Power LibName35=eSim_Sources LibName36=eSim_Subckt LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/modelParamXML/Ngveri/.gitignore b/library/modelParamXML/Ngveri/.gitignore new file mode 100644 index 00000000..86d0cb27 --- /dev/null +++ b/library/modelParamXML/Ngveri/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore
\ No newline at end of file diff --git a/library/tlv/clk_gate.v b/library/tlv/clk_gate.v new file mode 100755 index 00000000..77e9186d --- /dev/null +++ b/library/tlv/clk_gate.v @@ -0,0 +1,40 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +`include "sp_default.vh" +/* verilator lint_off LATCH */ + +// Clock gate module used by SandPiper default project. + +module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override); + wire clk_en; + reg latched_clk_en /*verilator clock_enable*/; + assign clk_en = func_en & (pwr_en | gating_override); + `TLV_BLATCH(latched_clk_en, clk_en, free_clk) + assign gated_clk = latched_clk_en & free_clk; +endmodule + diff --git a/library/tlv/lint_off.txt b/library/tlv/lint_off.txt new file mode 100755 index 00000000..e659e188 --- /dev/null +++ b/library/tlv/lint_off.txt @@ -0,0 +1,30 @@ +UNUSED +DECLFILENAME +BLKSEQ +WIDTH +SELRANGE +PINCONNECTEMPTY +DEFPARAM +IMPLICIT +COMBDLY +SYNCASYNCNET +UNOPTFLAT +UNSIGNED +CASEINCOMPLETE +UNDRIVEN +VARHIDDEN +CASEX +CASEOVERLAP +PINMISSING +LATCH +BLKANDNBLK +MULTIDRIVEN +NULLPORT +EOFNEWLINE +WIDTHCONCAT +ASSIGNDLY +MODDUP +STMTDLY +LITENDIAN +INITIALDLY + diff --git a/library/tlv/pseudo_rand.m4out.tlv b/library/tlv/pseudo_rand.m4out.tlv new file mode 100755 index 00000000..cb0d6149 --- /dev/null +++ b/library/tlv/pseudo_rand.m4out.tlv @@ -0,0 +1,69 @@ +\m4_TLV_version 1b: tl-x.org +\SV +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module pseudo_rand + #(parameter WIDTH=257) // Random vector width, to a max of 257. + (input logic clk, + input logic reset, + output logic [WIDTH-1:0] rand_vect + ); + +// Currently, this implements a Galois LFSR. +// TODO: It should be XORed with something else so it doesn't just shift. +// Using polynomials with maximal number of taps would have less regular shifting behavior. + +// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. + +// Choose optimal parameters for given WIDTH. +localparam LFSR_WIDTH = + (WIDTH <= 64) ? 64 : + (WIDTH <= 128) ? 128 : + (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. +// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf +localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, + (LFSR_WIDTH == 64) ? 8'b00011011 : + (LFSR_WIDTH == 128) ? 8'b10000111 : + (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; + +bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; + + + +\TLV + |default + @0 + $reset = reset; + @1 + $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY); + @2 + *rand_vect = $lfsr[WIDTH-1:0]; + +\SV + +endmodule diff --git a/library/tlv/pseudo_rand.sv b/library/tlv/pseudo_rand.sv new file mode 100755 index 00000000..a9988b58 --- /dev/null +++ b/library/tlv/pseudo_rand.sv @@ -0,0 +1,70 @@ +`line 2 "pseudo_rand.m4out.tlv" 0 //_\TLV_version 1b: tl-x.org, generated by SandPiper(TM) 1.11-2021/01/28-beta +`include "sp_default.vh" //_\SV +/* +Copyright (c) 2014, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +module pseudo_rand + #(parameter WIDTH=257) // Random vector width, to a max of 257. + (input logic clk, + input logic reset, + output logic [WIDTH-1:0] rand_vect + ); + +// Currently, this implements a Galois LFSR. +// TODO: It should be XORed with something else so it doesn't just shift. +// Using polynomials with maximal number of taps would have less regular shifting behavior. + +// Bits are numbered in the reverse of the traditional order. This puts the taps in the lower bit positions. + +// Choose optimal parameters for given WIDTH. +localparam LFSR_WIDTH = + (WIDTH <= 64) ? 64 : + (WIDTH <= 128) ? 128 : + (WIDTH <= 257) ? 257 : 0; // 257 enables a large non-power of two for replication on an irregular boundary. +// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf +localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}}, + (LFSR_WIDTH == 64) ? 8'b00011011 : + (LFSR_WIDTH == 128) ? 8'b10000111 : + (LFSR_WIDTH == 257) ? 8'b11000101 : 8'b0}; + +bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a; + + + +`include "pseudo_rand_gen.sv" //_\TLV + //_|default + //_@0 + assign DEFAULT_reset_a0 = reset; + //_@1 + assign DEFAULT_lfsr_a1[LFSR_WIDTH-1:0] = DEFAULT_reset_a1 ? SEED : {DEFAULT_lfsr_a2[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{DEFAULT_lfsr_a2[LFSR_WIDTH-1]}} & LFSR_POLY); + //_@2 + assign rand_vect = DEFAULT_lfsr_a2[WIDTH-1:0]; endgenerate + +//_\SV + +endmodule + diff --git a/library/tlv/pseudo_rand_gen.sv b/library/tlv/pseudo_rand_gen.sv new file mode 100755 index 00000000..ec008179 --- /dev/null +++ b/library/tlv/pseudo_rand_gen.sv @@ -0,0 +1,46 @@ +// Generated by SandPiper(TM) 1.11-2021/01/28-beta from Redwood EDA. +// Redwood EDA does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality. + + +`include "sandpiper_gen.vh" + + + + + +// +// Signals declared top-level. +// + +// For |default$lfsr. +logic [LFSR_WIDTH-1:0] DEFAULT_lfsr_a1, + DEFAULT_lfsr_a2; + +// For |default$reset. +logic DEFAULT_reset_a0, + DEFAULT_reset_a1; + + + +generate + + + // + // Scope: |default + // + + // For $lfsr. + always_ff @(posedge clk) DEFAULT_lfsr_a2[LFSR_WIDTH-1:0] <= DEFAULT_lfsr_a1[LFSR_WIDTH-1:0]; + + // For $reset. + always_ff @(posedge clk) DEFAULT_reset_a1 <= DEFAULT_reset_a0; + + + + +endgenerate + + + + +generate // This is awkward, but we need to go into 'generate' context in the line that `includes the declarations file. diff --git a/library/tlv/sandpiper.vh b/library/tlv/sandpiper.vh new file mode 100755 index 00000000..ccba8b0e --- /dev/null +++ b/library/tlv/sandpiper.vh @@ -0,0 +1,72 @@ +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +// Project-independent SandPiper header file. + +`ifndef SANDPIPER_VH +`define SANDPIPER_VH + + +// Note, these have no SP prefix, so collisions are possible. + + +`ifdef WHEN + // Make sure user definition does not collide. + !!!ERROR: WHEN macro already defined +`else + `ifdef SP_PHYS + // Phys compilation disabled X-injection. + `define WHEN(valid_sig) + `else + // Inject X. + `define WHEN(valid_sig) !valid_sig ? 'x : + `endif +`endif + + +// SandPiper does not generate set/reset flops. Reset is implemented as combinational +// logic, and it is up to synthesis to infer set/reset flops when possible. +//`ifdef RESET +// // Make sure user definition does not collide. +// !!!ERROR: RESET macro already defined +//`else +// `define RESET(i, reset) ((reset) ? '0 : i) +//`endif +// +//`ifdef SET +// // Make sure user definition does not collide. +// !!!ERROR: SET macro already defined +//`else +// `define SET(i, set) ((set) ? '1 : i) +//`endif + +// Since SandPiper required use of all signals, this is useful to create a +// bogus use and keep SandPiper happy when a signal, by intent, has no uses. +`define BOGUS_USE(ignore) + +`endif // SANDPIPER_VH + diff --git a/library/tlv/sandpiper_gen.vh b/library/tlv/sandpiper_gen.vh new file mode 100755 index 00000000..d063661a --- /dev/null +++ b/library/tlv/sandpiper_gen.vh @@ -0,0 +1,4 @@ +// This just verifies that sandpiper.vh has been included. +`ifndef SANDPIPER_VH + !!!ERROR: SandPiper project's sp_<proj>.vh file must include sandpiper.vh. +`endif diff --git a/library/tlv/sp_default.vh b/library/tlv/sp_default.vh new file mode 100755 index 00000000..5e74259a --- /dev/null +++ b/library/tlv/sp_default.vh @@ -0,0 +1,66 @@ +`ifndef SP_DEFAULT +`define SP_DEFAULT +/* +Copyright (c) 2015, Steven F. Hoover + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * The name of Steven F. Hoover + may not be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +// File included by SandPiper-generated code for the default project configuration. +`include "sandpiper.vh" + + +// Latch macros. Inject 'x in simulation for clk === 'x. + +// A-phase latch. +`ifdef SP_PHYS +`define TLV_LATCH(in, out, clk) \ +always @ (in, clk) begin \ + if (clk === 1'b1) \ + out <= in; \ + else if (clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in; +`endif // SP_PHYS + +// B-phase latch. +`ifdef SP_PHYS +`define TLV_BLATCH(out, in, clk) \ +always @ (in, clk) begin \ + if (!clk === 1'b1) \ + out <= in; \ + else if (!clk === 1'bx) \ + out <= 'x; \ +end +`else +`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in; +`endif // SP_PHYS + + + +`endif // SP_DEFAULT + @@ -9,7 +9,7 @@ Needed to define the module structure, look up `Modules` for python ''' setup( name='eSim', - version='2.1.0', + version='2.2.0', author='FOSSEE', author_email='contact-esim@fossee.in', package_dir={'': 'src'}, diff --git a/src/browser/UserManual.py b/src/browser/UserManual.py index e723680a..bf9c4b2b 100644 --- a/src/browser/UserManual.py +++ b/src/browser/UserManual.py @@ -14,7 +14,7 @@ class UserManual(QtWidgets.QWidget): self.vlayout = QtWidgets.QVBoxLayout() - manual = 'library/browser/User-Manual/eSim_Manual_2.1.pdf' + manual = 'library/browser/User-Manual/eSim_Manual_2.2.pdf' if os.name == 'nt': os.startfile(os.path.realpath(manual)) diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py index d0b4fd18..ab19ada5 100644 --- a/src/configuration/Appconfig.py +++ b/src/configuration/Appconfig.py @@ -34,9 +34,14 @@ class Appconfig(QtWidgets.QWidget): """ # Home directory + if os.name == 'nt': + user_home = os.path.join('library', 'config') + else: + user_home = os.path.expanduser('~') + try: file = open(os.path.join( - os.path.expanduser("~"), ".esim/workspace.txt"), 'r' + user_home, ".esim/workspace.txt"), 'r' ) workspace_check, home = file.readline().split(' ', 1) file.close() @@ -65,11 +70,8 @@ class Appconfig(QtWidgets.QWidget): parser_esim = ConfigParser() parser_esim.read( - os.path.join( - os.path.expanduser("~"), - os.path.join( - '.esim', - 'config.ini'))) + os.path.join(user_home, '.esim', 'config.ini') + ) # Try catch added, since eSim cannot be accessed under parser for Win10 try: @@ -103,9 +105,9 @@ class Appconfig(QtWidgets.QWidget): # Application Details self._APPLICATION = 'eSim' - self._VERSION = '2.1' + self._VERSION = '2.2' self._AUTHOR = 'Fahim' - self._REVISION = 'Rahul' + self._REVISION = 'Rahul, Sumanto' # Application geometry setting self._app_xpos = 100 diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py index 94bce4ae..d3ef020f 100644 --- a/src/frontEnd/Application.py +++ b/src/frontEnd/Application.py @@ -11,14 +11,16 @@ # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com # MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in +# Sumanto Kar, sumantokar@iitb.ac.in # ORGANIZATION: eSim Team at FOSSEE, IIT Bombay # CREATED: Tuesday 24 February 2015 -# REVISION: Sunday 13 December 2020 +# REVISION: Monday 31 January 2022 # ========================================================================= import os +import traceback -if os.name == 'nt': # noqa +if os.name == 'nt': from frontEnd import pathmagic # noqa:F401 init_path = '' else: @@ -39,9 +41,11 @@ from PyQt5.Qt import QSize import shutil import time import sys - +import psutil # Its our main window of application. + + class Application(QtWidgets.QMainWindow): """This class initializes all objects used in this file.""" global project_name @@ -86,7 +90,7 @@ class Application(QtWidgets.QMainWindow): - Top-tool-bar (New project, Open project, Close project, \ Mode switch, Help option) - - Left-tool-bar (Open Schematic, Convert KiCad to NgSpice, \ + - Left-tool-bar (Open Schematic, Convert KiCad to Ngspice, \ Simuation, Model Editor, Subcircuit, NGHDL, Modelica \ Converter, OM Optimisation) """ @@ -183,13 +187,13 @@ class Application(QtWidgets.QMainWindow): self.conversion = QtWidgets.QAction( QtGui.QIcon(init_path + 'images/ki-ng.png'), - '<b>Convert Kicad to Ngspice</b>', self + '<b>Convert KiCad to Ngspice</b>', self ) self.conversion.triggered.connect(self.obj_kicad.openKicadToNgspice) self.ngspice = QtWidgets.QAction( QtGui.QIcon(init_path + 'images/ngspice.png'), - '<b>Simulation</b>', self + '<b>Simulate</b>', self ) self.ngspice.triggered.connect(self.open_ngspice) @@ -206,10 +210,16 @@ class Application(QtWidgets.QMainWindow): self.subcircuit.triggered.connect(self.open_subcircuit) self.nghdl = QtWidgets.QAction( - QtGui.QIcon(init_path + 'images/nghdl.png'), '<b>Nghdl</b>', self + QtGui.QIcon(init_path + 'images/nghdl.png'), '<b>NGHDL</b>', self ) self.nghdl.triggered.connect(self.open_nghdl) + self.makerchip = QtWidgets.QAction( + QtGui.QIcon(init_path + 'images/makerchip.png'), + '<b>Makerchip-NgVeri</b>', self + ) + self.makerchip.triggered.connect(self.open_makerchip) + self.omedit = QtWidgets.QAction( QtGui.QIcon(init_path + 'images/omedit.png'), '<b>Modelica Converter</b>', self @@ -230,6 +240,7 @@ class Application(QtWidgets.QMainWindow): self.lefttoolbar.addAction(self.ngspice) self.lefttoolbar.addAction(self.model) self.lefttoolbar.addAction(self.subcircuit) + self.lefttoolbar.addAction(self.makerchip) self.lefttoolbar.addAction(self.nghdl) self.lefttoolbar.addAction(self.omedit) self.lefttoolbar.addAction(self.omoptim) @@ -505,7 +516,7 @@ class Application(QtWidgets.QMainWindow): self.msg.setWindowTitle("Error Message") self.msg.setModal(True) self.msg.showMessage( - 'Please save and close all the Kicad ' + + 'Please save and close all the KiCad ' + 'windows first, then change the mode' ) self.msg.exec_() @@ -523,17 +534,67 @@ class Application(QtWidgets.QMainWindow): print("Current Project is : ", self.obj_appconfig.current_project) self.obj_Mainview.obj_dockarea.usermanual() + def checkIfProcessRunning(self, processName): + ''' + Check if there is any running process + that contains the given name processName. + ''' + # Iterate over the all the running process + for proc in psutil.process_iter(): + try: + # Check if process name contains the given name string. + if processName.lower() in proc.name().lower(): + return True + except (psutil.NoSuchProcess, + psutil.AccessDenied, psutil.ZombieProcess): + pass + return False + def open_ngspice(self): """This Function execute ngspice on current project.""" self.projDir = self.obj_appconfig.current_project["ProjectName"] if self.projDir is not None: - self.obj_Mainview.obj_dockarea.ngspiceEditor(self.projDir) + + # Edited by Sumanto Kar 25/08/2021 + if self.obj_Mainview.obj_dockarea.ngspiceEditor( + self.projDir) is False: + print( + "Netlist file (*.cir.out) not found." + ) + + self.msg = QtWidgets.QErrorMessage() + self.msg.setModal(True) + self.msg.setWindowTitle("Error Message") + self.msg.showMessage( + 'Netlist file (*.cir.out) not found.' + ) + self.msg.exec_() + return currTime = time.time() count = 0 while True: try: + # if os.name == 'nt': + # proc = 'mintty' + # else: + # proc = 'xterm' + + # Edited by Sumanto Kar 25/08/2021 + if os.name != 'nt' and \ + self.checkIfProcessRunning('xterm') is False: + self.msg = QtWidgets.QErrorMessage() + self.msg.setModal(True) + self.msg.setWindowTitle("Warning Message") + self.msg.showMessage( + 'Simulation was interrupted/failed. ' + 'Please close all the Ngspice windows ' + 'and then rerun the simulation.' + ) + self.msg.exec_() + return + st = os.stat(os.path.join(self.projDir, "plot_data_i.txt")) if st.st_mtime >= currTime: break @@ -546,7 +607,8 @@ class Application(QtWidgets.QMainWindow): if count >= 10: print( "Ngspice taking too long for simulation. " - "Check netlist file to change simulation parameters." + "Check netlist file (*.cir.out) " + "to change simulation parameters." ) self.msg = QtWidgets.QErrorMessage() @@ -554,7 +616,8 @@ class Application(QtWidgets.QMainWindow): self.msg.setWindowTitle("Warning Message") self.msg.showMessage( 'Ngspice taking too long for simulation. ' - 'Check netlist file to change simulation parameters.' + 'Check netlist file (*.cir.out) ' + 'to change simulation parameters.' ) self.msg.exec_() @@ -572,7 +635,7 @@ class Application(QtWidgets.QMainWindow): ' Please look at console for more details.' ) self.msg.exec_() - print("Exception Message:", str(e)) + print("Exception Message:", str(e), traceback.format_exc()) self.obj_appconfig.print_error('Exception Message : ' + str(e)) else: @@ -626,6 +689,20 @@ class Application(QtWidgets.QMainWindow): 'Please make sure it is installed') self.msg.exec_() + def open_makerchip(self): + """ + This function opens 'subcircuit' option in left-tool-bar. + When 'subcircuit' icon is clicked wich is present in + left-tool-bar of main page: + + - Meassge shown on screen "Subcircuit editor is called". + - 'subcircuiteditor()' function is called using object + 'obj_dockarea' of class 'Mainview'. + """ + print("Function : Makerchip and Verilator to Ngspice Converter") + self.obj_appconfig.print_info('Makerchip is called') + self.obj_Mainview.obj_dockarea.makerchip() + def open_modelEditor(self): """ This function opens model editor option in left-tool-bar. @@ -707,7 +784,7 @@ class Application(QtWidgets.QMainWindow): else: self.msg = QtWidgets.QErrorMessage() self.msg.setModal(True) - self.msg.setWindowTitle("Missing Ngspice netlist") + self.msg.setWindowTitle("Missing Ngspice Netlist") self.msg.showMessage( 'Current project does not contain any Ngspice file. ' + 'Please create Ngspice file with extension .cir.out' @@ -718,8 +795,8 @@ class Application(QtWidgets.QMainWindow): self.msg.setModal(True) self.msg.setWindowTitle("Error Message") self.msg.showMessage( - 'Please select the project first. ' + - 'You can either create a new project or open existing project' + 'Please select the project first. You can either ' + + 'create a new project or open an existing project' ) self.msg.exec_() @@ -850,9 +927,12 @@ def main(args): appView.obj_workspace.returnWhetherClickedOrNot(appView) try: - file = open(os.path.join( - os.path.expanduser("~"), ".esim/workspace.txt"), 'r' - ) + if os.name == 'nt': + user_home = os.path.join('library', 'config') + else: + user_home = os.path.expanduser('~') + + file = open(os.path.join(user_home, ".esim/workspace.txt"), 'r') work = int(file.read(1)) file.close() except IOError: diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py index b96c468a..461240b9 100644..100755 --- a/src/frontEnd/DockArea.py +++ b/src/frontEnd/DockArea.py @@ -4,6 +4,7 @@ from ngspiceSimulation.NgspiceWidget import NgspiceWidget from configuration.Appconfig import Appconfig from modelEditor.ModelEditor import ModelEditorclass from subcircuit.Subcircuit import Subcircuit +from maker.makerchip import makerchip from kicadtoNgspice.KicadtoNgspice import MainWindow from browser.Welcome import Welcome from browser.UserManual import UserManual @@ -123,6 +124,10 @@ class DockArea(QtWidgets.QMainWindow): self.ngspiceNetlist = os.path.join( self.projDir, self.projName + ".cir.out") + # Edited by Sumanto Kar 25/08/2021 + if os.path.isfile(self.ngspiceNetlist) is False: + return False + global count self.ngspiceWidget = QtWidgets.QWidget() @@ -254,6 +259,34 @@ class DockArea(QtWidgets.QMainWindow): count = count + 1 + def makerchip(self): + """This function creates a widget for different subcircuit options.""" + global count + self.makerWidget = QtWidgets.QWidget() + self.makerLayout = QtWidgets.QVBoxLayout() + self.makerLayout.addWidget(makerchip(self)) + + self.makerWidget.setLayout(self.makerLayout) + dock['Makerchip-' + + str(count)] = QtWidgets.QDockWidget('Makerchip-' + str(count)) + dock['Makerchip-' + str(count)].setWidget(self.makerWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, + dock['Makerchip-' + str(count)]) + self.tabifyDockWidget(dock['Welcome'], + dock['Makerchip-' + str(count)]) + + # CSS + dock['Makerchip-' + str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray;\ + padding: 5px; width: 200px; height: 150px; } \ + ") + + dock['Makerchip-' + str(count)].setVisible(True) + dock['Makerchip-' + str(count)].setFocus() + dock['Makerchip-' + str(count)].raise_() + + count = count + 1 + def usermanual(self): """This function creates a widget for user manual.""" global count diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py index 456276c8..456276c8 100644..100755 --- a/src/frontEnd/ProjectExplorer.py +++ b/src/frontEnd/ProjectExplorer.py diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py index 4d033539..fca73e39 100644..100755 --- a/src/frontEnd/Workspace.py +++ b/src/frontEnd/Workspace.py @@ -124,9 +124,13 @@ class Workspace(QtWidgets.QWidget): self.obj_appconfig.workspace_check = self.chkbox.checkState() print(self.workspace_loc.text()) - file = open(os.path.join( - os.path.expanduser("~"), ".esim/workspace.txt"), 'w' - ) + + if os.name == 'nt': + user_home = os.path.join('library', 'config') + else: + user_home = os.path.expanduser('~') + + file = open(os.path.join(user_home, ".esim/workspace.txt"), 'w') file.writelines( str(self.obj_appconfig.workspace_check) + " " + self.workspace_loc.text() diff --git a/src/frontEnd/__init__.py b/src/frontEnd/__init__.py index e69de29b..e69de29b 100644..100755 --- a/src/frontEnd/__init__.py +++ b/src/frontEnd/__init__.py diff --git a/src/frontEnd/pathmagic.py b/src/frontEnd/pathmagic.py index 5f0d712c..5f0d712c 100644..100755 --- a/src/frontEnd/pathmagic.py +++ b/src/frontEnd/pathmagic.py diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py index 93cf6a4e..28294be1 100644 --- a/src/kicadtoNgspice/KicadtoNgspice.py +++ b/src/kicadtoNgspice/KicadtoNgspice.py @@ -663,7 +663,7 @@ class MainWindow(QtWidgets.QWidget): print("=========================================================") self.createNetlistFile(store_schematicInfo, plotText) - self.msg = "The Kicad to Ngspice Conversion completed " + self.msg = "The KiCad to Ngspice conversion completed " self.msg += "successfully!" QtWidgets.QMessageBox.information( self, "Information", self.msg, QtWidgets.QMessageBox.Ok diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py index 494c49b4..94a2e51f 100644 --- a/src/kicadtoNgspice/Processing.py +++ b/src/kicadtoNgspice/Processing.py @@ -318,7 +318,7 @@ class PrcocessNetlist: for item in param: # print "Tags ",item.tag # print "Value",item.text - if 'vector'in item.attrib: + if 'vector' in item.attrib: # print "Tag having vector attribute",\ # item.tag,item.attrib['vector'] temp_count = 1 diff --git a/src/maker/Appconfig.py b/src/maker/Appconfig.py new file mode 100755 index 00000000..06758898 --- /dev/null +++ b/src/maker/Appconfig.py @@ -0,0 +1,39 @@ +import os.path +from configparser import ConfigParser + + +class Appconfig: + if os.name == 'nt': + home = os.path.join('library', 'config') + else: + home = os.path.expanduser('~') + + # Reading all variables from eSim config.ini + parser_esim = ConfigParser() + parser_esim.read(os.path.join(home, os.path.join('.esim', 'config.ini'))) + try: + src_home = parser_esim.get('eSim', 'eSim_HOME') + xml_loc = os.path.join(src_home, 'library/modelParamXML') + lib_loc = os.path.expanduser('~') + except BaseException: + pass + esimFlag = 0 + + # Reading all variables from ngveri config.ini + # parser_ngveri = ConfigParser() + # parser_ngveri.read(os.path.join(home, + # os.path.join('.ngveri', 'config.ini'))) + + kicad_lib_template = { + "start_def": "DEF comp_name U 0 40 Y Y 1 F N", + "U_field": "F0 \"U\" 2850 1800 60 H V C CNN", + "comp_name_field": "F1 \"comp_name\" 2850 2000 60 H V C CNN", + "blank_field": ["F2 blank_quotes 2850 1950 60 H V C CNN", + "F3 blank_quotes 2850 1950 60 H V C CNN"], + "start_draw": "DRAW", + "draw_pos": "S 2350 2100 3350 1800 0 1 0 N", + "input_port": "X in 1 2150 2000 200 R 50 50 1 1 I", + "output_port": "X out 2 3550 2000 200 L 50 50 1 1 O", + "end_draw": "ENDDRAW", + "end_def": "ENDDEF" + } diff --git a/src/maker/Maker.py b/src/maker/Maker.py new file mode 100755 index 00000000..e5d11988 --- /dev/null +++ b/src/maker/Maker.py @@ -0,0 +1,545 @@ +# ========================================================================= +# FILE: Maker.py +# +# USAGE: --- +# +# DESCRIPTION: This define all components of the Makerchip Tab. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Sumanto Kar, sumantokar@iitb.ac.in, FOSSEE, IIT Bombay +# ACKNOWLEDGEMENTS: Rahul Paknikar, rahulp@iitb.ac.in, FOSSEE, IIT Bombay +# Digvijay Singh, digvijay.singh@iitb.ac.in, FOSSEE, IIT Bombay +# Prof. Maheswari R. and Team, VIT Chennai +# GUIDED BY: Steve Hoover, Founder Redwood EDA +# Kunal Ghosh, VLSI System Design Corp.Pvt.Ltd +# Anagha Ghosh, VLSI System Design Corp.Pvt.Ltd +# OTHER CONTRIBUTERS: +# Prof. Madhuri Kadam, Shree L. R. Tiwari College of Engineering +# Rohinth Ram, Madras Institue of Technology +# Charaan S., Madras Institue of Technology +# Nalinkumar S., Madras Institue of Technology +# ORGANIZATION: eSim Team at FOSSEE, IIT Bombay +# CREATED: Monday 29, November 2021 +# REVISION: Tuesday 25, January 2022 +# ========================================================================= + +# importing the files and libraries +import hdlparse.verilog_parser as vlog +from PyQt5 import QtCore, QtWidgets +from PyQt5.QtCore import QThread +from configuration.Appconfig import Appconfig +import os +import watchdog.events +import watchdog.observers +from os.path import expanduser +home = expanduser("~") +# import inotify.adapters + +# declaring the global variables +# verilogfile stores the name of the file +# toggle flag stores the object of the toggling button +verilogFile = [] +toggle_flag = [] + + +# This function is called to accept TOS of makerchip +def makerchipTOSAccepted(display=True): + if not os.path.isfile(home + "/.makerchip_accepted"): + if display: + reply = QtWidgets.QMessageBox.warning( + None, "Terms of Service", "Please review the Makerchip \ + Terms of Service \ + (<a href='https://www.makerchip.com/terms/'>\ + https://www.makerchip.com/terms/</a>). \ + Have you read and do you \ + accept these Terms of Service?", + QtWidgets.QMessageBox.Yes | QtWidgets.QMessageBox.No + ) + + if reply == QtWidgets.QMessageBox.Yes: + f = open(home + "/.makerchip_accepted", "w") + f.close() + return True + + return False + return True + + +# beginning class Maker. This class create the Maker Tab +class Maker(QtWidgets.QWidget): + + # initailising the varaibles + def __init__(self, filecount): + print(self) + + QtWidgets.QWidget.__init__(self) + self.count = 0 + self.text = "" + self.filecount = filecount + self.entry_var = {} + self.createMakerWidget() + self.obj_Appconfig = Appconfig() + verilogFile.append("") + + # Creating the various components of the Widget(Maker Tab) + def createMakerWidget(self): + + self.grid = QtWidgets.QGridLayout() + self.setLayout(self.grid) + + self.grid.addWidget(self.createoptionsBox(), 0, 0, QtCore.Qt.AlignTop) + self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + self.show() + + # This function is to Add new verilog file + def addverilog(self): + + init_path = '../../' + if os.name == 'nt': + init_path = '' + self.verilogfile = QtCore.QDir.toNativeSeparators( + QtWidgets.QFileDialog.getOpenFileName( + self, "Open Verilog Directory", + init_path + "home", "*v" + )[0] + ) + if self.verilogfile == "": + self.verilogfile = self.entry_var[0].text() + + if self.verilogfile == "": + reply = QtWidgets.QMessageBox.critical( + None, + "Error Message", + "<b>No Verilog File Chosen. \ + Please choose a verilog file.</b>", + QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel) + + if reply == QtWidgets.QMessageBox.Ok: + self.addverilog() + + if self.verilogfile == "": + return + + self.obj_Appconfig.print_info('Add Verilog File Called') + + elif reply == QtWidgets.QMessageBox.Cancel: + self.obj_Appconfig.print_info('No Verilog File Chosen') + return + + self.text = open(self.verilogfile).read() + self.entry_var[0].setText(self.verilogfile) + self.entry_var[1].setText(self.text) + global verilogFile + + verilogFile[self.filecount] = self.verilogfile + if self.refreshoption in toggle_flag: + toggle_flag.remove(self.refreshoption) + + self.observer = watchdog.observers.Observer() + self.event_handler = Handler( + self.verilogfile, + self.refreshoption, + self.observer) + + self.observer.schedule( + self.event_handler, + path=self.verilogfile, + recursive=True) + self.observer.start() + # self.notify=notify(self.verilogfile,self.refreshoption) + # self.notify.start() + # open("filepath.txt","w").write(self.verilogfile) + + # This function is used to call refresh while + # running Ngspice to Verilog Converter + # (as the original one gets destroyed) + def refresh_change(self): + if self.refreshoption in toggle_flag: + self.toggle = toggle(self.refreshoption) + self.toggle.start() + + # It is used to refresh the file in eSim if its edited anywhere else + def refresh(self): + if not hasattr(self, 'verilogfile'): + return + self.text = open(self.verilogfile).read() + self.entry_var[1].setText(self.text) + print("NgVeri File: " + self.verilogfile + " Refreshed") + self.obj_Appconfig.print_info( + "NgVeri File: " + self.verilogfile + " Refreshed") + self.observer = watchdog.observers.Observer() + self.event_handler = Handler( + self.verilogfile, + self.refreshoption, + self.observer) + + self.observer.schedule( + self.event_handler, + path=self.verilogfile, + recursive=True) + self.observer.start() + # self.notify.start() + global toggle_flag + if self.refreshoption in toggle_flag: + toggle_flag.remove(self.refreshoption) + + # This function is used to save the edited file in eSim + def save(self): + try: + wr = self.entry_var[1].toPlainText() + open(self.verilogfile, "w+").write(wr) + except BaseException as err: + self.msg = QtWidgets.QErrorMessage(self) + self.msg.setModal(True) + self.msg.setWindowTitle("Error Message") + self.msg.showMessage( + "Error in saving verilog file. Please check if it is chosen." + ) + self.msg.exec_() + print("Error in saving verilog file: " + str(err)) + + # This is used to run the makerchip-app + def runmakerchip(self): + init_path = '../../' + if os.name == 'nt': + init_path = '' + try: + if not makerchipTOSAccepted(True): + return + + print("Running Makerchip IDE...........................") + # self.file = open(self.verilogfile,"w") + # self.file.write(self.entry_var[1].toPlainText()) + # self.file.close() + filename = self.verilogfile + if self.verilogfile.split('.')[-1] != "tlv": + reply = QtWidgets.QMessageBox.warning( + None, + "Do you want to automate the top module? ", + "<b>Click on YES button if you want the top module \ + to be added automatically. A .tlv file will be created \ + in the directory of current verilog file \ + and the Makerchip IDE will be running on \ + this file. Otherwise click on NO button. \ + To not open Makerchip IDE, click on CANCEL button. </b>\ + <br><br> NOTE: Makerchip IDE requires an active \ + internet connection and a browser.", + QtWidgets.QMessageBox.Yes + | QtWidgets.QMessageBox.No + | QtWidgets.QMessageBox.Cancel) + if reply == QtWidgets.QMessageBox.Cancel: + return + if reply == QtWidgets.QMessageBox.Yes: + code = open(self.verilogfile).read() + text = code + filename = '.'.join( + self.verilogfile.split('.')[:-1]) + ".tlv" + file = os.path.basename('.'.join( + self.verilogfile.split('.')[:-1])) + f = open(filename, 'w') + code = code.replace(" wire ", " ") + code = code.replace(" reg ", " ") + vlog_ex = vlog.VerilogExtractor() + vlog_mods = vlog_ex.extract_objects_from_source(code) + lint_off = open( + init_path + "library/tlv/lint_off.txt" + ).readlines() + string = '''\\TLV_version 1d: tl-x.org\n\\SV\n''' + for item in lint_off: + string += "/* verilator lint_off " + \ + item.strip("\n") + "*/ " + string += '''\n\n//Your Verilog/System \ +Verilog Code Starts Here:\n''' + \ + text + '''\n\n//Top Module Code \ +Starts here:\n\tmodule top(input \ +logic clk, input logic reset, input logic [31:0] cyc_cnt, \ +output logic passed, output logic failed);\n''' + print(file) + for m in vlog_mods: + if m.name.lower() == file.lower(): + for p in m.ports: + if str( + p.name) != "clk" and str( + p.name) != "reset" and str( + p.name) != "cyc_cnt" and str( + p.name) != "passed" and str( + p.name) != "failed": + string += '\t\tlogic ' + p.data_type\ + + " " + p.name + ";//" + p.mode + "\n" + if m.name.lower() != file.lower(): + QtWidgets.QMessageBox.critical( + None, + "Error Message", + "<b>Error: File name and module \ + name are not same. Please \ + ensure that they are same.</b>", + QtWidgets.QMessageBox.Ok) + + self.obj_Appconfig.print_info( + 'NgVeri stopped due to file \ +name and module name not matching error') + return + string += "//The $random() can be replaced \ +if user wants to assign values\n" + for m in vlog_mods: + if m.name.lower() == file.lower(): + for p in m.ports: + if str( + p.mode) == "input" or str( + p.mode) == "inout": + if str( + p.name) != "clk" and str( + p.name) != "reset" and str( + p.name) != "cyc_cnt" and str( + p.name) != "passed" and str( + p.name) != "failed": + string += '\t\tassign ' + p.name\ + + " = " + "$random();\n" + + for m in vlog_mods: + if m.name.lower() == file.lower(): + string += '\t\t' + m.name + " " + m.name + '(' + i = 0 + for p in m.ports: + i = i + 1 + string += "."+p.name+"("+p.name+")" + if i == len(m.ports): + string += ");\n\t\n\\TLV\n//\ +Add \\TLV here if desired\ + \n\\SV\nendmodule\n\n" + else: + string += ", " + f.write(string) + + self.process = QtCore.QProcess(self) + cmd = 'makerchip ' + filename + print("File: " + filename) + self.process.start(cmd) + print( + "Makerchip IDE command process pid ---------->", + self.process.pid()) + except BaseException as e: + print(e) + self.msg = QtWidgets.QErrorMessage(self) + self.msg.setModal(True) + self.msg.setWindowTitle("Error Message") + self.msg.showMessage( + "Error in running Makerchip IDE. \ +Please check if verilog file is chosen.") + self.msg.exec_() + print("Error in running Makerchip IDE. \ +Please check if verilog file is chosen.") + # initial = self.read_file() + + # while True: + # current = self.read_file() + # if initial != current: + # for line in current: + # if line not in initial: + # print(line) + # initial = current + # self.processfile = QtCore.QProcess(self) + # self.processfile.start("python3 notify.py") + # print(self.processfile.readChannel()) + + # This creates the buttons/options + + def createoptionsBox(self): + + self.optionsbox = QtWidgets.QGroupBox() + self.optionsbox.setTitle("Select Options") + self.optionsgrid = QtWidgets.QGridLayout() + # self.optionsbox2 = QtWidgets.QGroupBox() + # self.optionsbox2.setTitle("Note: Please save the file once edited") + # self.optionsgrid2 = QtWidgets.QGridLayout() + self.optionsgroupbtn = QtWidgets.QButtonGroup() + self.addoptions = QtWidgets.QPushButton("Add Top Level Verilog Model") + self.optionsgroupbtn.addButton(self.addoptions) + self.addoptions.clicked.connect(self.addverilog) + self.optionsgrid.addWidget(self.addoptions, 0, 1) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0 + self.refreshoption = QtWidgets.QPushButton("Refresh") + self.optionsgroupbtn.addButton(self.refreshoption) + self.refreshoption.clicked.connect(self.refresh) + self.optionsgrid.addWidget(self.refreshoption, 0, 2) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + self.saveoption = QtWidgets.QPushButton("Save") + self.optionsgroupbtn.addButton(self.saveoption) + self.saveoption.clicked.connect(self.save) + self.optionsgrid.addWidget(self.saveoption, 0, 3) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + self.runoptions = QtWidgets.QPushButton("Edit in Makerchip IDE") + self.runoptions.setToolTip( + "Requires internet connection and a browser" + ) + self.runoptions.setToolTipDuration(5000) + self.optionsgroupbtn.addButton(self.runoptions) + self.runoptions.clicked.connect(self.runmakerchip) + self.optionsgrid.addWidget(self.runoptions, 0, 4) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + if not makerchipTOSAccepted(False): + self.acceptTOS = QtWidgets.QPushButton("Accept Makerchip TOS") + self.optionsgroupbtn.addButton(self.acceptTOS) + self.acceptTOS.clicked.connect(lambda: makerchipTOSAccepted(True)) + self.optionsgrid.addWidget(self.acceptTOS, 0, 5) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + self.optionsbox.setLayout(self.optionsgrid) + return self.optionsbox + + # This function adds the other parts of widget like text box + def creategroup(self): + self.trbox = QtWidgets.QGroupBox() + self.trbox.setTitle(".tlv file") + # self.trbox.setDisabled(True) + # self.trbox.setVisible(False) + self.trgrid = QtWidgets.QGridLayout() + self.trbox.setLayout(self.trgrid) + + self.start = QtWidgets.QLabel("Path to .tlv file") + self.trgrid.addWidget(self.start, 1, 0) + self.count = 0 + self.entry_var[self.count] = QtWidgets.QLabel() + self.trgrid.addWidget(self.entry_var[self.count], 1, 1) + self.entry_var[self.count].setMaximumWidth(1000) + self.count += 1 + + # CSS + self.trbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: \ + 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: \ + 10px; padding: 0 3px 0 3px; } \ + ") + + self.start = QtWidgets.QLabel(".tlv code") + # self.start2 = QtWidgets.QLabel("Note: \ + # Please save the file once edited") + # self.start2.setStyleSheet("background-color: red") + self.trgrid.addWidget(self.start, 2, 0) + # self.trgrid.addWidget(self.start2, 3,0) + self.entry_var[self.count] = QtWidgets.QTextEdit() + self.trgrid.addWidget(self.entry_var[self.count], 2, 1) + self.entry_var[self.count].setMaximumWidth(1000) + self.entry_var[self.count].setMaximumHeight(1000) + # self.entry_var[self.count].textChanged.connect(self.save) + self.count += 1 + + # CSS + self.trbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: \ + 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: \ + 10px; padding: 0 3px 0 3px; } \ + ") + + return self.trbox + + +# The Handler class is used to create a watch on the files using WatchDog +class Handler(watchdog.events.PatternMatchingEventHandler): + # this function initialisses the variable and the objects of watchdog + def __init__(self, verilogfile, refreshoption, observer): + # Set the patterns for PatternMatchingEventHandler + watchdog.events.PatternMatchingEventHandler.__init__( + self, ignore_directories=True, case_sensitive=False) + self.verilogfile = verilogfile + self.refreshoption = refreshoption + self.obj_Appconfig = Appconfig() + self.observer = observer + self.toggle = toggle(self.refreshoption) + + # if a file is modified, toggle starts to toggle the refresh button + def on_modified(self, event): + print("Watchdog received modified event - % s." % event.src_path) + msg = QtWidgets.QErrorMessage() + msg.setWindowTitle("eSim Message") + msg.showMessage( + "NgVeri File: " + + self.verilogfile + + " modified. Please click on Refresh") + msg.exec_() + print("NgVeri File: " + self.verilogfile + + " modified. Please click on Refresh") + # self.obj_Appconfig.print_info("NgVeri File:\ + # "+self.verilogfile+" modified. Please click on Refresh") + global toggle_flag + if not(self.refreshoption in toggle_flag): + toggle_flag.append(self.refreshoption) + # i.rm_watch() + self.observer.stop() + self.toggle.start() + + +# class notify(QThread): +# def __init__(self,verilogfile,refreshoption):#,obj_Appconfig): +# QThread.__init__(self) +# self.verilogfile=verilogfile +# self.refreshoption=refreshoption +# self.obj_Appconfig = Appconfig() +# self.toggle=toggle(self.refreshoption) + + +# def __del__(self): +# self.wait() + +# def run(self): +# i = inotify.adapters.Inotify() + +# i.add_watch(self.verilogfile) + +# for event in i.event_gen(): +# if not self.refreshoption.isVisible(): +# break +# if event!=None: +# print(event) +# if "IN_CLOSE_WRITE" in event[1] : +# msg = QtWidgets.QErrorMessage() +# msg.setModal(True) +# msg.setWindowTitle("eSim Message") +# msg.showMessage( +# "NgVeri File: "+self.verilogfile+"\ +# modified. Please click on Refresh") +# msg.exec_() +# print("NgVeri File: "+self.verilogfile+"\ +# modified. Please click on Refresh") +# # self.obj_Appconfig.print_info("NgVeri File: \ +# "+self.verilogfile+" modified. Please click on Refresh") +# global toggle_flag +# toggle_flag.append(self.refreshoption) +# #i.rm_watch() +# self.toggle.start() +# break + + +# This class is used to toggle a button(change colour by toggling) +class toggle(QThread): + # initialising the threads + def __init__(self, option): + QThread.__init__(self) + self.option = option + + def __del__(self): + self.wait() + + # running the thread to toggle + def run(self): + + while True: + self.option.setStyleSheet("background-color: red") + self.sleep(1) + self.option.setStyleSheet("background-color: none") + self.sleep(1) + print(toggle_flag) + if not self.option.isVisible(): + break + if self.option not in toggle_flag: + break diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py new file mode 100755 index 00000000..49d5da0b --- /dev/null +++ b/src/maker/ModelGeneration.py @@ -0,0 +1,1214 @@ +# ========================================================================= +# FILE: ModelGeneration.py +# +# USAGE: --- +# +# DESCRIPTION: This define all model generation processes of NgVeri. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Sumanto Kar, sumantokar@iitb.ac.in, FOSSEE, IIT Bombay +# ACKNOWLEDGEMENTS: Rahul Paknikar, rahulp@iitb.ac.in, FOSSEE, IIT Bombay +# Digvijay Singh, digvijay.singh@iitb.ac.in, FOSSEE, IIT Bombay +# Prof. Maheswari R. and Team, VIT Chennai +# GUIDED BY: Steve Hoover, Founder Redwood EDA +# Kunal Ghosh, VLSI System Design Corp.Pvt.Ltd +# Anagha Ghosh, VLSI System Design Corp.Pvt.Ltd +# OTHER CONTRIBUTERS: +# Prof. Madhuri Kadam, Shree L. R. Tiwari College of Engineering +# Rohinth Ram, Madras Institue of Technology +# Charaan S., Madras Institue of Technology +# Nalinkumar S., Madras Institue of Technology +# ORGANIZATION: eSim Team at FOSSEE, IIT Bombay +# CREATED: Monday 29, November 2021 +# REVISION: Tuesday 25, January 2022 +# ========================================================================= + + +# importing the files and libraries +import re +import os +from PyQt5 import QtCore, QtWidgets +from configparser import ConfigParser +from configuration import Appconfig +from . import createkicad +import hdlparse.verilog_parser as vlog + + +# Class is used to generate the Ngspice Model +class ModelGeneration(QtWidgets.QWidget): + + # initialising the variables + def __init__(self, file, termedit): + QtWidgets.QWidget.__init__(self) + super().__init__() + self.obj_Appconfig = Appconfig.Appconfig() + print("Argument is : ", file) + + if os.name == 'nt': + self.file = file.replace('\\', '/') + else: + self.file = file + + self.termedit = termedit + self.cur_dir = os.getcwd() + self.fname = os.path.basename(file) + self.fname = self.fname.lower() + print("Verilog/SystemVerilog/TL Verilog filename is : ", self.fname) + + if os.name == 'nt': + self.home = os.path.join('library', 'config') + else: + self.home = os.path.expanduser('~') + + self.parser = ConfigParser() + self.parser.read(os.path.join( + self.home, os.path.join('.nghdl', 'config.ini'))) + self.nghdl_home = self.parser.get('NGHDL', 'NGHDL_HOME') + self.release_dir = self.parser.get('NGHDL', 'RELEASE') + self.src_home = self.parser.get('SRC', 'SRC_HOME') + self.licensefile = self.parser.get('SRC', 'LICENSE') + self.digital_home = self.parser.get( + 'NGHDL', 'DIGITAL_MODEL') + "/Ngveri" + # # #### Creating connection_info.txt file from verilog file #### # + + # Reading the file and performing operations and + # copying it in the Ngspice folder + def verilogfile(self): + Text = "<span style=\" font-size:25pt;\ + font-weight:1000; color:#008000;\" >" + Text += ".................Running NgVeri..................." + Text += "</span>" + self.termedit.append(Text) + + read_verilog = open(self.file, 'r') + verilog_data = read_verilog.readlines() + read_verilog.close() + self.modelpath = self.digital_home + \ + "/" + self.fname.split('.')[0] + "/" + if not os.path.isdir(self.modelpath): + os.mkdir(self.modelpath) + + if self.fname.split('.')[1] == "tlv": + self.sandpiper() + read_verilog = open(self.modelpath + self.fname, 'r') + verilog_data = read_verilog.readlines() + read_verilog.close() + f = open(self.modelpath + self.fname, 'w') + + for item in verilog_data: + if self.fname.split('.')[1] == "sv": + string = item.replace("top", self.fname.split('.')[0]) + else: + string = item + f.write(string) + f.write("\n") + f.close() + + # This function calls the sandpiper to convert .tlv file to .sv file + def sandpiper(self): + init_path = '../../' + if os.name == 'nt': + init_path = '' + # Text="Running Sandpiper............" + print("Running Sandpiper-Saas for TLV to SV Conversion") + self.cmd = "cp " + init_path + "library/tlv/clk_gate.v " + \ + init_path + "library/tlv/pseudo_rand.sv " + \ + init_path + "library/tlv/sandpiper.vh " + \ + init_path + "library/tlv/sandpiper_gen.vh " + \ + init_path + "library/tlv/sp_default.vh " + \ + init_path + "library/tlv/pseudo_rand_gen.sv " + \ + init_path + "library/tlv/pseudo_rand.m4out.tlv " + \ + self.file + " " + self.modelpath + + self.process = QtCore.QProcess(self) + self.args = ['-c', self.cmd] + self.process.start('sh', self.args) + self.termedit.append("Command: " + self.cmd) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process.waitForFinished(50000) + print("Copied the files required for TLV successfully") + self.cur_dir = os.getcwd() + print("Running Sandpiper............") + os.chdir(self.modelpath) + self.cmd = "sandpiper-saas -i " + \ + self.fname.split('.')[0] + ".tlv -o "\ + + self.fname.split('.')[0] + ".sv" + # self.args = ['-c', self.cmd] + # self.process.start('sh', self.args) + self.process.start(self.cmd) + self.termtitle("RUN SANDPIPER-SAAS") + self.termtext("Current Directory: " + self.modelpath) + self.termtext("Command: " + self.cmd) + # self.process.setProcessChannelMode(QtCore.QProcess.MergedChannels) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process \ + .readyReadStandardError.connect(self.readAllStandard) + self.process.waitForFinished(50000) + print("Ran Sandpiper successfully") + os.chdir(self.cur_dir) + self.fname = self.fname.split('.')[0] + ".sv" + + # This function parses the module name and \ + # input/output ports of verilog code using HDL parse + # and writes to the connection_info.txt + + def verilogParse(self): + + with open(self.modelpath + self.fname, 'rt') as fh: + code = fh.read() + + code = code.replace("wire", " ") + code = code.replace("reg", " ") + vlog_ex = vlog.VerilogExtractor() + vlog_mods = vlog_ex.extract_objects_from_source(code) + f = open(self.modelpath + "connection_info.txt", 'w') + for m in vlog_mods: + if m.name.lower() == self.fname.split('.')[0]: + print(str(m.name) + " " + self.fname.split('.')[0]) + for p in m.ports: + print(p.data_type) + if str(p.data_type).find(':') == -1: + p.port_number = "1" + else: + x = p.data_type.split(":") + print(x) + y = x[0].split("[") + z = x[1].split("]") + z = int(y[1]) - int(z[0]) + p.port_number = z + 1 + + for m in vlog_mods: + if m.name.lower() == self.fname.split('.')[0]: + m.name = m.name.lower() + print('Module "{}":'.format(m.name)) + for p in m.generics: + print('\t{:20}{:8}{}'.format(p.name, p.mode, p.data_type)) + print(' Ports:') + for p in m.ports: + print( + '\t{:20}{:8}{}'.format( + p.name, p.mode, p.port_number)) + f.write( + '\t{:20}{:8}{}\n'.format( + p.name, p.mode, p.port_number)) + break + f.close() + if m.name.lower() != self.fname.split(".")[0]: + QtWidgets.QMessageBox.critical( + None, + "Error Message", + "<b>Error: File name and module \ + name are not same. Please ensure that they are same</b>", + QtWidgets.QMessageBox.Ok) + + self.obj_Appconfig.print_info( + 'NgVeri stopped due to file \ + name and module name not matching error') + return "Error" + modelname = str(m.name) + schematicLib = createkicad.AutoSchematic() + schematicLib.init(modelname, self.modelpath) + error = schematicLib.createkicad() + if error == "Error": + return "Error" + return "No Error" + + # This function is used to get the Port Information from + # connection_info.txt + def getPortInfo(self): + readfile = open(self.modelpath + 'connection_info.txt', 'r') + data = readfile.readlines() + self.input_list = [] + self.output_list = [] + for line in data: + if re.match(r'^\s*$', line): + pass + else: + in_items = re.findall( + "INPUT", line, re.MULTILINE | re.IGNORECASE + ) + inout_items = re.findall( + "INOUT", line, re.MULTILINE | re.IGNORECASE + ) + out_items = re.findall( + "OUTPUT", line, re.MULTILINE | re.IGNORECASE + ) + if in_items: + self.input_list.append(line.split()) + if inout_items: + self.input_list.append(line.split()) + if out_items: + self.output_list.append(line.split()) + + self.input_port = [] + self.output_port = [] + + # creating list of input and output port with its weight + for input in self.input_list: + self.input_port.append(input[0] + ":" + input[2]) + for output in self.output_list: + self.output_port.append(output[0] + ":" + output[2]) + + # This function is used to create the cfunc.mod file in Ngspice folder + # automatically + + def cfuncmod(self): + + # ############# Creating content for cfunc.mod file ############## # + + print("Starting With cfunc.mod file") + cfunc = open(self.modelpath + 'cfunc.mod', 'w') + print("Building content for cfunc.mod file") + + comment = '''/* This cfunc.mod file auto generated by gen_con_info.py + Developed by Sumanto, Rahul at IIT Bombay */\n + ''' + + header = ''' + #include <stdio.h> + #include <math.h> + #include <string.h> + #include "sim_main_''' + self.fname.split('.')[0] + '''.h" + + ''' + + function_open = ( + '''void cm_''' + self.fname.split('.')[0] + '''(ARGS) \n{''') + + digital_state_output = [] + for item in self.output_port: + digital_state_output.append( + "Digital_State_t *_op_" + item.split(':')[0] + + ", *_op_" + item.split(':')[0] + "_old;" + ) + + var_section = ''' + static int inst_count=0; + int count=0; + ''' + + # Start of INIT function + init_start_function = ''' + if(INIT) + { + inst_count++; + PARAM(instance_id)=inst_count; + foo_''' + self.fname.split('.')[0] + '''(0,inst_count); + /* Allocate storage for output ports \ +and set the load for input ports */ + + ''' + port_init = [] + for i, item in enumerate(self.input_port + self.output_port): + port_init.append(self.fname.split('.')[0] + '''_port_''' + + item.split(':')[0] + '''=PORT_SIZE(''' + + item.split(':')[0] + '''); +''') + + cm_event_alloc = [] + cm_count_output = 0 + for item in self.output_port: + cm_event_alloc.append( + "cm_event_alloc(" + + str(cm_count_output) + "," + item.split(':')[1] + + "*sizeof(Digital_State_t));" + ) + cm_count_output = cm_count_output + 1 + + load_in_port = [] + for item in self.input_port: + load_in_port.append( + "for(Ii=0;Ii<PORT_SIZE(" + item.split(':')[0] + + ");Ii++)\n\t\t{\n\t\t\tLOAD(" + item.split(':')[0] + + "[Ii])=PARAM(input_load); \n\t\t}" + ) + + cm_count_ptr = 0 + cm_event_get_ptr = [] + for item in self.output_port: + cm_event_get_ptr.append( + "_op_" + item.split(':')[0] + " = _op_" + + item.split(':')[0] + + "_old = (Digital_State_t *) cm_event_get_ptr(" + + str(cm_count_ptr) + ",0);" + ) + + cm_count_ptr = cm_count_ptr + 1 + + els_evt_ptr = [] + els_evt_count1 = 0 + els_evt_count2 = 0 + for item in self.output_port: + els_evt_ptr.append("_op_" + item.split(":")[0] + + " = (Digital_State_t *) cm_event_get_ptr(" + + str(els_evt_count1) + "," + + str(els_evt_count2) + ");") + els_evt_count2 = els_evt_count2 + 1 + els_evt_ptr.append("_op_" + item.split(":")[0] + "_old" + + " = (Digital_State_t *) cm_event_get_ptr(" + + str(els_evt_count1) + "," + + str(els_evt_count2) + ");") + els_evt_count1 = els_evt_count1 + 1 + + # Assign bit value to every input + assign_data_to_input = [] + for item in self.input_port: + assign_data_to_input.append("\ + for(Ii=0;Ii<PORT_SIZE(" + item.split(':')[0] + ");Ii++)\n\ + {\n\ + if( INPUT_STATE(" + item.split(':')[0] + "[Ii])==ZERO )\n\ + {\n\ + " + self.fname.split('.')[0] + + "_temp_" + item.split(':')[0] + "[Ii]=0;\ + }\n\ + else\n\ + {\n\ + " + self.fname.split('.')[0] + + "_temp_" + item.split(':')[0] + "[Ii]=1;\n\ + }\n\ + }\n") + + # Scheduling output event + sch_output_event = [] + + for item in self.output_port: + sch_output_event.append( + "\t/* Scheduling event and processing them */\n\ + for(Ii=0;Ii<PORT_SIZE(" + item.split(':')[0] + ");Ii++)\n\ + {\n\ + if(" + self.fname.split('.')[0] + "_temp_" + + item.split(':')[0] + "[Ii]==0)\n\ + {\n\ + _op_" + item.split(':')[0] + "[Ii]=ZERO;\n\ + }\n\ + else if(" + self.fname.split('.')[0] + + "_temp_" + item.split(':')[0] + "[Ii]==1)\n\ + {\n\ + _op_" + item.split(':')[0] + "[Ii]=ONE;\n\ + }\n\ + else\n\ + {\n\ + printf(\"Unknown value\\n\");\n\ + }\n\n\ + if(ANALYSIS == DC)\n\ + {\n\ + OUTPUT_STATE(" + item.split(':')[0] + "[Ii]) = _op_" + item.split(':')[0] + "[Ii];\n\ + }\n\ + else if(_op_" + item.split(':')[0] + "[Ii] != _op_" + item.split(':')[0] + "_old[Ii])\n\ + {\n\ + OUTPUT_STATE(" + item.split(':')[0] + "[Ii]) = _op_" + item.split(':')[0] + "[Ii];\n\ + OUTPUT_DELAY(" + item.split(':')[0] + "[Ii]) = ((_op_" + item.split(':')[0] + "[Ii] == ZERO) ? PARAM(fall_delay) : PARAM(rise_delay));\n\ + }\n\ + else\n\ + {\n\ + OUTPUT_CHANGED(" + item.split(':')[0] + "[Ii]) = FALSE;\n\ + }\n\ + OUTPUT_STRENGTH(" + item.split(':')[0] + "[Ii]) = STRONG;\n\ + }\n") + + # Writing content in cfunc.mod file + cfunc.write(comment) + cfunc.write(header) + cfunc.write("\n") + cfunc.write(function_open) + cfunc.write("\n") + + # Adding digital state Variable + for item in digital_state_output: + cfunc.write("\t" + item + "\n") + + # Adding variable declaration section + cfunc.write(var_section) + + # Adding INIT portion + cfunc.write(init_start_function) + for item in port_init: + cfunc.write(item) + for item in cm_event_alloc: + cfunc.write(2 * "\t" + item) + cfunc.write("\n") + + cfunc.write(2 * "\t" + "/* set the load for input ports. */") + cfunc.write("\n") + cfunc.write(2 * "\t" + "int Ii;") + cfunc.write("\n") + + for item in load_in_port: + cfunc.write(2 * "\t" + item) + cfunc.write("\n") + cfunc.write("\n") + cfunc.write(2 * "\t" + "/*Retrieve Storage for output*/") + cfunc.write("\n") + for item in cm_event_get_ptr: + cfunc.write(2 * "\t" + item) + cfunc.write("\n") + cfunc.write("\n") + + # if os.name == 'nt': + # digital_home = parser.get('NGHDL', 'DIGITAL_MODEL') + # msys_home = parser.get('COMPILER', 'MSYS_HOME') + # cmd_str2 = "/start_server.sh %d %s & read" + "\\" + "\"" + "\"" + # cmd_str1 = os.path.normpath( + # "\"" + digital_home + "/" + + # fname.split('.')[0] + "/DUTghdl/" + # ) + # cmd_str1 = cmd_str1.replace("\\", "/") + + # cfunc.write( + # '\t\tsnprintf(command,1024, "start mintty.exe -t ' + + # '\\"VHDL-Testbench Logs\\" -h always bash.exe -c ' + + # '\\' + cmd_str1 + cmd_str2 + ', sock_port, my_ip);' + # ) + # else: + # cfunc.write( + # '\t\tsnprintf(command,1024,"' + home + + # '/nghdl-simulator/src/xspice/icm/ghdl/' + + # fname.split('.')[0] + + # '/DUTghdl/start_server.sh %d %s &", sock_port, my_ip);' + # ) + + cfunc.write("\n\t}") + cfunc.write("\n") + cfunc.write("\telse\n\t{\n") + + for item in els_evt_ptr: + cfunc.write(2 * "\t" + item) + cfunc.write("\n") + cfunc.write("\t}") + cfunc.write("\n\n") + + cfunc.write("\t//Formating data for sending it to client\n") + cfunc.write("\tint Ii;\n") + cfunc.write("\tcount=(int)PARAM(instance_id);\n\n") + for item in assign_data_to_input: + cfunc.write(item) + + cfunc.write("\tfoo_" + self.fname.split('.')[0] + "(1,count);\n\n") + + for item in sch_output_event: + cfunc.write(item) + + # Close cm_ function + cfunc.write("\n}") + cfunc.close() + + # This function creates the ifspec file automatically in Ngspice folder + + def ifspecwrite(self): + print("Starting with ifspec.ifs file") + ifspec = open(self.modelpath + 'ifspec.ifs', 'w') + + print("Gathering Al the content for ifspec file") + + ifspec_comment = ''' + /* + SUMMARY: This file is auto generated and it contains the interface + specification for the code model. */\n + ''' + + name_table = 'NAME_TABLE:\n\ + C_Function_Name: cm_' + self.fname.split('.')[0] + '\n\ + Spice_Model_Name: ' + self.fname.split('.')[0] + '\n\ + Description: "Model generated from ghdl code ' + self.fname + '" \n' + + # Input and Output Port Table + in_port_table = [] + out_port_table = [] + + for item in self.input_port: + port_table = 'PORT_TABLE:\n' + port_name = 'Port_Name:\t' + item.split(':')[0] + '\n' + description = ( + 'Description:\t"input port ' + item.split(':')[0] + '"\n' + ) + direction = 'Direction:\tin\n' + default_type = 'Default_Type:\td\n' + allowed_type = 'Allowed_Types:\t[d]\n' + vector = 'Vector:\tyes\n' + vector_bounds = ( + 'Vector_Bounds:\t[' + item.split(':')[1] + + ' ' + item.split(":")[1] + ']\n' + ) + null_allowed = 'Null_Allowed:\tno\n' + + # Insert detail in the list + in_port_table.append( + port_table + port_name + description + + direction + default_type + allowed_type + + vector + vector_bounds + null_allowed + ) + + for item in self.output_port: + port_table = 'PORT_TABLE:\n' + port_name = 'Port_Name:\t' + item.split(':')[0] + '\n' + description = ( + 'Description:\t"output port ' + item.split(':')[0] + '"\n' + ) + direction = 'Direction:\tout\n' + default_type = 'Default_Type:\td\n' + allowed_type = 'Allowed_Types:\t[d]\n' + vector = 'Vector:\tyes\n' + vector_bounds = ( + 'Vector_Bounds:\t[' + item.split(':')[1] + + ' ' + item.split(":")[1] + ']\n' + ) + null_allowed = 'Null_Allowed:\tno\n' + + # Insert detail in the list + in_port_table.append( + port_table + port_name + description + + direction + default_type + allowed_type + + vector + vector_bounds + null_allowed + ) + + parameter_table = ''' + + PARAMETER_TABLE: + Parameter_Name: instance_id input_load + Description: "instance_id" "input load value (F)" + Data_Type: real real + Default_Value: 0 1.0e-12 + Limits: - - + Vector: no no + Vector_Bounds: - - + Null_Allowed: yes yes + + PARAMETER_TABLE: + Parameter_Name: rise_delay fall_delay + Description: "rise delay" "fall delay" + Data_Type: real real + Default_Value: 1.0e-9 1.0e-9 + Limits: [1e-12 -] [1e-12 -] + Vector: no no + Vector_Bounds: - - + Null_Allowed: yes yes + + ''' + + # Writing all the content in ifspec file + ifspec.write(ifspec_comment) + ifspec.write(name_table + "\n\n") + + for item in in_port_table: + ifspec.write(item + "\n") + + ifspec.write("\n") + + for item in out_port_table: + ifspec.write(item + "\n") + + ifspec.write("\n") + ifspec.write(parameter_table) + ifspec.write("\n") + ifspec.close() + + # This function creates the header file of sim_main file automatically in + # Ngspice folder + + def sim_main_header(self): + print("Starting With sim_main_" + self.fname.split('.')[0] + ".h file") + simh = open( + self.modelpath + + 'sim_main_' + + self.fname.split('.')[0] + + '.h', + 'w') + print("Building content for sim_main_" + + self.fname.split('.')[0] + ".h file") + simh.write("int foo_" + self.fname.split('.')[0] + "(int,int);") + extern_var = [] + for i, item in enumerate(self.input_port + self.output_port): + extern_var.append(''' + int ''' + self.fname.split('.')[0] + '''_temp_''' + + item.split(':')[0] + '''[1024]; + int ''' + self.fname.split('.')[0] + '''_port_''' + + item.split(':')[0] + ''';''') + for item in extern_var: + simh.write(item) + simh.close() + + # This function creates the sim_main file needed by verilator + # automatically in Ngspice folder + def sim_main(self): + print( + "Starting With sim_main_" + + self.fname.split('.')[0] + + ".cpp file") + csim = open( + self.modelpath + + 'sim_main_' + + self.fname.split('.')[0] + + '.cpp', + 'w') + print( + "Building content for sim_main_" + + self.fname.split('.')[0] + + ".cpp file") + + comment = '''/* This is cfunc.mod file auto generated by gen_con_info.py + Developed by Sumanto Kar at IIT Bombay */\n + ''' + + header = ''' + #include <memory> + #include <verilated.h> + #include "V''' + self.fname.split('.')[0] + '''.h" + #include <stdio.h> + #include <stdio.h> + #include <fstream> + #include <stdlib.h> + #include <string> + #include <iostream> + #include <cstring> + using namespace std; + ''' + + extern_var = [] + for i, item in enumerate(self.input_port + self.output_port): + extern_var.append(''' + extern "C" int ''' + self.fname.split('.')[0] + + '''_temp_''' + item.split(':')[0] + '''[1024]; + extern "C" int ''' + self.fname.split('.')[0] + + '''_port_''' + item.split(':')[0] + ''';''') + + extern_var.append(''' + extern "C" int foo_''' + self.fname.split('.')[0] + '''(int,int); + ''') + convert_func = ''' + void int2arr''' + self.fname.split('.')[0] + '''(int num, int array[], int n) + { + for (int i = 0; i < n && num>=0; i++) + { + array[n-i-1] = num % 2; + num /= 2; + } + } + int arr2int''' + self.fname.split('.')[0] + '''(int array[],int n) + { + int i,k=0; + for (i = 0; i < n; i++) + k = 2 * k + array[i]; + return k; + } + ''' + foo_func = ''' + int foo_''' + self.fname.split('.')[0] + '''(int init,int count) + { + static VerilatedContext* contextp = new VerilatedContext; + static V''' + self.fname.split('.')[0] + "* " + self.fname.split('.')[0] + '''[1024]; + count--; + if (init==0) + { + ''' + self.fname.split('.')[0] + '''[count]=new V''' + self.fname.split('.')[0] + '''{contextp}; + contextp->traceEverOn(true); + } + else + { + contextp->timeInc(1); + printf("=============''' + self.fname.split('.')[0] + ''' : New Iteration==========="); + printf("\\nInstance : %d\\n",count); + printf("\\nInside foo before eval.....\\n"); +''' + + before_eval = [] + after_eval = [] + for i, item in enumerate(self.input_port + self.output_port): + before_eval.append( + '''\t\t\t\tprintf("''' + + item.split(':')[0] + + '''=%d\\n", ''' + + self.fname.split('.')[0] + + '''[count] ->''' + + item.split(':')[0] + + ''');\n''') + for i, item in enumerate(self.input_port): + + before_eval.append( + '''\t\t\t\t''' + + self.fname.split('.')[0] + + '''[count]->''' + + item.split(':')[0] + + ''' = arr2int''' + + self.fname.split('.')[0] + + '''(''' + self.fname.split('.')[0] + '''_temp_''' + + item.split(':')[0] + + ''', ''' + self.fname.split('.')[0] + '''_port_''' + + item.split(':')[0] + + ''');\n''') + before_eval.append( + "\t\t\t\t" + + self.fname.split('.')[0] + + "[count]->eval();\n") + + after_eval.append(''' + printf("\\nInside foo after eval.....\\n");\n''') + for i, item in enumerate(self.input_port + self.output_port): + after_eval.append( + '''\t\t\t\tprintf("''' + + item.split(':')[0] + + '''=%d\\n", ''' + + self.fname.split('.')[0] + + '''[count] ->''' + + item.split(':')[0] + + ''');\n''') + + for i, item in enumerate(self.output_port): + after_eval.append( + "\t\t\t\tint2arr" + + self.fname.split('.')[0] + + "(" + + self.fname.split('.')[0] + + '''[count] -> ''' + + item.split(':')[0] + + ''', ''' + self.fname.split('.')[0] + '''_temp_''' + + item.split(':')[0] + + ''', ''' + self.fname.split('.')[0] + '''_port_''' + + item.split(':')[0] + + ''');\n''') + after_eval.append(''' + } + return 0; + }''') + + csim.write(comment) + csim.write(header) + for item in extern_var: + csim.write(item) + csim.write(convert_func) + csim.write(foo_func) + + for item in before_eval: + csim.write(item) + for item in after_eval: + csim.write(item) + csim.close() + + # This function creates modpathlst in Ngspice folder + def modpathlst(self): + print("Editing modpath.lst file") + mod = open(self.digital_home + '/modpath.lst', 'r') + text = mod.read() + mod.close() + mod = open(self.digital_home + '/modpath.lst', 'a+') + if not self.fname.split('.')[0] in text: + mod.write(self.fname.split('.')[0] + "\n") + mod.close() + + # This function is used to run the Verilator using the verilator commands + def run_verilator(self): + init_path = '../../' + if os.name == 'nt': + init_path = '' + + self.cur_dir = os.getcwd() + wno = " " + with open(init_path + "library/tlv/lint_off.txt") as file: + for item in file.readlines(): + if item and item.strip(): + wno += " -Wno-" + item.strip("\n") + + print("Running Verilator.............") + os.chdir(self.modelpath) + self.release_home = self.parser.get('NGHDL', 'RELEASE') + # print(self.modelpath) + + if os.name == 'nt': + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = "export VERILATOR_ROOT=" + self.msys_home + "/mingw64; " + else: + self.cmd = '' + + self.cmd = self.cmd + "verilator -Wall " + wno + " \ + --cc --exe --no-MMD --Mdir . -CFLAGS -fPIC sim_main_" + \ + self.fname.split('.')[0] + ".cpp " + self.fname + self.process = QtCore.QProcess(self) + self.process.readyReadStandardOutput.connect(self.readAllStandard) + self.process.start('sh', ['-c', self.cmd]) + self.termtitle("RUN VERILATOR") + self.termtext("Current Directory: " + self.modelpath) + self.termtext("Command: " + self.cmd) + # self.process.setProcessChannelMode(QtCore.QProcess.MergedChannels) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process \ + .readyReadStandardError.connect(self.readAllStandard) + self.process.waitForFinished(50000) + print("Verilator Executed") + os.chdir(self.cur_dir) + + # Running make verilator using this function + def make_verilator(self): + self.cur_dir = os.getcwd() + print("Make Verilator.............") + os.chdir(self.modelpath) + + if os.path.exists(self.modelpath + "../verilated.o"): + os.remove(self.modelpath + "../verilated.o") + + if os.name == 'nt': + # path to msys home directory + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe" + else: + self.cmd = "make" + + self.cmd = self.cmd + " -f V" + self.fname.split('.')[0]\ + + ".mk V" + self.fname.split( + '.')[0] + "__ALL.a sim_main_" \ + + self.fname.split('.')[0] + ".o ../verilated.o" + self.process = QtCore.QProcess(self) + self.process.readyReadStandardOutput.connect(self.readAllStandard) + self.process.start('sh', ['-c', self.cmd]) + self.termtitle("MAKE VERILATOR") + self.termtext("Current Directory: " + self.modelpath) + self.termtext("Command: " + self.cmd) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process \ + .readyReadStandardError.connect(self.readAllStandard) + self.process.waitForFinished(50000) + + print("Make Verilator Executed") + os.chdir(self.cur_dir) + + # This function copies the verilator files/object files from + # src/xspice/icm/Ngveri/ to release/src/xspice/icm/Ngveri/ + def copy_verilator(self): + self.cur_dir = os.getcwd() + print("Copying the required files to Release Folder.............") + os.chdir(self.modelpath) + self.release_home = self.parser.get('NGHDL', 'RELEASE') + path_icm = self.release_home + "/src/xspice/icm/Ngveri/" + if not os.path.isdir(path_icm + self.fname.split('.')[0]): + os.mkdir(path_icm + self.fname.split('.')[0]) + path_icm = path_icm + self.fname.split('.')[0] + if os.path.exists( + path_icm + + "sim_main_" + + self.fname.split('.')[0] + + ".o"): + os.remove(path_icm + "sim_main_" + self.fname.split('.')[0] + ".o") + if os.path.exists( + self.release_home + + "src/xspice/icm/Ngveri/" + + "verilated.o"): + os.remove( + self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o" + ) + if os.path.exists( + path_icm + + "V" + + self.fname.split('.')[0] + + "__ALL.o"): + os.remove(path_icm + "V" + self.fname.split('.')[0] + "__ALL.o") + # print(self.modelpath) + try: + self.cmd = "cp sim_main_" + \ + self.fname.split('.')[0] + ".o V" + \ + self.fname.split('.')[0] + "__ALL.o " + path_icm + self.process = QtCore.QProcess(self) + self.args = ['-c', self.cmd] + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process \ + .readyReadStandardError.connect(self.readAllStandard) + self.process.start('sh', self.args) + self.termtitle("COPYING FILES") + self.termtext("Current Directory: " + self.modelpath) + self.termtext("Command: " + self.cmd) + self.process.waitForFinished(50000) + self.cmd = "cp ../verilated.o " + self.release_home \ + + "/src/xspice/icm/Ngveri/" + self.process.start('sh', ['-c', self.cmd]) + self.termtext("Command: " + self.cmd) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process.waitForFinished(50000) + print("Copied the files") + os.chdir(self.cur_dir) + except BaseException: + print("There is error in Copying Files ") + + # Running the make command for Ngspice + def runMake(self): + print("run Make Called") + self.release_home = self.parser.get('NGHDL', 'RELEASE') + path_icm = os.path.join(self.release_home, "src/xspice/icm") + os.chdir(path_icm) + + try: + if os.name == 'nt': + # path to msys home directory + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe" + else: + self.cmd = "make" + + print("Running Make command in " + path_icm) + self.process = QtCore.QProcess(self) + self.process.start('sh', ['-c', self.cmd]) + print("make command process pid ---------- >", self.process.pid()) + + self.termtitle("MAKE COMMAND") + self.termtext("Current Directory: " + path_icm) + self.termtext("Command: " + self.cmd) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process \ + .readyReadStandardError.connect(self.readAllStandard) + self.process.waitForFinished(50000) + os.chdir(self.cur_dir) + except BaseException: + print("There is error in 'make' ") + # sys.exit() + + # Running the make install command for Ngspice + def runMakeInstall(self): + self.cur_dir = os.getcwd() + print("run Make Install Called") + self.release_home = self.parser.get('NGHDL', 'RELEASE') + path_icm = os.path.join(self.release_home, "src/xspice/icm") + os.chdir(path_icm) + + try: + if os.name == 'nt': + self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') + self.cmd = self.msys_home + \ + "/mingw64/bin/mingw32-make.exe install" + else: + self.cmd = "make install" + print("Running Make Install") + try: + self.process.close() + except BaseException: + pass + + self.process = QtCore.QProcess(self) + self.process.start('sh', ['-c', self.cmd]) + # text="<span style=\" font-size:8pt; font-weight:600; + # color:#000000;\" >" + self.termtitle("MAKE INSTALL COMMAND") + self.termtext("Current Directory: " + path_icm) + self.termtext("Command: " + self.cmd) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process \ + .readyReadStandardError.connect(self.readAllStandard) + self.process.waitForFinished(50000) + os.chdir(self.cur_dir) + + except BaseException as e: + print(e) + print("There is error in 'make install' ") + # sys.exit() + + # This function is used to add additional files required by the verilog + # top module + def addfile(self): + print("Adding the files required by the top level module file") + + init_path = '../../' + if os.name == 'nt': + init_path = '' + + includefile = QtCore.QDir.toNativeSeparators( + QtWidgets.QFileDialog.getOpenFileName( + self, + "Open adding other necessary files to be included", + init_path + "home")[0]) + + if includefile == "": + reply = QtWidgets.QMessageBox.critical( + None, "Error Message", + "<b>Error: No File Chosen. Please chose a file</b>", + QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel + ) + + if reply == QtWidgets.QMessageBox.Ok: + self.addfile() + + if includefile == "": + return + + self.obj_Appconfig.print_info('Add Other Files Called') + + elif reply == QtWidgets.QMessageBox.Cancel: + self.obj_Appconfig.print_info('No File Chosen') + return + + filename = os.path.basename(includefile) + self.modelpath = self.digital_home + \ + "/" + self.fname.split('.')[0] + "/" + + if not os.path.isdir(self.modelpath): + os.mkdir(self.modelpath) + text = open(includefile).read() + text = text + '\n' + f = open(self.modelpath + filename, 'w') + for item in text: + f.write(item) + f.write("\n") + f.close() + print("Added the File:" + filename) + self.termtitle("Added the File:" + filename) + + def addfolder(self): + ''' + This function is used to add additional folder required + by the verilog top module + ''' + # self.cur_dir = os.getcwd() + print("Adding the folder required by the top level module file") + + includefolder = QtCore.QDir.toNativeSeparators( + QtWidgets.QFileDialog.getExistingDirectory( + self, "open", "home" + ) + ) + + if includefolder == "": + reply = QtWidgets.QMessageBox.critical( + None, "Error Message", + "<b>Error: No Folder Chosen. Please chose a folder</b>", + QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel + ) + + if reply == QtWidgets.QMessageBox.Ok: + self.addfolder() + + if includefolder == "": + return + + self.obj_Appconfig.print_info('Add Folder Called') + + elif reply == QtWidgets.QMessageBox.Cancel: + self.obj_Appconfig.print_info('No Folder Chosen') + return + + self.modelpath = self.digital_home + \ + "/" + self.fname.split('.')[0] + "/" + + reply = QtWidgets.QMessageBox.question( + None, "Message", + '''<b>If you want only the contents\ + of the folder to be added press "Yes".\ + If you want complete folder \ + to be added, press "No". </b>''', + QtWidgets.QMessageBox.Yes | QtWidgets.QMessageBox.No + ) + if reply == QtWidgets.QMessageBox.Yes: + self.cmd = "cp -a " + includefolder + "/. " + self.modelpath + self.obj_Appconfig.print_info('Adding Contents of the Folder') + elif reply == QtWidgets.QMessageBox.No: + self.cmd = "cp -R " + includefolder + " " + self.modelpath + self.obj_Appconfig.print_info('Adding the Folder') + + print("Adding the Folder:" + includefolder.split('/')[-1]) + self.termtitle("Adding the Folder:" + includefolder.split('/')[-1]) + + self.process = QtCore.QProcess(self) + self.process.start('sh', ['-c', self.cmd]) + self.termtext("Command: " + self.cmd) + self.process \ + .readyReadStandardOutput.connect(self.readAllStandard) + self.process.waitForFinished(50000) + print("Added the folder") + # os.chdir(self.cur_dir) + + # This function is used to print the titles in the terminal of Ngveri tab + def termtitle(self, textin): + + Text = "<span style=\" font-size:20pt; \ + font-weight:1000; color:#0000FF;\" >" + Text += "<br>================================<br>" + Text += textin + Text += "<br>================================<br>" + Text += "</span>" + self.termedit.append(Text) + + # This function is used to print the text/commands in the terminal of + # Ngveri tab + def termtext(self, textin): + + Text = "<span style=\" font-size:12pt;\ + font-weight:500; color:#000000;\" >" + Text += textin + Text += "</span>" + self.termedit.append(Text) + + # This function reads all the Standard output data and the errors from the + # process that aree being run + @QtCore.pyqtSlot() + def readAllStandard(self): + # self.termedit = termedit + # self.termedit.append(str(self.process.readAll().data(),\ + # encoding='utf-8')) + stdoutput = self.process.readAll() + TextStdOut = "<span style=\" font-size:12pt;\ + font-weight:300; color:#000000;\" >" + for line in str(stdoutput.data(), encoding='utf-8').split("\n"): + TextStdOut += "<br>" + line + TextStdOut += "</span>" + self.termedit.append(TextStdOut) + # print(str(self.process.readAll().data(), encoding='utf-8')) + + stderror = self.process.readAllStandardError() + if stderror.toUpper().contains(b"ERROR"): + self.errorFlag = True + TextErr = "<span style=\" font-size:12pt; \ + font-weight:1000; color:#ff0000;\" >" + for line in str(stderror.data(), encoding='utf-8').split("\n"): + TextErr += "<br>" + line + TextErr += "</span>" + self.termedit.append(TextErr) + # @QtCore.pyqtSlot() + # def readAllStandard(self): + # #self.termedit = termedit + # self.termedit.append(str(self.process.\ + # readAll().data(), encoding='utf-8')) + + # print(str(self.process.readAll().data(), encoding='utf-8')) + # stderror = self.process.readAllStandardError() + # if stderror.toUpper().contains(b"ERROR"): + # self.errorFlag = True + # Text = "<span style=\" font-size:12pt;\ + # font-weight:1000; color:#ff0000;\" >" + # for line in str(stderror.data(), encoding='utf-8').split("\n"): + # Text += "<br>"+line+"<br>" + # Text += "</span>" + # self.termedit.append(Text+"\n") + + # init_path = '../../' + # if os.name == 'nt': + # init_path = '' + # includefile = QtCore.QDir.toNativeSeparators(\ + # QtWidgets.QFileDialog.getOpenFileName( + # self, "Open adding other necessary files to be included", + # init_path + "home" + # )[0] + # ) + # if includefile=="": + # reply=QtWidgets.QMessageBox.critical( + # None, "Error Message", + # "<b>Error: No File Chosen. Please chose a file</b>", + # QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel + # ) + # if reply == QtWidgets.QMessageBox.Ok: + # self.addfile() + # self.obj_Appconfig.print_info('Add Other Files Called') + + # elif reply == QtWidgets.QMessageBox.Cancel: + # self.obj_Appconfig.print_info('No File Chosen') + # filename = os.path.basename(includefile) + # self.modelpath=self.digital_home+"/"+self.fname.split('.')[0]+"/" + + # if not os.path.isdir(self.modelpath): + # os.mkdir(self.modelpath) + # text = open(includefile).read() + # open(self.modelpath+filename,'w').write(text) + # includefile.close() diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py new file mode 100755 index 00000000..4a221964 --- /dev/null +++ b/src/maker/NgVeri.py @@ -0,0 +1,428 @@ +# ========================================================================= +# FILE: NgVeri.py +# +# USAGE: --- +# +# DESCRIPTION: This define all components of the NgVeri Tab. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Sumanto Kar, sumantokar@iitb.ac.in, FOSSEE, IIT Bombay +# ACKNOWLEDGEMENTS: Rahul Paknikar, rahulp@iitb.ac.in, FOSSEE, IIT Bombay +# Digvijay Singh, digvijay.singh@iitb.ac.in, FOSSEE, IIT Bombay +# Prof. Maheswari R. and Team, VIT Chennai +# GUIDED BY: Steve Hoover, Founder Redwood EDA +# Kunal Ghosh, VLSI System Design Corp.Pvt.Ltd +# Anagha Ghosh, VLSI System Design Corp.Pvt.Ltd +# OTHER CONTRIBUTERS: +# Prof. Madhuri Kadam, Shree L. R. Tiwari College of Engineering +# Rohinth Ram, Madras Institue of Technology +# Charaan S., Madras Institue of Technology +# Nalinkumar S., Madras Institue of Technology +# ORGANIZATION: eSim Team at FOSSEE, IIT Bombay +# CREATED: Monday 29, November 2021 +# REVISION: Tuesday 25, January 2022 +# ========================================================================= + + +# importing the files and libraries +from PyQt5 import QtCore, QtWidgets +from . import Maker +from . import ModelGeneration +import os +import shutil +from configuration.Appconfig import Appconfig +from configparser import ConfigParser + + +# beginning class NgVeri. This class create the NgVeri Tab +class NgVeri(QtWidgets.QWidget): + + # initialising the variables + def __init__(self, filecount): + QtWidgets.QWidget.__init__(self) + # Maker.addverilog(self) + self.obj_Appconfig = Appconfig() + + if os.name == 'nt': + self.home = os.path.join('library', 'config') + else: + self.home = os.path.expanduser('~') + + self.parser = ConfigParser() + self.parser.read(os.path.join( + self.home, os.path.join('.nghdl', 'config.ini'))) + self.nghdl_home = self.parser.get('NGHDL', 'NGHDL_HOME') + self.release_dir = self.parser.get('NGHDL', 'RELEASE') + self.src_home = self.parser.get('SRC', 'SRC_HOME') + self.licensefile = self.parser.get('SRC', 'LICENSE') + self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL') + self.digital_home = self.digital_home + "/Ngveri" + self.count = 0 + self.text = "" + self.entry_var = {} + self.createNgveriWidget() + self.fname = "" + self.filecount = filecount + + # Creating the various components of the Widget(Ngveri Tab) + + def createNgveriWidget(self): + + self.grid = QtWidgets.QGridLayout() + self.setLayout(self.grid) + + self.grid.addWidget(self.createoptionsBox(), 0, 0, QtCore.Qt.AlignTop) + self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + + self.show() + + # Adding the verilog file in Maker tab to Ngveri Tab automatically + def addverilog(self): + # b=Maker.Maker(self) + print(Maker.verilogFile) + if Maker.verilogFile[self.filecount] == "": + reply = QtWidgets.QMessageBox.critical( + None, + "Error Message", + "<b>Error: No Verilog File Chosen. \ + Please choose a verilog file in Makerchip Tab</b>", + QtWidgets.QMessageBox.Ok) + if reply == QtWidgets.QMessageBox.Ok: + self.obj_Appconfig.print_error( + 'No Verilog File Chosen. ' + 'Please choose a verilog file in Makerchip Tab' + ) + return + + self.fname = Maker.verilogFile[self.filecount] + currentTermLogs = QtWidgets.QTextEdit() + model = ModelGeneration.ModelGeneration(self.fname, currentTermLogs) + file = (os.path.basename(self.fname)).split('.')[0] + if self.entry_var[1].findText(file) == -1: + self.entry_var[1].addItem(file) + + if not Maker.makerchipTOSAccepted(True): + QtWidgets.QMessageBox.warning( + None, "Warning Message", + "Please accept the Makerchip Terms of Service " + "to proceed further.", + QtWidgets.QMessageBox.Ok + ) + + return + + try: + model.verilogfile() + error = model.verilogParse() + if error != "Error": + model.getPortInfo() + model.cfuncmod() + model.ifspecwrite() + model.sim_main_header() + model.sim_main() + model.modpathlst() + model.run_verilator() + model.make_verilator() + model.copy_verilator() + model.runMake() + + if os.name != 'nt': + model.runMakeInstall() + else: + try: + shutil.copy( + self.release_dir + + "/src/xspice/icm/Ngveri/Ngveri.cm", + self.nghdl_home + "/lib/ngspice/" + ) + except FileNotFoundError as err: + currentTermLogs.append( + "Error in copying Ngveri code model: " + str(err) + ) + + if "error" not in currentTermLogs.toPlainText().lower(): + currentTermLogs.append(''' + <p style=\" font-size:16pt; font-weight:1000; + color:#00FF00;\"> Model Created Successfully! + </p> + ''') + + except BaseException as err: + currentTermLogs.append( + "Error in Ngspice code model generation " + + "from Verilog: " + str(err) + ) + + if "error" in currentTermLogs.toPlainText().lower(): + currentTermLogs.append(''' + <p style=\" font-size:16pt; font-weight:1000; + color:#FF0000;\">There was an error during model creation, + <br/>Please rectify the error and try again! + </p> + ''') + + self.entry_var[0].append(currentTermLogs.toHtml()) + + # Force scroll the terminal widget at bottom + self.entry_var[0].verticalScrollBar().setValue( + self.entry_var[0].verticalScrollBar().maximum() + ) + + def addfile(self): + ''' + This function is used to add additional files required + by the verilog top module + ''' + if len(Maker.verilogFile) < (self.filecount + 1): + reply = QtWidgets.QMessageBox.critical( + None, + "Error Message", + "<b>Error: No Verilog File Chosen. \ + Please choose a verilog file in Makerchip Tab</b>", + QtWidgets.QMessageBox.Ok) + if reply == QtWidgets.QMessageBox.Ok: + self.obj_Appconfig.print_error( + 'No Verilog File Chosen. Please choose \ + a verilog file in Makerchip Tab') + return + + self.fname = Maker.verilogFile[self.filecount] + model = ModelGeneration.ModelGeneration(self.fname, self.entry_var[0]) + # model.verilogfile() + model.addfile() + + # This function is used to add additional folder required by the verilog + # top module + def addfolder(self): + if len(Maker.verilogFile) < (self.filecount + 1): + reply = QtWidgets.QMessageBox.critical( + None, + "Error Message", + "<b>Error: No Verilog File Chosen. \ + Please choose a verilog file in Makerchip Tab</b>", + QtWidgets.QMessageBox.Ok) + if reply == QtWidgets.QMessageBox.Ok: + self.obj_Appconfig.print_error( + 'No Verilog File Chosen. Please choose \ + a verilog file in Makerchip Tab') + return + self.fname = Maker.verilogFile[self.filecount] + model = ModelGeneration.ModelGeneration(self.fname, self.entry_var[0]) + # model.verilogfile() + model.addfolder() + + # This function is used to clear the terminal + + def clearTerminal(self): + self.entry_var[0].setText("") + + # This function is used to create buttons/options + def createoptionsBox(self): + + self.optionsbox = QtWidgets.QGroupBox() + self.optionsbox.setTitle("Select Options") + self.optionsgrid = QtWidgets.QGridLayout() + + self.optionsgroupbtn = QtWidgets.QButtonGroup() + + self.addverilogbutton = QtWidgets.QPushButton( + "Convert Verilog to Ngspice") + self.addverilogbutton.setToolTip( + "Requires internet connection for converting TL-Verilog models" + ) + self.addverilogbutton.setToolTipDuration(5000) + self.optionsgroupbtn.addButton(self.addverilogbutton) + self.addverilogbutton.clicked.connect(self.addverilog) + self.optionsgrid.addWidget(self.addverilogbutton, 0, 1) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + + self.addfilebutton = QtWidgets.QPushButton("Add dependency files") + self.optionsgroupbtn.addButton(self.addfilebutton) + self.addfilebutton.clicked.connect(self.addfile) + self.optionsgrid.addWidget(self.addfilebutton, 0, 2) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + + self.addfolderbutton = QtWidgets.QPushButton("Add dependency folder") + self.optionsgroupbtn.addButton(self.addfolderbutton) + self.addfolderbutton.clicked.connect(self.addfolder) + self.optionsgrid.addWidget(self.addfolderbutton, 0, 3) + # self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + + self.clearTerminalBtn = QtWidgets.QPushButton("Clear Terminal") + self.optionsgroupbtn.addButton(self.clearTerminalBtn) + self.clearTerminalBtn.clicked.connect(self.clearTerminal) + self.optionsgrid.addWidget(self.clearTerminalBtn, 0, 4) + self.optionsbox.setLayout(self.optionsgrid) + # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) + + return self.optionsbox + + # This function is used to remove models in modlst of Ngspice folder if + # the user wants to remove a model. Note: files do not get removed + def edit_modlst(self, text): + if text == "Remove Verilog Models": + return + index = self.entry_var[1].findText(text) + self.entry_var[1].removeItem(index) + self.entry_var[1].setCurrentIndex(0) + ret = QtWidgets.QMessageBox.warning( + None, "Warning", '''<b>Do you want to remove the model: ''' + + text, + QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel + ) + if ret == QtWidgets.QMessageBox.Ok: + mod = open(self.digital_home + '/modpath.lst', 'r') + data = mod.readlines() + mod.close() + + data.remove(text + "\n") + mod = open(self.digital_home + '/modpath.lst', 'w') + for item in data: + mod.write(item) + self.fname = Maker.verilogFile[self.filecount] + model = ModelGeneration.ModelGeneration( + self.fname, self.entry_var[0]) + + try: + model.runMake() + + if os.name != 'nt': + model.runMakeInstall() + else: + shutil.copy( + self.release_dir + "/src/xspice/icm/Ngveri/Ngveri.cm", + self.nghdl_home + "/lib/ngspice/" + ) + except BaseException as err: + QtWidgets.QMessageBox.critical( + None, "Error Message", + "The verilog model '" + str(text) + + "' could not be removed: " + str(err), + QtWidgets.QMessageBox.Ok + ) + + def lint_off_edit(self, text): + ''' + This is to remove lint_off comments needed by the verilator warnings. + This function writes to the lint_off.txt in the library/tlv folder. + ''' + init_path = '../../' + if os.name == 'nt': + init_path = '' + + if text == "Remove lint_off": + return + index = self.entry_var[2].findText(text) + self.entry_var[2].removeItem(index) + self.entry_var[2].setCurrentIndex(0) + ret = QtWidgets.QMessageBox.warning( + None, + "Warning", + '''<b>Do you want to remove the lint off error: ''' + + text, + QtWidgets.QMessageBox.Ok, + QtWidgets.QMessageBox.Cancel) + + if ret == QtWidgets.QMessageBox.Ok: + file = open(init_path + "library/tlv/lint_off.txt", 'r') + data = file.readlines() + file.close() + + data.remove(text + "\n") + file = open(init_path + "library/tlv/lint_off.txt", 'w') + for item in data: + file.write(item) + + def add_lint_off(self): + ''' + This is to add lint_off comments needed by the verilator warnings. + This function writes to the lint_off.txt in the library/tlv folder. + ''' + init_path = '../../' + if os.name == 'nt': + init_path = '' + + text = self.entry_var[3].text() + + if self.entry_var[2].findText(text) == -1: + self.entry_var[2].addItem(text) + file = open(init_path + "library/tlv/lint_off.txt", 'a+') + file.write(text + "\n") + file.close() + self.entry_var[3].setText("") + + # creating various other groups like terminal, remove modlst, remove lint_off + # and add lint_off + + def creategroup(self): + + self.trbox = QtWidgets.QGroupBox() + self.trbox.setTitle("Terminal") + # self.trbox.setDisabled(True) + # self.trbox.setVisible(False) + self.trgrid = QtWidgets.QGridLayout() + self.trbox.setLayout(self.trgrid) + self.count = 0 + + self.start = QtWidgets.QLabel("Terminal") + # self.trgrid.addWidget(self.start, 2,0) + self.entry_var[self.count] = QtWidgets.QTextEdit() + self.entry_var[self.count].setReadOnly(1) + self.trgrid.addWidget(self.entry_var[self.count], 1, 1, 5, 3) + self.entry_var[self.count].setMaximumWidth(1000) + self.entry_var[self.count].setMaximumHeight(1000) + self.count += 1 + + self.entry_var[self.count] = QtWidgets.QComboBox() + self.entry_var[self.count].addItem("Remove Verilog Models") + self.modlst = open(self.digital_home + '/modpath.lst', 'r') + self.data = self.modlst.readlines() + self.modlst.close() + for item in self.data: + if item != "\n": + self.entry_var[self.count].addItem(item.strip()) + self.entry_var[self.count].activated[str].connect(self.edit_modlst) + self.trgrid.addWidget(self.entry_var[self.count], 1, 4, 1, 2) + self.count += 1 + self.entry_var[self.count] = QtWidgets.QComboBox() + self.entry_var[self.count].addItem("Remove lint_off") + + init_path = '../../' + if os.name == 'nt': + init_path = '' + self.lint_off = open(init_path + "library/tlv/lint_off.txt", 'r') + + self.data = self.lint_off.readlines() + self.lint_off.close() + for item in self.data: + if item != "\n": + self.entry_var[self.count].addItem(item.strip()) + self.entry_var[self.count].activated[str].connect(self.lint_off_edit) + self.trgrid.addWidget(self.entry_var[self.count], 2, 4, 1, 2) + self.count += 1 + self.entry_var[self.count] = QtWidgets.QLineEdit(self) + self.trgrid.addWidget(self.entry_var[self.count], 3, 4) + self.entry_var[self.count].setMaximumWidth(100) + self.count += 1 + self.entry_var[self.count] = QtWidgets.QPushButton("Add lint_off") + self.entry_var[self.count].setMaximumWidth(100) + self.trgrid.addWidget(self.entry_var[self.count], 3, 5) + self.entry_var[self.count].clicked.connect(self.add_lint_off) + + self.count += 1 + + # CSS + self.trbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: \ + 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: \ + 10px; padding: 0 3px 0 3px; } \ + ") + + return self.trbox diff --git a/src/maker/__init__.py b/src/maker/__init__.py new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/src/maker/__init__.py diff --git a/src/maker/createkicad.py b/src/maker/createkicad.py new file mode 100644 index 00000000..af30cee0 --- /dev/null +++ b/src/maker/createkicad.py @@ -0,0 +1,347 @@ +# ========================================================================= +# FILE: createkicad.py +# +# USAGE: --- +# +# DESCRIPTION: This define all components of to create the Kicad Library. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Sumanto Kar, sumantokar@iitb.ac.in, FOSSEE, IIT Bombay +# ACKNOWLEDGEMENTS: Rahul Paknikar, rahulp@iitb.ac.in, FOSSEE, IIT Bombay +# Digvijay Singh, digvijay.singh@iitb.ac.in, FOSSEE, IIT Bombay +# Prof. Maheswari R. and Team, VIT Chennai +# GUIDED BY: Steve Hoover, Founder Redwood EDA +# Kunal Ghosh, VLSI System Design Corp.Pvt.Ltd +# Anagha Ghosh, VLSI System Design Corp.Pvt.Ltd +# OTHER CONTRIBUTERS: +# Prof. Madhuri Kadam, Shree L. R. Tiwari College of Engineering +# Rohinth Ram, Madras Institue of Technology +# Charaan S., Madras Institue of Technology +# Nalinkumar S., Madras Institue of Technology +# ORGANIZATION: eSim Team at FOSSEE, IIT Bombay +# CREATED: Monday 29, November 2021 +# REVISION: Tuesday 25, January 2022 +# ========================================================================= + +# importing the files and libraries +from . import Appconfig +import re +import os +import xml.etree.cElementTree as ET +from PyQt5 import QtWidgets + +# beginning the AutoSchematic Class + + +class AutoSchematic: + + # initialising the variables here + def init(self, modelname, modelpath): + self.App_obj = Appconfig.Appconfig() + self.modelname = modelname.split('.')[0] + self.template = self.App_obj.kicad_lib_template.copy() + self.xml_loc = self.App_obj.xml_loc + self.lib_loc = self.App_obj.lib_loc + self.modelpath = modelpath + if os.name == 'nt': + eSim_src = self.App_obj.src_home + inst_dir = eSim_src.replace('\\eSim', '') + self.kicad_ngveri_lib = \ + inst_dir + '/KiCad/share/kicad/library/eSim_Ngveri.lib' + else: + self.kicad_ngveri_lib = '/usr/share/kicad/library/eSim_Ngveri.lib' + # self.parser = self.App_obj.parser_ngveri + + # creating KiCAD library using this function + def createkicad(self): + + xmlFound = None + # read_file = open(self.modelpath+'connection_info.txt', 'r') + # data = read_file.readlines() + # print(data) + xmlFound = None + for root, dirs, files in os.walk(self.xml_loc): + if (str(self.modelname) + '.xml') in files: + xmlFound = root + print(xmlFound) + break + + if xmlFound is None: + self.getPortInformation() + self.createXML() + self.createLib() + + elif (xmlFound == os.path.join(self.xml_loc, 'Ngveri')): + print('Library already exists...') + ret = QtWidgets.QMessageBox.warning( + None, "Warning", '''<b>Library files for this model''' + + ''' already exist. Do you want to overwrite it?</b><br/> + If yes press ok, else cancel it and ''' + + '''change the name of your verilog model.''', + QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel + ) + + if ret == QtWidgets.QMessageBox.Ok: + print("Overwriting existing libraries") + self.getPortInformation() + self.createXML() + self.removeOldLibrary() # Removes the existng library + self.createLib() + else: + print("Library Creation Cancelled") + return "Error" + + else: + print('Pre-existing library...') + ret = QtWidgets.QMessageBox.critical( + self.parent, "Error", '''<b>A standard library already ''' + + '''exists with this name.</b><br/><b>Please change the ''' + + '''name of your verilog model and add it again.</b>''', + QtWidgets.QMessageBox.Ok + ) + + # getting the port information here + def getPortInformation(self): + portInformation = PortInfo(self, self.modelpath) + portInformation.getPortInfo() + self.portInfo = portInformation.bit_list + self.input_length = portInformation.input_len + self.portName = portInformation.port_name + + # creating the XML files in eSim-2.2/library/modelParamXML/Ngveri + def createXML(self): + cwd = os.getcwd() + xmlDestination = os.path.join(self.xml_loc, 'Ngveri') + self.splitText = "" + for bit in self.portInfo[:-1]: + self.splitText += bit + "-V:" + self.splitText += self.portInfo[-1] + "-V" + + print("changing directory to ", xmlDestination) + os.chdir(xmlDestination) + + root = ET.Element("model") + ET.SubElement(root, "name").text = self.modelname + ET.SubElement(root, "type").text = "Ngveri" + ET.SubElement(root, "node_number").text = str(len(self.portInfo)) + ET.SubElement(root, "title").text = ( + "Add parameters for " + str(self.modelname)) + ET.SubElement(root, "split").text = self.splitText + param = ET.SubElement(root, "param") + ET.SubElement(param, "rise_delay", default="1.0e-9").text = ( + "Enter Rise Delay (default=1.0e-9)") + ET.SubElement(param, "fall_delay", default="1.0e-9").text = ( + "Enter Fall Delay (default=1.0e-9)") + ET.SubElement(param, "input_load", default="1.0e-12").text = ( + "Enter Input Load (default=1.0e-12)") + ET.SubElement(param, "instance_id", default="1").text = ( + "Enter Instance ID (Between 0-99)") + + tree = ET.ElementTree(root) + tree.write(str(self.modelname) + '.xml') + print("Leaving the directory ", xmlDestination) + os.chdir(cwd) + + # Calculates the maximum between input and output ports + def findBlockSize(self): + ind = self.input_length + return max( + self.char_sum(self.portInfo[:ind]), + self.char_sum(self.portInfo[ind:]) + ) + + def char_sum(self, ls): + return sum([int(x) for x in ls]) + + # removing the old library + def removeOldLibrary(self): + cwd = os.getcwd() + os.chdir(self.lib_loc) + print("Changing directory to ", self.lib_loc) + f = open(self.kicad_ngveri_lib) + lines = f.readlines() + f.close() + + output = [] + line_reading_flag = False + + for line in lines: + if line.startswith("DEF"): + if line.split()[1] == self.modelname: + line_reading_flag = True + if not line_reading_flag: + output.append(line) + if line.startswith("ENDDEF"): + line_reading_flag = False + + f = open(self.kicad_ngveri_lib, 'w') + for line in output: + f.write(line) + + os.chdir(cwd) + print("Leaving directory, ", self.lib_loc) + + # creating the library + def createLib(self): + self.dist_port = 100 # Distance between two ports + self.inc_size = 100 # Increment size of a block + cwd = os.getcwd() + os.chdir(self.lib_loc) + print("Changing directory to ", self.lib_loc) + + lib_file = open(self.kicad_ngveri_lib, "a") + line1 = self.template["start_def"] + line1 = line1.split() + line1 = [w.replace('comp_name', self.modelname) for w in line1] + self.template["start_def"] = ' '.join(line1) + if os.stat(self.kicad_ngveri_lib).st_size == 0: + lib_file.write("EESchema-LIBRARY Version 2.3" + "\n\n") + # lib_file.write("#encoding utf-8"+ "\n"+ "#"+ "\n" + + # "#test_compo" + "\n"+ "#"+ "\n") + lib_file.write( + self.template["start_def"] + "\n" + self.template["U_field"] + "\n" + ) + + line3 = self.template["comp_name_field"] + line3 = line3.split() + line3 = [w.replace('comp_name', self.modelname) for w in line3] + self.template["comp_name_field"] = ' '.join(line3) + + lib_file.write(self.template["comp_name_field"] + "\n") + + line4 = self.template["blank_field"] + line4_1 = line4[0] + line4_2 = line4[1] + line4_1 = line4_1.split() + line4_1 = [w.replace('blank_quotes', '""') for w in line4_1] + line4_2 = line4_2.split() + line4_2 = [w.replace('blank_quotes', '""') for w in line4_2] + line4[0] = ' '.join(line4_1) + line4[1] = ' '.join(line4_2) + self.template["blank_qoutes"] = line4 + + lib_file.write( + line4[0] + "\n" + line4[1] + "\n" + + self.template["start_draw"] + "\n" + ) + + draw_pos = self.template["draw_pos"] + draw_pos = draw_pos.split() + draw_pos[4] = str( + int(draw_pos[4]) - self.findBlockSize() * self.inc_size) + self.template["draw_pos"] = ' '.join(draw_pos) + + lib_file.write(self.template["draw_pos"] + "\n") + + input_port = self.template["input_port"] + input_port = input_port.split() + output_port = self.template["output_port"] + output_port = output_port.split() + inputs = self.portInfo[0: self.input_length] + outputs = self.portInfo[self.input_length:] + inputName = [] + outputName = [] + + for i in range(self.input_length): + for j in range(int(inputs[i])): + inputName.append( + self.portName[i] + str(int(inputs[i]) - j - 1)) + + for i in range(self.input_length, len(self.portName)): + for j in range(int(outputs[i - self.input_length])): + outputName.append( + self.portName[i] + + str(int(outputs[i - self.input_length]) - j - 1)) + + # print("INPUTS AND OUTPUTS ") + # print("INPUTS:"+inputName) + # print("OUTPUTS:"outputName) + # print(inputs) + # print(outputs) + + inputs = self.char_sum(inputs) + outputs = self.char_sum(outputs) + + total = inputs + outputs + + port_list = [] + j = 0 + for i in range(total): + if (i < inputs): + input_port[1] = inputName[i] + input_port[2] = str(i + 1) + input_port[4] = str(int(input_port[4]) - self.dist_port) + input_list = ' '.join(input_port) + port_list.append(input_list) + j = j + 1 + + else: + output_port[1] = outputName[i - inputs] + output_port[2] = str(i + 1) + output_port[4] = str(int(output_port[4]) - self.dist_port) + output_list = ' '.join(output_port) + port_list.append(output_list) + + for ports in port_list: + lib_file.write(ports + "\n") + lib_file.write( + self.template["end_draw"] + "\n" + + self.template["end_def"] + "\n\n\n" + ) + + os.chdir(cwd) + + +# beginning the PortInfo Class containing Port Information +class PortInfo: + + # initialising the variables + def __init__(self, model, modelpath): + self.modelname = model.modelname + # self.model_loc = model.parser.get('NGVERI', 'DIGITAL_MODEL') + self.bit_list = [] + self.port_name = [] + self.input_len = 0 + self.modelpath = modelpath + + # getting the port information from connection_info.txt + def getPortInfo(self): + input_list = [] + output_list = [] + read_file = open(self.modelpath + 'connection_info.txt', 'r') + data = read_file.readlines() + # print(data) + read_file.close() + + for line in data: + if re.match(r'^\s*$', line): + pass + else: + in_items = re.findall( + "INPUT", line, re.MULTILINE | re.IGNORECASE + ) + inout_items = re.findall( + "INOUT", line, re.MULTILINE | re.IGNORECASE + ) + + out_items = re.findall( + "OUTPUT", line, re.MULTILINE | re.IGNORECASE + ) + if in_items: + input_list.append(line.split()) + if inout_items: + input_list.append(line.split()) + if out_items: + output_list.append(line.split()) + # print(input_list) + # print(output_list) + for in_list in input_list: + self.bit_list.append(in_list[2]) + self.port_name.append(in_list[0]) + self.input_len = len(self.bit_list) + for out_list in output_list: + self.bit_list.append(out_list[2]) + self.port_name.append(out_list[0]) diff --git a/src/maker/makerchip.py b/src/maker/makerchip.py new file mode 100755 index 00000000..152c6cbb --- /dev/null +++ b/src/maker/makerchip.py @@ -0,0 +1,95 @@ +# ========================================================================= +# FILE: makerchip.py +# +# USAGE: --- +# +# DESCRIPTION: This defines all components of the Makerchip. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Sumanto Kar, sumantokar@iitb.ac.in, FOSSEE, IIT Bombay +# ACKNOWLEDGEMENTS: Rahul Paknikar, rahulp@iitb.ac.in, FOSSEE, IIT Bombay +# Digvijay Singh, digvijay.singh@iitb.ac.in, FOSSEE, IIT Bombay +# Prof. Maheswari R. and Team, VIT Chennai +# GUIDED BY: Steve Hoover, Founder Redwood EDA +# Kunal Ghosh, VLSI System Design Corp.Pvt.Ltd +# Anagha Ghosh, VLSI System Design Corp.Pvt.Ltd +# OTHER CONTRIBUTERS: +# Prof. Madhuri Kadam, Shree L. R. Tiwari College of Engineering +# Rohinth Ram, Madras Institue of Technology +# Charaan S., Madras Institue of Technology +# Nalinkumar S., Madras Institue of Technology +# ORGANIZATION: eSim Team at FOSSEE, IIT Bombay +# CREATED: Monday 29, November 2021 +# REVISION: Tuesday 25, January 2022 +# ========================================================================= + +# importing the files and libraries +from PyQt5 import QtWidgets +from . import Maker +from . import NgVeri + +# filecount is used to count thenumber of objects created +filecount = 0 + + +# This class creates objects for creating the Maker and the Ngveri tabs +class makerchip(QtWidgets.QWidget): + + # initialising the variables + def __init__(self, parent=None): + QtWidgets.QWidget.__init__(self) + + # filecount=int(open("a.txt",'r').read()) + print(filecount) + # self.splitter.setOrientation(QtCore.Qt.Vertical) + print("==================================") + print("Makerchip and Verilog to Ngspice Converter") + print("==================================") + self.createMainWindow() + + # Creating the main Window(Main tab) + + def createMainWindow(self): + self.vbox = QtWidgets.QVBoxLayout() + self.hbox = QtWidgets.QHBoxLayout() + self.hbox.addStretch(1) + self.vbox.addWidget(self.createWidget()) + self.vbox.addLayout(self.hbox) + + self.setLayout(self.vbox) + self.setWindowTitle("Makerchip and Verilog to Ngspice Converter") + self.show() + + # Creating the maker and ngveri widgets + def createWidget(self): + global obj_Maker + global filecount + self.convertWindow = QtWidgets.QWidget() + + self.MakerTab = QtWidgets.QScrollArea() + obj_Maker = Maker.Maker(filecount) + self.MakerTab.setWidget(obj_Maker) + self.MakerTab.setWidgetResizable(True) + + global obj_NgVeri + self.NgVeriTab = QtWidgets.QScrollArea() + obj_NgVeri = NgVeri.NgVeri(filecount) + self.NgVeriTab.setWidget(obj_NgVeri) + self.NgVeriTab.setWidgetResizable(True) + self.tabWidget = QtWidgets.QTabWidget() + self.tabWidget.addTab(self.MakerTab, "Makerchip") + self.tabWidget.addTab(self.NgVeriTab, "NgVeri") + # The object refresh gets destroyed when Ngspice\ + # to verilog converter is called + # so calling refresh_change to start toggling of refresh again + self.tabWidget.currentChanged.connect(obj_Maker.refresh_change) + self.mainLayout = QtWidgets.QVBoxLayout() + self.mainLayout.addWidget(self.tabWidget) + self.convertWindow.setLayout(self.mainLayout) + self.convertWindow.show() + # incrementing filecount for every new window + filecount = filecount + 1 + return self.convertWindow diff --git a/src/ngspiceSimulation/NgspiceWidget.py b/src/ngspiceSimulation/NgspiceWidget.py index 8114f56d..8c63a22a 100644 --- a/src/ngspiceSimulation/NgspiceWidget.py +++ b/src/ngspiceSimulation/NgspiceWidget.py @@ -23,24 +23,25 @@ class NgspiceWidget(QtWidgets.QWidget): print("Argument to ngspice command : ", command) if os.name == 'nt': # For Windows OS - home = os.path.expanduser("~") - parser_nghdl = ConfigParser() - parser_nghdl.read(os.path.join( - home, os.path.join('.nghdl', 'config.ini'))) + parser_nghdl.read( + os.path.join('library', 'config', '.nghdl', 'config.ini') + ) - msys_bin = parser_nghdl.get('COMPILER', 'MSYS_HOME') + msys_home = parser_nghdl.get('COMPILER', 'MSYS_HOME') tempdir = os.getcwd() projPath = self.obj_appconfig.current_project["ProjectName"] os.chdir(projPath) self.command = 'cmd /c '+'"start /min ' + \ - msys_bin + "/mintty.exe ngspice -p " + command + '"' + msys_home + "/usr/bin/mintty.exe ngspice -p " + command + '"' self.process.start(self.command) os.chdir(tempdir) else: # For Linux OS - self.command = "cd " + projPath + ";ngspice " + command + self.command = "cd " + projPath + \ + ";ngspice -r " + command.replace(".cir.out", ".raw") + \ + " " + command # Creating argument for process self.args = ['-hold', '-e', self.command] self.process.start('xterm', self.args) @@ -51,3 +52,7 @@ class NgspiceWidget(QtWidgets.QWidget): [self.obj_appconfig.current_project['ProjectName']].append( self.process.pid()) ) + self.process = QtCore.QProcess(self) + self.command = "gaw " + command.replace(".cir.out", ".raw") + self.process.start('sh', ['-c', self.command]) + print(self.command) diff --git a/src/ngspicetoModelica/ModelicaUI.py b/src/ngspicetoModelica/ModelicaUI.py index 6cd736b7..a687bb93 100644..100755 --- a/src/ngspicetoModelica/ModelicaUI.py +++ b/src/ngspicetoModelica/ModelicaUI.py @@ -28,7 +28,7 @@ class OpenModelicaEditor(QtWidgets.QWidget): self.FileEdit.setText(self.ngspiceNetlist) self.grid.addWidget(self.FileEdit, 0, 0) - self.browsebtn = QtWidgets.QPushButton("Browse") + self.browsebtn = QtWidgets.QPushButton("Browse Netlist (*.cir.out)") self.browsebtn.clicked.connect(self.browseFile) self.grid.addWidget(self.browsebtn, 0, 1) @@ -40,10 +40,29 @@ class OpenModelicaEditor(QtWidgets.QWidget): self.loadOMbtn.clicked.connect(self.callOMEdit) self.grid.addWidget(self.loadOMbtn, 3, 1) + self.OMPathtext = QtWidgets.QLineEdit() + self.OMPathtext.setText("") + self.grid.addWidget(self.OMPathtext, 4, 0) + + self.OMPathbrowsebtn = QtWidgets.QPushButton("Browse OM") + self.OMPathbrowsebtn.clicked.connect(self.OMPathbrowseFile) + self.grid.addWidget(self.OMPathbrowsebtn, 4, 1) + # self.setGeometry(300, 300, 350, 300) self.setLayout(self.grid) self.show() + def OMPathbrowseFile(self): + temp = QtCore.QDir.toNativeSeparators( + QtWidgets.QFileDialog.getExistingDirectory( + self, "Open OpenModelica Directory", "home" + ) + ) + + if temp: + self.OMPath = temp + self.OMPathtext.setText(self.OMPath) + def browseFile(self): temp = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getOpenFileName( @@ -216,16 +235,17 @@ class OpenModelicaEditor(QtWidgets.QWidget): def callOMEdit(self): - if self.obj_validation.validateTool("OMEdit"): + try: modelFiles = glob.glob(self.modelicaNetlist) modelFiles = ' '.join(file for file in modelFiles) - self.cmd2 = "OMEdit " + modelFiles + self.cmd2 = self.OMPath+"/OMEdit " + modelFiles + print(self.cmd2) self.obj_workThread2 = Worker.WorkerThread(self.cmd2) self.obj_workThread2.start() print("OMEdit called") self.obj_appconfig.print_info("OMEdit called") - else: + except BaseException: self.msg = QtWidgets.QMessageBox() self.msgContent = ( "There was an error while opening OMEdit.<br/>" diff --git a/src/ngspicetoModelica/NgspicetoModelica.py b/src/ngspicetoModelica/NgspicetoModelica.py index 4df65c8d..6951e3c8 100644..100755 --- a/src/ngspicetoModelica/NgspicetoModelica.py +++ b/src/ngspicetoModelica/NgspicetoModelica.py @@ -344,7 +344,7 @@ class NgMoConverter: stat = self.mappingData["Sources"][sourceType][typ[0]] +\ ' ' + compName + '(offset = ' +\ self.getUnitVal(typ[1]) +\ - ', V = ' + self.getUnitVal(words[4]) + ', freqHz = ' +\ + ', V = ' + self.getUnitVal(words[4]) + ', f = ' +\ self.getUnitVal(words[5]) + ', startTime = ' +\ self.getUnitVal(words[6]) + ', phase = ' +\ self.getUnitVal(theta[0]) + ');' diff --git a/src/ngspicetoModelica/__init__.py b/src/ngspicetoModelica/__init__.py index e69de29b..e69de29b 100644..100755 --- a/src/ngspicetoModelica/__init__.py +++ b/src/ngspicetoModelica/__init__.py diff --git a/src/projManagement/Kicad.py b/src/projManagement/Kicad.py index 8f25b732..8c92c06b 100644 --- a/src/projManagement/Kicad.py +++ b/src/projManagement/Kicad.py @@ -96,11 +96,11 @@ class Kicad: self.msg.setWindowTitle("Error Message") self.msg.showMessage( 'Please select the project first. You can either ' + - 'create new project or open existing project') + 'create new project or open an existing project') self.msg.exec_() self.obj_appconfig.print_warning( 'Please select the project first. You can either ' + - 'create new project or open existing project') + 'create new project or open an existing project') ''' # Commenting as it is no longer needed as PCB and Layout will open from @@ -133,10 +133,10 @@ class Kicad: self.msg.setModal(True) self.msg.setWindowTitle("Error Message") self.msg.showMessage('Please select the project first. You can' - + 'either create new project or open existing project') + + 'either create new project or open an existing project') self.msg.exec_() self.obj_appconfig.print_warning('Please select the project' - + 'first. You can either create new project or open existing' + + 'first. You can either create new project or open an existing' + 'project') def openLayout(self): @@ -166,10 +166,10 @@ class Kicad: self.msg.setModal(True) self.msg.setWindowTitle("Error Message") self.msg.showMessage('Please select the project first. You can' - + 'either create new project or open existing project') + + 'either create new project or open an existing project') self.msg.exec_() self.obj_appconfig.print_warning('Please select the project' - + 'first. You can either create new project or open existing' + + 'first. You can either create new project or open an existing' + 'project') ''' @@ -226,8 +226,8 @@ class Kicad: self.msg.setWindowTitle("Error Message") self.msg.showMessage( 'Please select the project first. You can either ' + - 'create new project or open existing project') + 'create new project or open an existing project') self.msg.exec_() self.obj_appconfig.print_warning( 'Please select the project first. You can either ' + - 'create new project or open existing project') + 'create new project or open an existing project') diff --git a/src/projManagement/Worker.py b/src/projManagement/Worker.py index 970bfccd..6ff1e361 100644 --- a/src/projManagement/Worker.py +++ b/src/projManagement/Worker.py @@ -16,7 +16,7 @@ # REVISION: Sunday 16 August 2020 # ========================================================================= -from PyQt5 import QtCore +from PyQt5 import QtCore, QtWidgets import subprocess from configuration.Appconfig import Appconfig @@ -97,7 +97,25 @@ class WorkerThread(QtCore.QThread): """ procThread = Appconfig() + projDir = procThread.current_project["ProjectName"] + + if (projDir is None) and ('nghdl' not in command): + msg = QtWidgets.QErrorMessage() + msg.setModal(True) + msg.setWindowTitle("Error Message") + msg.showMessage( + 'Please select the project first. You can either ' + + 'create a new project or open an existing project.' + ) + msg.exec_() + + return + proc = subprocess.Popen(command.split()) + + if 'nghdl' in command: + return + self.my_workers.append(proc) procThread.procThread_list.append(proc) procThread.proc_dict[procThread.current_project['ProjectName']].append( |
