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diff --git a/INSTALL b/INSTALL new file mode 100644 index 00000000..4860d95b --- /dev/null +++ b/INSTALL @@ -0,0 +1,48 @@ + +eSim installation instructions +================================= + +Table of contents + + 1. eSim installation in Ubuntu (LINUX) + + 2. eSim installation in Windows + + + +1. eSim installation in Ubuntu. + + After downloading eSim, extract it using: + + $ unzip eSim.zip + + Now change directories in to the top-level source directory (where this INSTALL file can be found). + + To install eSim and other dependecies run the following command. + + $ ./install-linux.sh --install + + Above script will install eSim along with dependencies. + + Please report any eSim installation related issue/error at forums.fossee.in + + How to Run eSim + ================= + + A. Through Terminal + $ esim + + B. Double click eSim desktop icon + + C. From command line : Do `cd src/fronEnd` and type `python2 Application.py` to open eSim. + + +2. eSim installation in Windows + + After downloading eSim for Windows from esim.fossee.in , extract it. + + Now right click the `Setup.exe` and `run it as Administrator`. And then follow the instruction. + + Note : Please make you run it as administrator otherwise it won't set the environment variable properly. + + diff --git a/Installation_Sheet_eSim.pdf b/Installation_Sheet_eSim.pdf Binary files differnew file mode 100644 index 00000000..fd44d784 --- /dev/null +++ b/Installation_Sheet_eSim.pdf diff --git a/LICENSE b/LICENSE new file mode 100644 index 00000000..6b156fe1 --- /dev/null +++ b/LICENSE @@ -0,0 +1,675 @@ +GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see <http://www.gnu.org/licenses/>. + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + {project} Copyright (C) {year} {fullname} + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +<http://www.gnu.org/licenses/>. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +<http://www.gnu.org/philosophy/why-not-lgpl.html>. + diff --git a/README.md b/README.md new file mode 100644 index 00000000..8170bd80 --- /dev/null +++ b/README.md @@ -0,0 +1,27 @@ +##eSim + +eSim is an open source EDA tool for circuit design, simulation, analysis and PCB design, developed by FOSSEE team at IIT Bombay. +It is an integrated tool build using open source software such as Kicad (http://www.kicad-pcd.org), Ngspice (http://ngspice.sourcefouge.net/) +It is released under GNU GPL License. It runs on Ubuntu Linux, Windows XP and Windows. + +eSim has been successfully ported to low cost FOSSEE laptop (http://laptop.fossee.in) + +##Pre-requisites +1. Python 2.7 +2. PyQt4 +3. Matplotlib +4. NgSpice v.26 +5. Kicad 4.0.7 (Latest Version build on July-14) + +## eSim Installation Ubuntu +Refer INSTALL file for eSim installation on Ubuntu. + + +## For using the Cvpcb feature of KiCad in offline/online mode: +Whether to look for footprints locally or through github is decided by fp-lib-table file. +Currently we are forcing all users to look for footprints locally, by placing a fp-lib-table in the ~/.config/kicad/ directory. [Read copyKicadLibrary function in install-linux.sh] +If you wish to use the Cvpcb tool[access the footprints available on kicad's github repo], open the fp-lib-table using gedit/text editors and replace the word "KISYSMOD" with "KIGITHUB", and replace the word "KiCad" with "Github" throughout the file. + +Two footprints are stored locally in /usr/share/kicad/modules/Connectors_Terminal_Blocks.pretty/ +and /usr/share/kicad/modules/TO_SOT_Packages_THT.pretty/ to keep eSim compliant with the Spoken Tutorials created. + diff --git a/VERSION b/VERSION new file mode 100644 index 00000000..879ef789 --- /dev/null +++ b/VERSION @@ -0,0 +1,3 @@ +1.0.0 +1.0.1 +1.0.2 diff --git a/esim-start.sh b/esim-start.sh new file mode 100755 index 00000000..1b83b81d --- /dev/null +++ b/esim-start.sh @@ -0,0 +1,3 @@ +#!/bin/bash +cd /home/rahul/Downloads/eSim-1.1.2/src/frontEnd +python2 Application.py diff --git a/esim.desktop b/esim.desktop new file mode 100755 index 00000000..dacaac74 --- /dev/null +++ b/esim.desktop @@ -0,0 +1,15 @@ +[Desktop Entry] +Version=1.0.2 +Name=eSim +Comment=EDA Tools +GenericName=eSim +Keywords=eda-tools +Exec=esim %u +Terminal=false +X-MultipleArgs=false +Type=Application +Icon=/home/fossee/.esim/logo.png +Categories=Development; +MimeType=text/html;text/xml;application/xhtml+xml;application/xml;application/rss+xml;application/rdf+xml;image/gif;image/jpeg;image/png;x-scheme-handler/http;x-scheme-handler/https;x-scheme-handler/ftp;x-scheme-handler/chrome;video/webm;application/x-xpinstall; +StartupNotify=true +Actions=NewWindow;NewPrivateWindow; diff --git a/images/Ps2Ki.png b/images/Ps2Ki.png Binary files differnew file mode 100644 index 00000000..f58756b7 --- /dev/null +++ b/images/Ps2Ki.png diff --git a/images/branch-closed.png b/images/branch-closed.png Binary files differnew file mode 100644 index 00000000..213ffdd8 --- /dev/null +++ b/images/branch-closed.png diff --git a/images/branch-end.png b/images/branch-end.png Binary files differnew file mode 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files differnew file mode 100644 index 00000000..e3dee87a --- /dev/null +++ b/images/warning.png diff --git a/kicadSchematicLibrary/eSim_Analog.dcm b/kicadSchematicLibrary/eSim_Analog.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Analog.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Analog.lib b/kicadSchematicLibrary/eSim_Analog.lib new file mode 100644 index 00000000..16797d6f --- /dev/null +++ b/kicadSchematicLibrary/eSim_Analog.lib @@ -0,0 +1,234 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# climit +# +DEF climit U 0 40 Y Y 1 F N +F0 "U" -150 100 51 H V C CNN +F1 "climit" -100 -100 51 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X CIN1 2 -50 350 200 D 50 43 1 1 I +X CIN2 3 100 -300 200 U 50 43 1 1 I +X OUT 4 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dt +# +DEF d_dt U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_dt" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# divide +# +DEF divide U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "divide" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X NUM 1 -400 150 200 R 50 50 1 1 I +X DEN 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# gain +# +DEF gain U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "gain" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# hyst +# +DEF hyst U 0 40 Y Y 1 F N +F0 "U" 0 0 47 H V C CNN +F1 "hyst" 0 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -150 150 150 -50 0 1 0 N +X IN 1 -350 50 200 R 50 39 1 1 I +X OUT 2 350 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# ilimit +# +DEF ilimit U 0 40 Y Y 1 F N +F0 "U" -150 100 51 H V C CNN +F1 "ilimit" -100 -100 51 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X PWR1 2 -50 350 200 D 50 43 1 1 B +X PWR2 3 100 -300 200 U 50 43 1 1 B +X OUT 4 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# int +# +DEF int U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "int" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# mult +# +DEF mult U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "mult" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN1 1 -400 150 200 R 50 50 1 1 I +X IN2 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# slew +# +DEF slew U 0 40 Y Y 1 F N +F0 "U" 0 0 47 H V C CNN +F1 "slew" 0 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -150 150 150 -50 0 1 0 N +X IN 1 -350 50 200 R 50 39 1 1 I +X OUT 2 350 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# summer +# +DEF summer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "summer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN1 1 -400 150 200 R 50 50 1 1 I +X IN2 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# TRANSFO +# +DEF TRANSFO U 0 40 Y N 1 F N +F0 "U" 0 250 50 H V C CNN +F1 "TRANSFO" 0 -300 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +A -100 -150 50 899 1 0 1 0 N -100 -100 -50 -150 +A -100 -150 50 -1 -899 0 1 0 N -50 -150 -100 -199 +A -100 -50 50 899 1 0 1 0 N -100 0 -50 -50 +A -100 -50 50 -1 -899 0 1 0 N -50 -50 -100 -99 +A -100 50 50 899 1 0 1 0 N -100 100 -50 50 +A -100 50 50 -1 -899 0 1 0 N -50 50 -100 1 +A -100 150 50 899 1 0 1 0 N -100 200 -50 150 +A -100 150 50 -1 -899 0 1 0 N -50 150 -100 101 +A 100 -50 50 899 -1799 0 1 0 N 100 0 51 -50 +A 100 -50 50 1799 -899 0 1 0 N 51 -50 100 -99 +A 100 50 50 899 -1799 0 1 0 N 100 100 51 50 +A 100 50 50 1799 -899 0 1 0 N 51 50 100 1 +A 100 150 50 899 -1799 0 1 0 N 100 200 51 150 +A 100 150 50 1799 -899 0 1 0 N 51 150 100 101 +A 101 -150 50 910 -1799 0 1 0 N 101 -100 52 -150 +A 101 -150 50 -912 -1799 0 1 0 N 101 -199 52 -150 +P 2 0 1 0 -25 200 -25 -200 N +P 2 0 1 0 25 -200 25 200 N +X AA 1 -400 200 300 R 50 50 1 1 P +X AB 2 -400 -200 300 R 50 50 1 1 P +X SA 3 400 -200 300 L 50 50 1 1 P +X SB 4 400 200 300 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Devices.bak b/kicadSchematicLibrary/eSim_Devices.bak new file mode 100644 index 00000000..be133df8 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Devices.bak @@ -0,0 +1,253 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_L +# +DEF eSim_L L 0 40 N N 1 F N +F0 "L" 1950 500 50 H V C CNN +F1 "eSim_L" 1950 650 50 H V C CNN +F2 "" 1950 550 60 V V C CNN +F3 "" 1950 550 60 V V C CNN +DRAW +A 1802 550 48 11 1789 0 1 0 N 1849 551 1754 551 +A 1899 550 51 11 1789 0 1 0 N 1949 551 1848 551 +A 1999 550 51 11 1789 0 1 0 N 2049 551 1948 551 +A 2100 550 50 11 1789 0 1 0 N 2149 551 2050 551 +X 1 1 1650 550 100 R 70 70 1 1 P +X 2 2 2250 550 100 L 70 70 1 1 P +ENDDRAW +ENDDEF +# +# eSim_LED +# +DEF eSim_LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_LED" 50 -100 31 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + LED* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 -50 -50 50 N +P 2 0 1 0 -50 0 50 0 N +P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N +P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N +P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N +X A 1 150 0 100 L 50 50 1 1 P +X K 2 -150 0 100 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PJF +# +DEF eSim_PJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_PJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 -45 0 -5 15 -5 -15 -45 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Devices.bck b/kicadSchematicLibrary/eSim_Devices.bck new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Devices.bck @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Devices.dcm b/kicadSchematicLibrary/eSim_Devices.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Devices.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Devices.lib b/kicadSchematicLibrary/eSim_Devices.lib new file mode 100644 index 00000000..978dfc81 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Devices.lib @@ -0,0 +1,253 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_L +# +DEF eSim_L L 0 40 N N 1 F N +F0 "L" 1950 500 50 H V C CNN +F1 "eSim_L" 1950 650 50 H V C CNN +F2 "" 1950 550 60 V V C CNN +F3 "" 1950 550 60 V V C CNN +DRAW +A 1802 550 48 11 1789 0 1 0 N 1849 551 1754 551 +A 1899 550 51 11 1789 0 1 0 N 1949 551 1848 551 +A 1999 550 51 11 1789 0 1 0 N 2049 551 1948 551 +A 2100 550 50 11 1789 0 1 0 N 2149 551 2050 551 +X 1 1 1650 550 100 R 70 70 1 1 P +X 2 2 2250 550 100 L 70 70 1 1 P +ENDDRAW +ENDDEF +# +# eSim_LED +# +DEF eSim_LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_LED" 50 -100 31 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + LED* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 -50 -50 50 N +P 2 0 1 0 -50 0 50 0 N +P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N +P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N +P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N +X A 1 150 0 100 L 50 50 1 1 P +X K 2 -150 0 100 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PJF +# +DEF eSim_PJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_PJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 -45 0 -5 15 -5 -15 -45 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Digital.dcm b/kicadSchematicLibrary/eSim_Digital.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Digital.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Digital.lib b/kicadSchematicLibrary/eSim_Digital.lib new file mode 100644 index 00000000..ff53d004 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Digital.lib @@ -0,0 +1,384 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_dlatch +# +DEF d_dlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dlatch" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X EN 2 -550 -300 200 R 50 50 1 1 I +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_fdiv +# +DEF d_fdiv U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "d_fdiv" 0 600 60 H V C CNN +F2 "" 0 500 60 H V C CNN +F3 "" 0 500 60 H V C CNN +DRAW +S -400 650 500 400 0 1 0 N +X Fre_IN 1 -600 500 200 R 50 50 1 1 I +X Fre_OUT 2 700 500 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_jkff +# +DEF d_jkff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_jkff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X J 1 -800 400 200 R 50 50 1 1 I +X K 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_pulldown +# +DEF d_pulldown U 0 40 Y Y 1 F N +F0 "U" 0 200 60 H V C CNN +F1 "d_pulldown" -50 300 55 H V C CNN +F2 "" 0 200 60 H V C CNN +F3 "" 0 200 60 H V C CNN +DRAW +S 200 350 -300 150 0 1 0 N +X OUT 1 -500 250 200 R 50 43 1 1 I +ENDDRAW +ENDDEF +# +# d_pullup +# +DEF d_pullup U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_pullup" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 200 150 -300 -50 0 1 0 N +X OUT 1 -500 50 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# d_ram +# +DEF d_ram U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_ram" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -300 0 1 0 N +X DIN1 1 -250 -500 200 U 50 43 1 1 I +X DIN2 2 -200 -500 200 U 50 43 1 1 I +X DIN3 3 -150 -500 200 U 50 43 1 1 I +X DIN4 4 -100 -500 200 U 50 43 1 1 I +X DOUT1 5 250 -500 200 U 50 43 1 1 O +X DOUT2 6 200 -500 200 U 50 43 1 1 O +X DOUT3 7 150 -500 200 U 50 43 1 1 O +X DOUT4 8 100 -500 200 U 50 43 1 1 O +X A1 9 -150 600 200 D 50 43 1 1 I +X A2 10 -100 600 200 D 50 43 1 1 I +X CS3 20 -500 150 200 R 50 43 1 1 I +X A3 11 -50 600 200 D 50 43 1 1 I +X A4 12 0 600 200 D 50 43 1 1 I +X A5 13 50 600 200 D 50 43 1 1 I +X A6 14 100 600 200 D 50 43 1 1 I +X A7 15 150 600 200 D 50 43 1 1 I +X A8 16 200 600 200 D 50 43 1 1 I +X WR_EN 17 500 200 200 L 50 43 1 1 I +X CS1 18 -500 250 200 R 50 43 1 1 I +X CS2 19 -500 200 200 R 50 43 1 1 I +ENDDRAW +ENDDEF +# +# d_source +# +DEF d_source U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_source" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 450 -50 0 1 0 N +X OUT1 1 650 150 200 L 50 43 1 1 O +X OUT2 2 650 100 200 L 50 43 1 1 O +X OUT3 3 650 50 200 L 50 43 1 1 O +X OUT4 4 650 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +# d_srff +# +DEF d_srff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_state +# +DEF d_state U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_state" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 400 -50 0 1 0 N +X IN1 1 -550 250 200 R 50 43 1 1 I +X IN2 2 -550 200 200 R 50 43 1 1 I +X IN3 3 -550 150 200 R 50 43 1 1 I +X IN4 4 -550 100 200 R 50 43 1 1 I +X CLK 5 600 50 200 L 50 43 1 1 I C +X RST 6 600 200 200 L 50 43 1 1 I +X OUT1 7 -150 550 200 D 50 43 1 1 O +X OUT2 8 -100 550 200 D 50 43 1 1 O +X OUT3 9 -50 550 200 D 50 43 1 1 O +X OUT4 10 0 550 200 D 50 43 1 1 O +X OUT5 11 50 550 200 D 50 43 1 1 O +X OUT6 12 100 550 200 D 50 43 1 1 O +X OUT7 13 150 550 200 D 50 43 1 1 O +X OUT8 14 200 550 200 D 50 43 1 1 O +ENDDRAW +ENDDEF +# +# d_tff +# +DEF d_tff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_tff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X T 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Out 5 550 350 200 L 50 50 1 1 O +X Nout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Hybrid.dcm b/kicadSchematicLibrary/eSim_Hybrid.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Hybrid.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Hybrid.lib b/kicadSchematicLibrary/eSim_Hybrid.lib new file mode 100644 index 00000000..e793288d --- /dev/null +++ b/kicadSchematicLibrary/eSim_Hybrid.lib @@ -0,0 +1,340 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_5 +# +DEF adc_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_6 +# +DEF adc_bridge_6 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_6" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -500 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X OUT1 7 550 50 200 L 50 50 1 1 O +X OUT2 8 550 -50 200 L 50 50 1 1 O +X OUT3 9 550 -150 200 L 50 50 1 1 O +X OUT4 10 550 -250 200 L 50 50 1 1 O +X OUT5 11 550 -350 200 L 50 50 1 1 O +X OUT6 12 550 -450 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_7 +# +DEF adc_bridge_7 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_7" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -600 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X OUT1 8 550 50 200 L 50 50 1 1 O +X OUT2 9 550 -50 200 L 50 50 1 1 O +X OUT3 10 550 -150 200 L 50 50 1 1 O +X OUT4 11 550 -250 200 L 50 50 1 1 O +X OUT5 12 550 -350 200 L 50 50 1 1 O +X OUT6 13 550 -450 200 L 50 50 1 1 O +X OUT7 14 550 -550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_3 +# +DEF dac_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_6 +# +DEF dac_bridge_6 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_6" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -500 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X OUT1 7 550 50 200 L 50 50 1 1 O +X OUT2 8 550 -50 200 L 50 50 1 1 O +X OUT3 9 550 -150 200 L 50 50 1 1 O +X OUT4 10 550 -250 200 L 50 50 1 1 O +X OUT5 11 550 -350 200 L 50 50 1 1 O +X OUT6 12 550 -450 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_7 +# +DEF dac_bridge_7 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_7" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -600 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X OUT1 8 550 50 200 L 50 50 1 1 O +X OUT2 9 550 -50 200 L 50 50 1 1 O +X OUT3 10 550 -150 200 L 50 50 1 1 O +X OUT4 11 550 -250 200 L 50 50 1 1 O +X OUT5 12 550 -350 200 L 50 50 1 1 O +X OUT6 13 550 -450 200 L 50 50 1 1 O +X OUT7 14 550 -550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Miscellaneous.dcm b/kicadSchematicLibrary/eSim_Miscellaneous.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Miscellaneous.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Miscellaneous.lib b/kicadSchematicLibrary/eSim_Miscellaneous.lib new file mode 100644 index 00000000..f12f1dac --- /dev/null +++ b/kicadSchematicLibrary/eSim_Miscellaneous.lib @@ -0,0 +1,129 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# IC +# +DEF IC U 0 40 Y Y 1 F N +F0 "U" 300 150 60 H V C CNN +F1 "IC" 250 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 5 0 1 0 200 300 100 250 200 200 300 250 200 300 N +X ~ 1 200 50 146 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_1PinConn +# +DEF eSim_1PinConn J 0 40 Y N 1 F N +F0 "J" 0 100 50 H V C CNN +F1 "eSim_1PinConn" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_??x*mm* + Connector*:*1x??x*mm* + Pin?Header?Straight?1X* + Pin?Header?Angled?1X* + Socket?Strip?Straight?1X* + Socket?Strip?Angled?1X* +$ENDFPLIST +DRAW +S -50 5 0 -5 1 1 6 N +S -50 50 50 -50 1 1 10 f +X Pin_1 1 -200 0 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_2PinConn +# +DEF eSim_2PinConn J 0 40 Y N 1 F N +F0 "J" 0 100 50 H V C CNN +F1 "eSim_2PinConn" 0 -200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_??x*mm* + Connector*:*1x??x*mm* + Pin?Header?Straight?1X* + Pin?Header?Angled?1X* + Socket?Strip?Straight?1X* + Socket?Strip?Angled?1X* +$ENDFPLIST +DRAW +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 50 50 -150 1 1 10 f +X Pin_1 1 -200 0 150 R 50 50 1 1 P +X Pin_2 2 -200 -100 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_3PinConn +# +DEF eSim_3PinConn J 0 40 Y N 1 F N +F0 "J" 0 200 50 H V C CNN +F1 "eSim_3PinConn" 0 -200 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_??x*mm* + Connector*:*1x??x*mm* + Pin?Header?Straight?1X* + Pin?Header?Angled?1X* + Socket?Strip?Straight?1X* + Socket?Strip?Angled?1X* +$ENDFPLIST +DRAW +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 105 0 95 1 1 6 N +S -50 150 50 -150 1 1 10 f +X Pin_1 1 -200 100 150 R 50 50 1 1 P +X Pin_2 2 -200 0 150 R 50 50 1 1 P +X Pin_3 3 -200 -100 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_PSpice.dcm b/kicadSchematicLibrary/eSim_PSpice.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_PSpice.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_PSpice.lib b/kicadSchematicLibrary/eSim_PSpice.lib new file mode 100644 index 00000000..788f6b6d --- /dev/null +++ b/kicadSchematicLibrary/eSim_PSpice.lib @@ -0,0 +1,13556 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# +5V_PSPICE +# +DEF +5V_PSPICE #PWR 0 30 Y Y 1 F N +F0 "#PWR" 0 0 30 H V L CNN +F1 "+5V_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 100 0 0 1 0 N +C 0 130 30 0 1 0 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# -5V_PSPICE +# +DEF -5V_PSPICE #PWR 0 30 Y Y 1 F N +F0 "#PWR" 0 0 30 H V L CNN +F1 "-5V_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 100 0 0 1 0 N +C 0 130 30 0 1 0 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 00_PSPICE +# +DEF 00_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "00_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 01_PSPICE +# +DEF 01_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "01_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 02_PSPICE +# +DEF 02_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "02_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 03_PSPICE +# +DEF 03_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "03_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 04_PSPICE +# +DEF 04_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "04_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 O +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 05_PSPICE +# +DEF 05_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "05_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 06_PSPICE +# +DEF 06_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "06_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 07_PSPICE +# +DEF 07_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "07_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 08_PSPICE +# +DEF 08_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "08_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 09_PSPICE +# +DEF 09_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "09_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 100_PSPICE +# +DEF 100_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "100_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ C 0 0 100 R 30 30 0 1 I +X ~ D1 0 -100 100 R 30 30 0 1 I +X ~ Q1 600 -100 100 L 30 30 0 1 O +X ~ D2 0 -200 100 R 30 30 0 1 I +X ~ Q2 600 -200 100 L 30 30 0 1 O +X ~ D3 0 -300 100 R 30 30 0 1 I +X ~ Q3 600 -300 100 L 30 30 0 1 O +X ~ D4 0 -400 100 R 30 30 0 1 I +X ~ Q4 600 -400 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 107_PSPICE +# +DEF 107_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "107_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 600 -300 100 L 30 30 0 1 O +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 109_PSPICE +# +DEF 109_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "109_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \K\ 0 -400 100 R 30 30 0 1 I +X ~ \Q\ 600 -300 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 10_PSPICE +# +DEF 10_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "10_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 110_PSPICE +# +DEF 110_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "110_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -800 0 1 0 N +X ~ Q 600 -200 100 L 30 30 0 1 O +X ~ J1 0 0 100 R 30 30 0 1 I +X ~ K1 0 -400 100 R 30 30 0 1 I +X ~ J2 0 -100 100 R 30 30 0 1 I +X ~ K2 0 -500 100 R 30 30 0 1 I +X ~ J3 0 -200 100 R 30 30 0 1 I +X ~ K3 0 -600 100 R 30 30 0 1 I +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -300 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -400 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 111_PSPICE +# +DEF 111_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "111_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -300 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 11_PSPICE +# +DEF 11_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "11_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 121_PSPICE +# +DEF 121_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "121_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -700 0 1 0 N +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ Q 700 -200 100 L 30 30 0 1 P +X ~ A1 0 -400 100 R 30 30 0 1 P +X ~ A2 0 -500 100 R 30 30 0 1 P +X ~ GND 300 -800 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 700 -400 100 L 30 30 0 1 P +X ~ RINT 0 -100 100 R 30 30 0 1 P +X ~ CEXT 0 -200 100 R 30 30 0 1 P +X ~ REXT/CEXT 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 122_PSPICE +# +DEF 122_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "122_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -900 0 1 0 N +X ~ Q 700 -200 100 L 30 30 0 1 P +X ~ A1 0 -400 100 R 30 30 0 1 P +X ~ B1 0 -600 100 R 30 30 0 1 P +X ~ A2 0 -500 100 R 30 30 0 1 P +X ~ B2 0 -700 100 R 30 30 0 1 P +X ~ GND 200 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 700 -400 100 L 30 30 0 1 P +X ~ \CLR\ 300 -1000 100 U 30 30 0 1 P +X ~ RINT 0 -100 100 R 30 30 0 1 P +X ~ CEXT 0 -200 100 R 30 30 0 1 P +X ~ REXT/CEXT 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 123_PSPICE +# +DEF 123_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "123_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -600 0 1 0 N +X ~ A 0 -300 100 R 30 30 0 1 P +X ~ B 0 -400 100 R 30 30 0 1 P +X ~ Q 700 -100 100 L 30 30 0 1 P +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 700 -300 100 L 30 30 0 1 P +X ~ \CLR\ 300 -700 100 U 30 30 0 1 P +X ~ CEXT 0 -100 100 R 30 30 0 1 P +X ~ REXT/CEXT 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 125_PSPICE +# +DEF 125_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "125_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -160 40 0 1 0 N +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -140 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 126_PSPICE +# +DEF 126_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "126_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -200 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ G 0 0 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 128_PSPICE +# +DEF 128_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "128_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A -250 -90 400 -308 283 0 1 0 N 93 -295 101 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 100 -300 300 -300 N +P 2 0 1 0 100 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 12_PSPICE +# +DEF 12_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "12_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 132_PSPICE +# +DEF 132_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "132_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 136_PSPICE +# +DEF 136_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "136_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A -250 -90 400 -308 283 0 1 0 N 93 -295 101 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 100 -300 300 -300 N +P 2 0 1 0 100 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 13_PSPICE +# +DEF 13_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "13_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 200 -150 350 -150 N +P 2 0 1 0 250 -250 250 -150 N +P 2 0 1 0 350 -150 350 -250 N +P 2 0 1 0 400 -250 250 -250 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 145_PSPICE +# +DEF 145_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "145_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -900 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ B 0 -200 100 R 30 30 0 1 P +X ~ C 0 -400 100 R 30 30 0 1 P +X ~ D 0 -600 100 R 30 30 0 1 P +X ~ Y0 600 100 100 L 30 30 0 1 P +X ~ Y1 600 0 100 L 30 30 0 1 P +X ~ Y2 600 -100 100 L 30 30 0 1 P +X ~ Y3 600 -200 100 L 30 30 0 1 P +X ~ Y4 600 -300 100 L 30 30 0 1 P +X ~ Y5 600 -400 100 L 30 30 0 1 P +X ~ Y6 600 -500 100 L 30 30 0 1 P +X ~ Y7 600 -600 100 L 30 30 0 1 P +X ~ Y8 600 -700 100 L 30 30 0 1 P +X ~ Y9 600 -800 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 147_PSPICE +# +DEF 147_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "147_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A 600 -100 100 L 30 30 0 1 P +X ~ B 600 -300 100 L 30 30 0 1 P +X ~ C 600 -500 100 L 30 30 0 1 P +X ~ D 600 -700 100 L 30 30 0 1 P +X ~ IN1 0 0 100 R 30 30 0 1 P +X ~ IN2 0 -100 100 R 30 30 0 1 P +X ~ IN3 0 -200 100 R 30 30 0 1 P +X ~ IN4 0 -300 100 R 30 30 0 1 P +X ~ IN5 0 -400 100 R 30 30 0 1 P +X ~ IN6 0 -500 100 R 30 30 0 1 P +X ~ IN7 0 -600 100 R 30 30 0 1 P +X ~ IN8 0 -700 100 R 30 30 0 1 P +X ~ IN9 0 -800 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 148_PSPICE +# +DEF 148_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "148_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A0 600 0 100 L 30 30 0 1 P +X ~ A1 600 -200 100 L 30 30 0 1 P +X ~ A2 600 -400 100 L 30 30 0 1 P +X ~ EI 0 -800 100 R 30 30 0 1 P +X ~ EO 600 -800 100 L 30 30 0 1 P +X ~ GS 600 -600 100 L 30 30 0 1 P +X ~ IN0 0 0 100 R 30 30 0 1 P +X ~ IN1 0 -100 100 R 30 30 0 1 P +X ~ IN2 0 -200 100 R 30 30 0 1 P +X ~ IN3 0 -300 100 R 30 30 0 1 P +X ~ IN4 0 -400 100 R 30 30 0 1 P +X ~ IN5 0 -500 100 R 30 30 0 1 P +X ~ IN6 0 -600 100 R 30 30 0 1 P +X ~ IN7 0 -700 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 14_PSPICE +# +DEF 14_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "14_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 140 40 260 40 N +P 2 0 1 0 180 -40 180 40 N +P 2 0 1 0 260 40 260 -40 N +P 2 0 1 0 300 -40 180 -40 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 O +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 151A_PSPICE +# +DEF 151A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "151A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ Z 600 -300 100 L 30 30 0 1 O +X ~ I0 0 -200 100 R 30 30 0 1 I +X ~ S0 0 -1100 100 R 30 30 0 1 I +X ~ I1 0 -300 100 R 30 30 0 1 I +X ~ S1 0 -1200 100 R 30 30 0 1 I +X ~ I2 0 -400 100 R 30 30 0 1 I +X ~ S2 0 -1300 100 R 30 30 0 1 I +X ~ I3 0 -500 100 R 30 30 0 1 I +X ~ I4 0 -600 100 R 30 30 0 1 I +X ~ I5 0 -700 100 R 30 30 0 1 I +X ~ I6 0 -800 100 R 30 30 0 1 I +X ~ I7 0 -900 100 R 30 30 0 1 I +X ~ GND 300 -1500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \E\ 0 0 100 R 30 30 0 1 I +X ~ \Z\ 600 -700 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 152_PSPICE +# +DEF 152_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "152_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1200 0 1 0 N +X ~ A 0 -900 100 R 30 30 0 1 I +X ~ B 0 -1000 100 R 30 30 0 1 I +X ~ C 0 -1100 100 R 30 30 0 1 I +X ~ W 600 -500 100 L 30 30 0 1 O +X ~ D0 0 0 100 R 30 30 0 1 I +X ~ D1 0 -100 100 R 30 30 0 1 I +X ~ D2 0 -200 100 R 30 30 0 1 I +X ~ D3 0 -300 100 R 30 30 0 1 I +X ~ D4 0 -400 100 R 30 30 0 1 I +X ~ D5 0 -500 100 R 30 30 0 1 I +X ~ D6 0 -600 100 R 30 30 0 1 I +X ~ D7 0 -700 100 R 30 30 0 1 I +X ~ GND 300 -1300 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 153A_PSPICE +# +DEF 153A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "153A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ S0 0 0 100 R 30 30 0 1 I +X ~ S1 0 -100 100 R 30 30 0 1 I +X ~ ZA 600 -500 100 L 30 30 0 1 O +X ~ ZB 600 -1100 100 L 30 30 0 1 O +X ~ I0A 0 -400 100 R 30 30 0 1 I +X ~ I1A 0 -500 100 R 30 30 0 1 I +X ~ I2A 0 -600 100 R 30 30 0 1 I +X ~ I3A 0 -700 100 R 30 30 0 1 I +X ~ I0B 0 -1000 100 R 30 30 0 1 I +X ~ I1B 0 -1100 100 R 30 30 0 1 I +X ~ I2B 0 -1200 100 R 30 30 0 1 I +X ~ I3B 0 -1300 100 R 30 30 0 1 I +X ~ GND 300 -1500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \EA\ 0 -300 100 R 30 30 0 1 I +X ~ \EB\ 0 -900 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 154_PSPICE +# +DEF 154_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "154_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1600 0 1 0 N +X ~ A 0 -600 100 R 30 30 0 1 I +X ~ B 0 -800 100 R 30 30 0 1 I +X ~ C 0 -1000 100 R 30 30 0 1 I +X ~ D 0 -1200 100 R 30 30 0 1 I +X ~ Y0 600 0 100 L 30 30 0 1 O +X ~ Y1 600 -100 100 L 30 30 0 1 O +X ~ Y2 600 -200 100 L 30 30 0 1 O +X ~ Y3 600 -300 100 L 30 30 0 1 O +X ~ Y4 600 -400 100 L 30 30 0 1 O +X ~ Y5 600 -500 100 L 30 30 0 1 O +X ~ Y6 600 -600 100 L 30 30 0 1 O +X ~ Y7 600 -700 100 L 30 30 0 1 O +X ~ Y8 600 -800 100 L 30 30 0 1 O +X ~ Y9 600 -900 100 L 30 30 0 1 O +X ~ Y10 600 -1000 100 L 30 30 0 1 O +X ~ Y11 600 -1100 100 L 30 30 0 1 O +X ~ Y12 600 -1200 100 L 30 30 0 1 O +X ~ Y13 600 -1300 100 L 30 30 0 1 O +X ~ Y14 600 -1400 100 L 30 30 0 1 O +X ~ Y15 600 -1500 100 L 30 30 0 1 O +X ~ GND 300 -1700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 I +X ~ \G\2 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 155_PSPICE +# +DEF 155_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "155_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ B 0 -400 100 R 30 30 0 1 I +X ~ 1C 0 -100 100 R 30 30 0 1 I +X ~ 1Y0 600 0 100 L 30 30 0 1 O +X ~ 2Y0 600 -400 100 L 30 30 0 1 O +X ~ 1Y1 600 -100 100 L 30 30 0 1 O +X ~ 2Y1 600 -500 100 L 30 30 0 1 O +X ~ 1Y2 600 -200 100 L 30 30 0 1 O +X ~ 2Y2 600 -600 100 L 30 30 0 1 O +X ~ 1Y3 600 -300 100 L 30 30 0 1 O +X ~ 2Y3 600 -700 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 2\C\ 0 -700 100 R 30 30 0 1 I +X ~ 1\G\ 0 0 100 R 30 30 0 1 I +X ~ 2\G\ 0 -600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 156_PSPICE +# +DEF 156_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "156_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ B 0 -400 100 R 30 30 0 1 I +X ~ 1C 0 -100 100 R 30 30 0 1 I +X ~ 1Y0 600 0 100 L 30 30 0 1 O +X ~ 2Y0 600 -400 100 L 30 30 0 1 O +X ~ 1Y1 600 -100 100 L 30 30 0 1 O +X ~ 2Y1 600 -500 100 L 30 30 0 1 O +X ~ 1Y2 600 -200 100 L 30 30 0 1 O +X ~ 2Y2 600 -600 100 L 30 30 0 1 O +X ~ 1Y3 600 -300 100 L 30 30 0 1 O +X ~ 2Y3 600 -700 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 2\C\ 0 -700 100 R 30 30 0 1 I +X ~ 1\G\ 0 0 100 R 30 30 0 1 I +X ~ 2\G\ 0 -600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 157_PSPICE +# +DEF 157_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "157_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1100 0 1 0 N +X ~ 1A 0 0 100 R 30 30 0 1 P +X ~ 2A 0 -200 100 R 30 30 0 1 P +X ~ 3A 0 -400 100 R 30 30 0 1 P +X ~ 4A 0 -600 100 R 30 30 0 1 P +X ~ 1B 0 -100 100 R 30 30 0 1 P +X ~ 2B 0 -300 100 R 30 30 0 1 P +X ~ 3B 0 -500 100 R 30 30 0 1 P +X ~ 4B 0 -700 100 R 30 30 0 1 P +X ~ 1Y 700 -100 100 L 30 30 0 1 P +X ~ 2Y 700 -300 100 L 30 30 0 1 P +X ~ 3Y 700 -500 100 L 30 30 0 1 P +X ~ 4Y 700 -700 100 L 30 30 0 1 P +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SELECT\A\B 0 -1000 100 R 30 30 0 1 P +X ~ STROBE\G\ 0 -900 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 160_PSPICE +# +DEF 160_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "160_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 161_PSPICE +# +DEF 161_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "161_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 162_PSPICE +# +DEF 162_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "162_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 163_PSPICE +# +DEF 163_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "163_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 164_PSPICE +# +DEF 164_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "164_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 300 500 -700 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ QA 600 200 100 L 30 30 0 1 O +X ~ QB 600 100 100 L 30 30 0 1 O +X ~ QC 600 0 100 L 30 30 0 1 O +X ~ QD 600 -100 100 L 30 30 0 1 O +X ~ QE 600 -200 100 L 30 30 0 1 O +X ~ QF 600 -300 100 L 30 30 0 1 O +X ~ QG 600 -400 100 L 30 30 0 1 O +X ~ QH 600 -500 100 L 30 30 0 1 O +X ~ GND 200 -800 100 U 30 30 0 1 W +X ~ CLK 0 -400 100 R 30 30 0 1 I +X ~ PWR 300 400 100 D 30 30 0 1 W +X ~ \CLR\ 300 -800 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 16_PSPICE +# +DEF 16_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "16_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 173_PSPICE +# +DEF 173_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "173_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ M 0 -800 100 R 30 30 0 1 I +X ~ N 0 -900 100 R 30 30 0 1 I +X ~ 1D 0 -300 100 R 30 30 0 1 I +X ~ 2D 0 -400 100 R 30 30 0 1 I +X ~ 3D 0 -500 100 R 30 30 0 1 I +X ~ 4D 0 -600 100 R 30 30 0 1 I +X ~ 1Q 600 -300 100 L 30 30 0 1 O +X ~ 2Q 600 -400 100 L 30 30 0 1 O +X ~ 3Q 600 -500 100 L 30 30 0 1 O +X ~ 4Q 600 -600 100 L 30 30 0 1 O +X ~ GND 200 -1200 100 U 30 30 0 1 W +X ~ CLK 0 0 100 R 30 30 0 1 P +X ~ CLR 300 -1200 100 U 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 -100 100 R 30 30 0 1 I +X ~ \G\2 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 174_PSPICE +# +DEF 174_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "174_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ 1D 0 0 100 R 30 30 0 1 P +X ~ 2D 0 -100 100 R 30 30 0 1 P +X ~ 3D 0 -200 100 R 30 30 0 1 P +X ~ 4D 0 -300 100 R 30 30 0 1 P +X ~ 5D 0 -400 100 R 30 30 0 1 P +X ~ 6D 0 -500 100 R 30 30 0 1 P +X ~ 1Q 600 0 100 L 30 30 0 1 P +X ~ 2Q 600 -100 100 L 30 30 0 1 P +X ~ 3Q 600 -200 100 L 30 30 0 1 P +X ~ 4Q 600 -300 100 L 30 30 0 1 P +X ~ 5Q 600 -400 100 L 30 30 0 1 P +X ~ 6Q 600 -500 100 L 30 30 0 1 P +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -600 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -900 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 175_PSPICE +# +DEF 175_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "175_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ 1D 0 0 100 R 30 30 0 1 P +X ~ 2D 0 -200 100 R 30 30 0 1 P +X ~ 3D 0 -400 100 R 30 30 0 1 P +X ~ 4D 0 -600 100 R 30 30 0 1 P +X ~ 1Q 600 0 100 L 30 30 0 1 P +X ~ 2Q 600 -200 100 L 30 30 0 1 P +X ~ 3Q 600 -400 100 L 30 30 0 1 P +X ~ 4Q 600 -600 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +X ~ 1\Q\ 600 -100 100 L 30 30 0 1 P +X ~ 2\Q\ 600 -300 100 L 30 30 0 1 P +X ~ 3\Q\ 600 -500 100 L 30 30 0 1 P +X ~ 4\Q\ 600 -700 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 176_PSPICE +# +DEF 176_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "176_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -100 100 R 30 30 0 1 P +X ~ B 0 -200 100 R 30 30 0 1 P +X ~ C 0 -300 100 R 30 30 0 1 P +X ~ D 0 -400 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -200 100 L 30 30 0 1 P +X ~ QC 600 -300 100 L 30 30 0 1 P +X ~ QD 600 -400 100 L 30 30 0 1 P +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -500 100 R 30 30 0 1 P +X ~ CLK2 0 -600 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -900 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 177_PSPICE +# +DEF 177_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "177_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -100 100 R 30 30 0 1 P +X ~ B 0 -200 100 R 30 30 0 1 P +X ~ C 0 -300 100 R 30 30 0 1 P +X ~ D 0 -400 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -200 100 L 30 30 0 1 P +X ~ QC 600 -300 100 L 30 30 0 1 P +X ~ QD 600 -400 100 L 30 30 0 1 P +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -500 100 R 30 30 0 1 P +X ~ CLK2 0 -600 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -900 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 178_PSPICE +# +DEF 178_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "178_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -400 100 R 30 30 0 1 P +X ~ B 0 -500 100 R 30 30 0 1 P +X ~ C 0 -600 100 R 30 30 0 1 P +X ~ D 0 -700 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -900 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ LOAD 0 -100 100 R 30 30 0 1 P +X ~ SHIFT 0 -200 100 R 30 30 0 1 P +X ~ SERIAL 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 179_PSPICE +# +DEF 179_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "179_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ A 0 -400 100 R 30 30 0 1 P +X ~ B 0 -500 100 R 30 30 0 1 P +X ~ C 0 -600 100 R 30 30 0 1 P +X ~ D 0 -700 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1200 100 U 30 30 0 1 W +X ~ CLK 0 -900 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ LOAD 0 -100 100 R 30 30 0 1 P +X ~ \Q\D 600 -900 100 L 30 30 0 1 P +X ~ SHIFT 0 -200 100 R 30 30 0 1 P +X ~ SERIAL 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 17_PSPICE +# +DEF 17_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "17_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 180_PSPICE +# +DEF 180_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "180_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ B 0 -100 100 R 30 30 0 1 P +X ~ C 0 -200 100 R 30 30 0 1 P +X ~ D 0 -300 100 R 30 30 0 1 P +X ~ E 0 -400 100 R 30 30 0 1 P +X ~ F 0 -500 100 R 30 30 0 1 P +X ~ G 0 -600 100 R 30 30 0 1 P +X ~ H 0 -700 100 R 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ EVEN_IN 0 -800 100 R 30 30 0 1 P +X ~ EVEN_OUT 700 -200 100 L 30 30 0 1 P +X ~ ODD_IN 0 -900 100 R 30 30 0 1 P +X ~ ODD_OUT 700 -400 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 181_PSPICE +# +DEF 181_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "181_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 600 -1000 0 1 0 N +X ~ M 0 -900 100 R 30 30 0 1 P +X ~ S0 500 300 100 D 30 30 0 1 P +X ~ S1 400 300 100 D 30 30 0 1 P +X ~ S2 300 300 100 D 30 30 0 1 P +X ~ S3 200 300 100 D 30 30 0 1 P +X ~ CN 0 -800 100 R 30 30 0 1 P +X ~ A=B 700 -500 100 L 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 100 300 100 D 30 30 0 1 W +X ~ \G\ 700 -700 100 L 30 30 0 1 P +X ~ \P\ 700 -800 100 L 30 30 0 1 P +X ~ \A\0 0 0 100 R 30 30 0 1 P +X ~ \B\0 0 -400 100 R 30 30 0 1 P +X ~ \F\0 700 0 100 L 30 30 0 1 P +X ~ \A\1 0 -100 100 R 30 30 0 1 P +X ~ \B\1 0 -500 100 R 30 30 0 1 P +X ~ \F\1 700 -100 100 L 30 30 0 1 P +X ~ \A\2 0 -200 100 R 30 30 0 1 P +X ~ \B\2 0 -600 100 R 30 30 0 1 P +X ~ \F\2 700 -200 100 L 30 30 0 1 P +X ~ \A\3 0 -300 100 R 30 30 0 1 P +X ~ \B\3 0 -700 100 R 30 30 0 1 P +X ~ \F\3 700 -300 100 L 30 30 0 1 P +X ~ CN+4 700 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 182_PSPICE +# +DEF 182_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "182_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ CN 0 -800 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 600 -400 100 L 30 30 0 1 P +X ~ \P\ 600 -200 100 L 30 30 0 1 P +X ~ \G\0 0 -400 100 R 30 30 0 1 P +X ~ \P\0 0 0 100 R 30 30 0 1 P +X ~ \G\1 0 -500 100 R 30 30 0 1 P +X ~ \P\1 0 -100 100 R 30 30 0 1 P +X ~ \G\2 0 -600 100 R 30 30 0 1 P +X ~ \P\2 0 -200 100 R 30 30 0 1 P +X ~ \G\3 0 -700 100 R 30 30 0 1 P +X ~ \P\3 0 -300 100 R 30 30 0 1 P +X ~ CN+X 600 -600 100 L 30 30 0 1 P +X ~ CN+Y 600 -700 100 L 30 30 0 1 P +X ~ CN+Z 600 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 184_PSPICE +# +DEF 184_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "184_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -200 100 R 30 30 0 1 P +X ~ B 0 -300 100 R 30 30 0 1 P +X ~ C 0 -400 100 R 30 30 0 1 P +X ~ D 0 -500 100 R 30 30 0 1 P +X ~ E 0 -600 100 R 30 30 0 1 P +X ~ Y1 600 0 100 L 30 30 0 1 P +X ~ Y2 600 -100 100 L 30 30 0 1 P +X ~ Y3 600 -200 100 L 30 30 0 1 P +X ~ Y4 600 -300 100 L 30 30 0 1 P +X ~ Y5 600 -400 100 L 30 30 0 1 P +X ~ Y6 600 -500 100 L 30 30 0 1 P +X ~ Y7 600 -600 100 L 30 30 0 1 P +X ~ Y8 600 -700 100 L 30 30 0 1 P +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 185_PSPICE +# +DEF 185_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "185_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -200 100 R 30 30 0 1 P +X ~ B 0 -300 100 R 30 30 0 1 P +X ~ C 0 -400 100 R 30 30 0 1 P +X ~ D 0 -500 100 R 30 30 0 1 P +X ~ E 0 -600 100 R 30 30 0 1 P +X ~ Y1 600 0 100 L 30 30 0 1 P +X ~ Y2 600 -100 100 L 30 30 0 1 P +X ~ Y3 600 -200 100 L 30 30 0 1 P +X ~ Y4 600 -300 100 L 30 30 0 1 P +X ~ Y5 600 -400 100 L 30 30 0 1 P +X ~ Y6 600 -500 100 L 30 30 0 1 P +X ~ Y7 600 -600 100 L 30 30 0 1 P +X ~ Y8 600 -700 100 L 30 30 0 1 P +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 194_PSPICE +# +DEF 194_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "194_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -400 100 R 30 30 0 1 P +X ~ B 0 -500 100 R 30 30 0 1 P +X ~ C 0 -600 100 R 30 30 0 1 P +X ~ D 0 -700 100 R 30 30 0 1 P +X ~ S0 0 -100 100 R 30 30 0 1 P +X ~ S1 0 0 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ SL 0 -200 100 R 30 30 0 1 P +X ~ SR 0 -300 100 R 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 195_PSPICE +# +DEF 195_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "195_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1200 0 1 0 N +X ~ A 0 -500 100 R 30 30 0 1 P +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ C 0 -700 100 R 30 30 0 1 P +X ~ D 0 -800 100 R 30 30 0 1 P +X ~ J 0 -200 100 R 30 30 0 1 P +X ~ QA 600 -200 100 L 30 30 0 1 P +X ~ QB 600 -400 100 L 30 30 0 1 P +X ~ QC 600 -600 100 L 30 30 0 1 P +X ~ QD 600 -800 100 L 30 30 0 1 P +X ~ GND 200 -1300 100 U 30 30 0 1 W +X ~ CLK 0 -1000 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \K\ 0 -300 100 R 30 30 0 1 P +X ~ \Q\D 600 -1000 100 L 30 30 0 1 P +X ~ \CLR\ 300 -1300 100 U 30 30 0 1 P +X ~ SH/\LD\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 196_PSPICE +# +DEF 196_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "196_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -500 100 R 30 30 0 1 P +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ C 0 -700 100 R 30 30 0 1 P +X ~ D 0 -800 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -200 100 R 30 30 0 1 P +X ~ CLK2 0 -300 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 197_PSPICE +# +DEF 197_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "197_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -500 100 R 30 30 0 1 P +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ C 0 -700 100 R 30 30 0 1 P +X ~ D 0 -800 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -200 100 R 30 30 0 1 P +X ~ CLK2 0 -300 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 20_PSPICE +# +DEF 20_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "20_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 22_PSPICE +# +DEF 22_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "22_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 P +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 23_PSPICE +# +DEF 23_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "23_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -1300 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -1300 100 -1300 N +P 2 0 1 0 500 100 500 -1300 N +X ~ X 0 -500 100 R 30 30 0 1 I +X ~ 1A 0 0 100 R 30 30 0 1 I +X ~ 2A 0 -800 100 R 30 30 0 1 I +X ~ 1B 0 -100 100 R 30 30 0 1 I +X ~ 2B 0 -900 100 R 30 30 0 1 I +X ~ 1C 0 -200 100 R 30 30 0 1 I +X ~ 2C 0 -1000 100 R 30 30 0 1 I +X ~ 1D 0 -300 100 R 30 30 0 1 I +X ~ 2D 0 -1100 100 R 30 30 0 1 I +X ~ 1G 0 -400 100 R 30 30 0 1 I +X ~ 2G 0 -1200 100 R 30 30 0 1 I +X ~ 1Y 600 -200 100 L 30 30 0 1 I +X ~ 2Y 600 -1000 100 L 30 30 0 1 I +X ~ GND 300 -1400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \X\ 0 -600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 246_PSPICE +# +DEF 246_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "246_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 247_PSPICE +# +DEF 247_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "247_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 248_PSPICE +# +DEF 248_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "248_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 249_PSPICE +# +DEF 249_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "249_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 251_PSPICE +# +DEF 251_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "251_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ A 0 -1100 100 R 30 30 0 1 P +X ~ B 0 -1200 100 R 30 30 0 1 P +X ~ C 0 -1300 100 R 30 30 0 1 P +X ~ Y 600 -200 100 L 30 30 0 1 P +X ~ D0 0 -200 100 R 30 30 0 1 P +X ~ D1 0 -300 100 R 30 30 0 1 P +X ~ D2 0 -400 100 R 30 30 0 1 P +X ~ D3 0 -500 100 R 30 30 0 1 P +X ~ D4 0 -600 100 R 30 30 0 1 P +X ~ D5 0 -700 100 R 30 30 0 1 P +X ~ D6 0 -800 100 R 30 30 0 1 P +X ~ D7 0 -900 100 R 30 30 0 1 P +X ~ GND 300 -1500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +X ~ \W\ 600 -400 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 259_PSPICE +# +DEF 259_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "259_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ D 0 -200 100 R 30 30 0 1 P +X ~ Q0 600 0 100 L 30 30 0 1 P +X ~ S0 0 -400 100 R 30 30 0 1 P +X ~ Q1 600 -100 100 L 30 30 0 1 P +X ~ S1 0 -500 100 R 30 30 0 1 P +X ~ Q2 600 -200 100 L 30 30 0 1 P +X ~ S2 0 -600 100 R 30 30 0 1 P +X ~ Q3 600 -300 100 L 30 30 0 1 P +X ~ Q4 600 -400 100 L 30 30 0 1 P +X ~ Q5 600 -500 100 L 30 30 0 1 P +X ~ Q6 600 -600 100 L 30 30 0 1 P +X ~ Q7 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1000 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 25_PSPICE +# +DEF 25_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "25_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -500 100 -500 N +P 2 0 1 0 500 100 500 -500 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ G 0 -400 100 R 30 30 0 1 I +X ~ Y 600 -200 100 L 30 30 0 1 I +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 265_PSPICE +# +DEF 265_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "265_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ 1A 0 0 100 R 30 30 0 1 P +X ~ 2A 0 -300 100 R 30 30 0 1 P +X ~ 3A 0 -600 100 R 30 30 0 1 P +X ~ 4A 0 -900 100 R 30 30 0 1 P +X ~ 2B 0 -400 100 R 30 30 0 1 P +X ~ 3B 0 -700 100 R 30 30 0 1 P +X ~ 1W 600 0 100 L 30 30 0 1 P +X ~ 2W 600 -300 100 L 30 30 0 1 P +X ~ 3W 600 -600 100 L 30 30 0 1 P +X ~ 4W 600 -900 100 L 30 30 0 1 P +X ~ 1Y 600 -100 100 L 30 30 0 1 P +X ~ 2Y 600 -400 100 L 30 30 0 1 P +X ~ 3Y 600 -700 100 L 30 30 0 1 P +X ~ 4Y 600 -1000 100 L 30 30 0 1 P +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 26_PSPICE +# +DEF 26_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "26_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 273_PSPICE +# +DEF 273_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "273_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ D1 0 0 100 R 30 30 0 1 P +X ~ Q1 600 0 100 L 30 30 0 1 P +X ~ D2 0 -100 100 R 30 30 0 1 P +X ~ Q2 600 -100 100 L 30 30 0 1 P +X ~ D3 0 -200 100 R 30 30 0 1 P +X ~ Q3 600 -200 100 L 30 30 0 1 P +X ~ D4 0 -300 100 R 30 30 0 1 P +X ~ Q4 600 -300 100 L 30 30 0 1 P +X ~ D5 0 -400 100 R 30 30 0 1 P +X ~ Q5 600 -400 100 L 30 30 0 1 P +X ~ D6 0 -500 100 R 30 30 0 1 P +X ~ Q6 600 -500 100 L 30 30 0 1 P +X ~ D7 0 -600 100 R 30 30 0 1 P +X ~ Q7 600 -600 100 L 30 30 0 1 P +X ~ D8 0 -700 100 R 30 30 0 1 P +X ~ Q8 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 276_PSPICE +# +DEF 276_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "276_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -1300 0 1 0 N +X ~ 1J 0 0 100 R 30 30 0 1 P +X ~ 2J 0 -300 100 R 30 30 0 1 P +X ~ 3J 0 -600 100 R 30 30 0 1 P +X ~ 4J 0 -900 100 R 30 30 0 1 P +X ~ 1Q 600 0 100 L 30 30 0 1 P +X ~ 2Q 600 -300 100 L 30 30 0 1 P +X ~ 3Q 600 -600 100 L 30 30 0 1 P +X ~ 4Q 600 -900 100 L 30 30 0 1 P +X ~ GND 200 -1400 100 U 30 30 0 1 W +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \PRE\ 300 300 100 D 30 30 0 1 P +X ~ 1CLK 0 -100 100 R 30 30 0 1 P +X ~ 2CLK 0 -400 100 R 30 30 0 1 P +X ~ 3CLK 0 -700 100 R 30 30 0 1 P +X ~ 4CLK 0 -1000 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1400 100 U 30 30 0 1 P +X ~ 1\K\ 0 -200 100 R 30 30 0 1 P +X ~ 2\K\ 0 -500 100 R 30 30 0 1 P +X ~ 3\K\ 0 -800 100 R 30 30 0 1 P +X ~ 4\K\ 0 -1100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 278_PSPICE +# +DEF 278_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "278_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -700 0 1 0 N +X ~ P0 0 0 100 R 30 30 0 1 P +X ~ D1 0 -300 100 R 30 30 0 1 P +X ~ P1 600 0 100 L 30 30 0 1 P +X ~ Y1 600 -300 100 L 30 30 0 1 P +X ~ D2 0 -400 100 R 30 30 0 1 P +X ~ Y2 600 -400 100 L 30 30 0 1 P +X ~ D3 0 -500 100 R 30 30 0 1 P +X ~ Y3 600 -500 100 L 30 30 0 1 P +X ~ D4 0 -600 100 R 30 30 0 1 P +X ~ Y4 600 -600 100 L 30 30 0 1 P +X ~ GND 300 -800 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ STRB 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 279_PSPICE +# +DEF 279_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "279_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -600 0 1 0 N +X ~ 1Q 600 -200 100 L 30 30 0 1 P +X ~ 2Q 600 -500 100 L 30 30 0 1 P +X ~ GND 300 -700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\R\ 0 0 100 R 30 30 0 1 P +X ~ 2\R\ 0 -400 100 R 30 30 0 1 P +X ~ 1\S\1 0 -100 100 R 30 30 0 1 P +X ~ 1\S\2 0 -200 100 R 30 30 0 1 P +X ~ 2\S\ 0 -500 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 27_PSPICE +# +DEF 27_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "27_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 283_PSPICE +# +DEF 283_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "283_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ C0 0 -900 100 R 30 30 0 1 P +X ~ A1 0 -700 100 R 30 30 0 1 P +X ~ B1 0 -600 100 R 30 30 0 1 P +X ~ A2 0 -500 100 R 30 30 0 1 P +X ~ B2 0 -400 100 R 30 30 0 1 P +X ~ A3 0 -300 100 R 30 30 0 1 P +X ~ B3 0 -200 100 R 30 30 0 1 P +X ~ A4 0 -100 100 R 30 30 0 1 P +X ~ B4 0 0 100 R 30 30 0 1 P +X ~ C4 600 -900 100 L 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SUM1 600 -700 100 L 30 30 0 1 P +X ~ SUM2 600 -500 100 L 30 30 0 1 P +X ~ SUM3 600 -300 100 L 30 30 0 1 P +X ~ SUM4 600 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 28_PSPICE +# +DEF 28_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "28_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 290_PSPICE +# +DEF 290_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "290_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ R01 0 -600 100 R 30 30 0 1 P +X ~ R91 0 0 100 R 30 30 0 1 P +X ~ R02 0 -700 100 R 30 30 0 1 P +X ~ R92 0 -100 100 R 30 30 0 1 P +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLKA 0 -300 100 R 30 30 0 1 P +X ~ CLKB 0 -400 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 293_PSPICE +# +DEF 293_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "293_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ QA 600 0 100 L 30 30 0 1 P +X ~ QB 600 -100 100 L 30 30 0 1 P +X ~ QC 600 -200 100 L 30 30 0 1 P +X ~ QD 600 -300 100 L 30 30 0 1 P +X ~ R01 0 -300 100 R 30 30 0 1 P +X ~ R02 0 -400 100 R 30 30 0 1 P +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLKA 0 0 100 R 30 30 0 1 P +X ~ CLKB 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 298_PSPICE +# +DEF 298_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "298_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ A1 0 -200 100 R 30 30 0 1 P +X ~ B1 0 -400 100 R 30 30 0 1 P +X ~ C1 0 -600 100 R 30 30 0 1 P +X ~ D1 0 -800 100 R 30 30 0 1 P +X ~ A2 0 -300 100 R 30 30 0 1 P +X ~ B2 0 -500 100 R 30 30 0 1 P +X ~ C2 0 -700 100 R 30 30 0 1 P +X ~ D2 0 -900 100 R 30 30 0 1 P +X ~ QA 600 -200 100 L 30 30 0 1 P +X ~ QB 600 -400 100 L 30 30 0 1 P +X ~ QC 600 -600 100 L 30 30 0 1 P +X ~ QD 600 -800 100 L 30 30 0 1 P +X ~ WS 0 0 100 R 30 30 0 1 P +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ CLK 0 -1000 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 2N1595_PSPICE +# +DEF 2N1595_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "2N1595_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 200 50 200 -50 N +P 2 0 1 0 300 -100 200 0 N +P 2 0 1 0 300 0 200 0 N +P 4 0 1 0 100 50 100 -50 200 0 100 50 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ G 300 -200 100 U 30 30 0 1 P +X ~ K 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 2N5444_PSPICE +# +DEF 2N5444_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "2N5444_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 200 -50 300 -100 N +P 2 0 1 0 200 0 200 -50 N +P 2 0 1 0 200 0 300 0 N +P 4 0 1 0 100 100 100 -100 200 -50 100 0 N +P 4 0 1 0 200 0 100 50 200 100 200 0 N +X ~ G 300 -200 100 U 30 30 0 1 P +X ~ MT1 400 0 100 L 30 30 0 1 P +X ~ MT2 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 30_PSPICE +# +DEF 30_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "30_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ E 0 -400 100 R 30 30 0 1 I +X ~ F 0 -500 100 R 30 30 0 1 I +X ~ G 0 -600 100 R 30 30 0 1 I +X ~ H 0 -700 100 R 30 30 0 1 I +X ~ Y 600 -300 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 32_PSPICE +# +DEF 32_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "32_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 33_PSPICE +# +DEF 33_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "33_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 351_PSPICE +# +DEF 351_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "351_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -2000 0 1 0 N +X ~ A 0 -1700 100 R 30 30 0 1 P +X ~ B 0 -1800 100 R 30 30 0 1 P +X ~ C 0 -1900 100 R 30 30 0 1 P +X ~ D4 0 -1200 100 R 30 30 0 1 P +X ~ D5 0 -1300 100 R 30 30 0 1 P +X ~ D6 0 -1400 100 R 30 30 0 1 P +X ~ D7 0 -1500 100 R 30 30 0 1 P +X ~ 1Y 600 -200 100 L 30 30 0 1 P +X ~ 2Y 600 -700 100 L 30 30 0 1 P +X ~ 1D0 0 -200 100 R 30 30 0 1 P +X ~ 2D0 0 -700 100 R 30 30 0 1 P +X ~ 1D1 0 -300 100 R 30 30 0 1 P +X ~ 2D1 0 -800 100 R 30 30 0 1 P +X ~ 1D2 0 -400 100 R 30 30 0 1 P +X ~ 2D2 0 -900 100 R 30 30 0 1 P +X ~ 1D3 0 -500 100 R 30 30 0 1 P +X ~ 2D3 0 -1000 100 R 30 30 0 1 P +X ~ GND 300 -2100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 365_PSPICE +# +DEF 365_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "365_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A1 0 -300 100 R 30 30 0 1 P +X ~ Y1 600 -300 100 L 30 30 0 1 P +X ~ A2 0 -400 100 R 30 30 0 1 P +X ~ Y2 600 -400 100 L 30 30 0 1 P +X ~ A3 0 -500 100 R 30 30 0 1 P +X ~ Y3 600 -500 100 L 30 30 0 1 P +X ~ A4 0 -600 100 R 30 30 0 1 P +X ~ Y4 600 -600 100 L 30 30 0 1 P +X ~ A5 0 -700 100 R 30 30 0 1 P +X ~ Y5 600 -700 100 L 30 30 0 1 P +X ~ A6 0 -800 100 R 30 30 0 1 P +X ~ Y6 600 -800 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 P +X ~ \G\2 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 366_PSPICE +# +DEF 366_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "366_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A1 0 -300 100 R 30 30 0 1 P +X ~ Y1 600 -300 100 L 30 30 0 1 P +X ~ A2 0 -400 100 R 30 30 0 1 P +X ~ Y2 600 -400 100 L 30 30 0 1 P +X ~ A3 0 -500 100 R 30 30 0 1 P +X ~ Y3 600 -500 100 L 30 30 0 1 P +X ~ A4 0 -600 100 R 30 30 0 1 P +X ~ Y4 600 -600 100 L 30 30 0 1 P +X ~ A5 0 -700 100 R 30 30 0 1 P +X ~ Y5 600 -700 100 L 30 30 0 1 P +X ~ A6 0 -800 100 R 30 30 0 1 P +X ~ Y6 600 -800 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 P +X ~ \G\2 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 367_PSPICE +# +DEF 367_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "367_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ 1A1 0 -100 100 R 30 30 0 1 P +X ~ 2A1 0 -700 100 R 30 30 0 1 P +X ~ 1Y1 600 -100 100 L 30 30 0 1 P +X ~ 2Y1 600 -700 100 L 30 30 0 1 P +X ~ 1A2 0 -200 100 R 30 30 0 1 P +X ~ 2A2 0 -800 100 R 30 30 0 1 P +X ~ 1Y2 600 -200 100 L 30 30 0 1 P +X ~ 2Y2 600 -800 100 L 30 30 0 1 P +X ~ 1A3 0 -300 100 R 30 30 0 1 P +X ~ 1Y3 600 -300 100 L 30 30 0 1 P +X ~ 1A4 0 -400 100 R 30 30 0 1 P +X ~ 1Y4 600 -400 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\G\ 0 0 100 R 30 30 0 1 P +X ~ 2\G\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 368_PSPICE +# +DEF 368_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "368_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ 1A1 0 -100 100 R 30 30 0 1 P +X ~ 2A1 0 -700 100 R 30 30 0 1 P +X ~ 1Y1 600 -100 100 L 30 30 0 1 P +X ~ 2Y1 600 -700 100 L 30 30 0 1 P +X ~ 1A2 0 -200 100 R 30 30 0 1 P +X ~ 2A2 0 -800 100 R 30 30 0 1 P +X ~ 1Y2 600 -200 100 L 30 30 0 1 P +X ~ 2Y2 600 -800 100 L 30 30 0 1 P +X ~ 1A3 0 -300 100 R 30 30 0 1 P +X ~ 1Y3 600 -300 100 L 30 30 0 1 P +X ~ 1A4 0 -400 100 R 30 30 0 1 P +X ~ 1Y4 600 -400 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\G\ 0 0 100 R 30 30 0 1 P +X ~ 2\G\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 376_PSPICE +# +DEF 376_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "376_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ 1J 0 0 100 R 30 30 0 1 P +X ~ 2J 0 -200 100 R 30 30 0 1 P +X ~ 3J 0 -400 100 R 30 30 0 1 P +X ~ 4J 0 -600 100 R 30 30 0 1 P +X ~ 1Q 600 -100 100 L 30 30 0 1 P +X ~ 2Q 600 -300 100 L 30 30 0 1 P +X ~ 3Q 600 -500 100 L 30 30 0 1 P +X ~ 4Q 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +X ~ 1\K\ 0 -100 100 R 30 30 0 1 P +X ~ 2\K\ 0 -300 100 R 30 30 0 1 P +X ~ 3\K\ 0 -500 100 R 30 30 0 1 P +X ~ 4\K\ 0 -700 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 37_PSPICE +# +DEF 37_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "37_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 38_PSPICE +# +DEF 38_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "38_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 390_PSPICE +# +DEF 390_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "390_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -400 0 1 0 N +X ~ QA 600 100 100 L 30 30 0 1 P +X ~ QB 600 0 100 L 30 30 0 1 P +X ~ QC 600 -100 100 L 30 30 0 1 P +X ~ QD 600 -200 100 L 30 30 0 1 P +X ~ CKA 0 0 100 R 30 30 0 1 P +X ~ CKB 0 -200 100 R 30 30 0 1 P +X ~ GND 200 -500 100 U 30 30 0 1 W +X ~ CLR 300 -500 100 U 30 30 0 1 P +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 393_PSPICE +# +DEF 393_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "393_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -400 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ QA 600 0 100 L 30 30 0 1 P +X ~ QB 600 -100 100 L 30 30 0 1 P +X ~ QC 600 -200 100 L 30 30 0 1 P +X ~ QD 600 -300 100 L 30 30 0 1 P +X ~ GND 200 -500 100 U 30 30 0 1 W +X ~ CLR 300 -500 100 U 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 39_PSPICE +# +DEF 39_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "39_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 40_PSPICE +# +DEF 40_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "40_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 411/OP_PSPICE +# +DEF 411/OP_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "411/OP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 500 -300 600 -400 N +P 2 0 1 0 600 -400 700 -400 N +P 2 0 1 0 600 0 500 -100 N +P 2 0 1 0 600 0 700 0 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ V+ 400 100 100 D 30 30 0 1 W +X ~ V- 400 -500 100 U 30 30 0 1 W +X ~ B1 800 -400 100 L 30 30 0 1 I +X ~ B2 800 0 100 L 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 425_PSPICE +# +DEF 425_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "425_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -160 40 0 1 0 N +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -140 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 426_PSPICE +# +DEF 426_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "426_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -200 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ G 0 0 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 42_PSPICE +# +DEF 42_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "42_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 43_PSPICE +# +DEF 43_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "43_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 44_PSPICE +# +DEF 44_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "44_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 45_PSPICE +# +DEF 45_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "45_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 46_PSPICE +# +DEF 46_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "46_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ INA 0 -400 100 R 30 30 0 1 I +X ~ INB 0 -500 100 R 30 30 0 1 I +X ~ INC 0 -600 100 R 30 30 0 1 I +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ IND 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 -100 100 L 30 30 0 1 O +X ~ OUTB 600 -200 100 L 30 30 0 1 O +X ~ OUTC 600 -300 100 L 30 30 0 1 O +X ~ OUTD 600 -400 100 L 30 30 0 1 O +X ~ OUTE 600 -500 100 L 30 30 0 1 O +X ~ OUTF 600 -600 100 L 30 30 0 1 O +X ~ OUTG 600 -700 100 L 30 30 0 1 O +X ~ \RBI\ 0 -100 100 R 30 30 0 1 I +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +X ~ \LT\ 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 47_PSPICE +# +DEF 47_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "47_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ INA 0 -400 100 R 30 30 0 1 I +X ~ INB 0 -500 100 R 30 30 0 1 I +X ~ INC 0 -600 100 R 30 30 0 1 I +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ IND 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 -100 100 L 30 30 0 1 O +X ~ OUTB 600 -200 100 L 30 30 0 1 O +X ~ OUTC 600 -300 100 L 30 30 0 1 O +X ~ OUTD 600 -400 100 L 30 30 0 1 O +X ~ OUTE 600 -500 100 L 30 30 0 1 O +X ~ OUTF 600 -600 100 L 30 30 0 1 O +X ~ OUTG 600 -700 100 L 30 30 0 1 O +X ~ \RBI\ 0 -100 100 R 30 30 0 1 I +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +X ~ \LT\ 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 48_PSPICE +# +DEF 48_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "48_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ A 0 -400 100 R 30 30 0 1 I +X ~ B 0 -500 100 R 30 30 0 1 I +X ~ C 0 -600 100 R 30 30 0 1 I +X ~ D 0 -700 100 R 30 30 0 1 I +X ~ OA 600 0 100 L 30 30 0 1 O +X ~ OB 600 -100 100 L 30 30 0 1 O +X ~ OC 600 -200 100 L 30 30 0 1 O +X ~ OD 600 -300 100 L 30 30 0 1 O +X ~ OE 600 -400 100 L 30 30 0 1 O +X ~ OF 600 -500 100 L 30 30 0 1 O +X ~ OG 600 -600 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \RBI\ 0 -100 100 R 30 30 0 1 I +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +X ~ \LT\ 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 490_PSPICE +# +DEF 490_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "490_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -400 0 1 0 N +X ~ QA 600 100 100 L 30 30 0 1 P +X ~ QB 600 0 100 L 30 30 0 1 P +X ~ QC 600 -100 100 L 30 30 0 1 P +X ~ QD 600 -200 100 L 30 30 0 1 P +X ~ GND 200 -500 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 P +X ~ CLR 300 -500 100 U 30 30 0 1 P +X ~ PWR 300 300 100 D 30 30 0 1 W +X ~ SET9 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 49_PSPICE +# +DEF 49_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "49_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -700 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -700 100 -700 N +P 2 0 1 0 500 100 500 -700 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ B 0 -400 100 R 30 30 0 1 I +X ~ C 0 -500 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ OA 600 0 100 L 30 30 0 1 O +X ~ OB 600 -100 100 L 30 30 0 1 O +X ~ OC 600 -200 100 L 30 30 0 1 O +X ~ OD 600 -300 100 L 30 30 0 1 O +X ~ OE 600 -400 100 L 30 30 0 1 O +X ~ OF 600 -500 100 L 30 30 0 1 O +X ~ OG 600 -600 100 L 30 30 0 1 O +X ~ GND 300 -800 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 50_PSPICE +# +DEF 50_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "50_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -1100 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -1100 100 -1100 N +P 2 0 1 0 500 100 500 -1100 N +X ~ 1A 0 0 100 R 30 30 0 1 I +X ~ 2A 0 -700 100 R 30 30 0 1 I +X ~ 1B 0 -100 100 R 30 30 0 1 I +X ~ 2B 0 -800 100 R 30 30 0 1 I +X ~ 1C 0 -200 100 R 30 30 0 1 I +X ~ 2C 0 -900 100 R 30 30 0 1 I +X ~ 1D 0 -300 100 R 30 30 0 1 I +X ~ 2D 0 -1000 100 R 30 30 0 1 I +X ~ 1X 0 -400 100 R 30 30 0 1 I +X ~ 1Y 600 -200 100 L 30 30 0 1 O +X ~ 2Y 600 -900 100 L 30 30 0 1 O +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\X\ 0 -500 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 51_PSPICE +# +DEF 51_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "51_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ Y 600 -100 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 54152A_PSPICE +# +DEF 54152A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "54152A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1200 0 1 0 N +X ~ A 0 -900 100 R 30 30 0 1 I +X ~ B 0 -1000 100 R 30 30 0 1 I +X ~ C 0 -1100 100 R 30 30 0 1 I +X ~ W 600 -500 100 L 30 30 0 1 O +X ~ D0 0 0 100 R 30 30 0 1 I +X ~ D1 0 -100 100 R 30 30 0 1 I +X ~ D2 0 -200 100 R 30 30 0 1 I +X ~ D3 0 -300 100 R 30 30 0 1 I +X ~ D4 0 -400 100 R 30 30 0 1 I +X ~ D5 0 -500 100 R 30 30 0 1 I +X ~ D6 0 -600 100 R 30 30 0 1 I +X ~ D7 0 -700 100 R 30 30 0 1 I +X ~ GND 300 -1300 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 555D_PSPICE +# +DEF 555D_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "555D_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 900 -600 0 1 0 N +X ~ VCC 500 300 100 D 30 30 0 1 P +X ~ GND 500 -700 100 U 30 30 0 1 P +X ~ DISCHARGE 0 -400 100 R 30 30 0 1 P +X ~ THRESHOLD 0 -300 100 R 30 30 0 1 P +X ~ RESET 0 -100 100 R 30 30 0 1 P +X ~ TRIGGER 0 0 100 R 30 30 0 1 P +X ~ OUTPUT 1000 -100 100 L 30 30 0 1 P +X ~ CONTROL 0 -200 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 60_PSPICE +# +DEF 60_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "60_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -500 100 -500 N +P 2 0 1 0 500 100 500 -500 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ X 600 -100 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \X\ 0 -400 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 70_PSPICE +# +DEF 70_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "70_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -800 0 1 0 N +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ J1 0 0 100 R 30 30 0 1 I +X ~ K1 0 -400 100 R 30 30 0 1 I +X ~ J2 0 -100 100 R 30 30 0 1 I +X ~ K2 0 -500 100 R 30 30 0 1 I +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -300 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \J\ 0 -200 100 R 30 30 0 1 I +X ~ \K\ 0 -600 100 R 30 30 0 1 I +X ~ \Q\ 600 -500 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 72_PSPICE +# +DEF 72_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "72_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 200 500 -800 N +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ J1 0 0 100 R 30 30 0 1 I +X ~ K1 0 -400 100 R 30 30 0 1 I +X ~ J2 0 -100 100 R 30 30 0 1 I +X ~ K2 0 -500 100 R 30 30 0 1 I +X ~ J3 0 -200 100 R 30 30 0 1 I +X ~ K3 0 -600 100 R 30 30 0 1 I +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -300 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -500 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 73_PSPICE +# +DEF 73_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "73_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 0 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 600 -400 100 L 30 30 0 1 O +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7400_PSPICE +# +DEF 7400_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7400_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7401_PSPICE +# +DEF 7401_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7401_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7402_PSPICE +# +DEF 7402_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7402_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7403_PSPICE +# +DEF 7403_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7403_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7404_PSPICE +# +DEF 7404_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7404_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 O +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7405_PSPICE +# +DEF 7405_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7405_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7406_PSPICE +# +DEF 7406_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7406_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7407_PSPICE +# +DEF 7407_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7407_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7408_PSPICE +# +DEF 7408_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7408_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7409_PSPICE +# +DEF 7409_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7409_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 741/OP_PSPICE +# +DEF 741/OP_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "741/OP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 500 -300 600 -400 N +P 2 0 1 0 600 -400 700 -400 N +P 2 0 1 0 600 0 500 -100 N +P 2 0 1 0 600 0 700 0 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ V+ 400 100 100 D 30 30 0 1 W +X ~ V- 400 -500 100 U 30 30 0 1 W +X ~ OS1 800 -400 100 L 30 30 0 1 I +X ~ OS2 800 0 100 L 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 74100_PSPICE +# +DEF 74100_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74100_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ C 0 0 100 R 30 30 0 1 I +X ~ D1 0 -100 100 R 30 30 0 1 I +X ~ Q1 600 -100 100 L 30 30 0 1 O +X ~ D2 0 -200 100 R 30 30 0 1 I +X ~ Q2 600 -200 100 L 30 30 0 1 O +X ~ D3 0 -300 100 R 30 30 0 1 I +X ~ Q3 600 -300 100 L 30 30 0 1 O +X ~ D4 0 -400 100 R 30 30 0 1 I +X ~ Q4 600 -400 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74107_PSPICE +# +DEF 74107_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74107_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 600 -300 100 L 30 30 0 1 O +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74109_PSPICE +# +DEF 74109_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74109_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \K\ 0 -400 100 R 30 30 0 1 I +X ~ \Q\ 600 -300 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7410_PSPICE +# +DEF 7410_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7410_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74110_PSPICE +# +DEF 74110_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74110_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -800 0 1 0 N +X ~ Q 600 -200 100 L 30 30 0 1 O +X ~ J1 0 0 100 R 30 30 0 1 I +X ~ K1 0 -400 100 R 30 30 0 1 I +X ~ J2 0 -100 100 R 30 30 0 1 I +X ~ K2 0 -500 100 R 30 30 0 1 I +X ~ J3 0 -200 100 R 30 30 0 1 I +X ~ K3 0 -600 100 R 30 30 0 1 I +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -300 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -400 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74111_PSPICE +# +DEF 74111_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74111_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -300 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7411_PSPICE +# +DEF 7411_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7411_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74121_PSPICE +# +DEF 74121_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74121_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -700 0 1 0 N +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ Q 700 -200 100 L 30 30 0 1 P +X ~ A1 0 -400 100 R 30 30 0 1 P +X ~ A2 0 -500 100 R 30 30 0 1 P +X ~ GND 300 -800 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 700 -400 100 L 30 30 0 1 P +X ~ RINT 0 -100 100 R 30 30 0 1 P +X ~ CEXT 0 -200 100 R 30 30 0 1 P +X ~ REXT/CEXT 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74122_PSPICE +# +DEF 74122_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74122_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -900 0 1 0 N +X ~ Q 700 -200 100 L 30 30 0 1 P +X ~ A1 0 -400 100 R 30 30 0 1 P +X ~ B1 0 -600 100 R 30 30 0 1 P +X ~ A2 0 -500 100 R 30 30 0 1 P +X ~ B2 0 -700 100 R 30 30 0 1 P +X ~ GND 200 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 700 -400 100 L 30 30 0 1 P +X ~ \CLR\ 300 -1000 100 U 30 30 0 1 P +X ~ RINT 0 -100 100 R 30 30 0 1 P +X ~ CEXT 0 -200 100 R 30 30 0 1 P +X ~ REXT/CEXT 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74123_PSPICE +# +DEF 74123_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74123_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -600 0 1 0 N +X ~ A 0 -300 100 R 30 30 0 1 P +X ~ B 0 -400 100 R 30 30 0 1 P +X ~ Q 700 -100 100 L 30 30 0 1 P +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 700 -300 100 L 30 30 0 1 P +X ~ \CLR\ 300 -700 100 U 30 30 0 1 P +X ~ CEXT 0 -100 100 R 30 30 0 1 P +X ~ REXT/CEXT 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74125_PSPICE +# +DEF 74125_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74125_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -160 40 0 1 0 N +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -140 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74126_PSPICE +# +DEF 74126_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74126_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -200 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ G 0 0 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74128_PSPICE +# +DEF 74128_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74128_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A -250 -90 400 -308 283 0 1 0 N 93 -295 101 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 100 -300 300 -300 N +P 2 0 1 0 100 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7412_PSPICE +# +DEF 7412_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7412_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74132_PSPICE +# +DEF 74132_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74132_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74136_PSPICE +# +DEF 74136_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74136_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A -250 -90 400 -308 283 0 1 0 N 93 -295 101 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 100 -300 300 -300 N +P 2 0 1 0 100 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7413_PSPICE +# +DEF 7413_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7413_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 200 -150 350 -150 N +P 2 0 1 0 250 -250 250 -150 N +P 2 0 1 0 350 -150 350 -250 N +P 2 0 1 0 400 -250 250 -250 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74147_PSPICE +# +DEF 74147_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74147_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A 600 -100 100 L 30 30 0 1 P +X ~ B 600 -300 100 L 30 30 0 1 P +X ~ C 600 -500 100 L 30 30 0 1 P +X ~ D 600 -700 100 L 30 30 0 1 P +X ~ IN1 0 0 100 R 30 30 0 1 P +X ~ IN2 0 -100 100 R 30 30 0 1 P +X ~ IN3 0 -200 100 R 30 30 0 1 P +X ~ IN4 0 -300 100 R 30 30 0 1 P +X ~ IN5 0 -400 100 R 30 30 0 1 P +X ~ IN6 0 -500 100 R 30 30 0 1 P +X ~ IN7 0 -600 100 R 30 30 0 1 P +X ~ IN8 0 -700 100 R 30 30 0 1 P +X ~ IN9 0 -800 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74148_PSPICE +# +DEF 74148_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74148_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A0 600 0 100 L 30 30 0 1 P +X ~ A1 600 -200 100 L 30 30 0 1 P +X ~ A2 600 -400 100 L 30 30 0 1 P +X ~ EI 0 -800 100 R 30 30 0 1 P +X ~ EO 600 -800 100 L 30 30 0 1 P +X ~ GS 600 -600 100 L 30 30 0 1 P +X ~ IN0 0 0 100 R 30 30 0 1 P +X ~ IN1 0 -100 100 R 30 30 0 1 P +X ~ IN2 0 -200 100 R 30 30 0 1 P +X ~ IN3 0 -300 100 R 30 30 0 1 P +X ~ IN4 0 -400 100 R 30 30 0 1 P +X ~ IN5 0 -500 100 R 30 30 0 1 P +X ~ IN6 0 -600 100 R 30 30 0 1 P +X ~ IN7 0 -700 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7414_PSPICE +# +DEF 7414_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7414_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 140 40 260 40 N +P 2 0 1 0 180 -40 180 40 N +P 2 0 1 0 260 40 260 -40 N +P 2 0 1 0 300 -40 180 -40 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 O +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74151A_PSPICE +# +DEF 74151A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74151A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ Z 600 -300 100 L 30 30 0 1 O +X ~ I0 0 -200 100 R 30 30 0 1 I +X ~ S0 0 -1100 100 R 30 30 0 1 I +X ~ I1 0 -300 100 R 30 30 0 1 I +X ~ S1 0 -1200 100 R 30 30 0 1 I +X ~ I2 0 -400 100 R 30 30 0 1 I +X ~ S2 0 -1300 100 R 30 30 0 1 I +X ~ I3 0 -500 100 R 30 30 0 1 I +X ~ I4 0 -600 100 R 30 30 0 1 I +X ~ I5 0 -700 100 R 30 30 0 1 I +X ~ I6 0 -800 100 R 30 30 0 1 I +X ~ I7 0 -900 100 R 30 30 0 1 I +X ~ GND 300 -1500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \E\ 0 0 100 R 30 30 0 1 I +X ~ \Z\ 600 -700 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 74153_PSPICE +# +DEF 74153_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74153_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ S0 0 0 100 R 30 30 0 1 I +X ~ S1 0 -100 100 R 30 30 0 1 I +X ~ ZA 600 -500 100 L 30 30 0 1 O +X ~ ZB 600 -1100 100 L 30 30 0 1 O +X ~ I0A 0 -400 100 R 30 30 0 1 I +X ~ I1A 0 -500 100 R 30 30 0 1 I +X ~ I2A 0 -600 100 R 30 30 0 1 I +X ~ I3A 0 -700 100 R 30 30 0 1 I +X ~ I0B 0 -1000 100 R 30 30 0 1 I +X ~ I1B 0 -1100 100 R 30 30 0 1 I +X ~ I2B 0 -1200 100 R 30 30 0 1 I +X ~ I3B 0 -1300 100 R 30 30 0 1 I +X ~ GND 300 -1500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \EA\ 0 -300 100 R 30 30 0 1 I +X ~ \EB\ 0 -900 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74154_PSPICE +# +DEF 74154_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74154_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1600 0 1 0 N +X ~ A 0 -600 100 R 30 30 0 1 I +X ~ B 0 -800 100 R 30 30 0 1 I +X ~ C 0 -1000 100 R 30 30 0 1 I +X ~ D 0 -1200 100 R 30 30 0 1 I +X ~ Y0 600 0 100 L 30 30 0 1 O +X ~ Y1 600 -100 100 L 30 30 0 1 O +X ~ Y2 600 -200 100 L 30 30 0 1 O +X ~ Y3 600 -300 100 L 30 30 0 1 O +X ~ Y4 600 -400 100 L 30 30 0 1 O +X ~ Y5 600 -500 100 L 30 30 0 1 O +X ~ Y6 600 -600 100 L 30 30 0 1 O +X ~ Y7 600 -700 100 L 30 30 0 1 O +X ~ Y8 600 -800 100 L 30 30 0 1 O +X ~ Y9 600 -900 100 L 30 30 0 1 O +X ~ Y10 600 -1000 100 L 30 30 0 1 O +X ~ Y11 600 -1100 100 L 30 30 0 1 O +X ~ Y12 600 -1200 100 L 30 30 0 1 O +X ~ Y13 600 -1300 100 L 30 30 0 1 O +X ~ Y14 600 -1400 100 L 30 30 0 1 O +X ~ Y15 600 -1500 100 L 30 30 0 1 O +X ~ GND 300 -1700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 I +X ~ \G\2 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74155_PSPICE +# +DEF 74155_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74155_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ B 0 -400 100 R 30 30 0 1 I +X ~ 1C 0 -100 100 R 30 30 0 1 I +X ~ 1Y0 600 0 100 L 30 30 0 1 O +X ~ 2Y0 600 -400 100 L 30 30 0 1 O +X ~ 1Y1 600 -100 100 L 30 30 0 1 O +X ~ 2Y1 600 -500 100 L 30 30 0 1 O +X ~ 1Y2 600 -200 100 L 30 30 0 1 O +X ~ 2Y2 600 -600 100 L 30 30 0 1 O +X ~ 1Y3 600 -300 100 L 30 30 0 1 O +X ~ 2Y3 600 -700 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 2\C\ 0 -700 100 R 30 30 0 1 I +X ~ 1\G\ 0 0 100 R 30 30 0 1 I +X ~ 2\G\ 0 -600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74156_PSPICE +# +DEF 74156_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74156_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ B 0 -400 100 R 30 30 0 1 I +X ~ 1C 0 -100 100 R 30 30 0 1 I +X ~ 1Y0 600 0 100 L 30 30 0 1 O +X ~ 2Y0 600 -400 100 L 30 30 0 1 O +X ~ 1Y1 600 -100 100 L 30 30 0 1 O +X ~ 2Y1 600 -500 100 L 30 30 0 1 O +X ~ 1Y2 600 -200 100 L 30 30 0 1 O +X ~ 2Y2 600 -600 100 L 30 30 0 1 O +X ~ 1Y3 600 -300 100 L 30 30 0 1 O +X ~ 2Y3 600 -700 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 2\C\ 0 -700 100 R 30 30 0 1 I +X ~ 1\G\ 0 0 100 R 30 30 0 1 I +X ~ 2\G\ 0 -600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74157_PSPICE +# +DEF 74157_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74157_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1100 0 1 0 N +X ~ 1A 0 0 100 R 30 30 0 1 P +X ~ 2A 0 -200 100 R 30 30 0 1 P +X ~ 3A 0 -400 100 R 30 30 0 1 P +X ~ 4A 0 -600 100 R 30 30 0 1 P +X ~ 1B 0 -100 100 R 30 30 0 1 P +X ~ 2B 0 -300 100 R 30 30 0 1 P +X ~ 3B 0 -500 100 R 30 30 0 1 P +X ~ 4B 0 -700 100 R 30 30 0 1 P +X ~ 1Y 700 -100 100 L 30 30 0 1 P +X ~ 2Y 700 -300 100 L 30 30 0 1 P +X ~ 3Y 700 -500 100 L 30 30 0 1 P +X ~ 4Y 700 -700 100 L 30 30 0 1 P +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SELECT\A\B 0 -1000 100 R 30 30 0 1 P +X ~ STROBE\G\ 0 -900 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74159_PSPICE +# +DEF 74159_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74159_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1600 0 1 0 N +X ~ A 0 -600 100 R 30 30 0 1 I +X ~ B 0 -800 100 R 30 30 0 1 I +X ~ C 0 -1000 100 R 30 30 0 1 I +X ~ D 0 -1200 100 R 30 30 0 1 I +X ~ Y0 600 0 100 L 30 30 0 1 O +X ~ Y1 600 -100 100 L 30 30 0 1 O +X ~ Y2 600 -200 100 L 30 30 0 1 O +X ~ Y3 600 -300 100 L 30 30 0 1 O +X ~ Y4 600 -400 100 L 30 30 0 1 O +X ~ Y5 600 -500 100 L 30 30 0 1 O +X ~ Y6 600 -600 100 L 30 30 0 1 O +X ~ Y7 600 -700 100 L 30 30 0 1 O +X ~ Y8 600 -800 100 L 30 30 0 1 O +X ~ Y9 600 -900 100 L 30 30 0 1 O +X ~ Y10 600 -1000 100 L 30 30 0 1 O +X ~ Y11 600 -1100 100 L 30 30 0 1 O +X ~ Y12 600 -1200 100 L 30 30 0 1 O +X ~ Y13 600 -1300 100 L 30 30 0 1 O +X ~ Y14 600 -1400 100 L 30 30 0 1 O +X ~ Y15 600 -1500 100 L 30 30 0 1 O +X ~ GND 300 -1700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 I +X ~ \G\2 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74160_PSPICE +# +DEF 74160_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74160_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74161_PSPICE +# +DEF 74161_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74161_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74162_PSPICE +# +DEF 74162_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74162_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74163_PSPICE +# +DEF 74163_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74163_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -500 100 R 30 30 0 1 I +X ~ RCO 600 -400 100 L 30 30 0 1 O +X ~ ENP 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ ENT 0 -600 100 R 30 30 0 1 I +X ~ \LOAD\ 0 -800 100 R 30 30 0 1 I +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74164_PSPICE +# +DEF 74164_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74164_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 300 500 -700 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ QA 600 200 100 L 30 30 0 1 O +X ~ QB 600 100 100 L 30 30 0 1 O +X ~ QC 600 0 100 L 30 30 0 1 O +X ~ QD 600 -100 100 L 30 30 0 1 O +X ~ QE 600 -200 100 L 30 30 0 1 O +X ~ QF 600 -300 100 L 30 30 0 1 O +X ~ QG 600 -400 100 L 30 30 0 1 O +X ~ QH 600 -500 100 L 30 30 0 1 O +X ~ GND 200 -800 100 U 30 30 0 1 W +X ~ CLK 0 -400 100 R 30 30 0 1 I +X ~ PWR 300 400 100 D 30 30 0 1 W +X ~ \CLR\ 300 -800 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7416_PSPICE +# +DEF 7416_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7416_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74173_PSPICE +# +DEF 74173_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74173_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ M 0 -800 100 R 30 30 0 1 I +X ~ N 0 -900 100 R 30 30 0 1 I +X ~ 1D 0 -300 100 R 30 30 0 1 I +X ~ 2D 0 -400 100 R 30 30 0 1 I +X ~ 3D 0 -500 100 R 30 30 0 1 I +X ~ 4D 0 -600 100 R 30 30 0 1 I +X ~ 1Q 600 -300 100 L 30 30 0 1 O +X ~ 2Q 600 -400 100 L 30 30 0 1 O +X ~ 3Q 600 -500 100 L 30 30 0 1 O +X ~ 4Q 600 -600 100 L 30 30 0 1 O +X ~ GND 200 -1200 100 U 30 30 0 1 W +X ~ CLK 0 0 100 R 30 30 0 1 P +X ~ CLR 300 -1200 100 U 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 -100 100 R 30 30 0 1 I +X ~ \G\2 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74174_PSPICE +# +DEF 74174_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74174_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ 1D 0 0 100 R 30 30 0 1 P +X ~ 2D 0 -100 100 R 30 30 0 1 P +X ~ 3D 0 -200 100 R 30 30 0 1 P +X ~ 4D 0 -300 100 R 30 30 0 1 P +X ~ 5D 0 -400 100 R 30 30 0 1 P +X ~ 6D 0 -500 100 R 30 30 0 1 P +X ~ 1Q 600 0 100 L 30 30 0 1 P +X ~ 2Q 600 -100 100 L 30 30 0 1 P +X ~ 3Q 600 -200 100 L 30 30 0 1 P +X ~ 4Q 600 -300 100 L 30 30 0 1 P +X ~ 5Q 600 -400 100 L 30 30 0 1 P +X ~ 6Q 600 -500 100 L 30 30 0 1 P +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -600 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -900 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74175_PSPICE +# +DEF 74175_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74175_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ 1D 0 0 100 R 30 30 0 1 P +X ~ 2D 0 -200 100 R 30 30 0 1 P +X ~ 3D 0 -400 100 R 30 30 0 1 P +X ~ 4D 0 -600 100 R 30 30 0 1 P +X ~ 1Q 600 0 100 L 30 30 0 1 P +X ~ 2Q 600 -200 100 L 30 30 0 1 P +X ~ 3Q 600 -400 100 L 30 30 0 1 P +X ~ 4Q 600 -600 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +X ~ 1\Q\ 600 -100 100 L 30 30 0 1 P +X ~ 2\Q\ 600 -300 100 L 30 30 0 1 P +X ~ 3\Q\ 600 -500 100 L 30 30 0 1 P +X ~ 4\Q\ 600 -700 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74176_PSPICE +# +DEF 74176_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74176_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -100 100 R 30 30 0 1 P +X ~ B 0 -200 100 R 30 30 0 1 P +X ~ C 0 -300 100 R 30 30 0 1 P +X ~ D 0 -400 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -200 100 L 30 30 0 1 P +X ~ QC 600 -300 100 L 30 30 0 1 P +X ~ QD 600 -400 100 L 30 30 0 1 P +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -500 100 R 30 30 0 1 P +X ~ CLK2 0 -600 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -900 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74177_PSPICE +# +DEF 74177_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74177_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -100 100 R 30 30 0 1 P +X ~ B 0 -200 100 R 30 30 0 1 P +X ~ C 0 -300 100 R 30 30 0 1 P +X ~ D 0 -400 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -200 100 L 30 30 0 1 P +X ~ QC 600 -300 100 L 30 30 0 1 P +X ~ QD 600 -400 100 L 30 30 0 1 P +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -500 100 R 30 30 0 1 P +X ~ CLK2 0 -600 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -900 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74178_PSPICE +# +DEF 74178_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74178_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -400 100 R 30 30 0 1 P +X ~ B 0 -500 100 R 30 30 0 1 P +X ~ C 0 -600 100 R 30 30 0 1 P +X ~ D 0 -700 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -900 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ LOAD 0 -100 100 R 30 30 0 1 P +X ~ SHIFT 0 -200 100 R 30 30 0 1 P +X ~ SERIAL 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74179_PSPICE +# +DEF 74179_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74179_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ A 0 -400 100 R 30 30 0 1 P +X ~ B 0 -500 100 R 30 30 0 1 P +X ~ C 0 -600 100 R 30 30 0 1 P +X ~ D 0 -700 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1200 100 U 30 30 0 1 W +X ~ CLK 0 -900 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ LOAD 0 -100 100 R 30 30 0 1 P +X ~ \Q\D 600 -900 100 L 30 30 0 1 P +X ~ SHIFT 0 -200 100 R 30 30 0 1 P +X ~ SERIAL 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7417_PSPICE +# +DEF 7417_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7417_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 400 0 N +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 400 0 100 200 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ Y 500 0 100 L 30 30 0 1 P +X ~ GND 250 -200 100 U 30 30 0 1 W +X ~ PWR 250 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74180_PSPICE +# +DEF 74180_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74180_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ B 0 -100 100 R 30 30 0 1 P +X ~ C 0 -200 100 R 30 30 0 1 P +X ~ D 0 -300 100 R 30 30 0 1 P +X ~ E 0 -400 100 R 30 30 0 1 P +X ~ F 0 -500 100 R 30 30 0 1 P +X ~ G 0 -600 100 R 30 30 0 1 P +X ~ H 0 -700 100 R 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ EVEN_IN 0 -800 100 R 30 30 0 1 P +X ~ EVEN_OUT 700 -200 100 L 30 30 0 1 P +X ~ ODD_IN 0 -900 100 R 30 30 0 1 P +X ~ ODD_OUT 700 -400 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74181_PSPICE +# +DEF 74181_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74181_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 600 -1000 0 1 0 N +X ~ M 0 -900 100 R 30 30 0 1 P +X ~ S0 500 300 100 D 30 30 0 1 P +X ~ S1 400 300 100 D 30 30 0 1 P +X ~ S2 300 300 100 D 30 30 0 1 P +X ~ S3 200 300 100 D 30 30 0 1 P +X ~ CN 0 -800 100 R 30 30 0 1 P +X ~ A=B 700 -500 100 L 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 100 300 100 D 30 30 0 1 W +X ~ \G\ 700 -700 100 L 30 30 0 1 P +X ~ \P\ 700 -800 100 L 30 30 0 1 P +X ~ \A\0 0 0 100 R 30 30 0 1 P +X ~ \B\0 0 -400 100 R 30 30 0 1 P +X ~ \F\0 700 0 100 L 30 30 0 1 P +X ~ \A\1 0 -100 100 R 30 30 0 1 P +X ~ \B\1 0 -500 100 R 30 30 0 1 P +X ~ \F\1 700 -100 100 L 30 30 0 1 P +X ~ \A\2 0 -200 100 R 30 30 0 1 P +X ~ \B\2 0 -600 100 R 30 30 0 1 P +X ~ \F\2 700 -200 100 L 30 30 0 1 P +X ~ \A\3 0 -300 100 R 30 30 0 1 P +X ~ \B\3 0 -700 100 R 30 30 0 1 P +X ~ \F\3 700 -300 100 L 30 30 0 1 P +X ~ CN+4 700 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74182_PSPICE +# +DEF 74182_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74182_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ CN 0 -800 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 600 -400 100 L 30 30 0 1 P +X ~ \P\ 600 -200 100 L 30 30 0 1 P +X ~ \G\0 0 -400 100 R 30 30 0 1 P +X ~ \P\0 0 0 100 R 30 30 0 1 P +X ~ \G\1 0 -500 100 R 30 30 0 1 P +X ~ \P\1 0 -100 100 R 30 30 0 1 P +X ~ \G\2 0 -600 100 R 30 30 0 1 P +X ~ \P\2 0 -200 100 R 30 30 0 1 P +X ~ \G\3 0 -700 100 R 30 30 0 1 P +X ~ \P\3 0 -300 100 R 30 30 0 1 P +X ~ CN+X 600 -600 100 L 30 30 0 1 P +X ~ CN+Y 600 -700 100 L 30 30 0 1 P +X ~ CN+Z 600 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74184_PSPICE +# +DEF 74184_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74184_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -200 100 R 30 30 0 1 P +X ~ B 0 -300 100 R 30 30 0 1 P +X ~ C 0 -400 100 R 30 30 0 1 P +X ~ D 0 -500 100 R 30 30 0 1 P +X ~ E 0 -600 100 R 30 30 0 1 P +X ~ Y1 600 0 100 L 30 30 0 1 P +X ~ Y2 600 -100 100 L 30 30 0 1 P +X ~ Y3 600 -200 100 L 30 30 0 1 P +X ~ Y4 600 -300 100 L 30 30 0 1 P +X ~ Y5 600 -400 100 L 30 30 0 1 P +X ~ Y6 600 -500 100 L 30 30 0 1 P +X ~ Y7 600 -600 100 L 30 30 0 1 P +X ~ Y8 600 -700 100 L 30 30 0 1 P +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74185A_PSPICE +# +DEF 74185A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74185A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 -200 100 R 30 30 0 1 P +X ~ B 0 -300 100 R 30 30 0 1 P +X ~ C 0 -400 100 R 30 30 0 1 P +X ~ D 0 -500 100 R 30 30 0 1 P +X ~ E 0 -600 100 R 30 30 0 1 P +X ~ Y1 600 0 100 L 30 30 0 1 P +X ~ Y2 600 -100 100 L 30 30 0 1 P +X ~ Y3 600 -200 100 L 30 30 0 1 P +X ~ Y4 600 -300 100 L 30 30 0 1 P +X ~ Y5 600 -400 100 L 30 30 0 1 P +X ~ Y6 600 -500 100 L 30 30 0 1 P +X ~ Y7 600 -600 100 L 30 30 0 1 P +X ~ Y8 600 -700 100 L 30 30 0 1 P +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74194_PSPICE +# +DEF 74194_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74194_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -400 100 R 30 30 0 1 P +X ~ B 0 -500 100 R 30 30 0 1 P +X ~ C 0 -600 100 R 30 30 0 1 P +X ~ D 0 -700 100 R 30 30 0 1 P +X ~ S0 0 -100 100 R 30 30 0 1 P +X ~ S1 0 0 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ SL 0 -200 100 R 30 30 0 1 P +X ~ SR 0 -300 100 R 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74195_PSPICE +# +DEF 74195_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74195_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1200 0 1 0 N +X ~ A 0 -500 100 R 30 30 0 1 P +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ C 0 -700 100 R 30 30 0 1 P +X ~ D 0 -800 100 R 30 30 0 1 P +X ~ J 0 -200 100 R 30 30 0 1 P +X ~ QA 600 -200 100 L 30 30 0 1 P +X ~ QB 600 -400 100 L 30 30 0 1 P +X ~ QC 600 -600 100 L 30 30 0 1 P +X ~ QD 600 -800 100 L 30 30 0 1 P +X ~ GND 200 -1300 100 U 30 30 0 1 W +X ~ CLK 0 -1000 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \K\ 0 -300 100 R 30 30 0 1 P +X ~ \Q\D 600 -1000 100 L 30 30 0 1 P +X ~ \CLR\ 300 -1300 100 U 30 30 0 1 P +X ~ SH/\LD\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74196_PSPICE +# +DEF 74196_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74196_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -500 100 R 30 30 0 1 P +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ C 0 -700 100 R 30 30 0 1 P +X ~ D 0 -800 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -200 100 R 30 30 0 1 P +X ~ CLK2 0 -300 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74197_PSPICE +# +DEF 74197_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74197_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 -500 100 R 30 30 0 1 P +X ~ B 0 -600 100 R 30 30 0 1 P +X ~ C 0 -700 100 R 30 30 0 1 P +X ~ D 0 -800 100 R 30 30 0 1 P +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -200 100 R 30 30 0 1 P +X ~ CLK2 0 -300 100 R 30 30 0 1 P +X ~ \LOAD\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7420_PSPICE +# +DEF 7420_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7420_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7422_PSPICE +# +DEF 7422_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7422_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 P +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7423_PSPICE +# +DEF 7423_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7423_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -1300 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -1300 100 -1300 N +P 2 0 1 0 500 100 500 -1300 N +X ~ X 0 -500 100 R 30 30 0 1 I +X ~ 1A 0 0 100 R 30 30 0 1 I +X ~ 2A 0 -800 100 R 30 30 0 1 I +X ~ 1B 0 -100 100 R 30 30 0 1 I +X ~ 2B 0 -900 100 R 30 30 0 1 I +X ~ 1C 0 -200 100 R 30 30 0 1 I +X ~ 2C 0 -1000 100 R 30 30 0 1 I +X ~ 1D 0 -300 100 R 30 30 0 1 I +X ~ 2D 0 -1100 100 R 30 30 0 1 I +X ~ 1G 0 -400 100 R 30 30 0 1 I +X ~ 2G 0 -1200 100 R 30 30 0 1 I +X ~ 1Y 600 -200 100 L 30 30 0 1 I +X ~ 2Y 600 -1000 100 L 30 30 0 1 I +X ~ GND 300 -1400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \X\ 0 -600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74246_PSPICE +# +DEF 74246_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74246_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74248_PSPICE +# +DEF 74248_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74248_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74249_PSPICE +# +DEF 74249_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74249_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ INA 0 0 100 R 30 30 0 1 P +X ~ INB 0 -100 100 R 30 30 0 1 P +X ~ INC 0 -200 100 R 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ IND 0 -300 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 0 100 L 30 30 0 1 P +X ~ OUTB 600 -100 100 L 30 30 0 1 P +X ~ OUTC 600 -200 100 L 30 30 0 1 P +X ~ OUTD 600 -300 100 L 30 30 0 1 P +X ~ OUTE 600 -400 100 L 30 30 0 1 P +X ~ OUTF 600 -500 100 L 30 30 0 1 P +X ~ OUTG 600 -600 100 L 30 30 0 1 P +X ~ \RBI\ 0 -700 100 R 30 30 0 1 P +X ~ \BI\/\RBO\ 0 -800 100 R 30 30 0 1 P +X ~ \LT\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74251_PSPICE +# +DEF 74251_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74251_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ A 0 -1100 100 R 30 30 0 1 P +X ~ B 0 -1200 100 R 30 30 0 1 P +X ~ C 0 -1300 100 R 30 30 0 1 P +X ~ Y 600 -200 100 L 30 30 0 1 P +X ~ D0 0 -200 100 R 30 30 0 1 P +X ~ D1 0 -300 100 R 30 30 0 1 P +X ~ D2 0 -400 100 R 30 30 0 1 P +X ~ D3 0 -500 100 R 30 30 0 1 P +X ~ D4 0 -600 100 R 30 30 0 1 P +X ~ D5 0 -700 100 R 30 30 0 1 P +X ~ D6 0 -800 100 R 30 30 0 1 P +X ~ D7 0 -900 100 R 30 30 0 1 P +X ~ GND 300 -1500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +X ~ \W\ 600 -400 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74259_PSPICE +# +DEF 74259_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74259_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ D 0 -200 100 R 30 30 0 1 P +X ~ Q0 600 0 100 L 30 30 0 1 P +X ~ S0 0 -400 100 R 30 30 0 1 P +X ~ Q1 600 -100 100 L 30 30 0 1 P +X ~ S1 0 -500 100 R 30 30 0 1 P +X ~ Q2 600 -200 100 L 30 30 0 1 P +X ~ S2 0 -600 100 R 30 30 0 1 P +X ~ Q3 600 -300 100 L 30 30 0 1 P +X ~ Q4 600 -400 100 L 30 30 0 1 P +X ~ Q5 600 -500 100 L 30 30 0 1 P +X ~ Q6 600 -600 100 L 30 30 0 1 P +X ~ Q7 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1000 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7425_PSPICE +# +DEF 7425_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7425_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -500 100 -500 N +P 2 0 1 0 500 100 500 -500 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ G 0 -400 100 R 30 30 0 1 I +X ~ Y 600 -200 100 L 30 30 0 1 I +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74265_PSPICE +# +DEF 74265_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74265_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ 1A 0 0 100 R 30 30 0 1 P +X ~ 2A 0 -300 100 R 30 30 0 1 P +X ~ 3A 0 -600 100 R 30 30 0 1 P +X ~ 4A 0 -900 100 R 30 30 0 1 P +X ~ 2B 0 -400 100 R 30 30 0 1 P +X ~ 3B 0 -700 100 R 30 30 0 1 P +X ~ 1W 600 0 100 L 30 30 0 1 P +X ~ 2W 600 -300 100 L 30 30 0 1 P +X ~ 3W 600 -600 100 L 30 30 0 1 P +X ~ 4W 600 -900 100 L 30 30 0 1 P +X ~ 1Y 600 -100 100 L 30 30 0 1 P +X ~ 2Y 600 -400 100 L 30 30 0 1 P +X ~ 3Y 600 -700 100 L 30 30 0 1 P +X ~ 4Y 600 -1000 100 L 30 30 0 1 P +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7426_PSPICE +# +DEF 7426_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7426_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74273_PSPICE +# +DEF 74273_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74273_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ D1 0 0 100 R 30 30 0 1 P +X ~ Q1 600 0 100 L 30 30 0 1 P +X ~ D2 0 -100 100 R 30 30 0 1 P +X ~ Q2 600 -100 100 L 30 30 0 1 P +X ~ D3 0 -200 100 R 30 30 0 1 P +X ~ Q3 600 -200 100 L 30 30 0 1 P +X ~ D4 0 -300 100 R 30 30 0 1 P +X ~ Q4 600 -300 100 L 30 30 0 1 P +X ~ D5 0 -400 100 R 30 30 0 1 P +X ~ Q5 600 -400 100 L 30 30 0 1 P +X ~ D6 0 -500 100 R 30 30 0 1 P +X ~ Q6 600 -500 100 L 30 30 0 1 P +X ~ D7 0 -600 100 R 30 30 0 1 P +X ~ Q7 600 -600 100 L 30 30 0 1 P +X ~ D8 0 -700 100 R 30 30 0 1 P +X ~ Q8 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74276_PSPICE +# +DEF 74276_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74276_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -1300 0 1 0 N +X ~ 1J 0 0 100 R 30 30 0 1 P +X ~ 2J 0 -300 100 R 30 30 0 1 P +X ~ 3J 0 -600 100 R 30 30 0 1 P +X ~ 4J 0 -900 100 R 30 30 0 1 P +X ~ 1Q 600 0 100 L 30 30 0 1 P +X ~ 2Q 600 -300 100 L 30 30 0 1 P +X ~ 3Q 600 -600 100 L 30 30 0 1 P +X ~ 4Q 600 -900 100 L 30 30 0 1 P +X ~ GND 200 -1400 100 U 30 30 0 1 W +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \PRE\ 300 300 100 D 30 30 0 1 P +X ~ 1CLK 0 -100 100 R 30 30 0 1 P +X ~ 2CLK 0 -400 100 R 30 30 0 1 P +X ~ 3CLK 0 -700 100 R 30 30 0 1 P +X ~ 4CLK 0 -1000 100 R 30 30 0 1 P +X ~ \CLR\ 300 -1400 100 U 30 30 0 1 P +X ~ 1\K\ 0 -200 100 R 30 30 0 1 P +X ~ 2\K\ 0 -500 100 R 30 30 0 1 P +X ~ 3\K\ 0 -800 100 R 30 30 0 1 P +X ~ 4\K\ 0 -1100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74278_PSPICE +# +DEF 74278_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74278_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -700 0 1 0 N +X ~ P0 0 0 100 R 30 30 0 1 P +X ~ D1 0 -300 100 R 30 30 0 1 P +X ~ P1 600 0 100 L 30 30 0 1 P +X ~ Y1 600 -300 100 L 30 30 0 1 P +X ~ D2 0 -400 100 R 30 30 0 1 P +X ~ Y2 600 -400 100 L 30 30 0 1 P +X ~ D3 0 -500 100 R 30 30 0 1 P +X ~ Y3 600 -500 100 L 30 30 0 1 P +X ~ D4 0 -600 100 R 30 30 0 1 P +X ~ Y4 600 -600 100 L 30 30 0 1 P +X ~ GND 300 -800 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ STRB 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74279_PSPICE +# +DEF 74279_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74279_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -600 0 1 0 N +X ~ 1Q 600 -200 100 L 30 30 0 1 P +X ~ 2Q 600 -500 100 L 30 30 0 1 P +X ~ GND 300 -700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\R\ 0 0 100 R 30 30 0 1 P +X ~ 2\R\ 0 -400 100 R 30 30 0 1 P +X ~ 1\S\1 0 -100 100 R 30 30 0 1 P +X ~ 1\S\2 0 -200 100 R 30 30 0 1 P +X ~ 2\S\ 0 -500 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7427_PSPICE +# +DEF 7427_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7427_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74283_PSPICE +# +DEF 74283_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74283_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ C0 0 -900 100 R 30 30 0 1 P +X ~ A1 0 -700 100 R 30 30 0 1 P +X ~ B1 0 -600 100 R 30 30 0 1 P +X ~ A2 0 -500 100 R 30 30 0 1 P +X ~ B2 0 -400 100 R 30 30 0 1 P +X ~ A3 0 -300 100 R 30 30 0 1 P +X ~ B3 0 -200 100 R 30 30 0 1 P +X ~ A4 0 -100 100 R 30 30 0 1 P +X ~ B4 0 0 100 R 30 30 0 1 P +X ~ C4 600 -900 100 L 30 30 0 1 P +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SUM1 600 -700 100 L 30 30 0 1 P +X ~ SUM2 600 -500 100 L 30 30 0 1 P +X ~ SUM3 600 -300 100 L 30 30 0 1 P +X ~ SUM4 600 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7428_PSPICE +# +DEF 7428_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7428_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74290_PSPICE +# +DEF 74290_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74290_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ QA 600 -100 100 L 30 30 0 1 P +X ~ QB 600 -300 100 L 30 30 0 1 P +X ~ QC 600 -500 100 L 30 30 0 1 P +X ~ QD 600 -700 100 L 30 30 0 1 P +X ~ R01 0 -600 100 R 30 30 0 1 P +X ~ R91 0 0 100 R 30 30 0 1 P +X ~ R02 0 -700 100 R 30 30 0 1 P +X ~ R92 0 -100 100 R 30 30 0 1 P +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLKA 0 -300 100 R 30 30 0 1 P +X ~ CLKB 0 -400 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74293_PSPICE +# +DEF 74293_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74293_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ QA 600 0 100 L 30 30 0 1 P +X ~ QB 600 -100 100 L 30 30 0 1 P +X ~ QC 600 -200 100 L 30 30 0 1 P +X ~ QD 600 -300 100 L 30 30 0 1 P +X ~ R01 0 -300 100 R 30 30 0 1 P +X ~ R02 0 -400 100 R 30 30 0 1 P +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLKA 0 0 100 R 30 30 0 1 P +X ~ CLKB 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74298_PSPICE +# +DEF 74298_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74298_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ A1 0 -200 100 R 30 30 0 1 P +X ~ B1 0 -400 100 R 30 30 0 1 P +X ~ C1 0 -600 100 R 30 30 0 1 P +X ~ D1 0 -800 100 R 30 30 0 1 P +X ~ A2 0 -300 100 R 30 30 0 1 P +X ~ B2 0 -500 100 R 30 30 0 1 P +X ~ C2 0 -700 100 R 30 30 0 1 P +X ~ D2 0 -900 100 R 30 30 0 1 P +X ~ QA 600 -200 100 L 30 30 0 1 P +X ~ QB 600 -400 100 L 30 30 0 1 P +X ~ QC 600 -600 100 L 30 30 0 1 P +X ~ QD 600 -800 100 L 30 30 0 1 P +X ~ WS 0 0 100 R 30 30 0 1 P +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ CLK 0 -1000 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7430_PSPICE +# +DEF 7430_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7430_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ E 0 -400 100 R 30 30 0 1 I +X ~ F 0 -500 100 R 30 30 0 1 I +X ~ G 0 -600 100 R 30 30 0 1 I +X ~ H 0 -700 100 R 30 30 0 1 I +X ~ Y 600 -300 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7432_PSPICE +# +DEF 7432_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7432_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7433_PSPICE +# +DEF 7433_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7433_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 60 -300 300 -300 N +P 2 0 1 0 60 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74351_PSPICE +# +DEF 74351_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74351_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -2000 0 1 0 N +X ~ A 0 -1700 100 R 30 30 0 1 P +X ~ B 0 -1800 100 R 30 30 0 1 P +X ~ C 0 -1900 100 R 30 30 0 1 P +X ~ D4 0 -1200 100 R 30 30 0 1 P +X ~ D5 0 -1300 100 R 30 30 0 1 P +X ~ D6 0 -1400 100 R 30 30 0 1 P +X ~ D7 0 -1500 100 R 30 30 0 1 P +X ~ 1Y 600 -200 100 L 30 30 0 1 P +X ~ 2Y 600 -700 100 L 30 30 0 1 P +X ~ 1D0 0 -200 100 R 30 30 0 1 P +X ~ 2D0 0 -700 100 R 30 30 0 1 P +X ~ 1D1 0 -300 100 R 30 30 0 1 P +X ~ 2D1 0 -800 100 R 30 30 0 1 P +X ~ 1D2 0 -400 100 R 30 30 0 1 P +X ~ 2D2 0 -900 100 R 30 30 0 1 P +X ~ 1D3 0 -500 100 R 30 30 0 1 P +X ~ 2D3 0 -1000 100 R 30 30 0 1 P +X ~ GND 300 -2100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74365A_PSPICE +# +DEF 74365A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74365A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A1 0 -300 100 R 30 30 0 1 P +X ~ Y1 600 -300 100 L 30 30 0 1 P +X ~ A2 0 -400 100 R 30 30 0 1 P +X ~ Y2 600 -400 100 L 30 30 0 1 P +X ~ A3 0 -500 100 R 30 30 0 1 P +X ~ Y3 600 -500 100 L 30 30 0 1 P +X ~ A4 0 -600 100 R 30 30 0 1 P +X ~ Y4 600 -600 100 L 30 30 0 1 P +X ~ A5 0 -700 100 R 30 30 0 1 P +X ~ Y5 600 -700 100 L 30 30 0 1 P +X ~ A6 0 -800 100 R 30 30 0 1 P +X ~ Y6 600 -800 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 P +X ~ \G\2 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74366A_PSPICE +# +DEF 74366A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74366A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ A1 0 -300 100 R 30 30 0 1 P +X ~ Y1 600 -300 100 L 30 30 0 1 P +X ~ A2 0 -400 100 R 30 30 0 1 P +X ~ Y2 600 -400 100 L 30 30 0 1 P +X ~ A3 0 -500 100 R 30 30 0 1 P +X ~ Y3 600 -500 100 L 30 30 0 1 P +X ~ A4 0 -600 100 R 30 30 0 1 P +X ~ Y4 600 -600 100 L 30 30 0 1 P +X ~ A5 0 -700 100 R 30 30 0 1 P +X ~ Y5 600 -700 100 L 30 30 0 1 P +X ~ A6 0 -800 100 R 30 30 0 1 P +X ~ Y6 600 -800 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \G\1 0 0 100 R 30 30 0 1 P +X ~ \G\2 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74367A_PSPICE +# +DEF 74367A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74367A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ 1A1 0 -100 100 R 30 30 0 1 P +X ~ 2A1 0 -700 100 R 30 30 0 1 P +X ~ 1Y1 600 -100 100 L 30 30 0 1 P +X ~ 2Y1 600 -700 100 L 30 30 0 1 P +X ~ 1A2 0 -200 100 R 30 30 0 1 P +X ~ 2A2 0 -800 100 R 30 30 0 1 P +X ~ 1Y2 600 -200 100 L 30 30 0 1 P +X ~ 2Y2 600 -800 100 L 30 30 0 1 P +X ~ 1A3 0 -300 100 R 30 30 0 1 P +X ~ 1Y3 600 -300 100 L 30 30 0 1 P +X ~ 1A4 0 -400 100 R 30 30 0 1 P +X ~ 1Y4 600 -400 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\G\ 0 0 100 R 30 30 0 1 P +X ~ 2\G\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74368A_PSPICE +# +DEF 74368A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74368A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ 1A1 0 -100 100 R 30 30 0 1 P +X ~ 2A1 0 -700 100 R 30 30 0 1 P +X ~ 1Y1 600 -100 100 L 30 30 0 1 P +X ~ 2Y1 600 -700 100 L 30 30 0 1 P +X ~ 1A2 0 -200 100 R 30 30 0 1 P +X ~ 2A2 0 -800 100 R 30 30 0 1 P +X ~ 1Y2 600 -200 100 L 30 30 0 1 P +X ~ 2Y2 600 -800 100 L 30 30 0 1 P +X ~ 1A3 0 -300 100 R 30 30 0 1 P +X ~ 1Y3 600 -300 100 L 30 30 0 1 P +X ~ 1A4 0 -400 100 R 30 30 0 1 P +X ~ 1Y4 600 -400 100 L 30 30 0 1 P +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\G\ 0 0 100 R 30 30 0 1 P +X ~ 2\G\ 0 -600 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 74376_PSPICE +# +DEF 74376_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74376_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ 1J 0 0 100 R 30 30 0 1 P +X ~ 2J 0 -200 100 R 30 30 0 1 P +X ~ 3J 0 -400 100 R 30 30 0 1 P +X ~ 4J 0 -600 100 R 30 30 0 1 P +X ~ 1Q 600 -100 100 L 30 30 0 1 P +X ~ 2Q 600 -300 100 L 30 30 0 1 P +X ~ 3Q 600 -500 100 L 30 30 0 1 P +X ~ 4Q 600 -700 100 L 30 30 0 1 P +X ~ GND 200 -1100 100 U 30 30 0 1 W +X ~ CLK 0 -800 100 R 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \CLR\ 300 -1100 100 U 30 30 0 1 P +X ~ 1\K\ 0 -100 100 R 30 30 0 1 P +X ~ 2\K\ 0 -300 100 R 30 30 0 1 P +X ~ 3\K\ 0 -500 100 R 30 30 0 1 P +X ~ 4\K\ 0 -700 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7437_PSPICE +# +DEF 7437_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7437_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7438_PSPICE +# +DEF 7438_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7438_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74390_PSPICE +# +DEF 74390_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74390_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -400 0 1 0 N +X ~ QA 600 100 100 L 30 30 0 1 P +X ~ QB 600 0 100 L 30 30 0 1 P +X ~ QC 600 -100 100 L 30 30 0 1 P +X ~ QD 600 -200 100 L 30 30 0 1 P +X ~ CKA 0 0 100 R 30 30 0 1 P +X ~ CKB 0 -200 100 R 30 30 0 1 P +X ~ GND 200 -500 100 U 30 30 0 1 W +X ~ CLR 300 -500 100 U 30 30 0 1 P +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74393_PSPICE +# +DEF 74393_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74393_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -400 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ QA 600 0 100 L 30 30 0 1 P +X ~ QB 600 -100 100 L 30 30 0 1 P +X ~ QC 600 -200 100 L 30 30 0 1 P +X ~ QD 600 -300 100 L 30 30 0 1 P +X ~ GND 200 -500 100 U 30 30 0 1 W +X ~ CLR 300 -500 100 U 30 30 0 1 P +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7439_PSPICE +# +DEF 7439_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7439_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 P +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7440_PSPICE +# +DEF 7440_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7440_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -200 200 -899 899 0 1 0 N 400 -400 400 0 +P 2 0 1 0 100 -400 400 -400 N +P 2 0 1 0 100 0 100 -400 N +P 2 0 1 0 400 0 100 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ D 0 -400 100 R 30 30 0 1 I +X ~ Y 700 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 100 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74425_PSPICE +# +DEF 74425_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74425_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -160 40 0 1 0 N +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -140 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +X ~ \G\ 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74426_PSPICE +# +DEF 74426_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74426_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 400 -300 N +P 2 0 1 0 100 -100 100 -500 N +P 2 0 1 0 100 0 250 0 N +P 2 0 1 0 250 0 250 -200 N +P 2 0 1 0 400 -300 100 -100 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ G 0 0 100 R 30 30 0 1 I +X ~ Y 500 -300 100 L 30 30 0 1 O +X ~ GND 200 -530 100 U 30 30 0 1 W +X ~ PWR 200 -70 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7442A_PSPICE +# +DEF 7442A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7442A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7443A_PSPICE +# +DEF 7443A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7443A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7444A_PSPICE +# +DEF 7444A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7444A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7445_PSPICE +# +DEF 7445_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7445_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 200 500 -900 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ Y0 600 100 100 L 30 30 0 1 O +X ~ Y1 600 0 100 L 30 30 0 1 O +X ~ Y2 600 -100 100 L 30 30 0 1 O +X ~ Y3 600 -200 100 L 30 30 0 1 O +X ~ Y4 600 -300 100 L 30 30 0 1 O +X ~ Y5 600 -400 100 L 30 30 0 1 O +X ~ Y6 600 -500 100 L 30 30 0 1 O +X ~ Y7 600 -600 100 L 30 30 0 1 O +X ~ Y8 600 -700 100 L 30 30 0 1 O +X ~ Y9 600 -800 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 300 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7446A_PSPICE +# +DEF 7446A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7446A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ INA 0 -400 100 R 30 30 0 1 I +X ~ INB 0 -500 100 R 30 30 0 1 I +X ~ INC 0 -600 100 R 30 30 0 1 I +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ IND 0 -700 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ OUTA 600 -100 100 L 30 30 0 1 O +X ~ OUTB 600 -200 100 L 30 30 0 1 O +X ~ OUTC 600 -300 100 L 30 30 0 1 O +X ~ OUTD 600 -400 100 L 30 30 0 1 O +X ~ OUTE 600 -500 100 L 30 30 0 1 O +X ~ OUTF 600 -600 100 L 30 30 0 1 O +X ~ OUTG 600 -700 100 L 30 30 0 1 O +X ~ \RBI\ 0 -100 100 R 30 30 0 1 I +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +X ~ \LT\ 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7448_PSPICE +# +DEF 7448_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7448_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ A 0 -400 100 R 30 30 0 1 I +X ~ B 0 -500 100 R 30 30 0 1 I +X ~ C 0 -600 100 R 30 30 0 1 I +X ~ D 0 -700 100 R 30 30 0 1 I +X ~ OA 600 0 100 L 30 30 0 1 O +X ~ OB 600 -100 100 L 30 30 0 1 O +X ~ OC 600 -200 100 L 30 30 0 1 O +X ~ OD 600 -300 100 L 30 30 0 1 O +X ~ OE 600 -400 100 L 30 30 0 1 O +X ~ OF 600 -500 100 L 30 30 0 1 O +X ~ OG 600 -600 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \RBI\ 0 -100 100 R 30 30 0 1 I +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +X ~ \LT\ 0 -200 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74490_PSPICE +# +DEF 74490_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74490_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -400 0 1 0 N +X ~ QA 600 100 100 L 30 30 0 1 P +X ~ QB 600 0 100 L 30 30 0 1 P +X ~ QC 600 -100 100 L 30 30 0 1 P +X ~ QD 600 -200 100 L 30 30 0 1 P +X ~ GND 200 -500 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 P +X ~ CLR 300 -500 100 U 30 30 0 1 P +X ~ PWR 300 300 100 D 30 30 0 1 W +X ~ SET9 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# 7449_PSPICE +# +DEF 7449_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7449_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -700 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -700 100 -700 N +P 2 0 1 0 500 100 500 -700 N +X ~ A 0 -300 100 R 30 30 0 1 I +X ~ B 0 -400 100 R 30 30 0 1 I +X ~ C 0 -500 100 R 30 30 0 1 I +X ~ D 0 -600 100 R 30 30 0 1 I +X ~ OA 600 0 100 L 30 30 0 1 O +X ~ OB 600 -100 100 L 30 30 0 1 O +X ~ OC 600 -200 100 L 30 30 0 1 O +X ~ OD 600 -300 100 L 30 30 0 1 O +X ~ OE 600 -400 100 L 30 30 0 1 O +X ~ OF 600 -500 100 L 30 30 0 1 O +X ~ OG 600 -600 100 L 30 30 0 1 O +X ~ GND 300 -800 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \BI\/\RBO\ 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7450_PSPICE +# +DEF 7450_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7450_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -1100 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -1100 100 -1100 N +P 2 0 1 0 500 100 500 -1100 N +X ~ 1A 0 0 100 R 30 30 0 1 I +X ~ 2A 0 -700 100 R 30 30 0 1 I +X ~ 1B 0 -100 100 R 30 30 0 1 I +X ~ 2B 0 -800 100 R 30 30 0 1 I +X ~ 1C 0 -200 100 R 30 30 0 1 I +X ~ 2C 0 -900 100 R 30 30 0 1 I +X ~ 1D 0 -300 100 R 30 30 0 1 I +X ~ 2D 0 -1000 100 R 30 30 0 1 I +X ~ 1X 0 -400 100 R 30 30 0 1 I +X ~ 1Y 600 -200 100 L 30 30 0 1 O +X ~ 2Y 600 -900 100 L 30 30 0 1 O +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\X\ 0 -500 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7451_PSPICE +# +DEF 7451_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7451_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ Y 600 -100 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7453_PSPICE +# +DEF 7453_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7453_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1000 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ E 0 -400 100 R 30 30 0 1 I +X ~ F 0 -500 100 R 30 30 0 1 I +X ~ G 0 -600 100 R 30 30 0 1 I +X ~ H 0 -700 100 R 30 30 0 1 I +X ~ X 0 -800 100 R 30 30 0 1 I +X ~ Y 600 -400 100 L 30 30 0 1 O +X ~ GND 300 -1100 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \X\ 0 -900 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7454_PSPICE +# +DEF 7454_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7454_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -800 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ E 0 -400 100 R 30 30 0 1 I +X ~ F 0 -500 100 R 30 30 0 1 I +X ~ G 0 -600 100 R 30 30 0 1 I +X ~ H 0 -700 100 R 30 30 0 1 I +X ~ Y 600 -300 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7460_PSPICE +# +DEF 7460_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7460_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -500 100 -500 N +P 2 0 1 0 500 100 500 -500 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ D 0 -300 100 R 30 30 0 1 I +X ~ X 600 -100 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \X\ 0 -400 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7470_PSPICE +# +DEF 7470_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7470_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -800 0 1 0 N +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ J1 0 0 100 R 30 30 0 1 I +X ~ K1 0 -400 100 R 30 30 0 1 I +X ~ J2 0 -100 100 R 30 30 0 1 I +X ~ K2 0 -500 100 R 30 30 0 1 I +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -300 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \J\ 0 -200 100 R 30 30 0 1 I +X ~ \K\ 0 -600 100 R 30 30 0 1 I +X ~ \Q\ 600 -500 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7472_PSPICE +# +DEF 7472_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7472_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 200 500 -800 N +X ~ Q 600 -100 100 L 30 30 0 1 O +X ~ J1 0 0 100 R 30 30 0 1 I +X ~ K1 0 -400 100 R 30 30 0 1 I +X ~ J2 0 -100 100 R 30 30 0 1 I +X ~ K2 0 -500 100 R 30 30 0 1 I +X ~ J3 0 -200 100 R 30 30 0 1 I +X ~ K3 0 -600 100 R 30 30 0 1 I +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ CLK 0 -300 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -500 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7473_PSPICE +# +DEF 7473_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7473_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 0 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ \Q\ 600 -400 100 L 30 30 0 1 O +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7474_PSPICE +# +DEF 7474_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7474_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7475_PSPICE +# +DEF 7475_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7475_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ 1D 0 0 100 R 30 30 0 1 I +X ~ 2D 0 -100 100 R 30 30 0 1 I +X ~ 1Q 600 0 100 L 30 30 0 1 O +X ~ 2Q 600 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\Q\ 600 -100 100 L 30 30 0 1 O +X ~ 2\Q\ 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 7476_PSPICE +# +DEF 7476_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7476_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 0 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -400 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7477_PSPICE +# +DEF 7477_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7477_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ 1D 0 0 100 R 30 30 0 1 I +X ~ 2D 0 -400 100 R 30 30 0 1 I +X ~ 1Q 600 -100 100 L 30 30 0 1 O +X ~ 2Q 600 -300 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7482_PSPICE +# +DEF 7482_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7482_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ C0 0 0 100 R 30 30 0 1 I +X ~ A1 0 -100 100 R 30 30 0 1 I +X ~ B1 0 -200 100 R 30 30 0 1 I +X ~ A2 0 -300 100 R 30 30 0 1 I +X ~ B2 0 -400 100 R 30 30 0 1 I +X ~ C2 600 -400 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SUM1 600 -100 100 L 30 30 0 1 O +X ~ SUM2 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 7483A_PSPICE +# +DEF 7483A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7483A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 100 500 -900 N +X ~ C0 0 -800 100 R 30 30 0 1 I +X ~ A1 0 -300 100 R 30 30 0 1 I +X ~ B1 0 -700 100 R 30 30 0 1 I +X ~ A2 0 -200 100 R 30 30 0 1 I +X ~ B2 0 -600 100 R 30 30 0 1 I +X ~ A3 0 -100 100 R 30 30 0 1 I +X ~ B3 0 -500 100 R 30 30 0 1 I +X ~ A4 0 0 100 R 30 30 0 1 I +X ~ B4 0 -400 100 R 30 30 0 1 I +X ~ C4 600 0 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SUM1 600 -800 100 L 30 30 0 1 O +X ~ SUM2 600 -600 100 L 30 30 0 1 O +X ~ SUM3 600 -400 100 L 30 30 0 1 O +X ~ SUM4 600 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 7485_PSPICE +# +DEF 7485_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7485_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ A0 0 -700 100 R 30 30 0 1 I +X ~ B0 0 -600 100 R 30 30 0 1 I +X ~ A1 0 -500 100 R 30 30 0 1 I +X ~ B1 0 -400 100 R 30 30 0 1 I +X ~ A2 0 -300 100 R 30 30 0 1 I +X ~ B2 0 -200 100 R 30 30 0 1 I +X ~ A3 0 -100 100 R 30 30 0 1 I +X ~ B3 0 0 100 R 30 30 0 1 I +X ~ A<B 600 -400 100 L 30 30 0 1 O +X ~ A=B 600 -500 100 L 30 30 0 1 O +X ~ A>B 600 -600 100 L 30 30 0 1 O +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ A<B_IN 0 -800 100 R 30 30 0 1 I +X ~ A=B_IN 0 -900 100 R 30 30 0 1 I +X ~ A>B_IN 0 -1000 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7486_PSPICE +# +DEF 7486_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7486_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A -250 -90 400 -308 283 0 1 0 N 93 -295 101 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 100 -300 300 -300 N +P 2 0 1 0 100 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7490A_PSPICE +# +DEF 7490A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7490A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ QA 600 -100 100 L 30 30 0 1 O +X ~ QB 600 -300 100 L 30 30 0 1 O +X ~ QC 600 -500 100 L 30 30 0 1 O +X ~ QD 600 -700 100 L 30 30 0 1 O +X ~ R01 0 -700 100 R 30 30 0 1 I +X ~ R91 0 0 100 R 30 30 0 1 I +X ~ R02 0 -800 100 R 30 30 0 1 I +X ~ R92 0 -100 100 R 30 30 0 1 I +X ~ CKA 0 -300 100 R 30 30 0 1 I +X ~ CKB 0 -500 100 R 30 30 0 1 I +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7491A_PSPICE +# +DEF 7491A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7491A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -300 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -300 100 -300 N +P 2 0 1 0 500 100 500 -300 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ QH 600 0 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLOCK 0 -200 100 R 30 30 0 1 I +X ~ \QH\ 600 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 7492A_PSPICE +# +DEF 7492A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7492A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ R01 0 -200 100 R 30 30 0 1 I +X ~ R02 0 -300 100 R 30 30 0 1 I +X ~ CKA 0 0 100 R 30 30 0 1 I +X ~ CKB 0 -100 100 R 30 30 0 1 I +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7493A_PSPICE +# +DEF 7493A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7493A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ R01 0 -200 100 R 30 30 0 1 I +X ~ R02 0 -300 100 R 30 30 0 1 I +X ~ CKA 0 0 100 R 30 30 0 1 I +X ~ CKB 0 -100 100 R 30 30 0 1 I +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 7494_PSPICE +# +DEF 7494_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7494_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1600 0 1 0 N +X ~ QD 600 -700 100 L 30 30 0 1 O +X ~ PE1 0 -100 100 R 30 30 0 1 I +X ~ PE2 0 0 100 R 30 30 0 1 I +X ~ P1A 0 -300 100 R 30 30 0 1 I +X ~ P2A 0 -800 100 R 30 30 0 1 I +X ~ P1B 0 -400 100 R 30 30 0 1 I +X ~ P2B 0 -900 100 R 30 30 0 1 I +X ~ P1C 0 -500 100 R 30 30 0 1 I +X ~ P2C 0 -1000 100 R 30 30 0 1 I +X ~ P1D 0 -600 100 R 30 30 0 1 I +X ~ P2D 0 -1100 100 R 30 30 0 1 I +X ~ GND 300 -1700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLEAR 0 -1500 100 R 30 30 0 1 I +X ~ CLOCK 0 -1400 100 R 30 30 0 1 I +X ~ SER_IN 0 -1300 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7495A_PSPICE +# +DEF 7495A_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7495A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ A 0 -400 100 R 30 30 0 1 I +X ~ B 0 -500 100 R 30 30 0 1 I +X ~ C 0 -600 100 R 30 30 0 1 I +X ~ D 0 -700 100 R 30 30 0 1 I +X ~ QA 600 -400 100 L 30 30 0 1 O +X ~ QB 600 -500 100 L 30 30 0 1 O +X ~ QC 600 -600 100 L 30 30 0 1 O +X ~ QD 600 -700 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ SER 0 -100 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -200 100 R 30 30 0 1 I +X ~ CLK2 0 -300 100 R 30 30 0 1 I +X ~ MODE 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 7496_PSPICE +# +DEF 7496_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "7496_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 200 500 -800 N +X ~ A 0 -200 100 R 30 30 0 1 I +X ~ B 0 -300 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -500 100 R 30 30 0 1 I +X ~ E 0 -600 100 R 30 30 0 1 I +X ~ QA 600 -200 100 L 30 30 0 1 O +X ~ QB 600 -300 100 L 30 30 0 1 O +X ~ QC 600 -400 100 L 30 30 0 1 O +X ~ QD 600 -500 100 L 30 30 0 1 O +X ~ QE 600 -600 100 L 30 30 0 1 O +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ PRE 300 300 100 D 30 30 0 1 I +X ~ CLK 0 -100 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ SERIAL 0 0 100 R 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 74S11_PSPICE +# +DEF 74S11_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74S11_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 74_PSPICE +# +DEF 74_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "74_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 400 -100 200 -899 899 0 1 0 N 400 -300 400 100 +P 2 0 1 0 100 -300 400 -300 N +P 2 0 1 0 100 100 100 -300 N +P 2 0 1 0 400 100 100 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 75_PSPICE +# +DEF 75_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "75_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ C 0 -300 100 R 30 30 0 1 I +X ~ 1D 0 0 100 R 30 30 0 1 I +X ~ 2D 0 -100 100 R 30 30 0 1 I +X ~ 1Q 600 0 100 L 30 30 0 1 O +X ~ 2Q 600 -200 100 L 30 30 0 1 O +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ 1\Q\ 600 -100 100 L 30 30 0 1 O +X ~ 2\Q\ 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 76_PSPICE +# +DEF 76_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "76_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -600 0 1 0 N +X ~ J 0 0 100 R 30 30 0 1 I +X ~ K 0 -400 100 R 30 30 0 1 I +X ~ Q 600 0 100 L 30 30 0 1 O +X ~ GND 200 -700 100 U 30 30 0 1 W +X ~ CLK 0 -200 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ \Q\ 600 -400 100 L 30 30 0 1 O +X ~ \PRE\ 300 300 100 D 30 30 0 1 I +X ~ \CLR\ 300 -700 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 77_PSPICE +# +DEF 77_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "77_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ C 0 -200 100 R 30 30 0 1 I +X ~ 1D 0 0 100 R 30 30 0 1 I +X ~ 2D 0 -400 100 R 30 30 0 1 I +X ~ 1Q 600 -100 100 L 30 30 0 1 O +X ~ 2Q 600 -300 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 82_PSPICE +# +DEF 82_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "82_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -500 0 1 0 N +X ~ C0 0 0 100 R 30 30 0 1 I +X ~ A1 0 -100 100 R 30 30 0 1 I +X ~ B1 0 -200 100 R 30 30 0 1 I +X ~ A2 0 -300 100 R 30 30 0 1 I +X ~ B2 0 -400 100 R 30 30 0 1 I +X ~ C2 600 -400 100 L 30 30 0 1 O +X ~ GND 300 -600 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SUM1 600 -100 100 L 30 30 0 1 O +X ~ SUM2 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 83_PSPICE +# +DEF 83_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "83_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -900 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -900 100 -900 N +P 2 0 1 0 500 100 500 -900 N +X ~ C0 0 -800 100 R 30 30 0 1 I +X ~ A1 0 -300 100 R 30 30 0 1 I +X ~ B1 0 -700 100 R 30 30 0 1 I +X ~ A2 0 -200 100 R 30 30 0 1 I +X ~ B2 0 -600 100 R 30 30 0 1 I +X ~ A3 0 -100 100 R 30 30 0 1 I +X ~ B3 0 -500 100 R 30 30 0 1 I +X ~ A4 0 0 100 R 30 30 0 1 I +X ~ B4 0 -400 100 R 30 30 0 1 I +X ~ C4 600 0 100 L 30 30 0 1 O +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ SUM1 600 -800 100 L 30 30 0 1 O +X ~ SUM2 600 -600 100 L 30 30 0 1 O +X ~ SUM3 600 -400 100 L 30 30 0 1 O +X ~ SUM4 600 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 85_PSPICE +# +DEF 85_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "85_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1100 0 1 0 N +X ~ A0 0 -700 100 R 30 30 0 1 I +X ~ B0 0 -600 100 R 30 30 0 1 I +X ~ A1 0 -500 100 R 30 30 0 1 I +X ~ B1 0 -400 100 R 30 30 0 1 I +X ~ A2 0 -300 100 R 30 30 0 1 I +X ~ B2 0 -200 100 R 30 30 0 1 I +X ~ A3 0 -100 100 R 30 30 0 1 I +X ~ B3 0 0 100 R 30 30 0 1 I +X ~ A<B 600 -400 100 L 30 30 0 1 O +X ~ A=B 600 -500 100 L 30 30 0 1 O +X ~ A>B 600 -600 100 L 30 30 0 1 O +X ~ GND 300 -1200 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ A<B_IN 0 -800 100 R 30 30 0 1 I +X ~ A=B_IN 0 -900 100 R 30 30 0 1 I +X ~ A>B_IN 0 -1000 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 86_PSPICE +# +DEF 86_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "86_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -290 -90 400 -308 283 0 1 0 N 53 -295 61 100 +A -250 -90 400 -308 283 0 1 0 N 93 -295 101 100 +A 290 -220 330 212 881 0 1 0 N 597 -101 300 109 +A 290 30 330 -881 -228 0 1 0 N 300 -299 594 -97 +P 2 0 1 0 100 -300 300 -300 N +P 2 0 1 0 100 100 300 100 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -200 100 R 30 30 0 1 I +X ~ Y 700 -100 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 90_PSPICE +# +DEF 90_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "90_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -900 0 1 0 N +X ~ QA 600 -100 100 L 30 30 0 1 O +X ~ QB 600 -300 100 L 30 30 0 1 O +X ~ QC 600 -500 100 L 30 30 0 1 O +X ~ QD 600 -700 100 L 30 30 0 1 O +X ~ R01 0 -700 100 R 30 30 0 1 I +X ~ R91 0 0 100 R 30 30 0 1 I +X ~ R02 0 -800 100 R 30 30 0 1 I +X ~ R92 0 -100 100 R 30 30 0 1 I +X ~ CKA 0 -300 100 R 30 30 0 1 I +X ~ CKB 0 -500 100 R 30 30 0 1 I +X ~ GND 300 -1000 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 91_PSPICE +# +DEF 91_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "91_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -300 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -300 100 -300 N +P 2 0 1 0 500 100 500 -300 N +X ~ A 0 0 100 R 30 30 0 1 I +X ~ B 0 -100 100 R 30 30 0 1 I +X ~ QH 600 0 100 L 30 30 0 1 O +X ~ GND 300 -400 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLOCK 0 -200 100 R 30 30 0 1 I +X ~ \QH\ 600 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# 92_PSPICE +# +DEF 92_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "92_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ R01 0 -200 100 R 30 30 0 1 I +X ~ R02 0 -300 100 R 30 30 0 1 I +X ~ CKA 0 0 100 R 30 30 0 1 I +X ~ CKB 0 -100 100 R 30 30 0 1 I +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 93_PSPICE +# +DEF 93_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "93_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -400 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -400 100 -400 N +P 2 0 1 0 500 100 500 -400 N +X ~ QA 600 0 100 L 30 30 0 1 O +X ~ QB 600 -100 100 L 30 30 0 1 O +X ~ QC 600 -200 100 L 30 30 0 1 O +X ~ QD 600 -300 100 L 30 30 0 1 O +X ~ R01 0 -200 100 R 30 30 0 1 I +X ~ R02 0 -300 100 R 30 30 0 1 I +X ~ CKA 0 0 100 R 30 30 0 1 I +X ~ CKB 0 -100 100 R 30 30 0 1 I +X ~ GND 300 -500 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# 94_PSPICE +# +DEF 94_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "94_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1600 0 1 0 N +X ~ QD 600 -700 100 L 30 30 0 1 O +X ~ PE1 0 -100 100 R 30 30 0 1 I +X ~ PE2 0 0 100 R 30 30 0 1 I +X ~ P1A 0 -300 100 R 30 30 0 1 I +X ~ P2A 0 -800 100 R 30 30 0 1 I +X ~ P1B 0 -400 100 R 30 30 0 1 I +X ~ P2B 0 -900 100 R 30 30 0 1 I +X ~ P1C 0 -500 100 R 30 30 0 1 I +X ~ P2C 0 -1000 100 R 30 30 0 1 I +X ~ P1D 0 -600 100 R 30 30 0 1 I +X ~ P2D 0 -1100 100 R 30 30 0 1 I +X ~ GND 300 -1700 100 U 30 30 0 1 W +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLEAR 0 -1500 100 R 30 30 0 1 I +X ~ CLOCK 0 -1400 100 R 30 30 0 1 I +X ~ SER_IN 0 -1300 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 95_PSPICE +# +DEF 95_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "95_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 100 N +P 2 0 1 0 100 100 500 100 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 100 500 -800 N +X ~ A 0 -400 100 R 30 30 0 1 I +X ~ B 0 -500 100 R 30 30 0 1 I +X ~ C 0 -600 100 R 30 30 0 1 I +X ~ D 0 -700 100 R 30 30 0 1 I +X ~ QA 600 -400 100 L 30 30 0 1 O +X ~ QB 600 -500 100 L 30 30 0 1 O +X ~ QC 600 -600 100 L 30 30 0 1 O +X ~ QD 600 -700 100 L 30 30 0 1 O +X ~ GND 300 -900 100 U 30 30 0 1 W +X ~ SER 0 -100 100 R 30 30 0 1 I +X ~ PWR 300 200 100 D 30 30 0 1 W +X ~ CLK1 0 -200 100 R 30 30 0 1 I +X ~ CLK2 0 -300 100 R 30 30 0 1 I +X ~ MODE 0 0 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# 96_PSPICE +# +DEF 96_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "96_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -800 100 200 N +P 2 0 1 0 100 200 500 200 N +P 2 0 1 0 500 -800 100 -800 N +P 2 0 1 0 500 200 500 -800 N +X ~ A 0 -200 100 R 30 30 0 1 I +X ~ B 0 -300 100 R 30 30 0 1 I +X ~ C 0 -400 100 R 30 30 0 1 I +X ~ D 0 -500 100 R 30 30 0 1 I +X ~ E 0 -600 100 R 30 30 0 1 I +X ~ QA 600 -200 100 L 30 30 0 1 O +X ~ QB 600 -300 100 L 30 30 0 1 O +X ~ QC 600 -400 100 L 30 30 0 1 O +X ~ QD 600 -500 100 L 30 30 0 1 O +X ~ QE 600 -600 100 L 30 30 0 1 O +X ~ GND 200 -900 100 U 30 30 0 1 W +X ~ PRE 300 300 100 D 30 30 0 1 I +X ~ CLK 0 -100 100 R 30 30 0 1 I +X ~ PWR 200 300 100 D 30 30 0 1 W +X ~ SERIAL 0 0 100 R 30 30 0 1 I +X ~ \CLR\ 300 -900 100 U 30 30 0 1 I +ENDDRAW +ENDDEF +# +# A4N25_PSPICE +# +DEF A4N25_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "A4N25_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -300 0 1 0 N +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 170 -50 200 -130 N +P 2 0 1 0 200 -200 100 -200 N +P 2 0 1 0 200 -130 200 -200 N +P 2 0 1 0 200 -130 230 -50 N +P 2 0 1 0 200 0 200 -50 N +P 2 0 1 0 230 -130 170 -130 N +P 2 0 1 0 230 -50 170 -50 N +P 2 0 1 0 300 -80 300 -300 N +P 2 0 1 0 420 -80 300 -80 N +P 2 0 1 0 420 -80 500 -160 N +P 2 0 1 0 420 0 420 -160 N +P 2 0 1 0 500 -160 450 -160 N +P 2 0 1 0 500 -160 500 -300 N +P 2 0 1 0 500 -110 500 -160 N +P 2 0 1 0 500 0 420 -80 N +P 2 0 1 0 500 0 600 0 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -200 100 R 30 30 0 1 P +X ~ 4 500 -400 100 U 30 30 0 1 P +X ~ 5 700 0 100 L 30 30 0 1 P +X ~ 6 300 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM/I_PSPICE +# +DEF ABM/I_PSPICE ABMI 0 30 Y Y 1 F N +F0 "ABMI" 0 0 30 H V L CNN +F1 "ABM/I_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C -180 -90 40 0 1 0 N +S -900 100 -100 -300 0 1 0 N +P 2 0 1 0 -200 -90 -180 -120 N +P 2 0 1 0 -180 -200 -100 -200 N +P 2 0 1 0 -180 -140 -180 -200 N +P 2 0 1 0 -180 -120 -160 -90 N +P 2 0 1 0 -180 -40 -180 -140 N +P 2 0 1 0 -180 0 -180 -40 N +P 2 0 1 0 -100 0 -180 0 N +X ~ out+ 0 0 100 L 30 30 0 1 P +X ~ out- 0 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM1/I_PSPICE +# +DEF ABM1/I_PSPICE ABMII 0 30 Y Y 1 F N +F0 "ABMII" 0 0 30 H V L CNN +F1 "ABM1/I_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 720 10 40 0 1 0 N +S 100 200 800 -200 0 1 0 N +P 2 0 1 0 700 10 720 -20 N +P 2 0 1 0 720 -100 800 -100 N +P 2 0 1 0 720 -40 720 -100 N +P 2 0 1 0 720 -20 740 10 N +P 2 0 1 0 720 60 720 -40 N +P 2 0 1 0 720 100 720 60 N +P 2 0 1 0 800 100 720 100 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ out+ 900 100 100 L 30 30 0 1 P +X ~ out- 900 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM1_PSPICE +# +DEF ABM1_PSPICE ABM1 0 30 Y Y 1 F N +F0 "ABM1" 0 0 30 H V L CNN +F1 "ABM1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 800 -200 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 900 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM2/I_PSPICE +# +DEF ABM2/I_PSPICE ABM2I 0 30 Y Y 1 F N +F0 "ABM2I" 0 0 30 H V L CNN +F1 "ABM2/I_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 720 -90 40 0 1 0 N +S 100 100 800 -300 0 1 0 N +P 2 0 1 0 700 -90 720 -120 N +P 2 0 1 0 720 -200 800 -200 N +P 2 0 1 0 720 -140 720 -200 N +P 2 0 1 0 720 -120 740 -90 N +P 2 0 1 0 720 -40 720 -140 N +P 2 0 1 0 720 0 720 -40 N +P 2 0 1 0 800 0 720 0 N +X ~ IN1 0 0 100 R 30 30 0 1 P +X ~ IN2 0 -200 100 R 30 30 0 1 P +X ~ out+ 900 0 100 L 30 30 0 1 P +X ~ out- 900 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM2_PSPICE +# +DEF ABM2_PSPICE ABM2 0 30 Y Y 1 F N +F0 "ABM2" 0 0 30 H V L CNN +F1 "ABM2_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 800 -300 0 1 0 N +X ~ IN1 0 0 100 R 30 30 0 1 P +X ~ IN2 0 -200 100 R 30 30 0 1 P +X ~ OUT 900 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM3/I_PSPICE +# +DEF ABM3/I_PSPICE ABM3I 0 30 Y Y 1 F N +F0 "ABM3I" 0 0 30 H V L CNN +F1 "ABM3/I_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 720 -90 40 0 1 0 N +S 100 100 800 -300 0 1 0 N +P 2 0 1 0 700 -90 720 -120 N +P 2 0 1 0 720 -200 800 -200 N +P 2 0 1 0 720 -140 720 -200 N +P 2 0 1 0 720 -120 740 -90 N +P 2 0 1 0 720 -40 720 -140 N +P 2 0 1 0 720 0 720 -40 N +P 2 0 1 0 800 0 720 0 N +X ~ IN1 0 0 100 R 30 30 0 1 P +X ~ IN2 0 -100 100 R 30 30 0 1 P +X ~ IN3 0 -200 100 R 30 30 0 1 P +X ~ out+ 900 0 100 L 30 30 0 1 P +X ~ out- 900 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM3_PSPICE +# +DEF ABM3_PSPICE ABM3 0 30 Y Y 1 F N +F0 "ABM3" 0 0 30 H V L CNN +F1 "ABM3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 800 -300 0 1 0 N +X ~ IN1 0 0 100 R 30 30 0 1 P +X ~ IN2 0 -100 100 R 30 30 0 1 P +X ~ IN3 0 -200 100 R 30 30 0 1 P +X ~ OUT 900 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABM_PSPICE +# +DEF ABM_PSPICE ABM 0 30 Y Y 1 F N +F0 "ABM" 0 0 30 H V L CNN +F1 "ABM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -900 200 -100 -200 0 1 0 N +X ~ OUT 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ABS_PSPICE +# +DEF ABS_PSPICE ABS 0 30 Y Y 1 F N +F0 "ABS" 0 0 30 H V L CNN +F1 "ABS_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ADC10break_PSPICE +# +DEF ADC10break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "ADC10break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ DB0 700 -900 100 L 30 30 0 1 P +X ~ DB1 700 -800 100 L 30 30 0 1 P +X ~ DB2 700 -700 100 L 30 30 0 1 P +X ~ DB3 700 -600 100 L 30 30 0 1 P +X ~ DB4 700 -500 100 L 30 30 0 1 P +X ~ DB5 700 -400 100 L 30 30 0 1 P +X ~ DB6 700 -300 100 L 30 30 0 1 P +X ~ DB7 700 -200 100 L 30 30 0 1 P +X ~ DB8 700 -100 100 L 30 30 0 1 P +X ~ DB9 700 0 100 L 30 30 0 1 P +X ~ GND 400 -1200 100 U 30 30 0 1 P +X ~ REF 0 -800 100 R 30 30 0 1 P +X ~ DGND 300 -1200 100 U 30 30 0 1 P +X ~ OVER 0 -600 100 R 30 30 0 1 P +X ~ CNVRT 0 -200 100 R 30 30 0 1 P +X ~ DPWR 300 200 100 D 30 30 0 1 P +X ~ STAT 0 -400 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ADC12break_PSPICE +# +DEF ADC12break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "ADC12break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1300 0 1 0 N +S 700 -1200 700 -1200 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ DB0 700 -1100 100 L 30 30 0 1 P +X ~ DB1 700 -1000 100 L 30 30 0 1 P +X ~ DB2 700 -900 100 L 30 30 0 1 P +X ~ DB3 700 -800 100 L 30 30 0 1 P +X ~ DB4 700 -700 100 L 30 30 0 1 P +X ~ DB5 700 -600 100 L 30 30 0 1 P +X ~ DB6 700 -500 100 L 30 30 0 1 P +X ~ DB7 700 -400 100 L 30 30 0 1 P +X ~ DB8 700 -300 100 L 30 30 0 1 P +X ~ DB9 700 -200 100 L 30 30 0 1 P +X ~ GND 400 -1400 100 U 30 30 0 1 P +X ~ REF 0 -800 100 R 30 30 0 1 P +X ~ DB10 700 -100 100 L 30 30 0 1 P +X ~ DB11 700 0 100 L 30 30 0 1 P +X ~ DGND 300 -1400 100 U 30 30 0 1 P +X ~ OVER 0 -600 100 R 30 30 0 1 P +X ~ CNVRT 0 -200 100 R 30 30 0 1 P +X ~ DPWR 300 200 100 D 30 30 0 1 P +X ~ STAT 0 -400 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ADC8break_PSPICE +# +DEF ADC8break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "ADC8break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -900 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ DB0 700 -700 100 L 30 30 0 1 P +X ~ DB1 700 -600 100 L 30 30 0 1 P +X ~ DB2 700 -500 100 L 30 30 0 1 P +X ~ DB3 700 -400 100 L 30 30 0 1 P +X ~ DB4 700 -300 100 L 30 30 0 1 P +X ~ DB5 700 -200 100 L 30 30 0 1 P +X ~ DB6 700 -100 100 L 30 30 0 1 P +X ~ DB7 700 0 100 L 30 30 0 1 P +X ~ GND 400 -1000 100 U 30 30 0 1 P +X ~ REF 0 -800 100 R 30 30 0 1 P +X ~ DGND 300 -1000 100 U 30 30 0 1 P +X ~ OVER 0 -600 100 R 30 30 0 1 P +X ~ CNVRT 0 -200 100 R 30 30 0 1 P +X ~ DPWR 300 200 100 D 30 30 0 1 P +X ~ STAT 0 -400 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# AGND_PSPICE +# +DEF AGND_PSPICE #PWR 0 30 Y Y 1 F N +F0 "#PWR" 0 0 30 H V L CNN +F1 "AGND_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -50 -100 0 -150 N +P 2 0 1 0 -50 -100 50 -100 N +P 2 0 1 0 0 -150 50 -100 N +X ~ AGND 0 0 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ARCTAN_PSPICE +# +DEF ARCTAN_PSPICE ATAN 0 30 Y Y 1 F N +F0 "ATAN" 0 0 30 H V L CNN +F1 "ARCTAN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ATAN_PSPICE +# +DEF ATAN_PSPICE ATAN 0 30 Y Y 1 F N +F0 "ATAN" 0 0 30 H V L CNN +F1 "ATAN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# BANDPASS_PSPICE +# +DEF BANDPASS_PSPICE BPASS 0 30 Y Y 1 F N +F0 "BPASS" 0 0 30 H V L CNN +F1 "BANDPASS_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 240 -40 60 1 1799 0 1 0 N 300 -40 180 -40 +A 240 40 60 1 1799 0 1 0 N 300 40 180 40 +A 240 120 60 1 1799 0 1 0 N 300 120 180 120 +A 350 -40 50 -1799 -1 0 1 0 N 300 -40 400 -40 +A 350 40 50 -1799 -1 0 1 0 N 300 40 400 40 +A 350 120 50 -1799 -1 0 1 0 N 300 120 400 120 +S 100 200 800 -200 0 1 0 N +P 2 0 1 0 180 -60 400 -20 N +P 2 0 1 0 180 100 400 140 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 900 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# BANDREJ_PSPICE +# +DEF BANDREJ_PSPICE BREJ 0 30 Y Y 1 F N +F0 "BREJ" 0 0 30 H V L CNN +F1 "BANDREJ_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 240 -40 60 1 1799 0 1 0 N 300 -40 180 -40 +A 240 40 60 1 1799 0 1 0 N 300 40 180 40 +A 240 120 60 1 1799 0 1 0 N 300 120 180 120 +A 350 -40 50 -1799 -1 0 1 0 N 300 -40 400 -40 +A 350 40 50 -1799 -1 0 1 0 N 300 40 400 40 +A 350 120 50 -1799 -1 0 1 0 N 300 120 400 120 +S 100 200 800 -200 0 1 0 N +P 2 0 1 0 180 20 400 60 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 900 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# BUBBLE_PSPICE +# +DEF BUBBLE_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "BUBBLE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 100 0 0 1 0 N +C 0 130 30 0 1 0 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Bbreak_PSPICE +# +DEF Bbreak_PSPICE B 0 30 Y Y 1 F N +F0 "B" 0 0 30 H V L CNN +F1 "Bbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +X ~ d 300 200 100 D 30 30 0 1 P +X ~ g 0 0 100 R 30 30 0 1 P +X ~ s 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# CD4000_PWR_PSPICE +# +DEF CD4000_PWR_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "CD4000_PWR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 0 1500 -700 0 1 0 N +P 2 0 1 0 0 -150 1500 -150 N +X ~ VDD -100 -300 100 R 30 30 0 1 P +X ~ VSS 1600 -300 100 L 30 30 0 1 P +X ~ AGND 500 -800 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# CD4016BD_PSPICE +# +DEF CD4016BD_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "CD4016BD_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 -300 500 -300 0 1 0 N +S 100 0 200 0 0 1 0 N +S 100 200 100 -200 0 1 0 N +S 100 200 100 200 0 1 0 N +S 100 200 500 200 0 1 0 N +S 500 200 500 -200 0 1 0 N +P 2 0 1 0 100 -200 100 -300 N +P 2 0 1 0 400 0 500 0 N +P 2 0 1 0 400 100 200 0 N +P 2 0 1 0 500 -200 500 -300 N +X ~ VC 0 -200 100 R 30 30 0 1 P +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ VDD 300 300 100 D 30 30 0 1 P +X ~ VSS 300 -400 100 U 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# CMOD_PSPICE +# +DEF CMOD_PSPICE K 0 30 Y Y 1 F N +F0 "K" 0 0 30 H V L CNN +F1 "CMOD_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 20 20 30 0 0 0 K Normal 0 C C +S 0 100 100 0 0 1 0 N +ENDDRAW +ENDDEF +# +# COMP_PSPICE +# +DEF COMP_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "COMP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 4 0 1 0 100 100 700 -200 100 -500 100 100 N +X ~ pin1 0 0 100 R 30 30 0 1 P +X ~ pin2 0 -300 100 R 30 30 0 1 P +X ~ pin3 800 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# CONNECTOR_PSPICE +# +DEF CONNECTOR_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "CONNECTOR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 50 -150 100 -100 N +P 2 0 1 0 50 -50 100 -100 N +P 2 0 1 0 100 -100 200 -100 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# CONST_PSPICE +# +DEF CONST_PSPICE CONST 0 30 Y Y 1 F N +F0 "CONST" 0 0 30 H V L CNN +F1 "CONST_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -100 0 1 0 N +X ~ OUT 0 0 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# COS_PSPICE +# +DEF COS_PSPICE COS 0 30 Y Y 1 F N +F0 "COS" 0 0 30 H V L CNN +F1 "COS_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# COUPLED_INDUCTOR_PSPICE +# +DEF COUPLED_INDUCTOR_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "COUPLED_INDUCTOR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# C_PSPICE +# +DEF C_PSPICE C 0 30 Y Y 1 F N +F0 "C" 0 0 30 H V L CNN +F1 "C_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 130 0 N +P 2 0 1 0 130 50 130 -50 N +P 2 0 1 0 170 0 200 0 N +P 2 0 1 0 170 50 170 -50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# C_var_PSPICE +# +DEF C_var_PSPICE C 0 30 Y Y 1 F N +F0 "C" 0 0 30 H V L CNN +F1 "C_var_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 130 0 N +P 2 0 1 0 100 50 200 -50 N +P 2 0 1 0 130 -50 130 50 N +P 2 0 1 0 170 -50 170 50 N +P 2 0 1 0 170 0 200 0 N +P 2 0 1 0 200 -50 180 -50 N +P 2 0 1 0 200 -50 200 -30 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Cbreak_PSPICE +# +DEF Cbreak_PSPICE C 0 30 Y Y 1 F N +F0 "C" 0 0 30 H V L CNN +F1 "Cbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 130 0 N +P 2 0 1 0 130 50 130 -50 N +P 2 0 1 0 170 0 200 0 N +P 2 0 1 0 170 50 170 -50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# D1N4002_PSPICE +# +DEF D1N4002_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "D1N4002_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# D1N4148_PSPICE +# +DEF D1N4148_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "D1N4148_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# D1N750_PSPICE +# +DEF D1N750_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "D1N750_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 170 70 200 50 N +P 2 0 1 0 200 -50 230 -70 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# D1N914_PSPICE +# +DEF D1N914_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "D1N914_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DAC10break_PSPICE +# +DEF DAC10break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "DAC10break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1100 0 1 0 N +X ~ DB0 0 -900 100 R 30 30 0 1 P +X ~ DB1 0 -800 100 R 30 30 0 1 P +X ~ DB2 0 -700 100 R 30 30 0 1 P +X ~ DB3 0 -600 100 R 30 30 0 1 P +X ~ DB4 0 -500 100 R 30 30 0 1 P +X ~ DB5 0 -400 100 R 30 30 0 1 P +X ~ DB6 0 -300 100 R 30 30 0 1 P +X ~ DB7 0 -200 100 R 30 30 0 1 P +X ~ DB8 0 -100 100 R 30 30 0 1 P +X ~ DB9 0 0 100 R 30 30 0 1 P +X ~ GND 400 -1200 100 U 30 30 0 1 P +X ~ REF 700 -600 100 L 30 30 0 1 P +X ~ OUT 700 -300 100 L 30 30 0 1 P +X ~ DGND 300 -1200 100 U 30 30 0 1 P +X ~ DPWR 300 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DAC12break_PSPICE +# +DEF DAC12break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "DAC12break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1300 0 1 0 N +X ~ DB0 0 -1100 100 R 30 30 0 1 P +X ~ DB1 0 -1000 100 R 30 30 0 1 P +X ~ DB2 0 -900 100 R 30 30 0 1 P +X ~ DB3 0 -800 100 R 30 30 0 1 P +X ~ DB4 0 -700 100 R 30 30 0 1 P +X ~ DB5 0 -600 100 R 30 30 0 1 P +X ~ DB6 0 -500 100 R 30 30 0 1 P +X ~ DB7 0 -400 100 R 30 30 0 1 P +X ~ DB8 0 -300 100 R 30 30 0 1 P +X ~ DB9 0 -200 100 R 30 30 0 1 P +X ~ GND 400 -1400 100 U 30 30 0 1 P +X ~ REF 700 -600 100 L 30 30 0 1 P +X ~ OUT 700 -300 100 L 30 30 0 1 P +X ~ DB10 0 -100 100 R 30 30 0 1 P +X ~ DB11 0 0 100 R 30 30 0 1 P +X ~ DGND 300 -1400 100 U 30 30 0 1 P +X ~ DPWR 300 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DAC8break_PSPICE +# +DEF DAC8break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "DAC8break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -900 0 1 0 N +X ~ DB0 0 -700 100 R 30 30 0 1 P +X ~ DB1 0 -600 100 R 30 30 0 1 P +X ~ DB2 0 -500 100 R 30 30 0 1 P +X ~ DB3 0 -400 100 R 30 30 0 1 P +X ~ DB4 0 -300 100 R 30 30 0 1 P +X ~ DB5 0 -200 100 R 30 30 0 1 P +X ~ DB6 0 -100 100 R 30 30 0 1 P +X ~ DB7 0 0 100 R 30 30 0 1 P +X ~ GND 400 -1000 100 U 30 30 0 1 P +X ~ REF 700 -600 100 L 30 30 0 1 P +X ~ OUT 700 -300 100 L 30 30 0 1 P +X ~ DGND 300 -1000 100 U 30 30 0 1 P +X ~ DPWR 300 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB25F-B_PSPICE +# +DEF DB25F-B_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "DB25F-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -2410 90 -962 62 0 1 0 N -199 -2499 -100 -2400 +P 2 0 1 0 -400 -2500 -310 -2500 N +P 2 0 1 0 -400 -2400 -400 -2500 N +P 2 0 1 0 -400 -2400 -400 -800 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -350 -1200 -380 -1220 N +P 2 0 1 0 -350 -1200 -380 -1180 N +P 2 0 1 0 -350 -1200 -260 -1200 N +P 2 0 1 0 -310 -2500 -240 -2500 N +P 2 0 1 0 -240 -2500 -180 -2500 N +P 2 0 1 0 -100 -2200 -100 -2400 N +P 2 0 1 0 -100 -800 -100 -2200 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +X ~ 10 0 -900 100 L 30 30 0 1 P +X ~ 20 0 -1900 100 L 30 30 0 1 P +X ~ 11 0 -1000 100 L 30 30 0 1 P +X ~ 21 0 -2000 100 L 30 30 0 1 P +X ~ 12 0 -1100 100 L 30 30 0 1 P +X ~ 22 0 -2100 100 L 30 30 0 1 P +X ~ 13 0 -1200 100 L 30 30 0 1 P +X ~ 23 0 -2200 100 L 30 30 0 1 P +X ~ 14 0 -1300 100 L 30 30 0 1 P +X ~ 24 0 -2300 100 L 30 30 0 1 P +X ~ 15 0 -1400 100 L 30 30 0 1 P +X ~ 25 0 -2400 100 L 30 30 0 1 P +X ~ 16 0 -1500 100 L 30 30 0 1 P +X ~ 17 0 -1600 100 L 30 30 0 1 P +X ~ 18 0 -1700 100 L 30 30 0 1 P +X ~ 19 0 -1800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB25F_PSPICE +# +DEF DB25F_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "DB25F_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -2410 90 -962 62 0 1 0 N -199 -2499 -100 -2400 +P 2 0 1 0 -400 -2500 -310 -2500 N +P 2 0 1 0 -400 -2400 -400 -2500 N +P 2 0 1 0 -400 -2400 -400 -800 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -350 -1200 -380 -1220 N +P 2 0 1 0 -350 -1200 -380 -1180 N +P 2 0 1 0 -350 -1200 -260 -1200 N +P 2 0 1 0 -310 -2500 -240 -2500 N +P 2 0 1 0 -240 -2500 -180 -2500 N +P 2 0 1 0 -100 -2200 -100 -2400 N +P 2 0 1 0 -100 -800 -100 -2200 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +X ~ 10 0 -900 100 L 30 30 0 1 P +X ~ 20 0 -1900 100 L 30 30 0 1 P +X ~ 11 0 -1000 100 L 30 30 0 1 P +X ~ 21 0 -2000 100 L 30 30 0 1 P +X ~ 12 0 -1100 100 L 30 30 0 1 P +X ~ 22 0 -2100 100 L 30 30 0 1 P +X ~ 13 0 -1200 100 L 30 30 0 1 P +X ~ 23 0 -2200 100 L 30 30 0 1 P +X ~ 14 0 -1300 100 L 30 30 0 1 P +X ~ 24 0 -2300 100 L 30 30 0 1 P +X ~ 15 0 -1400 100 L 30 30 0 1 P +X ~ 25 0 -2400 100 L 30 30 0 1 P +X ~ 16 0 -1500 100 L 30 30 0 1 P +X ~ 17 0 -1600 100 L 30 30 0 1 P +X ~ 18 0 -1700 100 L 30 30 0 1 P +X ~ 19 0 -1800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB25M-B_PSPICE +# +DEF DB25M-B_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DB25M-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -2410 90 -962 62 0 1 0 N -199 -2499 -100 -2400 +P 2 0 1 0 -400 -2500 -310 -2500 N +P 2 0 1 0 -400 -2400 -400 -2500 N +P 2 0 1 0 -400 -2400 -400 -800 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -360 -1200 -270 -1200 N +P 2 0 1 0 -310 -2500 -240 -2500 N +P 2 0 1 0 -270 -1200 -300 -1220 N +P 2 0 1 0 -270 -1200 -300 -1180 N +P 2 0 1 0 -240 -2500 -180 -2500 N +P 2 0 1 0 -100 -2200 -100 -2400 N +P 2 0 1 0 -100 -800 -100 -2200 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +X ~ 10 0 -900 100 L 30 30 0 1 P +X ~ 20 0 -1900 100 L 30 30 0 1 P +X ~ 11 0 -1000 100 L 30 30 0 1 P +X ~ 21 0 -2000 100 L 30 30 0 1 P +X ~ 12 0 -1100 100 L 30 30 0 1 P +X ~ 22 0 -2100 100 L 30 30 0 1 P +X ~ 13 0 -1200 100 L 30 30 0 1 P +X ~ 23 0 -2200 100 L 30 30 0 1 P +X ~ 14 0 -1300 100 L 30 30 0 1 P +X ~ 24 0 -2300 100 L 30 30 0 1 P +X ~ 15 0 -1400 100 L 30 30 0 1 P +X ~ 25 0 -2400 100 L 30 30 0 1 P +X ~ 16 0 -1500 100 L 30 30 0 1 P +X ~ 17 0 -1600 100 L 30 30 0 1 P +X ~ 18 0 -1700 100 L 30 30 0 1 P +X ~ 19 0 -1800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB25M_PSPICE +# +DEF DB25M_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DB25M_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -2410 90 -962 62 0 1 0 N -199 -2499 -100 -2400 +P 2 0 1 0 -400 -2500 -310 -2500 N +P 2 0 1 0 -400 -2400 -400 -2500 N +P 2 0 1 0 -400 -2400 -400 -800 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -360 -1200 -270 -1200 N +P 2 0 1 0 -310 -2500 -240 -2500 N +P 2 0 1 0 -270 -1200 -300 -1220 N +P 2 0 1 0 -270 -1200 -300 -1180 N +P 2 0 1 0 -240 -2500 -180 -2500 N +P 2 0 1 0 -100 -2200 -100 -2400 N +P 2 0 1 0 -100 -800 -100 -2200 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +X ~ 10 0 -900 100 L 30 30 0 1 P +X ~ 20 0 -1900 100 L 30 30 0 1 P +X ~ 11 0 -1000 100 L 30 30 0 1 P +X ~ 21 0 -2000 100 L 30 30 0 1 P +X ~ 12 0 -1100 100 L 30 30 0 1 P +X ~ 22 0 -2100 100 L 30 30 0 1 P +X ~ 13 0 -1200 100 L 30 30 0 1 P +X ~ 23 0 -2200 100 L 30 30 0 1 P +X ~ 14 0 -1300 100 L 30 30 0 1 P +X ~ 24 0 -2300 100 L 30 30 0 1 P +X ~ 15 0 -1400 100 L 30 30 0 1 P +X ~ 25 0 -2400 100 L 30 30 0 1 P +X ~ 16 0 -1500 100 L 30 30 0 1 P +X ~ 17 0 -1600 100 L 30 30 0 1 P +X ~ 18 0 -1700 100 L 30 30 0 1 P +X ~ 19 0 -1800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB25_PSPICE +# +DEF DB25_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DB25_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -2410 90 -962 62 0 1 0 N -199 -2499 -100 -2400 +P 2 0 1 0 -400 -2500 -310 -2500 N +P 2 0 1 0 -400 -2400 -400 -2500 N +P 2 0 1 0 -400 -2400 -400 -800 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -360 -1200 -270 -1200 N +P 2 0 1 0 -310 -2500 -240 -2500 N +P 2 0 1 0 -270 -1200 -300 -1220 N +P 2 0 1 0 -270 -1200 -300 -1180 N +P 2 0 1 0 -240 -2500 -180 -2500 N +P 2 0 1 0 -100 -2200 -100 -2400 N +P 2 0 1 0 -100 -800 -100 -2200 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +X ~ 10 0 -900 100 L 30 30 0 1 P +X ~ 20 0 -1900 100 L 30 30 0 1 P +X ~ 11 0 -1000 100 L 30 30 0 1 P +X ~ 21 0 -2000 100 L 30 30 0 1 P +X ~ 12 0 -1100 100 L 30 30 0 1 P +X ~ 22 0 -2100 100 L 30 30 0 1 P +X ~ 13 0 -1200 100 L 30 30 0 1 P +X ~ 23 0 -2200 100 L 30 30 0 1 P +X ~ 14 0 -1300 100 L 30 30 0 1 P +X ~ 24 0 -2300 100 L 30 30 0 1 P +X ~ 15 0 -1400 100 L 30 30 0 1 P +X ~ 25 0 -2400 100 L 30 30 0 1 P +X ~ 16 0 -1500 100 L 30 30 0 1 P +X ~ 17 0 -1600 100 L 30 30 0 1 P +X ~ 18 0 -1700 100 L 30 30 0 1 P +X ~ 19 0 -1800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB9F-B_PSPICE +# +DEF DB9F-B_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "DB9F-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -400 -900 -310 -900 N +P 2 0 1 0 -400 -800 -400 -900 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -320 -400 -380 -440 N +P 2 0 1 0 -320 -400 -380 -360 N +P 2 0 1 0 -320 -400 -180 -400 N +P 2 0 1 0 -310 -900 -240 -900 N +P 2 0 1 0 -240 -900 -180 -900 N +P 2 0 1 0 -200 -900 -100 -900 N +P 2 0 1 0 -200 100 -100 100 N +P 2 0 1 0 -100 -900 -100 -800 N +P 2 0 1 0 -100 0 -100 -800 N +P 2 0 1 0 -100 100 -100 0 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB9F_PSPICE +# +DEF DB9F_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "DB9F_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -400 -900 -310 -900 N +P 2 0 1 0 -400 -800 -400 -900 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -320 -400 -380 -440 N +P 2 0 1 0 -320 -400 -380 -360 N +P 2 0 1 0 -320 -400 -180 -400 N +P 2 0 1 0 -310 -900 -240 -900 N +P 2 0 1 0 -240 -900 -180 -900 N +P 2 0 1 0 -200 -900 -100 -900 N +P 2 0 1 0 -200 100 -100 100 N +P 2 0 1 0 -100 -900 -100 -800 N +P 2 0 1 0 -100 0 -100 -800 N +P 2 0 1 0 -100 100 -100 0 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB9M-B_PSPICE +# +DEF DB9M-B_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DB9M-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -810 90 -962 62 0 1 0 N -199 -899 -100 -800 +P 2 0 1 0 -400 -900 -310 -900 N +P 2 0 1 0 -400 -800 -400 -900 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -360 -400 -220 -400 N +P 2 0 1 0 -310 -900 -240 -900 N +P 2 0 1 0 -240 -900 -180 -900 N +P 2 0 1 0 -220 -400 -280 -440 N +P 2 0 1 0 -220 -400 -280 -360 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB9M_PSPICE +# +DEF DB9M_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DB9M_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -810 90 -962 62 0 1 0 N -199 -899 -100 -800 +P 2 0 1 0 -400 -900 -310 -900 N +P 2 0 1 0 -400 -800 -400 -900 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -360 -400 -220 -400 N +P 2 0 1 0 -310 -900 -240 -900 N +P 2 0 1 0 -240 -900 -180 -900 N +P 2 0 1 0 -220 -400 -280 -440 N +P 2 0 1 0 -220 -400 -280 -360 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DB9_PSPICE +# +DEF DB9_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DB9_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -220 -10 120 48 899 0 1 0 N -100 0 -220 110 +A -190 -810 90 -962 62 0 1 0 N -199 -899 -100 -800 +P 2 0 1 0 -400 -900 -310 -900 N +P 2 0 1 0 -400 -800 -400 -900 N +P 2 0 1 0 -400 0 -400 -800 N +P 2 0 1 0 -400 0 -400 100 N +P 2 0 1 0 -400 100 -220 100 N +P 2 0 1 0 -360 -400 -220 -400 N +P 2 0 1 0 -310 -900 -240 -900 N +P 2 0 1 0 -240 -900 -180 -900 N +P 2 0 1 0 -220 -400 -280 -440 N +P 2 0 1 0 -220 -400 -280 -360 N +P 2 0 1 0 -100 0 -100 -800 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ 2 0 -100 100 L 30 30 0 1 P +X ~ 3 0 -200 100 L 30 30 0 1 P +X ~ 4 0 -300 100 L 30 30 0 1 P +X ~ 5 0 -400 100 L 30 30 0 1 P +X ~ 6 0 -500 100 L 30 30 0 1 P +X ~ 7 0 -600 100 L 30 30 0 1 P +X ~ 8 0 -700 100 L 30 30 0 1 P +X ~ 9 0 -800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DIFFER_PSPICE +# +DEF DIFFER_PSPICE DIFFER 0 30 Y Y 1 F N +F0 "DIFFER" 0 0 30 H V L CNN +F1 "DIFFER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 400 -200 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 500 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DIFF_PSPICE +# +DEF DIFF_PSPICE DIFF 0 30 Y Y 1 F N +F0 "DIFF" 0 0 30 H V L CNN +F1 "DIFF_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 100 0 100 0 1 0 N +P 2 0 1 0 0 0 -60 -20 N +P 2 0 1 0 0 0 -60 20 N +P 2 0 1 0 20 0 60 0 N +P 2 0 1 0 40 20 40 -20 N +P 2 0 1 0 80 60 120 60 N +P 2 0 1 0 100 100 80 160 N +P 2 0 1 0 100 100 120 160 N +X ~ IN1 100 100 100 D 30 30 0 1 I +X ~ IN2 0 0 100 R 30 30 0 1 I +X ~ OUT 300 0 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# DIGIFPWR_PSPICE +# +DEF DIGIFPWR_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "DIGIFPWR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 0 1500 -700 0 1 0 N +P 2 0 1 0 0 -150 1500 -150 N +X ~ GND 1600 -300 100 L 30 30 0 1 P +X ~ PWR -100 -300 100 R 30 30 0 1 P +X ~ AGND 500 -800 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DIN5_PSPICE +# +DEF DIN5_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DIN5_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 100 -100 -500 0 1 0 N +P 2 0 1 0 -350 -400 -400 -450 N +P 2 0 1 0 -350 -400 -400 -350 N +P 2 0 1 0 -350 -400 -150 -400 N +P 2 0 1 0 -350 -300 -400 -350 N +P 2 0 1 0 -350 -300 -400 -250 N +P 2 0 1 0 -350 -200 -400 -250 N +P 2 0 1 0 -350 -200 -400 -150 N +P 2 0 1 0 -350 -100 -400 -150 N +P 2 0 1 0 -350 -100 -400 -50 N +P 2 0 1 0 -350 0 -400 -50 N +P 2 0 1 0 -350 0 -400 50 N +P 2 0 1 0 -200 -300 -50 -300 N +P 2 0 1 0 -150 -400 -100 -400 N +P 2 0 1 0 -150 -300 -350 -300 N +P 2 0 1 0 -150 -200 -350 -200 N +P 2 0 1 0 -150 -200 -100 -200 N +P 2 0 1 0 -150 -100 -350 -100 N +P 2 0 1 0 -150 -100 -50 -100 N +P 2 0 1 0 -150 0 -350 0 N +P 2 0 1 0 -100 0 -200 0 N +X ~ pin1 0 0 100 L 30 30 0 1 P +X ~ pin2 0 -100 100 L 30 30 0 1 P +X ~ pin3 0 -200 100 L 30 30 0 1 P +X ~ pin4 0 -300 100 L 30 30 0 1 P +X ~ pin5 0 -400 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DIN96_PSPICE +# +DEF DIN96_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "DIN96_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 50 -150 100 -100 N +P 2 0 1 0 50 -50 100 -100 N +P 2 0 1 0 100 -100 200 -100 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DXY_PSPICE +# +DEF DXY_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "DXY_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DX_PSPICE +# +DEF DX_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "DX_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Dbreak3_PSPICE +# +DEF Dbreak3_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "Dbreak3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -200 120 -200 N +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 -200 300 -200 N +P 2 0 1 0 200 -150 200 -250 N +P 2 0 1 0 200 50 200 -50 N +P 2 0 1 0 300 -200 300 0 N +P 2 0 1 0 300 0 200 0 N +P 4 0 1 0 120 -150 120 -250 200 -200 120 -150 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -200 100 R 30 30 0 1 P +X ~ 3 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DbreakCR_PSPICE +# +DEF DbreakCR_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "DbreakCR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 180 -50 220 -50 N +P 2 0 1 0 180 50 220 50 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DbreakVV_PSPICE +# +DEF DbreakVV_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "DbreakVV_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 270 0 50 1269 -1270 0 1 0 N 240 40 239 -39 +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DbreakZ_PSPICE +# +DEF DbreakZ_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "DbreakZ_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 170 70 200 50 N +P 2 0 1 0 200 -50 230 -70 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Dbreak_PSPICE +# +DEF Dbreak_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "Dbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# DigClock_PSPICE +# +DEF DigClock_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "DigClock_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -360 -20 -310 -20 N +P 2 0 1 0 -310 -20 -310 20 N +P 2 0 1 0 -310 20 -260 20 N +P 2 0 1 0 -260 -20 -210 -20 N +P 2 0 1 0 -260 20 -260 -20 N +P 2 0 1 0 -210 -20 -210 20 N +P 2 0 1 0 -210 20 -160 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ 1 0 0 100 L 30 30 0 1 P +X ~ gnd -250 -150 100 U 30 30 0 1 W +X ~ pwr -250 150 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# DigStim_PSPICE +# +DEF DigStim_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "DigStim_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -400 -20 -350 -20 N +P 2 0 1 0 -350 -20 -350 20 N +P 2 0 1 0 -350 20 -300 20 N +P 2 0 1 0 -300 -20 -250 -20 N +P 2 0 1 0 -300 20 -300 -20 N +P 2 0 1 0 -250 -20 -250 20 N +P 2 0 1 0 -250 20 -200 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ GND -200 -150 100 U 30 30 0 1 W +X ~ PWR -200 150 100 D 30 30 0 1 W +X ~ *OUT 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ECL_100K_PWR_PSPICE +# +DEF ECL_100K_PWR_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "ECL_100K_PWR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 0 1600 -1200 0 1 0 N +P 2 0 1 0 0 -150 1600 -150 N +X ~ VEE -100 -200 100 R 30 30 0 1 P +X ~ VTT -100 -400 100 R 30 30 0 1 P +X ~ VCC1 1700 -200 100 L 30 30 0 1 P +X ~ VCC2 1700 -400 100 L 30 30 0 1 P +X ~ AGND 700 -1290 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ECL_10K_PWR_PSPICE +# +DEF ECL_10K_PWR_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "ECL_10K_PWR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 0 1500 -1200 0 1 0 N +P 2 0 1 0 0 -150 1500 -150 N +X ~ VEE -100 -200 100 R 30 30 0 1 P +X ~ VTT -100 -400 100 R 30 30 0 1 P +X ~ VCC1 1600 -200 100 L 30 30 0 1 P +X ~ VCC2 1600 -400 100 L 30 30 0 1 P +X ~ AGND 700 -1300 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE26_PSPICE +# +DEF EDGE26_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "EDGE26_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 50 -150 100 -100 N +P 2 0 1 0 50 -50 100 -100 N +P 2 0 1 0 100 -100 200 -100 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE40F-B_PSPICE +# +DEF EDGE40F-B_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "EDGE40F-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -4000 0 1 0 N +X ~ A1 0 0 100 L 30 30 0 1 P +X ~ B1 0 -2000 100 L 30 30 0 1 P +X ~ A2 0 -100 100 L 30 30 0 1 P +X ~ B2 0 -2100 100 L 30 30 0 1 P +X ~ A3 0 -200 100 L 30 30 0 1 P +X ~ B3 0 -2200 100 L 30 30 0 1 P +X ~ A4 0 -300 100 L 30 30 0 1 P +X ~ B4 0 -2300 100 L 30 30 0 1 P +X ~ A5 0 -400 100 L 30 30 0 1 P +X ~ B5 0 -2400 100 L 30 30 0 1 P +X ~ A6 0 -500 100 L 30 30 0 1 P +X ~ B6 0 -2500 100 L 30 30 0 1 P +X ~ A7 0 -600 100 L 30 30 0 1 P +X ~ B7 0 -2600 100 L 30 30 0 1 P +X ~ A8 0 -700 100 L 30 30 0 1 P +X ~ B8 0 -2700 100 L 30 30 0 1 P +X ~ A9 0 -800 100 L 30 30 0 1 P +X ~ B9 0 -2800 100 L 30 30 0 1 P +X ~ A10 0 -900 100 L 30 30 0 1 P +X ~ B10 0 -2900 100 L 30 30 0 1 P +X ~ A20 0 -1900 100 L 30 30 0 1 P +X ~ B20 0 -3900 100 L 30 30 0 1 P +X ~ A11 0 -1000 100 L 30 30 0 1 P +X ~ B11 0 -3000 100 L 30 30 0 1 P +X ~ A12 0 -1100 100 L 30 30 0 1 P +X ~ B12 0 -3100 100 L 30 30 0 1 P +X ~ A13 0 -1200 100 L 30 30 0 1 P +X ~ B13 0 -3200 100 L 30 30 0 1 P +X ~ A14 0 -1300 100 L 30 30 0 1 P +X ~ B14 0 -3300 100 L 30 30 0 1 P +X ~ A15 0 -1400 100 L 30 30 0 1 P +X ~ B15 0 -3400 100 L 30 30 0 1 P +X ~ A16 0 -1500 100 L 30 30 0 1 P +X ~ B16 0 -3500 100 L 30 30 0 1 P +X ~ A17 0 -1600 100 L 30 30 0 1 P +X ~ B17 0 -3600 100 L 30 30 0 1 P +X ~ A18 0 -1700 100 L 30 30 0 1 P +X ~ B18 0 -3700 100 L 30 30 0 1 P +X ~ A19 0 -1800 100 L 30 30 0 1 P +X ~ B19 0 -3800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE40M-B_PSPICE +# +DEF EDGE40M-B_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "EDGE40M-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -4000 0 1 0 N +X ~ A1 0 0 100 L 30 30 0 1 P +X ~ B1 0 -2000 100 L 30 30 0 1 P +X ~ A2 0 -100 100 L 30 30 0 1 P +X ~ B2 0 -2100 100 L 30 30 0 1 P +X ~ A3 0 -200 100 L 30 30 0 1 P +X ~ B3 0 -2200 100 L 30 30 0 1 P +X ~ A4 0 -300 100 L 30 30 0 1 P +X ~ B4 0 -2300 100 L 30 30 0 1 P +X ~ A5 0 -400 100 L 30 30 0 1 P +X ~ B5 0 -2400 100 L 30 30 0 1 P +X ~ A6 0 -500 100 L 30 30 0 1 P +X ~ B6 0 -2500 100 L 30 30 0 1 P +X ~ A7 0 -600 100 L 30 30 0 1 P +X ~ B7 0 -2600 100 L 30 30 0 1 P +X ~ A8 0 -700 100 L 30 30 0 1 P +X ~ B8 0 -2700 100 L 30 30 0 1 P +X ~ A9 0 -800 100 L 30 30 0 1 P +X ~ B9 0 -2800 100 L 30 30 0 1 P +X ~ A10 0 -900 100 L 30 30 0 1 P +X ~ B10 0 -2900 100 L 30 30 0 1 P +X ~ A20 0 -1900 100 L 30 30 0 1 P +X ~ B20 0 -3900 100 L 30 30 0 1 P +X ~ A11 0 -1000 100 L 30 30 0 1 P +X ~ B11 0 -3000 100 L 30 30 0 1 P +X ~ A12 0 -1100 100 L 30 30 0 1 P +X ~ B12 0 -3100 100 L 30 30 0 1 P +X ~ A13 0 -1200 100 L 30 30 0 1 P +X ~ B13 0 -3200 100 L 30 30 0 1 P +X ~ A14 0 -1300 100 L 30 30 0 1 P +X ~ B14 0 -3300 100 L 30 30 0 1 P +X ~ A15 0 -1400 100 L 30 30 0 1 P +X ~ B15 0 -3400 100 L 30 30 0 1 P +X ~ A16 0 -1500 100 L 30 30 0 1 P +X ~ B16 0 -3500 100 L 30 30 0 1 P +X ~ A17 0 -1600 100 L 30 30 0 1 P +X ~ B17 0 -3600 100 L 30 30 0 1 P +X ~ A18 0 -1700 100 L 30 30 0 1 P +X ~ B18 0 -3700 100 L 30 30 0 1 P +X ~ A19 0 -1800 100 L 30 30 0 1 P +X ~ B19 0 -3800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE40_PSPICE +# +DEF EDGE40_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "EDGE40_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -4000 0 1 0 N +X ~ A1 0 0 100 L 30 30 0 1 P +X ~ B1 0 -2000 100 L 30 30 0 1 P +X ~ A2 0 -100 100 L 30 30 0 1 P +X ~ B2 0 -2100 100 L 30 30 0 1 P +X ~ A3 0 -200 100 L 30 30 0 1 P +X ~ B3 0 -2200 100 L 30 30 0 1 P +X ~ A4 0 -300 100 L 30 30 0 1 P +X ~ B4 0 -2300 100 L 30 30 0 1 P +X ~ A5 0 -400 100 L 30 30 0 1 P +X ~ B5 0 -2400 100 L 30 30 0 1 P +X ~ A6 0 -500 100 L 30 30 0 1 P +X ~ B6 0 -2500 100 L 30 30 0 1 P +X ~ A7 0 -600 100 L 30 30 0 1 P +X ~ B7 0 -2600 100 L 30 30 0 1 P +X ~ A8 0 -700 100 L 30 30 0 1 P +X ~ B8 0 -2700 100 L 30 30 0 1 P +X ~ A9 0 -800 100 L 30 30 0 1 P +X ~ B9 0 -2800 100 L 30 30 0 1 P +X ~ A10 0 -900 100 L 30 30 0 1 P +X ~ B10 0 -2900 100 L 30 30 0 1 P +X ~ A20 0 -1900 100 L 30 30 0 1 P +X ~ B20 0 -3900 100 L 30 30 0 1 P +X ~ A11 0 -1000 100 L 30 30 0 1 P +X ~ B11 0 -3000 100 L 30 30 0 1 P +X ~ A12 0 -1100 100 L 30 30 0 1 P +X ~ B12 0 -3100 100 L 30 30 0 1 P +X ~ A13 0 -1200 100 L 30 30 0 1 P +X ~ B13 0 -3200 100 L 30 30 0 1 P +X ~ A14 0 -1300 100 L 30 30 0 1 P +X ~ B14 0 -3300 100 L 30 30 0 1 P +X ~ A15 0 -1400 100 L 30 30 0 1 P +X ~ B15 0 -3400 100 L 30 30 0 1 P +X ~ A16 0 -1500 100 L 30 30 0 1 P +X ~ B16 0 -3500 100 L 30 30 0 1 P +X ~ A17 0 -1600 100 L 30 30 0 1 P +X ~ B17 0 -3600 100 L 30 30 0 1 P +X ~ A18 0 -1700 100 L 30 30 0 1 P +X ~ B18 0 -3700 100 L 30 30 0 1 P +X ~ A19 0 -1800 100 L 30 30 0 1 P +X ~ B19 0 -3800 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE62F-B_PSPICE +# +DEF EDGE62F-B_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "EDGE62F-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -6200 0 1 0 N +X ~ A1 0 0 100 L 30 30 0 1 P +X ~ B1 0 -3100 100 L 30 30 0 1 P +X ~ A2 0 -100 100 L 30 30 0 1 P +X ~ B2 0 -3200 100 L 30 30 0 1 P +X ~ A3 0 -200 100 L 30 30 0 1 P +X ~ B3 0 -3300 100 L 30 30 0 1 P +X ~ A4 0 -300 100 L 30 30 0 1 P +X ~ B4 0 -3400 100 L 30 30 0 1 P +X ~ A5 0 -400 100 L 30 30 0 1 P +X ~ B5 0 -3500 100 L 30 30 0 1 P +X ~ A6 0 -500 100 L 30 30 0 1 P +X ~ B6 0 -3600 100 L 30 30 0 1 P +X ~ A7 0 -600 100 L 30 30 0 1 P +X ~ B7 0 -3700 100 L 30 30 0 1 P +X ~ A8 0 -700 100 L 30 30 0 1 P +X ~ B8 0 -3800 100 L 30 30 0 1 P +X ~ A9 0 -800 100 L 30 30 0 1 P +X ~ B9 0 -3900 100 L 30 30 0 1 P +X ~ A10 0 -900 100 L 30 30 0 1 P +X ~ B10 0 -4000 100 L 30 30 0 1 P +X ~ A20 0 -1900 100 L 30 30 0 1 P +X ~ B20 0 -5000 100 L 30 30 0 1 P +X ~ A30 0 -2900 100 L 30 30 0 1 P +X ~ B30 0 -6000 100 L 30 30 0 1 P +X ~ A11 0 -1000 100 L 30 30 0 1 P +X ~ B11 0 -4100 100 L 30 30 0 1 P +X ~ A21 0 -2000 100 L 30 30 0 1 P +X ~ B21 0 -5100 100 L 30 30 0 1 P +X ~ A31 0 -3000 100 L 30 30 0 1 P +X ~ B31 0 -6100 100 L 30 30 0 1 P +X ~ A12 0 -1100 100 L 30 30 0 1 P +X ~ B12 0 -4200 100 L 30 30 0 1 P +X ~ A22 0 -2100 100 L 30 30 0 1 P +X ~ B22 0 -5200 100 L 30 30 0 1 P +X ~ A13 0 -1200 100 L 30 30 0 1 P +X ~ B13 0 -4300 100 L 30 30 0 1 P +X ~ A23 0 -2200 100 L 30 30 0 1 P +X ~ B23 0 -5300 100 L 30 30 0 1 P +X ~ A14 0 -1300 100 L 30 30 0 1 P +X ~ B14 0 -4400 100 L 30 30 0 1 P +X ~ A24 0 -2300 100 L 30 30 0 1 P +X ~ B24 0 -5400 100 L 30 30 0 1 P +X ~ A15 0 -1400 100 L 30 30 0 1 P +X ~ B15 0 -4500 100 L 30 30 0 1 P +X ~ A25 0 -2400 100 L 30 30 0 1 P +X ~ B25 0 -5500 100 L 30 30 0 1 P +X ~ A16 0 -1500 100 L 30 30 0 1 P +X ~ B16 0 -4600 100 L 30 30 0 1 P +X ~ A26 0 -2500 100 L 30 30 0 1 P +X ~ B26 0 -5600 100 L 30 30 0 1 P +X ~ A17 0 -1600 100 L 30 30 0 1 P +X ~ B17 0 -4700 100 L 30 30 0 1 P +X ~ A27 0 -2600 100 L 30 30 0 1 P +X ~ B27 0 -5700 100 L 30 30 0 1 P +X ~ A18 0 -1700 100 L 30 30 0 1 P +X ~ B18 0 -4800 100 L 30 30 0 1 P +X ~ A28 0 -2700 100 L 30 30 0 1 P +X ~ B28 0 -5800 100 L 30 30 0 1 P +X ~ A19 0 -1800 100 L 30 30 0 1 P +X ~ B19 0 -4900 100 L 30 30 0 1 P +X ~ A29 0 -2800 100 L 30 30 0 1 P +X ~ B29 0 -5900 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE62M-B_PSPICE +# +DEF EDGE62M-B_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "EDGE62M-B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -6200 0 1 0 N +X ~ A1 0 0 100 L 30 30 0 1 P +X ~ B1 0 -3100 100 L 30 30 0 1 P +X ~ A2 0 -100 100 L 30 30 0 1 P +X ~ B2 0 -3200 100 L 30 30 0 1 P +X ~ A3 0 -200 100 L 30 30 0 1 P +X ~ B3 0 -3300 100 L 30 30 0 1 P +X ~ A4 0 -300 100 L 30 30 0 1 P +X ~ B4 0 -3400 100 L 30 30 0 1 P +X ~ A5 0 -400 100 L 30 30 0 1 P +X ~ B5 0 -3500 100 L 30 30 0 1 P +X ~ A6 0 -500 100 L 30 30 0 1 P +X ~ B6 0 -3600 100 L 30 30 0 1 P +X ~ A7 0 -600 100 L 30 30 0 1 P +X ~ B7 0 -3700 100 L 30 30 0 1 P +X ~ A8 0 -700 100 L 30 30 0 1 P +X ~ B8 0 -3800 100 L 30 30 0 1 P +X ~ A9 0 -800 100 L 30 30 0 1 P +X ~ B9 0 -3900 100 L 30 30 0 1 P +X ~ A10 0 -900 100 L 30 30 0 1 P +X ~ B10 0 -4000 100 L 30 30 0 1 P +X ~ A20 0 -1900 100 L 30 30 0 1 P +X ~ B20 0 -5000 100 L 30 30 0 1 P +X ~ A30 0 -2900 100 L 30 30 0 1 P +X ~ B30 0 -6000 100 L 30 30 0 1 P +X ~ A11 0 -1000 100 L 30 30 0 1 P +X ~ B11 0 -4100 100 L 30 30 0 1 P +X ~ A21 0 -2000 100 L 30 30 0 1 P +X ~ B21 0 -5100 100 L 30 30 0 1 P +X ~ A31 0 -3000 100 L 30 30 0 1 P +X ~ B31 0 -6100 100 L 30 30 0 1 P +X ~ A12 0 -1100 100 L 30 30 0 1 P +X ~ B12 0 -4200 100 L 30 30 0 1 P +X ~ A22 0 -2100 100 L 30 30 0 1 P +X ~ B22 0 -5200 100 L 30 30 0 1 P +X ~ A13 0 -1200 100 L 30 30 0 1 P +X ~ B13 0 -4300 100 L 30 30 0 1 P +X ~ A23 0 -2200 100 L 30 30 0 1 P +X ~ B23 0 -5300 100 L 30 30 0 1 P +X ~ A14 0 -1300 100 L 30 30 0 1 P +X ~ B14 0 -4400 100 L 30 30 0 1 P +X ~ A24 0 -2300 100 L 30 30 0 1 P +X ~ B24 0 -5400 100 L 30 30 0 1 P +X ~ A15 0 -1400 100 L 30 30 0 1 P +X ~ B15 0 -4500 100 L 30 30 0 1 P +X ~ A25 0 -2400 100 L 30 30 0 1 P +X ~ B25 0 -5500 100 L 30 30 0 1 P +X ~ A16 0 -1500 100 L 30 30 0 1 P +X ~ B16 0 -4600 100 L 30 30 0 1 P +X ~ A26 0 -2500 100 L 30 30 0 1 P +X ~ B26 0 -5600 100 L 30 30 0 1 P +X ~ A17 0 -1600 100 L 30 30 0 1 P +X ~ B17 0 -4700 100 L 30 30 0 1 P +X ~ A27 0 -2600 100 L 30 30 0 1 P +X ~ B27 0 -5700 100 L 30 30 0 1 P +X ~ A18 0 -1700 100 L 30 30 0 1 P +X ~ B18 0 -4800 100 L 30 30 0 1 P +X ~ A28 0 -2700 100 L 30 30 0 1 P +X ~ B28 0 -5800 100 L 30 30 0 1 P +X ~ A19 0 -1800 100 L 30 30 0 1 P +X ~ B19 0 -4900 100 L 30 30 0 1 P +X ~ A29 0 -2800 100 L 30 30 0 1 P +X ~ B29 0 -5900 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EDGE62_PSPICE +# +DEF EDGE62_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "EDGE62_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 100 -100 -6200 0 1 0 N +X ~ A1 0 0 100 L 30 30 0 1 P +X ~ B1 0 -3100 100 L 30 30 0 1 P +X ~ A2 0 -100 100 L 30 30 0 1 P +X ~ B2 0 -3200 100 L 30 30 0 1 P +X ~ A3 0 -200 100 L 30 30 0 1 P +X ~ B3 0 -3300 100 L 30 30 0 1 P +X ~ A4 0 -300 100 L 30 30 0 1 P +X ~ B4 0 -3400 100 L 30 30 0 1 P +X ~ A5 0 -400 100 L 30 30 0 1 P +X ~ B5 0 -3500 100 L 30 30 0 1 P +X ~ A6 0 -500 100 L 30 30 0 1 P +X ~ B6 0 -3600 100 L 30 30 0 1 P +X ~ A7 0 -600 100 L 30 30 0 1 P +X ~ B7 0 -3700 100 L 30 30 0 1 P +X ~ A8 0 -700 100 L 30 30 0 1 P +X ~ B8 0 -3800 100 L 30 30 0 1 P +X ~ A9 0 -800 100 L 30 30 0 1 P +X ~ B9 0 -3900 100 L 30 30 0 1 P +X ~ A10 0 -900 100 L 30 30 0 1 P +X ~ B10 0 -4000 100 L 30 30 0 1 P +X ~ A20 0 -1900 100 L 30 30 0 1 P +X ~ B20 0 -5000 100 L 30 30 0 1 P +X ~ A30 0 -2900 100 L 30 30 0 1 P +X ~ B30 0 -6000 100 L 30 30 0 1 P +X ~ A11 0 -1000 100 L 30 30 0 1 P +X ~ B11 0 -4100 100 L 30 30 0 1 P +X ~ A21 0 -2000 100 L 30 30 0 1 P +X ~ B21 0 -5100 100 L 30 30 0 1 P +X ~ A31 0 -3000 100 L 30 30 0 1 P +X ~ B31 0 -6100 100 L 30 30 0 1 P +X ~ A12 0 -1100 100 L 30 30 0 1 P +X ~ B12 0 -4200 100 L 30 30 0 1 P +X ~ A22 0 -2100 100 L 30 30 0 1 P +X ~ B22 0 -5200 100 L 30 30 0 1 P +X ~ A13 0 -1200 100 L 30 30 0 1 P +X ~ B13 0 -4300 100 L 30 30 0 1 P +X ~ A23 0 -2200 100 L 30 30 0 1 P +X ~ B23 0 -5300 100 L 30 30 0 1 P +X ~ A14 0 -1300 100 L 30 30 0 1 P +X ~ B14 0 -4400 100 L 30 30 0 1 P +X ~ A24 0 -2300 100 L 30 30 0 1 P +X ~ B24 0 -5400 100 L 30 30 0 1 P +X ~ A15 0 -1400 100 L 30 30 0 1 P +X ~ B15 0 -4500 100 L 30 30 0 1 P +X ~ A25 0 -2400 100 L 30 30 0 1 P +X ~ B25 0 -5500 100 L 30 30 0 1 P +X ~ A16 0 -1500 100 L 30 30 0 1 P +X ~ B16 0 -4600 100 L 30 30 0 1 P +X ~ A26 0 -2500 100 L 30 30 0 1 P +X ~ B26 0 -5600 100 L 30 30 0 1 P +X ~ A17 0 -1600 100 L 30 30 0 1 P +X ~ B17 0 -4700 100 L 30 30 0 1 P +X ~ A27 0 -2600 100 L 30 30 0 1 P +X ~ B27 0 -5700 100 L 30 30 0 1 P +X ~ A18 0 -1700 100 L 30 30 0 1 P +X ~ B18 0 -4800 100 L 30 30 0 1 P +X ~ A28 0 -2700 100 L 30 30 0 1 P +X ~ B28 0 -5800 100 L 30 30 0 1 P +X ~ A19 0 -1800 100 L 30 30 0 1 P +X ~ B19 0 -4900 100 L 30 30 0 1 P +X ~ A29 0 -2800 100 L 30 30 0 1 P +X ~ B29 0 -5900 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# EFREQ_PSPICE +# +DEF EFREQ_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "EFREQ_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 50 400 -150 0 1 0 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# EGND_PSPICE +# +DEF EGND_PSPICE #PWR 0 30 Y Y 1 F N +F0 "#PWR" 0 0 30 H V L CNN +F1 "EGND_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -50 -100 50 -100 N +P 2 0 1 0 -30 -120 30 -120 N +P 2 0 1 0 -10 -140 10 -140 N +X ~ EGND 0 0 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ELAPLACE_PSPICE +# +DEF ELAPLACE_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "ELAPLACE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 50 400 -150 0 1 0 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# EMULT_PSPICE +# +DEF EMULT_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "EMULT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 50 500 -450 0 1 0 N +X ~ IN1+ 0 0 100 R 30 30 0 1 I +X ~ IN2+ 0 -300 100 R 30 30 0 1 I +X ~ OUT+ 600 -100 100 L 30 30 0 1 O +X ~ IN1- 0 -100 100 R 30 30 0 1 I +X ~ IN2- 0 -400 100 R 30 30 0 1 I +X ~ OUT- 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# EPOLY_PSPICE +# +DEF EPOLY_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "EPOLY_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 250 -100 250 -90 N +P 2 0 1 0 250 0 250 -10 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ESUM_PSPICE +# +DEF ESUM_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "ESUM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 50 500 -450 0 1 0 N +X ~ IN1+ 0 0 100 R 30 30 0 1 I +X ~ IN2+ 0 -300 100 R 30 30 0 1 I +X ~ OUT+ 600 -100 100 L 30 30 0 1 O +X ~ IN1- 0 -100 100 R 30 30 0 1 I +X ~ IN2- 0 -400 100 R 30 30 0 1 I +X ~ OUT- 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# ETABLE_PSPICE +# +DEF ETABLE_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "ETABLE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 50 400 -150 0 1 0 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# EVALUE_PSPICE +# +DEF EVALUE_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "EVALUE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 50 400 -150 0 1 0 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# EXP_PSPICE +# +DEF EXP_PSPICE EXP 0 30 Y Y 1 F N +F0 "EXP" 0 0 30 H V L CNN +F1 "EXP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# E_PSPICE +# +DEF E_PSPICE E 0 30 Y Y 1 F N +F0 "E" 0 0 30 H V L CNN +F1 "E_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 250 -100 250 -90 N +P 2 0 1 0 250 0 250 -10 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# FPOLY_PSPICE +# +DEF FPOLY_PSPICE F 0 30 Y Y 1 F N +F0 "F" 0 0 30 H V L CNN +F1 "FPOLY_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 100 -100 140 -100 N +P 2 0 1 0 100 0 140 0 N +P 2 0 1 0 120 -50 140 -80 N +P 2 0 1 0 140 -80 160 -50 N +P 2 0 1 0 140 0 140 -100 N +P 2 0 1 0 230 -50 250 -80 N +P 2 0 1 0 250 -80 270 -50 N +P 2 0 1 0 250 0 250 -100 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# FTABLE_PSPICE +# +DEF FTABLE_PSPICE FTABLE 0 30 Y Y 1 F N +F0 "FTABLE" 0 0 30 H V L CNN +F1 "FTABLE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +P 2 0 1 0 0 -200 500 -200 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# F_PSPICE +# +DEF F_PSPICE F 0 30 Y Y 1 F N +F0 "F" 0 0 30 H V L CNN +F1 "F_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 100 -100 140 -100 N +P 2 0 1 0 100 0 140 0 N +P 2 0 1 0 120 -50 140 -80 N +P 2 0 1 0 140 -80 160 -50 N +P 2 0 1 0 140 0 140 -100 N +P 2 0 1 0 230 -50 250 -80 N +P 2 0 1 0 250 -80 270 -50 N +P 2 0 1 0 250 0 250 -100 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# FileStim_PSPICE +# +DEF FileStim_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "FileStim_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -400 -20 -350 -20 N +P 2 0 1 0 -350 -20 -350 20 N +P 2 0 1 0 -350 20 -300 20 N +P 2 0 1 0 -300 -20 -250 -20 N +P 2 0 1 0 -300 20 -300 -20 N +P 2 0 1 0 -250 -20 -250 20 N +P 2 0 1 0 -250 20 -200 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ *1 0 0 100 L 30 30 0 1 P +X ~ GND -200 -150 100 U 30 30 0 1 W +X ~ PWR -200 150 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# GAIN_PSPICE +# +DEF GAIN_PSPICE GAIN 0 30 Y Y 1 F N +F0 "GAIN" 0 0 30 H V L CNN +F1 "GAIN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 200 100 -200 N +P 2 0 1 0 100 200 400 0 N +P 2 0 1 0 400 0 100 -200 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 500 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GFREQ_PSPICE +# +DEF GFREQ_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GFREQ_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 350 -50 40 0 1 0 N +S 100 50 400 -150 0 1 0 N +P 2 0 1 0 330 -50 350 -80 N +P 2 0 1 0 350 -80 370 -50 N +P 2 0 1 0 350 0 350 -100 N +P 2 0 1 0 350 0 400 0 N +P 2 0 1 0 400 -100 350 -100 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# GLAPLACE_PSPICE +# +DEF GLAPLACE_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GLAPLACE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 350 -50 40 0 1 0 N +S 100 50 400 -150 0 1 0 N +P 2 0 1 0 330 -50 350 -80 N +P 2 0 1 0 350 -80 370 -50 N +P 2 0 1 0 350 0 350 -100 N +P 2 0 1 0 350 0 400 0 N +P 2 0 1 0 400 -100 350 -100 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# GLIMIT_PSPICE +# +DEF GLIMIT_PSPICE GLIMIT 0 30 Y Y 1 F N +F0 "GLIMIT" 0 0 30 H V L CNN +F1 "GLIMIT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -200 0 1 0 N +P 2 0 1 0 180 -100 320 0 N +P 2 0 1 0 180 100 180 -100 N +P 2 0 1 0 320 -160 400 -160 N +P 2 0 1 0 320 0 180 100 N +P 2 0 1 0 400 -160 400 160 N +P 2 0 1 0 400 160 480 160 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GLOBAL_PSPICE +# +DEF GLOBAL_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "GLOBAL_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 50 -100 -50 0 1 0 N +X ~ 1 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GMULT_PSPICE +# +DEF GMULT_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GMULT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 450 -200 40 0 1 0 N +S 100 50 500 -450 0 1 0 N +P 2 0 1 0 430 -200 450 -230 N +P 2 0 1 0 450 -300 450 -250 N +P 2 0 1 0 450 -230 470 -200 N +P 2 0 1 0 450 -150 450 -250 N +P 2 0 1 0 450 -100 450 -150 N +P 2 0 1 0 500 -300 450 -300 N +P 2 0 1 0 500 -100 450 -100 N +X ~ IN1+ 0 0 100 R 30 30 0 1 I +X ~ IN2+ 0 -300 100 R 30 30 0 1 I +X ~ OUT+ 600 -100 100 L 30 30 0 1 O +X ~ IN1- 0 -100 100 R 30 30 0 1 I +X ~ IN2- 0 -400 100 R 30 30 0 1 I +X ~ OUT- 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# GND_ANALOG_PSPICE +# +DEF GND_ANALOG_PSPICE #PWR 0 30 Y Y 1 F N +F0 "#PWR" 0 0 30 H V L CNN +F1 "GND_ANALOG_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -50 -100 0 -150 N +P 2 0 1 0 -50 -100 50 -100 N +P 2 0 1 0 0 -150 50 -100 N +X ~ AGND 0 0 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GND_EARTH_PSPICE +# +DEF GND_EARTH_PSPICE #PWR 0 30 Y Y 1 F N +F0 "#PWR" 0 0 30 H V L CNN +F1 "GND_EARTH_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -50 -100 50 -100 N +P 2 0 1 0 -30 -120 30 -120 N +P 2 0 1 0 -10 -140 10 -140 N +X ~ EGND 0 0 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GPOLY_PSPICE +# +DEF GPOLY_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GPOLY_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 230 -50 250 -80 N +P 2 0 1 0 250 -80 270 -50 N +P 2 0 1 0 250 0 250 -100 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GSUM_PSPICE +# +DEF GSUM_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GSUM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 450 -200 40 0 1 0 N +S 100 50 500 -450 0 1 0 N +P 2 0 1 0 430 -200 450 -230 N +P 2 0 1 0 450 -300 450 -250 N +P 2 0 1 0 450 -230 470 -200 N +P 2 0 1 0 450 -150 450 -250 N +P 2 0 1 0 450 -100 450 -150 N +P 2 0 1 0 500 -300 450 -300 N +P 2 0 1 0 500 -100 450 -100 N +X ~ IN1+ 0 0 100 R 30 30 0 1 I +X ~ IN2+ 0 -300 100 R 30 30 0 1 I +X ~ OUT+ 600 -100 100 L 30 30 0 1 O +X ~ IN1- 0 -100 100 R 30 30 0 1 I +X ~ IN2- 0 -400 100 R 30 30 0 1 I +X ~ OUT- 600 -300 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# GTABLE_PSPICE +# +DEF GTABLE_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GTABLE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 350 -50 40 0 1 0 N +S 100 50 400 -150 0 1 0 N +P 2 0 1 0 330 -50 350 -80 N +P 2 0 1 0 350 -80 370 -50 N +P 2 0 1 0 350 0 350 -100 N +P 2 0 1 0 350 0 400 0 N +P 2 0 1 0 400 -100 350 -100 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# GVALUE_PSPICE +# +DEF GVALUE_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "GVALUE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 350 -50 40 0 1 0 N +S 100 50 400 -150 0 1 0 N +P 2 0 1 0 330 -50 350 -80 N +P 2 0 1 0 350 -80 370 -50 N +P 2 0 1 0 350 0 350 -100 N +P 2 0 1 0 350 0 400 0 N +P 2 0 1 0 400 -100 350 -100 N +X ~ IN+ 0 0 100 R 30 30 0 1 I +X ~ IN- 0 -100 100 R 30 30 0 1 I +X ~ OUT+ 500 0 100 L 30 30 0 1 O +X ~ OUT- 500 -100 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# G_PSPICE +# +DEF G_PSPICE G 0 30 Y Y 1 F N +F0 "G" 0 0 30 H V L CNN +F1 "G_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 230 -50 250 -80 N +P 2 0 1 0 250 -80 270 -50 N +P 2 0 1 0 250 0 250 -100 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# GaAsFET_PSPICE +# +DEF GaAsFET_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "GaAsFET_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +ENDDRAW +ENDDEF +# +# HDR20_PSPICE +# +DEF HDR20_PSPICE ~ 0 30 Y Y 1 F N +F0 "" 0 0 30 H V L CNN +F1 "HDR20_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 50 -150 100 -100 N +P 2 0 1 0 50 -50 100 -100 N +P 2 0 1 0 100 -100 200 -100 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# HDR50_PSPICE +# +DEF HDR50_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "HDR50_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 50 N +P 2 0 1 0 150 -50 100 0 N +P 2 0 1 0 150 50 400 50 N +P 2 0 1 0 400 -50 150 -50 N +P 2 0 1 0 400 50 400 -50 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# HILO_PSPICE +# +DEF HILO_PSPICE LIMIT 0 30 Y Y 1 F N +F0 "LIMIT" 0 0 30 H V L CNN +F1 "HILO_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 400 -200 0 1 0 N +P 2 0 1 0 220 -160 300 -160 N +P 2 0 1 0 300 -160 300 160 N +P 2 0 1 0 300 160 380 160 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 500 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# HIPASS_PSPICE +# +DEF HIPASS_PSPICE HIPASS 0 30 Y Y 1 F N +F0 "HIPASS" 0 0 30 H V L CNN +F1 "HIPASS_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 240 -40 60 1 1799 0 1 0 N 300 -40 180 -40 +A 240 60 60 1 1799 0 1 0 N 300 60 180 60 +A 350 -40 50 -1799 -1 0 1 0 N 300 -40 400 -40 +A 350 60 50 -1799 -1 0 1 0 N 300 60 400 60 +S 100 200 800 -200 0 1 0 N +P 2 0 1 0 180 -60 400 -20 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 900 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# HI_PSPICE +# +DEF HI_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "HI_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -300 -50 -200 -50 N +P 2 0 1 0 -300 50 -300 -50 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -300 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ HI 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# HPOLY_PSPICE +# +DEF HPOLY_PSPICE H 0 30 Y Y 1 F N +F0 "H" 0 0 30 H V L CNN +F1 "HPOLY_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 100 -100 140 -100 N +P 2 0 1 0 100 0 140 0 N +P 2 0 1 0 120 -50 140 -80 N +P 2 0 1 0 140 -80 160 -50 N +P 2 0 1 0 140 0 140 -100 N +P 2 0 1 0 250 -100 250 -90 N +P 2 0 1 0 250 0 250 -10 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# H_PSPICE +# +DEF H_PSPICE H 0 30 Y Y 1 F N +F0 "H" 0 0 30 H V L CNN +F1 "H_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 250 -50 40 0 1 0 N +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 100 -100 140 -100 N +P 2 0 1 0 100 0 140 0 N +P 2 0 1 0 120 -50 140 -80 N +P 2 0 1 0 140 -80 160 -50 N +P 2 0 1 0 140 0 140 -100 N +P 2 0 1 0 250 -100 250 -90 N +P 2 0 1 0 250 0 250 -10 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 400 0 100 L 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +X ~ 3 0 0 100 R 30 30 0 1 P +X ~ 4 0 -100 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IAC_PSPICE +# +DEF IAC_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IAC_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -30 -200 30 1 1799 0 1 0 N 0 -200 -60 -200 +A 30 -200 30 -1799 -1 0 1 0 N 0 -200 60 -200 +C 0 -200 100 0 1 0 N +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IC1_PSPICE +# +DEF IC1_PSPICE IC 0 30 Y Y 1 F N +F0 "IC" 0 0 30 H V L CNN +F1 "IC1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -100 200 100 100 0 1 0 N +X ~ + 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IC2_PSPICE +# +DEF IC2_PSPICE IC 0 30 Y Y 1 F N +F0 "IC" 0 0 30 H V L CNN +F1 "IC2_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 200 300 100 0 1 0 N +X ~ + 0 0 100 U 30 30 0 1 P +X ~ - 300 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IDC_PSPICE +# +DEF IDC_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IDC_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 0 -250 -50 -200 N +P 2 0 1 0 0 -250 50 -200 N +P 2 0 1 0 0 -150 0 -250 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IDEAL_TRAN_PSPICE +# +DEF IDEAL_TRAN_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "IDEAL_TRAN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 180 -500 180 -500 N +P 2 0 1 0 180 -100 180 -500 N +P 2 0 1 0 220 -500 220 -500 N +P 2 0 1 0 220 -100 220 -500 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IEXP_PSPICE +# +DEF IEXP_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IEXP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -10 -230 60 716 -1720 0 1 0 N 9 -173 -69 -238 +A 70 -170 60 -1799 -901 0 1 0 N 10 -170 70 -230 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IF_IN_PSPICE +# +DEF IF_IN_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "IF_IN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 0 -400 -50 N +P 2 0 1 0 -400 -50 -200 -50 N +P 2 0 1 0 -400 50 -500 0 N +P 2 0 1 0 -400 50 -200 50 N +P 2 0 1 0 -240 50 -140 0 N +P 2 0 1 0 -200 50 -100 0 N +P 2 0 1 0 -140 0 -240 -50 N +P 2 0 1 0 -100 0 -200 -50 N +X ~ 1 0 0 100 L 30 30 0 1 I +ENDDRAW +ENDDEF +# +# IF_OUT_PSPICE +# +DEF IF_OUT_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "IF_OUT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 -50 N +P 2 0 1 0 200 50 100 0 N +P 2 0 1 0 360 50 460 0 N +P 2 0 1 0 400 -50 200 -50 N +P 2 0 1 0 400 50 200 50 N +P 2 0 1 0 400 50 500 0 N +P 2 0 1 0 460 0 360 -50 N +P 2 0 1 0 500 0 400 -50 N +X ~ 1 0 0 100 R 30 30 0 1 O +ENDDRAW +ENDDEF +# +# IGBT_PSPICE +# +DEF IGBT_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "IGBT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 170 0 N +P 2 0 1 0 170 200 170 0 N +P 2 0 1 0 200 50 300 0 N +P 2 0 1 0 200 200 200 0 N +P 2 0 1 0 300 200 200 150 N +P 3 0 1 0 210 20 280 10 230 60 N +ENDDRAW +ENDDEF +# +# IMARKER_PSPICE +# +DEF IMARKER_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "IMARKER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +P 2 0 1 0 180 180 220 180 N +P 2 0 1 0 180 230 220 230 N +P 2 0 1 0 200 230 200 180 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# INCLUDE_PSPICE +# +DEF INCLUDE_PSPICE IN 0 30 Y Y 1 F N +F0 "IN" 0 0 30 H V L CNN +F1 "INCLUDE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +ENDDRAW +ENDDEF +# +# INTEG_PSPICE +# +DEF INTEG_PSPICE INTEG 0 30 Y Y 1 F N +F0 "INTEG" 0 0 30 H V L CNN +F1 "INTEG_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 160 -200 0 1 0 N +P 2 0 1 0 160 -200 400 0 N +P 2 0 1 0 160 200 400 0 N +X ~ in 0 0 100 R 30 30 0 1 P +X ~ out 500 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# INTERFACE_PSPICE +# +DEF INTERFACE_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "INTERFACE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 0 -400 -50 N +P 2 0 1 0 -400 -50 -200 -50 N +P 2 0 1 0 -400 50 -500 0 N +P 2 0 1 0 -400 50 -200 50 N +P 2 0 1 0 -200 50 -100 0 N +P 2 0 1 0 -100 0 -200 -50 N +X ~ 1 0 0 100 L 30 30 0 1 B +ENDDRAW +ENDDEF +# +# IPLOT_PSPICE +# +DEF IPLOT_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "IPLOT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 250 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 120 200 180 200 N +P 2 0 1 0 120 270 120 210 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 270 180 240 N +P 2 0 1 0 180 240 160 210 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +X ~ 2 200 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPRINT_PSPICE +# +DEF IPRINT_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "IPRINT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 250 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 120 200 180 200 N +P 2 0 1 0 120 200 180 200 N +P 2 0 1 0 120 220 180 220 N +P 2 0 1 0 120 240 180 240 N +P 2 0 1 0 120 260 180 260 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +X ~ 2 200 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPROBE_PSPICE +# +DEF IPROBE_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "IPROBE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -10 -190 80 141 1639 0 1 0 N 67 -170 -86 -167 +C 0 -200 100 0 1 0 N +P 2 0 1 0 0 -230 50 -150 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPULSE_PSPICE +# +DEF IPULSE_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPULSE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -250 N +P 2 0 1 0 -40 -250 -20 -180 N +P 2 0 1 0 -20 -180 20 -180 N +P 2 0 1 0 20 -180 40 -250 N +P 2 0 1 0 40 -250 70 -250 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_ENH_PSPICE +# +DEF IPWL_ENH_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_ENH_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_FILE_PSPICE +# +DEF IPWL_FILE_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_FILE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_F_RE_FOREVER_PSPICE +# +DEF IPWL_F_RE_FOREVER_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_F_RE_FOREVER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_F_RE_N_TIMES_PSPICE +# +DEF IPWL_F_RE_N_TIMES_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_F_RE_N_TIMES_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_PSPICE +# +DEF IPWL_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_RE_FOREVER_PSPICE +# +DEF IPWL_RE_FOREVER_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_RE_FOREVER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IPWL_RE_N_TIMES_PSPICE +# +DEF IPWL_RE_N_TIMES_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "IPWL_RE_N_TIMES_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IRF150_PSPICE +# +DEF IRF150_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "IRF150_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IRF9140_PSPICE +# +DEF IRF9140_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "IRF9140_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ISFFM_PSPICE +# +DEF ISFFM_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "ISFFM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -30 -200 30 1 1799 0 1 0 N 0 -200 -60 -200 +A 30 -200 30 -1799 -1 0 1 0 N 0 -200 60 -200 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ISIN_PSPICE +# +DEF ISIN_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "ISIN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -30 -200 30 1 1799 0 1 0 N 0 -200 -60 -200 +A 30 -200 30 -1799 -1 0 1 0 N 0 -200 60 -200 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ISRC_PSPICE +# +DEF ISRC_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "ISRC_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 0 -250 -50 -200 N +P 2 0 1 0 0 -250 50 -200 N +P 2 0 1 0 0 -150 0 -250 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ISTIM_PSPICE +# +DEF ISTIM_PSPICE I 0 30 Y Y 1 F N +F0 "I" 0 0 30 H V L CNN +F1 "ISTIM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 0 -250 -50 -200 N +P 2 0 1 0 0 -250 50 -200 N +P 2 0 1 0 0 -150 0 -250 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# IXGH40N60_PSPICE +# +DEF IXGH40N60_PSPICE Z 0 30 Y Y 1 F N +F0 "Z" 0 0 30 H V L CNN +F1 "IXGH40N60_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 170 0 N +P 2 0 1 0 170 200 170 0 N +P 2 0 1 0 200 50 300 0 N +P 2 0 1 0 200 200 200 0 N +P 2 0 1 0 300 200 200 150 N +P 3 0 1 0 210 20 280 10 230 60 N +X ~ C 300 300 100 D 30 30 0 1 P +X ~ E 300 -100 100 U 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# J2N3819_PSPICE +# +DEF J2N3819_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "J2N3819_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 3 0 1 0 110 20 170 0 110 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# J2N4393_PSPICE +# +DEF J2N4393_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "J2N4393_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 3 0 1 0 110 20 170 0 110 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# JFET_N_PSPICE +# +DEF JFET_N_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "JFET_N_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 3 0 1 0 110 20 170 0 110 -20 N +ENDDRAW +ENDDEF +# +# JFET_P_PSPICE +# +DEF JFET_P_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "JFET_P_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 3 0 1 0 170 -20 110 0 170 20 N +ENDDRAW +ENDDEF +# +# JbreakN_PSPICE +# +DEF JbreakN_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "JbreakN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 3 0 1 0 110 20 170 0 110 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# JbreakP_PSPICE +# +DEF JbreakP_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "JbreakP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 3 0 1 0 170 -20 110 0 170 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Jump1_PSPICE +# +DEF Jump1_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "Jump1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 160 -100 20 0 1 0 N +C 160 -100 40 0 1 0 N +P 2 0 1 0 140 -100 180 -100 N +P 2 0 1 0 160 -80 160 -120 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Jump2_PSPICE +# +DEF Jump2_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "Jump2_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 160 -200 20 0 1 0 N +C 160 -200 40 0 1 0 N +C 160 -100 20 0 1 0 N +C 160 -100 40 0 1 0 N +P 2 0 1 0 140 -200 180 -200 N +P 2 0 1 0 140 -100 180 -100 N +P 2 0 1 0 160 -180 160 -220 N +P 2 0 1 0 160 -80 160 -120 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +X ~ pin2 300 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# K3019PL_3C8_PSPICE +# +DEF K3019PL_3C8_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "K3019PL_3C8_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 180 -500 180 -500 N +P 2 0 1 0 180 -100 180 -500 N +P 2 0 1 0 220 -500 220 -500 N +P 2 0 1 0 220 -100 220 -500 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# K502T300_3C8_PSPICE +# +DEF K502T300_3C8_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "K502T300_3C8_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 180 -500 180 -500 N +P 2 0 1 0 180 -100 180 -500 N +P 2 0 1 0 220 -500 220 -500 N +P 2 0 1 0 220 -100 220 -500 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# K528T500_3C8_PSPICE +# +DEF K528T500_3C8_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "K528T500_3C8_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 180 -500 180 -500 N +P 2 0 1 0 180 -100 180 -500 N +P 2 0 1 0 220 -500 220 -500 N +P 2 0 1 0 220 -100 220 -500 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# KRM8PL_3C8_PSPICE +# +DEF KRM8PL_3C8_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "KRM8PL_3C8_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 180 -500 180 -500 N +P 2 0 1 0 180 -100 180 -500 N +P 2 0 1 0 220 -500 220 -500 N +P 2 0 1 0 220 -100 220 -500 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# K_Linear_PSPICE +# +DEF K_Linear_PSPICE K 0 30 Y Y 1 F N +F0 "K" 0 0 30 H V L CNN +F1 "K_Linear_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 100 100 0 0 1 0 N +ENDDRAW +ENDDEF +# +# LAPLACE_PSPICE +# +DEF LAPLACE_PSPICE LAPLACE 0 30 Y Y 1 F N +F0 "LAPLACE" 0 0 30 H V L CNN +F1 "LAPLACE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 500 -200 0 1 0 N +P 2 0 1 0 140 0 440 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# LF411_PSPICE +# +DEF LF411_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LF411_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 500 -300 600 -400 N +P 2 0 1 0 600 -400 700 -400 N +P 2 0 1 0 600 0 500 -100 N +P 2 0 1 0 600 0 700 0 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ V+ 400 100 100 D 30 30 0 1 W +X ~ V- 400 -500 100 U 30 30 0 1 W +X ~ B1 800 -400 100 L 30 30 0 1 I +X ~ B2 800 0 100 L 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# LIMIT_PSPICE +# +DEF LIMIT_PSPICE LIMIT 0 30 Y Y 1 F N +F0 "LIMIT" 0 0 30 H V L CNN +F1 "LIMIT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 200 400 -200 0 1 0 N +P 2 0 1 0 220 -160 300 -160 N +P 2 0 1 0 300 -160 300 160 N +P 2 0 1 0 300 160 380 160 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 500 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# LM111_PSPICE +# +DEF LM111_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM111_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 100 100 700 -200 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 500 0 500 -100 N +P 2 0 1 0 600 -400 500 -300 N +P 2 0 1 0 600 -100 560 -140 N +P 2 0 1 0 700 -400 600 -400 N +P 2 0 1 0 700 0 600 -100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ B 500 100 100 D 30 30 0 1 I +X ~ G 800 -400 100 L 30 30 0 1 P +X ~ V+ 400 100 100 D 30 30 0 1 W +X ~ V- 400 -500 100 U 30 30 0 1 W +X ~ B/S 800 0 100 L 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# LM324_PSPICE +# +DEF LM324_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM324_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ V+ 400 100 100 D 30 30 0 1 I +X ~ V- 400 -500 100 U 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# LM723C_PSPICE +# +DEF LM723C_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM723C_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -600 0 1 0 N +X ~ 2 0 0 100 R 30 30 0 1 B +X ~ 3 0 -100 100 R 30 30 0 1 B +X ~ 4 0 -200 100 R 30 30 0 1 B +X ~ 5 0 -300 100 R 30 30 0 1 B +X ~ 6 0 -400 100 R 30 30 0 1 B +X ~ 7 0 -500 100 R 30 30 0 1 B +X ~ 9 700 0 100 L 30 30 0 1 B +X ~ 10 700 -100 100 L 30 30 0 1 B +X ~ 11 700 -200 100 L 30 30 0 1 B +X ~ 12 700 -300 100 L 30 30 0 1 B +X ~ 13 700 -400 100 L 30 30 0 1 B +ENDDRAW +ENDDEF +# +# LM7805C_PSPICE +# +DEF LM7805C_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM7805C_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 1300 -200 0 1 0 N +X ~ OUTPUT 1400 0 100 L 30 30 0 1 B +X ~ GROUND 700 -300 100 U 30 30 0 1 B +X ~ INPUT 0 0 100 R 30 30 0 1 B +ENDDRAW +ENDDEF +# +# LM7815C_PSPICE +# +DEF LM7815C_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM7815C_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 1300 -200 0 1 0 N +X ~ OUTPUT 1400 0 100 L 30 30 0 1 B +X ~ GROUND 700 -300 100 U 30 30 0 1 B +X ~ INPUT 0 0 100 R 30 30 0 1 B +ENDDRAW +ENDDEF +# +# LM7905C_PSPICE +# +DEF LM7905C_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM7905C_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 1300 -200 0 1 0 N +X ~ OUTPUT 1400 0 100 L 30 30 0 1 B +X ~ GROUND 700 -300 100 U 30 30 0 1 B +X ~ INPUT 0 0 100 R 30 30 0 1 B +ENDDRAW +ENDDEF +# +# LM7915C_PSPICE +# +DEF LM7915C_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LM7915C_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 1300 -200 0 1 0 N +X ~ OUTPUT 1400 0 100 L 30 30 0 1 B +X ~ GROUND 700 -300 100 U 30 30 0 1 B +X ~ INPUT 0 0 100 R 30 30 0 1 B +ENDDRAW +ENDDEF +# +# LOG10_PSPICE +# +DEF LOG10_PSPICE LOG10 0 30 Y Y 1 F N +F0 "LOG10" 0 0 30 H V L CNN +F1 "LOG10_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# LOG_PSPICE +# +DEF LOG_PSPICE LOG 0 30 Y Y 1 F N +F0 "LOG" 0 0 30 H V L CNN +F1 "LOG_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# LOPASS_PSPICE +# +DEF LOPASS_PSPICE LOPASS 0 30 Y Y 1 F N +F0 "LOPASS" 0 0 30 H V L CNN +F1 "LOPASS_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 240 -40 60 1 1799 0 1 0 N 300 -40 180 -40 +A 240 60 60 1 1799 0 1 0 N 300 60 180 60 +A 350 -40 50 -1799 -1 0 1 0 N 300 -40 400 -40 +A 350 60 50 -1799 -1 0 1 0 N 300 60 400 60 +S 100 200 800 -200 0 1 0 N +P 2 0 1 0 180 40 400 80 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 900 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# LO_PSPICE +# +DEF LO_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "LO_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -300 -50 -200 -50 N +P 2 0 1 0 -300 50 -300 -50 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -300 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ LO 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# L_PSPICE +# +DEF L_PSPICE L 0 30 Y Y 1 F N +F0 "L" 0 0 30 H V L CNN +F1 "L_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 0 50 1 1799 0 1 0 N 200 0 100 0 +A 250 0 50 1 1799 0 1 0 N 300 0 200 0 +A 350 0 50 1 1799 0 1 0 N 400 0 300 0 +A 450 0 50 1 1799 0 1 0 N 500 0 400 0 +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Lbreak_PSPICE +# +DEF Lbreak_PSPICE L 0 30 Y Y 1 F N +F0 "L" 0 0 30 H V L CNN +F1 "Lbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 0 50 1 1799 0 1 0 N 200 0 100 0 +A 250 0 50 1 1799 0 1 0 N 300 0 200 0 +A 350 0 50 1 1799 0 1 0 N 400 0 300 0 +A 450 0 50 1 1799 0 1 0 N 500 0 400 0 +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MBD101_PSPICE +# +DEF MBD101_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "MBD101_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MULT_PSPICE +# +DEF MULT_PSPICE MULT 0 30 Y Y 1 F N +F0 "MULT" 0 0 30 H V L CNN +F1 "MULT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 100 0 100 0 1 0 N +P 2 0 1 0 0 0 -60 -20 N +P 2 0 1 0 0 0 -60 20 N +P 2 0 1 0 60 40 140 -40 N +P 2 0 1 0 100 100 80 160 N +P 2 0 1 0 100 100 120 160 N +P 2 0 1 0 140 40 60 -40 N +X ~ IN1 100 100 100 D 30 30 0 1 I +X ~ IN2 0 0 100 R 30 30 0 1 I +X ~ OUT 300 0 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# MV2201_PSPICE +# +DEF MV2201_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "MV2201_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 270 0 50 1269 -1270 0 1 0 N 240 40 239 -39 +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 100 50 100 -50 200 0 100 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakN3D_PSPICE +# +DEF MbreakN3D_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakN3D_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakN3_PSPICE +# +DEF MbreakN3_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakN3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakN4D_PSPICE +# +DEF MbreakN4D_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakN4D_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +X ~ b 400 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakN4_PSPICE +# +DEF MbreakN4_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakN4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +X ~ b 400 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakN_PSPICE +# +DEF MbreakN_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +X ~ b 400 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakP3D_PSPICE +# +DEF MbreakP3D_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakP3D_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakP3_PSPICE +# +DEF MbreakP3_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakP3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakP4D_PSPICE +# +DEF MbreakP4D_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakP4D_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 -130 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +X ~ b 400 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakP4_PSPICE +# +DEF MbreakP4_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakP4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +X ~ b 400 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# MbreakP_PSPICE +# +DEF MbreakP_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "MbreakP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +X ~ b 400 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# NIGBT_PSPICE +# +DEF NIGBT_PSPICE Z 0 30 Y Y 1 F N +F0 "Z" 0 0 30 H V L CNN +F1 "NIGBT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 170 0 N +P 2 0 1 0 170 200 170 0 N +P 2 0 1 0 200 50 300 0 N +P 2 0 1 0 200 200 200 0 N +P 2 0 1 0 300 200 200 150 N +P 3 0 1 0 210 20 280 10 230 60 N +X ~ C 300 300 100 D 30 30 0 1 P +X ~ E 300 -100 100 U 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# NODEMARKER_PSPICE +# +DEF NODEMARKER_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "NODEMARKER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# NODESET2_PSPICE +# +DEF NODESET2_PSPICE NS 0 30 Y Y 1 F N +F0 "NS" 0 0 30 H V L CNN +F1 "NODESET2_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -100 200 300 100 0 1 0 N +X ~ + 0 0 100 U 30 30 0 1 P +X ~ - 200 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# NoConnect_PSPICE +# +DEF NoConnect_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "NoConnect_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -50 50 50 -50 N +P 2 0 1 0 50 50 -50 -50 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# OFFPAGE_PSPICE +# +DEF OFFPAGE_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "OFFPAGE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 50 -100 -50 0 1 0 N +X ~ 1 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# OP-07_PSPICE +# +DEF OP-07_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "OP-07_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ V+ 400 100 100 D 30 30 0 1 I +X ~ V- 400 -500 100 U 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# OPAMP_PSPICE +# +DEF OPAMP_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "OPAMP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# OPTPARAM_PSPICE +# +DEF OPTPARAM_PSPICE PM 0 30 Y Y 1 F N +F0 "PM" 0 0 30 H V L CNN +F1 "OPTPARAM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -400 0 900 0 N +ENDDRAW +ENDDEF +# +# OP_AMP_PSPICE +# +DEF OP_AMP_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "OP_AMP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 1000 -400 0 1 0 N +X ~ OUT 1100 -100 100 L 30 30 0 1 B +X ~ INV 0 -300 100 R 30 30 0 1 B +X ~ NON_INV 0 0 100 R 30 30 0 1 B +ENDDRAW +ENDDEF +# +# PAL20RP4B_PSPICE +# +DEF PAL20RP4B_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "PAL20RP4B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -1400 0 1 0 N +X ~ pin1 0 0 100 R 30 30 0 1 I +X ~ pin2 0 -100 100 R 30 30 0 1 I +X ~ pin3 0 -200 100 R 30 30 0 1 I +X ~ pin4 0 -300 100 R 30 30 0 1 I +X ~ pin5 0 -400 100 R 30 30 0 1 I +X ~ pin6 0 -500 100 R 30 30 0 1 I +X ~ pin7 0 -600 100 R 30 30 0 1 I +X ~ pin8 0 -700 100 R 30 30 0 1 I +X ~ pin9 0 -800 100 R 30 30 0 1 I +X ~ pin10 0 -900 100 R 30 30 0 1 I +X ~ pin11 0 -1000 100 R 30 30 0 1 I +X ~ pin12 300 -1500 100 U 30 30 0 1 W +X ~ pin13 0 -1100 100 R 30 30 0 1 I +X ~ pin14 0 -1200 100 R 30 30 0 1 I +X ~ pin15 600 -1000 100 L 30 30 0 1 O +X ~ pin16 600 -900 100 L 30 30 0 1 O +X ~ pin17 600 -800 100 L 30 30 0 1 O +X ~ pin18 600 -700 100 L 30 30 0 1 O +X ~ pin19 600 -600 100 L 30 30 0 1 O +X ~ pin20 600 -500 100 L 30 30 0 1 O +X ~ pin21 600 -400 100 L 30 30 0 1 O +X ~ pin22 600 -300 100 L 30 30 0 1 O +X ~ pin23 0 -1300 100 R 30 30 0 1 I +X ~ pin24 300 200 100 D 30 30 0 1 W +ENDDRAW +ENDDEF +# +# POT_PSPICE +# +DEF POT_PSPICE R 0 30 Y Y 1 F N +F0 "R" 0 0 30 H V L CNN +F1 "POT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 110 0 N +P 2 0 1 0 110 0 130 40 N +P 2 0 1 0 130 40 160 -40 N +P 2 0 1 0 160 -40 190 40 N +P 2 0 1 0 190 -100 190 -100 N +P 2 0 1 0 190 -100 210 -100 N +P 2 0 1 0 190 40 220 -40 N +P 2 0 1 0 200 -100 200 -40 N +P 2 0 1 0 200 -40 190 -100 N +P 2 0 1 0 200 -40 200 -40 N +P 2 0 1 0 200 -40 200 -40 N +P 2 0 1 0 210 -100 200 -40 N +P 2 0 1 0 210 -100 210 -100 N +P 2 0 1 0 220 -40 250 40 N +P 2 0 1 0 250 40 280 -40 N +P 2 0 1 0 280 -40 300 0 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 400 0 100 L 30 30 0 1 P +X ~ t 200 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# PRINT1_PSPICE +# +DEF PRINT1_PSPICE PRINT 0 30 Y Y 1 F N +F0 "PRINT" 0 0 30 H V L CNN +F1 "PRINT1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 130 150 10 0 1 0 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 20 200 80 200 N +P 2 0 1 0 20 220 80 220 N +P 2 0 1 0 20 240 80 240 N +P 2 0 1 0 20 260 80 260 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 200 100 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# PRINTDGTLCHG_PSPICE +# +DEF PRINTDGTLCHG_PSPICE PRINT 0 30 Y Y 1 F N +F0 "PRINT" 0 0 30 H V L CNN +F1 "PRINTDGTLCHG_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 130 150 10 0 1 0 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 20 200 80 200 N +P 2 0 1 0 20 220 80 220 N +P 2 0 1 0 20 240 80 240 N +P 2 0 1 0 20 260 80 260 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 200 100 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# PWRS_PSPICE +# +DEF PWRS_PSPICE PWRS 0 30 Y Y 1 F N +F0 "PWRS" 0 0 30 H V L CNN +F1 "PWRS_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# PWR_PSPICE +# +DEF PWR_PSPICE PWR 0 30 Y Y 1 F N +F0 "PWR" 0 0 30 H V L CNN +F1 "PWR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q2N2222_PSPICE +# +DEF Q2N2222_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q2N2222_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 200 100 D 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q2N2907A_PSPICE +# +DEF Q2N2907A_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q2N2907A_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q2N3904_PSPICE +# +DEF Q2N3904_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q2N3904_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q2N3906_PSPICE +# +DEF Q2N3906_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q2N3906_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q2N6052_PSPICE +# +DEF Q2N6052_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q2N6052_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 100 50 N +P 2 0 1 0 200 100 400 100 N +P 2 0 1 0 300 -150 400 -200 N +P 2 0 1 0 300 0 300 -200 N +P 2 0 1 0 400 0 300 -50 N +P 2 0 1 0 400 100 400 0 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +P 3 0 1 0 390 -170 320 -160 370 -210 N +X ~ 1 400 -300 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 400 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q2N6059_PSPICE +# +DEF Q2N6059_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q2N6059_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 100 50 N +P 2 0 1 0 200 100 400 100 N +P 2 0 1 0 300 0 300 -200 N +P 2 0 1 0 400 -200 300 -150 N +P 2 0 1 0 400 0 300 -50 N +P 2 0 1 0 400 100 400 0 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +P 3 0 1 0 310 -180 380 -190 330 -140 N +X ~ 1 400 -300 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 400 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QDarBreakN_PSPICE +# +DEF QDarBreakN_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "QDarBreakN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 100 50 N +P 2 0 1 0 300 0 300 -200 N +P 2 0 1 0 400 -200 300 -150 N +P 2 0 1 0 400 0 300 -50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +P 3 0 1 0 200 100 400 100 400 0 N +P 3 0 1 0 310 -180 380 -190 330 -140 N +X ~ b 0 0 100 R 30 30 0 1 P +X ~ c 400 200 100 D 30 30 0 1 P +X ~ e 400 -300 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QDarBreakP_PSPICE +# +DEF QDarBreakP_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "QDarBreakP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 100 100 50 N +P 2 0 1 0 300 -150 400 -200 N +P 2 0 1 0 300 0 300 -200 N +P 2 0 1 0 400 0 300 -50 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +P 3 0 1 0 200 100 400 100 400 0 N +P 3 0 1 0 390 -170 320 -160 370 -210 N +X ~ b 0 0 100 R 30 30 0 1 P +X ~ c 400 200 100 D 30 30 0 1 P +X ~ e 400 -300 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QM_PSPICE +# +DEF QM_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QN_PSPICE +# +DEF QN_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Q_PI_PSPICE +# +DEF Q_PI_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "Q_PI_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakL_PSPICE +# +DEF QbreakL_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakL_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 70 -70 130 -70 N +P 2 0 1 0 100 -200 100 -120 N +P 2 0 1 0 100 -70 100 0 N +P 2 0 1 0 100 0 200 0 N +P 2 0 1 0 200 -50 300 -100 N +P 2 0 1 0 200 100 200 -100 N +P 2 0 1 0 300 -100 300 -200 N +P 2 0 1 0 300 100 200 50 N +P 3 0 1 0 290 -70 220 -60 270 -110 N +P 4 0 1 0 100 -70 70 -120 130 -120 100 -70 N +X ~ 1 300 -300 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 300 200 100 D 30 30 0 1 P +X ~ s 100 -300 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakN3_PSPICE +# +DEF QbreakN3_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakN3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakN4_PSPICE +# +DEF QbreakN4_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakN4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 270 30 330 30 N +P 2 0 1 0 300 -100 300 -20 N +P 2 0 1 0 300 30 300 100 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +P 4 0 1 0 300 30 270 -20 330 -20 300 30 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +X ~ s 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakN_PSPICE +# +DEF QbreakN_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakP3_PSPICE +# +DEF QbreakP3_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakP3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakP4_PSPICE +# +DEF QbreakP4_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakP4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 100 100 50 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 300 -30 300 -100 N +P 2 0 1 0 300 100 300 20 N +P 2 0 1 0 330 -30 270 -30 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +P 4 0 1 0 300 -30 330 20 270 20 300 -30 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +X ~ s 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# QbreakP_PSPICE +# +DEF QbreakP_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "QbreakP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +X ~ 1 200 -200 100 U 30 30 0 1 P +X ~ 2 0 0 100 R 30 30 0 1 P +X ~ 3 200 200 100 D 30 30 0 1 P +ENDDRAW +ENDDEF +# +# RAM8Kx1break_PSPICE +# +DEF RAM8Kx1break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "RAM8Kx1break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -2100 0 1 0 N +X ~ A0 0 0 100 R 30 30 0 1 I +X ~ A1 0 -100 100 R 30 30 0 1 I +X ~ A2 0 -200 100 R 30 30 0 1 I +X ~ A3 0 -300 100 R 30 30 0 1 I +X ~ A4 0 -400 100 R 30 30 0 1 I +X ~ A5 0 -500 100 R 30 30 0 1 I +X ~ A6 0 -600 100 R 30 30 0 1 I +X ~ A7 0 -700 100 R 30 30 0 1 I +X ~ A8 0 -800 100 R 30 30 0 1 I +X ~ A9 0 -900 100 R 30 30 0 1 I +X ~ RE 0 -1900 100 R 30 30 0 1 I +X ~ WE 0 -2000 100 R 30 30 0 1 I +X ~ A10 0 -1000 100 R 30 30 0 1 I +X ~ A11 0 -1100 100 R 30 30 0 1 I +X ~ A12 0 -1200 100 R 30 30 0 1 I +X ~ A13 0 -1300 100 R 30 30 0 1 P +X ~ A14 0 -1400 100 R 30 30 0 1 P +X ~ A15 0 -1500 100 R 30 30 0 1 P +X ~ VCC 400 200 100 D 30 30 0 1 W +X ~ GND 300 -2200 100 U 30 30 0 1 W +X ~ D_IN 0 -1700 100 R 30 30 0 1 P +X ~ D_OUT 700 -900 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# RAM8Kx8break_PSPICE +# +DEF RAM8Kx8break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "RAM8Kx8break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1700 0 1 0 N +X ~ A0 0 0 100 R 30 30 0 1 I +X ~ R0 700 -700 100 L 30 30 0 1 B +X ~ W0 700 -1600 100 L 30 30 0 1 P +X ~ A1 0 -100 100 R 30 30 0 1 I +X ~ R1 700 -600 100 L 30 30 0 1 B +X ~ W1 700 -1500 100 L 30 30 0 1 P +X ~ A2 0 -200 100 R 30 30 0 1 I +X ~ R2 700 -500 100 L 30 30 0 1 B +X ~ W2 700 -1400 100 L 30 30 0 1 P +X ~ A3 0 -300 100 R 30 30 0 1 I +X ~ R3 700 -400 100 L 30 30 0 1 B +X ~ W3 700 -1300 100 L 30 30 0 1 P +X ~ A4 0 -400 100 R 30 30 0 1 I +X ~ R4 700 -300 100 L 30 30 0 1 B +X ~ W4 700 -1200 100 L 30 30 0 1 P +X ~ A5 0 -500 100 R 30 30 0 1 I +X ~ R5 700 -200 100 L 30 30 0 1 B +X ~ W5 700 -1100 100 L 30 30 0 1 P +X ~ A6 0 -600 100 R 30 30 0 1 I +X ~ R6 700 -100 100 L 30 30 0 1 B +X ~ W6 700 -1000 100 L 30 30 0 1 P +X ~ A7 0 -700 100 R 30 30 0 1 I +X ~ R7 700 0 100 L 30 30 0 1 B +X ~ W7 700 -900 100 L 30 30 0 1 P +X ~ A8 0 -800 100 R 30 30 0 1 I +X ~ A9 0 -900 100 R 30 30 0 1 I +X ~ RE 0 -1500 100 R 30 30 0 1 I +X ~ WE 0 -1600 100 R 30 30 0 1 I +X ~ A10 0 -1000 100 R 30 30 0 1 I +X ~ A11 0 -1100 100 R 30 30 0 1 I +X ~ A12 0 -1200 100 R 30 30 0 1 I +X ~ VCC 400 200 100 D 30 30 0 1 W +X ~ GND 300 -1800 100 U 30 30 0 1 W +ENDDRAW +ENDDEF +# +# ROM32KX8break_PSPICE +# +DEF ROM32KX8break_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "ROM32KX8break_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -1800 0 1 0 N +X ~ A0 0 0 100 R 30 30 0 1 I +X ~ O0 700 -400 100 L 30 30 0 1 O +X ~ A1 0 -100 100 R 30 30 0 1 I +X ~ O1 700 -500 100 L 30 30 0 1 O +X ~ A2 0 -200 100 R 30 30 0 1 I +X ~ O2 700 -600 100 L 30 30 0 1 O +X ~ A3 0 -300 100 R 30 30 0 1 I +X ~ O3 700 -700 100 L 30 30 0 1 O +X ~ A4 0 -400 100 R 30 30 0 1 I +X ~ O4 700 -800 100 L 30 30 0 1 O +X ~ A5 0 -500 100 R 30 30 0 1 I +X ~ O5 700 -900 100 L 30 30 0 1 O +X ~ A6 0 -600 100 R 30 30 0 1 I +X ~ O6 700 -1000 100 L 30 30 0 1 O +X ~ A7 0 -700 100 R 30 30 0 1 I +X ~ O7 700 -1100 100 L 30 30 0 1 O +X ~ A8 0 -800 100 R 30 30 0 1 I +X ~ A9 0 -900 100 R 30 30 0 1 I +X ~ A10 0 -1000 100 R 30 30 0 1 I +X ~ A11 0 -1100 100 R 30 30 0 1 I +X ~ A12 0 -1200 100 R 30 30 0 1 I +X ~ A13 0 -1300 100 R 30 30 0 1 I +X ~ A14 0 -1400 100 R 30 30 0 1 I +X ~ VCC 400 200 100 D 30 30 0 1 W +X ~ GND 400 -1900 100 U 30 30 0 1 W +X ~ \OE\ 0 -1600 100 R 30 30 0 1 I +ENDDRAW +ENDDEF +# +# R_PSPICE +# +DEF R_PSPICE R 0 30 Y Y 1 F N +F0 "R" 0 0 30 H V L CNN +F1 "R_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 110 0 N +P 2 0 1 0 110 0 130 40 N +P 2 0 1 0 130 40 160 -40 N +P 2 0 1 0 160 -40 190 40 N +P 2 0 1 0 190 40 220 -40 N +P 2 0 1 0 220 -40 250 40 N +P 2 0 1 0 250 40 280 -40 N +P 2 0 1 0 280 -40 300 0 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# R_var_PSPICE +# +DEF R_var_PSPICE R 0 30 Y Y 1 F N +F0 "R" 0 0 30 H V L CNN +F1 "R_var_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -100 300 100 N +P 2 0 1 0 100 0 110 0 N +P 2 0 1 0 110 0 130 40 N +P 2 0 1 0 130 40 160 -40 N +P 2 0 1 0 160 -40 190 40 N +P 2 0 1 0 190 40 220 -40 N +P 2 0 1 0 220 -40 250 40 N +P 2 0 1 0 250 40 280 -40 N +P 2 0 1 0 250 100 300 100 N +P 2 0 1 0 280 -40 300 0 N +P 2 0 1 0 300 100 300 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Rbreak_PSPICE +# +DEF Rbreak_PSPICE R 0 30 Y Y 1 F N +F0 "R" 0 0 30 H V L CNN +F1 "Rbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 110 0 N +P 2 0 1 0 110 0 130 40 N +P 2 0 1 0 130 40 160 -40 N +P 2 0 1 0 160 -40 190 40 N +P 2 0 1 0 190 40 220 -40 N +P 2 0 1 0 220 -40 250 40 N +P 2 0 1 0 250 40 280 -40 N +P 2 0 1 0 280 -40 300 0 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# SCR2T_PSPICE +# +DEF SCR2T_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "SCR2T_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -100 0 1 0 N +X ~ A 0 0 100 R 30 30 0 1 B +X ~ K 700 0 100 L 30 30 0 1 B +ENDDRAW +ENDDEF +# +# SCR3T_PSPICE +# +DEF SCR3T_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "SCR3T_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 200 50 200 -50 N +P 2 0 1 0 300 -100 200 0 N +P 2 0 1 0 300 0 200 0 N +P 4 0 1 0 100 50 100 -50 200 0 100 50 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ G 300 -200 100 U 30 30 0 1 P +X ~ K 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# SCR_PSPICE +# +DEF SCR_PSPICE X 0 30 Y Y 1 F N +F0 "X" 0 0 30 H V L CNN +F1 "SCR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 200 50 200 -50 N +P 2 0 1 0 300 -100 200 0 N +P 2 0 1 0 300 0 200 0 N +P 4 0 1 0 100 50 100 -50 200 0 100 50 N +X ~ A 0 0 100 R 30 30 0 1 P +X ~ G 300 -200 100 U 30 30 0 1 P +X ~ K 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# SG1524B_PSPICE +# +DEF SG1524B_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "SG1524B_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -800 0 1 0 N +X ~ 1 0 0 100 R 30 30 0 1 B +X ~ 2 0 -100 100 R 30 30 0 1 B +X ~ 3 0 -200 100 R 30 30 0 1 B +X ~ 4 0 -300 100 R 30 30 0 1 B +X ~ 5 0 -400 100 R 30 30 0 1 B +X ~ 7 0 -500 100 R 30 30 0 1 B +X ~ 8 0 -600 100 R 30 30 0 1 B +X ~ 9 0 -700 100 R 30 30 0 1 B +X ~ 10 700 0 100 L 30 30 0 1 B +X ~ 11 700 -100 100 L 30 30 0 1 B +X ~ 12 700 -200 100 L 30 30 0 1 B +X ~ 13 700 -300 100 L 30 30 0 1 B +X ~ 14 700 -400 100 L 30 30 0 1 B +X ~ 15 700 -500 100 L 30 30 0 1 B +X ~ 16 700 -600 100 L 30 30 0 1 B +ENDDRAW +ENDDEF +# +# SIN_PSPICE +# +DEF SIN_PSPICE SIN 0 30 Y Y 1 F N +F0 "SIN" 0 0 30 H V L CNN +F1 "SIN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# SOFTLIM_PSPICE +# +DEF SOFTLIM_PSPICE SLIMIT 0 30 Y Y 1 F N +F0 "SLIMIT" 0 0 30 H V L CNN +F1 "SOFTLIM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 270 200 0 -199 499 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +A 330 200 0 1 -537 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +S 100 200 400 -200 0 1 0 N +P 2 0 1 0 200 -160 260 -160 N +P 2 0 1 0 300 120 300 -120 N +P 2 0 1 0 340 160 380 160 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 500 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# SQRT_PSPICE +# +DEF SQRT_PSPICE SQRT 0 30 Y Y 1 F N +F0 "SQRT" 0 0 30 H V L CNN +F1 "SQRT_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# STIM16_PSPICE +# +DEF STIM16_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "STIM16_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -450 -20 -400 -20 N +P 2 0 1 0 -400 -20 -400 20 N +P 2 0 1 0 -400 20 -350 20 N +P 2 0 1 0 -350 -20 -300 -20 N +P 2 0 1 0 -350 20 -350 -20 N +P 2 0 1 0 -300 -20 -300 20 N +P 2 0 1 0 -300 20 -250 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ pin[0-15] 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# STIM1_PSPICE +# +DEF STIM1_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "STIM1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -450 -20 -400 -20 N +P 2 0 1 0 -400 -20 -400 20 N +P 2 0 1 0 -400 20 -350 20 N +P 2 0 1 0 -350 -20 -300 -20 N +P 2 0 1 0 -350 20 -350 -20 N +P 2 0 1 0 -300 -20 -300 20 N +P 2 0 1 0 -300 20 -250 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ pin1 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# STIM4_PSPICE +# +DEF STIM4_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "STIM4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -450 -20 -400 -20 N +P 2 0 1 0 -400 -20 -400 20 N +P 2 0 1 0 -400 20 -350 20 N +P 2 0 1 0 -350 -20 -300 -20 N +P 2 0 1 0 -350 20 -350 -20 N +P 2 0 1 0 -300 -20 -300 20 N +P 2 0 1 0 -300 20 -250 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ pin[0-3] 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# STIM8_PSPICE +# +DEF STIM8_PSPICE DSTM 0 30 Y Y 1 F N +F0 "DSTM" 0 0 30 H V L CNN +F1 "STIM8_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -500 -50 -200 -50 N +P 2 0 1 0 -500 50 -500 -50 N +P 2 0 1 0 -450 -20 -400 -20 N +P 2 0 1 0 -400 -20 -400 20 N +P 2 0 1 0 -400 20 -350 20 N +P 2 0 1 0 -350 -20 -300 -20 N +P 2 0 1 0 -350 20 -350 -20 N +P 2 0 1 0 -300 -20 -300 20 N +P 2 0 1 0 -300 20 -250 20 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -500 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ pin[0-7] 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# SUM_PSPICE +# +DEF SUM_PSPICE SUM 0 30 Y Y 1 F N +F0 "SUM" 0 0 30 H V L CNN +F1 "SUM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 100 0 100 0 1 0 N +P 2 0 1 0 0 0 -60 -20 N +P 2 0 1 0 0 0 -60 20 N +P 2 0 1 0 40 0 160 0 N +P 2 0 1 0 100 60 100 -60 N +P 2 0 1 0 100 100 80 160 N +P 2 0 1 0 100 100 120 160 N +X ~ IN1 100 100 100 D 30 30 0 1 I +X ~ IN2 0 0 100 R 30 30 0 1 I +X ~ OUT 300 0 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# S_PSPICE +# +DEF S_PSPICE S 0 30 Y Y 1 F N +F0 "S" 0 0 30 H V L CNN +F1 "S_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 120 -20 30 0 0 0 + Normal 0 C C +T 0 240 0 30 0 0 0 + Normal 0 C C +T 0 120 -120 30 0 0 0 - Normal 0 C C +T 0 240 -140 30 0 0 0 - Normal 0 C C +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 250 -100 200 -20 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -100 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Sbreak_PSPICE +# +DEF Sbreak_PSPICE S 0 30 Y Y 1 F N +F0 "S" 0 0 30 H V L CNN +F1 "Sbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 120 -20 30 0 0 0 + Normal 0 C C +T 0 240 0 30 0 0 0 + Normal 0 C C +T 0 120 -120 30 0 0 0 - Normal 0 C C +T 0 240 -140 30 0 0 0 - Normal 0 C C +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 250 -100 200 -20 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -100 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Sw_tClose_PSPICE +# +DEF Sw_tClose_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "Sw_tClose_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 160 0 0 1 -1465 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +P 2 0 1 0 100 -100 300 0 N +P 2 0 1 0 250 -140 230 -110 N +P 2 0 1 0 250 -140 280 -120 N +X ~ 1 0 -100 100 R 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Sw_tOpen_PSPICE +# +DEF Sw_tOpen_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "Sw_tOpen_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 160 0 0 1 -1481 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +P 2 0 1 0 100 -100 300 0 N +P 2 0 1 0 170 0 190 -30 N +P 2 0 1 0 170 0 200 20 N +X ~ 1 0 -100 100 R 30 30 0 1 P +X ~ 2 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# T2coupled_PSPICE +# +DEF T2coupled_PSPICE T 0 30 Y Y 1 F N +F0 "T" 0 0 30 H V L CNN +F1 "T2coupled_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -200 0 1 0 N +X ~ in1 0 0 100 R 30 30 0 1 P +X ~ in2 0 -100 100 R 30 30 0 1 P +X ~ out1 700 0 100 L 30 30 0 1 P +X ~ out2 700 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# T3coupled_PSPICE +# +DEF T3coupled_PSPICE T 0 30 Y Y 1 F N +F0 "T" 0 0 30 H V L CNN +F1 "T3coupled_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 600 -300 0 1 0 N +X ~ in1 0 0 100 R 30 30 0 1 P +X ~ in2 0 -100 100 R 30 30 0 1 P +X ~ in3 0 -200 100 R 30 30 0 1 P +X ~ out1 700 0 100 L 30 30 0 1 P +X ~ out2 700 -100 100 L 30 30 0 1 P +X ~ out3 700 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# TABLE_PSPICE +# +DEF TABLE_PSPICE TABLE 0 30 Y Y 1 F N +F0 "TABLE" 0 0 30 H V L CNN +F1 "TABLE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +P 2 0 1 0 100 -200 500 -200 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# TAN_PSPICE +# +DEF TAN_PSPICE TAN 0 30 Y Y 1 F N +F0 "TAN" 0 0 30 H V L CNN +F1 "TAN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 100 100 500 -100 0 1 0 N +X ~ IN 0 0 100 R 30 30 0 1 P +X ~ OUT 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# TBCONT-A/B/C/G_PSPICE +# +DEF TBCONT-A/B/C/G_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "TBCONT-A/B/C/G_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -4250 0 0 0 N +P 2 0 1 0 -4250 250 0 250 N +P 2 0 1 0 -4250 620 -4250 0 N +P 2 0 1 0 -4250 620 0 620 N +P 2 0 1 0 -3870 620 -3870 250 N +P 2 0 1 0 -3250 250 -3250 0 N +P 2 0 1 0 -2750 620 -2750 250 N +P 2 0 1 0 -1750 250 -1750 0 N +P 2 0 1 0 -380 310 -380 260 N +P 2 0 1 0 -380 400 -380 350 N +P 2 0 1 0 -380 490 -380 440 N +P 2 0 1 0 -380 580 -380 530 N +P 2 0 1 0 0 0 0 620 N +ENDDRAW +ENDDEF +# +# TBCONT-D/E/F/H/J/K_PSPICE +# +DEF TBCONT-D/E/F/H/J/K_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "TBCONT-D/E/F/H/J/K_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -5120 0 -20 0 N +P 2 0 1 0 -5120 250 0 250 N +P 2 0 1 0 -5120 750 -5120 0 N +P 2 0 1 0 -5120 750 0 750 N +P 2 0 1 0 -4750 750 -4750 250 N +P 2 0 1 0 -3750 250 -3750 0 N +P 2 0 1 0 -3500 750 -3500 250 N +P 2 0 1 0 -1750 250 -1750 0 N +P 2 0 1 0 -500 370 -500 320 N +P 2 0 1 0 -500 460 -500 410 N +P 2 0 1 0 -500 550 -500 500 N +P 2 0 1 0 -500 640 -500 590 N +P 2 0 1 0 -500 730 -500 680 N +P 2 0 1 0 -450 280 -450 250 N +P 2 0 1 0 -30 0 0 0 N +P 2 0 1 0 0 0 0 750 N +ENDDRAW +ENDDEF +# +# TBLK-A/B/C/G_PSPICE +# +DEF TBLK-A/B/C/G_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "TBLK-A/B/C/G_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -6250 2000 0 0 0 1 0 N +P 2 0 1 0 -6180 250 -6230 250 N +P 2 0 1 0 -6180 500 -6230 500 N +P 2 0 1 0 -6090 250 -6140 250 N +P 2 0 1 0 -6090 500 -6140 500 N +P 2 0 1 0 -6000 250 -6050 250 N +P 2 0 1 0 -6000 500 -6050 500 N +P 2 0 1 0 -5910 250 -5960 250 N +P 2 0 1 0 -5910 500 -5960 500 N +P 2 0 1 0 -5820 250 -5870 250 N +P 2 0 1 0 -5820 500 -5870 500 N +P 2 0 1 0 -5730 250 -5780 250 N +P 2 0 1 0 -5730 500 -5780 500 N +P 2 0 1 0 -5640 250 -5690 250 N +P 2 0 1 0 -5640 500 -5690 500 N +P 2 0 1 0 -5550 250 -5600 250 N +P 2 0 1 0 -5550 500 -5600 500 N +P 2 0 1 0 -5460 250 -5510 250 N +P 2 0 1 0 -5460 500 -5510 500 N +P 2 0 1 0 -5370 250 -5420 250 N +P 2 0 1 0 -5370 500 -5420 500 N +P 2 0 1 0 -5280 250 -5330 250 N +P 2 0 1 0 -5280 500 -5330 500 N +P 2 0 1 0 -5190 250 -5240 250 N +P 2 0 1 0 -5190 500 -5240 500 N +P 2 0 1 0 -5100 250 -5150 250 N +P 2 0 1 0 -5100 500 -5150 500 N +P 2 0 1 0 -5010 250 -5060 250 N +P 2 0 1 0 -5010 500 -5060 500 N +P 2 0 1 0 -4920 250 -4970 250 N +P 2 0 1 0 -4920 500 -4970 500 N +P 2 0 1 0 -4830 250 -4880 250 N +P 2 0 1 0 -4830 500 -4880 500 N +P 2 0 1 0 -4740 250 -4790 250 N +P 2 0 1 0 -4740 500 -4790 500 N +P 2 0 1 0 -4650 250 -4700 250 N +P 2 0 1 0 -4650 500 -4700 500 N +P 2 0 1 0 -4560 250 -4610 250 N +P 2 0 1 0 -4560 500 -4610 500 N +P 2 0 1 0 -4470 250 -4520 250 N +P 2 0 1 0 -4470 500 -4520 500 N +P 2 0 1 0 -4380 250 -4430 250 N +P 2 0 1 0 -4380 500 -4430 500 N +P 2 0 1 0 -4290 250 -4340 250 N +P 2 0 1 0 -4290 500 -4340 500 N +P 2 0 1 0 -4250 250 0 250 N +P 2 0 1 0 -4250 620 0 620 N +P 2 0 1 0 -4250 1380 0 1380 N +P 2 0 1 0 -4250 2000 -4250 0 N +P 2 0 1 0 -3870 620 -3870 250 N +P 2 0 1 0 -3250 250 -3250 0 N +P 2 0 1 0 -2750 620 -2750 250 N +P 2 0 1 0 -1750 250 -1750 0 N +P 2 0 1 0 -380 310 -380 260 N +P 2 0 1 0 -380 400 -380 350 N +P 2 0 1 0 -380 490 -380 440 N +P 2 0 1 0 -380 580 -380 530 N +ENDDRAW +ENDDEF +# +# TBLK-D/E/F/H/J/K_PSPICE +# +DEF TBLK-D/E/F/H/J/K_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "TBLK-D/E/F/H/J/K_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -7620 2500 0 0 0 1 0 N +P 2 0 1 0 -7560 250 -7610 250 N +P 2 0 1 0 -7560 500 -7610 500 N +P 2 0 1 0 -7470 250 -7520 250 N +P 2 0 1 0 -7470 500 -7520 500 N +P 2 0 1 0 -7380 250 -7430 250 N +P 2 0 1 0 -7380 500 -7430 500 N +P 2 0 1 0 -7290 250 -7340 250 N +P 2 0 1 0 -7290 500 -7340 500 N +P 2 0 1 0 -7200 250 -7250 250 N +P 2 0 1 0 -7200 500 -7250 500 N +P 2 0 1 0 -7110 250 -7160 250 N +P 2 0 1 0 -7110 500 -7160 500 N +P 2 0 1 0 -7020 250 -7070 250 N +P 2 0 1 0 -7020 500 -7070 500 N +P 2 0 1 0 -6930 250 -6980 250 N +P 2 0 1 0 -6930 500 -6980 500 N +P 2 0 1 0 -6840 250 -6890 250 N +P 2 0 1 0 -6840 500 -6890 500 N +P 2 0 1 0 -6750 250 -6800 250 N +P 2 0 1 0 -6750 500 -6800 500 N +P 2 0 1 0 -6660 250 -6710 250 N +P 2 0 1 0 -6660 500 -6710 500 N +P 2 0 1 0 -6570 250 -6620 250 N +P 2 0 1 0 -6570 500 -6620 500 N +P 2 0 1 0 -6480 250 -6530 250 N +P 2 0 1 0 -6480 500 -6530 500 N +P 2 0 1 0 -6390 250 -6440 250 N +P 2 0 1 0 -6390 500 -6440 500 N +P 2 0 1 0 -6300 250 -6350 250 N +P 2 0 1 0 -6300 500 -6350 500 N +P 2 0 1 0 -6210 250 -6260 250 N +P 2 0 1 0 -6210 500 -6260 500 N +P 2 0 1 0 -6120 250 -6170 250 N +P 2 0 1 0 -6120 500 -6170 500 N +P 2 0 1 0 -6030 250 -6080 250 N +P 2 0 1 0 -6030 500 -6080 500 N +P 2 0 1 0 -5940 250 -5990 250 N +P 2 0 1 0 -5940 500 -5990 500 N +P 2 0 1 0 -5850 250 -5900 250 N +P 2 0 1 0 -5850 500 -5900 500 N +P 2 0 1 0 -5760 250 -5810 250 N +P 2 0 1 0 -5760 500 -5810 500 N +P 2 0 1 0 -5670 250 -5720 250 N +P 2 0 1 0 -5670 500 -5720 500 N +P 2 0 1 0 -5580 250 -5630 250 N +P 2 0 1 0 -5580 500 -5630 500 N +P 2 0 1 0 -5490 250 -5540 250 N +P 2 0 1 0 -5490 500 -5540 500 N +P 2 0 1 0 -5400 250 -5450 250 N +P 2 0 1 0 -5400 500 -5450 500 N +P 2 0 1 0 -5310 250 -5360 250 N +P 2 0 1 0 -5310 500 -5360 500 N +P 2 0 1 0 -5220 250 -5270 250 N +P 2 0 1 0 -5220 500 -5270 500 N +P 2 0 1 0 -5130 250 -5180 250 N +P 2 0 1 0 -5130 500 -5180 500 N +P 2 0 1 0 -5120 250 0 250 N +P 2 0 1 0 -5120 750 0 750 N +P 2 0 1 0 -5120 1880 0 1880 N +P 2 0 1 0 -5120 2500 -5120 0 N +P 2 0 1 0 -4750 750 -4750 250 N +P 2 0 1 0 -3750 250 -3750 0 N +P 2 0 1 0 -3500 750 -3500 250 N +P 2 0 1 0 -1750 250 -1750 0 N +P 2 0 1 0 -500 280 -500 250 N +P 2 0 1 0 -500 370 -500 320 N +P 2 0 1 0 -500 460 -500 410 N +P 2 0 1 0 -500 550 -500 500 N +P 2 0 1 0 -500 640 -500 590 N +P 2 0 1 0 -500 730 -500 680 N +ENDDRAW +ENDDEF +# +# TLOSSY_PSPICE +# +DEF TLOSSY_PSPICE T 0 30 Y Y 1 F N +F0 "T" 0 0 30 H V L CNN +F1 "TLOSSY_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 390 200 0 1318 -1516 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +A 490 200 0 1319 -1517 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +A 610 60 120 1317 -1515 0 1 0 N 530 149 504 2 +A 710 60 120 1317 -1515 0 1 0 N 630 149 604 2 +A 800 0 100 -899 899 0 1 0 N 800 -100 800 100 +C 200 0 100 0 1 0 N +P 2 0 1 0 200 -200 100 -200 N +P 2 0 1 0 200 -100 200 -200 N +P 2 0 1 0 200 -100 500 -100 N +P 2 0 1 0 200 0 100 0 N +P 2 0 1 0 200 100 500 100 N +P 2 0 1 0 600 -100 800 -100 N +P 2 0 1 0 600 100 800 100 N +P 2 0 1 0 800 -200 900 -200 N +P 2 0 1 0 800 -100 800 -200 N +X ~ A+ 0 0 100 R 30 30 0 1 P +X ~ B+ 1000 0 100 L 30 30 0 1 P +X ~ A- 0 -200 100 R 30 30 0 1 P +X ~ B- 1000 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# T_PSPICE +# +DEF T_PSPICE T 0 30 Y Y 1 F N +F0 "T" 0 0 30 H V L CNN +F1 "T_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 390 200 0 1318 -1516 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +A 490 200 0 1319 -1517 0 1 0 N -2147483648 -2147483648 -2147483648 -2147483648 +A 610 60 120 1317 -1515 0 1 0 N 530 149 504 2 +A 710 60 120 1317 -1515 0 1 0 N 630 149 604 2 +A 800 0 100 -899 899 0 1 0 N 800 -100 800 100 +C 200 0 100 0 1 0 N +P 2 0 1 0 200 -200 100 -200 N +P 2 0 1 0 200 -100 200 -200 N +P 2 0 1 0 200 -100 500 -100 N +P 2 0 1 0 200 0 100 0 N +P 2 0 1 0 200 100 500 100 N +P 2 0 1 0 600 -100 800 -100 N +P 2 0 1 0 600 100 800 100 N +P 2 0 1 0 800 -200 900 -200 N +P 2 0 1 0 800 -100 800 -200 N +X ~ A+ 0 0 100 R 30 30 0 1 P +X ~ B+ 1000 0 100 L 30 30 0 1 P +X ~ A- 0 -200 100 R 30 30 0 1 P +X ~ B- 1000 -200 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# UNKNOWN_PSPICE +# +DEF UNKNOWN_PSPICE *? 0 30 Y Y 1 F N +F0 "*?" 0 0 30 H V L CNN +F1 "UNKNOWN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 200 -150 50 1 1799 0 1 0 N 250 -150 150 -150 +A 200 -150 50 -899 899 0 1 0 N 200 -200 200 -100 +C 200 -350 20 0 1 0 N +S 0 0 400 -400 0 1 0 N +P 2 0 1 0 200 -200 200 -300 N +ENDDRAW +ENDDEF +# +# VAC_PSPICE +# +DEF VAC_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VAC_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -30 -200 30 1 1799 0 1 0 N 0 -200 -60 -200 +A 30 -200 30 -1799 -1 0 1 0 N 0 -200 60 -200 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VDC_PSPICE +# +DEF VDC_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VDC_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -100 -140 100 -140 N +P 2 0 1 0 -50 -240 50 -240 N +P 2 0 1 0 -50 -170 50 -170 N +P 2 0 1 0 0 -300 0 -240 N +P 2 0 1 0 0 -90 0 -140 N +P 2 0 1 0 100 -200 -100 -200 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VDIFFMARKER_PSPICE +# +DEF VDIFFMARKER_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "VDIFFMARKER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VEXP_PSPICE +# +DEF VEXP_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VEXP_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -10 -230 60 716 -1720 0 1 0 N 9 -173 -69 -238 +A 70 -170 60 -1799 -901 0 1 0 N 10 -170 70 -230 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPLOT1_PSPICE +# +DEF VPLOT1_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "VPLOT1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 130 150 10 0 1 0 N +C 130 150 10 0 1 0 N +C 130 150 10 0 1 0 N +C 130 150 10 0 1 0 N +C 130 150 10 0 1 0 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -50 200 150 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 20 200 80 200 N +P 2 0 1 0 20 270 20 210 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 70 270 80 240 N +P 2 0 1 0 80 240 60 210 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 200 100 150 N +P 2 0 1 0 150 200 100 150 N +P 2 0 1 0 150 200 100 150 N +P 2 0 1 0 150 200 100 150 N +P 2 0 1 0 150 200 100 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPLOT2_PSPICE +# +DEF VPLOT2_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "VPLOT2_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +C 230 150 10 0 1 0 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 50 200 250 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 120 200 180 200 N +P 2 0 1 0 120 270 120 210 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 170 270 180 240 N +P 2 0 1 0 180 240 160 210 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +P 2 0 1 0 250 200 200 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +X ~ 2 200 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPRINT1_PSPICE +# +DEF VPRINT1_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "VPRINT1_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 130 150 10 0 1 0 N +P 2 0 1 0 -100 100 100 100 N +P 2 0 1 0 -100 150 -100 100 N +P 2 0 1 0 -100 150 -50 200 N +P 2 0 1 0 -50 200 0 200 N +P 2 0 1 0 -30 170 0 200 N +P 2 0 1 0 0 200 0 280 N +P 2 0 1 0 0 280 100 280 N +P 2 0 1 0 20 200 80 200 N +P 2 0 1 0 20 220 80 220 N +P 2 0 1 0 20 240 80 240 N +P 2 0 1 0 20 260 80 260 N +P 2 0 1 0 50 130 80 130 N +P 2 0 1 0 70 170 -30 170 N +P 2 0 1 0 100 100 150 150 N +P 2 0 1 0 100 150 -100 150 N +P 2 0 1 0 100 150 100 100 N +P 2 0 1 0 100 200 70 170 N +P 2 0 1 0 100 200 150 200 N +P 2 0 1 0 100 280 100 200 N +P 2 0 1 0 150 150 150 200 N +P 2 0 1 0 150 200 100 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPRINT2_PSPICE +# +DEF VPRINT2_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "VPRINT2_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 230 150 10 0 1 0 N +P 2 0 1 0 0 100 200 100 N +P 2 0 1 0 0 150 0 100 N +P 2 0 1 0 0 150 50 200 N +P 2 0 1 0 50 200 100 200 N +P 2 0 1 0 70 170 100 200 N +P 2 0 1 0 100 200 100 280 N +P 2 0 1 0 100 280 200 280 N +P 2 0 1 0 120 200 180 200 N +P 2 0 1 0 120 220 180 220 N +P 2 0 1 0 120 240 180 240 N +P 2 0 1 0 120 260 180 260 N +P 2 0 1 0 150 130 180 130 N +P 2 0 1 0 170 170 70 170 N +P 2 0 1 0 200 100 250 150 N +P 2 0 1 0 200 150 0 150 N +P 2 0 1 0 200 150 200 100 N +P 2 0 1 0 200 200 170 170 N +P 2 0 1 0 200 200 250 200 N +P 2 0 1 0 200 280 200 200 N +P 2 0 1 0 250 150 250 200 N +P 2 0 1 0 250 200 200 150 N +X ~ 1 0 0 100 U 30 30 0 1 P +X ~ 2 200 0 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPULSE_PSPICE +# +DEF VPULSE_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPULSE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -250 N +P 2 0 1 0 -40 -250 -20 -180 N +P 2 0 1 0 -20 -180 20 -180 N +P 2 0 1 0 20 -180 40 -250 N +P 2 0 1 0 40 -250 70 -250 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_ENH_PSPICE +# +DEF VPWL_ENH_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_ENH_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_FILE_PSPICE +# +DEF VPWL_FILE_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_FILE_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_F_RE_FOREVER_PSPICE +# +DEF VPWL_F_RE_FOREVER_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_F_RE_FOREVER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_F_RE_N_TIMES_PSPICE +# +DEF VPWL_F_RE_N_TIMES_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_F_RE_N_TIMES_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_PSPICE +# +DEF VPWL_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_RE_FOREVER_PSPICE +# +DEF VPWL_RE_FOREVER_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_RE_FOREVER_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VPWL_RE_N_TIMES_PSPICE +# +DEF VPWL_RE_N_TIMES_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VPWL_RE_N_TIMES_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +P 2 0 1 0 -70 -250 -40 -150 N +P 2 0 1 0 -40 -150 -10 -210 N +P 2 0 1 0 -10 -210 30 -210 N +P 2 0 1 0 30 -210 60 -130 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VSFFM_PSPICE +# +DEF VSFFM_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VSFFM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -30 -200 30 1 1799 0 1 0 N 0 -200 -60 -200 +A 30 -200 30 -1799 -1 0 1 0 N 0 -200 60 -200 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VSIN_PSPICE +# +DEF VSIN_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VSIN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -30 -200 30 1 1799 0 1 0 N 0 -200 -60 -200 +A 30 -200 30 -1799 -1 0 1 0 N 0 -200 60 -200 +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VSRC_PSPICE +# +DEF VSRC_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VSRC_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# VSTIM_PSPICE +# +DEF VSTIM_PSPICE V 0 30 Y Y 1 F N +F0 "V" 0 0 30 H V L CNN +F1 "VSTIM_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 0 -200 100 0 1 0 N +X ~ + 0 0 100 D 30 30 0 1 P +X ~ - 0 -400 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# W_PSPICE +# +DEF W_PSPICE W 0 30 Y Y 1 F N +F0 "W" 0 0 30 H V L CNN +F1 "W_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 240 0 30 0 0 0 + Normal 0 C C +T 0 240 -140 30 0 0 0 - Normal 0 C C +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 100 -100 140 -100 N +P 2 0 1 0 100 0 140 0 N +P 2 0 1 0 140 0 140 -100 N +P 2 0 1 0 250 -100 200 -20 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +P 3 0 1 0 120 -30 140 -80 160 -30 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -100 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# Wbreak_PSPICE +# +DEF Wbreak_PSPICE W 0 30 Y Y 1 F N +F0 "W" 0 0 30 H V L CNN +F1 "Wbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +T 0 240 0 30 0 0 0 + Normal 0 C C +T 0 240 -140 30 0 0 0 - Normal 0 C C +S 100 50 300 -150 0 1 0 N +P 2 0 1 0 100 -100 140 -100 N +P 2 0 1 0 100 0 140 0 N +P 2 0 1 0 140 0 140 -100 N +P 2 0 1 0 250 -100 200 -20 N +P 2 0 1 0 250 0 300 0 N +P 2 0 1 0 300 -100 250 -100 N +P 3 0 1 0 120 -30 140 -80 160 -30 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -100 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# XFRM_LINEAR_PSPICE +# +DEF XFRM_LINEAR_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "XFRM_LINEAR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# XFRM_NONLINEAR_PSPICE +# +DEF XFRM_NONLINEAR_PSPICE TX 0 30 Y Y 1 F N +F0 "TX" 0 0 30 H V L CNN +F1 "XFRM_NONLINEAR_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 100 -450 50 -899 899 0 1 0 N 100 -500 100 -400 +A 100 -350 50 -899 899 0 1 0 N 100 -400 100 -300 +A 100 -250 50 -899 899 0 1 0 N 100 -300 100 -200 +A 100 -150 50 -899 899 0 1 0 N 100 -200 100 -100 +A 300 -450 50 901 -901 0 1 0 N 300 -400 300 -500 +A 300 -350 50 901 -901 0 1 0 N 300 -300 300 -400 +A 300 -250 50 901 -901 0 1 0 N 300 -200 300 -300 +A 300 -150 50 901 -901 0 1 0 N 300 -100 300 -200 +P 2 0 1 0 100 -500 100 -600 N +P 2 0 1 0 100 0 100 -100 N +P 2 0 1 0 180 -500 180 -500 N +P 2 0 1 0 180 -100 180 -500 N +P 2 0 1 0 220 -500 220 -500 N +P 2 0 1 0 220 -100 220 -500 N +P 2 0 1 0 300 -500 300 -600 N +P 2 0 1 0 300 0 300 -100 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 0 -600 100 R 30 30 0 1 P +X ~ 3 400 0 100 L 30 30 0 1 P +X ~ 4 400 -600 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# X_PSPICE +# +DEF X_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "X_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -300 -50 -200 -50 N +P 2 0 1 0 -300 50 -300 -50 N +P 2 0 1 0 -200 -50 -100 0 N +P 2 0 1 0 -200 50 -300 50 N +P 2 0 1 0 -100 0 -200 50 N +X ~ X 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ZbreakN_PSPICE +# +DEF ZbreakN_PSPICE Z 0 30 Y Y 1 F N +F0 "Z" 0 0 30 H V L CNN +F1 "ZbreakN_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 170 0 N +P 2 0 1 0 170 200 170 0 N +P 2 0 1 0 200 50 300 0 N +P 2 0 1 0 200 200 200 0 N +P 2 0 1 0 300 200 200 150 N +P 3 0 1 0 210 20 280 10 230 60 N +X ~ C 300 300 100 D 30 30 0 1 P +X ~ E 300 -100 100 U 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# c_PSPICE +# +DEF c_PSPICE C 0 30 Y Y 1 F N +F0 "C" 0 0 30 H V L CNN +F1 "c_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 130 0 N +P 2 0 1 0 130 50 130 -50 N +P 2 0 1 0 170 0 200 0 N +P 2 0 1 0 170 50 170 -50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# d_PSPICE +# +DEF d_PSPICE D 0 30 Y Y 1 F N +F0 "D" 0 0 30 H V L CNN +F1 "d_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 300 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# diode_PSPICE +# +DEF diode_PSPICE ~ 0 30 Y Y 1 F N +F0 "" 0 0 30 H V L CNN +F1 "diode_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +ENDDRAW +ENDDEF +# +# edge26_PSPICE +# +DEF edge26_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "edge26_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 50 -150 100 -100 N +P 2 0 1 0 50 -50 100 -100 N +P 2 0 1 0 100 -100 200 -100 N +X ~ pin1 300 -100 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# idb_PSPICE +# +DEF idb_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "idb_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# igroupdelay_PSPICE +# +DEF igroupdelay_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "igroupdelay_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# iimaginary_PSPICE +# +DEF iimaginary_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "iimaginary_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# iphase_PSPICE +# +DEF iphase_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "iphase_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# ireal_PSPICE +# +DEF ireal_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "ireal_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# kbreak_PSPICE +# +DEF kbreak_PSPICE K 0 30 Y Y 1 F N +F0 "K" 0 0 30 H V L CNN +F1 "kbreak_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 0 100 100 0 0 1 0 N +ENDDRAW +ENDDEF +# +# l_PSPICE +# +DEF l_PSPICE L 0 30 Y Y 1 F N +F0 "L" 0 0 30 H V L CNN +F1 "l_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 0 50 1 1799 0 1 0 N 200 0 100 0 +A 250 0 50 1 1799 0 1 0 N 300 0 200 0 +A 350 0 50 1 1799 0 1 0 N 400 0 300 0 +A 450 0 50 1 1799 0 1 0 N 500 0 400 0 +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 600 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# male_PSPICE +# +DEF male_PSPICE P 0 30 Y Y 1 F N +F0 "P" 0 0 30 H V L CNN +F1 "male_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 -200 0 -100 0 N +P 2 0 1 0 -150 -50 -200 0 N +P 2 0 1 0 -150 50 -200 0 N +X ~ pin1 0 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# mosfet_n_3_PSPICE +# +DEF mosfet_n_3_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "mosfet_n_3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +ENDDRAW +ENDDEF +# +# mosfet_n_4_PSPICE +# +DEF mosfet_n_4_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "mosfet_n_4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +ENDDRAW +ENDDEF +# +# mosfet_p_3_PSPICE +# +DEF mosfet_p_3_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "mosfet_p_3_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +ENDDRAW +ENDDEF +# +# mosfet_p_4_PSPICE +# +DEF mosfet_p_4_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "mosfet_p_4_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 400 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 400 0 400 -100 N +P 3 0 1 0 230 20 290 0 230 -20 N +ENDDRAW +ENDDEF +# +# nmose_PSPICE +# +DEF nmose_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "nmose_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 150 0 N +P 2 0 1 0 150 100 150 -100 N +P 2 0 1 0 200 -100 300 -100 N +P 2 0 1 0 200 -70 200 -130 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 30 200 -30 N +P 2 0 1 0 200 100 300 100 N +P 2 0 1 0 200 130 200 70 N +P 2 0 1 0 300 0 300 -100 N +P 3 0 1 0 290 -20 230 0 290 20 N +X ~ D 300 200 100 D 30 30 0 1 P +X ~ G 0 0 100 R 30 30 0 1 P +X ~ S 300 -200 100 U 30 30 0 1 P +ENDDRAW +ENDDEF +# +# npn_PSPICE +# +DEF npn_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "npn_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 -100 100 -50 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 110 -80 180 -90 130 -40 N +ENDDRAW +ENDDEF +# +# opamp5_PSPICE +# +DEF opamp5_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "opamp5_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 4 0 1 0 100 100 700 -200 100 -500 100 100 N +ENDDRAW +ENDDEF +# +# opamp6_PSPICE +# +DEF opamp6_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "opamp6_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 600 -400 500 -300 N +P 2 0 1 0 700 -400 600 -400 N +P 4 0 1 0 100 100 700 -200 100 -500 100 100 N +ENDDRAW +ENDDEF +# +# opamp7_PSPICE +# +DEF opamp7_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "opamp7_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 500 -300 600 -400 N +P 2 0 1 0 600 -400 700 -400 N +P 2 0 1 0 600 0 500 -100 N +P 2 0 1 0 600 0 700 0 N +P 4 0 1 0 100 100 700 -200 100 -500 100 100 N +ENDDRAW +ENDDEF +# +# pnp_PSPICE +# +DEF pnp_PSPICE Q 0 30 Y Y 1 F N +F0 "Q" 0 0 30 H V L CNN +F1 "pnp_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -50 200 -100 N +P 2 0 1 0 100 100 100 -100 N +P 2 0 1 0 200 100 100 50 N +P 3 0 1 0 190 -70 120 -60 170 -110 N +ENDDRAW +ENDDEF +# +# r_PSPICE +# +DEF r_PSPICE R 0 30 Y Y 1 F N +F0 "R" 0 0 30 H V L CNN +F1 "r_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 110 0 N +P 2 0 1 0 110 0 130 40 N +P 2 0 1 0 130 40 160 -40 N +P 2 0 1 0 160 -40 190 40 N +P 2 0 1 0 190 40 220 -40 N +P 2 0 1 0 220 -40 250 40 N +P 2 0 1 0 250 40 280 -40 N +P 2 0 1 0 280 -40 300 0 N +X ~ 1 0 0 100 R 30 30 0 1 P +X ~ 2 400 0 100 L 30 30 0 1 P +ENDDRAW +ENDDEF +# +# uA741_PSPICE +# +DEF uA741_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "uA741_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 -500 700 -200 N +P 2 0 1 0 100 100 100 -500 N +P 2 0 1 0 400 -400 400 -350 N +P 2 0 1 0 400 0 400 -50 N +P 2 0 1 0 500 -300 600 -400 N +P 2 0 1 0 600 -400 700 -400 N +P 2 0 1 0 600 0 500 -100 N +P 2 0 1 0 600 0 700 0 N +P 2 0 1 0 700 -200 100 100 N +X ~ + 0 0 100 R 30 30 0 1 I +X ~ - 0 -400 100 R 30 30 0 1 I +X ~ V+ 400 100 100 D 30 30 0 1 W +X ~ V- 400 -500 100 U 30 30 0 1 W +X ~ OS1 800 -400 100 L 30 30 0 1 I +X ~ OS2 800 0 100 L 30 30 0 1 I +X ~ OUT 800 -200 100 L 30 30 0 1 O +ENDDRAW +ENDDEF +# +# vdb_PSPICE +# +DEF vdb_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "vdb_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# vgroupdelay_PSPICE +# +DEF vgroupdelay_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "vgroupdelay_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# vimaginary_PSPICE +# +DEF vimaginary_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "vimaginary_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# vphase_PSPICE +# +DEF vphase_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "vphase_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# vreal_PSPICE +# +DEF vreal_PSPICE U 0 30 Y Y 1 F N +F0 "U" 0 0 30 H V L CNN +F1 "vreal_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 200 200 50 0 1 0 N +P 2 0 1 0 0 0 40 80 N +P 2 0 1 0 40 80 80 40 N +P 2 0 1 0 60 60 170 170 N +P 2 0 1 0 80 40 0 0 N +X ~ pin1 0 0 100 R 30 30 0 1 P +ENDDRAW +ENDDEF +# +# zener_diode_PSPICE +# +DEF zener_diode_PSPICE ~ 0 30 Y Y 1 F N +F0 "" 0 0 30 H V L CNN +F1 "zener_diode_PSPICE" 0 60 30 H V L CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 2 0 1 0 100 0 120 0 N +P 2 0 1 0 170 70 200 50 N +P 2 0 1 0 200 -50 230 -70 N +P 2 0 1 0 200 50 200 -50 N +P 4 0 1 0 120 50 120 -50 200 0 120 50 N +ENDDRAW +ENDDEF +# +#End Library + diff --git a/kicadSchematicLibrary/eSim_Plot.dcm b/kicadSchematicLibrary/eSim_Plot.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Plot.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Plot.lib b/kicadSchematicLibrary/eSim_Plot.lib new file mode 100644 index 00000000..5654a3d2 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Plot.lib @@ -0,0 +1,84 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# plot_db +# +DEF plot_db U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_db" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# plot_i2 +# +DEF plot_i2 U 0 40 Y Y 1 F N +F0 "U" 0 400 60 H V C CNN +F1 "plot_i2" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 250 100 0 1 0 N +X + 1 -300 250 200 R 50 50 1 1 I +X - 2 300 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# plot_log +# +DEF plot_log U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_log" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# plot_phase +# +DEF plot_phase U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_phase" 250 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# plot_v2 +# +DEF plot_v2 U 0 40 Y Y 1 F N +F0 "U" 0 400 60 H V C CNN +F1 "plot_v2" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 250 100 0 1 0 N +X + 1 -300 250 200 R 50 50 1 1 I +X - 2 300 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Power.dcm b/kicadSchematicLibrary/eSim_Power.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Power.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Power.lib b/kicadSchematicLibrary/eSim_Power.lib new file mode 100644 index 00000000..9e9dbcc8 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Power.lib @@ -0,0 +1,84 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DIAC +# +DEF DIAC X 0 10 Y Y 1 F N +F0 "X" -200 250 50 H V C CNN +F1 "DIAC" -250 -200 50 H V C CNN +F2 "" 0 -50 60 H V C CNN +F3 "" 0 -50 60 H V C CNN +DRAW +P 2 0 1 0 -300 -100 0 -100 N +P 2 0 1 0 0 150 300 150 N +P 3 0 1 0 -300 150 -150 -100 0 150 F +P 3 0 1 0 150 150 0 -100 300 -100 F +X ~ 1 0 -300 200 U 70 70 1 1 P +X ~ 2 0 350 200 D 70 70 1 1 P +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X K 1 0 -550 400 U 60 70 1 1 I +X G 2 -350 -400 150 R 60 60 1 1 I +X A 3 0 400 300 D 60 60 1 1 I +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# eSim_VCC +# +DEF eSim_VCC #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "eSim_VCC" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VCC 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# TRIAC +# +DEF TRIAC X 0 10 Y Y 1 F N +F0 "X" -250 250 50 H V C CNN +F1 "TRIAC" -300 -300 50 H V C CNN +F2 "" 0 -50 60 H V C CNN +F3 "" 0 -50 60 H V C CNN +DRAW +P 2 0 1 0 -300 -100 0 -100 N +P 2 0 1 0 -150 -100 -300 -250 N +P 2 0 1 0 0 150 300 150 N +P 3 0 1 0 -300 150 -150 -100 0 150 F +P 3 0 1 0 150 150 0 -100 300 -100 F +X ~ 1 0 -300 200 U 70 70 1 1 P +X ~ 2 0 350 200 D 70 70 1 1 P +X ~ 3 -500 -250 200 R 70 70 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Sources.dcm b/kicadSchematicLibrary/eSim_Sources.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_Sources.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Sources.lib b/kicadSchematicLibrary/eSim_Sources.lib new file mode 100644 index 00000000..c1c62410 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Sources.lib @@ -0,0 +1,220 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# AC +# +DEF AC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "AC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" 0 150 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# VCCS +# +DEF VCCS G 0 40 Y Y 1 F N +F0 "G" 0 150 50 H V C CNN +F1 "VCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# exp +# +DEF exp v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "exp" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A 1 -50 100 905 1800 0 1 0 N 0 50 -100 -50 +A 100 51 100 -1794 -900 0 1 0 N 0 50 100 -50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# pwl +# +DEF pwl v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pwl" -250 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -1144 -561 1253 291 240 0 1 0 N -50 50 0 -50 +A -765 421 941 -300 -232 0 1 0 N 50 -50 100 50 +A -75 -700 750 919 880 0 1 0 N -100 50 -50 50 +A 25 450 501 -928 -871 0 1 0 N 0 -50 50 -50 +A 1096 -609 1366 1511 1558 0 1 0 N -100 50 -150 -50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +# sine +# +DEF sine v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "sine" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 0 1 1 I +X - 2 0 -450 300 U 50 0 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Subckt.bak b/kicadSchematicLibrary/eSim_Subckt.bak new file mode 100644 index 00000000..797e6e7e --- /dev/null +++ b/kicadSchematicLibrary/eSim_Subckt.bak @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# Half_Adder +# +DEF Half_Adder X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Half_Adder" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -650 200 600 -300 0 1 0 N +X A 1 -850 150 200 R 50 50 1 1 I +X B 2 -850 -200 200 R 50 50 1 1 I +X Sum 3 800 100 200 L 50 50 1 1 O +X carry 4 800 -200 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UA741 +# +DEF UA741 X 0 40 Y Y 1 F N +F0 "X" 150 0 60 H V C CNN +F1 "UA741" 250 -150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 0 150 0 -150 350 0 0 150 N +X + 1 -200 100 200 R 50 50 1 1 I +X - 2 -200 -100 200 R 50 50 1 1 I +X ~ 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_Subckt.bck b/kicadSchematicLibrary/eSim_Subckt.bck new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Subckt.bck @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Subckt.dcm b/kicadSchematicLibrary/eSim_Subckt.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/kicadSchematicLibrary/eSim_Subckt.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_Subckt.lib b/kicadSchematicLibrary/eSim_Subckt.lib new file mode 100644 index 00000000..3a2abd7a --- /dev/null +++ b/kicadSchematicLibrary/eSim_Subckt.lib @@ -0,0 +1,595 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UA741 +# +DEF UA741 X 0 40 Y Y 1 F N +F0 "X" 150 0 60 H V C CNN +F1 "UA741" 250 -150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 0 150 0 -150 350 0 0 150 N +X + 1 -200 100 200 R 50 50 1 1 I +X - 2 -200 -100 200 R 50 50 1 1 I +X ~ 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 x 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicadSchematicLibrary/eSim_User.dcm b/kicadSchematicLibrary/eSim_User.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/kicadSchematicLibrary/eSim_User.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/kicadSchematicLibrary/eSim_User.lib b/kicadSchematicLibrary/eSim_User.lib new file mode 100644 index 00000000..2063b3ae --- /dev/null +++ b/kicadSchematicLibrary/eSim_User.lib @@ -0,0 +1,4 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +#End Library diff --git a/kicadSchematicLibrary/kicad.pro b/kicadSchematicLibrary/kicad.pro new file mode 100644 index 00000000..148e9ed5 --- /dev/null +++ b/kicadSchematicLibrary/kicad.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice + diff --git a/nghdl/.gitignore b/nghdl/.gitignore new file mode 100644 index 00000000..0d20b648 --- /dev/null +++ b/nghdl/.gitignore @@ -0,0 +1 @@ +*.pyc diff --git a/nghdl/Example/2-bit-inverter/2-bit-inverter.cir b/nghdl/Example/2-bit-inverter/2-bit-inverter.cir new file mode 100644 index 00000000..88580dd3 --- /dev/null +++ b/nghdl/Example/2-bit-inverter/2-bit-inverter.cir @@ -0,0 +1,36 @@ +* analysis type * +.tran 1n 100n +* +* input sources * +v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 2.0 20n 0 20.1n 2.0 25n 2.0 25.1n 2.0 30n 2.0 30.1n 2.0 + + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0) + +v2 200 0 DC PWL ( 0n 2.0 5n 2.0 5.1n 0.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 0.0 20n 0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 2.0 30.1n 2.0 + + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0) + +* resistors to ground * +r1 100 0 1k +r2 200 0 1k + +rload1 300 0 10k +rload2 400 0 10k +* +* adc_bridge blocks * +aconverter1 [100 200] [1 2] adc_bridge1 + +.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7 ++ rise_delay =1.0e-12 fall_delay =1.0e-12) + +ainverter [1 2] [10 20] inv1 + +.model inv1 inverter(instance_id = 101 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time=90e-9) + + +aconverter2 [10 20] [30 40] dac_bridge1 + +.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 ++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) + +.end + + diff --git a/nghdl/Example/2-bit-inverter/inverter.vhdl b/nghdl/Example/2-bit-inverter/inverter.vhdl new file mode 100644 index 00000000..7eb3c678 --- /dev/null +++ b/nghdl/Example/2-bit-inverter/inverter.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity inverter is + port ( i: in std_logic_vector(0 downto 0); + o: out std_logic_vector(0 downto 0)); +end inverter; + +architecture inverter_beh of inverter is +begin + o <= not i; +end inverter_beh; + + diff --git a/nghdl/Example/bin_to_gray/bin_to_gray.vhdl b/nghdl/Example/bin_to_gray/bin_to_gray.vhdl new file mode 100644 index 00000000..542f7ec9 --- /dev/null +++ b/nghdl/Example/bin_to_gray/bin_to_gray.vhdl @@ -0,0 +1,21 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +entity bin_to_gray is +port( + bin : in std_logic_vector(3 downto 0); -- binary input + G : out std_logic_vector(3 downto 0) -- gray code output + ); +end bin_to_gray; + + +architecture gate_level of bin_to_gray is + +begin + +G(3) <= bin(3); +G(2) <= bin(3) xor bin(2); +G(1) <= bin(2) xor bin(1); +G(0) <= bin(1) xor bin(0); + +end gate_level;
\ No newline at end of file diff --git a/nghdl/Example/counter/counter.o b/nghdl/Example/counter/counter.o Binary files differnew file mode 100644 index 00000000..442cc730 --- /dev/null +++ b/nghdl/Example/counter/counter.o diff --git a/nghdl/Example/counter/counter.vhdl b/nghdl/Example/counter/counter.vhdl new file mode 100644 index 00000000..6e16138c --- /dev/null +++ b/nghdl/Example/counter/counter.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity counter is +port(C : in std_logic; + CLR : in std_logic; + Q : out std_logic_vector(3 downto 0)); +end counter; +architecture bhv of counter is +signal tmp: std_logic_vector(3 downto 0); +begin +process (C, CLR) +begin +if (CLR='1') then +tmp <= "0000"; +elsif (C'event and C='1') then +tmp <= std_logic_vector(to_unsigned(1+to_integer(unsigned(tmp)), tmp'length)); +end if; +end process; +Q <= tmp; +end bhv;
\ No newline at end of file diff --git a/nghdl/Example/counter/work-obj93.cf b/nghdl/Example/counter/work-obj93.cf new file mode 100644 index 00000000..46d4772c --- /dev/null +++ b/nghdl/Example/counter/work-obj93.cf @@ -0,0 +1,4 @@ +v 4 +file . "counter.vhdl" "849ecbdf1a2a5f5cd553b9ca6594e4a3ae1e214a" "20190710170933.911": + entity counter at 1( 0) + 0 on 13; + architecture bhv of counter at 11( 229) + 0 on 14; diff --git a/nghdl/Example/decoder/decoder.vhdl b/nghdl/Example/decoder/decoder.vhdl new file mode 100644 index 00000000..e429ec93 --- /dev/null +++ b/nghdl/Example/decoder/decoder.vhdl @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity decoder is +port ( + p : in std_logic_vector(4 downto 0); + d : out std_logic_vector(31 downto 0) + ); +end decoder; + +architecture behav of decoder is + +begin + +with p select +d<="00000000000000000000000000000001" when "00000", +"00000000000000000000000000000010" when "00001", +"00000000000000000000000000000100" when "00010", +"00000000000000000000000000001000" when "00011", +"00000000000000000000000000010000" when "00100", +"00000000000000000000000000100000" when "00101", +"00000000000000000000000001000000" when "00110", +"00000000000000000000000010000000" when "00111", +"00000000000000000000000100000000" when "01000", +"00000000000000000000001000000000" when "01001", +"00000000000000000000010000000000" when "01010", +"00000000000000000000100000000000" when "01011", +"00000000000000000001000000000000" when "01100", +"00000000000000000010000000000000" when "01101", +"00000000000000000100000000000000" when "01110", +"00000000000000001000000000000000" when "01111", +"00000000000000010000000000000000" when "10000", +"00000000000000100000000000000000" when "10001", +"00000000000001000000000000000000" when "10010", +"00000000000010000000000000000000" when "10011", +"00000000000100000000000000000000" when "10100", +"00000000001000000000000000000000" when "10101", +"00000000010000000000000000000000" when "10110", +"00000000100000000000000000000000" when "10111", +"00000001000000000000000000000000" when "11000", +"00000010000000000000000000000000" when "11001", +"00000100000000000000000000000000" when "11010", +"00001000000000000000000000000000" when "11011", +"00010000000000000000000000000000" when "11100", +"00100000000000000000000000000000" when "11101", +"01000000000000000000000000000000" when "11110", +"10000000000000000000000000000000" when "11111", +"00000000000000000000000000000000" when others; + +end behav; diff --git a/nghdl/Example/esim_trial_xor/esim_trial_xor.vhdl b/nghdl/Example/esim_trial_xor/esim_trial_xor.vhdl new file mode 100644 index 00000000..ff9190cc --- /dev/null +++ b/nghdl/Example/esim_trial_xor/esim_trial_xor.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity esim_trial_xor is + port (a : in std_logic_vector(0 downto 0); + b : in std_logic_vector(0 downto 0); + c : out std_logic_vector(0 downto 0)); + end esim_trial_xor; + + architecture rtl of esim_trial_xor is + begin + + c <= a xor b; + + end rtl; diff --git a/nghdl/Example/fa_SL/full_adder_sl.vhdl b/nghdl/Example/fa_SL/full_adder_sl.vhdl new file mode 100644 index 00000000..e8305633 --- /dev/null +++ b/nghdl/Example/fa_SL/full_adder_sl.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_sl is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + i_bit3 : in std_logic; + o_sum : out std_logic; + o_carry : out std_logic + ); +end full_adder_sl; + +architecture rtl of full_adder_sl is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl;
\ No newline at end of file diff --git a/nghdl/Example/fa_SL_SLV/full_adder_sl_slv.vhdl b/nghdl/Example/fa_SL_SLV/full_adder_sl_slv.vhdl new file mode 100644 index 00000000..7de9c1b5 --- /dev/null +++ b/nghdl/Example/fa_SL_SLV/full_adder_sl_slv.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity full_adder_sl_slv is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic; + o_carry : out std_logic_vector(0 downto 0) + ); +end full_adder_sl_slv; + +architecture rtl of full_adder_sl_slv is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3(0); + o_carry(0) <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3(0)) or (i_bit3(0) and i_bit1); +end rtl;
\ No newline at end of file diff --git a/nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl b/nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl new file mode 100644 index 00000000..f9f2e929 --- /dev/null +++ b/nghdl/Example/nghdl_half_adder/nghdl_ha.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity nghdl_ha is +port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end nghdl_ha; + + +architecture rtl of nghdl_ha is + +begin + + o_sum <= i_bit1 xor i_bit2; + o_carry <= i_bit1 and i_bit2; + +end rtl;
\ No newline at end of file diff --git a/nghdl/Example/struct_fa/full_adder_structural.vhdl b/nghdl/Example/struct_fa/full_adder_structural.vhdl new file mode 100644 index 00000000..91b2762f --- /dev/null +++ b/nghdl/Example/struct_fa/full_adder_structural.vhdl @@ -0,0 +1,85 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity full_adder_structural is +port(a: in std_logic; + b: in std_logic; + cin: in std_logic; + sum: out std_logic; + carry: out std_logic); +end full_adder_structural; + +library ieee; +use ieee.std_logic_1164.all; + +entity andgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end andgate; + +architecture e1 of andgate is +begin +z <= a and b; +end e1; + +library ieee; +use ieee.std_logic_1164.all; + +entity xorgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end xorgate; + +architecture e2 of xorgate is +begin +z <= a xor b; +end e2; + +library ieee; +use ieee.std_logic_1164.all; + +entity orgate is +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end orgate; + +architecture e3 of orgate is +begin +z <= a or b; +end e3; + + +architecture structural of full_adder_structural is + +component andgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +component xorgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +component orgate +port(a: in std_logic; + b: in std_logic; + z: out std_logic); +end component; + +signal c1,c2,c3: std_logic; + +begin + +u1 : xorgate port map(a,b,c1); +u2 : xorgate port map(c1,cin,sum); +u3 : andgate port map(c1,cin,c2); +u4 : andgate port map(a,b,c3); +u5 : orgate port map(c2,c3,carry); + +end structural;
\ No newline at end of file diff --git a/nghdl/Example/trial_demux/t_demux.vhdl b/nghdl/Example/trial_demux/t_demux.vhdl new file mode 100644 index 00000000..1e1f0bde --- /dev/null +++ b/nghdl/Example/trial_demux/t_demux.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity t_demux is + port( + + F : in STD_LOGIC_vector(0 downto 0); + S0: in STD_LOGIC_vector(0 downto 0); + S1: in STD_LOGIC_vector(0 downto 0); + A: out STD_LOGIC_vector(0 downto 0); + B: out STD_LOGIC_vector(0 downto 0); + C: out STD_LOGIC_vector(0 downto 0); + D: out STD_LOGIC_vector(0 downto 0) + ); +end t_demux; + +architecture bhv of t_demux is +begin +process (F,S0,S1) is +begin + if (S0 ="0" and S1 = "0") then + A <= F; + elsif (S0 ="1" and S1 = "0") then + B <= F; + elsif (S0 ="0" and S1 = "1") then + C <= F; + else + D <= F; + end if; + +end process; +end bhv;
\ No newline at end of file diff --git a/nghdl/Example/trial_fa/trial_fa.vhdl b/nghdl/Example/trial_fa/trial_fa.vhdl new file mode 100644 index 00000000..6357aa23 --- /dev/null +++ b/nghdl/Example/trial_fa/trial_fa.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity trial_fa is + port ( + i_bit1 : in std_logic_vector(0 downto 0); + i_bit2 : in std_logic_vector(0 downto 0); + i_bit3 : in std_logic_vector(0 downto 0); + o_sum : out std_logic_vector(0 downto 0); + o_carry : out std_logic_vector(0 downto 0) + ); +end trial_fa; + +architecture rtl of trial_fa is +begin + o_sum <= i_bit1 xor i_bit2 xor i_bit3; + o_carry <= (i_bit1 and i_bit2) or (i_bit2 and i_bit3) or (i_bit3 and i_bit1); +end rtl;
\ No newline at end of file diff --git a/nghdl/Example/xor/myxor.vhdl b/nghdl/Example/xor/myxor.vhdl new file mode 100644 index 00000000..b49f3cad --- /dev/null +++ b/nghdl/Example/xor/myxor.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity myxor is + port (a : in std_logic_vector(0 downto 0); + b : in std_logic_vector(0 downto 0); + c : out std_logic_vector(0 downto 0)); + end myxor; + + architecture rtl of myxor is + begin + + c <= a xor b; + + end rtl; diff --git a/nghdl/Example/xor/xor-test.cir b/nghdl/Example/xor/xor-test.cir new file mode 100644 index 00000000..910839ee --- /dev/null +++ b/nghdl/Example/xor/xor-test.cir @@ -0,0 +1,45 @@ + +*** input sources *** + +v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0 + +40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0) + +v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0 + + 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0) + +Vvdd vdd 0 DC 2.0 + +*** resistors to ground *** +r1 100 0 1k +r2 200 0 1k + + +* +*** adc_bridge blocks *** +aconverter1 [100 200 ] [1 2] adc + + +axor [1] [2] [12] axors + +adac1 [12] [34] dac +*************model*********** + +.model axors myxor(instance_id = 112 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n) + +.model adc adc_bridge ( in_low =0.5 in_high =1.0 ++ rise_delay =1.0e-10 fall_delay =1.0e-10) +.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0 ++ input_load = 5.0e-14 t_rise = 1.0e-10 ++ t_fall = 1.0e-10) + + +.end + + + +.CONTROL + +option noopalter +tran .1n 100n +.ENDC + diff --git a/nghdl/GHDLside.md b/nghdl/GHDLside.md new file mode 100644 index 00000000..64ad7f0f --- /dev/null +++ b/nghdl/GHDLside.md @@ -0,0 +1,35 @@ +# Code Documentation (GHDL Side) + +This documentation will help you to know about the code written for communication between server and Digital logic written in VHDL + +## Files generated automatically for GHDL side + +* modelname_tb.vhdl +* Note: where modelname will be the name of your model + +## modelname_tb.vhdl + +* This is a testbench created to send and receive values from server and gives the input values to the digital design. +* It uses VHPI library of VHDL, by including this library we can use functions written in C program, in VHDL. +* In this test bench there are two processes used. +* First process is used to initialize, listen server and sending the output to server. +* Second process is used to giving inputs from server to digital design and taking the values to send through the server. + +### C functions used in modelname_tb.vhdl +#### Vhpi_Initialize +* This function is used to create the port and initialize the server. + +#### Vhpi_Listen +* This function is used to start communication between client and server. + +#### Vhpi_Send +* This function is used to send the values to client. + +#### Pack_String_To_Vhpi_String +* As we are sending values along with there variable name, we are using this function which convert the vhdl string to VHPI string. + +#### Vhpi_Get_Port_Value +* This function takes input values from server, when Vhpi_Listen called, and give it to digital design. + +#### Vhpi_Set_Port_Value +* This function is used to takes output values from digital design and send it through server when Vhpi_Send called. diff --git a/nghdl/LICENSE b/nghdl/LICENSE new file mode 100644 index 00000000..7080e5af --- /dev/null +++ b/nghdl/LICENSE @@ -0,0 +1,18 @@ + +Please note that the following codes are copyrighted under BSD license. + +src/ghdlserver/ghdlserver.c +src/ghdlserver/ghdlserver.h +src/ghdlserver/Utility_Package.vhdl +src/ghdlserver/Vhpi_Package.vhdl + +Copyright 2015 Prof.M.P Desai (madhav@ee.iitb.ac.in) and Powai Labs. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + diff --git a/nghdl/Workflow.md b/nghdl/Workflow.md new file mode 100644 index 00000000..1077d326 --- /dev/null +++ b/nghdl/Workflow.md @@ -0,0 +1,102 @@ +1. When `nghdl` button clicked in `eSim` it calls the `ngspice_ghdl.py` from `nghdl` installed directory +- `ngspice_ghdl.py` defines the UI for nghdl, and the functionality of each button +- When `Upload` clicked, it calls `uploadModle` function from `ngspice_ghdl.py` +- Similarly functions called on each button click defined +- `uploadModle` inturn calls these 5 functions sequentially => +- - createModelDirectory() +- - addingModelInModpath() +- - createModelFiles() +- - runMake() +- - runMakeInstall() + +2. `createModelDirectory()` +- Create directory for the specified file name at `~/ngspice-nghdl/src/xspice/icm/ghdl/` +- The location where the directory is created in mentioned at `~/.nghdl/config.ini`, this config file is inside a hidden folder `.ngdhl`, created when nghdl is installed +- If a folder of the same name exists, it asks to overwrite, then removes earlier folder, and writes new one + +3. `addingModelInModpath()` +- This adds the name of the new model created to `modpath.lst` file +- `modpath.lst` is located at `~/ngspice-nghdl/src/xspice/icm/ghdl`, this should contain name of all the models that the folder has +- Similarly you can look at `~/ngspice-nghdl/src/xspice/icm/digital` which also contains a `modpath.list` for all the models in that folder +- This `modpath.lst` is used in the `GNUMakefile` at `~/ngspice-nghdl/release/src/xspice/icm` +- This file used to keep a track of all components created +- If model already there it isn't added to the list + +4. `createModelFiles()` +- Calls `model_generation.py` at the installed nghdl location under `src/model_generation.py` +- Moves the generated `cfunc.mode` and `ifspec.ifs` files to `~/ngspice-nghdl/src/xspice/icm/ghdl/modelName` +- Creates `DUTghdl` folder at `~/ngspice-nghdl/src/xspice/icm/ghdl/modelName` +- Move `compile.sh`,`uthash.sh`,`ghdlserver.c`,`ghdlserver.h`,`Utility_Package.vhdl`,`Vhpi_Package.vhdl` to the `DUTghdl` folder +- Copy `modelName.vhdl` file from source location to `DUTghdl` folder +- Rum `compile.sh` which generates the object file for `ghdlserver.c` +- Give permission to `start_server.sh` and `sock_pkg_create.sh` to execute _chod a+x_ +- Finally remove `compile.sh` and `ghdlserver.c` + +5. `model_generation.py` +- Creates the following files => +- - `connection_info.txt` +- - `cfunc.mod` +- - `ifspec.ifs` +- - `modelName_tb.vhdl` => testbench file for the model +- - `start_server.sh` +- - `sock_pkg_create.sh` +- The above files can be found either at `~/ngspice-nghdl/src/xspice/icm/ghdl/modelName` or `DUTghdl` folder inside it + +6. `runMake()` +- Runs the `Makefile` at `~/ngspice-nghdl/release` +- Executing by running `make` command + +7. `runMakeInstall()` +- Executes `make install` +- Finally calls `createSchematicLib()` + +8. `createSchematicLib()` +- Connects with `createKicadLibrary.py` file at `~/nghdl/src` +- Generates the `lib` file for the model, to be used by `KiCad` +- This is generated from a template stored at `Appconfig.py` +- The generated `lib` is stored at `~/eSim_kicad.lib` +- Also creates `xml` file for the model, which is stored at eSim under `eSimLoc/src/modelParamXML/Nghdl + +<br/> + +Finally all the relevant files are generated, now while executing ngspice, we need to make sure to run the ngspice, which is located at - +- `~/ngspice-nghdl/install_dir/bin/ngspice` this has the binary for the ngspice, +- And also the script at `~/ngspice-nghdl/install_dir/share/ngspice/scripts/spinit` += ` spinit` has the line `codemodel ...` mentioning a `cm` file to execute at runtime +- This has mention of `ghdl.cm` which makes sure that our `cfunc.c` file is executed at runtime +- You can see the `ghdl.cm` file is located at `~/ngspice-nghdl/release/src/xspice/icm/ghdl` +- Also the `cfunc.c` files, located at `~/ngspice-nghdl/release/src/xspice/icm/ghdl/modelName` +- These have mention of the `start_server.sh` file at `DUTghdl`, hence server is started and values passed as well +- Also you can look at `~/ngspice-nghdl/release/src/xspice/icm/digital` it has `digital.cm` and the folders inside have `cfunc.c` +- Also has `ifspec.c` which defines the interface + +<br/> + +- Note that, if you have ngspice currently installed remove it and genearate a softlink or command for the ngspice installed at - +`~/ngspice-nghdl/install_dir/bin/ngspice` +- `whereis ngspice`, run this to get the location from where `ngspice` is being executed currently +<br/> + +- To generate softlink refer - [Creating softlink](https://askubuntu.com/questions/56339/how-to-create-a-soft-or-symbolic-link)i +- Exeecute `ln -s ~/ngspice-nghdl/install_dir/bin/ngspice /usr/bin/ngspice` + + +<br/> + +- Also the installation script doesn't install ghdl, you will have to do it manually, either through a `.deb` package or build it from [source](https://github.com/ghdl/ghdl) +- Note that since we are using socket programming here, we require either the `llvm` architecture or `gcc`. Using `mcode` backend won't work here + +<br/> + +- To install ghdl from source, [this](https://github.com/ghdl/ghdl/issues/550) Github issue might be helpfu, the steps are - +- - `sudo ./configure --with-llvm-config` +- - sudo make +- - sudo make install +- Check [this](https://github.com/ghdl/ghdl/issues/166) Github issue for those building from `.deb` package +- To check current version and architecure of ghdl use - +- - `ghdl --version` command, it should have `llvm` code generator or `gcc` +<br/> + +- Also once ghdl is installed, to check syntax of your vhdl files use - +`ghdl -s <vhdl file location>` +- Note that we need `std_vector_logic` as our ports here diff --git a/nghdl/doc/readme.md b/nghdl/doc/readme.md new file mode 100644 index 00000000..7aa0c6e2 --- /dev/null +++ b/nghdl/doc/readme.md @@ -0,0 +1,51 @@ +Ngspice Ghdl Interfacing Documentation +==== + +It contains all the documenation for Ngspice and Ghdl related work. + +Note: This project is still in alpha version and has been tested for basic digital components. +==== + +## What exactly interfacing of ngspice ghdl do? +Ngspice support mixed mode simulation. It can simulate both digital and analog component. + +Ngspice has something called model which define the functionality of your circuit,which can be used in the netlist. For example you can create adder model in ngspice and use it in any circuit netlist of ngspice. + +Now the question is if we already have digital model in ngspice why this interfacing ? +Well in ngspice it is little tediouse to write your digital model. But many people are familiar with ghdl and can easily write the vhdl code. +So the idea of interfacing is just to write ghdl code for a model and install it as dummy model in ngspice. So whenever ngspice look +for that model it will actually call the ghdl to get the result. + + +##Pre-requisites +1. Ubuntu 12.04 (You can try it on other version and let us know) +2. Python 2.7 +3. PyQt4 +4. ghdl + +##How to install? +1. Clone this repository. +2. Run `./install-nghdl.sh` It will install ngspice from source code and put it in $HOME. + + +##Few words about installed code structure. +1. Ngspice will be installed in home directory $HOME. If you already have ngspice-26 directory there it will take its backup. +2. Source code for all other file will be present in ~/.esim-nghdl +3. symlink nghdl is stored in /usr/local/bin + +##How to use? +1. Run nghdl in command terminal. +2. Upload your vhdl file. +3. Model will be created with your name of your vhdl file. +4. You can use this model in your netlist. + +##LIMITATION: +1. You can use only one output port in your file. +2. All the port should be std_logic_vector only. +3. We can use only one code model of such type in our netlist. + +##FUTURE WORK +1. Make changes to have more than one output. +2. Making changes to include use of more than one code models. +3. Interfacing it with esim formely known as Oscad so that we can use it in our schematic. + diff --git a/nghdl/install-nghdl.sh b/nghdl/install-nghdl.sh new file mode 100755 index 00000000..0831468a --- /dev/null +++ b/nghdl/install-nghdl.sh @@ -0,0 +1,272 @@ +#!/bin/bash +#=============================================================================== +# +# FILE: install-nghdl.sh +# +# USAGE: ./install-nghdl.sh +# +# DESCRIPTION: It is installation script for ngspice and ghdl work (nghdl). +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan , fahim.elex@gmail.com +# ORGANIZATION: eSim, FOSSEE group at IIT Bombay +# CREATED: Tuesday 02 December 2014 17:01 +# REVISION: --- +#=============================================================================== + +ngspice="ngspice-nghdl" +ghdl="ghdl-0.36" +config_dir="$HOME/.nghdl" +config_file="config.ini" +src_dir=`pwd` + +#Will be used to take backup of any file +sysdate="$(date)" +timestamp=`echo $sysdate|awk '{print $3"_"$2"_"$6"_"$4 }'` + + +#All functions goes here +function addghdlPPA +{ + ghdlppa="pgavin/ghdl" + #Checking if ghdl ppa is already exist + grep -h "^deb.*$ghdlppa*" /etc/apt/sources.list.d/* > /dev/null 2>&1 + if [ $? -ne 0 ] + then + echo "Adding ghdl PPA to install latest ghdl version" + sudo add-apt-repository -y ppa:pgavin/ghdl + sudo apt-get update + else + echo "ghdl is available in synaptic" + fi +} + +# make +# gnat +# llvm +# clang +# zlib1g-dev +function installDependency +{ + + # echo "Updating indexes to install latest versions......" + # sudo apt-get update + + # echo "Installing dependencies for ghdl-0.36 LLVM......." + # echo "Installing make.................................." + # sudo apt-get install -y make + # echo "Installing gnat-5.................................." + # sudo apt-get install -y gnat-5 + # echo "Installing llvm.................................." + # sudo apt-get install -y llvm + # echo "Installing clang.................................." + # sudo apt-get install -y clang + # echo "Installing zlib1g-dev.................................." + # sudo apt-get install -y zlib1g-dev + + # if [ -d $HOME/$ghdl ]; then + # echo "$ghdl directory already exists at $HOME" + # echo "Leaving ghdl-0.36 LLVM installation" + # else + # tar -xzvf $ghdl.tar.gz -C $HOME + # if [ "$?" == 0 ];then + # echo "ghdl-0.36 LLVM successfully extracted to $HOME......" + # echo "Changing directory to ghdl-0.36 LLVM installation..." + # cd $HOME/$ghdl + # echo "Configuring ghdl-0.36 build as per requirements....." + # #Other configure flags can be found at - https://github.com/ghdl/ghdl/blob/master/configure + # sudo ./configure --with-llvm-config + # echo "Building the install file for ghdl-0.36 LLVM....." + # sudo make + # echo "Installing ghdl-0.36 LLVM....." + # sudo make install + # else + # echo "Unable to extract ghdl-0.36 LLVM" + # echo "Exiting installation" + # exit 1 + # fi + # fi + + echo "Installing flex.................................." + sudo apt-get install -y flex + echo "Installing bison................................." + sudo apt-get install -y bison + + # Specific dependency for nvidia graphic cards + echo "Installing graphics dependency for ngspice souce build" + echo "Installing libxaw7................................" + sudo apt-get install libxaw7 + echo "Installing libxaw7-dev............................" + sudo apt-get install libxaw7-dev +} + + +function installNgspice +{ + echo "Installing ngspice..................................." + #Checking if ngspice-nghdl directory is already present in Home directory + if [ -d $HOME/$ngspice ];then + echo "$ngspice directory already exists at $HOME" + echo "Leaving ngspice installation" + else + #Extracting Ngspice to Home Directory + cd $src_dir + tar -xzvf $ngspice.tar.gz -C $HOME + if [ "$?" == 0 ];then + echo "Ngspice extracted sucessfuly to $HOME " + #change to ngspice-nghdl directory + cd $HOME/$ngspice + #Make local install directory + mkdir -p install_dir + #Make release directory for build + mkdir -p release + #Change to release directory + cd release + echo "Installing Ngspice....." + echo "------------------------------------" + sleep 5 + ../configure --enable-xspice --disable-debug --prefix=$HOME/$ngspice/install_dir/ --exec-prefix=$HOME/$ngspice/install_dir/ + + #dirty fix for adding patch to ngspice base code + cp $src_dir/src/outitf.c $HOME/$ngspice/src/frontend + + make + make install + if [ "$?" == 0 ];then + echo "Ngspice Installed sucessfully......" + echo "Adding softlink for the installed ngspice......" + + sudo ln -s $HOME/$ngspice/install_dir/bin/ngspice /usr/bin/ngspice + if [ "$?" == 0 ];then + echo "failed to add softlink" + echo "ngspice already installed at /usr/bin/ngspice..." + echo "Remove earlier installations and try again..." + else + echo "Added softlink for ngspce" + fi + + else + echo "There was some error in installing ngspice" + fi + + + else + echo "Unable to extract ngspice tar file" + exit 1; + fi + + fi +} + +function createConfigFile +{ + #Creating config.ini file and adding configuration information + #Check if config file is present + if [ -d $config_dir ];then + rm $config_dir/$config_file && touch $config_dir/$config_file + else + mkdir $config_dir && touch $config_dir/$config_file + + fi + + echo "[NGSPICE]" >> $config_dir/$config_file + echo "NGSPICE_HOME = $HOME/$ngspice" >> $config_dir/$config_file + echo "DIGITAL_MODEL = %(NGSPICE_HOME)s/src/xspice/icm/ghdl" >> $config_dir/$config_file + echo "RELEASE = %(NGSPICE_HOME)s/release" >> $config_dir/$config_file + echo "[SRC]" >> $config_dir/$config_file + echo "SRC_HOME = $src_dir" >> $config_dir/$config_file + echo "LICENSE = %(SRC_HOME)s/LICENSE" >> $config_dir/$config_file + +} + +function createSoftLink +{ + + ## Creating softlink + cd /usr/local/bin + if [[ -L nghdl ]];then + echo "Symlink was already present" + sudo unlink nghdl + sudo ln -sf $src_dir/src/ngspice_ghdl.py nghdl + + else + echo "Creating synmlink" + sudo ln -sf $src_dir/src/ngspice_ghdl.py nghdl + fi + cd $pwd + +} + +##################################################################### +# Script start from here # +##################################################################### +echo "Enter proxy details if you are connected to internet thorugh proxy" + +echo -n "Is your internet connection behind proxy? (y/n): " +read getProxy +if [ $getProxy == "y" -o $getProxy == "Y" ];then + echo -n 'Proxy hostname :' + read proxyHostname + + echo -n 'Proxy Port :' + read proxyPort + + echo -n username@$proxyHostname:$proxyPort : + read username + + echo -n 'Password :' + read -s passwd + + unset http_proxy + unset https_proxy + unset HTTP_PROXY + unset HTTPS_PROXY + unset ftp_proxy + unset FTP_PROXY + + export http_proxy=http://$username:$passwd@$proxyHostname:$proxyPort + export https_proxy=http://$username:$passwd@$proxyHostname:$proxyPort + export HTTP_PROXY=http://$username:$passwd@$proxyHostname:$proxyPort + export HTTPS_PROXY=http://$username:$passwd@$proxyHostname:$proxyPort + export ftp_proxy=http://$username:$passwd@$proxyHostname:$proxyPort + export FTP_PROXY=http://$username:$passwd@$proxyHostname:$proxyPort + + echo "Install with proxy" + #Calling functions + addghdlPPA + installDependency + if [ $? -ne 0 ];then + echo -e "\n\n\nERROR: Unable to install required packages. Please check your internet connection.\n\n" + exit 0 + fi + installNgspice + createConfigFile + createSoftLink + +elif [ $getProxy == "n" -o $getProxy == "N" ];then + echo "Install without proxy" + + #Calling functions + addghdlPPA + installDependency + if [ $? -ne 0 ];then + echo -e "\n\n\nERROR: Unable to install required packages. Please check your internet connection.\n\n" + exit 0 + fi + installNgspice + createConfigFile + createSoftLink + + +else + echo "Please select the right option" + exit 0 + +fi + + + + diff --git a/nghdl/ngspice-nghdl.tar.gz b/nghdl/ngspice-nghdl.tar.gz Binary files differnew file mode 100644 index 00000000..4996cdca --- /dev/null +++ b/nghdl/ngspice-nghdl.tar.gz diff --git a/nghdl/readme.md b/nghdl/readme.md new file mode 100644 index 00000000..f2e9a02d --- /dev/null +++ b/nghdl/readme.md @@ -0,0 +1,51 @@ +Ngspice Ghdl Interfacing Documentation +==== + +It contains all the documenation for Ngspice and Ghdl related work. + +Note: This project is still in alpha version and has been tested for basic digital components. +==== + +## What exactly interfacing of ngspice ghdl do? +Ngspice support mixed mode simulation. It can simulate both digital and analog component. + +Ngspice has something called model which define the functionality of your circuit,which can be used in the netlist. For example you can create adder model in ngspice and use it in any circuit netlist of ngspice. + +Now the question is if we already have digital model in ngspice why this interfacing ? +Well in ngspice it is little tediouse to write your digital model. But many people are familiar with ghdl and can easily write the vhdl code. +So the idea of interfacing is just to write ghdl code for a model and install it as dummy model in ngspice. So whenever ngspice look +for that model it will actually call the ghdl to get the result. + + +##Pre-requisites +1. Ubuntu 12.04 (You can try it on other version and let us know) +2. Python 2.7 +3. PyQt4 + + +##How to install? +1. Clone this repository. +2. Run `./install-nghdl.sh` It will install ngspice from source code and put it in $HOME. +3. Set ngspice path in `.bashrc` file. Add `export PATH=/home/{your-username}/ngspice-26/install_dir/bin:$PATH` line in .bashrc + +##Few words about installed code structure. +1. Ngspice will be installed in home directory $HOME. If you already have ngspice-26 directory there it will take its backup. +2. Source code for all other file will be present in ~/.esim-nghdl +3. symlink nghdl is stored in /usr/local/bin + +##How to use? +1. Run nghdl in command terminal. +2. Upload your vhdl file. +3. Model will be created with name of your vhdl file. It can be seen under (~ngspice-26/src/xspice/icm/ghdl/) +4. You can use this model in your netlist. + +##LIMITATION: +1. You can use only one output port in your file. +2. All the port should be std_logic_vector only. +3. We can use only one instance of code model in netlist. + +##FUTURE WORK +1. Make changes to have more than one output. +2. Making changes to include use of more than one instance of code models. +3. Interfacing it with eSim formely known as Oscad so that we can use it in our schematic. + diff --git a/nghdl/src/Appconfig.py b/nghdl/src/Appconfig.py new file mode 100644 index 00000000..6909c531 --- /dev/null +++ b/nghdl/src/Appconfig.py @@ -0,0 +1,35 @@ +import os.path +from ConfigParser import SafeConfigParser + + +class Appconfig: + home = os.path.expanduser("~") + #Reading all varibale from eSim config.ini + parser_esim = SafeConfigParser() + parser_esim.read(os.path.join(home, os.path.join('.esim','config.ini'))) + try: + src_home = parser_esim.get('eSim','eSim_HOME') + xml_loc = os.path.join(src_home,'src/modelParamXML') + lib_loc = os.path.expanduser('~') + except: + pass + esimFlag = 0 + + #Reading all variable from nghdl config.ini + parser_nghdl = SafeConfigParser() + parser_nghdl.read(os.path.join(home,os.path.join('.nghdl','config.ini'))) + + kicad_lib_template = { + "start_def":"DEF comp_name U 0 40 Y Y 1 F N", + "U_field":"F0 \"U\" 2850 1800 60 H V C CNN", + "comp_name_field":"F1 \"comp_name\" 2850 2000 60 H V C CNN", + "blank_field":["F2 blank_quotes 2850 1950 60 H V C CNN","F3 blank_quotes 2850 1950 60 H V C CNN"], + "start_draw":"DRAW", + "draw_pos":"S 2550 2100 3150 1800 0 1 0 N", + "input_port":"X in 1 2350 2000 200 R 50 50 1 1 I", + "output_port":"X out 2 3350 2000 200 L 50 50 1 1 O", + "end_draw":"ENDDRAW", + "end_def":"ENDDEF" + } + + diff --git a/nghdl/src/createKicadLibrary.py b/nghdl/src/createKicadLibrary.py new file mode 100644 index 00000000..d2290660 --- /dev/null +++ b/nghdl/src/createKicadLibrary.py @@ -0,0 +1,236 @@ +from Appconfig import Appconfig +import re +import os +import xml.etree.cElementTree as ET +from PyQt4 import QtGui, QtCore + + +class AutoSchematic(QtGui.QWidget): + + def __init__(self, modelname): + QtGui.QWidget.__init__(self) + self.modelname = modelname.split('.')[0] + self.template = Appconfig.kicad_lib_template + self.xml_loc = Appconfig.xml_loc + self.lib_loc = Appconfig.lib_loc + self.kicad_nghdl_lib = 'eSim_kicad.lib' + self.parser = Appconfig.parser_nghdl + + def createKicadLibrary(self): + xmlFound = None + for root, dirs, files in os.walk(self.xml_loc): + if (str(self.modelname) + '.xml') in files: + xmlFound = root + print(xmlFound) + if (xmlFound == None): + self.getPortInformation() + self.createXML() + self.createLib() + elif (xmlFound == self.xml_loc + '/Nghdl'): + print 'Library already exists...' + ret = QtGui.QMessageBox.critical(self, "Critical",'''<b>The Libraries of this model already exist.Do you want to overwrite it?</b><br/> + <b>If yes press ok else cancel it and change the name of your vhdl file</b>''', QtGui.QMessageBox.Ok, QtGui.QMessageBox.Cancel) + if ret == QtGui.QMessageBox.Ok: + print "Overwriting existing libraries" + self.getPortInformation() + self.createXML() + self.removeOldLibrary() #Removes the exisitng library + self.createLib() + else: + print "Exiting Nghdl" + quit() + else: + print 'Pre existing library...' + ret = QtGui.QMessageBox.critical(self, "Error",'''<b>A standard library already exists in this name.</b><br/> + <b>Please change the name of your vhdl file and upload it again</b>''', QtGui.QMessageBox.Ok) + + # quit() + + def getPortInformation(self): + portInformation = PortInfo(self) + portInformation.getPortInfo() + self.portInfo = portInformation.bit_list + self.input_length = portInformation.input_len + + def createXML(self): + cwd = os.getcwd() + xmlDestination = os.path.join(self.xml_loc, 'Nghdl') + self.splitText = "" + for bit in self.portInfo[:-1]: + self.splitText += bit + "-V:" + self.splitText += self.portInfo[-1] + "-V" + + print "changing directory to ", (xmlDestination) + os.chdir(xmlDestination) + + root = ET.Element("model") + ET.SubElement(root, "name").text = self.modelname + ET.SubElement(root, "type").text = "Nghdl" + ET.SubElement(root, "node_number").text = str(len(self.portInfo)) + ET.SubElement(root, "title").text = "Add parameters for " + str(self.modelname) + ET.SubElement(root, "split").text = self.splitText + param = ET.SubElement(root, "param") + ET.SubElement(param, "rise_delay", default = "1.0e-9").text = "Enter Rise Delay (default=1.0e-9)" + ET.SubElement(param ,"fall_delay", default ="1.0e-9").text = "Enter Fall Delay (default=1.0e-9)" + ET.SubElement(param ,"input_load", default ="1.0e-12").text = "Enter Input Load (default=1.0e-12)" + ET.SubElement(param ,"instance_id", default ="1").text = "Enter Instance ID (Between 0-99)" + ET.SubElement(param ,"stop_time", default ="90e-9").text = "Enter the stop time to end the simulation (default=90e-9)" + tree = ET.ElementTree(root) + tree.write(str(self.modelname) + '.xml') + print "Leaving the directory ", (xmlDestination) + os.chdir(cwd) + + #Calculates the maximum between input and output ports + def findBlockSize(self): + ind = self.input_length + return max(self.char_sum(self.portInfo[:ind]), self.char_sum(self.portInfo[ind:])) + + def char_sum(self, ls): + return sum([int(x) for x in ls]) + + def removeOldLibrary(self): + cwd = os.getcwd() + os.chdir(self.lib_loc) + print "Changing directory to ", self.lib_loc + f = open(self.kicad_nghdl_lib) + lines = f.readlines() + f.close() + + output = [] + line_reading_flag = False + + for line in lines: + if line.startswith("DEF"): + if line.split()[1] == self.modelname: + line_reading_flag = True + if not line_reading_flag: + output.append(line) + if line.startswith("ENDDEF"): + line_reading_flag = False + + f = open(self.kicad_nghdl_lib, 'w') + for line in output: + f.write(line) + + os.chdir(cwd) + print "Leaving directory, ", self.lib_loc + + def createLib(self): + self.dist_port = 100 #distance between two ports + self.inc_size = 100 #Increment size of a block + cwd = os.getcwd() + os.chdir(self.lib_loc) + print "Changing directory to ", self.lib_loc + + lib_file = open(self.kicad_nghdl_lib,"a") + line1 = self.template["start_def"] + line1 = line1.split() + line1 = [w.replace('comp_name', self.modelname) for w in line1] + self.template["start_def"] = ' '.join(line1) + if os.stat(self.kicad_nghdl_lib).st_size == 0: + lib_file.write("EESchema-LIBRARY Version 2.3"+ "\n\n") + #lib_file.write("#encoding utf-8"+ "\n"+ "#"+ "\n" + "#test_compo" + "\n"+ "#"+ "\n") + lib_file.write(self.template["start_def"]+ "\n"+self.template["U_field"]+"\n") + + line3 = self.template["comp_name_field"] + line3 = line3.split() + line3 = [w.replace('comp_name', self.modelname) for w in line3] + self.template["comp_name_field"] = ' '.join(line3) + + lib_file.write(self.template["comp_name_field"]+ "\n") + + line4 = self.template["blank_field"] + line4_1 = line4[0] + line4_2 = line4[1] + line4_1 = line4_1.split() + line4_1 = [w.replace('blank_quotes','""') for w in line4_1] + line4_2 = line4_2.split() + line4_2 = [w.replace('blank_quotes','""') for w in line4_2] + line4[0] = ' '.join(line4_1) + line4[1] = ' '.join(line4_2) + self.template["blank_qoutes"] = line4 + + lib_file.write(line4[0]+"\n" + line4[1]+"\n"+ self.template["start_draw"]+ "\n") + + draw_pos = self.template["draw_pos"] + draw_pos = draw_pos.split() + draw_pos[4] = str(int(draw_pos[4])- self.findBlockSize() * self.inc_size) + self.template["draw_pos"] = ' '.join(draw_pos) + + lib_file.write(self.template["draw_pos"]+"\n") + + input_port = self.template["input_port"] + input_port = input_port.split() + output_port = self.template["output_port"] + output_port = output_port.split() + inputs = self.portInfo[0: self.input_length] + outputs = self.portInfo[self.input_length:] + + print "INPUTS AND OUTPUTS " + print inputs + print outputs + + inputs = self.char_sum(inputs) + outputs= self.char_sum(outputs) + + total = inputs+outputs + + port_list = [] + + for i in xrange(total): + if (i < inputs): + input_port[1] = "in"+str(i+1) + input_port[2] = str(i+1) + input_port[4] = str(int(input_port[4])-self.dist_port) + input_list = ' '.join(input_port) + port_list.append(input_list) + + else: + output_port[1] = "out"+str(i- inputs+1) + output_port[2] = str(i+1) + output_port[4] = str(int(output_port[4])-self.dist_port) + output_list = ' '.join(output_port) + port_list.append(output_list) + + for ports in port_list: + lib_file.write(ports+"\n") + lib_file.write(self.template["end_draw"]+"\n"+ self.template["end_def"] + "\n\n\n") + + os.chdir(cwd) + print 'Leaving directory, ', self.lib_loc + QtGui.QMessageBox.information(self, "Library added", '''Library details for this model is added to the <b>eSim-kicad.lib</b> in the home directory''', QtGui.QMessageBox.Ok) + + +class PortInfo: + def __init__(self, model): + self.modelname = model.modelname + self.model_loc = model.parser.get('NGSPICE', 'DIGITAL_MODEL') + self.bit_list = [] + self.input_len = 0 + + def getPortInfo(self): + info_loc = os.path.join(self.model_loc, self.modelname+'/DUTghdl/') + input_list = [] + output_list = [] + read_file=open(info_loc + 'connection_info.txt','r') + data=read_file.readlines() + read_file.close() + + for line in data: + if re.match(r'^\s*$', line): + pass + else: + in_items=re.findall("IN",line,re.MULTILINE|re.IGNORECASE) + out_items=re.findall("OUT",line,re.MULTILINE|re.IGNORECASE) + if in_items: + input_list.append(line.split()) + if out_items: + output_list.append(line.split()) + + for in_list in input_list: + self.bit_list.append(in_list[2]) + self.input_len = len(self.bit_list) + for out_list in output_list: + self.bit_list.append(out_list[2]) + + diff --git a/nghdl/src/ghdlserver/Utility_Package.vhdl b/nghdl/src/ghdlserver/Utility_Package.vhdl new file mode 100755 index 00000000..887a5a4d --- /dev/null +++ b/nghdl/src/ghdlserver/Utility_Package.vhdl @@ -0,0 +1,204 @@ +-- author: Madhav P. Desai +library ieee; +use ieee.std_logic_1164.all; + +package Utility_Package is + + ----------------------------------------------------------------------------- + -- constants + ----------------------------------------------------------------------------- + constant c_word_length : integer := 32; + constant c_vhpi_max_string_length : integer := 1024; + + ----------------------------------------------------------------------------- + -- types + ----------------------------------------------------------------------------- + subtype VhpiString is string(1 to c_vhpi_max_string_length); + + ----------------------------------------------------------------------------- + -- utility functions + ----------------------------------------------------------------------------- + function Minimum(x,y: integer) return integer; -- returns minimum + function Pack_String_To_Vhpi_String(x: string) return VhpiString; -- converts x to null terminated string + function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString; -- converts slv x to null terminated string + function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector; -- convert null term string to slv + function To_Std_Logic(x: VhpiString) return std_logic; -- string to sl + function To_String(x: std_logic) return VhpiString; -- string to sl + function Convert_To_String(val : natural) return STRING; -- convert val to string. + function Convert_SLV_To_String(val : std_logic_vector) return STRING; -- convert val to string. + function To_Hex_Char (constant val: std_logic_vector) return character; + function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING; -- convert val to string. + +end package Utility_Package; + +package body Utility_Package is + + ----------------------------------------------------------------------------- + -- utility functions + ----------------------------------------------------------------------------- + function Minimum(x,y: integer) return integer is + begin + if( x < y) then return x; else return y; end if; + end Minimum; + + function Ceiling(x,y: integer) return integer is + variable ret_var : integer; + begin + assert x /= 0 report "divide by zero in ceiling function" severity failure; + ret_var := x/y; + if(ret_var*y < x) then ret_var := ret_var + 1; end if; + return(ret_var); + end Ceiling; + + function Pack_String_To_Vhpi_String(x: string) return VhpiString is + alias lx: string(1 to x'length) is x; + variable strlen: integer; + variable ret_var : VhpiString; + begin + strlen := Minimum(c_vhpi_max_string_length-1,x'length); + for I in 1 to strlen loop + ret_var(I) := lx(I); + end loop; + ret_var(strlen+1) := nul; + return(ret_var); + end Pack_String_To_Vhpi_String; + + function Pack_SLV_To_Vhpi_String(x: std_logic_vector) return VhpiString is + alias lx : std_logic_vector(1 to x'length) is x; + variable strlen: integer; + variable ret_var : VhpiString; + begin + strlen := Minimum(c_vhpi_max_string_length-1,x'length); + for I in 1 to strlen loop + if(lx(I) = '1') then + ret_var(I) := '1'; + else + ret_var(I) := '0'; + end if; + end loop; + ret_var(strlen+1) := nul; + return(ret_var); + end Pack_SLV_To_Vhpi_String; + + function Unpack_String(x: VhpiString; lgth: integer) return std_logic_vector is + variable ret_var : std_logic_vector(1 to lgth); + variable strlen: integer; + begin + strlen := Minimum(c_vhpi_max_string_length-1,lgth); + for I in 1 to strlen loop + if(x(I) = '1') then + ret_var(I) := '1'; + else + ret_var(I) := '0'; + end if; + end loop; + return(ret_var); + end Unpack_String; + + function To_Std_Logic(x: VhpiString) return std_logic is + variable s: std_logic_vector(0 downto 0); + begin + s := Unpack_String(x,1); + return(s(0)); + end To_Std_Logic; + + function To_String(x: std_logic) return VhpiString is + variable s: std_logic_vector(0 downto 0); + begin + s(0) := x; + return(Pack_SLV_To_Vhpi_String(s)); + end To_String; + + -- Thanks to: D. Calvet calvet@hep.saclay.cea.fr + function Convert_To_String(val : NATURAL) return STRING is + variable result : STRING(10 downto 1) := (others => '0'); -- smallest natural, longest string + variable pos : NATURAL := 1; + variable tmp, digit : NATURAL; + begin + tmp := val; + loop + digit := abs(tmp MOD 10); + tmp := tmp / 10; + result(pos) := character'val(character'pos('0') + digit); + pos := pos + 1; + exit when tmp = 0; + end loop; + return result((pos-1) downto 1); + end Convert_To_String; + + function Convert_SLV_To_String(val : std_logic_vector) return STRING is + alias lval: std_logic_vector(1 to val'length) is val; + variable ret_var: string( 1 to lval'length); + begin + for I in lval'range loop + if(lval(I) = '1') then + ret_var(I) := '1'; + elsif (lval(I) = '0') then + ret_var(I) := '0'; + else + ret_var(I) := 'X'; + end if; + end loop; + return(ret_var); + end Convert_SLV_To_String; + + function To_Hex_Char (constant val: std_logic_vector) return character is + alias lval: std_logic_vector(1 to val'length) is val; + variable tvar : std_logic_vector(1 to 4); + variable ret_val : character; + begin + if(lval'length >= 4) then + tvar := lval(1 to 4); + else + tvar := (others => '0'); + tvar(1 to lval'length) := lval; + end if; + + case tvar is + when "0000" => ret_val := '0'; + when "0001" => ret_val := '1'; + when "0010" => ret_val := '2'; + when "0011" => ret_val := '3'; + when "0100" => ret_val := '4'; + when "0101" => ret_val := '5'; + when "0110" => ret_val := '6'; + when "0111" => ret_val := '7'; + when "1000" => ret_val := '8'; + when "1001" => ret_val := '9'; + when "1010" => ret_val := 'a'; + when "1011" => ret_val := 'b'; + when "1100" => ret_val := 'c'; + when "1101" => ret_val := 'd'; + when "1110" => ret_val := 'e'; + when "1111" => ret_val := 'f'; + when others => ret_val := 'f'; + end case; + + return(ret_val); + end To_Hex_Char; + + function Convert_SLV_To_Hex_String(val : std_logic_vector) return STRING is + alias lval: std_logic_vector(val'length downto 1) is val; + variable ret_var: string( 1 to Ceiling(lval'length,4)); + variable hstr : std_logic_vector(4 downto 1); + variable I : integer; + begin + + I := 0; + + while I < (lval'length/4) loop + hstr := lval(4*(I+1) downto (4*I)+1); + ret_var(ret_var'length - I) := To_Hex_Char(hstr); + I := (I + 1); + end loop; -- I + + hstr := (others => '0'); + if(ret_var'length > (lval'length/4)) then + hstr((lval'length-((lval'length/4)*4)) downto 1) := lval(lval'length downto (4*(lval'length/4))+1); + ret_var(1) := To_Hex_Char(hstr); + end if; + + return(ret_var); + end Convert_SLV_To_Hex_String; +end Utility_Package; + diff --git a/nghdl/src/ghdlserver/Vhpi_Package.vhdl b/nghdl/src/ghdlserver/Vhpi_Package.vhdl new file mode 100755 index 00000000..0c0baac4 --- /dev/null +++ b/nghdl/src/ghdlserver/Vhpi_Package.vhdl @@ -0,0 +1,77 @@ +-- author: Madhav P. Desai +library ieee; +use ieee.std_logic_1164.all; +library work; +use work.Utility_Package.all; +package Vhpi_Foreign is + + ----------------------------------------------------------------------------- + -- foreign Vhpi function + ----------------------------------------------------------------------------- + procedure Vhpi_Initialize(sock_port : in integer); + attribute foreign of Vhpi_Initialize : procedure is "VHPIDIRECT Vhpi_Initialize"; + + procedure Vhpi_Close; -- close . + attribute foreign of Vhpi_Close : procedure is "VHPIDIRECT Vhpi_Close"; + + procedure Vhpi_Listen; + attribute foreign of Vhpi_Listen : procedure is "VHPIDIRECT Vhpi_Listen"; + + procedure Vhpi_Send; + attribute foreign of Vhpi_Send : procedure is "VHPIDIRECT Vhpi_Send"; + + procedure Vhpi_Set_Port_Value(port_name: in VhpiString; port_value: in VhpiString; port_width: in integer); + attribute foreign of Vhpi_Set_Port_Value: procedure is "VHPIDIRECT Vhpi_Set_Port_Value"; + + procedure Vhpi_Get_Port_Value(port_name: in VhpiString; port_value : out VhpiString; port_width: in integer); + attribute foreign of Vhpi_Get_Port_Value : procedure is "VHPIDIRECT Vhpi_Get_Port_Value"; + + procedure Vhpi_Log(message_string: in VhpiString); + attribute foreign of Vhpi_Log : procedure is "VHPIDIRECT Vhpi_Log"; + +end Vhpi_Foreign; + +package body Vhpi_Foreign is + + ----------------------------------------------------------------------------- + -- subprogram bodies for foreign vhpi routines. will never be called + ----------------------------------------------------------------------------- + procedure Vhpi_Initialize(sock_port: in integer) is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Initialize; + + procedure Vhpi_Close is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Close; + + procedure Vhpi_Listen is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Listen; + + procedure Vhpi_Send is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Send; + + procedure Vhpi_Set_Port_Value(port_name: in VhpiString; port_value: in VhpiString; port_width: in integer) is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Set_Port_Value; + + procedure Vhpi_Get_Port_Value(port_name : in VhpiString; port_value: out VhpiString; port_width: in integer)is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Get_Port_Value; + + procedure Vhpi_Log(message_string: in VhpiString) is + begin + assert false report "fatal: this should never be called" severity failure; + end Vhpi_Log; + +end Vhpi_Foreign; + + + diff --git a/nghdl/src/ghdlserver/compile.sh b/nghdl/src/ghdlserver/compile.sh new file mode 100755 index 00000000..bfe413e3 --- /dev/null +++ b/nghdl/src/ghdlserver/compile.sh @@ -0,0 +1,6 @@ +#!/bin/sh +gcc -c ghdlserver.c +ghdl -a Utility_Package.vhdl && +ghdl -a Vhpi_Package.vhdl + + diff --git a/nghdl/src/ghdlserver/ghdlserver.c b/nghdl/src/ghdlserver/ghdlserver.c new file mode 100644 index 00000000..5bf2e993 --- /dev/null +++ b/nghdl/src/ghdlserver/ghdlserver.c @@ -0,0 +1,667 @@ +/************************************************************************* + * <ghdlserver.c> FOSSEE, IIT-Mumbai + * 24.Mar.2017 - Raj Mohan - Added signal handler for SIGUSR1, to handle an + * orphan test bench process. + * The test bench will now create a PID file in + * /tmp directory with the name + * NGHDL_<ngspice pid>_<test bench>_<instance_id> + * This file contains the PID of the test bench . + * On exit, the test bench removes this file. + * The SIGUSR1 signal serves the same purpose as the + * "End" signal. + * - Added syslog interface for logging. + * - Enabled SO_REUSEADDR socket option. + * - Added the following functions: + * o create_pid_file() + * o get_ngspice_pid() + * 22.Feb.2017 - Raj Mohan - Implemented a kludge to fix a problem in the + * test bench VHDL code. + * - Changed sleep() to nanosleep(). + * 10.Feb.2017 - Raj Mohan - Log messages with timestamp/code clean up. + * Added the following functions: + * o curtim() + * o print_hash_table() + ************************************************************************* + */ +#include <string.h> +#include "ghdlserver.h" +#include "uthash.h" +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <assert.h> +#include <signal.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/socket.h> +#include <sys/time.h> +#include <netinet/in.h> +#include <netdb.h> +#include <limits.h> +#include <time.h> +#include <errno.h> +#include <dirent.h> +#include <syslog.h> + +#define _XOPEN_SOURCE 500 +#define MAX_NUMBER_PORT 100 + +#define NGSPICE "ngspice" // 17.Mar.2017 - RM + +extern char* __progname; // 26.Feb.2017 May not be portable to non-GNU systems. + +void Vhpi_Exit(int sig); + +static FILE* pid_file; +static char pid_filename[80]; + +static char* Out_Port_Array[MAX_NUMBER_PORT]; +static int out_port_num = 0; +static int server_socket_id = -1; +static int sendto_sock; // 22.Feb.2017 - RM - Kludge +static int prev_sendto_sock; // 22.Feb.2017 - RM - Kludge +static int pid_file_created; // 10.Mar.2017 - RM + +struct my_struct { + char val[1024]; + char key[1024]; + UT_hash_handle hh; //Makes this structure hashable. +}; + +static struct my_struct *s, *users, *tmp = NULL; + +/* 17.Mar.2017 - RM - Get the process id of ngspice program.*/ +static int get_ngspice_pid(void) +{ + DIR* dirp; + FILE* fp = NULL; + struct dirent* dir_entry; + char path[1024], rd_buff[1024]; + pid_t pid = -1; + + if ((dirp = opendir("/proc/")) == NULL) + { + perror("opendir /proc failed"); + exit(-1); + } + + while ((dir_entry = readdir(dirp)) != NULL) + { + char* nptr; + int valid_num = 0; + + int tmp = strtol(dir_entry->d_name, &nptr, 10); + if ((errno == ERANGE) && (tmp == LONG_MAX || tmp == LONG_MIN)) + { + perror("strtol"); // Number out of range. + return(-1); + } + if (dir_entry->d_name == nptr) + { + continue; // No digits found. + } + if (tmp) + { + sprintf(path, "/proc/%s/comm", dir_entry->d_name); + if ((fp = fopen(path, "r")) != NULL) + { + fscanf(fp, "%s", rd_buff); + if (strcmp(rd_buff, NGSPICE) == 0) + { + pid = (pid_t)tmp; + } + } + } + } + + if (fp) fclose(fp); + + return(pid); +} + +/* 23.Mar.2017 - RM - Pass the sock_port argument. We need this if a netlist + * uses more than one instance of the same test bench, so that we can uniquely + * identify the PID files. + */ +/* 10.Mar.2017 - RM - Create PID file for the test bench in /tmp. */ +static void create_pid_file(int sock_port) +{ + pid_t my_pid = getpid(); + pid_t ngspice_pid = get_ngspice_pid(); + if (ngspice_pid == -1) + { + fprintf(stderr, "create_pid_file() Failed to get ngspice PID"); + syslog(LOG_ERR, "create_pid_file() Failed to get ngspice PID"); + exit(1); + } + sprintf(pid_filename, "/tmp/NGHDL_%d_%s_%d", ngspice_pid, __progname, + sock_port); + pid_file = fopen(pid_filename, "w"); + if (pid_file) + { + pid_file_created = 1; + fprintf(pid_file,"%d\n", my_pid); + fclose(pid_file); + } else { + perror("fopen() - PID file"); + syslog(LOG_ERR, "create_pid_file(): Unable to open PID file in /tmp"); + exit(1); + } + + return; +} + +#ifdef DEBUG +static char* curtim(void) +{ + static char ct[50]; + struct timeval tv; + struct tm* ptm; + long milliseconds; + char time_string[40]; + + gettimeofday (&tv, NULL); + ptm = localtime (&tv.tv_sec); + strftime (time_string, sizeof (time_string), "%Y-%m-%d %H:%M:%S", ptm); + milliseconds = tv.tv_usec / 1000; + sprintf (ct, "%s.%03ld", time_string, milliseconds); + return(ct); +} +#endif + +#ifdef DEBUG +static void print_hash_table(void) +{ + struct my_struct *sptr; + + for(sptr=users; sptr != NULL; sptr=sptr->hh.next) + { + syslog(LOG_INFO, "Hash table:val:%s: key: %s", sptr->val, sptr->key); + } +} +#endif + +static void parse_buffer(int sock_id, char* receive_buffer) +{ + static int rcvnum; + + syslog(LOG_INFO,"RCVD RCVN:%d from CLT:%d buffer : %s", + rcvnum++, sock_id,receive_buffer); + + /*Parsing buffer to store in hash table */ + char *rest; + char *token; + char *ptr1=receive_buffer; + char *var; + char *value; + + // Processing tokens. + while(token = strtok_r(ptr1, ",", &rest)) + { + ptr1 = rest; + while(var=strtok_r(token, ":", &value)) + { + s = (struct my_struct*)malloc(sizeof(struct my_struct)); + strncpy(s->key, var, 64); + strncpy(s->val, value, 64); + HASH_ADD_STR(users, key, s ); + break; + } + } + + s = (struct my_struct*)malloc(sizeof(struct my_struct)); + strncpy(s->key, "sock_id", 64); + snprintf(s->val,64, "%d", sock_id); + HASH_ADD_STR(users, key, s); +} + +// +//Create Server and listen for client connections. +// +static int create_server(int port_number,int max_connections) +{ + int sockfd, reuse = 1; + struct sockaddr_in serv_addr; + + sockfd = socket(AF_INET, SOCK_STREAM, 0); + + if (sockfd < 0) + { + fprintf(stderr, "%s- Error: in opening socket on port %d\n", + __progname, port_number); + exit(1); + } + +/* 20.Mar.2017 - RM - SO_REUSEADDR option. To take care of TIME_WAIT state.*/ + int ret = setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &reuse, sizeof(int)); + if (ret < 0) + { + syslog(LOG_ERR, "create_server:setsockopt() failed...."); + } + + bzero((char *) &serv_addr, sizeof(serv_addr)); + serv_addr.sin_family = AF_INET; + serv_addr.sin_addr.s_addr = INADDR_ANY; + serv_addr.sin_port = htons(port_number); + + if (bind(sockfd, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) + { + fprintf(stderr,"%s- Error: could not bind socket to port %d\n", + __progname, port_number); + syslog(LOG_ERR, "Error: could not bind socket to port %d", port_number); + + close(sockfd); + + exit(1); + } + + // Start listening on the server. + listen(sockfd, max_connections); + + return sockfd; +} + +// The server to wait (non-blocking) for a client connection. +static int connect_to_client(int server_fd) +{ + int ret_val = 1; + int newsockfd = -1; + socklen_t clilen; + struct sockaddr_in cli_addr; + fd_set c_set; + struct timeval time_limit; + + time_limit.tv_sec = 0; + time_limit.tv_usec = 1000; + + clilen = sizeof(cli_addr); + + FD_ZERO(&c_set); + FD_SET(server_fd, &c_set); + + select(server_fd + 1, &c_set, NULL, NULL, &time_limit); + + ret_val = FD_ISSET(server_fd, &c_set); + + if(ret_val) + { + newsockfd = accept(server_fd, (struct sockaddr *) &cli_addr, &clilen); + if (newsockfd >= 0) + { + syslog(LOG_INFO, "SRV:%d New Client Connection CLT:%d", server_fd, newsockfd); + } + else + { + syslog(LOG_ERR,"Error: failed in accept(), socket=%d", server_fd); + exit(1); + } + } + + return(newsockfd); +} + +// +// Check if we can read from the socket.. +// +static int can_read_from_socket(int socket_id) +{ + struct timeval time_limit; + time_limit.tv_sec = 0; + time_limit.tv_usec = 1000; + + fd_set c_set; + FD_ZERO(&c_set); + FD_SET(socket_id, &c_set); + + int npending = select(socket_id + 1, &c_set, NULL, NULL, &time_limit); + if (npending == -1) + { + npending = errno; + syslog(LOG_ERR, "can_read_from_socket:select() ERRNO=%d",npending); + return(-100); + } + return(FD_ISSET(socket_id, &c_set)); +} + +// +// Check if we can write to the socket.. +// +static int can_write_to_socket(int socket_id) +{ + struct timeval time_limit; + time_limit.tv_sec = 0; + time_limit.tv_usec = 1000; + + fd_set c_set; + FD_ZERO(&c_set); + FD_SET(socket_id, &c_set); + + int npending = select(socket_id + 1, NULL, &c_set, NULL, &time_limit); + if (npending == -1) + { + npending = errno; + + syslog(LOG_ERR, "can_write_to_socket() select() ERRNO=%d",npending); + + return (-100); + } else if (npending == 0) { // select() timed out... + return(0); + } + return(FD_ISSET(socket_id,&c_set)); +} + +//Receive string from socket and put it inside buffer. +static int receive_string(int sock_id, char* buffer) +{ + int nbytes = 0; + int ret; + + while(1) + { + ret = can_read_from_socket(sock_id); + if (ret == 0) + { // select() had timed out. Retry... + usleep(1000); + continue; + } else + if (ret == -100) + { + return(-1); + } + break; + } + + nbytes = recv(sock_id, buffer, MAX_BUF_SIZE, 0); + if (nbytes < 0) + { + perror("READ FAILURE"); + exit(1); + } + return(nbytes); +} + +static void set_non_blocking(int sock_id) +{ + int x; + x = fcntl(sock_id, F_GETFL, 0); + fcntl(sock_id, F_SETFL, x | O_NONBLOCK); + syslog(LOG_INFO, "Setting server to non blocking state."); +} + +static void Data_Send(int sockid) +{ + static int trnum; + char* out; + + int i; + char colon = ':'; + char semicolon = ';'; + int wrt_retries = 0; + int ret; + + s = NULL; + int found = 0; + + out = calloc(1, 2048); + + for (i=0; i<out_port_num; i++) + { + + found = 0; + + HASH_FIND_STR(users,Out_Port_Array[i],s); + if (strcmp(Out_Port_Array[i], s->key) == 0) + { + found=1; + } + + if(found) + { + strncat(out, s->key, strlen(s->key)); + strncat(out, &colon, 1); + strncat(out, s->val, strlen(s->val)); + strncat(out, &semicolon, 1); + } + else + { + + syslog(LOG_ERR,"The %s's value not found in the table.", + Out_Port_Array[i]); + free(out); + return; + } + + } + + while(1) + { + if (wrt_retries > 2) // 22.Feb.2017 - Kludge + { + free(out); + return; + } + ret = can_write_to_socket(sockid); + if (ret > 0) break; + + if( ret == -100) + { + syslog(LOG_ERR,"Send aborted to CLT:%d buffer:%s ret=%d", + sockid, out,ret); + free(out); + return; + } + else // select() timed out. Retry.... + { + printf("\n Sleep \n"); + usleep(1000); + wrt_retries++; + } + } + + if ((send(sockid, out, strlen(out), 0)) == -1) + { + syslog(LOG_ERR,"Failure sending to CLT:%d buffer:%s", sockid, out); + exit(1); + } + + syslog(LOG_INFO,"SNT:TRNUM:%d to CLT:%d buffer: %s", trnum++, sockid, out); + free(out); + +} + +void Vhpi_Initialize(int sock_port) +{ + DEFAULT_SERVER_PORT = sock_port; + + signal(SIGINT,Vhpi_Exit); + signal(SIGTERM,Vhpi_Exit); + + signal(SIGUSR1, Vhpi_Exit); //10.Mar.2017 - RM + + int try_limit = 100; + + while(try_limit > 0) + { + server_socket_id = create_server(DEFAULT_SERVER_PORT,DEFAULT_MAX_CONNECTIONS); + if(server_socket_id > 0) + { + syslog(LOG_INFO,"Started the server on port %d SRV:%d", + DEFAULT_SERVER_PORT, server_socket_id); + set_non_blocking(server_socket_id); + break; + } + else + { + syslog(LOG_ERR,"Could not start server on port %d,will try again", + DEFAULT_SERVER_PORT); + usleep(1000); + try_limit--; + + if(try_limit==0) + { + syslog(LOG_ERR, + "Error:Tried to start server on port %d, failed..giving up.", + DEFAULT_SERVER_PORT); + exit(1); + } + + } + } + // + //Reading Output Port name and storing in Out_Port_Array; + // + char* line = NULL; + size_t len = 0; + ssize_t read; + char *token; + FILE *fp; + struct timespec ts; + + fp=fopen("connection_info.txt","r"); + if (! fp) + { + syslog(LOG_ERR,"Vhpi_Initialize: Failed to open connection_info.txt. Exiting..."); + exit(1); + } + + line = (char*) malloc(80); + while ((read = getline(&line, &len, fp)) != -1) + { + if (strstr(line,"OUT") != NULL || strstr(line,"out") != NULL ) + { + strtok_r(line, " ",&token); + Out_Port_Array[out_port_num] = line; + out_port_num++; + } + line = (char*) malloc(80); + } + fclose(fp); + + free(line); + + ts.tv_sec = 2; + ts.tv_nsec = 0; + nanosleep(&ts, NULL); + +// 10.Mar.2017 - RM - Create PID file for the test bench. + create_pid_file(sock_port); +} +void Vhpi_Set_Port_Value(char *port_name,char *port_value,int port_width) +{ + + s = (struct my_struct*)malloc(sizeof(struct my_struct)); + strncpy(s->key, port_name,64); + strncpy(s->val,port_value,64); + HASH_ADD_STR( users, key, s ); + +} + +void Vhpi_Get_Port_Value(char* port_name,char* port_value,int port_width) +{ + + HASH_FIND_STR(users,port_name,s); + if(s) + { + snprintf(port_value,sizeof(port_value),"%s",s->val); + + HASH_DEL(users, s); + free(s); + s=NULL; + } +} + +void Vhpi_Listen() +{ + int new_sock; + + while(1) + { + new_sock = connect_to_client(server_socket_id); + if(new_sock > 0) + { + char receive_buffer[MAX_BUF_SIZE]; + int n = receive_string(new_sock, receive_buffer); + if(n > 0) + { + sendto_sock = new_sock; // 22.Feb.2017 - RM - Kludge + syslog(LOG_INFO, "Vhpi_Listen:New socket connection CLT:%d",new_sock); + + printf("\n\n%s\n\n", receive_buffer); + + if(strcmp(receive_buffer, "END")==0) + { + syslog(LOG_INFO, "RCVD:CLOSE REQUEST from CLT:%d", new_sock); + Vhpi_Exit(0); + } + else + { + parse_buffer(new_sock,receive_buffer); + } + break; + } + } + else + { + break; + } + } +} + + +void Vhpi_Send() +{ + int sockid; + char* out; + +// Traverse the list of finished jobs and send out the resulting port values.. +// 22.Feb.2017 - RM - Kludge +// log_server=fopen("server.log","a"); +// fprintf(log_server, "%s Vhpi_Send() called\n", curtim()); + +// fprintf(log_server,"Vhpi_Send()-------------------\n"); +// print_hash_table(); +// fprintf(log_server,"----------------------------------------\n"); +// HASH_FIND_STR(users,"sock_id",s); +// if(s) +// { +// sockid=atoi(s->val); +// } +// else +// { +// fprintf(log_server,"%s Socket id not in table - key=%s val=%s\n", +// curtim(), +// users->key, users->val); +// } +// Data_Send(sockid); + + if (prev_sendto_sock != sendto_sock) + { + Data_Send(sendto_sock); + prev_sendto_sock = sendto_sock; + } +// 22.Feb.2017 End kludge + +} + +void Vhpi_Close() +{ + close(server_socket_id); + syslog(LOG_INFO, "*** Closed VHPI link. ***"); +} + +void Vhpi_Exit(int sig) +{ + Vhpi_Close(); + + // printf("\nVHPI EXIT\n"); + +// 10.Mar.2017 - RM + if (pid_file_created) { + // printf("%s\n", pid_filename); + remove(pid_filename); + } + + syslog(LOG_INFO, "*** Exiting ***"); + + exit(0); +} diff --git a/nghdl/src/ghdlserver/ghdlserver.h b/nghdl/src/ghdlserver/ghdlserver.h new file mode 100644 index 00000000..9dc8afc2 --- /dev/null +++ b/nghdl/src/ghdlserver/ghdlserver.h @@ -0,0 +1,33 @@ +/* 18.Mar.2017 - RM - Cleaned up.*/ + +#include <stdlib.h> +#include <stdint.h> +#include <stdio.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/socket.h> +#include <netinet/in.h> +#include <netdb.h> + +// Should be enough.. +#define MAX_BUF_SIZE 4096 + +//Defualt port number + +//unlikely to have more than 16 active +//threads talking to the TB? +#define DEFAULT_MAX_CONNECTIONS 65535 + +int DEFAULT_SERVER_PORT; + +//Vhpi Functions. +void Vhpi_Initialize(int sock_port); +void Vhpi_Close(); +void Vhpi_Exit(); +void Vhpi_Listen(); +void Vhpi_Send(); +void Vhpi_Set_Port_Value(char* reg_name, char* reg_value, int port_width); +void Vhpi_Get_Port_Value(char* reg_name, char* reg_value, int port_width); + + + diff --git a/nghdl/src/ghdlserver/start_server.sh b/nghdl/src/ghdlserver/start_server.sh new file mode 100755 index 00000000..548d7d76 --- /dev/null +++ b/nghdl/src/ghdlserver/start_server.sh @@ -0,0 +1,10 @@ +#!/bin/sh +gcc -c ghdlserver.c +ghdl -a Utility_Package.vhdl && +ghdl -a Vhpi_Package.vhdl && +ghdl -a inverter.vhdl && +ghdl -a inverter_tb.vhdl && + +ghdl -e -Wl,ghdlserver.o inverter_tb && +./inverter_tb + diff --git a/nghdl/src/ghdlserver/uthash.h b/nghdl/src/ghdlserver/uthash.h new file mode 100644 index 00000000..ae09d9e1 --- /dev/null +++ b/nghdl/src/ghdlserver/uthash.h @@ -0,0 +1,948 @@ +/* +Copyright (c) 2003-2014, Troy D. Hanson http://troydhanson.github.com/uthash/ +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef UTHASH_H +#define UTHASH_H + +#include <string.h> /* memcmp,strlen */ +#include <stddef.h> /* ptrdiff_t */ +#include <stdlib.h> /* exit() */ + +/* These macros use decltype or the earlier __typeof GNU extension. + As decltype is only available in newer compilers (VS2010 or gcc 4.3+ + when compiling c++ source) this code uses whatever method is needed + or, for VS2008 where neither is available, uses casting workarounds. */ +#ifdef _MSC_VER /* MS compiler */ +#if _MSC_VER >= 1600 && defined(__cplusplus) /* VS2010 or newer in C++ mode */ +#define DECLTYPE(x) (decltype(x)) +#else /* VS2008 or older (or VS2010 in C mode) */ +#define NO_DECLTYPE +#define DECLTYPE(x) +#endif +#else /* GNU, Sun and other compilers */ +#define DECLTYPE(x) (__typeof(x)) +#endif + +#ifdef NO_DECLTYPE +#define DECLTYPE_ASSIGN(dst,src) \ +do { \ + char **_da_dst = (char**)(&(dst)); \ + *_da_dst = (char*)(src); \ +} while(0) +#else +#define DECLTYPE_ASSIGN(dst,src) \ +do { \ + (dst) = DECLTYPE(dst)(src); \ +} while(0) +#endif + +/* a number of the hash function use uint32_t which isn't defined on win32 */ +#ifdef _MSC_VER +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +#else +#include <inttypes.h> /* uint32_t */ +#endif + +#define UTHASH_VERSION 1.9.9 + +#ifndef uthash_fatal +#define uthash_fatal(msg) exit(-1) /* fatal error (out of memory,etc) */ +#endif +#ifndef uthash_malloc +#define uthash_malloc(sz) malloc(sz) /* malloc fcn */ +#endif +#ifndef uthash_free +#define uthash_free(ptr,sz) free(ptr) /* free fcn */ +#endif + +#ifndef uthash_noexpand_fyi +#define uthash_noexpand_fyi(tbl) /* can be defined to log noexpand */ +#endif +#ifndef uthash_expand_fyi +#define uthash_expand_fyi(tbl) /* can be defined to log expands */ +#endif + +/* initial number of buckets */ +#define HASH_INITIAL_NUM_BUCKETS 32 /* initial number of buckets */ +#define HASH_INITIAL_NUM_BUCKETS_LOG2 5 /* lg2 of initial number of buckets */ +#define HASH_BKT_CAPACITY_THRESH 10 /* expand when bucket count reaches */ + +/* calculate the element whose hash handle address is hhe */ +#define ELMT_FROM_HH(tbl,hhp) ((void*)(((char*)(hhp)) - ((tbl)->hho))) + +#define HASH_FIND(hh,head,keyptr,keylen,out) \ +do { \ + unsigned _hf_bkt,_hf_hashv; \ + out=NULL; \ + if (head) { \ + HASH_FCN(keyptr,keylen, (head)->hh.tbl->num_buckets, _hf_hashv, _hf_bkt); \ + if (HASH_BLOOM_TEST((head)->hh.tbl, _hf_hashv)) { \ + HASH_FIND_IN_BKT((head)->hh.tbl, hh, (head)->hh.tbl->buckets[ _hf_bkt ], \ + keyptr,keylen,out); \ + } \ + } \ +} while (0) + +#ifdef HASH_BLOOM +#define HASH_BLOOM_BITLEN (1ULL << HASH_BLOOM) +#define HASH_BLOOM_BYTELEN (HASH_BLOOM_BITLEN/8) + ((HASH_BLOOM_BITLEN%8) ? 1:0) +#define HASH_BLOOM_MAKE(tbl) \ +do { \ + (tbl)->bloom_nbits = HASH_BLOOM; \ + (tbl)->bloom_bv = (uint8_t*)uthash_malloc(HASH_BLOOM_BYTELEN); \ + if (!((tbl)->bloom_bv)) { uthash_fatal( "out of memory"); } \ + memset((tbl)->bloom_bv, 0, HASH_BLOOM_BYTELEN); \ + (tbl)->bloom_sig = HASH_BLOOM_SIGNATURE; \ +} while (0) + +#define HASH_BLOOM_FREE(tbl) \ +do { \ + uthash_free((tbl)->bloom_bv, HASH_BLOOM_BYTELEN); \ +} while (0) + +#define HASH_BLOOM_BITSET(bv,idx) (bv[(idx)/8] |= (1U << ((idx)%8))) +#define HASH_BLOOM_BITTEST(bv,idx) (bv[(idx)/8] & (1U << ((idx)%8))) + +#define HASH_BLOOM_ADD(tbl,hashv) \ + HASH_BLOOM_BITSET((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1))) + +#define HASH_BLOOM_TEST(tbl,hashv) \ + HASH_BLOOM_BITTEST((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1))) + +#else +#define HASH_BLOOM_MAKE(tbl) +#define HASH_BLOOM_FREE(tbl) +#define HASH_BLOOM_ADD(tbl,hashv) +#define HASH_BLOOM_TEST(tbl,hashv) (1) +#define HASH_BLOOM_BYTELEN 0 +#endif + +#define HASH_MAKE_TABLE(hh,head) \ +do { \ + (head)->hh.tbl = (UT_hash_table*)uthash_malloc( \ + sizeof(UT_hash_table)); \ + if (!((head)->hh.tbl)) { uthash_fatal( "out of memory"); } \ + memset((head)->hh.tbl, 0, sizeof(UT_hash_table)); \ + (head)->hh.tbl->tail = &((head)->hh); \ + (head)->hh.tbl->num_buckets = HASH_INITIAL_NUM_BUCKETS; \ + (head)->hh.tbl->log2_num_buckets = HASH_INITIAL_NUM_BUCKETS_LOG2; \ + (head)->hh.tbl->hho = (char*)(&(head)->hh) - (char*)(head); \ + (head)->hh.tbl->buckets = (UT_hash_bucket*)uthash_malloc( \ + HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket)); \ + if (! (head)->hh.tbl->buckets) { uthash_fatal( "out of memory"); } \ + memset((head)->hh.tbl->buckets, 0, \ + HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket)); \ + HASH_BLOOM_MAKE((head)->hh.tbl); \ + (head)->hh.tbl->signature = HASH_SIGNATURE; \ +} while(0) + +#define HASH_ADD(hh,head,fieldname,keylen_in,add) \ + HASH_ADD_KEYPTR(hh,head,&((add)->fieldname),keylen_in,add) + +#define HASH_REPLACE(hh,head,fieldname,keylen_in,add,replaced) \ +do { \ + replaced=NULL; \ + HASH_FIND(hh,head,&((add)->fieldname),keylen_in,replaced); \ + if (replaced!=NULL) { \ + HASH_DELETE(hh,head,replaced); \ + }; \ + HASH_ADD(hh,head,fieldname,keylen_in,add); \ +} while(0) + +#define HASH_ADD_KEYPTR(hh,head,keyptr,keylen_in,add) \ +do { \ + unsigned _ha_bkt; \ + (add)->hh.next = NULL; \ + (add)->hh.key = (char*)(keyptr); \ + (add)->hh.keylen = (unsigned)(keylen_in); \ + if (!(head)) { \ + head = (add); \ + (head)->hh.prev = NULL; \ + HASH_MAKE_TABLE(hh,head); \ + } else { \ + (head)->hh.tbl->tail->next = (add); \ + (add)->hh.prev = ELMT_FROM_HH((head)->hh.tbl, (head)->hh.tbl->tail); \ + (head)->hh.tbl->tail = &((add)->hh); \ + } \ + (head)->hh.tbl->num_items++; \ + (add)->hh.tbl = (head)->hh.tbl; \ + HASH_FCN(keyptr,keylen_in, (head)->hh.tbl->num_buckets, \ + (add)->hh.hashv, _ha_bkt); \ + HASH_ADD_TO_BKT((head)->hh.tbl->buckets[_ha_bkt],&(add)->hh); \ + HASH_BLOOM_ADD((head)->hh.tbl,(add)->hh.hashv); \ + HASH_EMIT_KEY(hh,head,keyptr,keylen_in); \ + HASH_FSCK(hh,head); \ +} while(0) + +#define HASH_TO_BKT( hashv, num_bkts, bkt ) \ +do { \ + bkt = ((hashv) & ((num_bkts) - 1)); \ +} while(0) + +/* delete "delptr" from the hash table. + * "the usual" patch-up process for the app-order doubly-linked-list. + * The use of _hd_hh_del below deserves special explanation. + * These used to be expressed using (delptr) but that led to a bug + * if someone used the same symbol for the head and deletee, like + * HASH_DELETE(hh,users,users); + * We want that to work, but by changing the head (users) below + * we were forfeiting our ability to further refer to the deletee (users) + * in the patch-up process. Solution: use scratch space to + * copy the deletee pointer, then the latter references are via that + * scratch pointer rather than through the repointed (users) symbol. + */ +#define HASH_DELETE(hh,head,delptr) \ +do { \ + unsigned _hd_bkt; \ + struct UT_hash_handle *_hd_hh_del; \ + if ( ((delptr)->hh.prev == NULL) && ((delptr)->hh.next == NULL) ) { \ + uthash_free((head)->hh.tbl->buckets, \ + (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \ + HASH_BLOOM_FREE((head)->hh.tbl); \ + uthash_free((head)->hh.tbl, sizeof(UT_hash_table)); \ + head = NULL; \ + } else { \ + _hd_hh_del = &((delptr)->hh); \ + if ((delptr) == ELMT_FROM_HH((head)->hh.tbl,(head)->hh.tbl->tail)) { \ + (head)->hh.tbl->tail = \ + (UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) + \ + (head)->hh.tbl->hho); \ + } \ + if ((delptr)->hh.prev) { \ + ((UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) + \ + (head)->hh.tbl->hho))->next = (delptr)->hh.next; \ + } else { \ + DECLTYPE_ASSIGN(head,(delptr)->hh.next); \ + } \ + if (_hd_hh_del->next) { \ + ((UT_hash_handle*)((ptrdiff_t)_hd_hh_del->next + \ + (head)->hh.tbl->hho))->prev = \ + _hd_hh_del->prev; \ + } \ + HASH_TO_BKT( _hd_hh_del->hashv, (head)->hh.tbl->num_buckets, _hd_bkt); \ + HASH_DEL_IN_BKT(hh,(head)->hh.tbl->buckets[_hd_bkt], _hd_hh_del); \ + (head)->hh.tbl->num_items--; \ + } \ + HASH_FSCK(hh,head); \ +} while (0) + + +/* convenience forms of HASH_FIND/HASH_ADD/HASH_DEL */ +#define HASH_FIND_STR(head,findstr,out) \ + HASH_FIND(hh,head,findstr,strlen(findstr),out) +#define HASH_ADD_STR(head,strfield,add) \ + HASH_ADD(hh,head,strfield[0],strlen(add->strfield),add) +#define HASH_REPLACE_STR(head,strfield,add,replaced) \ + HASH_REPLACE(hh,head,strfield,strlen(add->strfield),add,replaced) +#define HASH_FIND_INT(head,findint,out) \ + HASH_FIND(hh,head,findint,sizeof(int),out) +#define HASH_ADD_INT(head,intfield,add) \ + HASH_ADD(hh,head,intfield,sizeof(int),add) +#define HASH_REPLACE_INT(head,intfield,add,replaced) \ + HASH_REPLACE(hh,head,intfield,sizeof(int),add,replaced) +#define HASH_FIND_PTR(head,findptr,out) \ + HASH_FIND(hh,head,findptr,sizeof(void *),out) +#define HASH_ADD_PTR(head,ptrfield,add) \ + HASH_ADD(hh,head,ptrfield,sizeof(void *),add) +#define HASH_REPLACE_PTR(head,ptrfield,add,replaced) \ + HASH_REPLACE(hh,head,ptrfield,sizeof(void *),add,replaced) +#define HASH_DEL(head,delptr) \ + HASH_DELETE(hh,head,delptr) + +/* HASH_FSCK checks hash integrity on every add/delete when HASH_DEBUG is defined. + * This is for uthash developer only; it compiles away if HASH_DEBUG isn't defined. + */ +#ifdef HASH_DEBUG +#define HASH_OOPS(...) do { fprintf(stderr,__VA_ARGS__); exit(-1); } while (0) +#define HASH_FSCK(hh,head) \ +do { \ + unsigned _bkt_i; \ + unsigned _count, _bkt_count; \ + char *_prev; \ + struct UT_hash_handle *_thh; \ + if (head) { \ + _count = 0; \ + for( _bkt_i = 0; _bkt_i < (head)->hh.tbl->num_buckets; _bkt_i++) { \ + _bkt_count = 0; \ + _thh = (head)->hh.tbl->buckets[_bkt_i].hh_head; \ + _prev = NULL; \ + while (_thh) { \ + if (_prev != (char*)(_thh->hh_prev)) { \ + HASH_OOPS("invalid hh_prev %p, actual %p\n", \ + _thh->hh_prev, _prev ); \ + } \ + _bkt_count++; \ + _prev = (char*)(_thh); \ + _thh = _thh->hh_next; \ + } \ + _count += _bkt_count; \ + if ((head)->hh.tbl->buckets[_bkt_i].count != _bkt_count) { \ + HASH_OOPS("invalid bucket count %d, actual %d\n", \ + (head)->hh.tbl->buckets[_bkt_i].count, _bkt_count); \ + } \ + } \ + if (_count != (head)->hh.tbl->num_items) { \ + HASH_OOPS("invalid hh item count %d, actual %d\n", \ + (head)->hh.tbl->num_items, _count ); \ + } \ + /* traverse hh in app order; check next/prev integrity, count */ \ + _count = 0; \ + _prev = NULL; \ + _thh = &(head)->hh; \ + while (_thh) { \ + _count++; \ + if (_prev !=(char*)(_thh->prev)) { \ + HASH_OOPS("invalid prev %p, actual %p\n", \ + _thh->prev, _prev ); \ + } \ + _prev = (char*)ELMT_FROM_HH((head)->hh.tbl, _thh); \ + _thh = ( _thh->next ? (UT_hash_handle*)((char*)(_thh->next) + \ + (head)->hh.tbl->hho) : NULL ); \ + } \ + if (_count != (head)->hh.tbl->num_items) { \ + HASH_OOPS("invalid app item count %d, actual %d\n", \ + (head)->hh.tbl->num_items, _count ); \ + } \ + } \ +} while (0) +#else +#define HASH_FSCK(hh,head) +#endif + +/* When compiled with -DHASH_EMIT_KEYS, length-prefixed keys are emitted to + * the descriptor to which this macro is defined for tuning the hash function. + * The app can #include <unistd.h> to get the prototype for write(2). */ +#ifdef HASH_EMIT_KEYS +#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen) \ +do { \ + unsigned _klen = fieldlen; \ + write(HASH_EMIT_KEYS, &_klen, sizeof(_klen)); \ + write(HASH_EMIT_KEYS, keyptr, fieldlen); \ +} while (0) +#else +#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen) +#endif + +/* default to Jenkin's hash unless overridden e.g. DHASH_FUNCTION=HASH_SAX */ +#ifdef HASH_FUNCTION +#define HASH_FCN HASH_FUNCTION +#else +#define HASH_FCN HASH_JEN +#endif + +/* The Bernstein hash function, used in Perl prior to v5.6 */ +#define HASH_BER(key,keylen,num_bkts,hashv,bkt) \ +do { \ + unsigned _hb_keylen=keylen; \ + char *_hb_key=(char*)(key); \ + (hashv) = 0; \ + while (_hb_keylen--) { (hashv) = ((hashv) * 33) + *_hb_key++; } \ + bkt = (hashv) & (num_bkts-1); \ +} while (0) + + +/* SAX/FNV/OAT/JEN hash functions are macro variants of those listed at + * http://eternallyconfuzzled.com/tuts/algorithms/jsw_tut_hashing.aspx */ +#define HASH_SAX(key,keylen,num_bkts,hashv,bkt) \ +do { \ + unsigned _sx_i; \ + char *_hs_key=(char*)(key); \ + hashv = 0; \ + for(_sx_i=0; _sx_i < keylen; _sx_i++) \ + hashv ^= (hashv << 5) + (hashv >> 2) + _hs_key[_sx_i]; \ + bkt = hashv & (num_bkts-1); \ +} while (0) + +#define HASH_FNV(key,keylen,num_bkts,hashv,bkt) \ +do { \ + unsigned _fn_i; \ + char *_hf_key=(char*)(key); \ + hashv = 2166136261UL; \ + for(_fn_i=0; _fn_i < keylen; _fn_i++) \ + hashv = (hashv * 16777619) ^ _hf_key[_fn_i]; \ + bkt = hashv & (num_bkts-1); \ +} while(0) + +#define HASH_OAT(key,keylen,num_bkts,hashv,bkt) \ +do { \ + unsigned _ho_i; \ + char *_ho_key=(char*)(key); \ + hashv = 0; \ + for(_ho_i=0; _ho_i < keylen; _ho_i++) { \ + hashv += _ho_key[_ho_i]; \ + hashv += (hashv << 10); \ + hashv ^= (hashv >> 6); \ + } \ + hashv += (hashv << 3); \ + hashv ^= (hashv >> 11); \ + hashv += (hashv << 15); \ + bkt = hashv & (num_bkts-1); \ +} while(0) + +#define HASH_JEN_MIX(a,b,c) \ +do { \ + a -= b; a -= c; a ^= ( c >> 13 ); \ + b -= c; b -= a; b ^= ( a << 8 ); \ + c -= a; c -= b; c ^= ( b >> 13 ); \ + a -= b; a -= c; a ^= ( c >> 12 ); \ + b -= c; b -= a; b ^= ( a << 16 ); \ + c -= a; c -= b; c ^= ( b >> 5 ); \ + a -= b; a -= c; a ^= ( c >> 3 ); \ + b -= c; b -= a; b ^= ( a << 10 ); \ + c -= a; c -= b; c ^= ( b >> 15 ); \ +} while (0) + +#define HASH_JEN(key,keylen,num_bkts,hashv,bkt) \ +do { \ + unsigned _hj_i,_hj_j,_hj_k; \ + unsigned char *_hj_key=(unsigned char*)(key); \ + hashv = 0xfeedbeef; \ + _hj_i = _hj_j = 0x9e3779b9; \ + _hj_k = (unsigned)(keylen); \ + while (_hj_k >= 12) { \ + _hj_i += (_hj_key[0] + ( (unsigned)_hj_key[1] << 8 ) \ + + ( (unsigned)_hj_key[2] << 16 ) \ + + ( (unsigned)_hj_key[3] << 24 ) ); \ + _hj_j += (_hj_key[4] + ( (unsigned)_hj_key[5] << 8 ) \ + + ( (unsigned)_hj_key[6] << 16 ) \ + + ( (unsigned)_hj_key[7] << 24 ) ); \ + hashv += (_hj_key[8] + ( (unsigned)_hj_key[9] << 8 ) \ + + ( (unsigned)_hj_key[10] << 16 ) \ + + ( (unsigned)_hj_key[11] << 24 ) ); \ + \ + HASH_JEN_MIX(_hj_i, _hj_j, hashv); \ + \ + _hj_key += 12; \ + _hj_k -= 12; \ + } \ + hashv += keylen; \ + switch ( _hj_k ) { \ + case 11: hashv += ( (unsigned)_hj_key[10] << 24 ); \ + case 10: hashv += ( (unsigned)_hj_key[9] << 16 ); \ + case 9: hashv += ( (unsigned)_hj_key[8] << 8 ); \ + case 8: _hj_j += ( (unsigned)_hj_key[7] << 24 ); \ + case 7: _hj_j += ( (unsigned)_hj_key[6] << 16 ); \ + case 6: _hj_j += ( (unsigned)_hj_key[5] << 8 ); \ + case 5: _hj_j += _hj_key[4]; \ + case 4: _hj_i += ( (unsigned)_hj_key[3] << 24 ); \ + case 3: _hj_i += ( (unsigned)_hj_key[2] << 16 ); \ + case 2: _hj_i += ( (unsigned)_hj_key[1] << 8 ); \ + case 1: _hj_i += _hj_key[0]; \ + } \ + HASH_JEN_MIX(_hj_i, _hj_j, hashv); \ + bkt = hashv & (num_bkts-1); \ +} while(0) + +/* The Paul Hsieh hash function */ +#undef get16bits +#if (defined(__GNUC__) && defined(__i386__)) || defined(__WATCOMC__) \ + || defined(_MSC_VER) || defined (__BORLANDC__) || defined (__TURBOC__) +#define get16bits(d) (*((const uint16_t *) (d))) +#endif + +#if !defined (get16bits) +#define get16bits(d) ((((uint32_t)(((const uint8_t *)(d))[1])) << 8) \ + +(uint32_t)(((const uint8_t *)(d))[0]) ) +#endif +#define HASH_SFH(key,keylen,num_bkts,hashv,bkt) \ +do { \ + unsigned char *_sfh_key=(unsigned char*)(key); \ + uint32_t _sfh_tmp, _sfh_len = keylen; \ + \ + int _sfh_rem = _sfh_len & 3; \ + _sfh_len >>= 2; \ + hashv = 0xcafebabe; \ + \ + /* Main loop */ \ + for (;_sfh_len > 0; _sfh_len--) { \ + hashv += get16bits (_sfh_key); \ + _sfh_tmp = (uint32_t)(get16bits (_sfh_key+2)) << 11 ^ hashv; \ + hashv = (hashv << 16) ^ _sfh_tmp; \ + _sfh_key += 2*sizeof (uint16_t); \ + hashv += hashv >> 11; \ + } \ + \ + /* Handle end cases */ \ + switch (_sfh_rem) { \ + case 3: hashv += get16bits (_sfh_key); \ + hashv ^= hashv << 16; \ + hashv ^= (uint32_t)(_sfh_key[sizeof (uint16_t)] << 18); \ + hashv += hashv >> 11; \ + break; \ + case 2: hashv += get16bits (_sfh_key); \ + hashv ^= hashv << 11; \ + hashv += hashv >> 17; \ + break; \ + case 1: hashv += *_sfh_key; \ + hashv ^= hashv << 10; \ + hashv += hashv >> 1; \ + } \ + \ + /* Force "avalanching" of final 127 bits */ \ + hashv ^= hashv << 3; \ + hashv += hashv >> 5; \ + hashv ^= hashv << 4; \ + hashv += hashv >> 17; \ + hashv ^= hashv << 25; \ + hashv += hashv >> 6; \ + bkt = hashv & (num_bkts-1); \ +} while(0) + +#ifdef HASH_USING_NO_STRICT_ALIASING +/* The MurmurHash exploits some CPU's (x86,x86_64) tolerance for unaligned reads. + * For other types of CPU's (e.g. Sparc) an unaligned read causes a bus error. + * MurmurHash uses the faster approach only on CPU's where we know it's safe. + * + * Note the preprocessor built-in defines can be emitted using: + * + * gcc -m64 -dM -E - < /dev/null (on gcc) + * cc -## a.c (where a.c is a simple test file) (Sun Studio) + */ +#if (defined(__i386__) || defined(__x86_64__) || defined(_M_IX86)) +#define MUR_GETBLOCK(p,i) p[i] +#else /* non intel */ +#define MUR_PLUS0_ALIGNED(p) (((unsigned long)p & 0x3) == 0) +#define MUR_PLUS1_ALIGNED(p) (((unsigned long)p & 0x3) == 1) +#define MUR_PLUS2_ALIGNED(p) (((unsigned long)p & 0x3) == 2) +#define MUR_PLUS3_ALIGNED(p) (((unsigned long)p & 0x3) == 3) +#define WP(p) ((uint32_t*)((unsigned long)(p) & ~3UL)) +#if (defined(__BIG_ENDIAN__) || defined(SPARC) || defined(__ppc__) || defined(__ppc64__)) +#define MUR_THREE_ONE(p) ((((*WP(p))&0x00ffffff) << 8) | (((*(WP(p)+1))&0xff000000) >> 24)) +#define MUR_TWO_TWO(p) ((((*WP(p))&0x0000ffff) <<16) | (((*(WP(p)+1))&0xffff0000) >> 16)) +#define MUR_ONE_THREE(p) ((((*WP(p))&0x000000ff) <<24) | (((*(WP(p)+1))&0xffffff00) >> 8)) +#else /* assume little endian non-intel */ +#define MUR_THREE_ONE(p) ((((*WP(p))&0xffffff00) >> 8) | (((*(WP(p)+1))&0x000000ff) << 24)) +#define MUR_TWO_TWO(p) ((((*WP(p))&0xffff0000) >>16) | (((*(WP(p)+1))&0x0000ffff) << 16)) +#define MUR_ONE_THREE(p) ((((*WP(p))&0xff000000) >>24) | (((*(WP(p)+1))&0x00ffffff) << 8)) +#endif +#define MUR_GETBLOCK(p,i) (MUR_PLUS0_ALIGNED(p) ? ((p)[i]) : \ + (MUR_PLUS1_ALIGNED(p) ? MUR_THREE_ONE(p) : \ + (MUR_PLUS2_ALIGNED(p) ? MUR_TWO_TWO(p) : \ + MUR_ONE_THREE(p)))) +#endif +#define MUR_ROTL32(x,r) (((x) << (r)) | ((x) >> (32 - (r)))) +#define MUR_FMIX(_h) \ +do { \ + _h ^= _h >> 16; \ + _h *= 0x85ebca6b; \ + _h ^= _h >> 13; \ + _h *= 0xc2b2ae35l; \ + _h ^= _h >> 16; \ +} while(0) + +#define HASH_MUR(key,keylen,num_bkts,hashv,bkt) \ +do { \ + const uint8_t *_mur_data = (const uint8_t*)(key); \ + const int _mur_nblocks = (keylen) / 4; \ + uint32_t _mur_h1 = 0xf88D5353; \ + uint32_t _mur_c1 = 0xcc9e2d51; \ + uint32_t _mur_c2 = 0x1b873593; \ + uint32_t _mur_k1 = 0; \ + const uint8_t *_mur_tail; \ + const uint32_t *_mur_blocks = (const uint32_t*)(_mur_data+_mur_nblocks*4); \ + int _mur_i; \ + for(_mur_i = -_mur_nblocks; _mur_i; _mur_i++) { \ + _mur_k1 = MUR_GETBLOCK(_mur_blocks,_mur_i); \ + _mur_k1 *= _mur_c1; \ + _mur_k1 = MUR_ROTL32(_mur_k1,15); \ + _mur_k1 *= _mur_c2; \ + \ + _mur_h1 ^= _mur_k1; \ + _mur_h1 = MUR_ROTL32(_mur_h1,13); \ + _mur_h1 = _mur_h1*5+0xe6546b64; \ + } \ + _mur_tail = (const uint8_t*)(_mur_data + _mur_nblocks*4); \ + _mur_k1=0; \ + switch((keylen) & 3) { \ + case 3: _mur_k1 ^= _mur_tail[2] << 16; \ + case 2: _mur_k1 ^= _mur_tail[1] << 8; \ + case 1: _mur_k1 ^= _mur_tail[0]; \ + _mur_k1 *= _mur_c1; \ + _mur_k1 = MUR_ROTL32(_mur_k1,15); \ + _mur_k1 *= _mur_c2; \ + _mur_h1 ^= _mur_k1; \ + } \ + _mur_h1 ^= (keylen); \ + MUR_FMIX(_mur_h1); \ + hashv = _mur_h1; \ + bkt = hashv & (num_bkts-1); \ +} while(0) +#endif /* HASH_USING_NO_STRICT_ALIASING */ + +/* key comparison function; return 0 if keys equal */ +#define HASH_KEYCMP(a,b,len) memcmp(a,b,len) + +/* iterate over items in a known bucket to find desired item */ +#define HASH_FIND_IN_BKT(tbl,hh,head,keyptr,keylen_in,out) \ +do { \ + if (head.hh_head) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,head.hh_head)); \ + else out=NULL; \ + while (out) { \ + if ((out)->hh.keylen == keylen_in) { \ + if ((HASH_KEYCMP((out)->hh.key,keyptr,keylen_in)) == 0) break; \ + } \ + if ((out)->hh.hh_next) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,(out)->hh.hh_next)); \ + else out = NULL; \ + } \ +} while(0) + +/* add an item to a bucket */ +#define HASH_ADD_TO_BKT(head,addhh) \ +do { \ + head.count++; \ + (addhh)->hh_next = head.hh_head; \ + (addhh)->hh_prev = NULL; \ + if (head.hh_head) { (head).hh_head->hh_prev = (addhh); } \ + (head).hh_head=addhh; \ + if (head.count >= ((head.expand_mult+1) * HASH_BKT_CAPACITY_THRESH) \ + && (addhh)->tbl->noexpand != 1) { \ + HASH_EXPAND_BUCKETS((addhh)->tbl); \ + } \ +} while(0) + +/* remove an item from a given bucket */ +#define HASH_DEL_IN_BKT(hh,head,hh_del) \ + (head).count--; \ + if ((head).hh_head == hh_del) { \ + (head).hh_head = hh_del->hh_next; \ + } \ + if (hh_del->hh_prev) { \ + hh_del->hh_prev->hh_next = hh_del->hh_next; \ + } \ + if (hh_del->hh_next) { \ + hh_del->hh_next->hh_prev = hh_del->hh_prev; \ + } + +/* Bucket expansion has the effect of doubling the number of buckets + * and redistributing the items into the new buckets. Ideally the + * items will distribute more or less evenly into the new buckets + * (the extent to which this is true is a measure of the quality of + * the hash function as it applies to the key domain). + * + * With the items distributed into more buckets, the chain length + * (item count) in each bucket is reduced. Thus by expanding buckets + * the hash keeps a bound on the chain length. This bounded chain + * length is the essence of how a hash provides constant time lookup. + * + * The calculation of tbl->ideal_chain_maxlen below deserves some + * explanation. First, keep in mind that we're calculating the ideal + * maximum chain length based on the *new* (doubled) bucket count. + * In fractions this is just n/b (n=number of items,b=new num buckets). + * Since the ideal chain length is an integer, we want to calculate + * ceil(n/b). We don't depend on floating point arithmetic in this + * hash, so to calculate ceil(n/b) with integers we could write + * + * ceil(n/b) = (n/b) + ((n%b)?1:0) + * + * and in fact a previous version of this hash did just that. + * But now we have improved things a bit by recognizing that b is + * always a power of two. We keep its base 2 log handy (call it lb), + * so now we can write this with a bit shift and logical AND: + * + * ceil(n/b) = (n>>lb) + ( (n & (b-1)) ? 1:0) + * + */ +#define HASH_EXPAND_BUCKETS(tbl) \ +do { \ + unsigned _he_bkt; \ + unsigned _he_bkt_i; \ + struct UT_hash_handle *_he_thh, *_he_hh_nxt; \ + UT_hash_bucket *_he_new_buckets, *_he_newbkt; \ + _he_new_buckets = (UT_hash_bucket*)uthash_malloc( \ + 2 * tbl->num_buckets * sizeof(struct UT_hash_bucket)); \ + if (!_he_new_buckets) { uthash_fatal( "out of memory"); } \ + memset(_he_new_buckets, 0, \ + 2 * tbl->num_buckets * sizeof(struct UT_hash_bucket)); \ + tbl->ideal_chain_maxlen = \ + (tbl->num_items >> (tbl->log2_num_buckets+1)) + \ + ((tbl->num_items & ((tbl->num_buckets*2)-1)) ? 1 : 0); \ + tbl->nonideal_items = 0; \ + for(_he_bkt_i = 0; _he_bkt_i < tbl->num_buckets; _he_bkt_i++) \ + { \ + _he_thh = tbl->buckets[ _he_bkt_i ].hh_head; \ + while (_he_thh) { \ + _he_hh_nxt = _he_thh->hh_next; \ + HASH_TO_BKT( _he_thh->hashv, tbl->num_buckets*2, _he_bkt); \ + _he_newbkt = &(_he_new_buckets[ _he_bkt ]); \ + if (++(_he_newbkt->count) > tbl->ideal_chain_maxlen) { \ + tbl->nonideal_items++; \ + _he_newbkt->expand_mult = _he_newbkt->count / \ + tbl->ideal_chain_maxlen; \ + } \ + _he_thh->hh_prev = NULL; \ + _he_thh->hh_next = _he_newbkt->hh_head; \ + if (_he_newbkt->hh_head) _he_newbkt->hh_head->hh_prev = \ + _he_thh; \ + _he_newbkt->hh_head = _he_thh; \ + _he_thh = _he_hh_nxt; \ + } \ + } \ + uthash_free( tbl->buckets, tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \ + tbl->num_buckets *= 2; \ + tbl->log2_num_buckets++; \ + tbl->buckets = _he_new_buckets; \ + tbl->ineff_expands = (tbl->nonideal_items > (tbl->num_items >> 1)) ? \ + (tbl->ineff_expands+1) : 0; \ + if (tbl->ineff_expands > 1) { \ + tbl->noexpand=1; \ + uthash_noexpand_fyi(tbl); \ + } \ + uthash_expand_fyi(tbl); \ +} while(0) + + +/* This is an adaptation of Simon Tatham's O(n log(n)) mergesort */ +/* Note that HASH_SORT assumes the hash handle name to be hh. + * HASH_SRT was added to allow the hash handle name to be passed in. */ +#define HASH_SORT(head,cmpfcn) HASH_SRT(hh,head,cmpfcn) +#define HASH_SRT(hh,head,cmpfcn) \ +do { \ + unsigned _hs_i; \ + unsigned _hs_looping,_hs_nmerges,_hs_insize,_hs_psize,_hs_qsize; \ + struct UT_hash_handle *_hs_p, *_hs_q, *_hs_e, *_hs_list, *_hs_tail; \ + if (head) { \ + _hs_insize = 1; \ + _hs_looping = 1; \ + _hs_list = &((head)->hh); \ + while (_hs_looping) { \ + _hs_p = _hs_list; \ + _hs_list = NULL; \ + _hs_tail = NULL; \ + _hs_nmerges = 0; \ + while (_hs_p) { \ + _hs_nmerges++; \ + _hs_q = _hs_p; \ + _hs_psize = 0; \ + for ( _hs_i = 0; _hs_i < _hs_insize; _hs_i++ ) { \ + _hs_psize++; \ + _hs_q = (UT_hash_handle*)((_hs_q->next) ? \ + ((void*)((char*)(_hs_q->next) + \ + (head)->hh.tbl->hho)) : NULL); \ + if (! (_hs_q) ) break; \ + } \ + _hs_qsize = _hs_insize; \ + while ((_hs_psize > 0) || ((_hs_qsize > 0) && _hs_q )) { \ + if (_hs_psize == 0) { \ + _hs_e = _hs_q; \ + _hs_q = (UT_hash_handle*)((_hs_q->next) ? \ + ((void*)((char*)(_hs_q->next) + \ + (head)->hh.tbl->hho)) : NULL); \ + _hs_qsize--; \ + } else if ( (_hs_qsize == 0) || !(_hs_q) ) { \ + _hs_e = _hs_p; \ + if (_hs_p){ \ + _hs_p = (UT_hash_handle*)((_hs_p->next) ? \ + ((void*)((char*)(_hs_p->next) + \ + (head)->hh.tbl->hho)) : NULL); \ + } \ + _hs_psize--; \ + } else if (( \ + cmpfcn(DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_p)), \ + DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_q))) \ + ) <= 0) { \ + _hs_e = _hs_p; \ + if (_hs_p){ \ + _hs_p = (UT_hash_handle*)((_hs_p->next) ? \ + ((void*)((char*)(_hs_p->next) + \ + (head)->hh.tbl->hho)) : NULL); \ + } \ + _hs_psize--; \ + } else { \ + _hs_e = _hs_q; \ + _hs_q = (UT_hash_handle*)((_hs_q->next) ? \ + ((void*)((char*)(_hs_q->next) + \ + (head)->hh.tbl->hho)) : NULL); \ + _hs_qsize--; \ + } \ + if ( _hs_tail ) { \ + _hs_tail->next = ((_hs_e) ? \ + ELMT_FROM_HH((head)->hh.tbl,_hs_e) : NULL); \ + } else { \ + _hs_list = _hs_e; \ + } \ + if (_hs_e) { \ + _hs_e->prev = ((_hs_tail) ? \ + ELMT_FROM_HH((head)->hh.tbl,_hs_tail) : NULL); \ + } \ + _hs_tail = _hs_e; \ + } \ + _hs_p = _hs_q; \ + } \ + if (_hs_tail){ \ + _hs_tail->next = NULL; \ + } \ + if ( _hs_nmerges <= 1 ) { \ + _hs_looping=0; \ + (head)->hh.tbl->tail = _hs_tail; \ + DECLTYPE_ASSIGN(head,ELMT_FROM_HH((head)->hh.tbl, _hs_list)); \ + } \ + _hs_insize *= 2; \ + } \ + HASH_FSCK(hh,head); \ + } \ +} while (0) + +/* This function selects items from one hash into another hash. + * The end result is that the selected items have dual presence + * in both hashes. There is no copy of the items made; rather + * they are added into the new hash through a secondary hash + * hash handle that must be present in the structure. */ +#define HASH_SELECT(hh_dst, dst, hh_src, src, cond) \ +do { \ + unsigned _src_bkt, _dst_bkt; \ + void *_last_elt=NULL, *_elt; \ + UT_hash_handle *_src_hh, *_dst_hh, *_last_elt_hh=NULL; \ + ptrdiff_t _dst_hho = ((char*)(&(dst)->hh_dst) - (char*)(dst)); \ + if (src) { \ + for(_src_bkt=0; _src_bkt < (src)->hh_src.tbl->num_buckets; _src_bkt++) { \ + for(_src_hh = (src)->hh_src.tbl->buckets[_src_bkt].hh_head; \ + _src_hh; \ + _src_hh = _src_hh->hh_next) { \ + _elt = ELMT_FROM_HH((src)->hh_src.tbl, _src_hh); \ + if (cond(_elt)) { \ + _dst_hh = (UT_hash_handle*)(((char*)_elt) + _dst_hho); \ + _dst_hh->key = _src_hh->key; \ + _dst_hh->keylen = _src_hh->keylen; \ + _dst_hh->hashv = _src_hh->hashv; \ + _dst_hh->prev = _last_elt; \ + _dst_hh->next = NULL; \ + if (_last_elt_hh) { _last_elt_hh->next = _elt; } \ + if (!dst) { \ + DECLTYPE_ASSIGN(dst,_elt); \ + HASH_MAKE_TABLE(hh_dst,dst); \ + } else { \ + _dst_hh->tbl = (dst)->hh_dst.tbl; \ + } \ + HASH_TO_BKT(_dst_hh->hashv, _dst_hh->tbl->num_buckets, _dst_bkt); \ + HASH_ADD_TO_BKT(_dst_hh->tbl->buckets[_dst_bkt],_dst_hh); \ + (dst)->hh_dst.tbl->num_items++; \ + _last_elt = _elt; \ + _last_elt_hh = _dst_hh; \ + } \ + } \ + } \ + } \ + HASH_FSCK(hh_dst,dst); \ +} while (0) + +#define HASH_CLEAR(hh,head) \ +do { \ + if (head) { \ + uthash_free((head)->hh.tbl->buckets, \ + (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket)); \ + HASH_BLOOM_FREE((head)->hh.tbl); \ + uthash_free((head)->hh.tbl, sizeof(UT_hash_table)); \ + (head)=NULL; \ + } \ +} while(0) + +#define HASH_OVERHEAD(hh,head) \ + (size_t)((((head)->hh.tbl->num_items * sizeof(UT_hash_handle)) + \ + ((head)->hh.tbl->num_buckets * sizeof(UT_hash_bucket)) + \ + (sizeof(UT_hash_table)) + \ + (HASH_BLOOM_BYTELEN))) + +#ifdef NO_DECLTYPE +#define HASH_ITER(hh,head,el,tmp) \ +for((el)=(head), (*(char**)(&(tmp)))=(char*)((head)?(head)->hh.next:NULL); \ + el; (el)=(tmp),(*(char**)(&(tmp)))=(char*)((tmp)?(tmp)->hh.next:NULL)) +#else +#define HASH_ITER(hh,head,el,tmp) \ +for((el)=(head),(tmp)=DECLTYPE(el)((head)?(head)->hh.next:NULL); \ + el; (el)=(tmp),(tmp)=DECLTYPE(el)((tmp)?(tmp)->hh.next:NULL)) +#endif + +/* obtain a count of items in the hash */ +#define HASH_COUNT(head) HASH_CNT(hh,head) +#define HASH_CNT(hh,head) ((head)?((head)->hh.tbl->num_items):0) + +typedef struct UT_hash_bucket { + struct UT_hash_handle *hh_head; + unsigned count; + + /* expand_mult is normally set to 0. In this situation, the max chain length + * threshold is enforced at its default value, HASH_BKT_CAPACITY_THRESH. (If + * the bucket's chain exceeds this length, bucket expansion is triggered). + * However, setting expand_mult to a non-zero value delays bucket expansion + * (that would be triggered by additions to this particular bucket) + * until its chain length reaches a *multiple* of HASH_BKT_CAPACITY_THRESH. + * (The multiplier is simply expand_mult+1). The whole idea of this + * multiplier is to reduce bucket expansions, since they are expensive, in + * situations where we know that a particular bucket tends to be overused. + * It is better to let its chain length grow to a longer yet-still-bounded + * value, than to do an O(n) bucket expansion too often. + */ + unsigned expand_mult; + +} UT_hash_bucket; + +/* random signature used only to find hash tables in external analysis */ +#define HASH_SIGNATURE 0xa0111fe1 +#define HASH_BLOOM_SIGNATURE 0xb12220f2 + +typedef struct UT_hash_table { + UT_hash_bucket *buckets; + unsigned num_buckets, log2_num_buckets; + unsigned num_items; + struct UT_hash_handle *tail; /* tail hh in app order, for fast append */ + ptrdiff_t hho; /* hash handle offset (byte pos of hash handle in element */ + + /* in an ideal situation (all buckets used equally), no bucket would have + * more than ceil(#items/#buckets) items. that's the ideal chain length. */ + unsigned ideal_chain_maxlen; + + /* nonideal_items is the number of items in the hash whose chain position + * exceeds the ideal chain maxlen. these items pay the penalty for an uneven + * hash distribution; reaching them in a chain traversal takes >ideal steps */ + unsigned nonideal_items; + + /* ineffective expands occur when a bucket doubling was performed, but + * afterward, more than half the items in the hash had nonideal chain + * positions. If this happens on two consecutive expansions we inhibit any + * further expansion, as it's not helping; this happens when the hash + * function isn't a good fit for the key domain. When expansion is inhibited + * the hash will still work, albeit no longer in constant time. */ + unsigned ineff_expands, noexpand; + + uint32_t signature; /* used only to find hash tables in external analysis */ +#ifdef HASH_BLOOM + uint32_t bloom_sig; /* used only to test bloom exists in external analysis */ + uint8_t *bloom_bv; + char bloom_nbits; +#endif + +} UT_hash_table; + +typedef struct UT_hash_handle { + struct UT_hash_table *tbl; + void *prev; /* prev element in app order */ + void *next; /* next element in app order */ + struct UT_hash_handle *hh_prev; /* previous hh in bucket order */ + struct UT_hash_handle *hh_next; /* next hh in bucket order */ + void *key; /* ptr to enclosing struct's key */ + unsigned keylen; /* enclosing struct's key len */ + unsigned hashv; /* result of hash-fcn(key) */ +} UT_hash_handle; + +#endif /* UTHASH_H */ diff --git a/nghdl/src/model_generation.py b/nghdl/src/model_generation.py new file mode 100644 index 00000000..772cbb52 --- /dev/null +++ b/nghdl/src/model_generation.py @@ -0,0 +1,845 @@ +#!/usr/bin/env python + +"""#!/usr/bin/python """ +import re +import sys +import os + +#######Script start from here +print "Arguement is :", sys.argv[1] +fname = os.path.basename(sys.argv[1]) +print "VHDL filename is :",fname +home = os.path.expanduser("~") +###########Creating connection_info.txt file from vhdl file##################### +read_vhdl = open(sys.argv[1],'r') +vhdl_data = read_vhdl.readlines() +read_vhdl.close() + +start_flag = -1 #Used for scaning part of data +scan_data=[] +#p=re.search('port(.*?)end',read_vhdl,re.M|re.I|re.DOTALL).group() + +for item in vhdl_data: + if re.search('port',item,re.I): + start_flag = 1 + + elif re.search("end",item,re.I): + start_flag = 0 + else: + pass + + if start_flag == 1: + item=re.sub("port", " ", item, flags=re.I) + item=re.sub("\(", " ", item, flags=re.I) + item=re.sub("\)", " ", item, flags=re.I) + item=re.sub(";"," ",item,flags=re.I) + + scan_data.append(item.rstrip()) + scan_data=filter(None, scan_data) + elif start_flag == 0: + break + +#print "Scan Data",scan_data +port_info=[] +port_vector_info = [] + +for item in scan_data: + print "Scan Data :",item + if re.search("in",item,flags=re.I): + if re.search("std_logic_vector",item,flags=re.I): + temp=re.compile(r"\s*std_logic_vector\s*",flags=re.I) + elif re.search("std_logic",item,flags=re.I): + temp=re.compile(r"\s*std_logic\s*",flags=re.I) + else: + print "Please check your vhdl code for datatype of input port" + sys.exit() + elif re.search("out",item,flags=re.I): + if re.search("std_logic_vector",item,flags=re.I): + temp=re.compile(r"\s*std_logic_vector\s*",flags=re.I) + elif re.search("std_logic",item,flags=re.I): + temp=re.compile(r"\s*std_logic\s*",flags=re.I) + else: + print "Please check your vhdl code for datatype of output port" + sys.exit() + else: + print "Please check the in/out direction of your port" + sys.exit() + + lhs=temp.split(item)[0] + rhs=temp.split(item)[1] + bit_info=re.compile(r"\s*downto\s*",flags=re.I).split(rhs)[0] + if bit_info: + port_info.append(lhs+":"+str(int(bit_info)+int(1))) + port_vector_info.append(1) + else: + port_info.append(lhs+":"+str(int(1))) + port_vector_info.append(0) + +print "Port Info :",port_info + +#Open connection_info.txt file + +con_ifo=open('connection_info.txt','w') + +for item in port_info: + word=item.split(':') + con_ifo.write(word[0].strip()+' '+word[1].strip()+' '+word[2].strip()) + con_ifo.write("\n") +con_ifo.close() +############### Reading connection/port information############################# + +#Declaring input and output list +input_list=[] +output_list=[] + +#Reading connection_info.txt file for port infomation +read_file=open('connection_info.txt','r') +data=read_file.readlines() +read_file.close() + +#Extracting input and output port list from data +print "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx" +for line in data: + print line + if re.match(r'^\s*$', line): + pass + #print "Blank Line" + else: + in_items=re.findall("IN",line,re.MULTILINE|re.IGNORECASE) + out_items=re.findall("OUT",line,re.MULTILINE|re.IGNORECASE) + #print "Line",line + if in_items: + input_list.append(line.split()) + #print "Found IN" + else: + pass + #print "Not Found" + + if out_items: + output_list.append(line.split()) + #print "Found Out" + else: + pass + +print "Inout List :",input_list +print "Output list",output_list +input_port=[] +output_port=[] +#creating list of input and output port with its weight +for input in input_list: + input_port.append(input[0]+":"+input[2]) + #print "Input List: ",input +for output in output_list: + output_port.append(output[0]+":"+output[2]) + #print "Output List: ",output + +print "Output Port List : ",output_port +print "Input Port List : ",input_port + +######################Creating content for cfunc.mod file####################### +print "Starting With cfunc.mod file" +cfunc=open('cfunc.mod','w') + +print "Building content for cfunc.mod file" + +comment='''/* This is cfunc.mod file auto generated by gen_con_info.py +Developed by Fahim at IIT Bombay */ \n + ''' + +header=''' +#include <stdio.h> +#include <math.h> +#include <string.h> +#include <time.h> +#include <sys/socket.h> +#include <sys/types.h> +#include <netinet/in.h> +#include <netdb.h> +#include <stdlib.h> +#include <unistd.h> +#include <errno.h> +''' + +function_open='''void cm_'''+fname.split('.')[0]+'''(ARGS) \n{''' + +digital_state_output=[] +for item in output_port: + digital_state_output.append("Digital_State_t *_op_"+item.split(':')[0]+", *_op_"+item.split(':')[0]+"_old;") + + +var_section=''' + // Declaring components of Client + static int flag=0; + FILE *log_client = NULL; + log_client=fopen("client.log","a"); + int socket_fd, bytes_recieved; + char send_data[1024]; + char recv_data[1024]; + char *key_iter; + struct hostent *host; + struct sockaddr_in server_addr; + double time_limit = PARAM(stop_time); + int sock_port = 5000+PARAM(instance_id); +''' +temp_input_var=[] +for item in input_port: + temp_input_var.append("char temp_"+item.split(':')[0]+"[1024];") + +#Start of INIT function +init_start_function=''' + if(INIT) + { + /* Allocate storage for output ports.And set the load for input ports */ +''' + +cm_event_alloc=[] +cm_count_output=0 +for item in output_port: + cm_event_alloc.append("cm_event_alloc("+str(cm_count_output)+","+item.split(':')[1]+"*sizeof(Digital_State_t));") + cm_count_output=cm_count_output+1 + +load_in_port=[] +for item in input_port: + load_in_port.append("for(Ii=0;Ii<PORT_SIZE("+item.split(':')[0]+");Ii++)\n\t\t{\n\t\t\tLOAD("+item.split(':')[0]+"[Ii])=PARAM(input_load); \n\t\t}") + +cm_count_ptr=0 +cm_event_get_ptr=[] +for item in output_port: + cm_event_get_ptr.append("_op_"+item.split(':')[0]+" = _op_"+item.split(':')[0]+"_old = (Digital_State_t *) cm_event_get_ptr("+str(cm_count_ptr)+",0);") + cm_count_ptr=cm_count_ptr+1 + +systime_info=''' + /*Taking system time info for log */ + time_t systime; + systime = time(NULL); + printf(ctime(&systime)); + printf("Client-Initialising ngspice \\n"); + fprintf(log_client,"Setup Client Server Connection at %s \\n",ctime(&systime)); +''' + +init_else=''' + printf("Client-Inside else of INIT \\n"); + fprintf(log_client,"Inside else of INIT \\n"); + /* retrieve storage for output ports. */ +''' + +els_evt_ptr=[] +els_evt_count1=0 +els_evt_count2=0 +for item in output_port: + els_evt_ptr.append("_op_"+item.split(":")[0]+" = cm_event_get_ptr("+str(els_evt_count1)+","+str(els_evt_count2)+");") + els_evt_count2=els_evt_count2+1 + els_evt_ptr.append("_op_"+item.split(":")[0]+"_old"+" = cm_event_get_ptr("+str(els_evt_count1)+","+str(els_evt_count2)+");") + els_evt_count1=els_evt_count1+1 + + +client_setup=''' + /* Client setup */ + //Default hostname assignment + host = gethostbyname("127.0.0.1"); + printf("Client-Creating Client Socket \\n"); + fprintf(log_client,"Creating client socket \\n"); +''' +create_socket=''' + //Creating socket for client + if ((socket_fd = socket(AF_INET, SOCK_STREAM, 0)) == -1) + { + perror("Client-Error while creating client Socket \\n"); + fprintf(log_client,"Error while creating client sockte \\n"); + exit(1); + } + + printf("Client-Client Socket created successfully \\n"); + printf("Client- Socket Id : %d \\n",socket_fd); + fprintf(log_client,"Client-Client Socket created successfully \\n"); + fprintf(log_client,"Client- Socket Id : %d \\n",socket_fd); + + // memset(&server_addr, 0, sizeof(server_addr)); + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(sock_port); + server_addr.sin_addr = *((struct in_addr *)host->h_addr); + bzero(&(server_addr.sin_zero),8); + +''' + +connect_server=''' + printf("Client-Connecting to server \\n"); + fprintf(log_client,"Client-Connecting to server \\n"); + //Conneting to server + + int try_limit=10; + while(try_limit>0) + { + if (connect(socket_fd, (struct sockaddr*)&server_addr,sizeof(struct sockaddr)) == -1) + { + sleep(1); + try_limit--; + if(try_limit==0) + { + fprintf(stderr,"Connect- Error:Tried to connect server on port , failed..giving up \\n"); + fprintf(log_client,"Connect- Error:Tried to connect server on port , failed..giving up \\n"); + exit(1); + } + } + else + { + printf("Client-Connected to server \\n"); + fprintf(log_client,"Client-Connected to server \\n"); + break; + } + } + +''' + +time_limit =''' + if(TIME < time_limit) + { + //Formating data for sending it to client + int Ii; + +''' +#Assign bit value to every input +assign_data_to_input=[] +for item in input_port: + assign_data_to_input.append("\t\t\tfor(Ii=0;Ii<PORT_SIZE("+item.split(':')[0]+");Ii++)\n\ +\t\t\t{\n\t\t\t\tif( INPUT_STATE("+item.split(':')[0]+"[Ii])==ZERO )\n\ +\t\t\t\t{\n\t\t\t\t\ttemp_"+item.split(':')[0]+"[Ii]='0';\n\t\t\t\t}\n\ +\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\ttemp_"+item.split(':')[0]+"[Ii]='1';\n\ +\t\t\t\t}\n\t\t\t}\n\t\t\ttemp_"+item.split(':')[0]+"[Ii]='\\0';\n\n") + + +snprintf_stmt=[] +snprintf_count=0 +snprintf_stmt.append("\t\t\t//Sending and receiving data to-from server \n") +snprintf_stmt.append('\t\t\tsnprintf(send_data,sizeof(send_data),"') +for item in input_port: + snprintf_count=snprintf_count+1 + snprintf_stmt.append(item.split(':')[0]+":%s") + if snprintf_count == len(input_port): + snprintf_stmt.append('",') + internal_count=0 + for item1 in input_port: + if internal_count == len(input_port): + pass + else: + snprintf_stmt.append("temp_"+item1.split(':')[0]) + internal_count=internal_count+1 + if internal_count == len(input_port): + pass + else: + snprintf_stmt.append(",") + snprintf_stmt.append(");") + else: + snprintf_stmt.append(",") + +snprintf_stmt.append('\n\t\t\tprintf("Client-Value of buffer string is %s \\n",send_data);') +snprintf_stmt.append('\n\t\t\tprintf("Client-Sending data to server from client \\n");') + +send_data=''' + + if ( send(socket_fd,send_data,sizeof(send_data),0)==-1) + { + fprintf(stderr, "Client-Failure Sending Message \\n"); + close(socket_fd); + exit(1); + } + else + { + printf("Client-Message being sent: %s \\n",send_data); + fprintf(log_client,"Socket Id : %d & Message sent : %s \\n",socket_fd,send_data); + } + +''' + +recv_data=''' + + bytes_recieved=recv(socket_fd,recv_data,sizeof(recv_data),0); + if ( bytes_recieved <= 0 ) + { + printf("Client-Either Connection Closed or Error \\n"); + exit(1); + } + recv_data[bytes_recieved] = '\\0'; + + printf("Client-Message Received From Server - %s\\n",recv_data); + fprintf(log_client,"Message Received From Server- %s\\n",recv_data); + +''' + +#Scheduling output event + +sch_output_event=[] + +for item in output_port: + sch_output_event.append("\t\t\t/* Scheduling event and processing them */\n\ +\t\t\tif((key_iter=strstr(recv_data, "+'"'+item.split(':')[0]+':"'")) != NULL)\n\ +\t\t\t{\n\ +\t\t\twhile(*key_iter++ != ':');\n\ +\t\t\tfor(Ii=0;*key_iter != ';';Ii++,key_iter++)\n\ +\t\t\t{\n\ +\t\t\t\tprintf(\"Client- Bit val is %c \\n\",*key_iter);\n\ +\t\t\t\tfprintf(log_client,\"Client-Bit val is %c \\n\",*key_iter);\n\ +\t\t\t\tif(*key_iter=='0')\n\t\t\t\t{\n\ +\t\t\t\t\tprintf(\"Client-Zero Received \");\n\ +\t\t\t\t\t_op_"+item.split(':')[0]+"[Ii]=ZERO;\n\t\t\t\t}\n\ +\t\t\t\telse if(*key_iter=='1')\n\t\t\t\t{\n\ +\t\t\t\t\tprintf(\"Client-One Received \\n\");\n\ +\t\t\t\t\t_op_"+item.split(':')[0]+"[Ii]=ONE;\n\ +\t\t\t\t}\n\t\t\t\telse\t\t\t\t{\n\ +\t\t\t\t\tfprintf(log_client,\"Unknow value return from server \\n\");\n\ +\t\t\t\t\tprintf(\"Client-Unknown value return \\n\");\n\t\t\t\t}\n\ +\t\t\t\tif(ANALYSIS == DC)\n\t\t\t\t{\n\ +\t\t\t\t\tOUTPUT_STATE("+item.split(':')[0]+"[Ii]) = _op_"+item.split(':')[0]+"[Ii];\n\ +\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\ +\t\t\t\t\tif(_op_"+item.split(':')[0]+"[Ii] != _op_"+item.split(':')[0]+"_old[Ii])\n\ +\t\t\t\t\t{\n\ +\t\t\t\t\t\tOUTPUT_STATE("+item.split(':')[0]+"[Ii]) = _op_"+item.split(':')[0]+"[Ii];\n\ +\t\t\t\t\t\tOUTPUT_DELAY("+item.split(':')[0]+"[Ii]) = ((_op_"+item.split(':')[0]+"[Ii] == ZERO) ? PARAM(fall_delay) : PARAM(rise_delay));\n\ +\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\ +\t\t\t\t\t\tOUTPUT_CHANGED("+item.split(':')[0]+"[Ii]) = FALSE;\n\t\t\t\t\t}\n\ +\t\t\t\t}\n\t\t\t\tOUTPUT_STRENGTH("+item.split(':')[0]+"[Ii]) = STRONG;\n\ +\t\t\t}\n\ +\t\t\t}\n") + + +els_time_limit=''' + + else + { + char *end_signal="END"; + printf("Closing Ngspice Simulation \\n"); + printf("current time = %g\\n",TIME); + fprintf(log_client,"Times : Closing Socket \\n"); + snprintf(send_data,sizeof(send_data),"%s",end_signal); + printf("Client-Value of buffer string is for END signal is %s \\n",send_data); + printf("Client-Sending data to server from client for end signal \\n"); + + if ( send(socket_fd,send_data,sizeof(send_data),0)==-1) + { + printf("Client-Failure Sending Message for END signal \\n"); + close(socket_fd); + exit(1); + } + else + { + printf("Client-Message being sent for END signal : %s\\n",send_data); + fprintf(log_client,"Socket Id : %d & Message sent : %s for END signal \\n",socket_fd,send_data); + } + flag++; + close(socket_fd); + } + +''' + + +#Writing content in cfunc.mod file +cfunc.write(comment) +cfunc.write(header) +cfunc.write("\n") +cfunc.write(function_open) +cfunc.write("\n") + +#Adding digital state Variable +for item in digital_state_output: + cfunc.write("\t"+item+"\n") + +#Adding variable declaration section +cfunc.write(var_section) +for item in temp_input_var: + cfunc.write("\t"+item+"\n") +cfunc.write("\n"); + +#Adding INIT portion +cfunc.write(init_start_function) +for item in cm_event_alloc: + cfunc.write(2*"\t"+item) + cfunc.write("\n") + +cfunc.write(2*"\t"+"/* set the load for input ports. */") +cfunc.write("\n") +cfunc.write(2*"\t"+"int Ii;") +cfunc.write("\n"); + +for item in load_in_port: + cfunc.write(2*"\t"+item) + cfunc.write("\n") +cfunc.write("\n") +cfunc.write(2*"\t"+"/*Retrieve Storage for output*/") +cfunc.write("\n") +for item in cm_event_get_ptr: + cfunc.write(2*"\t"+item) + cfunc.write("\n") +cfunc.write(systime_info) +cfunc.write("\n") +cfunc.write("\t\tchar command[1024];") +cfunc.write('\t\tsnprintf(command,1024,"'+home+'/ngspice-nghdl/src/xspice/icm/ghdl/'+fname.split('.')[0]+'/DUTghdl/start_server.sh %d &",sock_port);\n') +cfunc.write('\t\tsystem(command);') +cfunc.write("\t}") +cfunc.write("\n") +cfunc.write("\telse\n\t{\n") + +for item in els_evt_ptr: + cfunc.write(2*"\t"+item) + cfunc.write("\n") +cfunc.write("\t}") +cfunc.write("\n\n") +cfunc.write("\tif(flag==0)\n\t{") +cfunc.write(client_setup) +cfunc.write(create_socket) +cfunc.write(connect_server) +cfunc.write(time_limit) + +for item in assign_data_to_input: + cfunc.write(item) + +for item in snprintf_stmt: + cfunc.write(item) + +cfunc.write(send_data) +cfunc.write(recv_data) + +for item in sch_output_event: + cfunc.write(item) +#End of if statement of time limit +cfunc.write(2*"\t"+"}") + +#Else part of time limit -sending END signal +cfunc.write(els_time_limit) + +#Close if of flag==0 +cfunc.write("\t}\n\n") + +#close log_client file +cfunc.write("\tfclose(log_client);") + +#Close cm_ function +cfunc.write("\n}") +cfunc.close() + +################Creating ifspec.ifs file######################################## +print "Starting with ifspec.ifs file" +ifspec=open('ifspec.ifs','w') + +print "Gathering Al the content for ifspec file" + +ifspec_comment=''' +/* +SUMMARY: This file is auto generated and it contains the interface specification for the +code model. */\n +''' + +name_table='NAME_TABLE:\n\ +C_Function_Name: cm_'+fname.split('.')[0]+'\n\ +Spice_Model_Name: '+fname.split('.')[0]+'\n\ +Description: "Model generated from ghdl code '+fname+'" \n' + +#Input and Output Port Table +in_port_table=[] +out_port_table=[] + +for item in input_port: + port_table = 'PORT_TABLE:\n' + port_name = 'Port_Name:\t'+item.split(':')[0]+'\n' + description = 'Description:\t"input port '+item.split(':')[0]+'"\n' + direction = 'Direction:\tin\n' + default_type = 'Default_Type:\td\n' + allowed_type = 'Allowed_Types:\t[d]\n' + vector = 'Vector:\tyes\n' + vector_bounds = 'Vector_Bounds:\t['+item.split(':')[1]+' '+item.split(":")[1]+']\n' + null_allowed = 'Null_Allowed:\tno\n' + #Insert detail in the list + in_port_table.append(port_table+port_name+description+direction+default_type+allowed_type+vector+vector_bounds+null_allowed) + + +for item in output_port: + port_table = 'PORT_TABLE:\n' + port_name = 'Port_Name:\t'+item.split(':')[0]+'\n' + description = 'Description:\t"output port '+item.split(':')[0]+'"\n' + direction = 'Direction:\tout\n' + default_type = 'Default_Type:\td\n' + allowed_type = 'Allowed_Types:\t[d]\n' + vector = 'Vector:\tyes\n' + vector_bounds = 'Vector_Bounds:\t['+item.split(':')[1]+' '+item.split(":")[1]+']\n' + null_allowed = 'Null_Allowed:\tno\n' + #Insert detail in the list + in_port_table.append(port_table+port_name+description+direction+default_type+allowed_type+vector+vector_bounds+null_allowed) + +parameter_table=''' + +PARAMETER_TABLE: +Parameter_Name: instance_id +Description: "instance_id" +Data_Type: real +Default_Value: 0 +Limits: - +Vector: no +Vector_Bounds: - +Null_Allowed: yes + +PARAMETER_TABLE: +Parameter_Name: rise_delay fall_delay +Description: "rise delay" "fall delay" +Data_Type: real real +Default_Value: 1.0e-9 1.0e-9 +Limits: [1e-12 -] [1e-12 -] +Vector: no no +Vector_Bounds: - - +Null_Allowed: yes yes + +PARAMETER_TABLE: +Parameter_Name: input_load stop_time +Description: "input load value (F)" "time at which to shut-down (seconds)" +Data_Type: real real +Default_Value: 1.0e-12 1.0 +Limits: - [0.0 -] +Vector: no no +Vector_Bounds: - - +Null_Allowed: yes no + +''' + + +#Writing all the content in ifspec file +ifspec.write(ifspec_comment) +ifspec.write(name_table+"\n\n") + +for item in in_port_table: + ifspec.write(item+"\n") + +ifspec.write("\n") + +for item in out_port_table: + ifspec.write(item+"\n") + +ifspec.write("\n") +ifspec.write(parameter_table) +ifspec.close() + + +########Creating testbench file ################################################ +print "Starting with testbench file" + +testbench=open(fname.split('.')[0]+'_tb.vhdl','w') +print fname.split('.')[0] + '_tb.vhdl' +#comment +comment_vhdl="--------------------------------------------------------------------------------\n--This testbench has been created by Ambikeshwar Srivastava, FOSSEE, IIT Bombay\n-------------------------------------------------------------------------------" +#Adding header, entity and architecture statement +tb_header=''' +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.Vhpi_Foreign.all; +use work.Utility_Package.all; +use work.sock_pkg.all; + + +''' + +tb_entity="entity "+fname.split('.')[0]+"_tb is\nend entity;\n\n" + +arch="architecture "+fname.split('.')[0]+"_tb_beh of "+fname.split('.')[0]+"_tb is\n" + +#Adding components + +components=[] +components.append("\tcomponent "+fname.split('.')[0]+" is\n\t\tport(\n\t\t\t\t") + +port_vector_count = 0 + +for item in input_port: + if port_vector_info[port_vector_count]: + components.append(item.split(':')[0]+": in std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n\t\t\t\t") + else: + components.append(item.split(':')[0]+": in std_logic;\n\t\t\t\t") + + port_vector_count += 1 + #if item.split(":")[1] != '1': + # components.append(item.split(':')[0]+": in std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n\t\t\t\t") + #else: + # components.append(item.split(':')[0]+": in std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n\t\t\t\t") + +for item in output_port[:-1]: + if port_vector_info[port_vector_count]: + components.append(item.split(':')[0]+": out std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n\t\t\t\t") + else: + components.append(item.split(':')[0]+": out std_logic;\n\t\t\t\t") + + port_vector_count += 1 + +if port_vector_info[port_vector_count]: + components.append(output_port[-1].split(':')[0]+": out std_logic_vector("+str(int(output_port[-1].split(':')[1])-int(1))+" downto 0)\n\t\t\t\t") +else: + components.append(output_port[-1].split(':')[0]+": out std_logic\n\t\t\t\t") + #if item.split(":")[1] != '1': + # components.append(item.split(':')[0]+": out std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0)\n\t\t\t\t") + #else: + # components.append(item.split(':')[0]+": out std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0)\n\t\t\t\t") + +components.append(");\n") +components.append("\tend component;\n\n") + +#Adding signals +signals=[] +signals.append("\tsignal clk_s : std_logic := '0';\n") + +port_vector_count = 0 + +for item in input_port: + if port_vector_info[port_vector_count]: + signals.append("\tsignal "+item.split(':')[0]+": std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") + else: + signals.append("\tsignal "+item.split(':')[0]+": std_logic;\n") + port_vector_count += 1 + + #if item.split(":")[1] != '1': + # signals.append("\tsignal "+item.split(':')[0]+": std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") + #else: + # signals.append("\tsignal "+item.split(':')[0]+": std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") + + +for item in output_port: + if port_vector_info[port_vector_count]: + signals.append("\tsignal "+item.split(':')[0]+": std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") + else: + signals.append("\tsignal "+item.split(':')[0]+": std_logic;\n") + port_vector_count += 1 + #if item.split(":")[1] != '1': + # signals.append("\tsignal "+item.split(':')[0]+": std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") + #else: + # signals.append("\tsignal "+item.split(':')[0]+": std_logic_vector("+str(int(item.split(':')[1])-int(1))+" downto 0);\n") + +#Adding mapping part +map=[] +map.append("\tu1 : "+fname.split('.')[0]+" port map(\n") + +for item in input_port: + map.append("\t\t\t\t"+item.split(':')[0]+" => "+item.split(':')[0]+",\n") + +for item in output_port: + if output_port.index(item) == len(output_port) - 1: + map.append("\t\t\t\t"+item.split(':')[0]+" => "+item.split(':')[0]+"\n") + else: + map.append("\t\t\t\t"+item.split(':')[0]+" => "+item.split(':')[0]+",\n") +map.append("\t\t\t);") + + +#testbench Clock +tb_clk= "clk_s <= not clk_s after 5 us;\n\n" +#Adding Process block for Vhpi +process_Vhpi=[] +process_Vhpi.append("\tprocess\n\t\tvariable sock_port : integer;\n\t\tbegin\n\t\tsock_port := sock_pkg_fun;\n\t\tVhpi_Initialize(sock_port);\n\t\twait until clk_s = '1';\n\t\twhile true loop\n\t\t\twait until clk_s = '0';\n\t\t\tVhpi_Listen;\n\t\t\twait for 1 us;\n\t\t\tVhpi_Send;\n\t\tend loop;\n\t\twait;\n\tend process;\n\n") +#Adding process block +process=[] +process.append("\tprocess\n\n") + +for item in input_port: + process.append("\t\tvariable "+item.split(':')[0]+"_v : VhpiString;\n") + +for item in output_port: + process.append("\t\tvariable "+item.split(':')[0]+"_v : VhpiString;\n") + +process.append("\t\tvariable obj_ref : VhpiString;\n") +process.append("\tbegin\n") +process.append("\t\twhile true loop\n") +process.append("\t\t\twait until clk_s = '0';\n\n") + +port_vector_count = 0 + +for item in input_port: + process.append('\t\t\tobj_ref := Pack_String_To_Vhpi_String("'+item.split(':')[0]+'");\n') + process.append('\t\t\tVhpi_Get_Port_Value(obj_ref,'+item.split(':')[0]+'_v,'+item.split(':')[1]+');\n') + process.append('\t\t\tassert false report "Get port value '+item.split(':')[0]+' returns " &'+item.split(':')[0]+'_v severity note;\n') + if port_vector_info[port_vector_count]: + process.append('\t\t\t'+item.split(':')[0]+' <= Unpack_String('+item.split(':')[0]+'_v,'+item.split(':')[1]+');\n') + else: + process.append('\t\t\t'+item.split(':')[0]+' <= To_Std_Logic('+item.split(':')[0]+'_v'+');\n') + port_vector_count += 1 + process.append("\n") + +process.append('\t\t\twait for 1 us;\n') + +for item in output_port: + if port_vector_info[port_vector_count]: + process.append('\t\t\t'+item.split(':')[0]+'_v := Pack_String_To_Vhpi_String(Convert_SLV_To_String('+item.split(':')[0]+'));\n') + else: + process.append('\t\t\t'+item.split(':')[0]+'_v := Pack_String_To_Vhpi_String(To_String('+item.split(':')[0]+'));\n') + port_vector_count += 1 + + process.append('\t\t\tobj_ref := Pack_String_To_Vhpi_String("'+item.split(':')[0]+'");\n') + process.append('\t\t\tVhpi_Set_Port_Value(obj_ref,'+item.split(':')[0]+'_v,'+item.split(':')[1]+');\n') + process.append('\t\t\tassert false report "Set port value '+item.split(':')[0]+' returns " &'+item.split(':')[0]+'_v severity note;\n') + process.append("\n") +process.append("\t\tend loop;\n") +process.append("\tend process;\n\n") +process.append("end architecture;") + + +#Writing all the components to testbench file +testbench.write(comment_vhdl) +testbench.write(tb_header) +testbench.write(tb_entity) +testbench.write(arch) + +for item in components: + testbench.write(item) + +for item in signals: + testbench.write(item) + +testbench.write("\n\n") + +testbench.write("begin\n\n") + +for item in map: + testbench.write(item) + +testbench.write("\n\t"+tb_clk) + +for item in process_Vhpi: + testbench.write(item) + +for item in process: + testbench.write(item) + + +testbench.close() + +##################################### Creating and writing components in start_server.sh ################################ + +start_server = open('start_server.sh','w') + +start_server.write("#!/bin/bash\n\n") +start_server.write("###This server run ghdl testebench for infinite time till ngspice send END signal to stop it\n\n") +start_server.write("#gcc -c ghdlserver.c\n") +start_server.write("#ghdl -a Utility_Package.vhdl &&\n") +start_server.write("#ghdl -a Vhpi_Package.vhdl &&\n") +start_server.write("cd "+home+"/ngspice-nghdl/src/xspice/icm/ghdl/"+fname.split('.')[0]+"/DUTghdl/\n") +start_server.write("chmod 775 sock_pkg_create.sh &&\n") +start_server.write("./sock_pkg_create.sh $1 &&\n") +start_server.write("ghdl -a sock_pkg.vhdl &&\n") +start_server.write("ghdl -a "+fname+" &&\n") +start_server.write("ghdl -a "+fname.split('.')[0]+"_tb.vhdl &&\n") +start_server.write("ghdl -e -Wl,ghdlserver.o "+fname.split('.')[0]+"_tb &&\n") +start_server.write("./"+fname.split('.')[0]+"_tb") + +start_server.close() + +##################################### Creating and writing in sock_pkg_create.sh ######################################## + +sock_pkg_create = open('sock_pkg_create.sh','w') + +sock_pkg_create.write("#!/bin/bash\n\n") +sock_pkg_create.write("##This file create sock_pkg_create.vhdl file and set the instance id from parameter based on parameter\n\n") +sock_pkg_create.write("echo \"library ieee;\n") +sock_pkg_create.write("package sock_pkg is\n") +sock_pkg_create.write("\tfunction sock_pkg_fun return integer;\n") +sock_pkg_create.write("end;\n\n") +sock_pkg_create.write("\tpackage body sock_pkg is\n") +sock_pkg_create.write("\t function sock_pkg_fun return integer is") +sock_pkg_create.write("\t\tvariable sock_id : integer;\n") +sock_pkg_create.write("\t\t\tbegin\n") +sock_pkg_create.write("\t\t\t\tsock_id := $1;\n") +sock_pkg_create.write("\t\t\t\treturn sock_id;\n") +sock_pkg_create.write("\t\t\tend function;\n") +sock_pkg_create.write("\t\tend package body;\" > sock_pkg.vhdl")
\ No newline at end of file diff --git a/nghdl/src/ngspice_ghdl.py b/nghdl/src/ngspice_ghdl.py new file mode 100755 index 00000000..0a9e88cf --- /dev/null +++ b/nghdl/src/ngspice_ghdl.py @@ -0,0 +1,366 @@ +#!/usr/bin/env python + + +"""#!/usr/bin/python""" + +#This file create the gui to install code model in the ngspice. + +import os +import sys +import shutil +import subprocess +from PyQt4 import QtGui +from PyQt4 import QtCore +from ConfigParser import SafeConfigParser +from Appconfig import Appconfig +from createKicadLibrary import AutoSchematic + +class Mainwindow(QtGui.QWidget): + def __init__(self): + #super(Mainwindow, self).__init__() + QtGui.QMainWindow.__init__(self) + print "Initializing.........." + self.home = os.path.expanduser("~") + #Reading all varibale from config.ini + self.parser = SafeConfigParser() + self.parser.read(os.path.join(self.home, os.path.join('.nghdl','config.ini'))) + self.ngspice_home = self.parser.get('NGSPICE','NGSPICE_HOME') + self.release_dir = self.parser.get('NGSPICE','RELEASE') + self.src_home = self.parser.get('SRC','SRC_HOME') + self.licensefile = self.parser.get('SRC','LICENSE') + #Printing LICENCE file on terminal + fileopen = open(self.licensefile, 'r') + print fileopen.read() + self.file_list = [] #to keep the supporting files + self.initUI() + + def initUI(self): + self.uploadbtn = QtGui.QPushButton('Upload') + self.uploadbtn.clicked.connect(self.uploadModle) + self.exitbtn = QtGui.QPushButton('Exit') + self.exitbtn.clicked.connect(self.closeWindow) + self.browsebtn = QtGui.QPushButton('Browse') + self.browsebtn.clicked.connect(self.browseFile) + self.addbtn = QtGui.QPushButton('Add Files') + self.addbtn.clicked.connect(self.addFiles) + self.removebtn = QtGui.QPushButton('Remove Files') + self.removebtn.clicked.connect(self.removeFiles) + self.ledit = QtGui.QLineEdit(self) + self.sedit = QtGui.QTextEdit(self) + self.process = QtCore.QProcess(self) + self.termedit = QtGui.QTextEdit(self) + self.termedit.setReadOnly(1) + pal = QtGui.QPalette() + bgc = QtGui.QColor(0, 0, 0) + pal.setColor(QtGui.QPalette.Base, bgc) + self.termedit.setPalette(pal) + self.termedit.setStyleSheet("QTextEdit {color:white}") + + #Creating gridlayout + grid = QtGui.QGridLayout() + grid.setSpacing(5) + grid.addWidget(self.ledit, 1, 0) + grid.addWidget(self.browsebtn, 1, 1) + grid.addWidget(self.sedit, 2, 0, 4, 1) + grid.addWidget(self.addbtn, 2, 1) + grid.addWidget(self.removebtn, 3, 1) + grid.addWidget(self.termedit, 6, 0, 10, 1) + grid.addWidget(self.uploadbtn, 17, 0) + grid.addWidget(self.exitbtn,17, 1) + + self.setLayout(grid) + self.setGeometry(300, 300, 600,600) + self.setWindowTitle("Ngspice Digital Model Creator") + #self.setWindowIcon(QtGui.QIcon('logo.png')) + self.show() + + + + def closeWindow(self): + try: + self.process.close() + except: + pass + print "Close button clicked" + quit() + + def browseFile(self): + print "Browse button clicked" + self.filename = QtGui.QFileDialog.getOpenFileName(self, 'Open File', '.') + self.ledit.setText(self.filename) + print "Vhdl file uploaded to process :", self.filename + + def addFiles(self): + print "Starts adding supporting files" + title = self.addbtn.text() + for file in QtGui.QFileDialog.getOpenFileNames(self, title): + self.sedit.append(str(file)) + self.file_list.append(file) + print "Supporting Files are :",self.file_list + + + def removeFiles(self): + self.fileRemover = FileRemover(self) + + + #check extensions of all supporting files + def checkSupportFiles(self): + nonvhdl_count = 0 + for file in self.file_list: + extension = os.path.splitext(str(file))[1] + if extension != ".vhdl": + nonvhdl_count += 1 + self.file_list.remove(file) + + if nonvhdl_count > 0: + QtGui.QMessageBox.about(self,'Message','''<b>Important Message.</b><br/><br/>Supporting files should be <b>.vhdl</b> file ''') + + + def createModelDirectory(self): + print "Create Model Directory Called" + self.digital_home=self.parser.get('NGSPICE','DIGITAL_MODEL') + os.chdir(self.digital_home) + print "Current Working Directory Changed to",os.getcwd() + self.modelname = os.path.basename(str(self.filename)).split('.')[0] + print "Model to be created :",self.modelname + # Looking if model directory is present or not + if os.path.isdir(self.modelname): + print "Model Already present" + ret = QtGui.QMessageBox.critical(self, "Critical",'''<b>The Model already exist.Do you want to overwrite it?</b><br/> + <b>If yes press ok else cancel it and change the name of you vhdl file</b>''', QtGui.QMessageBox.Ok, QtGui.QMessageBox.Cancel) + if ret == QtGui.QMessageBox.Ok: + print "Overwriting existing model "+self.modelname + cmd="rm -rf "+self.modelname + #process = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE, shell=True) + subprocess.call(cmd, shell=True) + os.mkdir(self.modelname) + else: + print "Exiting application" + quit() + + + + else: + print "Creating model "+self.modelname+" directory" + os.mkdir(self.modelname) + + def addingModelInModpath(self): + print "Adding Model "+self.modelname+" in Modpath file "+self.digital_home + #Adding name of model in the modpath file + #Check if the string is already in the file + with open(self.digital_home+"/modpath.lst",'a+') as f: + flag = 0 + for line in f: + if line.strip() == self.modelname: + print "Found model "+self.modelname+" in the modpath.lst" + flag = 1 + break + else: + pass + + if flag == 0: + print "Adding model name "+self.modelname+" into modpath.lst" + f.write(self.modelname+"\n") + else: + print "Model name is already into modpath.lst" + + + def createModelFiles(self): + print "Create Model Files Called" + os.chdir(self.cur_dir) + print "Current Working directory changed to "+self.cur_dir + cmd = "python "+self.src_home+"/src/model_generation.py "+str(self.ledit.text()) + stdouterr = os.popen4(cmd)[1].read() + print stdouterr + #Moving file to model directory + path=os.path.join(self.digital_home,self.modelname) + shutil.move("cfunc.mod",path) + shutil.move("ifspec.ifs",path) + + #Creating directory inside model directoy + print "Creating DUT directory at "+os.path.join(path,"DUTghdl") + os.mkdir(path+"/DUTghdl/") + print "Copying required file to DUTghdl directory" + shutil.move("connection_info.txt",path+"/DUTghdl/") + shutil.move("start_server.sh",path+"/DUTghdl/") + shutil.move("sock_pkg_create.sh",path+"/DUTghdl/") + shutil.move(self.modelname+"_tb.vhdl",path+"/DUTghdl/") + + shutil.copy(str(self.filename),path+"/DUTghdl/") + shutil.copy(os.path.join(self.home, self.src_home)+"/src/ghdlserver/compile.sh",path+"/DUTghdl/") + shutil.copy(os.path.join(self.home, self.src_home)+"/src/ghdlserver/uthash.h",path+"/DUTghdl/") + shutil.copy(os.path.join(self.home, self.src_home)+"/src/ghdlserver/ghdlserver.c",path+"/DUTghdl/") + shutil.copy(os.path.join(self.home, self.src_home)+"/src/ghdlserver/ghdlserver.h",path+"/DUTghdl/") + shutil.copy(os.path.join(self.home, self.src_home)+"/src/ghdlserver/Utility_Package.vhdl",path+"/DUTghdl/") + shutil.copy(os.path.join(self.home, self.src_home)+"/src/ghdlserver/Vhpi_Package.vhdl",path+"/DUTghdl/") + + for file in self.file_list: + shutil.copy(str(file), path+"/DUTghdl/") + + os.chdir(path+"/DUTghdl") + subprocess.call("bash "+path+"/DUTghdl/compile.sh", shell=True) + subprocess.call("chmod a+x start_server.sh",shell=True) + subprocess.call("chmod a+x sock_pkg_create.sh",shell=True) + os.remove("compile.sh") + os.remove("ghdlserver.c") + #os.remove("ghdlserver.h") + #os.remove("Utility_Package.vhdl") + #os.remove("Vhpi_Package.vhdl") + + + #slot to redirect stdout to window console + @QtCore.pyqtSlot() + def readStdOutput(self): + self.termedit.append(QtCore.QString(self.process.readAllStandardOutput())) + + + def runMake(self): + print "run Make Called" + self.release_home=self.parser.get('NGSPICE','RELEASE') + os.chdir(self.release_home) + try: + cmd = " make" + print "Running Make command in "+self.release_home + path = os.getcwd() + self.process.start(cmd) + self.process.setProcessChannelMode(QtCore.QProcess.MergedChannels) + QtCore.QObject.connect(self.process, QtCore.SIGNAL("readyReadStandardOutput()"), self, QtCore.SLOT("readStdOutput()")) + print "make command process pid ---------- >",self.process.pid() + + except: + print "There is error in 'make' " + quit() + + def runMakeInstall(self): + print "run Make Install Called" + try: + cmd = " make install" + print "Running Make Install" + path = os.getcwd() + try: + self.process.close() + except: + pass + self.process.finished.connect(self.createSchematicLib) + self.process.start(cmd) + self.process.setProcessChannelMode(QtCore.QProcess.MergedChannels) + QtCore.QObject.connect(self.process, QtCore.SIGNAL("readyReadStandardOutput()"), self, QtCore.SLOT("readStdOutput()")) + os.chdir(self.cur_dir) + + except: + print "There is error during in 'make install' " + quit() + + def createSchematicLib(self): + if Appconfig.esimFlag == 1: + print 'Creating library files.................................' + self.schematicLib = AutoSchematic(self.modelname) + self.schematicLib.createKicadLibrary() + + def uploadModle(self): + print "Upload button clicked" + try: + self.process.close() + except: + pass + try: + self.file_extension = os.path.splitext(str(self.filename))[1] + print "Uploaded File extension :"+self.file_extension + self.cur_dir = os.getcwd() + print "Current Working Directory :"+self.cur_dir + self.checkSupportFiles() + if self.file_extension == ".vhdl": + self.createModelDirectory() + self.addingModelInModpath() + self.createModelFiles() + self.runMake() + self.runMakeInstall() + else: + QtGui.QMessageBox.about(self,'Message','''<b>Important Message.</b><br/><br/>This accepts only <b>.vhdl</b> file ''') + except: + QtGui.QMessageBox.about(self, 'Message','''<b>Error</b><br/><br/> select a <b>.vhdl</b> file ''') + +class FileRemover(QtGui.QWidget): + + def __init__(self, main_obj): + super(FileRemover, self).__init__() + self.row = 0 + self.col = 0 + self.cb_dict = {} + self.marked_list = [] + self.files = main_obj.file_list + self.sedit = main_obj.sedit + + print self.files + + self.grid = QtGui.QGridLayout() + removebtn = QtGui.QPushButton('Remove', self) + removebtn.clicked.connect(self.removeFiles) + + self.grid.addWidget(self.createCheckBox(), 0, 0) + self.grid.addWidget(removebtn, 1, 1) + + self.setLayout(self.grid) + self.show() + + def createCheckBox(self): + + self.checkbox = QtGui.QGroupBox() + self.checkbox.setTitle('Remove Files') + self.checkgrid = QtGui.QGridLayout() + + self.checkgroupbtn = QtGui.QButtonGroup() + + for path in self.files: + + print path + + self.cb_dict[path] = QtGui.QCheckBox(path) + self.checkgroupbtn.addButton(self.cb_dict[path]) + self.checkgrid.addWidget(self.cb_dict[path], self.row, self.col) + self.row += 1 + + self.checkgroupbtn.setExclusive(False) + self.checkgroupbtn.buttonClicked.connect(self.mark_file) + self.checkbox.setLayout(self.checkgrid) + + return self.checkbox + + def mark_file(self): + + for path in self.cb_dict: + if self.cb_dict[path].isChecked(): + if path not in self.marked_list: + self.marked_list.append(path) + + else: + if path in self.marked_list: + self.marked_list.remove(path) + + def removeFiles(self): + + for path in self.marked_list: + print path +" is removed" + self.sedit.append(path + " removed") + self.files.remove(path) + + self.sedit.clear() + for path in self.files: + self.sedit.append(path) + + self.marked_list[:] = [] + self.files[:] = [] + self.close() + + + +def main(): + app = QtGui.QApplication(sys.argv) + if len(sys.argv) > 1: + if sys.argv[1] == '-e': + Appconfig.esimFlag = 1 + w = Mainwindow() + sys.exit(app.exec_()) + +if __name__=='__main__': + main() diff --git a/nghdl/src/outitf.c b/nghdl/src/outitf.c new file mode 100644 index 00000000..819f0064 --- /dev/null +++ b/nghdl/src/outitf.c @@ -0,0 +1,1359 @@ +/********** +Copyright 1990 Regents of the University of California. All rights reserved. +Author: 1988 Wayne A. Christopher, U. C. Berkeley CAD Group +Modified: 2000 AlansFixes +**********/ +/************************************************************************** + * 10.Mar.2017 - RM - Added a dirty fix to handle orphan FOSSEE test bench + * processes. The following static functions were added in the process: + * o nghdl_orphan_tb() + * o nghdl_tb_SIGUSR1() + ************************************************************************** + */ +/* + * This module replaces the old "writedata" routines in nutmeg. + * Unlike the writedata routines, the OUT routines are only called by + * the simulator routines, and only call routines in nutmeg. The rest + * of nutmeg doesn't deal with OUT at all. + */ + +#include "ngspice/ngspice.h" +#include "ngspice/cpdefs.h" +#include "ngspice/ftedefs.h" +#include "ngspice/dvec.h" +#include "ngspice/plot.h" +#include "ngspice/sim.h" +#include "ngspice/inpdefs.h" /* for INPtables */ +#include "ngspice/ifsim.h" +#include "ngspice/jobdefs.h" +#include "ngspice/iferrmsg.h" +#include "circuits.h" +#include "outitf.h" +#include "variable.h" +#include <fcntl.h> +#include "ngspice/cktdefs.h" +#include "ngspice/inpdefs.h" +#include "breakp2.h" +#include "runcoms.h" +#include "plotting/graf.h" +#include "../misc/misc_time.h" + +/* 10.Mar.2917 - RM - Added the following #include */ +#include <dirent.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <signal.h> + +extern char *spice_analysis_get_name(int index); +extern char *spice_analysis_get_description(int index); + + +static int beginPlot(JOB *analysisPtr, CKTcircuit *circuitPtr, char *cktName, char *analName, + char *refName, int refType, int numNames, char **dataNames, int dataType, + bool windowed, runDesc **runp); +static int addDataDesc(runDesc *run, char *name, int type, int ind); +static int addSpecialDesc(runDesc *run, char *name, char *devname, char *param, int depind); +static void fileInit(runDesc *run); +static void fileInit_pass2(runDesc *run); +static void fileStartPoint(FILE *fp, bool bin, int num); +static void fileAddRealValue(FILE *fp, bool bin, double value); +static void fileAddComplexValue(FILE *fp, bool bin, IFcomplex value); +static void fileEndPoint(FILE *fp, bool bin); +static void fileEnd(runDesc *run); +static void plotInit(runDesc *run); +static void plotAddRealValue(dataDesc *desc, double value); +static void plotAddComplexValue(dataDesc *desc, IFcomplex value); +static void plotEnd(runDesc *run); +static bool parseSpecial(char *name, char *dev, char *param, char *ind); +static bool name_eq(char *n1, char *n2); +static bool getSpecial(dataDesc *desc, runDesc *run, IFvalue *val); +static void freeRun(runDesc *run); + +/*Output data to spice module*/ +#ifdef TCL_MODULE +#include "ngspice/tclspice.h" +#elif defined SHARED_MODULE +extern int sh_ExecutePerLoop(void); +extern void sh_vecinit(runDesc *run); +#endif + +/*Suppressing progress info in -o option */ +#ifndef HAS_WINGUI +extern bool orflag; +#endif + + +#define DOUBLE_PRECISION 15 + + +static clock_t lastclock, currclock; +static double *rowbuf; +static size_t column, rowbuflen; + +static bool shouldstop = FALSE; /* Tell simulator to stop next time it asks. */ + +/* 10.Mar.2017 - RM - Added nghdl_tb_SIGUSR1().*/ +static void nghdl_tb_SIGUSR1(char* pid_file) +{ + int ret; + char line[80]; + char* nptr; + + FILE* fp = fopen(pid_file, "r"); + + if (fp) + { + if (fscanf(fp, "%s", line) != EOF) + { + fclose(fp); + pid_t pid = (pid_t) strtol(line, &nptr, 10); + // PID is converted to a decimal value. + + + if ((errno != ERANGE) && (errno!= EINVAL)) + { + if (pid) + { + // Check if a process with this pid really exists. + ret = kill(pid, 0); + if (ret == 0) + { + kill(pid, SIGUSR1); + } + } + } + } + } +} + +/* 10.Mar.2017 - RM - Added nghdl_orphan_tb().*/ +static void nghdl_orphan_tb(void) +{ + struct dirent* dirp; + DIR* dirfd; + char* dir = "/tmp"; + char filename_tmp[1024]; + char pid_file_prefix[256]; + + sprintf(pid_file_prefix, "NGHDL_%d", getpid()); + + if ((dirfd = opendir(dir)) == NULL) + { + fprintf(stdout, "\n\n\n\n Cannot open /tmp \n\n"); + + fprintf(stderr, "nghdl_orphan_tb(): Cannot open /tmp\n"); + + return; + } + +/* Loop through /tmp directories looking for "NGHDL_<my pid>*" files.*/ + while ((dirp = readdir(dirfd)) != NULL) + { + struct stat stbuf; + sprintf(filename_tmp, "/tmp/%s", dirp->d_name); + if (strstr(filename_tmp, pid_file_prefix)) + { + if (stat(filename_tmp, &stbuf) == -1) + { + fprintf(stderr, "nghdl_orphan_tb: stat() failed; ERRNO=%d on file:%s\n", errno, filename_tmp); + continue; + } + + if ((stbuf.st_mode & S_IFMT) == S_IFDIR) + { + continue; + } + else + { + nghdl_tb_SIGUSR1(filename_tmp); + } + } + } +} +/* End 10.Mar.2017 - RM */ + +/* The two "begin plot" routines share all their internals... */ + +int +OUTpBeginPlot(CKTcircuit *circuitPtr, JOB *analysisPtr, + IFuid analName, + IFuid refName, int refType, + int numNames, IFuid *dataNames, int dataType, runDesc **plotPtr) +{ + char *name; + + if (ft_curckt->ci_ckt == circuitPtr) + name = ft_curckt->ci_name; + else + name = "circuit name"; + + return (beginPlot(analysisPtr, circuitPtr, name, + analName, refName, refType, numNames, + dataNames, dataType, FALSE, + plotPtr)); +} + + +int +OUTwBeginPlot(CKTcircuit *circuitPtr, JOB *analysisPtr, + IFuid analName, + IFuid refName, int refType, + int numNames, IFuid *dataNames, int dataType, runDesc **plotPtr) +{ + + return (beginPlot(analysisPtr, circuitPtr, "circuit name", + analName, refName, refType, numNames, + dataNames, dataType, TRUE, + plotPtr)); +} + + +static int +beginPlot(JOB *analysisPtr, CKTcircuit *circuitPtr, char *cktName, char *analName, char *refName, int refType, int numNames, char **dataNames, int dataType, bool windowed, runDesc **runp) +{ + runDesc *run; + struct save_info *saves; + bool *savesused = NULL; + int numsaves; + int i, j, depind = 0; + char namebuf[BSIZE_SP], parambuf[BSIZE_SP], depbuf[BSIZE_SP]; + char *ch, tmpname[BSIZE_SP]; + bool saveall = TRUE; + bool savealli = FALSE; + char *an_name; + /*to resume a run saj + *All it does is reassign the file pointer and return (requires *runp to be NULL if this is not needed) + */ + if (dataType == 666 && numNames == 666) { + run = *runp; + run->writeOut = ft_getOutReq(&run->fp, &run->runPlot, &run->binary, + run->type, run->name); + + } else { + /*end saj*/ + + /* Check to see if we want to print informational data. */ + if (cp_getvar("printinfo", CP_BOOL, NULL)) + fprintf(cp_err, "(debug printing enabled)\n"); + + *runp = run = alloc(struct runDesc); + + /* First fill in some general information. */ + run->analysis = analysisPtr; + run->circuit = circuitPtr; + run->name = copy(cktName); + run->type = copy(analName); + run->windowed = windowed; + run->numData = 0; + + an_name = spice_analysis_get_name(analysisPtr->JOBtype); + ft_curckt->ci_last_an = an_name; + + /* Now let's see which of these things we need. First toss in the + * reference vector. Then toss in anything that getSaves() tells + * us to save that we can find in the name list. Finally unpack + * the remaining saves into parameters. + */ + numsaves = ft_getSaves(&saves); + if (numsaves) { + savesused = TMALLOC(bool, numsaves); + saveall = FALSE; + for (i = 0; i < numsaves; i++) { + if (saves[i].analysis && !cieq(saves[i].analysis, an_name)) { + /* ignore this one this time around */ + savesused[i] = TRUE; + continue; + } + + /* Check for ".save all" and new synonym ".save allv" */ + + if (cieq(saves[i].name, "all") || cieq(saves[i].name, "allv")) { + saveall = TRUE; + savesused[i] = TRUE; + saves[i].used = 1; + continue; + } + + /* And now for the new ".save alli" option */ + + if (cieq(saves[i].name, "alli")) { + savealli = TRUE; + savesused[i] = TRUE; + saves[i].used = 1; + continue; + } + } + } + + /* Pass 0. */ + if (refName) { + addDataDesc(run, refName, refType, -1); + for (i = 0; i < numsaves; i++) + if (!savesused[i] && name_eq(saves[i].name, refName)) { + savesused[i] = TRUE; + saves[i].used = 1; + } + } else { + run->refIndex = -1; + } + + + /* Pass 1. */ + if (numsaves && !saveall) { + for (i = 0; i < numsaves; i++) + if (!savesused[i]) + for (j = 0; j < numNames; j++) + if (name_eq(saves[i].name, dataNames[j])) { + addDataDesc(run, dataNames[j], dataType, j); + savesused[i] = TRUE; + saves[i].used = 1; + break; + } + } else { + for (i = 0; i < numNames; i++) + if (!refName || !name_eq(dataNames[i], refName)) + /* Save the node as long as it's an internal device node */ + if (!strstr(dataNames[i], "#internal") && + !strstr(dataNames[i], "#source") && + !strstr(dataNames[i], "#drain") && + !strstr(dataNames[i], "#collector") && + !strstr(dataNames[i], "#emitter") && + !strstr(dataNames[i], "#base")) + { + addDataDesc(run, dataNames[i], dataType, i); + } + } + + /* Pass 1 and a bit. + This is a new pass which searches for all the internal device + nodes, and saves the terminal currents instead */ + + if (savealli) { + depind = 0; + for (i = 0; i < numNames; i++) { + if (strstr(dataNames[i], "#internal") || + strstr(dataNames[i], "#source") || + strstr(dataNames[i], "#drain") || + strstr(dataNames[i], "#collector") || + strstr(dataNames[i], "#emitter") || + strstr(dataNames[i], "#base")) + { + tmpname[0] = '@'; + tmpname[1] = '\0'; + strncat(tmpname, dataNames[i], BSIZE_SP-1); + ch = strchr(tmpname, '#'); + + if (strstr(ch, "#collector")) { + strcpy(ch, "[ic]"); + } else if (strstr(ch, "#base")) { + strcpy(ch, "[ib]"); + } else if (strstr(ch, "#emitter")) { + strcpy(ch, "[ie]"); + if (parseSpecial(tmpname, namebuf, parambuf, depbuf)) + addSpecialDesc(run, tmpname, namebuf, parambuf, depind); + strcpy(ch, "[is]"); + } else if (strstr(ch, "#drain")) { + strcpy(ch, "[id]"); + if (parseSpecial(tmpname, namebuf, parambuf, depbuf)) + addSpecialDesc(run, tmpname, namebuf, parambuf, depind); + strcpy(ch, "[ig]"); + } else if (strstr(ch, "#source")) { + strcpy(ch, "[is]"); + if (parseSpecial(tmpname, namebuf, parambuf, depbuf)) + addSpecialDesc(run, tmpname, namebuf, parambuf, depind); + strcpy(ch, "[ib]"); + } else if (strstr(ch, "#internal") && (tmpname[1] == 'd')) { + strcpy(ch, "[id]"); + } else { + fprintf(cp_err, + "Debug: could output current for %s\n", tmpname); + continue; + } + if (parseSpecial(tmpname, namebuf, parambuf, depbuf)) { + if (*depbuf) { + fprintf(stderr, + "Warning : unexpected dependent variable on %s\n", tmpname); + } else { + addSpecialDesc(run, tmpname, namebuf, parambuf, depind); + } + } + } + } + } + + + /* Pass 2. */ + for (i = 0; i < numsaves; i++) { + + if (savesused[i]) + continue; + + if (!parseSpecial(saves[i].name, namebuf, parambuf, depbuf)) { + if (saves[i].analysis) + fprintf(cp_err, "Warning: can't parse '%s': ignored\n", + saves[i].name); + continue; + } + + /* Now, if there's a dep variable, do we already have it? */ + if (*depbuf) { + for (j = 0; j < run->numData; j++) + if (name_eq(depbuf, run->data[j].name)) + break; + if (j == run->numData) { + /* Better add it. */ + for (j = 0; j < numNames; j++) + if (name_eq(depbuf, dataNames[j])) + break; + if (j == numNames) { + fprintf(cp_err, + "Warning: can't find '%s': value '%s' ignored\n", + depbuf, saves[i].name); + continue; + } + addDataDesc(run, dataNames[j], dataType, j); + savesused[i] = TRUE; + saves[i].used = 1; + depind = j; + } else { + depind = run->data[j].outIndex; + } + } + + addSpecialDesc(run, saves[i].name, namebuf, parambuf, depind); + } + + if (numsaves) { + for (i = 0; i < numsaves; i++) { + tfree(saves[i].analysis); + tfree(saves[i].name); + } + tfree(saves); + tfree(savesused); + } + + if (numNames && + ((run->numData == 1 && run->refIndex != -1) || + (run->numData == 0 && run->refIndex == -1))) + { + fprintf(cp_err, "Error: no data saved for %s; analysis not run\n", + spice_analysis_get_description(analysisPtr->JOBtype)); + return E_NOTFOUND; + } + + /* Now that we have our own data structures built up, let's see what + * nutmeg wants us to do. + */ + run->writeOut = ft_getOutReq(&run->fp, &run->runPlot, &run->binary, + run->type, run->name); + + if (run->writeOut) { + fileInit(run); + } else { + plotInit(run); + if (refName) + run->runPlot->pl_ndims = 1; + } + } + + /*Start BLT, initilises the blt vectors saj*/ +#ifdef TCL_MODULE + blt_init(run); +#elif defined SHARED_MODULE + sh_vecinit(run); +#endif + + return (OK); +} + + +static int +addDataDesc(runDesc *run, char *name, int type, int ind) +{ + dataDesc *data; + + if (!run->numData) + run->data = TMALLOC(dataDesc, 1); + else + run->data = TREALLOC(dataDesc, run->data, run->numData + 1); + + data = &run->data[run->numData]; + /* so freeRun will get nice NULL pointers for the fields we don't set */ + bzero(data, sizeof(dataDesc)); + + data->name = copy(name); + data->type = type; + data->gtype = GRID_LIN; + data->regular = TRUE; + data->outIndex = ind; + + /* It's the reference vector. */ + if (ind == -1) + run->refIndex = run->numData; + + run->numData++; + + return (OK); +} + + +static int +addSpecialDesc(runDesc *run, char *name, char *devname, char *param, int depind) +{ + dataDesc *data; + char *unique; /* unique char * from back-end */ + + if (!run->numData) + run->data = TMALLOC(dataDesc, 1); + else + run->data = TREALLOC(dataDesc, run->data, run->numData + 1); + + data = &run->data[run->numData]; + /* so freeRun will get nice NULL pointers for the fields we don't set */ + bzero(data, sizeof(dataDesc)); + + data->name = copy(name); + + unique = copy(devname); + + /* MW. My "special" routine here */ + INPinsertNofree(&unique, ft_curckt->ci_symtab); + data->specName = unique; + + data->specParamName = copy(param); + + data->specIndex = depind; + data->specType = -1; + data->specFast = NULL; + data->regular = FALSE; + + run->numData++; + + return (OK); +} + + +int +OUTpData(runDesc *plotPtr, IFvalue *refValue, IFvalue *valuePtr) +{ + runDesc *run = plotPtr; // FIXME + int i; + + run->pointCount++; + +#ifdef TCL_MODULE + steps_completed = run->pointCount; +#endif + + if (run->writeOut) { + + if (run->pointCount == 1) + fileInit_pass2(run); + + fileStartPoint(run->fp, run->binary, run->pointCount); + + if (run->refIndex != -1) { + if (run->isComplex) { + fileAddComplexValue(run->fp, run->binary, refValue->cValue); + + /* While we're looking at the reference value, print it to the screen + every quarter of a second, to give some feedback without using + too much CPU time */ +#ifndef HAS_WINGUI + if (!orflag) { + currclock = clock(); + if ((currclock-lastclock) > (0.25*CLOCKS_PER_SEC)) { + fprintf(stderr, " Reference value : % 12.5e\r", + refValue->cValue.real); + lastclock = currclock; + } + } +#endif + } else { + + /* And the same for a non-complex value */ + + fileAddRealValue(run->fp, run->binary, refValue->rValue); +#ifndef HAS_WINGUI + if (!orflag) { + currclock = clock(); + if ((currclock-lastclock) > (0.25*CLOCKS_PER_SEC)) { + fprintf(stderr, " Reference value : % 12.5e\r", + refValue->rValue); + lastclock = currclock; + } + } +#endif + } + } + + for (i = 0; i < run->numData; i++) { + /* we've already printed reference vec first */ + if (run->data[i].outIndex == -1) + continue; + +#ifdef TCL_MODULE + blt_add(i, refValue ? refValue->rValue : NAN); +#endif + + if (run->data[i].regular) { + if (run->data[i].type == IF_REAL) + fileAddRealValue(run->fp, run->binary, + valuePtr->v.vec.rVec [run->data[i].outIndex]); + else if (run->data[i].type == IF_COMPLEX) + fileAddComplexValue(run->fp, run->binary, + valuePtr->v.vec.cVec [run->data[i].outIndex]); + else + fprintf(stderr, "OUTpData: unsupported data type\n"); + } else { + IFvalue val; + /* should pre-check instance */ + if (!getSpecial(&run->data[i], run, &val)) { + + /* If this is the first data point, print a warning for any unrecognized + variables, since this has not already been checked */ + + if (run->pointCount == 1) + fprintf(stderr, "Warning: unrecognized variable - %s\n", + run->data[i].name); + + if (run->isComplex) { + val.cValue.real = 0; + val.cValue.imag = 0; + fileAddComplexValue(run->fp, run->binary, val.cValue); + } else { + val.rValue = 0; + fileAddRealValue(run->fp, run->binary, val.rValue); + } + + continue; + } + + if (run->data[i].type == IF_REAL) + fileAddRealValue(run->fp, run->binary, val.rValue); + else if (run->data[i].type == IF_COMPLEX) + fileAddComplexValue(run->fp, run->binary, val.cValue); + else + fprintf(stderr, "OUTpData: unsupported data type\n"); + } + +#ifdef TCL_MODULE + blt_add(i, valuePtr->v.vec.rVec [run->data[i].outIndex]); +#endif + + } + + + fileEndPoint(run->fp, run->binary); + + /* Check that the write to disk completed successfully, otherwise abort */ + + if (ferror(run->fp)) { + fprintf(stderr, "Warning: rawfile write error !!\n"); + shouldstop = TRUE; + } + + } else { + + /* This is interactive mode. Update the screen with the reference + variable just the same */ + +#ifndef HAS_WINGUI + if (!orflag) { + currclock = clock(); + if ((currclock-lastclock) > (0.25*CLOCKS_PER_SEC)) { + if (run->isComplex) { + fprintf(stderr, " Reference value : % 12.5e\r", + refValue ? refValue->cValue.real : NAN); + } else { + fprintf(stderr, " Reference value : % 12.5e\r", + refValue ? refValue->rValue : NAN); + } + lastclock = currclock; + } + } +#endif + + for (i = 0; i < run->numData; i++) { + +#ifdef TCL_MODULE + /*Locks the blt vector to stop access*/ + blt_lockvec(i); +#endif + + if (run->data[i].outIndex == -1) { + if (run->data[i].type == IF_REAL) + plotAddRealValue(&run->data[i], refValue->rValue); + else if (run->data[i].type == IF_COMPLEX) + plotAddComplexValue(&run->data[i], refValue->cValue); + } else if (run->data[i].regular) { + if (run->data[i].type == IF_REAL) + plotAddRealValue(&run->data[i], + valuePtr->v.vec.rVec[run->data[i].outIndex]); + else if (run->data[i].type == IF_COMPLEX) + plotAddComplexValue(&run->data[i], + valuePtr->v.vec.cVec[run->data[i].outIndex]); + } else { + IFvalue val; + /* should pre-check instance */ + if (!getSpecial(&run->data[i], run, &val)) + continue; + if (run->data[i].type == IF_REAL) + plotAddRealValue(&run->data[i], val.rValue); + else if (run->data[i].type == IF_COMPLEX) + plotAddComplexValue(&run->data[i], val.cValue); + else + fprintf(stderr, "OUTpData: unsupported data type\n"); + } + +#ifdef TCL_MODULE + /*relinks and unlocks vector*/ + blt_relink(i, (run->data[i]).vec); +#endif + + } + + gr_iplot(run->runPlot); + } + + if (ft_bpcheck(run->runPlot, run->pointCount) == FALSE) + shouldstop = TRUE; + +#ifdef TCL_MODULE + Tcl_ExecutePerLoop(); +#elif defined SHARED_MODULE + sh_ExecutePerLoop(); +#endif + + return (OK); +} + + +/* ARGSUSED */ /* until some code gets written */ +int +OUTwReference(void *plotPtr, IFvalue *valuePtr, void **refPtr) +{ + NG_IGNORE(refPtr); + NG_IGNORE(valuePtr); + NG_IGNORE(plotPtr); + + return (OK); +} + + +/* ARGSUSED */ /* until some code gets written */ +int +OUTwData(runDesc *plotPtr, int dataIndex, IFvalue *valuePtr, void *refPtr) +{ + NG_IGNORE(refPtr); + NG_IGNORE(valuePtr); + NG_IGNORE(dataIndex); + NG_IGNORE(plotPtr); + + return (OK); +} + + +/* ARGSUSED */ /* until some code gets written */ +int +OUTwEnd(runDesc *plotPtr) +{ + NG_IGNORE(plotPtr); + + return (OK); +} + + +int +OUTendPlot(runDesc *plotPtr) +{ + runDesc *run = plotPtr; // FIXME + + if (run->writeOut) { + fileEnd(run); + } else { + gr_end_iplot(); + plotEnd(run); + } + + freeRun(run); + + return (OK); +} + + +/* ARGSUSED */ /* until some code gets written */ +int +OUTbeginDomain(runDesc *plotPtr, IFuid refName, int refType, IFvalue *outerRefValue) +{ + NG_IGNORE(outerRefValue); + NG_IGNORE(refType); + NG_IGNORE(refName); + NG_IGNORE(plotPtr); + + return (OK); +} + + +/* ARGSUSED */ /* until some code gets written */ +int +OUTendDomain(runDesc *plotPtr) +{ + NG_IGNORE(plotPtr); + + return (OK); +} + + +/* ARGSUSED */ /* until some code gets written */ +int +OUTattributes(runDesc *plotPtr, IFuid varName, int param, IFvalue *value) +{ + runDesc *run = plotPtr; // FIXME + GRIDTYPE type; + + struct dvec *d; + + NG_IGNORE(value); + + if (param == OUT_SCALE_LIN) + type = GRID_LIN; + else if (param == OUT_SCALE_LOG) + type = GRID_XLOG; + else + return E_UNSUPP; + + if (run->writeOut) { + if (varName) { + int i; + for (i = 0; i < run->numData; i++) + if (!strcmp(varName, run->data[i].name)) + run->data[i].gtype = type; + } else { + run->data[run->refIndex].gtype = type; + } + } else { + if (varName) { + for (d = run->runPlot->pl_dvecs; d; d = d->v_next) + if (!strcmp(varName, d->v_name)) + d->v_gridtype = type; + } else if (param == PLOT_COMB) { + for (d = run->runPlot->pl_dvecs; d; d = d->v_next) + d->v_plottype = PLOT_COMB; + } else { + run->runPlot->pl_scale->v_gridtype = type; + } + } + + return (OK); +} + + +/* The file writing routines. */ + +static void +fileInit(runDesc *run) +{ + char buf[513]; + int i; + size_t n; + + lastclock = clock(); + + /* This is a hack. */ + run->isComplex = FALSE; + for (i = 0; i < run->numData; i++) + if (run->data[i].type == IF_COMPLEX) + run->isComplex = TRUE; + + n = 0; + sprintf(buf, "Title: %s\n", run->name); + n += strlen(buf); + fputs(buf, run->fp); + sprintf(buf, "Date: %s\n", datestring()); + n += strlen(buf); + fputs(buf, run->fp); + sprintf(buf, "Plotname: %s\n", run->type); + n += strlen(buf); + fputs(buf, run->fp); + sprintf(buf, "Flags: %s\n", run->isComplex ? "complex" : "real"); + n += strlen(buf); + fputs(buf, run->fp); + sprintf(buf, "No. Variables: %d\n", run->numData); + n += strlen(buf); + fputs(buf, run->fp); + sprintf(buf, "No. Points: "); + n += strlen(buf); + fputs(buf, run->fp); + + fflush(run->fp); /* Gotta do this for LATTICE. */ + if (run->fp == stdout || (run->pointPos = ftell(run->fp)) <= 0) + run->pointPos = (long) n; + fprintf(run->fp, "0 \n"); /* Save 8 spaces here. */ + + /*fprintf(run->fp, "Command: version %s\n", ft_sim->version);*/ + fprintf(run->fp, "Variables:\n"); + + printf("No. of Data Columns : %d \n", run->numData); +} + + +static void +fileInit_pass2(runDesc *run) +{ + int i, type; + + for (i = 0; i < run->numData; i++) { + + char *name = run->data[i].name; + + if (substring("#branch", name)) + type = SV_CURRENT; + else if (cieq(name, "time")) + type = SV_TIME; + else if (cieq(name, "frequency")) + type = SV_FREQUENCY; + else if (cieq(name, "temp-sweep")) + type = SV_TEMP; + else if (cieq(name, "res-sweep")) + type = SV_RES; + else if ((*name == '@') && (substring("[g", name))) + type = SV_ADMITTANCE; + else if ((*name == '@') && (substring("[c", name))) + type = SV_CAPACITANCE; + else if ((*name == '@') && (substring("[i", name))) + type = SV_CURRENT; + else if ((*name == '@') && (substring("[q", name))) + type = SV_CHARGE; + else + type = SV_VOLTAGE; + + if (type == SV_CURRENT) { + char *branch = strstr(name, "#branch"); + if (branch) + *branch = '\0'; + fprintf(run->fp, "\t%d\ti(%s)\t%s", i, name, ft_typenames(type)); + if (branch) + *branch = '#'; + } else if (type == SV_VOLTAGE) { + fprintf(run->fp, "\t%d\tv(%s)\t%s", i, name, ft_typenames(type)); + } else { + fprintf(run->fp, "\t%d\t%s\t%s", i, name, ft_typenames(type)); + } + + if (run->data[i].gtype == GRID_XLOG) + fprintf(run->fp, "\tgrid=3"); + + fprintf(run->fp, "\n"); + } + + fprintf(run->fp, "%s:\n", run->binary ? "Binary" : "Values"); + fflush(run->fp); + + /* Allocate Row buffer */ + + if (run->binary) { + rowbuflen = (size_t) (run->numData); + if (run->isComplex) + rowbuflen *= 2; + rowbuf = TMALLOC(double, rowbuflen); + } else { + // fIXME rowbuflen = 0; + rowbuf = NULL; + } +} + + +static void +fileStartPoint(FILE *fp, bool bin, int num) +{ + if (!bin) + fprintf(fp, "%d\t", num - 1); + + /* reset buffer pointer to zero */ + + column = 0; +} + + +static void +fileAddRealValue(FILE *fp, bool bin, double value) +{ + if (bin) + rowbuf[column++] = value; + else + fprintf(fp, "\t%.*e\n", DOUBLE_PRECISION, value); +} + + +static void +fileAddComplexValue(FILE *fp, bool bin, IFcomplex value) +{ + if (bin) { + rowbuf[column++] = value.real; + rowbuf[column++] = value.imag; + } else { + fprintf(fp, "\t%.*e,%.*e\n", DOUBLE_PRECISION, value.real, + DOUBLE_PRECISION, value.imag); + } +} + + +/* ARGSUSED */ /* until some code gets written */ +static void +fileEndPoint(FILE *fp, bool bin) +{ + /* write row buffer to file */ + /* otherwise the data has already been written */ + + if (bin) + fwrite(rowbuf, sizeof(double), rowbuflen, fp); +} + + +/* Here's the hack... Run back and fill in the number of points. */ + +static void +fileEnd(runDesc *run) +{ +/* 10.Mar.2017 - RM - Check if any orphan test benches are running. If any are + * found, force them to exit. + */ + + nghdl_orphan_tb(); + +/* End 10.Mar.2017 */ + + if (run->fp != stdout) { + long place = ftell(run->fp); + fseek(run->fp, run->pointPos, SEEK_SET); + fprintf(run->fp, "%d", run->pointCount); + fprintf(stdout, "\nNo. of Data Rows : %d\n", run->pointCount); + fseek(run->fp, place, SEEK_SET); + } else { + /* Yet another hack-around */ + fprintf(stderr, "@@@ %ld %d\n", run->pointPos, run->pointCount); + } + + fflush(run->fp); + + if (run->binary) { + /* deallocate row buffer */ + tfree(rowbuf); + } +} + + +/* The plot maintenance routines. */ + +static void +plotInit(runDesc *run) +{ + struct plot *pl = plot_alloc(run->type); + char buf[100]; + struct dvec *v; + dataDesc *dd; + int i; + + pl->pl_title = copy(run->name); + pl->pl_name = copy(run->type); + pl->pl_date = copy(datestring()); + pl->pl_ndims = 0; + plot_new(pl); + plot_setcur(pl->pl_typename); + run->runPlot = pl; + + /* This is a hack. */ + /* if any of them complex, make them all complex */ + run->isComplex = FALSE; + for (i = 0; i < run->numData; i++) + if (run->data[i].type == IF_COMPLEX) + run->isComplex = TRUE; + + for (i = 0; i < run->numData; i++) { + dd = &run->data[i]; + v = alloc(struct dvec); + if (isdigit(*dd->name)) { + (void) sprintf(buf, "V(%s)", dd->name); + v->v_name = copy(buf); + } else { + v->v_name = copy(dd->name); + } + if (substring("#branch", v->v_name)) + v->v_type = SV_CURRENT; + else if (cieq(v->v_name, "time")) + v->v_type = SV_TIME; + else if (cieq(v->v_name, "frequency")) + v->v_type = SV_FREQUENCY; + else if (cieq(v->v_name, "onoise_spectrum")) + v->v_type = SV_OUTPUT_N_DENS; + else if (cieq(v->v_name, "onoise_integrated")) + v->v_type = SV_OUTPUT_NOISE; + else if (cieq(v->v_name, "inoise_spectrum")) + v->v_type = SV_INPUT_N_DENS; + else if (cieq(v->v_name, "inoise_integrated")) + v->v_type = SV_INPUT_NOISE; + else if (cieq(v->v_name, "temp-sweep")) + v->v_type = SV_TEMP; + else if (cieq(v->v_name, "res-sweep")) + v->v_type = SV_RES; + else if ((*(v->v_name) == '@') && (substring("[g", v->v_name))) + v->v_type = SV_ADMITTANCE; + else if ((*(v->v_name) == '@') && (substring("[c", v->v_name))) + v->v_type = SV_CAPACITANCE; + else if ((*(v->v_name) == '@') && (substring("[i", v->v_name))) + v->v_type = SV_CURRENT; + else if ((*(v->v_name) == '@') && (substring("[q", v->v_name))) + v->v_type = SV_CHARGE; + else + v->v_type = SV_VOLTAGE; + v->v_length = 0; + v->v_scale = NULL; + if (!run->isComplex) { + v->v_flags = VF_REAL; + v->v_realdata = NULL; + } else { + v->v_flags = VF_COMPLEX; + v->v_compdata = NULL; + } + + v->v_flags |= VF_PERMANENT; + + vec_new(v); + dd->vec = v; + } +} + + +static void +plotAddRealValue(dataDesc *desc, double value) +{ + struct dvec *v = desc->vec; + + if (isreal(v)) { + v->v_realdata = TREALLOC(double, v->v_realdata, v->v_length + 1); + v->v_realdata[v->v_length] = value; + } else { + /* a real parading as a VF_COMPLEX */ + v->v_compdata = TREALLOC(ngcomplex_t, v->v_compdata, v->v_length + 1); + v->v_compdata[v->v_length].cx_real = value; + v->v_compdata[v->v_length].cx_imag = 0.0; + } + + v->v_length++; + v->v_dims[0] = v->v_length; /* va, must be updated */ +} + + +static void +plotAddComplexValue(dataDesc *desc, IFcomplex value) +{ + struct dvec *v = desc->vec; + + v->v_compdata = TREALLOC(ngcomplex_t, v->v_compdata, v->v_length + 1); + v->v_compdata[v->v_length].cx_real = value.real; + v->v_compdata[v->v_length].cx_imag = value.imag; + + v->v_length++; + v->v_dims[0] = v->v_length; /* va, must be updated */ +} + + +/* ARGSUSED */ /* until some code gets written */ +static void +plotEnd(runDesc *run) +{ +/* 10.Mar.2017 - RM */ + nghdl_orphan_tb(); +/* End 10.Mar.2017 */ + + fprintf(stderr, "\n"); + fprintf(stdout, "\nNo. of Data Rows : %d\n", run->pointCount); +} + +/* ParseSpecial takes something of the form "@name[param,index]" and rips + * out name, param, andstrchr. + */ + +static bool +parseSpecial(char *name, char *dev, char *param, char *ind) +{ + char *s; + + *dev = *param = *ind = '\0'; + + if (*name != '@') + return FALSE; + name++; + + s = dev; + while (*name && (*name != '[')) + *s++ = *name++; + *s = '\0'; + + if (!*name) + return TRUE; + name++; + + s = param; + while (*name && (*name != ',') && (*name != ']')) + *s++ = *name++; + *s = '\0'; + + if (*name == ']') + return (!name[1] ? TRUE : FALSE); + else if (!*name) + return FALSE; + name++; + + s = ind; + while (*name && (*name != ']')) + *s++ = *name++; + *s = '\0'; + + if (*name && !name[1]) + return TRUE; + else + return FALSE; +} + + +/* This routine must match two names with or without a V() around them. */ + +static bool +name_eq(char *n1, char *n2) +{ + char buf1[BSIZE_SP], buf2[BSIZE_SP], *s; + + if ((s = strchr(n1, '(')) != NULL) { + strcpy(buf1, s); + if ((s = strchr(buf1, ')')) == NULL) + return FALSE; + *s = '\0'; + n1 = buf1; + } + + if ((s = strchr(n2, '(')) != NULL) { + strcpy(buf2, s); + if ((s = strchr(buf2, ')')) == NULL) + return FALSE; + *s = '\0'; + n2 = buf2; + } + + return (strcmp(n1, n2) ? FALSE : TRUE); +} + + +static bool +getSpecial(dataDesc *desc, runDesc *run, IFvalue *val) +{ + IFvalue selector; + struct variable *vv; + + selector.iValue = desc->specIndex; + if (INPaName(desc->specParamName, val, run->circuit, &desc->specType, + desc->specName, &desc->specFast, ft_sim, &desc->type, + &selector) == OK) { + desc->type &= (IF_REAL | IF_COMPLEX); /* mask out other bits */ + return TRUE; + } + + if ((vv = if_getstat(run->circuit, &desc->name[1])) != NULL) { + /* skip @ sign */ + desc->type = IF_REAL; + if (vv->va_type == CP_REAL) + val->rValue = vv->va_real; + else if (vv->va_type == CP_NUM) + val->rValue = vv->va_num; + else if (vv->va_type == CP_BOOL) + val->rValue = (vv->va_bool ? 1.0 : 0.0); + else + return FALSE; /* not a real */ + tfree(vv); + return TRUE; + } + + return FALSE; +} + + +static void +freeRun(runDesc *run) +{ + int i; + + for (i = 0; i < run->numData; i++) { + tfree(run->data[i].name); + tfree(run->data[i].specParamName); + } + + tfree(run->data); + tfree(run->type); + tfree(run->name); + + tfree(run); +} + + +int +OUTstopnow(void) +{ + if (ft_intrpt || shouldstop) { + ft_intrpt = shouldstop = FALSE; + return (1); + } + + return (0); +} + + +/* Print out error messages. */ + +static struct mesg { + char *string; + long flag; +} msgs[] = { + { "Warning", ERR_WARNING } , + { "Fatal error", ERR_FATAL } , + { "Panic", ERR_PANIC } , + { "Note", ERR_INFO } , + { NULL, 0 } +}; + + +void +OUTerror(int flags, char *format, IFuid *names) +{ + struct mesg *m; + char buf[BSIZE_SP], *s, *bptr; + int nindex = 0; + + if ((flags == ERR_INFO) && cp_getvar("printinfo", CP_BOOL, NULL)) + return; + + for (m = msgs; m->flag; m++) + if (flags & m->flag) + fprintf(cp_err, "%s: ", m->string); + + for (s = format, bptr = buf; *s; s++) { + if (*s == '%' && (s == format || s[-1] != '%') && s[1] == 's') { + if (names[nindex]) + strcpy(bptr, names[nindex]); + else + strcpy(bptr, "(null)"); + bptr += strlen(bptr); + s++; + nindex++; + } else { + *bptr++ = *s; + } + } + + *bptr = '\0'; + fprintf(cp_err, "%s\n", buf); + fflush(cp_err); +} diff --git a/src/.OfflineFiles/TO-220-3_Vertical.kicad_mod b/src/.OfflineFiles/TO-220-3_Vertical.kicad_mod new file mode 100644 index 00000000..379fbf9d --- /dev/null +++ b/src/.OfflineFiles/TO-220-3_Vertical.kicad_mod @@ -0,0 +1,39 @@ +(module TO-220-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) + (descr "TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf") + (tags "TO-220-3 Vertical RM 2.54mm") + (fp_text reference REF** (at 2.54 -4.27) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value TO-220-3_Vertical (at 2.54 2.5) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.46 -3.15) (end -2.46 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -2.46 1.25) (end 7.54 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 7.54 1.25) (end 7.54 -3.15) (layer F.Fab) (width 0.1)) + (fp_line (start 7.54 -3.15) (end -2.46 -3.15) (layer F.Fab) (width 0.1)) + (fp_line (start -2.46 -1.88) (end 7.54 -1.88) (layer F.Fab) (width 0.1)) + (fp_line (start 0.69 -3.15) (end 0.69 -1.88) (layer F.Fab) (width 0.1)) + (fp_line (start 4.39 -3.15) (end 4.39 -1.88) (layer F.Fab) (width 0.1)) + (fp_line (start -2.58 -3.27) (end 7.66 -3.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.58 1.371) (end 7.66 1.371) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.58 -3.27) (end -2.58 1.371) (layer F.SilkS) (width 0.12)) + (fp_line (start 7.66 -3.27) (end 7.66 1.371) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.58 -1.76) (end 7.66 -1.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.69 -3.27) (end 0.69 -1.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.391 -3.27) (end 4.391 -1.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.71 -3.4) (end -2.71 1.51) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.71 1.51) (end 7.79 1.51) (layer F.CrtYd) (width 0.05)) + (fp_line (start 7.79 1.51) (end 7.79 -3.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 7.79 -3.4) (end -2.71 -3.4) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole rect (at 0 0) (size 1.905 2) (drill 1.1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 2.54 0) (size 1.905 2) (drill 1.1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 5.08 0) (size 1.905 2) (drill 1.1) (layers *.Cu *.Mask)) + (fp_text user %R (at 2.54 -4.27) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-220-3_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +)
\ No newline at end of file diff --git a/src/.OfflineFiles/TerminalBlock_Altech_AK300-2_P5.00mm.kicad_mod b/src/.OfflineFiles/TerminalBlock_Altech_AK300-2_P5.00mm.kicad_mod new file mode 100644 index 00000000..49a28291 --- /dev/null +++ b/src/.OfflineFiles/TerminalBlock_Altech_AK300-2_P5.00mm.kicad_mod @@ -0,0 +1,116 @@ +(module TerminalBlock_Altech_AK300-2_P5.00mm (layer F.Cu) (tedit 59FF0306) + (descr "Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf") + (tags "Altech AK300 terminal block pitch 5.0mm") + (fp_text reference REF** (at -1.92 -6.99) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value TerminalBlock_Altech_AK300-2_P5.00mm (at 2.78 7.75) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 2.5 -2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.65 -6.3) (end -2.65 6.3) (layer F.SilkS) (width 0.12)) + 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3.39 -4.45) (end 6.44 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 3.52 -4.32) (end 6.56 -4.95) (layer F.Fab) (width 0.1)) + (fp_line (start -1.62 -4.45) (end 1.44 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -1.49 -4.32) (end 1.56 -4.95) (layer F.Fab) (width 0.1)) + (fp_line (start -2.02 -0.25) (end -1.64 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 2.04 -0.25) (end 1.66 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.66 -0.25) (end -1.64 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -2.58 -0.64) (end -1.64 -0.64) (layer F.Fab) (width 0.1)) + (fp_line (start -1.64 -0.64) (end 1.66 -0.64) (layer F.Fab) (width 0.1)) + (fp_line (start 1.66 -0.64) (end 3.36 -0.64) (layer F.Fab) (width 0.1)) + (fp_line (start 7.61 -0.64) (end 6.67 -0.64) (layer F.Fab) (width 0.1)) + (fp_line (start 6.67 -0.64) (end 3.36 -0.64) (layer F.Fab) (width 0.1)) + (fp_line (start 7.05 -0.25) (end 6.67 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 2.98 -0.25) (end 3.36 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 3.36 -0.25) (end 6.67 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -2.83 -6.47) (end 8.36 -6.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.83 -6.47) (end -2.83 6.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.36 6.47) (end 8.36 -6.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.36 6.47) (end -2.83 6.47) (layer F.CrtYd) (width 0.05)) + (fp_arc (start 6.03 -4.59) (end 6.54 -5.05) (angle 90.5) (layer F.Fab) (width 0.1)) + (fp_arc (start 5.07 -6.07) (end 6.53 -4.12) (angle 75.5) (layer F.Fab) (width 0.1)) + (fp_arc (start 4.99 -3.71) (end 3.39 -5) (angle 100) (layer F.Fab) (width 0.1)) + (fp_arc (start 3.87 -4.65) (end 3.58 -4.13) (angle 104.2) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.03 -4.59) (end 1.53 -5.05) (angle 90.5) (layer F.Fab) (width 0.1)) + (fp_arc (start 0.06 -6.07) (end 1.53 -4.12) (angle 75.5) (layer F.Fab) (width 0.1)) + (fp_arc (start -0.01 -3.71) (end -1.62 -5) (angle 100) (layer F.Fab) (width 0.1)) + (fp_arc (start -1.13 -4.65) (end -1.42 -4.13) (angle 104.2) (layer F.Fab) (width 0.1)) + (pad 1 thru_hole rect (at 0 0) (size 1.98 3.96) (drill 1.32) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 5 0) (size 1.98 3.96) (drill 1.32) (layers *.Cu *.Mask)) + (model ${KISYS3DMOD}/TerminalBlock.3dshapes/TerminalBlock_Altech_AK300-2_P5.00mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/src/.OfflineFiles/fp-lib-table b/src/.OfflineFiles/fp-lib-table new file mode 100644 index 00000000..ff605eaf --- /dev/null +++ b/src/.OfflineFiles/fp-lib-table @@ -0,0 +1,92 @@ +(fp_lib_table + (lib (name Battery_Holders)(type KiCad)(uri ${KISYSMOD}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders")) + (lib (name Buttons_Switches_SMD)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount")) + (lib (name Buttons_Switches_THT)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole")) + (lib (name Buzzers_Beepers)(type KiCad)(uri ${KISYSMOD}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices")) + (lib (name Capacitors_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount")) + (lib (name Capacitors_Tantalum_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount")) + (lib (name Capacitors_THT)(type KiCad)(uri ${KISYSMOD}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole")) + (lib (name Connectors_Card)(type KiCad)(uri ${KISYSMOD}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders")) + (lib (name Connectors_Harwin)(type KiCad)(uri ${KISYSMOD}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com")) + (lib (name Connectors_HDMI)(type KiCad)(uri ${KISYSMOD}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints")) + (lib (name Connectors_Hirose)(type KiCad)(uri ${KISYSMOD}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com")) + (lib (name Connectors_IEC_DIN)(type KiCad)(uri ${KISYSMOD}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints")) + (lib (name Connectors_JAE)(type KiCad)(uri ${KISYSMOD}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors")) + (lib (name Connectors_JST)(type KiCad)(uri ${KISYSMOD}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com")) + (lib (name Connectors_Mini-Universal)(type KiCad)(uri ${KISYSMOD}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok)) + (lib (name Connectors_Molex)(type KiCad)(uri ${KISYSMOD}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com")) + (lib (name Connectors_Multicomp)(type KiCad)(uri ${KISYSMOD}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints")) + (lib (name Connectors_Phoenix)(type KiCad)(uri ${KISYSMOD}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints")) + (lib (name Connectors_Samtec)(type KiCad)(uri ${KISYSMOD}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints")) + (lib (name Connectors_TE-Connectivity)(type KiCad)(uri ${KISYSMOD}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com")) + (lib (name Connectors_Terminal_Blocks)(type KiCad)(uri ${KISYSMOD}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors")) + (lib (name Connectors_WAGO)(type KiCad)(uri ${KISYSMOD}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com")) + (lib (name Connectors_USB)(type KiCad)(uri ${KISYSMOD}/Connectors_USB.pretty)(options "")(descr "USB connector footprints")) + (lib (name Connectors)(type KiCad)(uri ${KISYSMOD}/Connectors.pretty)(options "")(descr "Assorted connector footprints")) + (lib (name Converters_DCDC_ACDC)(type KiCad)(uri ${KISYSMOD}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules")) + (lib (name Crystals)(type KiCad)(uri ${KISYSMOD}/Crystals.pretty)(options "")(descr "Crystals and oscillators")) + (lib (name Diodes_SMD)(type KiCad)(uri ${KISYSMOD}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount")) + (lib (name Diodes_THT)(type KiCad)(uri ${KISYSMOD}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole")) + (lib (name Displays_7-Segment)(type KiCad)(uri ${KISYSMOD}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays")) + (lib (name Displays)(type KiCad)(uri ${KISYSMOD}/Displays.pretty)(options "")(descr "Display modules")) + (lib (name Enclosures)(type KiCad)(uri ${KISYSMOD}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings")) + (lib (name EuroBoard_Outline)(type KiCad)(uri ${KISYSMOD}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed")) + (lib (name Fiducials)(type KiCad)(uri ${KISYSMOD}/Fiducials.pretty)(options "")(descr "Fiducial markings")) + (lib (name Fuse_Holders_and_Fuses)(type KiCad)(uri ${KISYSMOD}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders")) + (lib (name Hall-Effect_Transducers_LEM)(type KiCad)(uri ${KISYSMOD}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers")) + (lib (name Heatsinks)(type KiCad)(uri ${KISYSMOD}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products")) + (lib (name Housings_BGA)(type KiCad)(uri ${KISYSMOD}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)")) + (lib (name Housings_CSP)(type KiCad)(uri ${KISYSMOD}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)")) + (lib (name Housings_DFN_QFN)(type KiCad)(uri ${KISYSMOD}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN")) + (lib (name Housings_DIP)(type KiCad)(uri ${KISYSMOD}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP")) + (lib (name Housings_LCC)(type KiCad)(uri ${KISYSMOD}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)")) + (lib (name Housings_LGA)(type KiCad)(uri ${KISYSMOD}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)")) + (lib (name Housings_PGA)(type KiCad)(uri ${KISYSMOD}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)")) + (lib (name Housings_QFP)(type KiCad)(uri ${KISYSMOD}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)")) + (lib (name Housings_SIP)(type KiCad)(uri ${KISYSMOD}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)")) + (lib (name Housings_SOIC)(type KiCad)(uri ${KISYSMOD}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)")) + (lib (name Housings_SON)(type KiCad)(uri ${KISYSMOD}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)")) + (lib (name Housings_SSOP)(type KiCad)(uri ${KISYSMOD}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages")) + (lib (name Inductors_SMD)(type KiCad)(uri ${KISYSMOD}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount")) + (lib (name Inductors_THT)(type KiCad)(uri ${KISYSMOD}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole")) + (lib (name IR-DirectFETs)(type KiCad)(uri ${KISYSMOD}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier")) + (lib (name LEDs)(type KiCad)(uri ${KISYSMOD}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)")) + (lib (name Measurement_Points)(type KiCad)(uri ${KISYSMOD}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment")) + (lib (name Measurement_Scales)(type KiCad)(uri ${KISYSMOD}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges")) + (lib (name Microwave)(type KiCad)(uri ${KISYSMOD}/Microwave.pretty)(options "")(descr Microwave)) + (lib (name Modules)(type KiCad)(uri ${KISYSMOD}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module")) + (lib (name Mounting_Holes)(type KiCad)(uri ${KISYSMOD}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners")) + (lib (name Opto-Devices)(type KiCad)(uri ${KISYSMOD}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices")) + (lib (name Oscillators)(type KiCad)(uri ${KISYSMOD}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules")) + (lib (name PFF_PSF_PSS_Leadforms)(type KiCad)(uri ${KISYSMOD}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages")) + (lib (name Pin_Headers)(type KiCad)(uri ${KISYSMOD}/Pin_Headers.pretty)(options "")(descr "Male pin headers")) + (lib (name Potentiometers)(type KiCad)(uri ${KISYSMOD}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors")) + (lib (name Power_Integrations)(type KiCad)(uri ${KISYSMOD}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints")) + (lib (name Relays_SMD)(type KiCad)(uri ${KISYSMOD}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages")) + (lib (name Relays_THT)(type KiCad)(uri ${KISYSMOD}/Relays_THT.pretty)(options "")(descr "Through hole relay packages")) + (lib (name Resistors_SMD)(type KiCad)(uri ${KISYSMOD}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount")) + (lib (name Resistors_THT)(type KiCad)(uri ${KISYSMOD}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole")) + (lib (name Resistors_Universal)(type KiCad)(uri ${KISYSMOD}/Resistors_Universal.pretty)(options "")(descr Experimental)) + (lib (name RF_Antennas)(type KiCad)(uri ${KISYSMOD}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints")) + (lib (name RF_Modules)(type KiCad)(uri ${KISYSMOD}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules")) + (lib (name Shielding_Cabinets)(type KiCad)(uri ${KISYSMOD}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields")) + (lib (name SMD_Packages)(type KiCad)(uri ${KISYSMOD}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries")) + (lib (name Socket_Strips)(type KiCad)(uri ${KISYSMOD}/Socket_Strips.pretty)(options "")(descr "Female socket strips")) + (lib (name Sockets)(type KiCad)(uri ${KISYSMOD}/Sockets.pretty)(options "")(descr "IC sockets")) + (lib (name Symbols)(type KiCad)(uri ${KISYSMOD}/Symbols.pretty)(options "")(descr "PCB symbols")) + (lib (name TerminalBlocks_Phoenix)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks")) + (lib (name TerminalBlocks_WAGO)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks")) + (lib (name TO_SOT_Packages_SMD)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages")) + (lib (name TO_SOT_Packages_THT)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages")) + (lib (name Transformers_SMD)(type KiCad)(uri ${KISYSMOD}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers")) + (lib (name Transformers_THT)(type KiCad)(uri ${KISYSMOD}/Transformers_THT.pretty)(options "")(descr "Through hole transformers")) + (lib (name Transistors_OldSowjetAera)(type KiCad)(uri ${KISYSMOD}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors")) + (lib (name Valves)(type KiCad)(uri ${KISYSMOD}/Valves.pretty)(options "")(descr Valves)) + (lib (name Varistors)(type KiCad)(uri ${KISYSMOD}/Varistors.pretty)(options "")(descr Varistors)) + (lib (name Wire_Connections_Bridges)(type KiCad)(uri ${KISYSMOD}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points")) + (lib (name Wire_Pads)(type KiCad)(uri ${KISYSMOD}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points")) + (lib (name Choke_Common-Mode_Wurth)(type KiCad)(uri "$(KISYSMOD)Choke_Common-Mode_Wurth.pretty")(options "")(descr "")) + (lib (name Choke_Radial_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Radial_ThroughHole.pretty")(options "")(descr "")) + (lib (name Choke_SMD)(type KiCad)(uri "$(KISYSMOD)Choke_SMD.pretty")(options "")(descr "")) + (lib (name Choke_Toroid_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Toroid_ThroughHole.pretty")(options "")(descr "")) +) diff --git a/src/.OfflineFiles/fp-lib-table-online b/src/.OfflineFiles/fp-lib-table-online new file mode 100644 index 00000000..5b4081ff --- /dev/null +++ b/src/.OfflineFiles/fp-lib-table-online @@ -0,0 +1,88 @@ +(fp_lib_table + (lib (name Battery_Holders)(type Github)(uri ${KIGITHUB}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders")) + (lib (name Buttons_Switches_SMD)(type Github)(uri ${KIGITHUB}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount")) + (lib (name Buttons_Switches_THT)(type Github)(uri ${KIGITHUB}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole")) + (lib (name Buzzers_Beepers)(type Github)(uri ${KIGITHUB}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices")) + (lib (name Capacitors_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount")) + (lib (name Capacitors_Tantalum_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount")) + (lib (name Capacitors_THT)(type Github)(uri ${KIGITHUB}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole")) + (lib (name Connectors_Card)(type Github)(uri ${KIGITHUB}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders")) + (lib (name Connectors_Harwin)(type Github)(uri ${KIGITHUB}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com")) + (lib (name Connectors_HDMI)(type Github)(uri ${KIGITHUB}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints")) + (lib (name Connectors_Hirose)(type Github)(uri ${KIGITHUB}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com")) + (lib (name Connectors_IEC_DIN)(type Github)(uri ${KIGITHUB}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints")) + (lib (name Connectors_JAE)(type Github)(uri ${KIGITHUB}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors")) + (lib (name Connectors_JST)(type Github)(uri ${KIGITHUB}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com")) + (lib (name Connectors_Mini-Universal)(type Github)(uri ${KIGITHUB}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok)) + (lib (name Connectors_Molex)(type Github)(uri ${KIGITHUB}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com")) + (lib (name Connectors_Multicomp)(type Github)(uri ${KIGITHUB}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints")) + (lib (name Connectors_Phoenix)(type Github)(uri ${KIGITHUB}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints")) + (lib (name Connectors_Samtec)(type Github)(uri ${KIGITHUB}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints")) + (lib (name Connectors_TE-Connectivity)(type Github)(uri ${KIGITHUB}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com")) + (lib (name Connectors_Terminal_Blocks)(type Github)(uri ${KIGITHUB}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors")) + (lib (name Connectors_WAGO)(type Github)(uri ${KIGITHUB}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com")) + (lib (name Connectors_USB)(type Github)(uri ${KIGITHUB}/Connectors_USB.pretty)(options "")(descr "USB connector footprints")) + (lib (name Connectors)(type Github)(uri ${KIGITHUB}/Connectors.pretty)(options "")(descr "Assorted connector footprints")) + (lib (name Converters_DCDC_ACDC)(type Github)(uri ${KIGITHUB}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules")) + (lib (name Crystals)(type Github)(uri ${KIGITHUB}/Crystals.pretty)(options "")(descr "Crystals and oscillators")) + (lib (name Diodes_SMD)(type Github)(uri ${KIGITHUB}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount")) + (lib (name Diodes_THT)(type Github)(uri ${KIGITHUB}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole")) + (lib (name Displays_7-Segment)(type Github)(uri ${KIGITHUB}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays")) + (lib (name Displays)(type Github)(uri ${KIGITHUB}/Displays.pretty)(options "")(descr "Display modules")) + (lib (name Enclosures)(type Github)(uri ${KIGITHUB}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings")) + (lib (name EuroBoard_Outline)(type Github)(uri ${KIGITHUB}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed")) + (lib (name Fiducials)(type Github)(uri ${KIGITHUB}/Fiducials.pretty)(options "")(descr "Fiducial markings")) + (lib (name Fuse_Holders_and_Fuses)(type Github)(uri ${KIGITHUB}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders")) + (lib (name Hall-Effect_Transducers_LEM)(type Github)(uri ${KIGITHUB}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers")) + (lib (name Heatsinks)(type Github)(uri ${KIGITHUB}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products")) + (lib (name Housings_BGA)(type Github)(uri ${KIGITHUB}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)")) + (lib (name Housings_CSP)(type Github)(uri ${KIGITHUB}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)")) + (lib (name Housings_DFN_QFN)(type Github)(uri ${KIGITHUB}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN")) + (lib (name Housings_DIP)(type Github)(uri ${KIGITHUB}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP")) + (lib (name Housings_LCC)(type Github)(uri ${KIGITHUB}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)")) + (lib (name Housings_LGA)(type Github)(uri ${KIGITHUB}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)")) + (lib (name Housings_PGA)(type Github)(uri ${KIGITHUB}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)")) + (lib (name Housings_QFP)(type Github)(uri ${KIGITHUB}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)")) + (lib (name Housings_SIP)(type Github)(uri ${KIGITHUB}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)")) + (lib (name Housings_SOIC)(type Github)(uri ${KIGITHUB}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)")) + (lib (name Housings_SON)(type Github)(uri ${KIGITHUB}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)")) + (lib (name Housings_SSOP)(type Github)(uri ${KIGITHUB}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages")) + (lib (name Inductors_SMD)(type Github)(uri ${KIGITHUB}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount")) + (lib (name Inductors_THT)(type Github)(uri ${KIGITHUB}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole")) + (lib (name IR-DirectFETs)(type Github)(uri ${KIGITHUB}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier")) + (lib (name LEDs)(type Github)(uri ${KIGITHUB}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)")) + (lib (name Measurement_Points)(type Github)(uri ${KIGITHUB}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment")) + (lib (name Measurement_Scales)(type Github)(uri ${KIGITHUB}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges")) + (lib (name Microwave)(type Github)(uri ${KIGITHUB}/Microwave.pretty)(options "")(descr "Microwave")) + (lib (name Modules)(type Github)(uri ${KIGITHUB}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module")) + (lib (name Mounting_Holes)(type Github)(uri ${KIGITHUB}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners")) + (lib (name Opto-Devices)(type Github)(uri ${KIGITHUB}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices")) + (lib (name Oscillators)(type Github)(uri ${KIGITHUB}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules")) + (lib (name PFF_PSF_PSS_Leadforms)(type Github)(uri ${KIGITHUB}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages")) + (lib (name Pin_Headers)(type Github)(uri ${KIGITHUB}/Pin_Headers.pretty)(options "")(descr "Male pin headers")) + (lib (name Potentiometers)(type Github)(uri ${KIGITHUB}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors")) + (lib (name Power_Integrations)(type Github)(uri ${KIGITHUB}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints")) + (lib (name Relays_SMD)(type Github)(uri ${KIGITHUB}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages")) + (lib (name Relays_THT)(type Github)(uri ${KIGITHUB}/Relays_THT.pretty)(options "")(descr "Through hole relay packages")) + (lib (name Resistors_SMD)(type Github)(uri ${KIGITHUB}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount")) + (lib (name Resistors_THT)(type Github)(uri ${KIGITHUB}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole")) + (lib (name Resistors_Universal)(type Github)(uri ${KIGITHUB}/Resistors_Universal.pretty)(options "")(descr Experimental)) + (lib (name RF_Antennas)(type Github)(uri ${KIGITHUB}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints")) + (lib (name RF_Modules)(type Github)(uri ${KIGITHUB}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules")) + (lib (name Shielding_Cabinets)(type Github)(uri ${KIGITHUB}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields")) + (lib (name SMD_Packages)(type Github)(uri ${KIGITHUB}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries")) + (lib (name Socket_Strips)(type Github)(uri ${KIGITHUB}/Socket_Strips.pretty)(options "")(descr "Female socket strips")) + (lib (name Sockets)(type Github)(uri ${KIGITHUB}/Sockets.pretty)(options "")(descr "IC sockets")) + (lib (name Symbols)(type Github)(uri ${KIGITHUB}/Symbols.pretty)(options "")(descr "PCB symbols")) + (lib (name TerminalBlocks_Phoenix)(type Github)(uri ${KIGITHUB}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks")) + (lib (name TerminalBlocks_WAGO)(type Github)(uri ${KIGITHUB}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks")) + (lib (name TO_SOT_Packages_SMD)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages")) + (lib (name TO_SOT_Packages_THT)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages")) + (lib (name Transformers_SMD)(type Github)(uri ${KIGITHUB}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers")) + (lib (name Transformers_THT)(type Github)(uri ${KIGITHUB}/Transformers_THT.pretty)(options "")(descr "Through hole transformers")) + (lib (name Transistors_OldSowjetAera)(type Github)(uri ${KIGITHUB}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors")) + (lib (name Valves)(type Github)(uri ${KIGITHUB}/Valves.pretty)(options "")(descr "Valves")) + (lib (name Varistors)(type Github)(uri ${KIGITHUB}/Varistors.pretty)(options "")(descr "Varistors")) + (lib (name Wire_Connections_Bridges)(type Github)(uri ${KIGITHUB}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points")) + (lib (name Wire_Pads)(type Github)(uri ${KIGITHUB}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points")) +) diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib new file mode 100644 index 00000000..e16831e4 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib @@ -0,0 +1,77 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.bak b/src/SubcircuitLibrary/2bitmul/2bitmul.bak new file mode 100644 index 00000000..0ee707fe --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.bak @@ -0,0 +1,360 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:2bitmul-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 5C7FC048 +P 8150 2950 +F 0 "U5" H 8150 2950 60 0000 C CNN +F 1 "d_and" H 8200 3050 60 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 1 8150 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FC0BC +P 7450 2950 +F 0 "U4" H 7450 2950 60 0000 C CNN +F 1 "d_and" H 7500 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0000 C CNN +F 3 "" H 7450 2950 60 0000 C CNN + 1 7450 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C7FC0F4 +P 6950 2950 +F 0 "U3" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 5C7FC11D +P 6400 2950 +F 0 "U2" H 6400 2950 60 0000 C CNN +F 1 "d_and" H 6450 3050 60 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 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+$EndComp +$Comp +L PORT U1 +U 8 1 5C7FC698 +P 6700 6200 +F 0 "U1" H 6750 6300 30 0000 C CNN +F 1 "PORT" H 6700 6200 30 0000 C CNN +F 2 "" H 6700 6200 60 0000 C CNN +F 3 "" H 6700 6200 60 0000 C CNN + 8 6700 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7FC6EC +P 10050 1900 +F 0 "U1" H 10100 2000 30 0000 C CNN +F 1 "PORT" H 10050 1900 30 0000 C CNN +F 2 "" H 10050 1900 60 0000 C CNN +F 3 "" H 10050 1900 60 0000 C CNN + 1 10050 1900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FC815 +P 10050 1550 +F 0 "U1" H 10100 1650 30 0000 C CNN +F 1 "PORT" H 10050 1550 30 0000 C CNN +F 2 "" H 10050 1550 60 0000 C CNN +F 3 "" H 10050 1550 60 0000 C CNN + 2 10050 1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FC857 +P 10050 1200 +F 0 "U1" H 10100 1300 30 0000 C CNN +F 1 "PORT" H 10050 1200 30 0000 C CNN +F 2 "" H 10050 1200 60 0000 C CNN +F 3 "" H 10050 1200 60 0000 C CNN + 3 10050 1200 + -1 0 0 1 +$EndComp +Connection ~ 8250 2250 +Wire Wire Line + 7900 1500 7900 2150 +Wire Wire Line + 7900 2150 7550 2150 +Connection ~ 7550 2450 +Wire Wire Line + 7550 1400 7550 2100 +Wire Wire Line + 7550 2100 7450 2100 +Connection ~ 7450 2350 +Wire Wire Line + 7200 1300 7200 2100 +Wire Wire Line + 7200 2100 6800 2100 +Wire Wire Line + 6800 2100 6800 2350 +Connection ~ 6800 2350 +Wire Wire Line + 8200 3400 8200 5050 +$Comp +L PORT U1 +U 4 1 5C7FC898 +P 10100 850 +F 0 "U1" H 10150 950 30 0000 C CNN +F 1 "PORT" H 10100 850 30 0000 C CNN +F 2 "" H 10100 850 60 0000 C CNN +F 3 "" H 10100 850 60 0000 C CNN + 4 10100 850 + -1 0 0 1 +$EndComp +$Comp +L adc_bridge_4 U? +U 1 1 5C80A2A9 +P 8950 1400 +F 0 "U?" H 8950 1400 60 0000 C CNN +F 1 "adc_bridge_4" H 8950 1700 60 0000 C CNN +F 2 "" H 8950 1400 60 0000 C CNN +F 3 "" H 8950 1400 60 0000 C CNN + 1 8950 1400 + -1 0 0 1 +$EndComp +Wire Wire Line + 8400 1600 8250 1600 +Wire Wire Line + 8400 1500 7900 1500 +Wire Wire Line + 8400 1400 7550 1400 +Wire Wire Line + 8400 1300 7200 1300 +Wire Wire Line + 9800 1900 9800 1600 +Wire Wire Line + 9800 1600 9500 1600 +Wire Wire Line + 9800 1550 9800 1500 +Wire Wire Line + 9800 1500 9500 1500 +Wire Wire Line + 9800 1200 9800 1400 +Wire Wire Line + 9800 1400 9500 1400 +Wire Wire Line + 9850 850 9650 850 +Wire Wire Line + 9650 850 9650 1300 +Wire Wire Line + 9650 1300 9500 1300 +$Comp +L dac_bridge_4 U? +U 1 1 5C80B255 +P 7200 5600 +F 0 "U?" H 7200 5600 60 0000 C CNN +F 1 "dac_bridge_4" H 7200 5900 60 0000 C CNN +F 2 "" H 7200 5600 60 0000 C CNN +F 3 "" H 7200 5600 60 0000 C CNN + 1 7200 5600 + 0 1 1 0 +$EndComp +Wire Wire Line + 7300 5050 7300 4850 +Wire Wire Line + 7300 4850 7900 4850 +Wire Wire Line + 7900 4850 7900 4800 +Wire Wire Line + 6750 4800 6750 4900 +Wire Wire Line + 6750 4900 7200 4900 +Wire Wire Line + 7200 4900 7200 5050 +Wire Wire Line + 6150 4800 6150 5000 +Wire Wire Line + 6150 5000 7100 5000 +Wire Wire Line + 7100 5000 7100 5050 +Wire Wire Line + 8200 5050 7400 5050 +Wire Wire Line + 7400 6150 7400 6250 +Wire Wire Line + 7400 6250 7500 6250 +Wire Wire Line + 7300 6150 7300 6400 +Wire Wire Line + 7200 6150 7200 6250 +Wire Wire Line + 7200 6250 7100 6250 +Wire Wire Line + 7100 6250 7100 6450 +Wire Wire Line + 7100 6450 7050 6450 +Wire Wire Line + 6950 6200 7100 6200 +Wire Wire Line + 7100 6200 7100 6150 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir new file mode 100644 index 00000000..0f4deb6c --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir @@ -0,0 +1,17 @@ +* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and +U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and +X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder +X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT + +.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out new file mode 100644 index 00000000..71766bd8 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out @@ -0,0 +1,31 @@ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir + +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro new file mode 100644 index 00000000..eafbfb80 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.pro @@ -0,0 +1,74 @@ +update=03/07/19 09:55:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch new file mode 100644 index 00000000..0ba61912 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:2bitmul-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 5C7FC048 +P 8150 2950 +F 0 "U5" H 8150 2950 60 0000 C CNN +F 1 "d_and" H 8200 3050 60 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 1 8150 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FC0BC +P 7450 2950 +F 0 "U4" H 7450 2950 60 0000 C CNN +F 1 "d_and" H 7500 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0000 C CNN +F 3 "" H 7450 2950 60 0000 C CNN + 1 7450 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C7FC0F4 +P 6950 2950 +F 0 "U3" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 5C7FC11D +P 6400 2950 +F 0 "U2" H 6400 2950 60 0000 C CNN +F 1 "d_and" H 6450 3050 60 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 8150 2500 8150 2350 +Wire Wire Line + 8150 2350 7450 2350 +Wire Wire Line + 7450 2100 7450 2500 +Wire Wire Line + 6950 2500 6950 2350 +Wire Wire Line + 6950 2350 6400 2350 +Wire Wire Line + 6400 2350 6400 2500 +Wire Wire Line + 8250 1100 8250 2500 +Wire Wire Line + 8250 2250 7050 2250 +Wire Wire Line + 7050 2250 7050 2500 +Wire Wire Line + 7550 2150 7550 2500 +Wire Wire Line + 7550 2450 6500 2450 +Wire Wire Line + 6500 2450 6500 2500 +$Comp +L half_adder X2 +U 1 1 5C7FC23A +P 7200 3350 +F 0 "X2" H 8100 3850 60 0000 C CNN +F 1 "half_adder" H 8100 3750 60 0000 C CNN +F 2 "" H 7200 3350 60 0000 C CNN +F 3 "" H 7200 3350 60 0000 C CNN + 1 7200 3350 + 0 1 1 0 +$EndComp +$Comp +L half_adder X1 +U 1 1 5C7FC324 +P 6050 3350 +F 0 "X1" H 6950 3850 60 0000 C CNN +F 1 "half_adder" H 6950 3750 60 0000 C CNN +F 2 "" H 6050 3350 60 0000 C CNN +F 3 "" H 6050 3350 60 0000 C CNN + 1 6050 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 7500 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 3650 +Wire Wire Line + 7000 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3650 +Wire Wire Line + 7300 4800 7050 4800 +Wire Wire Line + 7050 4800 7050 3600 +Wire Wire Line + 7050 3600 6750 3600 +Wire Wire Line + 6750 3600 6750 3650 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 6450 3650 6150 3650 +$Comp +L PORT U1 +U 5 1 5C7FC4F8 +P 8200 5300 +F 0 "U1" H 8250 5400 30 0000 C CNN +F 1 "PORT" H 8200 5300 30 0000 C CNN +F 2 "" H 8200 5300 60 0000 C CNN +F 3 "" H 8200 5300 60 0000 C CNN + 5 8200 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C7FC5D7 +P 7300 5300 +F 0 "U1" H 7350 5400 30 0000 C CNN +F 1 "PORT" H 7300 5300 30 0000 C CNN +F 2 "" H 7300 5300 60 0000 C CNN +F 3 "" H 7300 5300 60 0000 C CNN + 6 7300 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7FC641 +P 6750 5150 +F 0 "U1" H 6800 5250 30 0000 C CNN +F 1 "PORT" H 6750 5150 30 0000 C CNN +F 2 "" H 6750 5150 60 0000 C CNN +F 3 "" H 6750 5150 60 0000 C CNN + 7 6750 5150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7FC698 +P 6150 5250 +F 0 "U1" H 6200 5350 30 0000 C CNN +F 1 "PORT" H 6150 5250 30 0000 C CNN +F 2 "" H 6150 5250 60 0000 C CNN +F 3 "" H 6150 5250 60 0000 C CNN + 8 6150 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7FC6EC +P 8250 850 +F 0 "U1" H 8300 950 30 0000 C CNN +F 1 "PORT" H 8250 850 30 0000 C CNN +F 2 "" H 8250 850 60 0000 C CNN +F 3 "" H 8250 850 60 0000 C CNN + 1 8250 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FC815 +P 7900 850 +F 0 "U1" H 7950 950 30 0000 C CNN +F 1 "PORT" H 7900 850 30 0000 C CNN +F 2 "" H 7900 850 60 0000 C CNN +F 3 "" H 7900 850 60 0000 C CNN + 2 7900 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FC857 +P 7550 850 +F 0 "U1" H 7600 950 30 0000 C CNN +F 1 "PORT" H 7550 850 30 0000 C CNN +F 2 "" H 7550 850 60 0000 C CNN +F 3 "" H 7550 850 60 0000 C CNN + 3 7550 850 + 0 1 1 0 +$EndComp +Connection ~ 8250 2250 +Wire Wire Line + 7900 1100 7900 2150 +Wire Wire Line + 7900 2150 7550 2150 +Connection ~ 7550 2450 +Wire Wire Line + 7550 1100 7550 2100 +Wire Wire Line + 7550 2100 7450 2100 +Connection ~ 7450 2350 +Wire Wire Line + 7200 1050 7200 2100 +Wire Wire Line + 7200 2100 6800 2100 +Wire Wire Line + 6800 2100 6800 2350 +Connection ~ 6800 2350 +Wire Wire Line + 8200 3400 8200 5050 +$Comp +L PORT U1 +U 4 1 5C7FC898 +P 7200 800 +F 0 "U1" H 7250 900 30 0000 C CNN +F 1 "PORT" H 7200 800 30 0000 C CNN +F 2 "" H 7200 800 60 0000 C CNN +F 3 "" H 7200 800 60 0000 C CNN + 4 7200 800 + 0 1 1 0 +$EndComp +Wire Wire Line + 7300 5050 7300 4850 +Wire Wire Line + 7300 4850 7900 4850 +Wire Wire Line + 7900 4850 7900 4800 +Wire Wire Line + 6750 4800 6750 4900 +Wire Wire Line + 6150 4800 6150 5000 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub new file mode 100644 index 00000000..e77495a6 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sub @@ -0,0 +1,25 @@ +* Subcircuit 2bitmul +.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 2bitmul
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml new file mode 100644 index 00000000..8a55af97 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/analysis b/src/SubcircuitLibrary/2bitmul/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.pro b/src/SubcircuitLibrary/2bitmul/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sch b/src/SubcircuitLibrary/2bitmul/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sub b/src/SubcircuitLibrary/2bitmul/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and-cache.lib b/src/SubcircuitLibrary/3_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/3_and/3_and.bak b/src/SubcircuitLibrary/3_and/3_and.bak new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/3_and/3_and.cir b/src/SubcircuitLibrary/3_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/3_and/3_and.cir.out b/src/SubcircuitLibrary/3_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/3_and/3_and.pro b/src/SubcircuitLibrary/3_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/3_and/3_and.sch b/src/SubcircuitLibrary/3_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/3_and/3_and.sub b/src/SubcircuitLibrary/3_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/analysis b/src/SubcircuitLibrary/3_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/3_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/4002-cache.lib b/src/SubcircuitLibrary/4002/4002-cache.lib new file mode 100644 index 00000000..677411a9 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4002/4002.bak b/src/SubcircuitLibrary/4002/4002.bak new file mode 100644 index 00000000..545f46fe --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.bak @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5CEE059A +P 4750 2900 +F 0 "U2" H 4750 2900 60 0000 C CNN +F 1 "d_or" H 4750 3000 60 0000 C CNN +F 2 "" H 4750 2900 60 0000 C CNN +F 3 "" H 4750 2900 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5CEE0629 +P 4750 3450 +F 0 "U3" H 4750 3450 60 0000 C CNN +F 1 "d_or" H 4750 3550 60 0000 C CNN +F 2 "" H 4750 3450 60 0000 C CNN +F 3 "" H 4750 3450 60 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CEE0663 +P 6000 3100 +F 0 "U6" H 6000 3100 60 0000 C CNN +F 1 "d_nor" H 6050 3200 60 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5400 2850 +Wire Wire Line + 5400 2850 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 5200 3400 5400 3400 +Wire Wire Line + 5400 3400 5400 3100 +Wire Wire Line + 5400 3100 5550 3100 +Wire Wire Line + 5650 5350 6050 5350 +Wire Wire Line + 5650 5550 6050 5550 +Wire Wire Line + 5650 5800 6050 5800 +Wire Wire Line + 5650 6000 6050 6000 +NoConn ~ 5650 5350 +NoConn ~ 5650 5550 +NoConn ~ 5650 5800 +NoConn ~ 5650 6000 +$Comp +L PORT U1 +U 2 1 5CEE1C41 +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 2 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE22EE +P 3900 3050 +F 0 "U1" H 3950 3150 30 0000 C CNN +F 1 "PORT" H 3900 3050 30 0000 C CNN +F 2 "" H 3900 3050 60 0000 C CNN +F 3 "" H 3900 3050 60 0000 C CNN + 3 3900 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE2322 +P 3900 3250 +F 0 "U1" H 3950 3350 30 0000 C CNN +F 1 "PORT" H 3900 3250 30 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 5 3900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE2351 +P 3900 3550 +F 0 "U1" H 3950 3650 30 0000 C CNN +F 1 "PORT" H 3900 3550 30 0000 C CNN +F 2 "" H 3900 3550 60 0000 C CNN +F 3 "" H 3900 3550 60 0000 C CNN + 4 3900 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE2387 +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2800 4300 2800 +Wire Wire Line + 4150 3050 4150 2900 +Wire Wire Line + 4150 2900 4300 2900 +Wire Wire Line + 4150 3250 4300 3250 +Wire Wire Line + 4300 3250 4300 3350 +Wire Wire Line + 4150 3550 4150 3450 +Wire Wire Line + 4150 3450 4300 3450 +Wire Wire Line + 6700 3050 6450 3050 +$Comp +L d_or U4 +U 1 1 5CEE4ED7 +P 4900 4100 +F 0 "U4" H 4900 4100 60 0000 C CNN +F 1 "d_or" H 4900 4200 60 0000 C CNN +F 2 "" H 4900 4100 60 0000 C CNN +F 3 "" H 4900 4100 60 0000 C CNN + 1 4900 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5CEE4EDD +P 4900 4650 +F 0 "U5" H 4900 4650 60 0000 C CNN +F 1 "d_or" H 4900 4750 60 0000 C CNN +F 2 "" H 4900 4650 60 0000 C CNN +F 3 "" H 4900 4650 60 0000 C CNN + 1 4900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CEE4EE3 +P 6150 4300 +F 0 "U7" H 6150 4300 60 0000 C CNN +F 1 "d_nor" H 6200 4400 60 0000 C CNN +F 2 "" H 6150 4300 60 0000 C CNN +F 3 "" H 6150 4300 60 0000 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 4200 +Wire Wire Line + 5550 4200 5700 4200 +Wire Wire Line + 5350 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 4300 +Wire Wire Line + 5550 4300 5700 4300 +$Comp +L PORT U1 +U 9 1 5CEE4EEF +P 4000 4000 +F 0 "U1" H 4050 4100 30 0000 C CNN +F 1 "PORT" H 4000 4000 30 0000 C CNN +F 2 "" H 4000 4000 60 0000 C CNN +F 3 "" H 4000 4000 60 0000 C CNN + 9 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE4EF5 +P 4050 4250 +F 0 "U1" H 4100 4350 30 0000 C CNN +F 1 "PORT" H 4050 4250 30 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 10 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE4EFB +P 4050 4450 +F 0 "U1" H 4100 4550 30 0000 C CNN +F 1 "PORT" H 4050 4450 30 0000 C CNN +F 2 "" H 4050 4450 60 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 11 4050 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE4F01 +P 4050 4750 +F 0 "U1" H 4100 4850 30 0000 C CNN +F 1 "PORT" H 4050 4750 30 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 12 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE4F07 +P 7100 4250 +F 0 "U1" H 7150 4350 30 0000 C CNN +F 1 "PORT" H 7100 4250 30 0000 C CNN +F 2 "" H 7100 4250 60 0000 C CNN +F 3 "" H 7100 4250 60 0000 C CNN + 13 7100 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 4000 4450 4000 +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4450 4100 +Wire Wire Line + 4300 4450 4450 4450 +Wire Wire Line + 4450 4450 4450 4550 +Wire Wire Line + 4300 4750 4300 4650 +Wire Wire Line + 4300 4650 4450 4650 +Wire Wire Line + 6850 4250 6600 4250 +$Comp +L PORT U1 +U 6 1 5CEE51A5 +P 6300 5350 +F 0 "U1" H 6350 5450 30 0000 C CNN +F 1 "PORT" H 6300 5350 30 0000 C CNN +F 2 "" H 6300 5350 60 0000 C CNN +F 3 "" H 6300 5350 60 0000 C CNN + 6 6300 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE522C +P 6300 5550 +F 0 "U1" H 6350 5650 30 0000 C CNN +F 1 "PORT" H 6300 5550 30 0000 C CNN +F 2 "" H 6300 5550 60 0000 C CNN +F 3 "" H 6300 5550 60 0000 C CNN + 7 6300 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5276 +P 6300 5800 +F 0 "U1" H 6350 5900 30 0000 C CNN +F 1 "PORT" H 6300 5800 30 0000 C CNN +F 2 "" H 6300 5800 60 0000 C CNN +F 3 "" H 6300 5800 60 0000 C CNN + 8 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE52C5 +P 6300 6000 +F 0 "U1" H 6350 6100 30 0000 C CNN +F 1 "PORT" H 6300 6000 30 0000 C CNN +F 2 "" H 6300 6000 60 0000 C CNN +F 3 "" H 6300 6000 60 0000 C CNN + 14 6300 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4002/4002.cir b/src/SubcircuitLibrary/4002/4002.cir new file mode 100644 index 00000000..5d5c1ed7 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor + +.end diff --git a/src/SubcircuitLibrary/4002/4002.cir.out b/src/SubcircuitLibrary/4002/4002.cir.out new file mode 100644 index 00000000..e9cc6862 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir + +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4002/4002.pro b/src/SubcircuitLibrary/4002/4002.pro new file mode 100644 index 00000000..225ef82a --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog +LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices +LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital +LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid +LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot +LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power +LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources +LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt +LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User +LibName11=power diff --git a/src/SubcircuitLibrary/4002/4002.sch b/src/SubcircuitLibrary/4002/4002.sch new file mode 100644 index 00000000..545f46fe --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5CEE059A +P 4750 2900 +F 0 "U2" H 4750 2900 60 0000 C CNN +F 1 "d_or" H 4750 3000 60 0000 C CNN +F 2 "" H 4750 2900 60 0000 C CNN +F 3 "" H 4750 2900 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5CEE0629 +P 4750 3450 +F 0 "U3" H 4750 3450 60 0000 C CNN +F 1 "d_or" H 4750 3550 60 0000 C CNN +F 2 "" H 4750 3450 60 0000 C CNN +F 3 "" H 4750 3450 60 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CEE0663 +P 6000 3100 +F 0 "U6" H 6000 3100 60 0000 C CNN +F 1 "d_nor" H 6050 3200 60 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5400 2850 +Wire Wire Line + 5400 2850 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 5200 3400 5400 3400 +Wire Wire Line + 5400 3400 5400 3100 +Wire Wire Line + 5400 3100 5550 3100 +Wire Wire Line + 5650 5350 6050 5350 +Wire Wire Line + 5650 5550 6050 5550 +Wire Wire Line + 5650 5800 6050 5800 +Wire Wire Line + 5650 6000 6050 6000 +NoConn ~ 5650 5350 +NoConn ~ 5650 5550 +NoConn ~ 5650 5800 +NoConn ~ 5650 6000 +$Comp +L PORT U1 +U 2 1 5CEE1C41 +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 2 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE22EE +P 3900 3050 +F 0 "U1" H 3950 3150 30 0000 C CNN +F 1 "PORT" H 3900 3050 30 0000 C CNN +F 2 "" H 3900 3050 60 0000 C CNN +F 3 "" H 3900 3050 60 0000 C CNN + 3 3900 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE2322 +P 3900 3250 +F 0 "U1" H 3950 3350 30 0000 C CNN +F 1 "PORT" H 3900 3250 30 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 5 3900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE2351 +P 3900 3550 +F 0 "U1" H 3950 3650 30 0000 C CNN +F 1 "PORT" H 3900 3550 30 0000 C CNN +F 2 "" H 3900 3550 60 0000 C CNN +F 3 "" H 3900 3550 60 0000 C CNN + 4 3900 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE2387 +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2800 4300 2800 +Wire Wire Line + 4150 3050 4150 2900 +Wire Wire Line + 4150 2900 4300 2900 +Wire Wire Line + 4150 3250 4300 3250 +Wire Wire Line + 4300 3250 4300 3350 +Wire Wire Line + 4150 3550 4150 3450 +Wire Wire Line + 4150 3450 4300 3450 +Wire Wire Line + 6700 3050 6450 3050 +$Comp +L d_or U4 +U 1 1 5CEE4ED7 +P 4900 4100 +F 0 "U4" H 4900 4100 60 0000 C CNN +F 1 "d_or" H 4900 4200 60 0000 C CNN +F 2 "" H 4900 4100 60 0000 C CNN +F 3 "" H 4900 4100 60 0000 C CNN + 1 4900 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5CEE4EDD +P 4900 4650 +F 0 "U5" H 4900 4650 60 0000 C CNN +F 1 "d_or" H 4900 4750 60 0000 C CNN +F 2 "" H 4900 4650 60 0000 C CNN +F 3 "" H 4900 4650 60 0000 C CNN + 1 4900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CEE4EE3 +P 6150 4300 +F 0 "U7" H 6150 4300 60 0000 C CNN +F 1 "d_nor" H 6200 4400 60 0000 C CNN +F 2 "" H 6150 4300 60 0000 C CNN +F 3 "" H 6150 4300 60 0000 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 4200 +Wire Wire Line + 5550 4200 5700 4200 +Wire Wire Line + 5350 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 4300 +Wire Wire Line + 5550 4300 5700 4300 +$Comp +L PORT U1 +U 9 1 5CEE4EEF +P 4000 4000 +F 0 "U1" H 4050 4100 30 0000 C CNN +F 1 "PORT" H 4000 4000 30 0000 C CNN +F 2 "" H 4000 4000 60 0000 C CNN +F 3 "" H 4000 4000 60 0000 C CNN + 9 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE4EF5 +P 4050 4250 +F 0 "U1" H 4100 4350 30 0000 C CNN +F 1 "PORT" H 4050 4250 30 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 10 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE4EFB +P 4050 4450 +F 0 "U1" H 4100 4550 30 0000 C CNN +F 1 "PORT" H 4050 4450 30 0000 C CNN +F 2 "" H 4050 4450 60 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 11 4050 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE4F01 +P 4050 4750 +F 0 "U1" H 4100 4850 30 0000 C CNN +F 1 "PORT" H 4050 4750 30 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 12 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE4F07 +P 7100 4250 +F 0 "U1" H 7150 4350 30 0000 C CNN +F 1 "PORT" H 7100 4250 30 0000 C CNN +F 2 "" H 7100 4250 60 0000 C CNN +F 3 "" H 7100 4250 60 0000 C CNN + 13 7100 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 4000 4450 4000 +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4450 4100 +Wire Wire Line + 4300 4450 4450 4450 +Wire Wire Line + 4450 4450 4450 4550 +Wire Wire Line + 4300 4750 4300 4650 +Wire Wire Line + 4300 4650 4450 4650 +Wire Wire Line + 6850 4250 6600 4250 +$Comp +L PORT U1 +U 6 1 5CEE51A5 +P 6300 5350 +F 0 "U1" H 6350 5450 30 0000 C CNN +F 1 "PORT" H 6300 5350 30 0000 C CNN +F 2 "" H 6300 5350 60 0000 C CNN +F 3 "" H 6300 5350 60 0000 C CNN + 6 6300 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE522C +P 6300 5550 +F 0 "U1" H 6350 5650 30 0000 C CNN +F 1 "PORT" H 6300 5550 30 0000 C CNN +F 2 "" H 6300 5550 60 0000 C CNN +F 3 "" H 6300 5550 60 0000 C CNN + 7 6300 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5276 +P 6300 5800 +F 0 "U1" H 6350 5900 30 0000 C CNN +F 1 "PORT" H 6300 5800 30 0000 C CNN +F 2 "" H 6300 5800 60 0000 C CNN +F 3 "" H 6300 5800 60 0000 C CNN + 8 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE52C5 +P 6300 6000 +F 0 "U1" H 6350 6100 30 0000 C CNN +F 1 "PORT" H 6300 6000 30 0000 C CNN +F 2 "" H 6300 6000 60 0000 C CNN +F 3 "" H 6300 6000 60 0000 C CNN + 14 6300 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4002/4002.sub b/src/SubcircuitLibrary/4002/4002.sub new file mode 100644 index 00000000..b9726625 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002 +.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4002
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/analysis b/src/SubcircuitLibrary/4002/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4002/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/4012-cache.lib b/src/SubcircuitLibrary/4012/4012-cache.lib new file mode 100644 index 00000000..ea0d2d70 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4012/4012.bak b/src/SubcircuitLibrary/4012/4012.bak new file mode 100644 index 00000000..f7649cc4 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.bak @@ -0,0 +1,341 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5CEE53DC +P 3800 2700 +F 0 "U2" H 3800 2700 60 0000 C CNN +F 1 "d_and" H 3850 2800 60 0000 C CNN +F 2 "" H 3800 2700 60 0000 C CNN +F 3 "" H 3800 2700 60 0000 C CNN + 1 3800 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5CEE540C +P 3800 3300 +F 0 "U3" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 5CEE5432 +P 4750 3000 +F 0 "U6" H 4750 3000 60 0000 C CNN +F 1 "d_and" H 4800 3100 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 2650 4300 2650 +Wire Wire Line + 4300 2650 4300 2900 +Wire Wire Line + 4300 3000 4300 3250 +Wire Wire Line + 4300 3250 4250 3250 +Wire Wire Line + 3350 2600 2550 2600 +Wire Wire Line + 3350 2700 3150 2700 +Wire Wire Line + 3150 2700 3150 2850 +Wire Wire Line + 3150 2850 2550 2850 +Wire Wire Line + 3350 3200 3150 3200 +Wire Wire Line + 3150 3200 3150 3100 +Wire Wire Line + 3150 3100 2550 3100 +Wire Wire Line + 3350 3300 2550 3300 +Wire Wire Line + 5200 2950 5500 2950 +$Comp +L d_inverter U8 +U 1 1 5CEE55AB +P 5800 2950 +F 0 "U8" H 5800 2850 60 0000 C CNN +F 1 "d_inverter" H 5800 3100 60 0000 C CNN +F 2 "" H 5850 2900 60 0000 C CNN +F 3 "" H 5850 2900 60 0000 C CNN + 1 5800 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2950 6500 2950 +$Comp +L d_and U4 +U 1 1 5CEE56F6 +P 3850 4050 +F 0 "U4" H 3850 4050 60 0000 C CNN +F 1 "d_and" H 3900 4150 60 0000 C CNN +F 2 "" H 3850 4050 60 0000 C CNN +F 3 "" H 3850 4050 60 0000 C CNN + 1 3850 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5CEE56FC +P 3850 4650 +F 0 "U5" H 3850 4650 60 0000 C CNN +F 1 "d_and" H 3900 4750 60 0000 C CNN +F 2 "" H 3850 4650 60 0000 C CNN +F 3 "" H 3850 4650 60 0000 C CNN + 1 3850 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5CEE5702 +P 4800 4350 +F 0 "U7" H 4800 4350 60 0000 C CNN +F 1 "d_and" H 4850 4450 60 0000 C CNN +F 2 "" H 4800 4350 60 0000 C CNN +F 3 "" H 4800 4350 60 0000 C CNN + 1 4800 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 4000 4350 4000 +Wire Wire Line + 4350 4000 4350 4250 +Wire Wire Line + 4350 4350 4350 4600 +Wire Wire Line + 4350 4600 4300 4600 +Wire Wire Line + 3400 3950 2600 3950 +Wire Wire Line + 3400 4050 3200 4050 +Wire Wire Line + 3200 4050 3200 4200 +Wire Wire Line + 3200 4200 2600 4200 +Wire Wire Line + 3400 4550 3200 4550 +Wire Wire Line + 3200 4550 3200 4450 +Wire Wire Line + 3200 4450 2600 4450 +Wire Wire Line + 3400 4650 2600 4650 +Wire Wire Line + 5250 4300 5550 4300 +$Comp +L d_inverter U9 +U 1 1 5CEE5715 +P 5850 4300 +F 0 "U9" H 5850 4200 60 0000 C CNN +F 1 "d_inverter" H 5850 4450 60 0000 C CNN +F 2 "" H 5900 4250 60 0000 C CNN +F 3 "" H 5900 4250 60 0000 C CNN + 1 5850 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 4300 6550 4300 +$Comp +L PORT U1 +U 2 1 5CEE57D6 +P 2300 2600 +F 0 "U1" H 2350 2700 30 0000 C CNN +F 1 "PORT" H 2300 2600 30 0000 C CNN +F 2 "" H 2300 2600 60 0000 C CNN +F 3 "" H 2300 2600 60 0000 C CNN + 2 2300 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE587B +P 2300 2850 +F 0 "U1" H 2350 2950 30 0000 C CNN +F 1 "PORT" H 2300 2850 30 0000 C CNN +F 2 "" H 2300 2850 60 0000 C CNN +F 3 "" H 2300 2850 60 0000 C CNN + 3 2300 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE58AF +P 2300 3100 +F 0 "U1" H 2350 3200 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0000 C CNN +F 3 "" H 2300 3100 60 0000 C CNN + 4 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE58E6 +P 6800 4300 +F 0 "U1" H 6850 4400 30 0000 C CNN +F 1 "PORT" H 6800 4300 30 0000 C CNN +F 2 "" H 6800 4300 60 0000 C CNN +F 3 "" H 6800 4300 60 0000 C CNN + 13 6800 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE5922 +P 2300 3300 +AR Path="/5CEE58E6" Ref="U1" Part="1" +AR Path="/5CEE5922" Ref="U1" Part="5" +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 5 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CEE596F +P 2350 3950 +AR Path="/5CEE5922" Ref="U1" Part="5" +AR Path="/5CEE596F" Ref="U1" Part="9" +F 0 "U1" H 2400 4050 30 0000 C CNN +F 1 "PORT" H 2350 3950 30 0000 C CNN +F 2 "" H 2350 3950 60 0000 C CNN +F 3 "" H 2350 3950 60 0000 C CNN + 9 2350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE59AF +P 2350 4200 +AR Path="/5CEE596F" Ref="U1" Part="6" +AR Path="/5CEE59AF" Ref="U1" Part="10" +F 0 "U1" H 2400 4300 30 0000 C CNN +F 1 "PORT" H 2350 4200 30 0000 C CNN +F 2 "" H 2350 4200 60 0000 C CNN +F 3 "" H 2350 4200 60 0000 C CNN + 10 2350 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE59F6 +P 2350 4450 +AR Path="/5CEE59AF" Ref="U1" Part="7" +AR Path="/5CEE59F6" Ref="U1" Part="11" +F 0 "U1" H 2400 4550 30 0000 C CNN +F 1 "PORT" H 2350 4450 30 0000 C CNN +F 2 "" H 2350 4450 60 0000 C CNN +F 3 "" H 2350 4450 60 0000 C CNN + 11 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE5A6A +P 2350 4650 +AR Path="/5CEE59F6" Ref="U1" Part="8" +AR Path="/5CEE5A6A" Ref="U1" Part="12" +F 0 "U1" H 2400 4750 30 0000 C CNN +F 1 "PORT" H 2350 4650 30 0000 C CNN +F 2 "" H 2350 4650 60 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 12 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE5BF8 +P 6750 2950 +AR Path="/5CEE5A6A" Ref="U1" Part="9" +AR Path="/5CEE5BF8" Ref="U1" Part="1" +F 0 "U1" H 6800 3050 30 0000 C CNN +F 1 "PORT" H 6750 2950 30 0000 C CNN +F 2 "" H 6750 2950 60 0000 C CNN +F 3 "" H 6750 2950 60 0000 C CNN + 1 6750 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CEE5C72 +P 7850 1450 +F 0 "U1" H 7900 1550 30 0000 C CNN +F 1 "PORT" H 7850 1450 30 0000 C CNN +F 2 "" H 7850 1450 60 0000 C CNN +F 3 "" H 7850 1450 60 0000 C CNN + 6 7850 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE5D23 +P 7850 1700 +F 0 "U1" H 7900 1800 30 0000 C CNN +F 1 "PORT" H 7850 1700 30 0000 C CNN +F 2 "" H 7850 1700 60 0000 C CNN +F 3 "" H 7850 1700 60 0000 C CNN + 7 7850 1700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE5D75 +P 7850 1950 +F 0 "U1" H 7900 2050 30 0000 C CNN +F 1 "PORT" H 7850 1950 30 0000 C CNN +F 2 "" H 7850 1950 60 0000 C CNN +F 3 "" H 7850 1950 60 0000 C CNN + 14 7850 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5DCA +P 7850 2250 +F 0 "U1" H 7900 2350 30 0000 C CNN +F 1 "PORT" H 7850 2250 30 0000 C CNN +F 2 "" H 7850 2250 60 0000 C CNN +F 3 "" H 7850 2250 60 0000 C CNN + 8 7850 2250 + -1 0 0 1 +$EndComp +NoConn ~ 7600 1450 +NoConn ~ 7600 1700 +NoConn ~ 7600 1950 +NoConn ~ 7600 2250 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4012/4012.cir b/src/SubcircuitLibrary/4012/4012.cir new file mode 100644 index 00000000..a88a9da4 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter +U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and + +.end diff --git a/src/SubcircuitLibrary/4012/4012.cir.out b/src/SubcircuitLibrary/4012/4012.cir.out new file mode 100644 index 00000000..c43dda8c --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir + +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4012/4012.pro b/src/SubcircuitLibrary/4012/4012.pro new file mode 100644 index 00000000..0f76f4bb --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_User +LibName11=eSim_Subckt diff --git a/src/SubcircuitLibrary/4012/4012.sch b/src/SubcircuitLibrary/4012/4012.sch new file mode 100644 index 00000000..b3320871 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4012-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3350 2600 2550 2600 +Wire Wire Line + 3350 2700 3150 2700 +Wire Wire Line + 3150 2700 3150 2850 +Wire Wire Line + 3150 2850 2550 2850 +Wire Wire Line + 3350 3200 3150 3200 +Wire Wire Line + 3150 3200 3150 3100 +Wire Wire Line + 3150 3100 2550 3100 +Wire Wire Line + 3350 3300 2550 3300 +Wire Wire Line + 5200 2950 5500 2950 +$Comp +L d_inverter U8 +U 1 1 5CEE55AB +P 5800 2950 +F 0 "U8" H 5800 2850 60 0000 C CNN +F 1 "d_inverter" H 5800 3100 60 0000 C CNN +F 2 "" H 5850 2900 60 0000 C CNN +F 3 "" H 5850 2900 60 0000 C CNN + 1 5800 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2950 6500 2950 +Wire Wire Line + 3400 3950 2600 3950 +Wire Wire Line + 3400 4050 3200 4050 +Wire Wire Line + 3200 4050 3200 4200 +Wire Wire Line + 3200 4200 2600 4200 +Wire Wire Line + 3400 4550 3200 4550 +Wire Wire Line + 3200 4550 3200 4450 +Wire Wire Line + 3200 4450 2600 4450 +Wire Wire Line + 3400 4650 2600 4650 +Wire Wire Line + 5250 4300 5550 4300 +$Comp +L d_inverter U9 +U 1 1 5CEE5715 +P 5850 4300 +F 0 "U9" H 5850 4200 60 0000 C CNN +F 1 "d_inverter" H 5850 4450 60 0000 C CNN +F 2 "" H 5900 4250 60 0000 C CNN +F 3 "" H 5900 4250 60 0000 C CNN + 1 5850 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 4300 6550 4300 +$Comp +L PORT U1 +U 2 1 5CEE57D6 +P 2300 2600 +F 0 "U1" H 2350 2700 30 0000 C CNN +F 1 "PORT" H 2300 2600 30 0000 C CNN +F 2 "" H 2300 2600 60 0000 C CNN +F 3 "" H 2300 2600 60 0000 C CNN + 2 2300 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE587B +P 2300 2850 +F 0 "U1" H 2350 2950 30 0000 C CNN +F 1 "PORT" H 2300 2850 30 0000 C CNN +F 2 "" H 2300 2850 60 0000 C CNN +F 3 "" H 2300 2850 60 0000 C CNN + 3 2300 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE58AF +P 2300 3100 +F 0 "U1" H 2350 3200 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0000 C CNN +F 3 "" H 2300 3100 60 0000 C CNN + 4 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE58E6 +P 6800 4300 +F 0 "U1" H 6850 4400 30 0000 C CNN +F 1 "PORT" H 6800 4300 30 0000 C CNN +F 2 "" H 6800 4300 60 0000 C CNN +F 3 "" H 6800 4300 60 0000 C CNN + 13 6800 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE5922 +P 2300 3300 +AR Path="/5CEE58E6" Ref="U1" Part="1" +AR Path="/5CEE5922" Ref="U1" Part="5" +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 5 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CEE596F +P 2350 3950 +AR Path="/5CEE5922" Ref="U1" Part="5" +AR Path="/5CEE596F" Ref="U1" Part="9" +F 0 "U1" H 2400 4050 30 0000 C CNN +F 1 "PORT" H 2350 3950 30 0000 C CNN +F 2 "" H 2350 3950 60 0000 C CNN +F 3 "" H 2350 3950 60 0000 C CNN + 9 2350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE59AF +P 2350 4200 +AR Path="/5CEE596F" Ref="U1" Part="6" +AR Path="/5CEE59AF" Ref="U1" Part="10" +F 0 "U1" H 2400 4300 30 0000 C CNN +F 1 "PORT" H 2350 4200 30 0000 C CNN +F 2 "" H 2350 4200 60 0000 C CNN +F 3 "" H 2350 4200 60 0000 C CNN + 10 2350 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE59F6 +P 2350 4450 +AR Path="/5CEE59AF" Ref="U1" Part="7" +AR Path="/5CEE59F6" Ref="U1" Part="11" +F 0 "U1" H 2400 4550 30 0000 C CNN +F 1 "PORT" H 2350 4450 30 0000 C CNN +F 2 "" H 2350 4450 60 0000 C CNN +F 3 "" H 2350 4450 60 0000 C CNN + 11 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE5A6A +P 2350 4650 +AR Path="/5CEE59F6" Ref="U1" Part="8" +AR Path="/5CEE5A6A" Ref="U1" Part="12" +F 0 "U1" H 2400 4750 30 0000 C CNN +F 1 "PORT" H 2350 4650 30 0000 C CNN +F 2 "" H 2350 4650 60 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 12 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE5BF8 +P 6750 2950 +AR Path="/5CEE5A6A" Ref="U1" Part="9" +AR Path="/5CEE5BF8" Ref="U1" Part="1" +F 0 "U1" H 6800 3050 30 0000 C CNN +F 1 "PORT" H 6750 2950 30 0000 C CNN +F 2 "" H 6750 2950 60 0000 C CNN +F 3 "" H 6750 2950 60 0000 C CNN + 1 6750 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CEE5C72 +P 7850 1450 +F 0 "U1" H 7900 1550 30 0000 C CNN +F 1 "PORT" H 7850 1450 30 0000 C CNN +F 2 "" H 7850 1450 60 0000 C CNN +F 3 "" H 7850 1450 60 0000 C CNN + 6 7850 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE5D23 +P 7850 1700 +F 0 "U1" H 7900 1800 30 0000 C CNN +F 1 "PORT" H 7850 1700 30 0000 C CNN +F 2 "" H 7850 1700 60 0000 C CNN +F 3 "" H 7850 1700 60 0000 C CNN + 7 7850 1700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE5D75 +P 7850 1950 +F 0 "U1" H 7900 2050 30 0000 C CNN +F 1 "PORT" H 7850 1950 30 0000 C CNN +F 2 "" H 7850 1950 60 0000 C CNN +F 3 "" H 7850 1950 60 0000 C CNN + 14 7850 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5DCA +P 7850 2250 +F 0 "U1" H 7900 2350 30 0000 C CNN +F 1 "PORT" H 7850 2250 30 0000 C CNN +F 2 "" H 7850 2250 60 0000 C CNN +F 3 "" H 7850 2250 60 0000 C CNN + 8 7850 2250 + -1 0 0 1 +$EndComp +NoConn ~ 7600 1450 +NoConn ~ 7600 1700 +NoConn ~ 7600 1950 +NoConn ~ 7600 2250 +$Comp +L d_and U4 +U 1 1 5CEE56F6 +P 3850 4050 +F 0 "U4" H 3850 4050 60 0000 C CNN +F 1 "d_and" H 3900 4150 60 0000 C CNN +F 2 "" H 3850 4050 60 0000 C CNN +F 3 "" H 3850 4050 60 0000 C CNN + 1 3850 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5CEE56FC +P 3850 4650 +F 0 "U5" H 3850 4650 60 0000 C CNN +F 1 "d_and" H 3900 4750 60 0000 C CNN +F 2 "" H 3850 4650 60 0000 C CNN +F 3 "" H 3850 4650 60 0000 C CNN + 1 3850 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4600 4300 4600 +Wire Wire Line + 4350 4350 4350 4600 +Wire Wire Line + 4350 4000 4350 4250 +Wire Wire Line + 4300 4000 4350 4000 +$Comp +L d_and U7 +U 1 1 5CEE5702 +P 4800 4350 +F 0 "U7" H 4800 4350 60 0000 C CNN +F 1 "d_and" H 4850 4450 60 0000 C CNN +F 2 "" H 4800 4350 60 0000 C CNN +F 3 "" H 4800 4350 60 0000 C CNN + 1 4800 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 2650 4300 2650 +Wire Wire Line + 4300 3250 4250 3250 +Wire Wire Line + 4300 2650 4300 2900 +Wire Wire Line + 4300 3000 4300 3250 +$Comp +L d_and U6 +U 1 1 5CEE5432 +P 4750 3000 +F 0 "U6" H 4750 3000 60 0000 C CNN +F 1 "d_and" H 4800 3100 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5CEE540C +P 3800 3300 +F 0 "U3" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5CEE53DC +P 3800 2700 +F 0 "U2" H 3800 2700 60 0000 C CNN +F 1 "d_and" H 3850 2800 60 0000 C CNN +F 2 "" H 3800 2700 60 0000 C CNN +F 3 "" H 3800 2700 60 0000 C CNN + 1 3800 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4012/4012.sub b/src/SubcircuitLibrary/4012/4012.sub new file mode 100644 index 00000000..65263f03 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012 +.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4012
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/analysis b/src/SubcircuitLibrary/4012/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4012/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/4017-cache.lib b/src/SubcircuitLibrary/4017/4017-cache.lib new file mode 100644 index 00000000..efa6746f --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4017/4017.bak b/src/SubcircuitLibrary/4017/4017.bak new file mode 100644 index 00000000..5502933b --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.bak @@ -0,0 +1,635 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:4017-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U7 +U 1 1 5C7B9B95 +P 2300 4100 +F 0 "U7" H 2300 4100 60 0000 C CNN +F 1 "d_dff" H 2300 4250 60 0000 C CNN +F 2 "" H 2300 4100 60 0000 C CNN +F 3 "" H 2300 4100 60 0000 C CNN + 1 2300 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U11 +U 1 1 5C7B9CEE +P 3700 4100 +F 0 "U11" H 3700 4100 60 0000 C CNN +F 1 "d_dff" H 3700 4250 60 0000 C CNN +F 2 "" H 3700 4100 60 0000 C CNN +F 3 "" H 3700 4100 60 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_dff U15 +U 1 1 5C7B9D3E +P 5150 4100 +F 0 "U15" H 5150 4100 60 0000 C CNN +F 1 "d_dff" H 5150 4250 60 0000 C CNN +F 2 "" H 5150 4100 60 0000 C CNN +F 3 "" H 5150 4100 60 0000 C CNN + 1 5150 4100 + 1 0 0 -1 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0000 C CNN + 1 2100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U8 +U 1 1 5C7BEE9A +P 2750 1850 +F 0 "U8" H 2750 1850 60 0000 C CNN +F 1 "d_nand" H 2800 1950 60 0000 C CNN +F 2 "" H 2750 1850 60 0000 C CNN +F 3 "" H 2750 1850 60 0000 C CNN + 1 2750 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U10 +U 1 1 5C7BEF66 +P 3450 1850 +F 0 "U10" H 3450 1850 60 0000 C CNN +F 1 "d_nand" H 3500 1950 60 0000 C CNN +F 2 "" H 3450 1850 60 0000 C CNN +F 3 "" H 3450 1850 60 0000 C CNN + 1 3450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U12 +U 1 1 5C7BEFC3 +P 4000 1850 +F 0 "U12" H 4000 1850 60 0000 C CNN +F 1 "d_nand" H 4050 1950 60 0000 C CNN +F 2 "" H 4000 1850 60 0000 C CNN +F 3 "" H 4000 1850 60 0000 C CNN + 1 4000 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U14 +U 1 1 5C7BF047 +P 4650 1850 +F 0 "U14" H 4650 1850 60 0000 C CNN +F 1 "d_nand" H 4700 1950 60 0000 C CNN +F 2 "" H 4650 1850 60 0000 C CNN +F 3 "" H 4650 1850 60 0000 C CNN + 1 4650 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_nand U16 +U 1 1 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7850 1950 60 0000 C CNN +F 2 "" H 7800 1850 60 0000 C CNN +F 3 "" H 7800 1850 60 0000 C CNN + 1 7800 1850 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 2300 6700 1100 6700 +Connection ~ 2300 4900 +Wire Wire Line + 1550 3350 1550 5150 +Wire Wire Line + 1550 5150 2300 5150 +Connection ~ 2300 5150 +Connection ~ 2300 3350 +Wire Wire Line + 2550 5350 2550 6650 +Wire Wire Line + 2550 6650 2950 6650 +Wire Wire Line + 2950 6650 2950 7200 +Wire Wire Line + 2950 7200 2700 7200 +Connection ~ 2550 5350 +$Comp +L PORT U1 +U 6 1 5C7C1634 +P 5300 1000 +F 0 "U1" H 5350 1100 30 0000 C CNN +F 1 "PORT" H 5300 1000 30 0000 C CNN +F 2 "" H 5300 1000 60 0000 C CNN +F 3 "" H 5300 1000 60 0000 C CNN + 6 5300 1000 + 0 1 1 0 +$EndComp +Wire Wire Line + 5300 1250 5300 1400 +$Comp +L PORT U1 +U 2 1 5C7BC7B8 +P 2700 1000 +F 0 "U1" H 2750 1100 30 0000 C CNN +F 1 "PORT" H 2700 1000 30 0000 C CNN +F 2 "" H 2700 1000 60 0000 C CNN +F 3 "" H 2700 1000 60 0000 C CNN + 2 2700 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7BC953 +P 2050 950 +F 0 "U1" H 2100 1050 30 0000 C CNN +F 1 "PORT" H 2050 950 30 0000 C CNN +F 2 "" H 2050 950 60 0000 C CNN +F 3 "" H 2050 950 60 0000 C CNN + 1 2050 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7BC9D8 +P 3400 950 +F 0 "U1" H 3450 1050 30 0000 C CNN +F 1 "PORT" H 3400 950 30 0000 C CNN +F 2 "" H 3400 950 60 0000 C CNN +F 3 "" H 3400 950 60 0000 C CNN + 3 3400 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7BCAA7 +P 5850 950 +F 0 "U1" H 5900 1050 30 0000 C CNN +F 1 "PORT" H 5850 950 30 0000 C CNN +F 2 "" H 5850 950 60 0000 C CNN +F 3 "" H 5850 950 60 0000 C CNN + 7 5850 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7BCB20 +P 6400 1000 +F 0 "U1" H 6450 1100 30 0000 C CNN +F 1 "PORT" H 6400 1000 30 0000 C CNN +F 2 "" H 6400 1000 60 0000 C CNN +F 3 "" H 6400 1000 60 0000 C CNN + 8 6400 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7BCBB1 +P 3950 950 +F 0 "U1" H 4000 1050 30 0000 C CNN +F 1 "PORT" H 3950 950 30 0000 C CNN +F 2 "" H 3950 950 60 0000 C CNN +F 3 "" H 3950 950 60 0000 C CNN + 4 3950 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5C7BCF23 +P 7050 1000 +F 0 "U1" H 7100 1100 30 0000 C CNN +F 1 "PORT" H 7050 1000 30 0000 C CNN +F 2 "" H 7050 1000 60 0000 C CNN +F 3 "" H 7050 1000 60 0000 C CNN + 9 7050 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5C7BCFC0 +P 4600 950 +F 0 "U1" H 4650 1050 30 0000 C CNN +F 1 "PORT" H 4600 950 30 0000 C CNN +F 2 "" H 4600 950 60 0000 C CNN +F 3 "" H 4600 950 60 0000 C CNN + 5 4600 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5C7BD0A5 +P 7750 1000 +F 0 "U1" H 7800 1100 30 0000 C CNN +F 1 "PORT" H 7750 1000 30 0000 C CNN +F 2 "" H 7750 1000 60 0000 C CNN +F 3 "" H 7750 1000 60 0000 C CNN + 10 7750 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5C7BD5BB +P 850 6700 +F 0 "U1" H 900 6800 30 0000 C CNN +F 1 "PORT" H 850 6700 30 0000 C CNN +F 2 "" H 850 6700 60 0000 C CNN +F 3 "" H 850 6700 60 0000 C CNN + 11 850 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 1200 2050 1400 +Wire Wire Line + 2700 1250 2700 1400 +Wire Wire Line + 3400 1200 3400 1400 +Wire Wire Line + 3950 1200 3950 1400 +Wire Wire Line + 4600 1200 4600 1400 +Wire Wire Line + 5850 1200 5850 1400 +Wire Wire Line + 6400 1250 6400 1400 +Wire Wire Line + 7050 1250 7050 1400 +Wire Wire Line + 7750 1250 7750 1400 +$Comp +L PORT U1 +U 12 1 5C8A0119 +P 2450 7200 +F 0 "U1" H 2500 7300 30 0000 C CNN +F 1 "PORT" H 2450 7200 30 0000 C CNN +F 2 "" H 2450 7200 60 0000 C CNN +F 3 "" H 2450 7200 60 0000 C CNN + 12 2450 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U? +U 1 1 5C89EF41 +P 3300 6000 +F 0 "U?" H 3300 6000 60 0000 C CNN +F 1 "d_and" H 3350 6100 60 0000 C CNN +F 2 "" H 3300 6000 60 0000 C CNN +F 3 "" H 3300 6000 60 0000 C CNN + 1 3300 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_or U? +U 1 1 5C89EFB7 +P 4300 5950 +F 0 "U?" H 4300 5950 60 0000 C CNN +F 1 "d_or" H 4300 6050 60 0000 C CNN +F 2 "" H 4300 5950 60 0000 C CNN +F 3 "" H 4300 5950 60 0000 C CNN + 1 4300 5950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4017/4017.cir b/src/SubcircuitLibrary/4017/4017.cir new file mode 100644 index 00000000..67ac9971 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.cir @@ -0,0 +1,26 @@ +* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff +U11 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff +U15 Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff +U19 Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff +U22 Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and +U3 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and +U4 Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and +U5 Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and +U6 Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and +U8 Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and +U9 Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and + +.end diff --git a/src/SubcircuitLibrary/4017/4017.cir.out b/src/SubcircuitLibrary/4017/4017.cir.out new file mode 100644 index 00000000..e3a384c5 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.cir.out @@ -0,0 +1,72 @@ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir + +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4017/4017.pro b/src/SubcircuitLibrary/4017/4017.pro new file mode 100644 index 00000000..8cdecd6c --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.pro @@ -0,0 +1,72 @@ +update=Fri Jun 14 10:14:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot + diff --git a/src/SubcircuitLibrary/4017/4017.sch b/src/SubcircuitLibrary/4017/4017.sch new file mode 100644 index 00000000..05549a32 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.sch @@ -0,0 +1,580 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:4017-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U7 +U 1 1 5C7B9B95 +P 2300 4100 +F 0 "U7" H 2300 4100 60 0000 C CNN +F 1 "d_dff" H 2300 4250 60 0000 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0000 C CNN + 1 4000 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U6 +U 1 1 5C89FEBF +P 4650 1850 +F 0 "U6" H 4650 1850 60 0000 C CNN +F 1 "d_and" H 4700 1950 60 0000 C CNN +F 2 "" H 4650 1850 60 0000 C CNN +F 3 "" H 4650 1850 60 0000 C CNN + 1 4650 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U8 +U 1 1 5C89FF2C +P 5350 1850 +F 0 "U8" H 5350 1850 60 0000 C CNN +F 1 "d_and" H 5400 1950 60 0000 C CNN +F 2 "" H 5350 1850 60 0000 C CNN +F 3 "" H 5350 1850 60 0000 C CNN + 1 5350 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 5C89FF96 +P 5900 1850 +F 0 "U9" H 5900 1850 60 0000 C CNN +F 1 "d_and" H 5950 1950 60 0000 C CNN +F 2 "" H 5900 1850 60 0000 C CNN +F 3 "" H 5900 1850 60 0000 C CNN + 1 5900 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 5C8A066D +P 6450 1850 +F 0 "U10" H 6450 1850 60 0000 C CNN +F 1 "d_and" H 6500 1950 60 0000 C CNN +F 2 "" H 6450 1850 60 0000 C CNN +F 3 "" H 6450 1850 60 0000 C CNN + 1 6450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 5C8A06D8 +P 7100 1850 +F 0 "U12" H 7100 1850 60 0000 C CNN +F 1 "d_and" H 7150 1950 60 0000 C CNN +F 2 "" H 7100 1850 60 0000 C CNN +F 3 "" H 7100 1850 60 0000 C CNN + 1 7100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 5C8A12F5 +P 7800 1850 +F 0 "U13" H 7800 1850 60 0000 C CNN +F 1 "d_and" H 7850 1950 60 0000 C CNN +F 2 "" H 7800 1850 60 0000 C CNN +F 3 "" H 7800 1850 60 0000 C CNN + 1 7800 1850 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4017/4017.sub b/src/SubcircuitLibrary/4017/4017.sub new file mode 100644 index 00000000..2e27ab61 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.sub @@ -0,0 +1,66 @@ +* Subcircuit 4017 +.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4017
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml new file mode 100644 index 00000000..9dfd97a3 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/D.lib b/src/SubcircuitLibrary/4017/D.lib new file mode 100644 index 00000000..adbdfb35 --- /dev/null +++ b/src/SubcircuitLibrary/4017/D.lib @@ -0,0 +1,11 @@ +.MODEL 1N4148 D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=2.495E-09 ++ M=1.959E-01 ++ N=1.679E+00 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/analysis b/src/SubcircuitLibrary/4017/analysis new file mode 100644 index 00000000..40bd9d97 --- /dev/null +++ b/src/SubcircuitLibrary/4017/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/3_and-cache.lib b/src/SubcircuitLibrary/4023/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4023/3_and.bak b/src/SubcircuitLibrary/4023/3_and.bak new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/3_and.cir b/src/SubcircuitLibrary/4023/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4023/3_and.cir.out b/src/SubcircuitLibrary/4023/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4023/3_and.pro b/src/SubcircuitLibrary/4023/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4023/3_and.sch b/src/SubcircuitLibrary/4023/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/3_and.sub b/src/SubcircuitLibrary/4023/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/4023-cache.lib b/src/SubcircuitLibrary/4023/4023-cache.lib new file mode 100644 index 00000000..c989d8c7 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4023/4023.cir b/src/SubcircuitLibrary/4023/4023.cir new file mode 100644 index 00000000..6aad9b84 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.cir @@ -0,0 +1,17 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and +U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter + +.end diff --git a/src/SubcircuitLibrary/4023/4023.cir.out b/src/SubcircuitLibrary/4023/4023.cir.out new file mode 100644 index 00000000..7f48d16f --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir + +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4023/4023.pro b/src/SubcircuitLibrary/4023/4023.pro new file mode 100644 index 00000000..5a5ce355 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:32:35 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4023/4023.sch b/src/SubcircuitLibrary/4023/4023.sch new file mode 100644 index 00000000..57dd7868 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.sch @@ -0,0 +1,309 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X3 +U 1 1 5CF0FA82 +P 4800 2500 +F 0 "X3" H 4900 2450 60 0000 C CNN +F 1 "3_and" H 4950 2650 60 0000 C CNN +F 2 "" H 4800 2500 60 0000 C CNN +F 3 "" H 4800 2500 60 0000 C CNN + 1 4800 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF0FB13 +P 6150 2450 +F 0 "U4" H 6150 2350 60 0000 C CNN +F 1 "d_inverter" H 6150 2600 60 0000 C CNN +F 2 "" H 6200 2400 60 0000 C CNN +F 3 "" H 6200 2400 60 0000 C CNN + 1 6150 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF0FB34 +P 3100 1950 +F 0 "U1" H 3150 2050 30 0000 C CNN +F 1 "PORT" H 3100 1950 30 0000 C CNN +F 2 "" H 3100 1950 60 0000 C CNN +F 3 "" H 3100 1950 60 0000 C CNN + 11 3100 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF0FB90 +P 3100 2350 +F 0 "U1" H 3150 2450 30 0000 C CNN +F 1 "PORT" H 3100 2350 30 0000 C CNN +F 2 "" H 3100 2350 60 0000 C CNN +F 3 "" H 3100 2350 60 0000 C CNN + 12 3100 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF0FBB8 +P 3100 2750 +F 0 "U1" H 3150 2850 30 0000 C CNN +F 1 "PORT" H 3100 2750 30 0000 C CNN +F 2 "" H 3100 2750 60 0000 C CNN +F 3 "" H 3100 2750 60 0000 C CNN + 13 3100 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF0FBED +P 7800 2450 +F 0 "U1" H 7850 2550 30 0000 C CNN +F 1 "PORT" H 7800 2450 30 0000 C CNN +F 2 "" H 7800 2450 60 0000 C CNN +F 3 "" H 7800 2450 60 0000 C CNN + 10 7800 2450 + -1 0 0 1 +$EndComp +Wire Wire Line + 7550 2450 6450 2450 +Wire Wire Line + 5850 2450 5300 2450 +Wire Wire Line + 4450 2350 4450 1950 +Wire Wire Line + 4450 1950 3350 1950 +Wire Wire Line + 4450 2450 4100 2450 +Wire Wire Line + 4100 2450 4100 2350 +Wire Wire Line + 4100 2350 3350 2350 +Wire Wire Line + 3350 2750 3950 2750 +Wire Wire Line + 3950 2750 3950 2550 +Wire Wire Line + 3950 2550 4450 2550 +$Comp +L 3_and X2 +U 1 1 5CF0FF35 +P 4700 3800 +F 0 "X2" H 4800 3750 60 0000 C CNN +F 1 "3_and" H 4850 3950 60 0000 C CNN +F 2 "" H 4700 3800 60 0000 C CNN +F 3 "" H 4700 3800 60 0000 C CNN + 1 4700 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF0FF3B +P 6050 3750 +F 0 "U3" H 6050 3650 60 0000 C CNN +F 1 "d_inverter" H 6050 3900 60 0000 C CNN +F 2 "" H 6100 3700 60 0000 C CNN +F 3 "" H 6100 3700 60 0000 C CNN + 1 6050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF0FF41 +P 3000 3250 +F 0 "U1" H 3050 3350 30 0000 C CNN +F 1 "PORT" H 3000 3250 30 0000 C CNN +F 2 "" H 3000 3250 60 0000 C CNN +F 3 "" H 3000 3250 60 0000 C CNN + 4 3000 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF0FF47 +P 3000 3650 +F 0 "U1" H 3050 3750 30 0000 C CNN +F 1 "PORT" H 3000 3650 30 0000 C CNN +F 2 "" H 3000 3650 60 0000 C CNN +F 3 "" H 3000 3650 60 0000 C CNN + 5 3000 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF0FF4D +P 3000 4050 +F 0 "U1" H 3050 4150 30 0000 C CNN +F 1 "PORT" H 3000 4050 30 0000 C CNN +F 2 "" H 3000 4050 60 0000 C CNN +F 3 "" H 3000 4050 60 0000 C CNN + 3 3000 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF0FF53 +P 7700 3750 +F 0 "U1" H 7750 3850 30 0000 C CNN +F 1 "PORT" H 7700 3750 30 0000 C CNN +F 2 "" H 7700 3750 60 0000 C CNN +F 3 "" H 7700 3750 60 0000 C CNN + 6 7700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7450 3750 6350 3750 +Wire Wire Line + 5750 3750 5200 3750 +Wire Wire Line + 4350 3650 4350 3250 +Wire Wire Line + 4350 3250 3250 3250 +Wire Wire Line + 4350 3750 4000 3750 +Wire Wire Line + 4000 3750 4000 3650 +Wire Wire Line + 4000 3650 3250 3650 +Wire Wire Line + 3250 4050 3850 4050 +Wire Wire Line + 3850 4050 3850 3850 +Wire Wire Line + 3850 3850 4350 3850 +$Comp +L 3_and X1 +U 1 1 5CF100B9 +P 4650 5100 +F 0 "X1" H 4750 5050 60 0000 C CNN +F 1 "3_and" H 4800 5250 60 0000 C CNN +F 2 "" H 4650 5100 60 0000 C CNN +F 3 "" H 4650 5100 60 0000 C CNN + 1 4650 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF100BF +P 6000 5050 +F 0 "U2" H 6000 4950 60 0000 C CNN +F 1 "d_inverter" H 6000 5200 60 0000 C CNN +F 2 "" H 6050 5000 60 0000 C CNN +F 3 "" H 6050 5000 60 0000 C CNN + 1 6000 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF100C5 +P 2950 4550 +F 0 "U1" H 3000 4650 30 0000 C CNN +F 1 "PORT" H 2950 4550 30 0000 C CNN +F 2 "" H 2950 4550 60 0000 C CNN +F 3 "" H 2950 4550 60 0000 C CNN + 1 2950 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF100CB +P 2950 4950 +F 0 "U1" H 3000 5050 30 0000 C CNN +F 1 "PORT" H 2950 4950 30 0000 C CNN +F 2 "" H 2950 4950 60 0000 C CNN +F 3 "" H 2950 4950 60 0000 C CNN + 2 2950 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF100D1 +P 2950 5350 +F 0 "U1" H 3000 5450 30 0000 C CNN +F 1 "PORT" H 2950 5350 30 0000 C CNN +F 2 "" H 2950 5350 60 0000 C CNN +F 3 "" H 2950 5350 60 0000 C CNN + 8 2950 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF100D7 +P 7650 5050 +F 0 "U1" H 7700 5150 30 0000 C CNN +F 1 "PORT" H 7650 5050 30 0000 C CNN +F 2 "" H 7650 5050 60 0000 C CNN +F 3 "" H 7650 5050 60 0000 C CNN + 9 7650 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 7400 5050 6300 5050 +Wire Wire Line + 5700 5050 5150 5050 +Wire Wire Line + 4300 4950 4300 4550 +Wire Wire Line + 4300 4550 3200 4550 +Wire Wire Line + 4300 5050 3950 5050 +Wire Wire Line + 3950 5050 3950 4950 +Wire Wire Line + 3950 4950 3200 4950 +Wire Wire Line + 3200 5350 3800 5350 +Wire Wire Line + 3800 5350 3800 5150 +Wire Wire Line + 3800 5150 4300 5150 +$Comp +L PORT U1 +U 7 1 5CF101BF +P 9950 3350 +F 0 "U1" H 10000 3450 30 0000 C CNN +F 1 "PORT" H 9950 3350 30 0000 C CNN +F 2 "" H 9950 3350 60 0000 C CNN +F 3 "" H 9950 3350 60 0000 C CNN + 7 9950 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF1025C +P 9950 3900 +F 0 "U1" H 10000 4000 30 0000 C CNN +F 1 "PORT" H 9950 3900 30 0000 C CNN +F 2 "" H 9950 3900 60 0000 C CNN +F 3 "" H 9950 3900 60 0000 C CNN + 14 9950 3900 + -1 0 0 1 +$EndComp +NoConn ~ 9700 3350 +NoConn ~ 9700 3900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/4023.sub b/src/SubcircuitLibrary/4023/4023.sub new file mode 100644 index 00000000..b953da2e --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.sub @@ -0,0 +1,22 @@ +* Subcircuit 4023 +.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4023
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml new file mode 100644 index 00000000..ad900de2 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/analysis b/src/SubcircuitLibrary/4023/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4023/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/4028-cache.lib b/src/SubcircuitLibrary/4028/4028-cache.lib new file mode 100644 index 00000000..5b7e8ebd --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4028/4028.cir b/src/SubcircuitLibrary/4028/4028.cir new file mode 100644 index 00000000..ff25eb55 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor +U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor +U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor +U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor +U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor +U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter +U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter +U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and +U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and +U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and +U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and +U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and +U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and + +.end diff --git a/src/SubcircuitLibrary/4028/4028.cir.out b/src/SubcircuitLibrary/4028/4028.cir.out new file mode 100644 index 00000000..882115b7 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir + +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4028/4028.pro b/src/SubcircuitLibrary/4028/4028.pro new file mode 100644 index 00000000..a63207b3 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4028/4028.sch b/src/SubcircuitLibrary/4028/4028.sch new file mode 100644 index 00000000..373a95e6 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U9 +U 1 1 5CF0FE64 +P 3750 2500 +F 0 "U9" H 3750 2500 60 0000 C CNN +F 1 "d_nor" H 3800 2600 60 0000 C CNN +F 2 "" H 3750 2500 60 0000 C CNN +F 3 "" H 3750 2500 60 0000 C CNN + 1 3750 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 5CF0FEA4 +P 3750 3050 +F 0 "U10" H 3750 3050 60 0000 C CNN +F 1 "d_nor" H 3800 3150 60 0000 C CNN +F 2 "" H 3750 3050 60 0000 C CNN +F 3 "" H 3750 3050 60 0000 C CNN + 1 3750 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 5CF0FECC +P 3750 3550 +F 0 "U11" H 3750 3550 60 0000 C CNN +F 1 "d_nor" H 3800 3650 60 0000 C CNN +F 2 "" H 3750 3550 60 0000 C CNN +F 3 "" H 3750 3550 60 0000 C CNN + 1 3750 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 5CF0FEF5 +P 3750 4150 +F 0 "U12" H 3750 4150 60 0000 C CNN +F 1 "d_nor" H 3800 4250 60 0000 C CNN +F 2 "" H 3750 4150 60 0000 C CNN +F 3 "" H 3750 4150 60 0000 C CNN + 1 3750 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CF0FF23 +P 3700 4750 +F 0 "U6" H 3700 4750 60 0000 C CNN +F 1 "d_nor" H 3750 4850 60 0000 C CNN +F 2 "" H 3700 4750 60 0000 C CNN +F 3 "" H 3700 4750 60 0000 C CNN + 1 3700 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CF0FF59 +P 3700 5250 +F 0 "U7" H 3700 5250 60 0000 C CNN +F 1 "d_nor" H 3750 5350 60 0000 C CNN +F 2 "" H 3700 5250 60 0000 C CNN +F 3 "" H 3700 5250 60 0000 C CNN + 1 3700 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U8 +U 1 1 5CF0FFA9 +P 3750 2000 +F 0 "U8" H 3750 2000 60 0000 C CNN +F 1 "d_nor" H 3800 2100 60 0000 C CNN +F 2 "" H 3750 2000 60 0000 C CNN +F 3 "" H 3750 2000 60 0000 C CNN + 1 3750 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF1003A +P 2150 2400 +F 0 "U2" H 2150 2300 60 0000 C CNN +F 1 "d_inverter" H 2150 2550 60 0000 C CNN +F 2 "" H 2200 2350 60 0000 C CNN +F 3 "" H 2200 2350 60 0000 C CNN + 1 2150 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF1007F +P 2150 3300 +F 0 "U3" H 2150 3200 60 0000 C CNN +F 1 "d_inverter" H 2150 3450 60 0000 C CNN +F 2 "" H 2200 3250 60 0000 C CNN +F 3 "" H 2200 3250 60 0000 C CNN + 1 2150 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF100CC +P 2150 4150 +F 0 "U4" H 2150 4050 60 0000 C CNN +F 1 "d_inverter" H 2150 4300 60 0000 C CNN +F 2 "" H 2200 4100 60 0000 C CNN +F 3 "" H 2200 4100 60 0000 C CNN + 1 2150 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF10114 +P 2150 4900 +F 0 "U5" H 2150 4800 60 0000 C CNN +F 1 "d_inverter" H 2150 5050 60 0000 C CNN +F 2 "" H 2200 4850 60 0000 C CNN +F 3 "" H 2200 4850 60 0000 C CNN + 1 2150 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2400 1850 2400 +Wire Wire Line + 1400 3300 1850 3300 +Wire Wire Line + 1450 4150 1850 4150 +Wire Wire Line + 1450 4900 1850 4900 +Wire Wire Line + 2450 4900 2500 4900 +Wire Wire Line + 2500 4900 2500 5250 +Wire Wire Line + 2500 5250 3250 5250 +Wire Wire Line + 2450 4150 2550 4150 +Wire Wire Line + 2550 4150 2550 4650 +Wire Wire Line + 2550 4650 3250 4650 +Wire Wire Line + 2450 3300 2550 3300 +Wire Wire Line + 2550 3300 2550 3550 +Wire Wire Line + 2550 3550 3300 3550 +Wire Wire Line + 2450 2400 2450 2500 +Wire Wire Line + 2450 2500 3300 2500 +Wire Wire Line + 2800 2500 2800 3450 +Wire Wire Line + 2800 3450 3300 3450 +Connection ~ 2800 2500 +Wire Wire Line + 1650 2400 1650 1900 +Wire Wire Line + 1650 1900 3300 1900 +Connection ~ 1650 2400 +Wire Wire Line + 3300 2000 2850 2000 +Wire Wire Line + 2850 2000 2850 3000 +Wire Wire Line + 2850 3000 1650 3000 +Wire Wire Line + 1650 3000 1650 3300 +Connection ~ 1650 3300 +Wire Wire Line + 2850 2400 3300 2400 +Connection ~ 2850 2400 +Wire Wire Line + 2950 1900 2950 2950 +Wire Wire Line + 2950 2950 3300 2950 +Connection ~ 2950 1900 +Wire Wire Line + 3100 3550 3100 3050 +Wire Wire Line + 3100 3050 3300 3050 +Connection ~ 3100 3550 +Wire Wire Line + 1650 3900 1650 4150 +Wire Wire Line + 1650 3900 3050 3900 +Wire Wire Line + 3050 3900 3050 5150 +Wire Wire Line + 3050 4050 3300 4050 +Connection ~ 1650 4150 +Wire Wire Line + 1750 4900 1750 5150 +Wire Wire Line + 1750 5150 2750 5150 +Connection ~ 1750 4900 +Wire Wire Line + 2750 5150 2750 4150 +Wire Wire Line + 2750 4150 3300 4150 +Wire Wire Line + 2750 4750 3250 4750 +Connection ~ 2750 4750 +Wire Wire Line + 3050 5150 3250 5150 +Connection ~ 3050 4050 +$Comp +L d_and U15 +U 1 1 5CF106B1 +P 6600 1850 +F 0 "U15" H 6600 1850 60 0000 C CNN +F 1 "d_and" H 6650 1950 60 0000 C CNN +F 2 "" H 6600 1850 60 0000 C CNN +F 3 "" H 6600 1850 60 0000 C CNN + 1 6600 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 5CF10756 +P 6600 2350 +F 0 "U16" H 6600 2350 60 0000 C CNN +F 1 "d_and" H 6650 2450 60 0000 C CNN +F 2 "" H 6600 2350 60 0000 C CNN +F 3 "" H 6600 2350 60 0000 C CNN + 1 6600 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 5CF107A1 +P 6600 2800 +F 0 "U17" H 6600 2800 60 0000 C CNN +F 1 "d_and" H 6650 2900 60 0000 C CNN +F 2 "" H 6600 2800 60 0000 C CNN +F 3 "" H 6600 2800 60 0000 C CNN + 1 6600 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5CF107E9 +P 6600 3200 +F 0 "U18" H 6600 3200 60 0000 C CNN +F 1 "d_and" H 6650 3300 60 0000 C CNN +F 2 "" H 6600 3200 60 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5CF10834 +P 6600 3650 +F 0 "U19" H 6600 3650 60 0000 C CNN +F 1 "d_and" H 6650 3750 60 0000 C CNN +F 2 "" H 6600 3650 60 0000 C CNN +F 3 "" H 6600 3650 60 0000 C CNN + 1 6600 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5CF1087E +P 6600 4050 +F 0 "U20" H 6600 4050 60 0000 C CNN +F 1 "d_and" H 6650 4150 60 0000 C CNN +F 2 "" H 6600 4050 60 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5CF108F9 +P 6600 4450 +F 0 "U21" H 6600 4450 60 0000 C CNN +F 1 "d_and" H 6650 4550 60 0000 C CNN +F 2 "" H 6600 4450 60 0000 C CNN +F 3 "" H 6600 4450 60 0000 C CNN + 1 6600 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5CF1094D +P 6550 4900 +F 0 "U13" H 6550 4900 60 0000 C CNN +F 1 "d_and" H 6600 5000 60 0000 C CNN +F 2 "" H 6550 4900 60 0000 C CNN +F 3 "" H 6550 4900 60 0000 C CNN + 1 6550 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 5CF109A6 +P 6550 5350 +F 0 "U14" H 6550 5350 60 0000 C CNN +F 1 "d_and" H 6600 5450 60 0000 C CNN +F 2 "" H 6550 5350 60 0000 C CNN +F 3 "" H 6550 5350 60 0000 C CNN + 1 6550 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF11966 +P 1150 2400 +F 0 "U1" H 1200 2500 30 0000 C CNN +F 1 "PORT" H 1150 2400 30 0000 C CNN +F 2 "" H 1150 2400 60 0000 C CNN +F 3 "" H 1150 2400 60 0000 C CNN + 10 1150 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF119D4 +P 1150 3300 +F 0 "U1" H 1200 3400 30 0000 C CNN +F 1 "PORT" H 1150 3300 30 0000 C CNN +F 2 "" H 1150 3300 60 0000 C CNN +F 3 "" H 1150 3300 60 0000 C CNN + 13 1150 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF11AFC +P 1200 4150 +F 0 "U1" H 1250 4250 30 0000 C CNN +F 1 "PORT" H 1200 4150 30 0000 C CNN +F 2 "" H 1200 4150 60 0000 C CNN +F 3 "" H 1200 4150 60 0000 C CNN + 12 1200 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF11B6B +P 1200 4900 +F 0 "U1" H 1250 5000 30 0000 C CNN +F 1 "PORT" H 1200 4900 30 0000 C CNN +F 2 "" H 1200 4900 60 0000 C CNN +F 3 "" H 1200 4900 60 0000 C CNN + 11 1200 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF11BDB +P 8000 1800 +F 0 "U1" H 8050 1900 30 0000 C CNN +F 1 "PORT" H 8000 1800 30 0000 C CNN +F 2 "" H 8000 1800 60 0000 C CNN +F 3 "" H 8000 1800 60 0000 C CNN + 3 8000 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11F59 +P 8000 2300 +F 0 "U1" H 8050 2400 30 0000 C CNN +F 1 "PORT" H 8000 2300 30 0000 C CNN +F 2 "" H 8000 2300 60 0000 C CNN +F 3 "" H 8000 2300 60 0000 C CNN + 14 8000 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF11FC5 +P 8000 2750 +F 0 "U1" H 8050 2850 30 0000 C CNN +F 1 "PORT" H 8000 2750 30 0000 C CNN +F 2 "" H 8000 2750 60 0000 C CNN +F 3 "" H 8000 2750 60 0000 C CNN + 2 8000 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 5CF1204F +P 8000 3150 +F 0 "U1" H 8050 3250 30 0000 C CNN +F 1 "PORT" H 8000 3150 30 0000 C CNN +F 2 "" H 8000 3150 60 0000 C CNN +F 3 "" H 8000 3150 60 0000 C CNN + 15 8000 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF120C5 +P 7950 3600 +F 0 "U1" H 8000 3700 30 0000 C CNN +F 1 "PORT" H 7950 3600 30 0000 C CNN +F 2 "" H 7950 3600 60 0000 C CNN +F 3 "" H 7950 3600 60 0000 C CNN + 1 7950 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF1213C +P 7950 4000 +F 0 "U1" H 8000 4100 30 0000 C CNN +F 1 "PORT" H 7950 4000 30 0000 C CNN +F 2 "" H 7950 4000 60 0000 C CNN +F 3 "" H 7950 4000 60 0000 C CNN + 6 7950 4000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CF121B2 +P 7900 4400 +F 0 "U1" H 7950 4500 30 0000 C CNN +F 1 "PORT" H 7900 4400 30 0000 C CNN +F 2 "" H 7900 4400 60 0000 C CNN +F 3 "" H 7900 4400 60 0000 C CNN + 7 7900 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF1223D +P 7900 4850 +F 0 "U1" H 7950 4950 30 0000 C CNN +F 1 "PORT" H 7900 4850 30 0000 C CNN +F 2 "" H 7900 4850 60 0000 C CNN +F 3 "" H 7900 4850 60 0000 C CNN + 4 7900 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF1237B +P 7900 5300 +F 0 "U1" H 7950 5400 30 0000 C CNN +F 1 "PORT" H 7900 5300 30 0000 C CNN +F 2 "" H 7900 5300 60 0000 C CNN +F 3 "" H 7900 5300 60 0000 C CNN + 9 7900 5300 + -1 0 0 1 +$EndComp +Wire Wire Line + 7750 1800 7050 1800 +Wire Wire Line + 7050 2300 7750 2300 +Wire Wire Line + 7750 2750 7050 2750 +Wire Wire Line + 7050 3150 7750 3150 +Wire Wire Line + 7700 3600 7050 3600 +Wire Wire Line + 7050 4000 7700 4000 +Wire Wire Line + 7650 4400 7050 4400 +Wire Wire Line + 7000 4850 7650 4850 +Wire Wire Line + 7650 5300 7000 5300 +$Comp +L d_and U22 +U 1 1 5CF14904 +P 6550 5800 +F 0 "U22" H 6550 5800 60 0000 C CNN +F 1 "d_and" H 6600 5900 60 0000 C CNN +F 2 "" H 6550 5800 60 0000 C CNN +F 3 "" H 6550 5800 60 0000 C CNN + 1 6550 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 1950 4600 1950 +Wire Wire Line + 4600 1750 4600 5250 +Wire Wire Line + 4600 1750 6150 1750 +Wire Wire Line + 4600 5250 6100 5250 +Connection ~ 4600 1950 +Wire Wire Line + 6100 5800 5900 5800 +Wire Wire Line + 5900 5800 5900 5350 +Wire Wire Line + 5900 5350 6100 5350 +Wire Wire Line + 5850 4900 6100 4900 +Wire Wire Line + 5850 3650 5850 4900 +Wire Wire Line + 5850 4450 6150 4450 +Wire Wire Line + 5850 4050 6150 4050 +Connection ~ 5850 4450 +Wire Wire Line + 5850 3650 6150 3650 +Connection ~ 5850 4050 +Wire Wire Line + 5050 3200 6150 3200 +Wire Wire Line + 5850 1850 5850 3200 +Wire Wire Line + 5850 2800 6150 2800 +Wire Wire Line + 5850 2350 6150 2350 +Connection ~ 5850 2800 +Wire Wire Line + 5850 1850 6150 1850 +Connection ~ 5850 2350 +Wire Wire Line + 4200 2450 4700 2450 +Wire Wire Line + 4700 2250 4700 5700 +Wire Wire Line + 4700 2250 6150 2250 +Wire Wire Line + 4200 3000 4800 3000 +Wire Wire Line + 4800 2700 4800 4350 +Wire Wire Line + 4800 2700 6150 2700 +Wire Wire Line + 4700 5700 6100 5700 +Connection ~ 4700 2450 +Wire Wire Line + 6150 3550 4600 3550 +Connection ~ 4600 3550 +Wire Wire Line + 6150 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4800 4350 6150 4350 +Connection ~ 4800 3000 +Wire Wire Line + 4200 3500 4900 3500 +Wire Wire Line + 4900 3100 4900 4800 +Wire Wire Line + 4900 3100 6150 3100 +Wire Wire Line + 4900 4800 6100 4800 +Connection ~ 4900 3500 +Wire Wire Line + 4200 4100 5050 4100 +Wire Wire Line + 5050 4100 5050 3200 +Connection ~ 5850 3200 +Wire Wire Line + 4150 4700 5850 4700 +Connection ~ 5850 4700 +Wire Wire Line + 4150 5200 4500 5200 +Wire Wire Line + 4500 5200 4500 5550 +Wire Wire Line + 4500 5550 5900 5550 +Connection ~ 5900 5550 +$Comp +L PORT U1 +U 5 1 5CF1563E +P 7950 5750 +F 0 "U1" H 8000 5850 30 0000 C CNN +F 1 "PORT" H 7950 5750 30 0000 C CNN +F 2 "" H 7950 5750 60 0000 C CNN +F 3 "" H 7950 5750 60 0000 C CNN + 5 7950 5750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 5750 7000 5750 +$Comp +L PORT U1 +U 8 1 5CF15953 +P 9550 4800 +F 0 "U1" H 9600 4900 30 0000 C CNN +F 1 "PORT" H 9550 4800 30 0000 C CNN +F 2 "" H 9550 4800 60 0000 C CNN +F 3 "" H 9550 4800 60 0000 C CNN + 8 9550 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5CF15A07 +P 9550 5250 +F 0 "U1" H 9600 5350 30 0000 C CNN +F 1 "PORT" H 9550 5250 30 0000 C CNN +F 2 "" H 9550 5250 60 0000 C CNN +F 3 "" H 9550 5250 60 0000 C CNN + 16 9550 5250 + -1 0 0 1 +$EndComp +NoConn ~ 9300 4800 +NoConn ~ 9300 5250 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4028/4028.sub b/src/SubcircuitLibrary/4028/4028.sub new file mode 100644 index 00000000..828e0b67 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028 +.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4028
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/analysis b/src/SubcircuitLibrary/4028/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4028/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and-cache.lib b/src/SubcircuitLibrary/4073/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4073/3_and.bak b/src/SubcircuitLibrary/4073/3_and.bak new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/3_and.cir b/src/SubcircuitLibrary/4073/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4073/3_and.cir.out b/src/SubcircuitLibrary/4073/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4073/3_and.pro b/src/SubcircuitLibrary/4073/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4073/3_and.sch b/src/SubcircuitLibrary/4073/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/3_and.sub b/src/SubcircuitLibrary/4073/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073-cache.lib b/src/SubcircuitLibrary/4073/4073-cache.lib new file mode 100644 index 00000000..4ee605a2 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4073/4073.cir b/src/SubcircuitLibrary/4073/4073.cir new file mode 100644 index 00000000..e159f055 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and + +.end diff --git a/src/SubcircuitLibrary/4073/4073.cir.out b/src/SubcircuitLibrary/4073/4073.cir.out new file mode 100644 index 00000000..b25337cd --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.cir.out @@ -0,0 +1,16 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4073/4073.pro b/src/SubcircuitLibrary/4073/4073.pro new file mode 100644 index 00000000..94cd9bd4 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.pro @@ -0,0 +1,43 @@ +update=05/31/19 16:37:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4073/4073.sch b/src/SubcircuitLibrary/4073/4073.sch new file mode 100644 index 00000000..045208e6 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.sch @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5CF10AEA +P 4550 2650 +F 0 "X1" H 4650 2600 60 0000 C CNN +F 1 "3_and" H 4700 2800 60 0000 C CNN +F 2 "" H 4550 2650 60 0000 C CNN +F 3 "" H 4550 2650 60 0000 C CNN + 1 4550 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF10B72 +P 3100 2200 +F 0 "U1" H 3150 2300 30 0000 C CNN +F 1 "PORT" H 3100 2200 30 0000 C CNN +F 2 "" H 3100 2200 60 0000 C CNN +F 3 "" H 3100 2200 60 0000 C CNN + 1 3100 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF10BC9 +P 3100 2500 +F 0 "U1" H 3150 2600 30 0000 C CNN +F 1 "PORT" H 3100 2500 30 0000 C CNN +F 2 "" H 3100 2500 60 0000 C CNN +F 3 "" H 3100 2500 60 0000 C CNN + 2 3100 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF10BEA +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 8 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF10C10 +P 6200 2600 +F 0 "U1" H 6250 2700 30 0000 C CNN +F 1 "PORT" H 6200 2600 30 0000 C CNN +F 2 "" H 6200 2600 60 0000 C CNN +F 3 "" H 6200 2600 60 0000 C CNN + 9 6200 2600 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2600 5050 2600 +Wire Wire Line + 4200 2500 4200 2200 +Wire Wire Line + 4200 2200 3350 2200 +Wire Wire Line + 3350 2500 3850 2500 +Wire Wire Line + 3850 2500 3850 2600 +Wire Wire Line + 3850 2600 4200 2600 +Wire Wire Line + 4200 2700 4200 2850 +Wire Wire Line + 4200 2850 3350 2850 +$Comp +L 3_and X3 +U 1 1 5CF10DE5 +P 4600 4100 +F 0 "X3" H 4700 4050 60 0000 C CNN +F 1 "3_and" H 4750 4250 60 0000 C CNN +F 2 "" H 4600 4100 60 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4600 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF10DEB +P 3150 3650 +F 0 "U1" H 3200 3750 30 0000 C CNN +F 1 "PORT" H 3150 3650 30 0000 C CNN +F 2 "" H 3150 3650 60 0000 C CNN +F 3 "" H 3150 3650 60 0000 C CNN + 3 3150 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF10DF1 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 4 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF10DF7 +P 3150 4300 +F 0 "U1" H 3200 4400 30 0000 C CNN +F 1 "PORT" H 3150 4300 30 0000 C CNN +F 2 "" H 3150 4300 60 0000 C CNN +F 3 "" H 3150 4300 60 0000 C CNN + 5 3150 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF10DFD +P 6250 4050 +F 0 "U1" H 6300 4150 30 0000 C CNN +F 1 "PORT" H 6250 4050 30 0000 C CNN +F 2 "" H 6250 4050 60 0000 C CNN +F 3 "" H 6250 4050 60 0000 C CNN + 6 6250 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6000 4050 5100 4050 +Wire Wire Line + 4250 3950 4250 3650 +Wire Wire Line + 4250 3650 3400 3650 +Wire Wire Line + 3400 3950 3900 3950 +Wire Wire Line + 3900 3950 3900 4050 +Wire Wire Line + 3900 4050 4250 4050 +Wire Wire Line + 4250 4150 4250 4300 +Wire Wire Line + 4250 4300 3400 4300 +$Comp +L 3_and X2 +U 1 1 5CF10E9C +P 4550 5450 +F 0 "X2" H 4650 5400 60 0000 C CNN +F 1 "3_and" H 4700 5600 60 0000 C CNN +F 2 "" H 4550 5450 60 0000 C CNN +F 3 "" H 4550 5450 60 0000 C CNN + 1 4550 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF10EA2 +P 3100 5000 +F 0 "U1" H 3150 5100 30 0000 C CNN +F 1 "PORT" H 3100 5000 30 0000 C CNN +F 2 "" H 3100 5000 60 0000 C CNN +F 3 "" H 3100 5000 60 0000 C CNN + 11 3100 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF10EA8 +P 3100 5300 +F 0 "U1" H 3150 5400 30 0000 C CNN +F 1 "PORT" H 3100 5300 30 0000 C CNN +F 2 "" H 3100 5300 60 0000 C CNN +F 3 "" H 3100 5300 60 0000 C CNN + 12 3100 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF10EAE +P 3100 5650 +F 0 "U1" H 3150 5750 30 0000 C CNN +F 1 "PORT" H 3100 5650 30 0000 C CNN +F 2 "" H 3100 5650 60 0000 C CNN +F 3 "" H 3100 5650 60 0000 C CNN + 13 3100 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF10EB4 +P 6200 5400 +F 0 "U1" H 6250 5500 30 0000 C CNN +F 1 "PORT" H 6200 5400 30 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 10 6200 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 5400 5050 5400 +Wire Wire Line + 4200 5300 4200 5000 +Wire Wire Line + 4200 5000 3350 5000 +Wire Wire Line + 3350 5300 3850 5300 +Wire Wire Line + 3850 5300 3850 5400 +Wire Wire Line + 3850 5400 4200 5400 +Wire Wire Line + 4200 5500 4200 5650 +Wire Wire Line + 4200 5650 3350 5650 +$Comp +L PORT U1 +U 7 1 5CF11A2A +P 7500 4100 +F 0 "U1" H 7550 4200 30 0000 C CNN +F 1 "PORT" H 7500 4100 30 0000 C CNN +F 2 "" H 7500 4100 60 0000 C CNN +F 3 "" H 7500 4100 60 0000 C CNN + 7 7500 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11A8A +P 7550 4600 +F 0 "U1" H 7600 4700 30 0000 C CNN +F 1 "PORT" H 7550 4600 30 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 14 7550 4600 + -1 0 0 1 +$EndComp +NoConn ~ 7250 4100 +NoConn ~ 7300 4600 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/4073.sub b/src/SubcircuitLibrary/4073/4073.sub new file mode 100644 index 00000000..15208169 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073.sub @@ -0,0 +1,10 @@ +* Subcircuit 4073 +.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +* Control Statements + +.ends 4073
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073_Previous_Values.xml b/src/SubcircuitLibrary/4073/4073_Previous_Values.xml new file mode 100644 index 00000000..5acac768 --- /dev/null +++ b/src/SubcircuitLibrary/4073/4073_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/analysis b/src/SubcircuitLibrary/4073/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4073/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro new file mode 100644 index 00000000..9daf26bc --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.pro @@ -0,0 +1,45 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/analysis b/src/SubcircuitLibrary/4_OR/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_OR/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/3_and.bak b/src/SubcircuitLibrary/4_and/3_and.bak new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and.bak b/src/SubcircuitLibrary/4_and/4_and.bak new file mode 100644 index 00000000..a5be7d26 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.bak @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro new file mode 100644 index 00000000..9c0be79e --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.pro @@ -0,0 +1,58 @@ +update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/analysis b/src/SubcircuitLibrary/4_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.bak b/src/SubcircuitLibrary/4to16_demux/3_and.bak new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir b/src/SubcircuitLibrary/4to16_demux/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.pro b/src/SubcircuitLibrary/4to16_demux/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sch b/src/SubcircuitLibrary/4to16_demux/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sub b/src/SubcircuitLibrary/4to16_demux/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib b/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib new file mode 100644 index 00000000..898ea926 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_nand +# +DEF 5_nand X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_nand" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.bak b/src/SubcircuitLibrary/4to16_demux/4to16_demux.bak new file mode 100644 index 00000000..c9142e27 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.bak @@ -0,0 +1,889 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4to16_demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 5CF2315F +P 4700 1900 +F 0 "U3" H 4700 1800 60 0000 C CNN +F 1 "d_inverter" H 4700 2050 60 0000 C CNN +F 2 "" H 4750 1850 60 0000 C CNN +F 3 "" H 4750 1850 60 0000 C CNN + 1 4700 1900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF231D7 +P 5600 1850 +F 0 "U4" H 5600 1750 60 0000 C CNN +F 1 "d_inverter" H 5600 2000 60 0000 C CNN +F 2 "" H 5650 1800 60 0000 C CNN +F 3 "" H 5650 1800 60 0000 C CNN + 1 5600 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF23245 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"PORT" H 2150 6200 30 0000 C CNN +F 2 "" H 2150 6200 60 0000 C CNN +F 3 "" H 2150 6200 60 0000 C CNN + 2 2150 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF2E23B +P 2700 6200 +F 0 "U1" H 2750 6300 30 0000 C CNN +F 1 "PORT" H 2700 6200 30 0000 C CNN +F 2 "" H 2700 6200 60 0000 C CNN +F 3 "" H 2700 6200 60 0000 C CNN + 3 2700 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF2E2B3 +P 3250 6200 +F 0 "U1" H 3300 6300 30 0000 C CNN +F 1 "PORT" H 3250 6200 30 0000 C CNN +F 2 "" H 3250 6200 60 0000 C CNN +F 3 "" H 3250 6200 60 0000 C CNN + 4 3250 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF2E32C +P 3800 6200 +F 0 "U1" H 3850 6300 30 0000 C CNN +F 1 "PORT" H 3800 6200 30 0000 C CNN +F 2 "" H 3800 6200 60 0000 C CNN +F 3 "" H 3800 6200 60 0000 C CNN + 5 3800 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF2E3CE +P 4350 6200 +F 0 "U1" H 4400 6300 30 0000 C CNN +F 1 "PORT" H 4350 6200 30 0000 C CNN +F 2 "" H 4350 6200 60 0000 C CNN +F 3 "" H 4350 6200 60 0000 C CNN + 6 4350 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5CF2E4B6 +P 4900 6200 +F 0 "U1" H 4950 6300 30 0000 C CNN +F 1 "PORT" H 4900 6200 30 0000 C CNN +F 2 "" H 4900 6200 60 0000 C CNN +F 3 "" H 4900 6200 60 0000 C CNN + 7 4900 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF2E5CA +P 5450 6200 +F 0 "U1" H 5500 6300 30 0000 C CNN +F 1 "PORT" H 5450 6200 30 0000 C CNN +F 2 "" H 5450 6200 60 0000 C CNN +F 3 "" H 5450 6200 60 0000 C CNN + 8 5450 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF2E651 +P 6000 6200 +F 0 "U1" H 6050 6300 30 0000 C CNN +F 1 "PORT" H 6000 6200 30 0000 C CNN +F 2 "" H 6000 6200 60 0000 C CNN +F 3 "" H 6000 6200 60 0000 C CNN + 9 6000 6200 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF2E6E3 +P 6600 6150 +F 0 "U1" H 6650 6250 30 0000 C CNN +F 1 "PORT" H 6600 6150 30 0000 C CNN +F 2 "" H 6600 6150 60 0000 C CNN +F 3 "" H 6600 6150 60 0000 C CNN + 10 6600 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF2E770 +P 7150 6150 +F 0 "U1" H 7200 6250 30 0000 C CNN +F 1 "PORT" H 7150 6150 30 0000 C CNN +F 2 "" H 7150 6150 60 0000 C CNN +F 3 "" H 7150 6150 60 0000 C CNN + 11 7150 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF2E7F8 +P 7700 6150 +F 0 "U1" H 7750 6250 30 0000 C CNN +F 1 "PORT" H 7700 6150 30 0000 C CNN +F 2 "" H 7700 6150 60 0000 C CNN +F 3 "" H 7700 6150 60 0000 C CNN + 13 7700 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF2E989 +P 8250 6150 +F 0 "U1" H 8300 6250 30 0000 C CNN +F 1 "PORT" H 8250 6150 30 0000 C CNN +F 2 "" H 8250 6150 60 0000 C CNN +F 3 "" H 8250 6150 60 0000 C CNN + 14 8250 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 5CF2EA23 +P 8800 6150 +F 0 "U1" H 8850 6250 30 0000 C CNN +F 1 "PORT" H 8800 6150 30 0000 C CNN +F 2 "" H 8800 6150 60 0000 C CNN +F 3 "" H 8800 6150 60 0000 C CNN + 15 8800 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 16 1 5CF2EABA +P 9350 6150 +F 0 "U1" H 9400 6250 30 0000 C CNN +F 1 "PORT" H 9350 6150 30 0000 C CNN +F 2 "" H 9350 6150 60 0000 C CNN +F 3 "" H 9350 6150 60 0000 C CNN + 16 9350 6150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 17 1 5CF2EB7A +P 9900 6100 +F 0 "U1" H 9950 6200 30 0000 C CNN +F 1 "PORT" H 9900 6100 30 0000 C CNN +F 2 "" H 9900 6100 60 0000 C CNN +F 3 "" H 9900 6100 60 0000 C CNN + 17 9900 6100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 9900 5850 9900 5400 +Wire Wire Line + 9350 5400 9350 5900 +Wire Wire Line + 8800 5400 8800 5900 +Wire Wire Line + 8250 5400 8250 5900 +Wire Wire Line + 7700 5400 7700 5900 +Wire Wire Line + 7150 5400 7150 5900 +Wire Wire Line + 6600 5400 6600 5900 +Wire Wire Line + 6000 5400 6000 5950 +Wire Wire Line + 5450 5400 5450 5950 +Wire Wire Line + 4900 5400 4900 5950 +Wire Wire Line + 4350 5400 4350 5950 +Wire Wire Line + 3800 5400 3800 5950 +Wire Wire Line + 3250 5400 3250 5950 +Wire Wire Line + 2700 5400 2700 5950 +Wire Wire Line + 2150 5400 2150 5950 +Wire Wire Line + 1600 5400 1600 5950 +$Comp +L PORT U1 +U 24 1 5CF327C1 +P 6500 6950 +F 0 "U1" H 6550 7050 30 0000 C CNN +F 1 "PORT" H 6500 6950 30 0000 C CNN +F 2 "" H 6500 6950 60 0000 C CNN +F 3 "" H 6500 6950 60 0000 C CNN + 24 6500 6950 + 0 -1 -1 0 +$EndComp +NoConn ~ 6500 6700 +$Comp +L PORT U1 +U 12 1 5CF33A86 +P 3400 900 +F 0 "U1" H 3450 1000 30 0000 C CNN +F 1 "PORT" H 3400 900 30 0000 C CNN +F 2 "" H 3400 900 60 0000 C CNN +F 3 "" H 3400 900 60 0000 C CNN + 12 3400 900 + 0 1 1 0 +$EndComp +NoConn ~ 3400 1150 +$Comp +L 5_nand X1 +U 1 1 5D0CC4BF +P 1600 4850 +F 0 "X1" H 1650 4750 60 0000 C CNN +F 1 "5_nand" H 1700 5000 60 0000 C CNN +F 2 "" H 1600 4850 60 0000 C CNN +F 3 "" H 1600 4850 60 0000 C CNN + 1 1600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X2 +U 1 1 5D0CC967 +P 2150 4850 +F 0 "X2" H 2200 4750 60 0000 C CNN +F 1 "5_nand" H 2250 5000 60 0000 C CNN +F 2 "" H 2150 4850 60 0000 C CNN +F 3 "" H 2150 4850 60 0000 C CNN + 1 2150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X3 +U 1 1 5D0CC9F8 +P 2700 4850 +F 0 "X3" H 2750 4750 60 0000 C CNN +F 1 "5_nand" H 2800 5000 60 0000 C CNN +F 2 "" H 2700 4850 60 0000 C CNN +F 3 "" H 2700 4850 60 0000 C CNN + 1 2700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X4 +U 1 1 5D0CCA7E +P 3250 4850 +F 0 "X4" H 3300 4750 60 0000 C CNN +F 1 "5_nand" H 3350 5000 60 0000 C CNN +F 2 "" H 3250 4850 60 0000 C CNN +F 3 "" H 3250 4850 60 0000 C CNN + 1 3250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X5 +U 1 1 5D0CCB6A +P 3800 4850 +F 0 "X5" H 3850 4750 60 0000 C CNN +F 1 "5_nand" H 3900 5000 60 0000 C CNN +F 2 "" H 3800 4850 60 0000 C CNN +F 3 "" H 3800 4850 60 0000 C CNN + 1 3800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X6 +U 1 1 5D0CCBF6 +P 4350 4850 +F 0 "X6" H 4400 4750 60 0000 C CNN +F 1 "5_nand" H 4450 5000 60 0000 C CNN +F 2 "" H 4350 4850 60 0000 C CNN +F 3 "" H 4350 4850 60 0000 C CNN + 1 4350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X7 +U 1 1 5D0CCC81 +P 4900 4850 +F 0 "X7" H 4950 4750 60 0000 C CNN +F 1 "5_nand" H 5000 5000 60 0000 C CNN +F 2 "" H 4900 4850 60 0000 C CNN +F 3 "" H 4900 4850 60 0000 C CNN + 1 4900 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X8 +U 1 1 5D0CCD0B +P 5450 4850 +F 0 "X8" H 5500 4750 60 0000 C CNN +F 1 "5_nand" H 5550 5000 60 0000 C CNN +F 2 "" H 5450 4850 60 0000 C CNN +F 3 "" H 5450 4850 60 0000 C CNN + 1 5450 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X9 +U 1 1 5D0CCE34 +P 6000 4850 +F 0 "X9" H 6050 4750 60 0000 C CNN +F 1 "5_nand" H 6100 5000 60 0000 C CNN +F 2 "" H 6000 4850 60 0000 C CNN +F 3 "" H 6000 4850 60 0000 C CNN + 1 6000 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X10 +U 1 1 5D0CCECA +P 6600 4850 +F 0 "X10" H 6650 4750 60 0000 C CNN +F 1 "5_nand" H 6700 5000 60 0000 C CNN +F 2 "" H 6600 4850 60 0000 C CNN +F 3 "" H 6600 4850 60 0000 C CNN + 1 6600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X11 +U 1 1 5D0CCF63 +P 7150 4850 +F 0 "X11" H 7200 4750 60 0000 C CNN +F 1 "5_nand" H 7250 5000 60 0000 C CNN +F 2 "" H 7150 4850 60 0000 C CNN +F 3 "" H 7150 4850 60 0000 C CNN + 1 7150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X12 +U 1 1 5D0CD07D +P 7700 4850 +F 0 "X12" H 7750 4750 60 0000 C CNN +F 1 "5_nand" H 7800 5000 60 0000 C CNN +F 2 "" H 7700 4850 60 0000 C CNN +F 3 "" H 7700 4850 60 0000 C CNN + 1 7700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X13 +U 1 1 5D0CD124 +P 8250 4850 +F 0 "X13" H 8300 4750 60 0000 C CNN +F 1 "5_nand" H 8350 5000 60 0000 C CNN +F 2 "" H 8250 4850 60 0000 C CNN +F 3 "" H 8250 4850 60 0000 C CNN + 1 8250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X14 +U 1 1 5D0CD1C6 +P 8800 4850 +F 0 "X14" H 8850 4750 60 0000 C CNN +F 1 "5_nand" H 8900 5000 60 0000 C CNN +F 2 "" H 8800 4850 60 0000 C CNN +F 3 "" H 8800 4850 60 0000 C CNN + 1 8800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X15 +U 1 1 5D0CD348 +P 9350 4850 +F 0 "X15" H 9400 4750 60 0000 C CNN +F 1 "5_nand" H 9450 5000 60 0000 C CNN +F 2 "" H 9350 4850 60 0000 C CNN +F 3 "" H 9350 4850 60 0000 C CNN + 1 9350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X16 +U 1 1 5D0CD3EE +P 9900 4850 +F 0 "X16" H 9950 4750 60 0000 C CNN +F 1 "5_nand" H 10000 5000 60 0000 C CNN +F 2 "" H 9900 4850 60 0000 C CNN +F 3 "" H 9900 4850 60 0000 C CNN + 1 9900 4850 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir new file mode 100644 index 00000000..c97c2f8b --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir @@ -0,0 +1,32 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 17:01:07 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad23_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad22_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad21_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad20_ Net-_U6-Pad2_ d_inverter +U2 Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U2-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT +X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad1_ 5_nand +X2 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad2_ 5_nand +X3 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad3_ 5_nand +X4 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad4_ 5_nand +X5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad5_ 5_nand +X6 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad6_ 5_nand +X7 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad7_ 5_nand +X8 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad8_ 5_nand +X9 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad9_ 5_nand +X10 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad10_ 5_nand +X11 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad11_ 5_nand +X12 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad13_ 5_nand +X13 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad14_ 5_nand +X14 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad15_ 5_nand +X15 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad16_ 5_nand +X16 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad17_ 5_nand + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out new file mode 100644 index 00000000..eecdfb06 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out @@ -0,0 +1,49 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir + +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro b/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro new file mode 100644 index 00000000..5a167cd9 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro @@ -0,0 +1,43 @@ +update=Fri Jun 21 16:58:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_User +LibName10=eSim_Subckt diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch new file mode 100644 index 00000000..c9142e27 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch @@ -0,0 +1,889 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4to16_demux-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 5CF2315F +P 4700 1900 +F 0 "U3" H 4700 1800 60 0000 C CNN +F 1 "d_inverter" H 4700 2050 60 0000 C CNN +F 2 "" H 4750 1850 60 0000 C CNN +F 3 "" H 4750 1850 60 0000 C CNN + 1 4700 1900 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF231D7 +P 5600 1850 +F 0 "U4" H 5600 1750 60 0000 C CNN +F 1 "d_inverter" H 5600 2000 60 0000 C CNN +F 2 "" H 5650 1800 60 0000 C CNN +F 3 "" H 5650 1800 60 0000 C CNN + 1 5600 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF23245 +P 6550 1850 +F 0 "U5" H 6550 1750 60 0000 C CNN +F 1 "d_inverter" H 6550 2000 60 0000 C CNN +F 2 "" H 6600 1800 60 0000 C CNN +F 3 "" H 6600 1800 60 0000 C CNN + 1 6550 1850 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5CF232B2 +P 7500 1800 +F 0 "U6" H 7500 1700 60 0000 C CNN +F 1 "d_inverter" H 7500 1950 60 0000 C CNN +F 2 "" H 7550 1750 60 0000 C CNN +F 3 "" H 7550 1750 60 0000 C CNN + 1 7500 1800 + 0 1 1 0 +$EndComp +Text Notes 1300 5450 0 60 ~ 0 +~Y0 +Text Notes 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C CNN +F 3 "" H 3800 4850 60 0000 C CNN + 1 3800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X6 +U 1 1 5D0CCBF6 +P 4350 4850 +F 0 "X6" H 4400 4750 60 0000 C CNN +F 1 "5_nand" H 4450 5000 60 0000 C CNN +F 2 "" H 4350 4850 60 0000 C CNN +F 3 "" H 4350 4850 60 0000 C CNN + 1 4350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X7 +U 1 1 5D0CCC81 +P 4900 4850 +F 0 "X7" H 4950 4750 60 0000 C CNN +F 1 "5_nand" H 5000 5000 60 0000 C CNN +F 2 "" H 4900 4850 60 0000 C CNN +F 3 "" H 4900 4850 60 0000 C CNN + 1 4900 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X8 +U 1 1 5D0CCD0B +P 5450 4850 +F 0 "X8" H 5500 4750 60 0000 C CNN +F 1 "5_nand" H 5550 5000 60 0000 C CNN +F 2 "" H 5450 4850 60 0000 C CNN +F 3 "" H 5450 4850 60 0000 C CNN + 1 5450 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X9 +U 1 1 5D0CCE34 +P 6000 4850 +F 0 "X9" H 6050 4750 60 0000 C CNN +F 1 "5_nand" H 6100 5000 60 0000 C CNN +F 2 "" H 6000 4850 60 0000 C CNN +F 3 "" H 6000 4850 60 0000 C CNN + 1 6000 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X10 +U 1 1 5D0CCECA +P 6600 4850 +F 0 "X10" H 6650 4750 60 0000 C CNN +F 1 "5_nand" H 6700 5000 60 0000 C CNN +F 2 "" H 6600 4850 60 0000 C CNN +F 3 "" H 6600 4850 60 0000 C CNN + 1 6600 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X11 +U 1 1 5D0CCF63 +P 7150 4850 +F 0 "X11" H 7200 4750 60 0000 C CNN +F 1 "5_nand" H 7250 5000 60 0000 C CNN +F 2 "" H 7150 4850 60 0000 C CNN +F 3 "" H 7150 4850 60 0000 C CNN + 1 7150 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X12 +U 1 1 5D0CD07D +P 7700 4850 +F 0 "X12" H 7750 4750 60 0000 C CNN +F 1 "5_nand" H 7800 5000 60 0000 C CNN +F 2 "" H 7700 4850 60 0000 C CNN +F 3 "" H 7700 4850 60 0000 C CNN + 1 7700 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X13 +U 1 1 5D0CD124 +P 8250 4850 +F 0 "X13" H 8300 4750 60 0000 C CNN +F 1 "5_nand" H 8350 5000 60 0000 C CNN +F 2 "" H 8250 4850 60 0000 C CNN +F 3 "" H 8250 4850 60 0000 C CNN + 1 8250 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X14 +U 1 1 5D0CD1C6 +P 8800 4850 +F 0 "X14" H 8850 4750 60 0000 C CNN +F 1 "5_nand" H 8900 5000 60 0000 C CNN +F 2 "" H 8800 4850 60 0000 C CNN +F 3 "" H 8800 4850 60 0000 C CNN + 1 8800 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X15 +U 1 1 5D0CD348 +P 9350 4850 +F 0 "X15" H 9400 4750 60 0000 C CNN +F 1 "5_nand" H 9450 5000 60 0000 C CNN +F 2 "" H 9350 4850 60 0000 C CNN +F 3 "" H 9350 4850 60 0000 C CNN + 1 9350 4850 + 0 1 1 0 +$EndComp +$Comp +L 5_nand X16 +U 1 1 5D0CD3EE +P 9900 4850 +F 0 "X16" H 9950 4750 60 0000 C CNN +F 1 "5_nand" H 10000 5000 60 0000 C CNN +F 2 "" H 9900 4850 60 0000 C CNN +F 3 "" H 9900 4850 60 0000 C CNN + 1 9900 4850 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub new file mode 100644 index 00000000..4f7595da --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub @@ -0,0 +1,43 @@ +* Subcircuit 4to16_demux +.subckt 4to16_demux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir +.include 5_nand.sub +* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter +* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand +x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand +x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand +x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand +x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand +x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand +x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand +x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand +x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand +x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand +x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand +x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand +x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand +x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand +x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand +x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand +a1 net-_u1-pad23_ net-_u3-pad2_ u3 +a2 net-_u1-pad22_ net-_u4-pad2_ u4 +a3 net-_u1-pad21_ net-_u5-pad2_ u5 +a4 net-_u1-pad20_ net-_u6-pad2_ u6 +a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4to16_demux
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml new file mode 100644 index 00000000..93c6f25a --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x13><x14><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x14><x15><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x15><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x9><x16><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x16><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x12><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.bak b/src/SubcircuitLibrary/4to16_demux/5_and.bak new file mode 100644 index 00000000..da927b09 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.bak @@ -0,0 +1,158 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir b/src/SubcircuitLibrary/4to16_demux/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.pro b/src/SubcircuitLibrary/4to16_demux/5_and.pro new file mode 100644 index 00000000..7a2f090e --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sch b/src/SubcircuitLibrary/4to16_demux/5_and.sch new file mode 100644 index 00000000..e9eb58ee --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sub b/src/SubcircuitLibrary/4to16_demux/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib new file mode 100644 index 00000000..cb517be1 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib @@ -0,0 +1,78 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir b/src/SubcircuitLibrary/4to16_demux/5_nand.cir new file mode 100644 index 00000000..e833d0f4 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.cir @@ -0,0 +1,13 @@ +* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and +U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out new file mode 100644 index 00000000..164de911 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out @@ -0,0 +1,18 @@ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir + +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.pro b/src/SubcircuitLibrary/4to16_demux/5_nand.pro new file mode 100644 index 00000000..b7d23f44 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.pro @@ -0,0 +1,83 @@ +update=Fri Jun 21 16:46:10 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog +LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User + diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sch b/src/SubcircuitLibrary/4to16_demux/5_nand.sch new file mode 100644 index 00000000..86379b08 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.sch @@ -0,0 +1,175 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5D0CBD44 +P 4150 3700 +F 0 "X1" H 4200 3600 60 0000 C CNN +F 1 "5_and" H 4250 3850 60 0000 C CNN +F 2 "" H 4150 3700 60 0000 C CNN +F 3 "" H 4150 3700 60 0000 C CNN + 1 4150 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5D0CBD97 +P 5150 3700 +F 0 "U2" H 5150 3600 60 0000 C CNN +F 1 "d_inverter" H 5150 3850 60 0000 C CNN +F 2 "" H 5200 3650 60 0000 C CNN +F 3 "" H 5200 3650 60 0000 C CNN + 1 5150 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5D0CBDBE +P 2900 2900 +F 0 "U1" H 2950 3000 30 0000 C CNN +F 1 "PORT" H 2900 2900 30 0000 C CNN +F 2 "" H 2900 2900 60 0000 C CNN +F 3 "" H 2900 2900 60 0000 C CNN + 1 2900 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5D0CBDF4 +P 2900 3150 +F 0 "U1" H 2950 3250 30 0000 C CNN +F 1 "PORT" H 2900 3150 30 0000 C CNN +F 2 "" H 2900 3150 60 0000 C CNN +F 3 "" H 2900 3150 60 0000 C CNN + 2 2900 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5D0CBE16 +P 2900 3400 +F 0 "U1" H 2950 3500 30 0000 C CNN +F 1 "PORT" H 2900 3400 30 0000 C CNN +F 2 "" H 2900 3400 60 0000 C CNN +F 3 "" H 2900 3400 60 0000 C CNN + 3 2900 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5D0CBE3F +P 2900 3750 +F 0 "U1" H 2950 3850 30 0000 C CNN +F 1 "PORT" H 2900 3750 30 0000 C CNN +F 2 "" H 2900 3750 60 0000 C CNN +F 3 "" H 2900 3750 60 0000 C CNN + 4 2900 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5D0CBE6B +P 2900 4150 +F 0 "U1" H 2950 4250 30 0000 C CNN +F 1 "PORT" H 2900 4150 30 0000 C CNN +F 2 "" H 2900 4150 60 0000 C CNN +F 3 "" H 2900 4150 60 0000 C CNN + 5 2900 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5D0CBE9C +P 6200 3700 +F 0 "U1" H 6250 3800 30 0000 C CNN +F 1 "PORT" H 6200 3700 30 0000 C CNN +F 2 "" H 6200 3700 60 0000 C CNN +F 3 "" H 6200 3700 60 0000 C CNN + 6 6200 3700 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 2900 3700 2900 +Wire Wire Line + 3700 2900 3700 3500 +Wire Wire Line + 3700 3600 3500 3600 +Wire Wire Line + 3500 3600 3500 3150 +Wire Wire Line + 3500 3150 3150 3150 +Wire Wire Line + 3150 3400 3350 3400 +Wire Wire Line + 3350 3400 3350 3700 +Wire Wire Line + 3350 3700 3700 3700 +Wire Wire Line + 3700 3800 3250 3800 +Wire Wire Line + 3250 3800 3250 3750 +Wire Wire Line + 3250 3750 3150 3750 +Wire Wire Line + 3150 4150 3350 4150 +Wire Wire Line + 3350 4150 3350 3900 +Wire Wire Line + 3350 3900 3700 3900 +Wire Wire Line + 4700 3700 4850 3700 +Wire Wire Line + 5450 3700 5950 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sub b/src/SubcircuitLibrary/4to16_demux/5_nand.sub new file mode 100644 index 00000000..c3e041fa --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand.sub @@ -0,0 +1,12 @@ +* Subcircuit 5_nand +.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir +.include 5_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and +* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter +a1 net-_u2-pad1_ net-_u1-pad6_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_nand
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml new file mode 100644 index 00000000..c4b4cde2 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/analysis b/src/SubcircuitLibrary/4to16_demux/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4to16_demux/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/556/556-cache.lib b/src/SubcircuitLibrary/556/556-cache.lib new file mode 100644 index 00000000..75d610da --- /dev/null +++ b/src/SubcircuitLibrary/556/556-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/556/556.cir b/src/SubcircuitLibrary/556/556.cir new file mode 100644 index 00000000..48baa73e --- /dev/null +++ b/src/SubcircuitLibrary/556/556.cir @@ -0,0 +1,13 @@ +* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N +X2 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/src/SubcircuitLibrary/556/556.cir.out b/src/SubcircuitLibrary/556/556.cir.out new file mode 100644 index 00000000..c74aab7c --- /dev/null +++ b/src/SubcircuitLibrary/556/556.cir.out @@ -0,0 +1,15 @@ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir + +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/556/556.pro b/src/SubcircuitLibrary/556/556.pro new file mode 100644 index 00000000..a165313d --- /dev/null +++ b/src/SubcircuitLibrary/556/556.pro @@ -0,0 +1,72 @@ +update=03/18/19 18:13:51 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=microcontrollers +LibName12=dsp +LibName13=microchip +LibName14=analog_switches +LibName15=motorola +LibName16=texas +LibName17=intel +LibName18=audio +LibName19=interface +LibName20=digital-audio +LibName21=philips +LibName22=display +LibName23=cypress +LibName24=siliconi +LibName25=opto +LibName26=atmel +LibName27=contrib +LibName28=valves +LibName29=eSim_User +LibName30=eSim_Subckt +LibName31=eSim_Sources +LibName32=eSim_PSpice +LibName33=eSim_Power +LibName34=eSim_Plot +LibName35=eSim_Miscellaneous +LibName36=eSim_Hybrid +LibName37=eSim_Digital +LibName38=eSim_Devices +LibName39=eSim_Analog diff --git a/src/SubcircuitLibrary/556/556.sch b/src/SubcircuitLibrary/556/556.sch new file mode 100644 index 00000000..af4e1bc9 --- /dev/null +++ b/src/SubcircuitLibrary/556/556.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LM555N X1 +U 1 1 5C8F9298 +P 4150 3850 +F 0 "X1" H 4150 3800 60 0000 C CNN +F 1 "LM555N" H 4150 3950 60 0000 C CNN +F 2 "" H 4100 3850 60 0000 C CNN +F 3 "" H 4100 3850 60 0000 C CNN + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X2 +U 1 1 5C8F92E5 +P 7100 3850 +F 0 "X2" H 7100 3800 60 0000 C CNN +F 1 "LM555N" H 7100 3950 60 0000 C CNN +F 2 "" H 7050 3850 60 0000 C CNN +F 3 "" H 7050 3850 60 0000 C CNN + 1 7100 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 3250 4150 3000 +Wire Wire Line + 4150 3000 7100 3000 +Wire Wire Line + 4150 4450 4150 4650 +Wire Wire Line + 4150 4650 7100 4650 +$Comp +L PORT U1 +U 14 1 5C8F93E6 +P 4650 2600 +F 0 "U1" H 4700 2700 30 0000 C CNN +F 1 "PORT" H 4650 2600 30 0000 C CNN +F 2 "" H 4650 2600 60 0000 C CNN +F 3 "" H 4650 2600 60 0000 C CNN + 14 4650 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 2600 5000 2600 +Wire Wire Line + 5000 2600 5000 3000 +Connection ~ 5000 3000 +$Comp +L PORT U1 +U 6 1 5C8F94B6 +P 3050 3600 +F 0 "U1" H 3100 3700 30 0000 C CNN +F 1 "PORT" H 3050 3600 30 0000 C CNN +F 2 "" H 3050 3600 60 0000 C CNN +F 3 "" H 3050 3600 60 0000 C CNN + 6 3050 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C8F95C0 +P 3050 3850 +F 0 "U1" H 3100 3950 30 0000 C CNN +F 1 "PORT" H 3050 3850 30 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 3 3050 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C8F95E7 +P 3050 4100 +F 0 "U1" H 3100 4200 30 0000 C CNN +F 1 "PORT" H 3050 4100 30 0000 C CNN +F 2 "" H 3050 4100 60 0000 C CNN +F 3 "" H 3050 4100 60 0000 C CNN + 4 3050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 3000 7100 3250 +Wire Wire Line + 7100 4650 7100 4450 +$Comp +L PORT U1 +U 8 1 5C8F9C35 +P 6000 3600 +F 0 "U1" H 6050 3700 30 0000 C CNN +F 1 "PORT" H 6000 3600 30 0000 C CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 8 6000 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C8F9C3B +P 6000 3850 +F 0 "U1" H 6050 3950 30 0000 C CNN +F 1 "PORT" H 6000 3850 30 0000 C CNN +F 2 "" H 6000 3850 60 0000 C CNN +F 3 "" H 6000 3850 60 0000 C CNN + 11 6000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C8F9C41 +P 6000 4100 +F 0 "U1" H 6050 4200 30 0000 C CNN +F 1 "PORT" H 6000 4100 30 0000 C CNN +F 2 "" H 6000 4100 60 0000 C CNN +F 3 "" H 6000 4100 60 0000 C CNN + 10 6000 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C8F9D22 +P 5200 4100 +F 0 "U1" H 5250 4200 30 0000 C CNN +F 1 "PORT" H 5200 4100 30 0000 C CNN +F 2 "" H 5200 4100 60 0000 C CNN +F 3 "" H 5200 4100 60 0000 C CNN + 2 5200 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C8F9D28 +P 5200 3850 +F 0 "U1" H 5250 3950 30 0000 C CNN +F 1 "PORT" H 5200 3850 30 0000 C CNN +F 2 "" H 5200 3850 60 0000 C CNN +F 3 "" H 5200 3850 60 0000 C CNN + 1 5200 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C8F9D2E +P 5200 3600 +F 0 "U1" H 5250 3700 30 0000 C CNN +F 1 "PORT" H 5200 3600 30 0000 C CNN +F 2 "" H 5200 3600 60 0000 C CNN +F 3 "" H 5200 3600 60 0000 C CNN + 5 5200 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C8FA0FA +P 8250 4100 +F 0 "U1" H 8300 4200 30 0000 C CNN +F 1 "PORT" H 8250 4100 30 0000 C CNN +F 2 "" H 8250 4100 60 0000 C CNN +F 3 "" H 8250 4100 60 0000 C CNN + 12 8250 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C8FA100 +P 8250 3850 +F 0 "U1" H 8300 3950 30 0000 C CNN +F 1 "PORT" H 8250 3850 30 0000 C CNN +F 2 "" H 8250 3850 60 0000 C CNN +F 3 "" H 8250 3850 60 0000 C CNN + 13 8250 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C8FA106 +P 8250 3600 +F 0 "U1" H 8300 3700 30 0000 C CNN +F 1 "PORT" H 8250 3600 30 0000 C CNN +F 2 "" H 8250 3600 60 0000 C CNN +F 3 "" H 8250 3600 60 0000 C CNN + 9 8250 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C8FA319 +P 4950 5050 +F 0 "U1" H 5000 5150 30 0000 C CNN +F 1 "PORT" H 4950 5050 30 0000 C CNN +F 2 "" H 4950 5050 60 0000 C CNN +F 3 "" H 4950 5050 60 0000 C CNN + 7 4950 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 5050 5200 4650 +Connection ~ 5200 4650 +Wire Wire Line + 3300 3600 3600 3600 +Wire Wire Line + 3300 3850 3600 3850 +Wire Wire Line + 3300 4100 3600 4100 +Wire Wire Line + 4700 3600 4950 3600 +Wire Wire Line + 4700 3850 4950 3850 +Wire Wire Line + 4700 4100 4950 4100 +Wire Wire Line + 6250 3600 6550 3600 +Wire Wire Line + 6250 3850 6550 3850 +Wire Wire Line + 6250 4100 6550 4100 +Wire Wire Line + 8000 3600 7650 3600 +Wire Wire Line + 8000 3850 7650 3850 +Wire Wire Line + 8000 4100 7650 4100 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/556/556.sub b/src/SubcircuitLibrary/556/556.sub new file mode 100644 index 00000000..a370b703 --- /dev/null +++ b/src/SubcircuitLibrary/556/556.sub @@ -0,0 +1,9 @@ +* Subcircuit 556 +.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* Control Statements + +.ends 556
\ No newline at end of file diff --git a/src/SubcircuitLibrary/556/556_Previous_Values.xml b/src/SubcircuitLibrary/556/556_Previous_Values.xml new file mode 100644 index 00000000..c025c2d1 --- /dev/null +++ b/src/SubcircuitLibrary/556/556_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_and/3_and.bak b/src/SubcircuitLibrary/5_and/3_and.bak new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_and/5_and.bak b/src/SubcircuitLibrary/5_and/5_and.bak new file mode 100644 index 00000000..da927b09 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.bak @@ -0,0 +1,158 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro new file mode 100644 index 00000000..7a2f090e --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.pro @@ -0,0 +1,50 @@ +update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch new file mode 100644 index 00000000..e9eb58ee --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/analysis b/src/SubcircuitLibrary/5_and/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/5_and/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and-cache.lib b/src/SubcircuitLibrary/74153/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/3_and.bak b/src/SubcircuitLibrary/74153/3_and.bak new file mode 100644 index 00000000..82d9bc0b --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/3_and.cir b/src/SubcircuitLibrary/74153/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/3_and.cir.out b/src/SubcircuitLibrary/74153/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/3_and.pro b/src/SubcircuitLibrary/74153/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74153/3_and.sch b/src/SubcircuitLibrary/74153/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/3_and.sub b/src/SubcircuitLibrary/74153/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR-cache.lib b/src/SubcircuitLibrary/74153/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_OR.cir b/src/SubcircuitLibrary/74153/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/4_OR.cir.out b/src/SubcircuitLibrary/74153/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/4_OR.pro b/src/SubcircuitLibrary/74153/4_OR.pro new file mode 100644 index 00000000..2c258cec --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.pro @@ -0,0 +1,45 @@ +update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_OR.sch b/src/SubcircuitLibrary/74153/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml new file mode 100644 index 00000000..23698d37 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and-cache.lib b/src/SubcircuitLibrary/74153/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_and.cir b/src/SubcircuitLibrary/74153/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/4_and.cir.out b/src/SubcircuitLibrary/74153/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/4_and.pro b/src/SubcircuitLibrary/74153/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_and.sch b/src/SubcircuitLibrary/74153/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_and.sub b/src/SubcircuitLibrary/74153/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153-cache.lib b/src/SubcircuitLibrary/74153/74153-cache.lib new file mode 100644 index 00000000..1e85854e --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153-cache.lib @@ -0,0 +1,98 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/74153.bak b/src/SubcircuitLibrary/74153/74153.bak new file mode 100644 index 00000000..494df35a --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.bak @@ -0,0 +1,840 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U14 +U 1 1 5C936BFE +P 3850 2450 +F 0 "U14" H 3850 2450 60 0000 C CNN +F 1 "d_and" H 3900 2550 60 0000 C CNN +F 2 "" H 3850 2450 60 0000 C CNN +F 3 "" H 3850 2450 60 0000 C CNN + 1 3850 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 5C936C8A +P 4850 2600 +F 0 "U25" H 4850 2600 60 0000 C CNN +F 1 "d_and" H 4900 2700 60 0000 C CNN +F 2 "" H 4850 2600 60 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4850 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C936E84 +P 3800 3050 +F 0 "U5" H 3800 3050 60 0000 C CNN +F 1 "d_and" H 3850 3150 60 0000 C CNN +F 2 "" H 3800 3050 60 0000 C CNN +F 3 "" H 3800 3050 60 0000 C CNN + 1 3800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5C936E8A +P 4800 3200 +F 0 "U20" H 4800 3200 60 0000 C CNN +F 1 "d_and" H 4850 3300 60 0000 C CNN +F 2 "" H 4800 3200 60 0000 C CNN +F 3 "" H 4800 3200 60 0000 C CNN + 1 4800 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C936EF6 +P 3800 3550 +F 0 "U7" H 3800 3550 60 0000 C CNN +F 1 "d_and" H 3850 3650 60 0000 C CNN +F 2 "" H 3800 3550 60 0000 C CNN +F 3 "" H 3800 3550 60 0000 C CNN + 1 3800 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5C936EFC +P 4800 3700 +F 0 "U21" H 4800 3700 60 0000 C CNN +F 1 "d_and" H 4850 3800 60 0000 C CNN +F 2 "" H 4800 3700 60 0000 C CNN +F 3 "" H 4800 3700 60 0000 C CNN + 1 4800 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C936F88 +P 3950 1900 +F 0 "U18" H 3950 1900 60 0000 C CNN +F 1 "d_and" H 4000 2000 60 0000 C CNN +F 2 "" H 3950 1900 60 0000 C CNN +F 3 "" H 3950 1900 60 0000 C CNN + 1 3950 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 5C936F8E +P 4850 2150 +F 0 "U24" H 4850 2150 60 0000 C CNN +F 1 "d_and" H 4900 2250 60 0000 C CNN +F 2 "" H 4850 2150 60 0000 C CNN +F 3 "" H 4850 2150 60 0000 C CNN + 1 4850 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 5C937316 +P 5900 2550 +F 0 "U28" H 5900 2550 60 0000 C CNN +F 1 "d_or" H 5900 2650 60 0000 C CNN +F 2 "" H 5900 2550 60 0000 C CNN +F 3 "" H 5900 2550 60 0000 C CNN + 1 5900 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_or U29 +U 1 1 5C9373A8 +P 5900 2800 +F 0 "U29" H 5900 2800 60 0000 C CNN +F 1 "d_or" H 5900 2900 60 0000 C CNN +F 2 "" H 5900 2800 60 0000 C CNN +F 3 "" H 5900 2800 60 0000 C CNN + 1 5900 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 5C9373FC +P 6850 2650 +F 0 "U32" H 6850 2650 60 0000 C CNN +F 1 "d_or" H 6850 2750 60 0000 C CNN +F 2 "" H 6850 2650 60 0000 C CNN +F 3 "" H 6850 2650 60 0000 C CNN + 1 6850 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 1850 4400 2050 +Wire Wire Line + 4400 2500 4400 2400 +Wire Wire Line + 4400 2400 4300 2400 +Wire Wire Line + 4350 3100 4350 3000 +Wire Wire Line + 4350 3000 4250 3000 +Wire Wire Line + 4350 3600 4350 3500 +Wire Wire Line + 4350 3500 4250 3500 +Wire Wire Line + 6400 2550 6400 2500 +Wire Wire Line + 6400 2500 6350 2500 +Wire Wire Line + 6400 2650 6400 2750 +Wire Wire Line + 6400 2750 6350 2750 +Wire Wire Line + 5450 2450 5350 2450 +Wire Wire Line + 5350 2450 5350 2100 +Wire Wire Line + 5350 2100 5300 2100 +Wire Wire Line + 5300 2550 5450 2550 +Wire Wire Line + 5450 2700 5300 2700 +Wire Wire Line + 5300 2700 5300 3150 +Wire Wire Line + 5300 3150 5250 3150 +Wire Wire Line + 5250 3650 5400 3650 +Wire Wire Line + 5400 3650 5400 2800 +Wire Wire Line + 5400 2800 5450 2800 +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 1800 3100 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3500 1900 3200 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +$Comp +L d_and U15 +U 1 1 5C937C96 +P 3850 2700 +F 0 "U15" H 3850 2700 60 0000 C CNN +F 1 "d_and" H 3900 2800 60 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 1 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 5C937CEE +P 3800 3300 +F 0 "U6" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C937D35 +P 3800 3800 +F 0 "U8" H 3800 3800 60 0000 C CNN +F 1 "d_and" H 3850 3900 60 0000 C CNN +F 2 "" H 3800 3800 60 0000 C CNN +F 3 "" H 3800 3800 60 0000 C CNN + 1 3800 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C937DC5 +P 3800 2150 +F 0 "U4" H 3800 2150 60 0000 C CNN +F 1 "d_and" H 3850 2250 60 0000 C CNN +F 2 "" H 3800 2150 60 0000 C CNN +F 3 "" H 3800 2150 60 0000 C CNN + 1 3800 2150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 2150 3300 2150 +Wire Wire Line + 3300 2150 3300 3800 +Wire Wire Line + 3300 2700 3400 2700 +Wire Wire Line + 3300 3300 3350 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3350 3800 +Connection ~ 3300 3300 +Wire Wire Line + 4350 3200 4350 3250 +Wire Wire Line + 4350 3250 4250 3250 +Wire Wire Line + 4400 2600 4400 2650 +Wire Wire Line + 4400 2650 4300 2650 +Wire Wire Line + 4400 2150 4300 2150 +Wire Wire Line + 4300 2150 4300 2100 +Wire Wire Line + 4300 2100 4250 2100 +Wire Wire Line + 4350 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3750 +Wire Wire Line + 3350 3700 1600 3700 +Wire Wire Line + 3350 3200 1600 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 3350 2050 1600 2050 +Wire Wire Line + 3000 3800 3000 3950 +Wire Wire Line + 1600 3950 2400 3950 +Connection ~ 3300 3800 +$Comp +L d_and U16 +U 1 1 5C9388D0 +P 3850 5100 +F 0 "U16" H 3850 5100 60 0000 C CNN +F 1 "d_and" H 3900 5200 60 0000 C CNN +F 2 "" H 3850 5100 60 0000 C CNN +F 3 "" H 3850 5100 60 0000 C CNN + 1 3850 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 5C9388D6 +P 4850 5250 +F 0 "U27" H 4850 5250 60 0000 C CNN +F 1 "d_and" H 4900 5350 60 0000 C CNN +F 2 "" H 4850 5250 60 0000 C CNN +F 3 "" H 4850 5250 60 0000 C CNN + 1 4850 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9388DC +P 3800 5700 +F 0 "U10" H 3800 5700 60 0000 C CNN +F 1 "d_and" H 3850 5800 60 0000 C CNN +F 2 "" H 3800 5700 60 0000 C CNN +F 3 "" H 3800 5700 60 0000 C CNN + 1 3800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 5C9388E2 +P 4800 5850 +F 0 "U22" H 4800 5850 60 0000 C CNN +F 1 "d_and" H 4850 5950 60 0000 C CNN +F 2 "" H 4800 5850 60 0000 C CNN +F 3 "" H 4800 5850 60 0000 C CNN + 1 4800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 5C9388E8 +P 3800 6200 +F 0 "U12" H 3800 6200 60 0000 C CNN +F 1 "d_and" H 3850 6300 60 0000 C CNN +F 2 "" H 3800 6200 60 0000 C CNN +F 3 "" H 3800 6200 60 0000 C CNN + 1 3800 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 5C9388EE +P 4800 6350 +F 0 "U23" H 4800 6350 60 0000 C CNN +F 1 "d_and" H 4850 6450 60 0000 C CNN +F 2 "" H 4800 6350 60 0000 C CNN +F 3 "" H 4800 6350 60 0000 C CNN + 1 4800 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9388F4 +P 3950 4550 +F 0 "U19" H 3950 4550 60 0000 C CNN +F 1 "d_and" H 4000 4650 60 0000 C CNN +F 2 "" H 3950 4550 60 0000 C CNN +F 3 "" H 3950 4550 60 0000 C CNN + 1 3950 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 5C9388FA +P 4850 4800 +F 0 "U26" H 4850 4800 60 0000 C CNN +F 1 "d_and" H 4900 4900 60 0000 C CNN +F 2 "" H 4850 4800 60 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4850 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U30 +U 1 1 5C938900 +P 5900 5200 +F 0 "U30" H 5900 5200 60 0000 C CNN +F 1 "d_or" H 5900 5300 60 0000 C CNN +F 2 "" H 5900 5200 60 0000 C CNN +F 3 "" H 5900 5200 60 0000 C CNN + 1 5900 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U31 +U 1 1 5C938906 +P 5900 5450 +F 0 "U31" H 5900 5450 60 0000 C CNN +F 1 "d_or" H 5900 5550 60 0000 C CNN +F 2 "" H 5900 5450 60 0000 C CNN +F 3 "" H 5900 5450 60 0000 C CNN + 1 5900 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 5C93890C +P 6850 5300 +F 0 "U33" H 6850 5300 60 0000 C CNN +F 1 "d_or" H 6850 5400 60 0000 C CNN +F 2 "" H 6850 5300 60 0000 C CNN +F 3 "" H 6850 5300 60 0000 C CNN + 1 6850 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4500 4400 4700 +Wire Wire Line + 4400 5150 4400 5050 +Wire Wire Line + 4400 5050 4300 5050 +Wire Wire Line + 4350 5750 4350 5650 +Wire Wire Line + 4350 5650 4250 5650 +Wire Wire Line + 4350 6250 4350 6150 +Wire Wire Line + 4350 6150 4250 6150 +Wire Wire Line + 6400 5200 6400 5150 +Wire Wire Line + 6400 5150 6350 5150 +Wire Wire Line + 6400 5300 6400 5400 +Wire Wire Line + 6400 5400 6350 5400 +Wire Wire Line + 5450 5100 5350 5100 +Wire Wire Line + 5350 5100 5350 4750 +Wire Wire Line + 5350 4750 5300 4750 +Wire Wire Line + 5300 5200 5450 5200 +Wire Wire Line + 5450 5350 5300 5350 +Wire Wire Line + 5300 5350 5300 5800 +Wire Wire Line + 5300 5800 5250 5800 +Wire Wire Line + 5250 6300 5400 6300 +Wire Wire Line + 5400 6300 5400 5450 +Wire Wire Line + 5400 5450 5450 5450 +Wire Wire Line + 3100 4450 3500 4450 +Wire Wire Line + 3200 4550 3500 4550 +$Comp +L d_and U17 +U 1 1 5C938937 +P 3850 5350 +F 0 "U17" H 3850 5350 60 0000 C CNN +F 1 "d_and" H 3900 5450 60 0000 C CNN +F 2 "" H 3850 5350 60 0000 C CNN +F 3 "" H 3850 5350 60 0000 C CNN + 1 3850 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 5C93893D +P 3800 5950 +F 0 "U11" H 3800 5950 60 0000 C CNN +F 1 "d_and" H 3850 6050 60 0000 C CNN +F 2 "" H 3800 5950 60 0000 C CNN +F 3 "" H 3800 5950 60 0000 C CNN + 1 3800 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5C938943 +P 3800 6450 +F 0 "U13" H 3800 6450 60 0000 C CNN +F 1 "d_and" H 3850 6550 60 0000 C CNN +F 2 "" H 3800 6450 60 0000 C CNN +F 3 "" H 3800 6450 60 0000 C CNN + 1 3800 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C938949 +P 3800 4800 +F 0 "U9" H 3800 4800 60 0000 C CNN +F 1 "d_and" H 3850 4900 60 0000 C CNN +F 2 "" H 3800 4800 60 0000 C CNN +F 3 "" H 3800 4800 60 0000 C CNN + 1 3800 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 4800 3300 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3400 5350 +Wire Wire Line + 3300 5950 3350 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3350 6450 +Connection ~ 3300 5950 +Wire Wire Line + 4350 5850 4350 5900 +Wire Wire Line + 4350 5900 4250 5900 +Wire Wire Line + 4400 5250 4400 5300 +Wire Wire Line + 4400 5300 4300 5300 +Wire Wire Line + 4400 4800 4300 4800 +Wire Wire Line + 4300 4800 4300 4750 +Wire Wire Line + 4300 4750 4250 4750 +Wire Wire Line + 4350 6350 4250 6350 +Wire Wire Line + 4250 6350 4250 6400 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 3350 5850 1600 5850 +Wire Wire Line + 3400 5250 1600 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 2950 6600 3200 6600 +Wire Wire Line + 1600 6600 2350 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U35 +U 1 1 5C95CBCC +P 2700 3950 +F 0 "U35" H 2700 3850 60 0000 C CNN +F 1 "d_inverter" H 2700 4100 60 0000 C CNN +F 2 "" H 2750 3900 60 0000 C CNN +F 3 "" H 2750 3900 60 0000 C CNN + 1 2700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 5C95CC99 +P 2650 6600 +F 0 "U34" H 2650 6500 60 0000 C CNN +F 1 "d_inverter" H 2650 6750 60 0000 C CNN +F 2 "" H 2700 6550 60 0000 C CNN +F 3 "" H 2700 6550 60 0000 C CNN + 1 2650 6600 + 1 0 0 -1 +$EndComp +Text Notes 1750 2050 0 60 ~ 12 +A0 +Text Notes 1800 2600 0 60 ~ 12 +A1 +Text Notes 1800 3200 0 60 ~ 12 +A2 +Text Notes 1750 3700 0 60 ~ 12 +A3\n +Text Notes 1750 3950 0 60 ~ 12 +EnA\n +Text Notes 1800 4700 0 60 ~ 12 +B0\n +Text Notes 1800 5250 0 60 ~ 12 +B1 +Text Notes 1800 5850 0 60 ~ 12 +B2 +Text Notes 1750 6350 0 60 ~ 12 +B3 +Text Notes 1800 6600 0 60 ~ 12 +EnB +Text Notes 2000 950 0 60 ~ 12 +S1\n +Text Notes 2000 1350 0 60 ~ 12 +S0 +Text Notes 7350 2600 0 60 ~ 12 +YA +Text Notes 7400 5250 0 60 ~ 12 +YB +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/74153.cir b/src/SubcircuitLibrary/74153/74153.cir new file mode 100644 index 00000000..b20e6858 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U35 Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter +U34 Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter +X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and +X9 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and +X4 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and +X10 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and +X6 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and +X7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR +X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR + +.end diff --git a/src/SubcircuitLibrary/74153/74153.cir.out b/src/SubcircuitLibrary/74153/74153.cir.out new file mode 100644 index 00000000..c95e5ad9 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.cir.out @@ -0,0 +1,40 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/74153.pro b/src/SubcircuitLibrary/74153/74153.pro new file mode 100644 index 00000000..ed8b8bf2 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.pro @@ -0,0 +1,59 @@ +update=03/28/19 23:27:36 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=texas +LibName4=intel +LibName5=audio +LibName6=interface +LibName7=digital-audio +LibName8=philips +LibName9=display +LibName10=cypress +LibName11=siliconi +LibName12=opto +LibName13=atmel +LibName14=contrib +LibName15=valves +LibName16=eSim_Analog +LibName17=eSim_Devices +LibName18=eSim_Digital +LibName19=eSim_Hybrid +LibName20=eSim_Miscellaneous +LibName21=eSim_Plot +LibName22=eSim_Power +LibName23=eSim_PSpice +LibName24=eSim_Sources +LibName25=eSim_User +LibName26=eSim_Subckt diff --git a/src/SubcircuitLibrary/74153/74153.sch b/src/SubcircuitLibrary/74153/74153.sch new file mode 100644 index 00000000..e0bcf950 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.sch @@ -0,0 +1,568 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices 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60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 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+F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 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60 0000 C CNN +F 3 "" H 2150 8400 60 0000 C CNN + 1 2150 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 5100 5550 4600 +Wire Wire Line + 5550 4600 4650 4600 +Wire Wire Line + 5550 5200 4650 5200 +Wire Wire Line + 4650 5200 4650 5150 +Wire Wire Line + 4600 5750 4600 5300 +Wire Wire Line + 4600 5300 5550 5300 +Wire Wire Line + 4650 6250 4650 5400 +Wire Wire Line + 4650 5400 5550 5400 +$Comp +L 4_OR X2 +U 1 1 5C9D28DE +P 2250 5750 +F 0 "X2" H 6150 8800 60 0000 C CNN +F 1 "4_OR" H 6150 9000 60 0000 C CNN +F 2 "" H 2250 5750 60 0000 C CNN +F 3 "" H 2250 5750 60 0000 C CNN + 1 2250 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1950 5650 1950 +Wire Wire Line + 5650 1950 5650 2450 +Wire Wire Line + 5650 2550 4700 2550 +Wire Wire Line + 4700 2550 4700 2500 +Wire Wire Line + 4650 3100 4650 2650 +Wire Wire Line + 4650 2650 5650 2650 +Wire Wire Line + 4700 3600 4700 2750 +Wire Wire Line + 4700 2750 5650 2750 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/74153.sub b/src/SubcircuitLibrary/74153/74153.sub new file mode 100644 index 00000000..6e00261f --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153.sub @@ -0,0 +1,34 @@ +* Subcircuit 74153 +.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74153
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml new file mode 100644 index 00000000..ea70e6f3 --- /dev/null +++ b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib new file mode 100644 index 00000000..10496d63 --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.bak b/src/SubcircuitLibrary/74153/Dual4to1MUX.bak new file mode 100644 index 00000000..9f57486b --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.bak @@ -0,0 +1,788 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U14 +U 1 1 5C936BFE +P 3850 2450 +F 0 "U14" H 3850 2450 60 0000 C CNN +F 1 "d_and" H 3900 2550 60 0000 C CNN +F 2 "" H 3850 2450 60 0000 C CNN +F 3 "" H 3850 2450 60 0000 C CNN + 1 3850 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 5C936C8A +P 4850 2600 +F 0 "U25" H 4850 2600 60 0000 C CNN +F 1 "d_and" H 4900 2700 60 0000 C CNN +F 2 "" H 4850 2600 60 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4850 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C936E84 +P 3800 3050 +F 0 "U5" H 3800 3050 60 0000 C CNN +F 1 "d_and" H 3850 3150 60 0000 C CNN +F 2 "" H 3800 3050 60 0000 C CNN +F 3 "" H 3800 3050 60 0000 C CNN + 1 3800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5C936E8A +P 4800 3200 +F 0 "U20" H 4800 3200 60 0000 C CNN +F 1 "d_and" H 4850 3300 60 0000 C CNN +F 2 "" H 4800 3200 60 0000 C CNN +F 3 "" H 4800 3200 60 0000 C CNN + 1 4800 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C936EF6 +P 3800 3550 +F 0 "U7" H 3800 3550 60 0000 C CNN +F 1 "d_and" H 3850 3650 60 0000 C CNN +F 2 "" H 3800 3550 60 0000 C CNN +F 3 "" H 3800 3550 60 0000 C CNN + 1 3800 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5C936EFC +P 4800 3700 +F 0 "U21" H 4800 3700 60 0000 C CNN +F 1 "d_and" H 4850 3800 60 0000 C CNN +F 2 "" H 4800 3700 60 0000 C CNN +F 3 "" H 4800 3700 60 0000 C CNN + 1 4800 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C936F88 +P 3950 1900 +F 0 "U18" H 3950 1900 60 0000 C CNN +F 1 "d_and" H 4000 2000 60 0000 C CNN +F 2 "" H 3950 1900 60 0000 C CNN +F 3 "" H 3950 1900 60 0000 C CNN + 1 3950 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 5C936F8E +P 4850 2150 +F 0 "U24" H 4850 2150 60 0000 C CNN +F 1 "d_and" H 4900 2250 60 0000 C CNN +F 2 "" H 4850 2150 60 0000 C CNN +F 3 "" H 4850 2150 60 0000 C CNN + 1 4850 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 5C937316 +P 5900 2550 +F 0 "U28" H 5900 2550 60 0000 C CNN +F 1 "d_or" H 5900 2650 60 0000 C CNN +F 2 "" H 5900 2550 60 0000 C CNN +F 3 "" H 5900 2550 60 0000 C CNN + 1 5900 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_or U29 +U 1 1 5C9373A8 +P 5900 2800 +F 0 "U29" H 5900 2800 60 0000 C CNN +F 1 "d_or" H 5900 2900 60 0000 C CNN +F 2 "" H 5900 2800 60 0000 C CNN +F 3 "" H 5900 2800 60 0000 C CNN + 1 5900 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 5C9373FC +P 6850 2650 +F 0 "U32" H 6850 2650 60 0000 C CNN +F 1 "d_or" H 6850 2750 60 0000 C CNN +F 2 "" H 6850 2650 60 0000 C CNN +F 3 "" H 6850 2650 60 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0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 1800 3100 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3500 1900 3200 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +$Comp +L d_and U15 +U 1 1 5C937C96 +P 3850 2700 +F 0 "U15" H 3850 2700 60 0000 C CNN +F 1 "d_and" H 3900 2800 60 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 1 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 5C937CEE +P 3800 3300 +F 0 "U6" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C937D35 +P 3800 3800 +F 0 "U8" H 3800 3800 60 0000 C CNN +F 1 "d_and" H 3850 3900 60 0000 C CNN +F 2 "" H 3800 3800 60 0000 C CNN +F 3 "" H 3800 3800 60 0000 C CNN + 1 3800 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C937DC5 +P 3800 2150 +F 0 "U4" H 3800 2150 60 0000 C CNN +F 1 "d_and" H 3850 2250 60 0000 C CNN +F 2 "" H 3800 2150 60 0000 C CNN +F 3 "" H 3800 2150 60 0000 C CNN + 1 3800 2150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 2150 3300 2150 +Wire Wire Line + 3300 2150 3300 3800 +Wire Wire Line + 3300 2700 3400 2700 +Wire Wire Line + 3300 3300 3350 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3350 3800 +Connection ~ 3300 3300 +Wire Wire Line + 4350 3200 4350 3250 +Wire Wire Line + 4350 3250 4250 3250 +Wire Wire Line + 4400 2600 4400 2650 +Wire Wire Line + 4400 2650 4300 2650 +Wire Wire Line + 4400 2150 4300 2150 +Wire Wire Line + 4300 2150 4300 2100 +Wire Wire Line + 4300 2100 4250 2100 +Wire Wire Line + 4350 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3750 +Wire Wire Line + 3350 3700 1600 3700 +Wire Wire Line + 3350 3200 1600 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 3350 2050 1600 2050 +Wire Wire Line + 3000 3800 3000 3950 +Wire Wire Line + 3000 3950 1600 3950 +Connection ~ 3300 3800 +$Comp +L d_and U16 +U 1 1 5C9388D0 +P 3850 5100 +F 0 "U16" H 3850 5100 60 0000 C CNN +F 1 "d_and" H 3900 5200 60 0000 C CNN +F 2 "" H 3850 5100 60 0000 C CNN +F 3 "" H 3850 5100 60 0000 C CNN + 1 3850 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 5C9388D6 +P 4850 5250 +F 0 "U27" H 4850 5250 60 0000 C CNN +F 1 "d_and" H 4900 5350 60 0000 C CNN +F 2 "" H 4850 5250 60 0000 C CNN +F 3 "" H 4850 5250 60 0000 C CNN + 1 4850 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9388DC +P 3800 5700 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3950 4550 60 0000 C CNN +F 3 "" H 3950 4550 60 0000 C CNN + 1 3950 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 5C9388FA +P 4850 4800 +F 0 "U26" H 4850 4800 60 0000 C CNN +F 1 "d_and" H 4900 4900 60 0000 C CNN +F 2 "" H 4850 4800 60 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4850 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U30 +U 1 1 5C938900 +P 5900 5200 +F 0 "U30" H 5900 5200 60 0000 C CNN +F 1 "d_or" H 5900 5300 60 0000 C CNN +F 2 "" H 5900 5200 60 0000 C CNN +F 3 "" H 5900 5200 60 0000 C CNN + 1 5900 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U31 +U 1 1 5C938906 +P 5900 5450 +F 0 "U31" H 5900 5450 60 0000 C CNN +F 1 "d_or" H 5900 5550 60 0000 C CNN +F 2 "" H 5900 5450 60 0000 C CNN +F 3 "" H 5900 5450 60 0000 C CNN + 1 5900 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 5C93890C +P 6850 5300 +F 0 "U33" H 6850 5300 60 0000 C CNN +F 1 "d_or" H 6850 5400 60 0000 C CNN +F 2 "" H 6850 5300 60 0000 C CNN +F 3 "" H 6850 5300 60 0000 C CNN + 1 6850 5300 + 1 0 0 -1 +$EndComp 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5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir new file mode 100644 index 00000000..583c4a00 --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir @@ -0,0 +1,45 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and +U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and +U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or +U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or +U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or +U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and +U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and +U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and +U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and +U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and +U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and +U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or +U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and +U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter +U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter + +.end diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch new file mode 100644 index 00000000..340b1a31 --- /dev/null +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch @@ -0,0 +1,814 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache 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+$EndComp +$Comp +L d_and U13 +U 1 1 5C938943 +P 3800 6450 +F 0 "U13" H 3800 6450 60 0000 C CNN +F 1 "d_and" H 3850 6550 60 0000 C CNN +F 2 "" H 3800 6450 60 0000 C CNN +F 3 "" H 3800 6450 60 0000 C CNN + 1 3800 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C938949 +P 3800 4800 +F 0 "U9" H 3800 4800 60 0000 C CNN +F 1 "d_and" H 3850 4900 60 0000 C CNN +F 2 "" H 3800 4800 60 0000 C CNN +F 3 "" H 3800 4800 60 0000 C CNN + 1 3800 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 4800 3300 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3400 5350 +Wire Wire Line + 3300 5950 3350 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3350 6450 +Connection ~ 3300 5950 +Wire Wire Line + 4350 5850 4350 5900 +Wire Wire Line + 4350 5900 4250 5900 +Wire Wire Line + 4400 5250 4400 5300 +Wire Wire Line + 4400 5300 4300 5300 +Wire Wire Line + 4400 4800 4300 4800 +Wire Wire Line + 4300 4800 4300 4750 +Wire Wire Line + 4300 4750 4250 4750 +Wire Wire Line + 4350 6350 4250 6350 +Wire Wire Line + 4250 6350 4250 6400 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 3350 5850 1600 5850 +Wire Wire Line + 3400 5250 1600 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 3000 6600 3200 6600 +Wire Wire Line + 1600 6600 2400 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U34 +U 1 1 5C95C9D0 +P 2650 3950 +F 0 "U34" H 2650 3850 60 0000 C CNN +F 1 "d_inverter" H 2650 4100 60 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 1 2650 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CD17 +P 2700 6600 +F 0 "U35" H 2700 6500 60 0000 C CNN +F 1 "d_inverter" H 2700 6750 60 0000 C CNN +F 2 "" H 2750 6550 60 0000 C CNN +F 3 "" H 2750 6550 60 0000 C CNN + 1 2700 6600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/analysis b/src/SubcircuitLibrary/74153/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/74153/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74157/3_and.bak b/src/SubcircuitLibrary/74157/3_and.bak new file mode 100644 index 00000000..82d9bc0b --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib new file mode 100644 index 00000000..de171255 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74157/74157.bak b/src/SubcircuitLibrary/74157/74157.bak new file mode 100644 index 00000000..71edac4c --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.bak @@ -0,0 +1,667 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U4 +U 1 1 5C95D4F6 +P 3950 2000 +F 0 "U4" H 3950 2000 60 0000 C CNN +F 1 "d_and" H 4000 2100 60 0000 C CNN +F 2 "" H 3950 2000 60 0000 C CNN +F 3 "" H 3950 2000 60 0000 C CNN + 1 3950 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 5C95D522 +P 4950 2200 +F 0 "U12" H 4950 2200 60 0000 C CNN +F 1 "d_and" H 5000 2300 60 0000 C CNN +F 2 "" H 4950 2200 60 0000 C CNN +F 3 "" H 4950 2200 60 0000 C CNN + 1 4950 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C95D596 +P 3950 2500 +F 0 "U5" H 3950 2500 60 0000 C CNN +F 1 "d_and" H 4000 2600 60 0000 C CNN +F 2 "" H 3950 2500 60 0000 C CNN +F 3 "" H 3950 2500 60 0000 C CNN + 1 3950 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5C95D59C +P 4950 2700 +F 0 "U13" H 4950 2700 60 0000 C CNN +F 1 "d_and" H 5000 2800 60 0000 C CNN +F 2 "" H 4950 2700 60 0000 C CNN +F 3 "" H 4950 2700 60 0000 C CNN + 1 4950 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C95D60E +P 4000 2950 +F 0 "U8" H 4000 2950 60 0000 C CNN +F 1 "d_and" H 4050 3050 60 0000 C CNN +F 2 "" H 4000 2950 60 0000 C CNN +F 3 "" H 4000 2950 60 0000 C CNN + 1 4000 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 5C95D614 +P 5000 3150 +F 0 "U16" H 5000 3150 60 0000 C CNN +F 1 "d_and" H 5050 3250 60 0000 C CNN +F 2 "" H 5000 3150 60 0000 C CNN +F 3 "" H 5000 3150 60 0000 C CNN + 1 5000 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C95D61A +P 4000 3450 +F 0 "U9" H 4000 3450 60 0000 C CNN +F 1 "d_and" H 4050 3550 60 0000 C CNN +F 2 "" H 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+F 1 "d_and" H 4050 5300 60 0000 C CNN +F 2 "" H 4000 5200 60 0000 C CNN +F 3 "" H 4000 5200 60 0000 C CNN + 1 4000 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C95D8D6 +P 5000 5400 +F 0 "U18" H 5000 5400 60 0000 C CNN +F 1 "d_and" H 5050 5500 60 0000 C CNN +F 2 "" H 5000 5400 60 0000 C CNN +F 3 "" H 5000 5400 60 0000 C CNN + 1 5000 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 5C95D8DC +P 4000 5700 +F 0 "U11" H 4000 5700 60 0000 C CNN +F 1 "d_and" H 4050 5800 60 0000 C CNN +F 2 "" H 4000 5700 60 0000 C CNN +F 3 "" H 4000 5700 60 0000 C CNN + 1 4000 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C95D8E2 +P 5000 5900 +F 0 "U19" H 5000 5900 60 0000 C CNN +F 1 "d_and" H 5050 6000 60 0000 C CNN +F 2 "" H 5000 5900 60 0000 C CNN +F 3 "" H 5000 5900 60 0000 C CNN + 1 5000 5900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 4350 4500 4200 +Wire Wire Line + 4500 4200 4400 4200 +Wire Wire Line + 4500 4850 4500 4700 +Wire Wire Line + 4500 4700 4400 4700 +Wire Wire Line + 4550 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C CNN +F 3 "" H 7350 3800 60 0000 C CNN + 1 7350 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 5C95E16E +P 7350 4250 +F 0 "U22" H 7350 4250 60 0000 C CNN +F 1 "d_or" H 7350 4350 60 0000 C CNN +F 2 "" H 7350 4250 60 0000 C CNN +F 3 "" H 7350 4250 60 0000 C CNN + 1 7350 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U23 +U 1 1 5C95E1C9 +P 7350 4750 +F 0 "U23" H 7350 4750 60 0000 C CNN +F 1 "d_or" H 7350 4850 60 0000 C CNN +F 2 "" H 7350 4750 60 0000 C CNN +F 3 "" H 7350 4750 60 0000 C CNN + 1 7350 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3200 6650 3200 +Wire Wire Line + 6650 3200 6650 2150 +Wire Wire Line + 6650 2150 5400 2150 +Wire Wire Line + 6900 3700 6550 3700 +Wire Wire Line + 6550 3700 6550 2650 +Wire Wire Line + 6550 2650 5400 2650 +Wire Wire Line + 6900 4150 6450 4150 +Wire Wire Line + 6450 4150 6450 3100 +Wire Wire Line + 6450 3100 5450 3100 +Wire Wire Line + 6900 4650 6350 4650 +Wire Wire Line + 6350 4650 6350 3600 +Wire Wire Line + 6350 3600 5450 3600 +Wire Wire Line + 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0000 C CNN +F 2 "" H 1400 1850 60 0000 C CNN +F 3 "" H 1400 1850 60 0000 C CNN + 1 1400 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C95E9CF +P 1400 2150 +F 0 "U1" H 1450 2250 30 0000 C CNN +F 1 "PORT" H 1400 2150 30 0000 C CNN +F 2 "" H 1400 2150 60 0000 C CNN +F 3 "" H 1400 2150 60 0000 C CNN + 2 1400 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C95EA28 +P 1400 2700 +F 0 "U1" H 1450 2800 30 0000 C CNN +F 1 "PORT" H 1400 2700 30 0000 C CNN +F 2 "" H 1400 2700 60 0000 C CNN +F 3 "" H 1400 2700 60 0000 C CNN + 3 1400 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95EA9C +P 1400 2900 +F 0 "U1" H 1450 3000 30 0000 C CNN +F 1 "PORT" H 1400 2900 30 0000 C CNN +F 2 "" H 1400 2900 60 0000 C CNN +F 3 "" H 1400 2900 60 0000 C CNN + 4 1400 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95EAFD +P 1400 3350 +F 0 "U1" H 1450 3450 30 0000 C CNN +F 1 "PORT" H 1400 3350 30 0000 C CNN +F 2 "" H 1400 3350 60 0000 C CNN +F 3 "" H 1400 3350 60 0000 C CNN + 5 1400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C95EB63 +P 1400 3600 +F 0 "U1" H 1450 3700 30 0000 C CNN +F 1 "PORT" H 1400 3600 30 0000 C CNN +F 2 "" H 1400 3600 60 0000 C CNN +F 3 "" H 1400 3600 60 0000 C CNN + 6 1400 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C95EBC8 +P 1400 4050 +F 0 "U1" H 1450 4150 30 0000 C CNN +F 1 "PORT" H 1400 4050 30 0000 C CNN +F 2 "" H 1400 4050 60 0000 C CNN +F 3 "" H 1400 4050 60 0000 C CNN + 7 1400 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C95EC38 +P 1400 4300 +F 0 "U1" H 1450 4400 30 0000 C CNN +F 1 "PORT" H 1400 4300 30 0000 C CNN +F 2 "" H 1400 4300 60 0000 C CNN +F 3 "" H 1400 4300 60 0000 C CNN + 8 1400 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C95ECA1 +P 1450 6250 +F 0 "U1" H 1500 6350 30 0000 C CNN +F 1 "PORT" H 1450 6250 30 0000 C CNN +F 2 "" H 1450 6250 60 0000 C CNN +F 3 "" H 1450 6250 60 0000 C CNN + 10 1450 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C95ED51 +P 1400 6650 +F 0 "U1" H 1450 6750 30 0000 C CNN +F 1 "PORT" H 1400 6650 30 0000 C CNN +F 2 "" H 1400 6650 60 0000 C CNN +F 3 "" H 1400 6650 60 0000 C CNN + 9 1400 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C95EDCC +P 9250 3250 +F 0 "U1" H 9300 3350 30 0000 C CNN +F 1 "PORT" H 9250 3250 30 0000 C CNN +F 2 "" H 9250 3250 60 0000 C CNN +F 3 "" H 9250 3250 60 0000 C CNN + 12 9250 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C95EEA6 +P 9250 3750 +F 0 "U1" H 9300 3850 30 0000 C CNN +F 1 "PORT" H 9250 3750 30 0000 C CNN +F 2 "" H 9250 3750 60 0000 C CNN +F 3 "" H 9250 3750 60 0000 C CNN + 13 9250 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C95EF2D +P 9250 4200 +F 0 "U1" H 9300 4300 30 0000 C CNN +F 1 "PORT" H 9250 4200 30 0000 C CNN +F 2 "" H 9250 4200 60 0000 C CNN +F 3 "" H 9250 4200 60 0000 C CNN + 14 9250 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C95EFB5 +P 9200 4700 +F 0 "U1" H 9250 4800 30 0000 C CNN +F 1 "PORT" H 9200 4700 30 0000 C CNN +F 2 "" H 9200 4700 60 0000 C CNN +F 3 "" H 9200 4700 60 0000 C CNN + 11 9200 4700 + -1 0 0 1 +$EndComp +Text Notes 1950 1800 0 60 ~ 12 +A0\n +Text Notes 1950 2100 0 60 ~ 12 +A1 +Text Notes 1900 2650 0 60 ~ 12 +B0 +Text Notes 1900 2900 0 60 ~ 12 +B1\n +Text Notes 1900 3350 0 60 ~ 12 +C0\n +Text Notes 1900 3600 0 60 ~ 12 +C1\n +Text Notes 1800 4050 0 60 ~ 12 +D0 +Text Notes 1800 4300 0 60 ~ 12 +D1 +Text Notes 1850 6250 0 60 ~ 12 +SEL\n +Text Notes 1800 6650 0 60 ~ 12 +~EN +$Comp +L d_inverter U2 +U 1 1 5C95FD56 +P 2650 6650 +F 0 "U2" H 2650 6550 60 0000 C CNN +F 1 "d_inverter" H 2650 6800 60 0000 C CNN +F 2 "" H 2700 6600 60 0000 C CNN +F 3 "" H 2700 6600 60 0000 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 6650 2950 6650 +Wire Wire Line + 1650 6650 2350 6650 +Text Notes 8550 3200 0 60 ~ 12 +YA +Text Notes 8550 3700 0 60 ~ 12 +YB +Text Notes 8550 4200 2 60 ~ 12 +YC +Text Notes 8500 4700 0 60 ~ 12 +YD +Wire Wire Line + 3500 2000 3450 2000 +Wire Wire Line + 3450 2000 3450 5700 +Wire Wire Line + 3450 2500 3500 2500 +Wire Wire Line + 3450 2950 3550 2950 +Connection ~ 3450 2500 +Wire Wire Line + 3450 3450 3550 3450 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4250 3500 4250 +Connection ~ 3450 3450 +Wire Wire Line + 3450 4750 3500 4750 +Connection ~ 3450 4250 +Wire Wire Line + 3450 5200 3550 5200 +Connection ~ 3450 4750 +Wire Wire Line + 3400 5700 3550 5700 +Connection ~ 3450 5200 +Wire Wire Line + 3300 5600 3550 5600 +Wire Wire Line + 3300 4150 3300 5600 +Wire Wire Line + 3300 5100 3550 5100 +Wire Wire Line + 3300 4650 3500 4650 +Connection ~ 3300 5100 +Wire Wire Line + 3300 4150 3500 4150 +Connection ~ 3300 4650 +Wire Wire Line + 3250 3350 3550 3350 +Wire Wire Line + 3250 1900 3250 3350 +Wire Wire Line + 3250 2850 3550 2850 +Wire Wire Line + 3500 2400 3250 2400 +Connection ~ 3250 2850 +Wire Wire Line + 3500 1900 3250 1900 +Connection ~ 3250 2400 +Wire Wire Line + 3250 3000 3100 3000 +Wire Wire Line + 3100 3000 3100 6250 +Wire Wire Line + 3100 6250 3050 6250 +Connection ~ 3250 3000 +Wire Wire Line + 3300 5500 2200 5500 +Connection ~ 3300 5500 +Wire Wire Line + 3400 6650 3400 5700 +Connection ~ 3450 5700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir new file mode 100644 index 00000000..6920161c --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.cir @@ -0,0 +1,25 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or +U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter +X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and +X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and +X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and +X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and +X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and +X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and +X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and +X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and + +.end diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out new file mode 100644 index 00000000..3a11a42d --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.cir.out @@ -0,0 +1,45 @@ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir + +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro new file mode 100644 index 00000000..fcbb1fc8 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.pro @@ -0,0 +1,57 @@ +update=03/28/19 22:30:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_User +LibName24=eSim_Subckt diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch new file mode 100644 index 00000000..7fd3609e --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.sch @@ -0,0 +1,549 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:74157-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 1650 1850 2750 1850 +Wire Wire Line + 2750 3350 1650 3350 +Wire Wire Line + 2750 3050 2750 3350 +Wire Wire Line + 2800 4050 1650 4050 +Wire Wire Line + 2800 3550 2800 4050 +Wire Wire Line + 2200 2150 2200 4350 +Wire Wire Line + 2200 2150 1650 2150 +Wire Wire Line + 2150 2900 2150 4850 +Wire Wire Line + 2150 2900 1650 2900 +Wire Wire Line + 2100 3600 2100 5300 +Wire Wire Line + 2100 3600 1650 3600 +Wire Wire Line + 2050 4300 2050 5800 +Wire Wire Line + 1650 4300 2050 4300 +Wire Wire Line + 2200 5500 2200 6250 +$Comp +L d_or U20 +U 1 1 5C95E06C +P 6650 3300 +F 0 "U20" H 6650 3300 60 0000 C CNN +F 1 "d_or" H 6650 3400 60 0000 C CNN +F 2 "" H 6650 3300 60 0000 C CNN +F 3 "" H 6650 3300 60 0000 C CNN + 1 6650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U21 +U 1 1 5C95E114 +P 6650 3800 +F 0 "U21" H 6650 3800 60 0000 C CNN +F 1 "d_or" H 6650 3900 60 0000 C CNN +F 2 "" H 6650 3800 60 0000 C CNN +F 3 "" H 6650 3800 60 0000 C CNN + 1 6650 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U22 +U 1 1 5C95E16E +P 6650 4250 +F 0 "U22" H 6650 4250 60 0000 C CNN +F 1 "d_or" H 6650 4350 60 0000 C CNN +F 2 "" H 6650 4250 60 0000 C CNN +F 3 "" H 6650 4250 60 0000 C CNN + 1 6650 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U23 +U 1 1 5C95E1C9 +P 6650 4750 +F 0 "U23" H 6650 4750 60 0000 C CNN +F 1 "d_or" H 6650 4850 60 0000 C CNN +F 2 "" H 6650 4750 60 0000 C CNN +F 3 "" H 6650 4750 60 0000 C CNN + 1 6650 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 3200 5950 3200 +Wire Wire Line + 5950 3200 5950 2000 +Wire Wire Line + 5950 2000 4750 2000 +Wire Wire Line + 6200 3700 5850 3700 +Wire Wire Line + 5850 3700 5850 2500 +Wire Wire Line + 5850 2500 4750 2500 +Wire Wire Line + 6200 4150 5750 4150 +Wire Wire Line + 5750 4150 5750 2950 +Wire Wire Line + 5750 2950 4750 2950 +Wire Wire Line + 6200 4650 5650 4650 +Wire Wire Line + 5650 4650 5650 3450 +Wire Wire Line + 5650 3450 4750 3450 +Wire Wire Line + 4750 4250 5450 4250 +Wire Wire Line + 5450 4250 5450 3300 +Wire Wire Line + 5450 3300 6200 3300 +Wire Wire Line + 4750 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3800 +Wire Wire Line + 5550 3800 6200 3800 +Wire Wire Line + 4700 5200 5600 5200 +Wire Wire Line + 5600 5200 5600 4250 +Wire Wire Line + 5600 4250 6200 4250 +Wire Wire Line + 4750 5700 5700 5700 +Wire Wire Line + 5700 5700 5700 4750 +Wire Wire Line + 5700 4750 6200 4750 +Wire Wire Line + 7100 3250 8300 3250 +Wire Wire Line + 7100 3750 8300 3750 +Wire Wire Line + 7100 4200 8300 4200 +Wire Wire Line + 7100 4700 8250 4700 +$Comp +L d_inverter U3 +U 1 1 5C95E74D +P 2750 6250 +F 0 "U3" H 2750 6150 60 0000 C CNN +F 1 "d_inverter" H 2750 6400 60 0000 C CNN +F 2 "" H 2800 6200 60 0000 C CNN +F 3 "" H 2800 6200 60 0000 C CNN + 1 2750 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1700 6250 2450 6250 +Connection ~ 2200 6250 +$Comp +L PORT U1 +U 1 1 5C95E920 +P 1400 1850 +F 0 "U1" H 1450 1950 30 0000 C CNN +F 1 "PORT" H 1400 1850 30 0000 C CNN +F 2 "" H 1400 1850 60 0000 C CNN +F 3 "" H 1400 1850 60 0000 C CNN + 1 1400 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C95E9CF +P 1400 2150 +F 0 "U1" H 1450 2250 30 0000 C CNN +F 1 "PORT" H 1400 2150 30 0000 C CNN +F 2 "" H 1400 2150 60 0000 C CNN +F 3 "" H 1400 2150 60 0000 C CNN + 2 1400 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C95EA28 +P 1400 2700 +F 0 "U1" H 1450 2800 30 0000 C CNN +F 1 "PORT" H 1400 2700 30 0000 C CNN +F 2 "" H 1400 2700 60 0000 C CNN +F 3 "" H 1400 2700 60 0000 C CNN + 3 1400 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95EA9C +P 1400 2900 +F 0 "U1" H 1450 3000 30 0000 C CNN +F 1 "PORT" H 1400 2900 30 0000 C CNN +F 2 "" H 1400 2900 60 0000 C CNN +F 3 "" H 1400 2900 60 0000 C CNN + 4 1400 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95EAFD +P 1400 3350 +F 0 "U1" H 1450 3450 30 0000 C CNN +F 1 "PORT" H 1400 3350 30 0000 C CNN +F 2 "" H 1400 3350 60 0000 C CNN +F 3 "" H 1400 3350 60 0000 C CNN + 5 1400 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C95EB63 +P 1400 3600 +F 0 "U1" H 1450 3700 30 0000 C CNN +F 1 "PORT" H 1400 3600 30 0000 C CNN +F 2 "" H 1400 3600 60 0000 C CNN +F 3 "" H 1400 3600 60 0000 C CNN + 6 1400 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C95EBC8 +P 1400 4050 +F 0 "U1" H 1450 4150 30 0000 C CNN +F 1 "PORT" H 1400 4050 30 0000 C CNN +F 2 "" H 1400 4050 60 0000 C CNN +F 3 "" H 1400 4050 60 0000 C CNN + 7 1400 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C95EC38 +P 1400 4300 +F 0 "U1" H 1450 4400 30 0000 C CNN +F 1 "PORT" H 1400 4300 30 0000 C CNN +F 2 "" H 1400 4300 60 0000 C CNN +F 3 "" H 1400 4300 60 0000 C CNN + 8 1400 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C95ECA1 +P 1450 6250 +F 0 "U1" H 1500 6350 30 0000 C CNN +F 1 "PORT" H 1450 6250 30 0000 C CNN +F 2 "" H 1450 6250 60 0000 C CNN +F 3 "" H 1450 6250 60 0000 C CNN + 10 1450 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C95ED51 +P 1400 6650 +F 0 "U1" H 1450 6750 30 0000 C CNN +F 1 "PORT" H 1400 6650 30 0000 C CNN +F 2 "" H 1400 6650 60 0000 C CNN +F 3 "" H 1400 6650 60 0000 C CNN + 9 1400 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C95EDCC +P 8550 3250 +F 0 "U1" H 8600 3350 30 0000 C CNN +F 1 "PORT" H 8550 3250 30 0000 C CNN +F 2 "" H 8550 3250 60 0000 C CNN +F 3 "" H 8550 3250 60 0000 C CNN + 12 8550 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C95EEA6 +P 8550 3750 +F 0 "U1" H 8600 3850 30 0000 C CNN +F 1 "PORT" H 8550 3750 30 0000 C CNN +F 2 "" H 8550 3750 60 0000 C CNN +F 3 "" H 8550 3750 60 0000 C CNN + 13 8550 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C95EF2D +P 8550 4200 +F 0 "U1" H 8600 4300 30 0000 C CNN +F 1 "PORT" H 8550 4200 30 0000 C CNN +F 2 "" H 8550 4200 60 0000 C CNN +F 3 "" H 8550 4200 60 0000 C CNN + 14 8550 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C95EFB5 +P 8500 4700 +F 0 "U1" H 8550 4800 30 0000 C CNN +F 1 "PORT" H 8500 4700 30 0000 C CNN +F 2 "" H 8500 4700 60 0000 C CNN +F 3 "" H 8500 4700 60 0000 C CNN + 11 8500 4700 + -1 0 0 1 +$EndComp +Text Notes 1950 1800 0 60 ~ 12 +A0\n +Text Notes 1950 2100 0 60 ~ 12 +A1 +Text Notes 1900 2650 0 60 ~ 12 +B0 +Text Notes 1900 2900 0 60 ~ 12 +B1\n +Text Notes 1900 3350 0 60 ~ 12 +C0\n +Text Notes 1900 3600 0 60 ~ 12 +C1\n +Text Notes 1800 4050 0 60 ~ 12 +D0 +Text Notes 1800 4300 0 60 ~ 12 +D1 +Text Notes 1850 6250 0 60 ~ 12 +SEL\n +Text Notes 1800 6650 0 60 ~ 12 +~EN +$Comp +L d_inverter U2 +U 1 1 5C95FD56 +P 2650 6650 +F 0 "U2" H 2650 6550 60 0000 C CNN +F 1 "d_inverter" H 2650 6800 60 0000 C CNN +F 2 "" H 2700 6600 60 0000 C CNN +F 3 "" H 2700 6600 60 0000 C CNN + 1 2650 6650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 6650 2950 6650 +Wire Wire Line + 1650 6650 2350 6650 +Text Notes 7850 3200 0 60 ~ 12 +YA +Text Notes 7850 3700 0 60 ~ 12 +YB +Text Notes 7850 4200 2 60 ~ 12 +YC +Text Notes 7800 4700 0 60 ~ 12 +YD +Wire Wire Line + 3450 2000 3900 2000 +Wire Wire Line + 3450 2000 3450 5700 +Wire Wire Line + 3450 2500 3900 2500 +Wire Wire Line + 3450 2950 3900 2950 +Connection ~ 3450 2500 +Wire Wire Line + 3450 3450 3900 3450 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4250 3900 4250 +Connection ~ 3450 3450 +Wire Wire Line + 3450 4750 3900 4750 +Connection ~ 3450 4250 +Wire Wire Line + 3450 5200 3850 5200 +Connection ~ 3450 4750 +Wire Wire Line + 3400 5700 3900 5700 +Connection ~ 3450 5200 +Wire Wire Line + 3300 5600 3900 5600 +Wire Wire Line + 3300 4150 3300 5600 +Wire Wire Line + 3300 5100 3850 5100 +Wire Wire Line + 3300 4650 3900 4650 +Connection ~ 3300 5100 +Wire Wire Line + 3300 4150 3900 4150 +Connection ~ 3300 4650 +Wire Wire Line + 3250 3350 3900 3350 +Wire Wire Line + 3250 1900 3250 3350 +Wire Wire Line + 3250 2850 3900 2850 +Wire Wire Line + 3250 2400 3900 2400 +Connection ~ 3250 2850 +Wire Wire Line + 3250 1900 3900 1900 +Connection ~ 3250 2400 +Wire Wire Line + 3250 3000 3100 3000 +Wire Wire Line + 3100 3000 3100 6250 +Wire Wire Line + 3100 6250 3050 6250 +Connection ~ 3250 3000 +Wire Wire Line + 3300 5500 2200 5500 +Connection ~ 3300 5500 +Wire Wire Line + 3400 6650 3400 5700 +Connection ~ 3450 5700 +$Comp +L 3_and X2 +U 1 1 5C9D0110 +P 3450 2400 +F 0 "X2" H 4350 2700 60 0000 C CNN +F 1 "3_and" H 4400 2900 60 0000 C CNN +F 2 "" H 3450 2400 60 0000 C CNN +F 3 "" H 3450 2400 60 0000 C CNN + 1 3450 2400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 5C9D01B8 +P 3450 2900 +F 0 "X3" H 4350 3200 60 0000 C CNN +F 1 "3_and" H 4400 3400 60 0000 C CNN +F 2 "" H 3450 2900 60 0000 C CNN +F 3 "" H 3450 2900 60 0000 C CNN + 1 3450 2900 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 5C9D0222 +P 3450 3350 +F 0 "X4" H 4350 3650 60 0000 C CNN +F 1 "3_and" H 4400 3850 60 0000 C CNN +F 2 "" H 3450 3350 60 0000 C CNN +F 3 "" H 3450 3350 60 0000 C CNN + 1 3450 3350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 5C9D0289 +P 3450 3850 +F 0 "X5" H 4350 4150 60 0000 C CNN +F 1 "3_and" H 4400 4350 60 0000 C CNN +F 2 "" H 3450 3850 60 0000 C CNN +F 3 "" H 3450 3850 60 0000 C CNN + 1 3450 3850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 5C9D0361 +P 3450 4650 +F 0 "X6" H 4350 4950 60 0000 C CNN +F 1 "3_and" H 4400 5150 60 0000 C CNN +F 2 "" H 3450 4650 60 0000 C CNN +F 3 "" H 3450 4650 60 0000 C CNN + 1 3450 4650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 5C9D0367 +P 3450 5150 +F 0 "X7" H 4350 5450 60 0000 C CNN +F 1 "3_and" H 4400 5650 60 0000 C CNN +F 2 "" H 3450 5150 60 0000 C CNN +F 3 "" H 3450 5150 60 0000 C CNN + 1 3450 5150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 5C9D036D +P 3400 5600 +F 0 "X1" H 4300 5900 60 0000 C CNN +F 1 "3_and" H 4350 6100 60 0000 C CNN +F 2 "" H 3400 5600 60 0000 C CNN +F 3 "" H 3400 5600 60 0000 C CNN + 1 3400 5600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 5C9D0373 +P 3450 6100 +F 0 "X8" H 4350 6400 60 0000 C CNN +F 1 "3_and" H 4400 6600 60 0000 C CNN +F 2 "" H 3450 6100 60 0000 C CNN +F 3 "" H 3450 6100 60 0000 C CNN + 1 3450 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 2100 2750 2100 +Wire Wire Line + 2750 2100 2750 1850 +Wire Wire Line + 3900 2600 1650 2600 +Wire Wire Line + 1650 2600 1650 2700 +Wire Wire Line + 3900 3050 2750 3050 +Wire Wire Line + 3900 3550 2800 3550 +Wire Wire Line + 2200 4350 3900 4350 +Wire Wire Line + 2150 4850 3900 4850 +Wire Wire Line + 2100 5300 3850 5300 +Wire Wire Line + 2050 5800 3900 5800 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub new file mode 100644 index 00000000..545741f5 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157.sub @@ -0,0 +1,39 @@ +* Subcircuit 74157 +.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir +.include 3_and.sub +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74157
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml new file mode 100644 index 00000000..85f14960 --- /dev/null +++ b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/analysis b/src/SubcircuitLibrary/74157/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/74157/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/3_and.bak b/src/SubcircuitLibrary/7485/3_and.bak new file mode 100644 index 00000000..82d9bc0b --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.bak @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.pro @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.sch @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir new file mode 100644 index 00000000..50d490fa --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro new file mode 100644 index 00000000..6eb77fff --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.pro @@ -0,0 +1,57 @@ +update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch new file mode 100644 index 00000000..883458e1 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.sch @@ -0,0 +1,139 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib new file mode 100644 index 00000000..ac396288 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro new file mode 100644 index 00000000..c82e4e6d --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.pro @@ -0,0 +1,50 @@ +update=03/26/19 18:50:27 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch new file mode 100644 index 00000000..da927b09 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.sch @@ -0,0 +1,158 @@ +EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib new file mode 100644 index 00000000..6edb5033 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485-cache.lib @@ -0,0 +1,175 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# c_gate +# +DEF c_gate X 0 40 Y Y 1 F N +F0 "X" 5900 4450 60 H V C CNN +F1 "c_gate" 5950 4700 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 +P 2 0 1 0 5550 4850 6100 4850 N +P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N +X in1 1 5350 4800 200 R 50 50 1 1 I I +X in2 2 5350 4700 200 R 50 50 1 1 I I +X in3 3 5350 4600 200 R 50 50 1 1 I I +X in4 4 5350 4500 200 R 50 50 1 1 I I +X in5 5 5350 4400 200 R 50 50 1 1 I I +X in6 6 5350 4300 200 R 50 50 1 1 I I +X out 7 6500 4550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/7485.bak b/src/SubcircuitLibrary/7485/7485.bak new file mode 100644 index 00000000..873613dc --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.bak @@ -0,0 +1,1006 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U2 +U 1 1 5C9A246F +P 2100 1450 +F 0 "U2" H 2100 1450 60 0000 C CNN +F 1 "d_nand" H 2150 1550 60 0000 C CNN +F 2 "" H 2100 1450 60 0000 C CNN +F 3 "" H 2100 1450 60 0000 C CNN + 1 2100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C9A24BA +P 3150 1600 +F 0 "U7" H 3150 1600 60 0000 C CNN +F 1 "d_and" H 3200 1700 60 0000 C CNN +F 2 "" H 3150 1600 60 0000 C CNN +F 3 "" H 3150 1600 60 0000 C CNN + 1 3150 1600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 5C9A252F +P 4050 1400 +F 0 "U14" H 4050 1400 60 0000 C CNN +F 1 "d_nor" H 4100 1500 60 0000 C CNN +F 2 "" H 4050 1400 60 0000 C CNN +F 3 "" H 4050 1400 60 0000 C CNN + 1 4050 1400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9A2580 +P 6900 1000 +F 0 "U19" H 6900 1000 60 0000 C CNN +F 1 "d_and" H 6950 1100 60 0000 C CNN +F 2 "" H 6900 1000 60 0000 C CNN +F 3 "" H 6900 1000 60 0000 C CNN + 1 6900 1000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X12 +U 1 1 5C9A2DC4 +P 6050 1650 +F 0 "X12" H 6950 1950 60 0000 C CNN +F 1 "3_and" H 7000 2150 60 0000 C CNN +F 2 "" H 6050 1650 60 0000 C CNN +F 3 "" H 6050 1650 60 0000 C CNN + 1 6050 1650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9A2EB7 +P 5450 2750 +F 0 "X7" H 6950 3800 60 0000 C CNN +F 1 "4_and" H 7000 3950 60 0000 C CNN +F 2 "" H 5450 2750 60 0000 C CNN +F 3 "" H 5450 2750 60 0000 C CNN + 1 5450 2750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 5C9A2F2E +P 5650 3050 +F 0 "X9" H 7000 3850 60 0000 C CNN +F 1 "5_and" H 7050 4100 60 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 5C9A2F95 +P 5650 3600 +F 0 "X10" H 7000 4400 60 0000 C CNN +F 1 "5_and" H 7050 4650 60 0000 C CNN +F 2 "" H 5650 3600 60 0000 C CNN +F 3 "" H 5650 3600 60 0000 C CNN + 1 5650 3600 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 5C9A3164 +P 5650 4150 +F 0 "X11" H 7000 4950 60 0000 C CNN +F 1 "5_and" H 7050 5200 60 0000 C CNN +F 2 "" H 5650 4150 60 0000 C CNN +F 3 "" H 5650 4150 60 0000 C CNN + 1 5650 4150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 5C9A31B3 +P 7550 4850 +F 0 "X13" H 8900 5650 60 0000 C CNN +F 1 "5_and" H 8950 5900 60 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~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir new file mode 100644 index 00000000..e15a357f --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.cir @@ -0,0 +1,42 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand +U7 Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U19 Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +X12 Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and +X7 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and +X9 Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and +X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and +X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and +X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and +U18 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +X8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and +X3 Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and +X6 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and +X5 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and +X4 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and +U8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and +U3 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand +U9 Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor +U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U5 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand +U13 Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor +U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U4 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand +U11 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and +U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor +X2 Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out new file mode 100644 index 00000000..afc7b865 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.cir.out @@ -0,0 +1,101 @@ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir + +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro new file mode 100644 index 00000000..8fb4abb4 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.pro @@ -0,0 +1,58 @@ +update=03/26/19 19:27:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_User +LibName25=eSim_Subckt diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch new file mode 100644 index 00000000..0db5f0d6 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.sch @@ -0,0 +1,1127 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U2 +U 1 1 5C9A246F +P 2100 1450 +F 0 "U2" H 2100 1450 60 0000 C CNN +F 1 "d_nand" H 2150 1550 60 0000 C CNN +F 2 "" H 2100 1450 60 0000 C CNN +F 3 "" H 2100 1450 60 0000 C CNN + 1 2100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C9A24BA +P 3150 1600 +F 0 "U7" H 3150 1600 60 0000 C CNN +F 1 "d_and" H 3200 1700 60 0000 C CNN +F 2 "" H 3150 1600 60 0000 C CNN +F 3 "" H 3150 1600 60 0000 C CNN + 1 3150 1600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 5C9A252F +P 4050 1400 +F 0 "U14" H 4050 1400 60 0000 C CNN +F 1 "d_nor" H 4100 1500 60 0000 C CNN +F 2 "" H 4050 1400 60 0000 C CNN +F 3 "" H 4050 1400 60 0000 C CNN + 1 4050 1400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9A2580 +P 6900 1000 +F 0 "U19" H 6900 1000 60 0000 C CNN +F 1 "d_and" H 6950 1100 60 0000 C CNN +F 2 "" H 6900 1000 60 0000 C CNN +F 3 "" H 6900 1000 60 0000 C CNN + 1 6900 1000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X12 +U 1 1 5C9A2DC4 +P 6050 1650 +F 0 "X12" H 6950 1950 60 0000 C CNN +F 1 "3_and" H 7000 2150 60 0000 C CNN +F 2 "" H 6050 1650 60 0000 C CNN +F 3 "" H 6050 1650 60 0000 C CNN + 1 6050 1650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9A2EB7 +P 5450 2750 +F 0 "X7" H 6950 3800 60 0000 C CNN +F 1 "4_and" H 7000 3950 60 0000 C CNN +F 2 "" H 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1100 1450 +$Comp +L PORT U1 +U 6 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 6 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 7 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 7 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 8 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 9 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 11 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 1 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 2 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +Wire Wire Line + 2600 3400 2050 3400 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub new file mode 100644 index 00000000..5a45c57c --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485.sub @@ -0,0 +1,95 @@ +* Subcircuit 7485 +.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 +a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 +a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 7485
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml new file mode 100644 index 00000000..6d8f93b6 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib new file mode 100644 index 00000000..6edb5033 --- /dev/null +++ b/src/SubcircuitLibrary/7485/7485mod-cache.lib @@ -0,0 +1,175 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# c_gate +# +DEF c_gate X 0 40 Y Y 1 F N +F0 "X" 5900 4450 60 H V C CNN +F1 "c_gate" 5950 4700 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 +P 2 0 1 0 5550 4850 6100 4850 N +P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N +X in1 1 5350 4800 200 R 50 50 1 1 I I +X in2 2 5350 4700 200 R 50 50 1 1 I I +X in3 3 5350 4600 200 R 50 50 1 1 I I +X in4 4 5350 4500 200 R 50 50 1 1 I I +X in5 5 5350 4400 200 R 50 50 1 1 I I +X in6 6 5350 4300 200 R 50 50 1 1 I I +X out 7 6500 4550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch new file mode 100644 index 00000000..f7e537ad --- /dev/null +++ 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1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/analysis b/src/SubcircuitLibrary/7485/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/7485/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib new file mode 100644 index 00000000..05fb44d7 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/c_gate.bak b/src/SubcircuitLibrary/7485/c_gate.bak new file mode 100644 index 00000000..817352b8 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.bak @@ -0,0 +1,245 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5C9A2B0B +P 3300 3750 +F 0 "X1" H 4650 4550 60 0000 C CNN +F 1 "5_and" H 4700 4800 60 0000 C CNN +F 2 "" H 3300 3750 60 0000 C CNN +F 3 "" H 3300 3750 60 0000 C CNN + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A2B3E +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5C9A2CDC +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C9A2D06 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5C9A2D26 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5C9A2D49 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5C9A2D73 +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C9A2D9E +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5C9A2F6F +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A2FAB +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2FDD +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A301A +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A3052 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A308D +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A30DD +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir new file mode 100644 index 00000000..1ac12515 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out new file mode 100644 index 00000000..db7bb2f8 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.cir.out @@ -0,0 +1,42 @@ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir + +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro new file mode 100644 index 00000000..f0743529 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.pro @@ -0,0 +1,57 @@ +update=03/26/19 19:06:59 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch new file mode 100644 index 00000000..5d960c8d --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.sch @@ -0,0 +1,246 @@ +EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5C9A2B0B +P 3300 3750 +F 0 "X1" H 4650 4550 60 0000 C CNN +F 1 "5_and" H 4700 4800 60 0000 C CNN +F 2 "" H 3300 3750 60 0000 C CNN +F 3 "" H 3300 3750 60 0000 C CNN + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A2B3E +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5C9A2CDC +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C9A2D06 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5C9A2D26 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5C9A2D49 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5C9A2D73 +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C9A2D9E +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5C9A2F6F +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A2FAB +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2FDD +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A301A +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A3052 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A308D +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A30DD +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub new file mode 100644 index 00000000..c6eaa478 --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate.sub @@ -0,0 +1,36 @@ +* Subcircuit c_gate +.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends c_gate
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml new file mode 100644 index 00000000..e51d62de --- /dev/null +++ b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib new file mode 100644 index 00000000..c02b3211 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib @@ -0,0 +1,135 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib new file mode 100644 index 00000000..e6cfa7d6 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM7812/LM7812.bak b/src/SubcircuitLibrary/LM7812/LM7812.bak new file mode 100644 index 00000000..59b2f109 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.bak @@ -0,0 +1,757 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LM7812-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection 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V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "10.38k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir b/src/SubcircuitLibrary/LM7812/LM7812.cir new file mode 100644 index 00000000..3f0d3adf --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.cir @@ -0,0 +1,51 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir.out b/src/SubcircuitLibrary/LM7812/LM7812.cir.out new file mode 100644 index 00000000..73404965 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.cir.out @@ -0,0 +1,60 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LM7812/LM7812.pro b/src/SubcircuitLibrary/LM7812/LM7812.pro new file mode 100644 index 00000000..12d08139 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.pro @@ -0,0 +1,46 @@ +update=Mon Aug 26 14:09:03 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=LM7812-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User + diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sch b/src/SubcircuitLibrary/LM7812/LM7812.sch new file mode 100644 index 00000000..ca95c2ca --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.sch @@ -0,0 +1,758 @@ +EESchema Schematic File Version 2 +LIBS:LM7812-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LM7812-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 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R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 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CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line 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1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP-RESCUE-LM7812 Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN-RESCUE-LM7812 Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "10.38k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN-RESCUE-LM7812 Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sub b/src/SubcircuitLibrary/LM7812/LM7812.sub new file mode 100644 index 00000000..0dd95154 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.sub @@ -0,0 +1,54 @@ +* Subcircuit LM7812 +.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends LM7812
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml new file mode 100644 index 00000000..263f360c --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/NPN.lib b/src/SubcircuitLibrary/LM7812/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/PNP.lib b/src/SubcircuitLibrary/LM7812/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/Q_PNP.lib b/src/SubcircuitLibrary/LM7812/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/analysis b/src/SubcircuitLibrary/LM7812/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/analysis b/src/SubcircuitLibrary/full_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir b/src/SubcircuitLibrary/full_adder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir.out b/src/SubcircuitLibrary/full_adder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_adder/full_adder.pro b/src/SubcircuitLibrary/full_adder/full_adder.pro new file mode 100644 index 00000000..c0db0775 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sch b/src/SubcircuitLibrary/full_adder/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sub b/src/SubcircuitLibrary/full_adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir b/src/SubcircuitLibrary/full_adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir.out b/src/SubcircuitLibrary/full_adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_adder/half_adder.pro b/src/SubcircuitLibrary/full_adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sch b/src/SubcircuitLibrary/full_adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sub b/src/SubcircuitLibrary/full_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/analysis b/src/SubcircuitLibrary/full_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib new file mode 100644 index 00000000..6949ac1a --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib new file mode 100644 index 00000000..803b5ece --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib @@ -0,0 +1,20 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# half_sub-RESCUE-full_sub +# +DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1450 850 1550 -1050 0 1 0 N +X A 1 -1100 850 200 R 50 50 1 1 I +X B 2 -350 850 200 R 50 50 1 1 I +X D 3 -800 -1050 200 L 50 50 1 1 O +X BORROW 4 0 -1050 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub.bak b/src/SubcircuitLibrary/full_sub/full_sub.bak new file mode 100644 index 00000000..a8114299 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.bak @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:full_sub-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:full_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5C80734A +P 9350 4050 +F 0 "U3" H 9350 4050 60 0000 C CNN +F 1 "d_or" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4050 60 0000 C CNN +F 3 "" H 9350 4050 60 0000 C CNN + 1 9350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 3600 5800 3600 +Wire Wire Line + 4650 2800 8600 2800 +Wire Wire Line + 8600 2800 8600 3950 +Wire Wire Line + 8600 3950 8900 3950 +Wire Wire Line + 8100 4450 8650 4450 +Wire Wire Line + 8650 4450 8650 4050 +Wire Wire Line + 8650 4050 8900 4050 +Wire Wire Line + 2800 3450 2800 3250 +Wire Wire Line + 2800 3250 3300 3250 +Wire Wire Line + 1450 3550 3300 3550 +Wire Wire Line + 4050 5100 5200 5100 +Wire Wire Line + 5800 3600 5800 5250 +Wire Wire Line + 8250 5250 9350 5250 +Wire Wire Line + 9350 5250 9350 4900 +Wire Wire Line + 9350 4900 10750 4900 +Wire Wire Line + 9800 4000 9800 4600 +Wire Wire Line + 9800 4600 9550 4600 +Wire Wire Line + 9550 4600 9550 4800 +Wire Wire Line + 9550 4800 10750 4800 +$Comp +L PORT U5 +U 1 1 5C80A4E8 +P 1200 3450 +F 0 "U5" H 1250 3550 30 0000 C CNN +F 1 "PORT" H 1200 3450 30 0000 C CNN +F 2 "" H 1200 3450 60 0000 C CNN +F 3 "" H 1200 3450 60 0000 C CNN + 1 1200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 2 1 5C80A51E +P 1200 3650 +F 0 "U5" H 1250 3750 30 0000 C CNN +F 1 "PORT" H 1200 3650 30 0000 C CNN +F 2 "" H 1200 3650 60 0000 C CNN +F 3 "" H 1200 3650 60 0000 C CNN + 2 1200 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C80A54E +P 3800 5100 +F 0 "U5" H 3850 5200 30 0000 C CNN +F 1 "PORT" H 3800 5100 30 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 3 3800 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 5 1 5C80A828 +P 11000 4800 +F 0 "U5" H 11050 4900 30 0000 C CNN +F 1 "PORT" H 11000 4800 30 0000 C CNN +F 2 "" H 11000 4800 60 0000 C CNN +F 3 "" H 11000 4800 60 0000 C CNN + 5 11000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C80AB2A +P 11000 4950 +F 0 "U5" H 11050 5050 30 0000 C CNN +F 1 "PORT" H 11000 4950 30 0000 C CNN +F 2 "" H 11000 4950 60 0000 C CNN +F 3 "" H 11000 4950 60 0000 C CNN + 4 11000 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 3450 2800 3450 +Wire Wire Line + 1450 3650 1450 3550 +Wire Wire Line + 10750 4900 10750 4950 +$Comp +L half_sub X? +U 1 1 5C80AC4D +P 3800 3450 +F 0 "X?" H 3800 3450 60 0000 C CNN +F 1 "half_sub" H 3800 3450 60 0000 C CNN +F 2 "" H 3800 3450 60 0001 C CNN +F 3 "" H 3800 3450 60 0001 C CNN + 1 3800 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 2800 +Wire Wire Line + 4300 3300 4850 3300 +Wire Wire Line + 4850 3300 4850 3600 +$Comp +L half_sub X? +U 1 1 5C80AD72 +P 7300 5150 +F 0 "X?" H 7300 5150 60 0000 C CNN +F 1 "half_sub" H 7300 5150 60 0000 C CNN +F 2 "" H 7300 5150 60 0001 C CNN +F 3 "" H 7300 5150 60 0001 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 5250 6800 5250 +Wire Wire Line + 5200 5100 5200 4950 +Wire Wire Line + 5200 4950 6800 4950 +Wire Wire Line + 7800 5000 8250 5000 +Wire Wire Line + 8250 5000 8250 5250 +Wire Wire Line + 7800 5250 8100 5250 +Wire Wire Line + 8100 5250 8100 4450 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir new file mode 100644 index 00000000..67359421 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir @@ -0,0 +1,14 @@ +* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT +X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub +X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub + +.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out new file mode 100644 index 00000000..5e58cc0a --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir.out @@ -0,0 +1,19 @@ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir + +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro new file mode 100644 index 00000000..1a0c3543 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.pro @@ -0,0 +1,74 @@ +update=03/07/19 10:55:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=full_sub-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=device +LibName24=transistors +LibName25=conn +LibName26=linear +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_User +LibName39=eSim_Plot +LibName40=eSim_PSpice + diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch new file mode 100644 index 00000000..99ca85e5 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:full_sub-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:full_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5C80734A +P 9350 4050 +F 0 "U3" H 9350 4050 60 0000 C CNN +F 1 "d_or" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4050 60 0000 C CNN +F 3 "" H 9350 4050 60 0000 C CNN + 1 9350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 3600 5800 3600 +Wire Wire Line + 4650 2800 8600 2800 +Wire Wire Line + 8600 2800 8600 3950 +Wire Wire Line + 8600 3950 8900 3950 +Wire Wire Line + 8100 4450 8650 4450 +Wire Wire Line + 8650 4450 8650 4050 +Wire Wire Line + 8650 4050 8900 4050 +Wire Wire Line + 2800 3450 2800 3250 +Wire Wire Line + 2800 3250 3300 3250 +Wire Wire Line + 1450 3550 3300 3550 +Wire Wire Line + 4050 5100 5200 5100 +Wire Wire Line + 5800 3600 5800 5250 +Wire Wire Line + 8250 5250 9350 5250 +Wire Wire Line + 9350 5250 9350 4900 +Wire Wire Line + 9350 4900 10750 4900 +Wire Wire Line + 9800 4000 9800 4600 +Wire Wire Line + 9800 4600 9550 4600 +Wire Wire Line + 9550 4600 9550 4800 +Wire Wire Line + 9550 4800 10750 4800 +$Comp +L PORT U5 +U 1 1 5C80A4E8 +P 1200 3450 +F 0 "U5" H 1250 3550 30 0000 C CNN +F 1 "PORT" H 1200 3450 30 0000 C CNN +F 2 "" H 1200 3450 60 0000 C CNN +F 3 "" H 1200 3450 60 0000 C CNN + 1 1200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 2 1 5C80A51E +P 1200 3650 +F 0 "U5" H 1250 3750 30 0000 C CNN +F 1 "PORT" H 1200 3650 30 0000 C CNN +F 2 "" H 1200 3650 60 0000 C CNN +F 3 "" H 1200 3650 60 0000 C CNN + 2 1200 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C80A54E +P 3800 5100 +F 0 "U5" H 3850 5200 30 0000 C CNN +F 1 "PORT" H 3800 5100 30 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 3 3800 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 5 1 5C80A828 +P 11000 4800 +F 0 "U5" H 11050 4900 30 0000 C CNN +F 1 "PORT" H 11000 4800 30 0000 C CNN +F 2 "" H 11000 4800 60 0000 C CNN +F 3 "" H 11000 4800 60 0000 C CNN + 5 11000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C80AB2A +P 11000 4950 +F 0 "U5" H 11050 5050 30 0000 C CNN +F 1 "PORT" H 11000 4950 30 0000 C CNN +F 2 "" H 11000 4950 60 0000 C CNN +F 3 "" H 11000 4950 60 0000 C CNN + 4 11000 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 3450 2800 3450 +Wire Wire Line + 1450 3650 1450 3550 +Wire Wire Line + 10750 4900 10750 4950 +$Comp +L half_sub X1 +U 1 1 5C80AC4D +P 3800 3450 +F 0 "X1" H 3800 3450 60 0000 C CNN +F 1 "half_sub" H 3800 3450 60 0000 C CNN +F 2 "" H 3800 3450 60 0001 C CNN +F 3 "" H 3800 3450 60 0001 C CNN + 1 3800 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 2800 +Wire Wire Line + 4300 3300 4850 3300 +Wire Wire Line + 4850 3300 4850 3600 +$Comp +L half_sub X2 +U 1 1 5C80AD72 +P 7300 5150 +F 0 "X2" H 7300 5150 60 0000 C CNN +F 1 "half_sub" H 7300 5150 60 0000 C CNN +F 2 "" H 7300 5150 60 0001 C CNN +F 3 "" H 7300 5150 60 0001 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 5250 6800 5250 +Wire Wire Line + 5200 5100 5200 4950 +Wire Wire Line + 5200 4950 6800 4950 +Wire Wire Line + 7800 5000 8250 5000 +Wire Wire Line + 8250 5000 8250 5250 +Wire Wire Line + 7800 5250 8100 5250 +Wire Wire Line + 8100 5250 8100 4450 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub new file mode 100644 index 00000000..9c9dcc5a --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub.sub @@ -0,0 +1,13 @@ +* Subcircuit full_sub +.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml new file mode 100644 index 00000000..fcdb63e0 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub-cache.lib b/src/SubcircuitLibrary/full_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir b/src/SubcircuitLibrary/full_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.pro b/src/SubcircuitLibrary/full_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sch b/src/SubcircuitLibrary/full_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub new file mode 100644 index 00000000..a61a3409 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/analysis b/src/SubcircuitLibrary/half_adder/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir b/src/SubcircuitLibrary/half_adder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir.out b/src/SubcircuitLibrary/half_adder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/half_adder/half_adder.pro b/src/SubcircuitLibrary/half_adder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sch b/src/SubcircuitLibrary/half_adder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sub b/src/SubcircuitLibrary/half_adder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/analysis b/src/SubcircuitLibrary/half_sub/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/half_sub-cache.lib b/src/SubcircuitLibrary/half_sub/half_sub-cache.lib new file mode 100644 index 00000000..bd15e664 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir b/src/SubcircuitLibrary/half_sub/half_sub.cir new file mode 100644 index 00000000..f20f0368 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.cir @@ -0,0 +1,14 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir.out b/src/SubcircuitLibrary/half_sub/half_sub.cir.out new file mode 100644 index 00000000..91816956 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.cir.out @@ -0,0 +1,24 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.pro b/src/SubcircuitLibrary/half_sub/half_sub.pro new file mode 100644 index 00000000..90e3ded9 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.pro @@ -0,0 +1,74 @@ +update=Wed 06 Mar 2019 11:10:38 PM IST +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sch b/src/SubcircuitLibrary/half_sub/half_sub.sch new file mode 100644 index 00000000..e70b1675 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U3 +U 1 1 5C7FDDA3 +P 4400 3150 +F 0 "U3" H 4400 3150 60 0000 C CNN +F 1 "d_xor" H 4450 3250 47 0000 C CNN +F 2 "" H 4400 3150 60 0000 C CNN +F 3 "" H 4400 3150 60 0000 C CNN + 1 4400 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5C7FDDD8 +P 3400 3750 +F 0 "U2" H 3400 3650 60 0000 C CNN +F 1 "d_inverter" H 3400 3900 60 0000 C CNN +F 2 "" H 3450 3700 60 0000 C CNN +F 3 "" H 3450 3700 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FDE57 +P 4450 3750 +F 0 "U4" H 4450 3750 60 0000 C CNN +F 1 "d_and" H 4500 3850 60 0000 C CNN +F 2 "" H 4450 3750 60 0000 C CNN +F 3 "" H 4450 3750 60 0000 C CNN + 1 4450 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3150 3950 3650 +Wire Wire Line + 3950 3650 4000 3650 +Wire Wire Line + 3700 3750 4000 3750 +Wire Wire Line + 3100 3750 3100 3050 +Wire Wire Line + 2950 3050 3950 3050 +$Comp +L PORT U1 +U 1 1 5C7FDF5A +P 2700 3050 +F 0 "U1" H 2750 3150 30 0000 C CNN +F 1 "PORT" H 2700 3050 30 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FDF97 +P 3500 3350 +F 0 "U1" H 3550 3450 30 0000 C CNN +F 1 "PORT" H 3500 3350 30 0000 C CNN +F 2 "" H 3500 3350 60 0000 C CNN +F 3 "" H 3500 3350 60 0000 C CNN + 2 3500 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FE00A +P 5300 3100 +F 0 "U1" H 5350 3200 30 0000 C CNN +F 1 "PORT" H 5300 3100 30 0000 C CNN +F 2 "" H 5300 3100 60 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 3 5300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C7FE064 +P 5350 3700 +F 0 "U1" H 5400 3800 30 0000 C CNN +F 1 "PORT" H 5350 3700 30 0000 C CNN +F 2 "" H 5350 3700 60 0000 C CNN +F 3 "" H 5350 3700 60 0000 C CNN + 4 5350 3700 + -1 0 0 1 +$EndComp +Connection ~ 3100 3050 +Wire Wire Line + 3750 3350 3950 3350 +Connection ~ 3950 3350 +Wire Wire Line + 4850 3100 5050 3100 +Wire Wire Line + 4900 3700 5100 3700 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sub b/src/SubcircuitLibrary/half_sub/half_sub.sub new file mode 100644 index 00000000..a61a3409 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub.sub @@ -0,0 +1,18 @@ +* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml new file mode 100644 index 00000000..115ba703 --- /dev/null +++ b/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/NPN.lib b/src/SubcircuitLibrary/lm555n/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis new file mode 100644 index 00000000..a0953567 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/lm555n-cache.bak b/src/SubcircuitLibrary/lm555n/lm555n-cache.bak new file mode 100644 index 00000000..29460f2a --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n-cache.bak @@ -0,0 +1,207 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:00:30 AM IST +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter" 100 100 40 H V C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +# D_SRLatch +# +DEF D_SRLatch U 0 40 Y Y 1 F N +F0 "U" -200 250 60 H V C CNN +F1 "D_SRLatch" 0 100 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X S 1 -600 150 300 R 50 50 1 1 I +X R 2 -600 -150 300 R 50 50 1 1 I +X Enable 3 -600 0 300 R 50 50 1 1 I +X Set 4 150 -500 300 U 50 50 1 1 I +X Reset 5 -150 -500 300 U 50 50 1 1 I +X Q 6 600 150 300 L 50 50 1 1 O +X ~Q 7 600 -150 300 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# DAC8 +# +DEF DAC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "DAC8" 0 0 40 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# LIMIT8 +# +DEF LIMIT8 U 0 40 Y Y 8 F N +F0 "U" 0 100 30 H V C CNN +F1 "LIMIT8" 0 0 30 H V C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in 1 -300 0 150 R 25 25 1 1 I +X out 9 300 0 150 L 25 25 1 1 O +X in 2 -300 0 150 R 25 25 2 1 I +X out 10 300 0 150 L 25 25 2 1 O +X in 3 -300 0 150 R 25 25 3 1 I +X out 11 300 0 150 L 25 25 3 1 O +X in 4 -300 0 150 R 25 25 4 1 I +X out 12 300 0 150 L 25 25 4 1 O +X in 5 -300 0 150 R 25 25 5 1 I +X out 13 300 0 150 L 25 25 5 1 O +X in 6 -300 0 150 R 25 25 6 1 I +X out 14 300 0 150 L 25 25 6 1 O +X in 7 -300 0 150 R 25 25 7 1 I +X out 15 300 0 150 L 25 25 7 1 O +X in 8 -300 0 150 R 25 25 8 1 I +X out 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib new file mode 100644 index 00000000..fb2aef47 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib @@ -0,0 +1,246 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# ADC8 +# +DEF ADC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "ADC8" 0 0 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# DAC8 +# +DEF DAC8 U 0 10 Y Y 8 L N +F0 "U" -100 100 40 H V C CNN +F1 "DAC8" 0 0 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in1 1 -300 0 150 R 25 25 1 1 I +X out1 9 300 0 150 L 25 25 1 1 O +X in2 2 -300 0 150 R 25 25 2 1 I +X out2 10 300 0 150 L 25 25 2 1 O +X in3 3 -300 0 150 R 25 25 3 1 I +X out3 11 300 0 150 L 25 25 3 1 O +X in4 4 -300 0 150 R 25 25 4 1 I +X out4 12 300 0 150 L 25 25 4 1 O +X in5 5 -300 0 150 R 25 25 5 1 I +X out5 13 300 0 150 L 25 25 5 1 O +X in6 6 -300 0 150 R 25 25 6 1 I +X out6 14 300 0 150 L 25 25 6 1 O +X in7 7 -300 0 150 R 25 25 7 1 I +X out7 15 300 0 150 L 25 25 7 1 O +X in8 8 -300 0 150 R 25 25 8 1 I +X out8 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# D_SRLatch +# +DEF D_SRLatch U 0 40 Y Y 1 F N +F0 "U" -200 250 60 H V C CNN +F1 "D_SRLatch" 0 100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X S 1 -600 150 300 R 50 50 1 1 I +X R 2 -600 -150 300 R 50 50 1 1 I +X Enable 3 -600 0 300 R 50 50 1 1 I +X Set 4 150 -500 300 U 50 50 1 1 I +X Reset 5 -150 -500 300 U 50 50 1 1 I +X Q 6 600 150 300 L 50 50 1 1 O +X ~Q 7 600 -150 300 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# GND-RESCUE-lm555n +# +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# LIMIT8 +# +DEF LIMIT8 U 0 40 Y Y 8 F N +F0 "U" 0 100 30 H V C CNN +F1 "LIMIT8" 0 0 30 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -150 50 150 -50 0 1 0 N +X in 1 -300 0 150 R 25 25 1 1 I +X out 9 300 0 150 L 25 25 1 1 O +X in 2 -300 0 150 R 25 25 2 1 I +X out 10 300 0 150 L 25 25 2 1 O +X in 3 -300 0 150 R 25 25 3 1 I +X out 11 300 0 150 L 25 25 3 1 O +X in 4 -300 0 150 R 25 25 4 1 I +X out 12 300 0 150 L 25 25 4 1 O +X in 5 -300 0 150 R 25 25 5 1 I +X out 13 300 0 150 L 25 25 5 1 O +X in 6 -300 0 150 R 25 25 6 1 I +X out 14 300 0 150 L 25 25 6 1 O +X in 7 -300 0 150 R 25 25 7 1 I +X out 15 300 0 150 L 25 25 7 1 O +X in 8 -300 0 150 R 25 25 8 1 I +X out 16 300 0 150 L 25 25 8 1 O +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R-RESCUE-lm555n +# +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib new file mode 100644 index 00000000..fffeca36 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm555n/lm555n.bak b/src/SubcircuitLibrary/lm555n/lm555n.bak new file mode 100644 index 00000000..066e1c98 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.bak @@ -0,0 +1,486 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN +F 2 "" H 6700 4050 60 0001 C CNN +F 3 "" H 6700 4050 60 0001 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLatch U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN +F 2 "" H 7100 3400 60 0001 C CNN +F 3 "" H 7100 3400 60 0001 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN +F 2 "" H 5050 4050 60 0001 C CNN +F 3 "" H 5050 4050 60 0001 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN +F 2 "" H 6000 3550 60 0001 C CNN +F 3 "" H 6000 3550 60 0001 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN +F 2 "" H 5800 3850 60 0001 C CNN +F 3 "" H 5800 3850 60 0001 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN +F 2 "" H 7700 3950 60 0001 C CNN +F 3 "" H 7700 3950 60 0001 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN +F 2 "" H 7850 3550 60 0001 C CNN +F 3 "" H 7850 3550 60 0001 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN +F 2 "" H 6350 4350 60 0001 C CNN +F 3 "" H 6350 4350 60 0001 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN +F 2 "" H 6350 3550 60 0001 C CNN +F 3 "" H 6350 3550 60 0001 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN +F 2 "" H 6200 3850 60 0001 C CNN +F 3 "" H 6200 3850 60 0001 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN +F 2 "" H 5750 4400 60 0001 C CNN +F 3 "" H 5750 4400 60 0001 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN +F 2 "" H 4050 3550 60 0001 C CNN +F 3 "" H 4050 3550 60 0001 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN +F 2 "" H 4050 4900 60 0001 C CNN +F 3 "" H 4050 4900 60 0001 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN +F 2 "" H 4700 5000 60 0001 C CNN +F 3 "" H 4700 5000 60 0001 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN +F 2 "" H 6350 5000 60 0001 C CNN +F 3 "" H 6350 5000 60 0001 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN +F 2 "" H 8050 4350 60 0001 C CNN +F 3 "" H 8050 4350 60 0001 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN +F 2 "" H 8150 3850 60 0001 C CNN +F 3 "" H 8150 3850 60 0001 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN +F 2 "" H 5150 3000 60 0001 C CNN +F 3 "" H 5150 3000 60 0001 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN +F 2 "" H 4050 3000 60 0001 C CNN +F 3 "" H 4050 3000 60 0001 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN +F 2 "" H 7350 4250 60 0001 C CNN +F 3 "" H 7350 4250 60 0001 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN +F 2 "" H 7600 4600 60 0001 C CNN +F 3 "" H 7600 4600 60 0001 C CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN +F 2 "" H 5550 4500 60 0001 C CNN +F 3 "" H 5550 4500 60 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN +F 2 "" H 5650 3250 60 0001 C CNN +F 3 "" H 5650 3250 60 0001 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN +F 2 "" H 5450 3550 60 0001 C CNN +F 3 "" H 5450 3550 60 0001 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN +F 2 "" H 5500 4050 60 0001 C CNN +F 3 "" H 5500 4050 60 0001 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN +F 2 "" H 4700 3250 60 0001 C CNN +F 3 "" H 4700 3250 60 0001 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN +F 2 "" H 4700 4400 60 0001 C CNN +F 3 "" H 4700 4400 60 0001 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN +F 2 "" H 4400 4450 60 0001 C CNN +F 3 "" H 4400 4450 60 0001 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN +F 2 "" H 4400 3850 60 0001 C CNN +F 3 "" H 4400 3850 60 0001 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN +F 2 "" H 4400 3250 60 0001 C CNN +F 3 "" H 4400 3250 60 0001 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir new file mode 100644 index 00000000..807cd6e9 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir @@ -0,0 +1,27 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jan 28 13:25:01 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U2-Pad11_ Net-_U5-Pad2_ D_INVERTER +U6 Net-_U2-Pad10_ Net-_U2-Pad9_ Net-_U2-Pad11_ Net-_U5-Pad2_ Net-_U5-Pad2_ Net-_U3-Pad1_ Net-_U3-Pad2_ D_SRLATCH +E2 Net-_E2-Pad1_ GND /c /d 10000 +U4 Net-_R6-Pad2_ Net-_R7-Pad2_ Net-_U2-Pad1_ Net-_U2-Pad2_ LIMIT8 +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_R8-Pad1_ DAC8 +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ ADC8 +U1 Net-_Q1-Pad1_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad3_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ QNOM +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad1_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 + +.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt new file mode 100644 index 00000000..f45920fd --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out new file mode 100644 index 00000000..f45920fd --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro new file mode 100644 index 00000000..0a5408b6 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.pro @@ -0,0 +1,57 @@ +update=Tue Apr 2 17:35:59 2019 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=lm555n-rescue +LibName2=power +LibName3=device +LibName4=transistors +LibName5=conn +LibName6=linear +LibName7=regul +LibName8=74xx +LibName9=cmos4000 +LibName10=adc-dac +LibName11=memory +LibName12=xilinx +LibName13=special +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=valves +LibName32=analogSpice +LibName33=analogXSpice +LibName34=converterSpice +LibName35=digitalSpice +LibName36=linearSpice +LibName37=measurementSpice +LibName38=portSpice +LibName39=sourcesSpice +LibName40=digitalXSpice +LibName41=eSim_User +LibName42=eSim_Subckt +LibName43=eSim_Sources +LibName44=eSim_PSpice +LibName45=eSim_Power +LibName46=eSim_Plot +LibName47=eSim_Miscellaneous +LibName48=eSim_Hybrid +LibName49=eSim_Digital +LibName50=eSim_Devices +LibName51=eSim_Analog diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch new file mode 100644 index 00000000..6b588212 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.sch @@ -0,0 +1,497 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter-RESCUE-lm555n U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN +F 2 "" H 6700 4050 60 0001 C CNN +F 3 "" H 6700 4050 60 0001 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLatch U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN +F 2 "" H 7100 3400 60 0001 C CNN +F 3 "" H 7100 3400 60 0001 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN +F 2 "" H 5050 4050 60 0001 C CNN +F 3 "" H 5050 4050 60 0001 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN +F 2 "" H 6000 3550 60 0001 C CNN +F 3 "" H 6000 3550 60 0001 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN +F 2 "" H 5800 3850 60 0001 C CNN +F 3 "" H 5800 3850 60 0001 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN +F 2 "" H 7700 3950 60 0001 C CNN +F 3 "" H 7700 3950 60 0001 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN +F 2 "" H 7850 3550 60 0001 C CNN +F 3 "" H 7850 3550 60 0001 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN +F 2 "" H 6350 4350 60 0001 C CNN +F 3 "" H 6350 4350 60 0001 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN +F 2 "" H 6350 3550 60 0001 C CNN +F 3 "" H 6350 3550 60 0001 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN +F 2 "" H 6200 3850 60 0001 C CNN +F 3 "" H 6200 3850 60 0001 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN +F 2 "" H 5750 4400 60 0001 C CNN +F 3 "" H 5750 4400 60 0001 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN +F 2 "" H 4050 3550 60 0001 C CNN +F 3 "" H 4050 3550 60 0001 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN +F 2 "" H 4050 4900 60 0001 C CNN +F 3 "" H 4050 4900 60 0001 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN +F 2 "" H 4700 5000 60 0001 C CNN +F 3 "" H 4700 5000 60 0001 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN +F 2 "" H 6350 5000 60 0001 C CNN +F 3 "" H 6350 5000 60 0001 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN +F 2 "" H 8050 4350 60 0001 C CNN +F 3 "" H 8050 4350 60 0001 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN +F 2 "" H 8150 3850 60 0001 C CNN +F 3 "" H 8150 3850 60 0001 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN +F 2 "" H 5150 3000 60 0001 C CNN +F 3 "" H 5150 3000 60 0001 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN +F 2 "" H 4050 3000 60 0001 C CNN +F 3 "" H 4050 3000 60 0001 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN +F 2 "" H 7350 4250 60 0001 C CNN +F 3 "" H 7350 4250 60 0001 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN +F 2 "" H 7600 4600 60 0001 C CNN +F 3 "" H 7600 4600 60 0001 C CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN +F 2 "" H 5550 4500 60 0001 C CNN +F 3 "" H 5550 4500 60 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN +F 2 "" H 5650 3250 60 0001 C CNN +F 3 "" H 5650 3250 60 0001 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN +F 2 "" H 5450 3550 60 0001 C CNN +F 3 "" H 5450 3550 60 0001 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN +F 2 "" H 5500 4050 60 0001 C CNN +F 3 "" H 5500 4050 60 0001 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN +F 2 "" H 4700 3250 60 0001 C CNN +F 3 "" H 4700 3250 60 0001 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN +F 2 "" H 4700 4400 60 0001 C CNN +F 3 "" H 4700 4400 60 0001 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN +F 2 "" H 4400 4450 60 0001 C CNN +F 3 "" H 4400 4450 60 0001 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN +F 2 "" H 4400 3850 60 0001 C CNN +F 3 "" H 4400 3850 60 0001 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN +F 2 "" H 4400 3250 60 0001 C CNN +F 3 "" H 4400 3250 60 0001 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub new file mode 100644 index 00000000..beeefc43 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.sub @@ -0,0 +1,37 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.ends lm555n
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml new file mode 100644 index 00000000..58d33ec5 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/NPN.lib b/src/SubcircuitLibrary/lm7805/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm7805/PNP.lib b/src/SubcircuitLibrary/lm7805/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/lm7805/Q_PNP.lib b/src/SubcircuitLibrary/lm7805/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/analysis b/src/SubcircuitLibrary/lm7805/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib new file mode 100644 index 00000000..aaf8454e --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm7805/lm7805.bak b/src/SubcircuitLibrary/lm7805/lm7805.bak new file mode 100644 index 00000000..9c341478 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.bak @@ -0,0 +1,785 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:lm7805-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "1.385k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir b/src/SubcircuitLibrary/lm7805/lm7805.cir new file mode 100644 index 00000000..081b4920 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.cir @@ -0,0 +1,51 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir.out b/src/SubcircuitLibrary/lm7805/lm7805.cir.out new file mode 100644 index 00000000..f122fba6 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.cir.out @@ -0,0 +1,60 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm7805/lm7805.pro b/src/SubcircuitLibrary/lm7805/lm7805.pro new file mode 100644 index 00000000..d410e2fa --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.pro @@ -0,0 +1,45 @@ +update=Mon Aug 26 14:34:23 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User + diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sch b/src/SubcircuitLibrary/lm7805/lm7805.sch new file mode 100644 index 00000000..701d163d --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.sch @@ -0,0 +1,757 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm7805-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 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C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 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V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp 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Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sub b/src/SubcircuitLibrary/lm7805/lm7805.sub new file mode 100644 index 00000000..7ee1489c --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.sub @@ -0,0 +1,54 @@ +* Subcircuit lm7805 +.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends lm7805
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml new file mode 100644 index 00000000..7395bd7c --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/NPN.lib b/src/SubcircuitLibrary/lm_741/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm_741/PNP.lib b/src/SubcircuitLibrary/lm_741/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/lm_741/analysis b/src/SubcircuitLibrary/lm_741/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm_741/lm_741.bak b/src/SubcircuitLibrary/lm_741/lm_741.bak new file mode 100644 index 00000000..2c42e859 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.bak @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:741_7-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 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C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 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8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir b/src/SubcircuitLibrary/lm_741/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir.out b/src/SubcircuitLibrary/lm_741/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm_741/lm_741.pro b/src/SubcircuitLibrary/lm_741/lm_741.pro new file mode 100644 index 00000000..cbe83f35 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.pro @@ -0,0 +1,45 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sch b/src/SubcircuitLibrary/lm_741/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sub b/src/SubcircuitLibrary/lm_741/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/npn_1.lib b/src/SubcircuitLibrary/lm_741/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/pnp_1.lib b/src/SubcircuitLibrary/lm_741/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib new file mode 100644 index 00000000..ef18bb50 --- /dev/null +++ b/src/SubcircuitLibrary/scr/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/src/SubcircuitLibrary/scr/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/analysis b/src/SubcircuitLibrary/scr/analysis new file mode 100644 index 00000000..687c71ec --- /dev/null +++ b/src/SubcircuitLibrary/scr/analysis @@ -0,0 +1 @@ +.tran 0e-12 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib new file mode 100644 index 00000000..0a685b80 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/scr/scr-rescue.lib b/src/SubcircuitLibrary/scr/scr-rescue.lib new file mode 100644 index 00000000..64237b7d --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr-rescue.lib @@ -0,0 +1,39 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/scr/scr.bak b/src/SubcircuitLibrary/scr/scr.bak new file mode 100644 index 00000000..1f23ec65 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.bak @@ -0,0 +1,241 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:scr-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 aug 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3600 3250 3600 3150 +Connection ~ 5550 4950 +Wire Wire Line + 5800 3900 5800 3850 +Wire Wire Line + 5800 3850 6150 3850 +Wire Wire Line + 6150 3850 6150 4950 +Wire Wire Line + 6150 4950 3600 4950 +Connection ~ 4300 4950 +Wire Wire Line + 4300 4950 4300 4050 +Wire Wire Line + 4300 4050 3850 4050 +Wire Wire Line + 4700 5400 4700 5950 +Wire Wire Line + 4250 5950 4250 5500 +Connection ~ 4250 4950 +Wire Wire Line + 4250 4950 4250 5200 +Wire Wire Line + 5550 3600 5550 3450 +Wire Wire Line + 5550 4950 5550 4250 +Wire Wire Line + 3600 4950 3600 4400 +Wire Wire Line + 3600 2300 3600 2850 +Wire Wire Line + 3600 2300 3150 2300 +Wire Wire Line + 3600 4150 3600 4300 +Wire Wire Line + 5550 4150 5550 4000 +Wire Wire Line + 5550 2550 5550 2250 +Wire Wire Line + 4700 4950 4700 5100 +Connection ~ 4700 4950 +Wire Wire Line + 6650 2000 6650 5950 +Connection ~ 4700 5950 +Wire Wire Line + 3850 4650 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 4250 5950 +Wire Wire Line + 5800 4500 5800 5950 +Connection ~ 5800 5950 +$Comp +L PORT U2 +U 3 1 53F4C93D +P 6650 2250 +F 0 "U2" H 6650 2200 30 0000 C CNN +F 1 "PORT" H 6650 2250 30 0000 C CNN +F 2 "" H 6650 2250 60 0001 C CNN +F 3 "" H 6650 2250 60 0001 C CNN + 3 6650 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 53F4C934 +P 2900 2300 +F 0 "U2" H 2900 2250 30 0000 C CNN +F 1 "PORT" H 2900 2300 30 0000 C CNN +F 2 "" H 2900 2300 60 0001 C CNN +F 3 "" H 2900 2300 60 0001 C CNN + 2 2900 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 1 1 53F4C92A +P 6400 4950 +F 0 "U2" H 6400 4900 30 0000 C CNN +F 1 "PORT" H 6400 4950 30 0000 C CNN +F 2 "" H 6400 4950 60 0001 C CNN +F 3 "" H 6400 4950 60 0001 C CNN + 1 6400 4950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 53F4C735 +P 5750 4200 +F 0 "F2" H 5550 4300 50 0000 C CNN +F 1 "100" H 5550 4150 50 0000 C CNN +F 2 "" H 5750 4200 60 0001 C CNN +F 3 "" H 5750 4200 60 0001 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 53F4C6D9 +P 5550 3800 +F 0 "D1" H 5550 3900 40 0000 C CNN +F 1 "D" H 5550 3700 40 0000 C CNN +F 2 "" H 5550 3800 60 0001 C CNN +F 3 "" H 5550 3800 60 0001 C CNN + 1 5550 3800 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 53F4C6C2 +P 4700 5250 +F 0 "C1" H 4750 5350 50 0000 L CNN +F 1 "10u" H 4750 5150 50 0000 L CNN +F 2 "" H 4700 5250 60 0001 C CNN +F 3 "" H 4700 5250 60 0001 C CNN + 1 4700 5250 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 53F4C67F +P 3800 4350 +F 0 "F1" H 3600 4450 50 0000 C CNN +F 1 "10" H 3600 4300 50 0000 C CNN +F 2 "" H 3800 4350 60 0001 C CNN +F 3 "" H 3800 4350 60 0001 C CNN + 1 3800 4350 + 0 1 1 0 +$EndComp +$Comp +L dc v1 +U 1 1 565DBF58 +P 3600 3700 +F 0 "v1" H 3400 3800 60 0000 C CNN +F 1 "dc" H 3400 3650 60 0000 C CNN +F 2 "R1" H 3300 3700 60 0000 C CNN +F 3 "" H 3600 3700 60 0000 C CNN + 1 3600 3700 + 1 0 0 -1 +$EndComp +$Comp +L dc v2 +U 1 1 565DC066 +P 5550 3000 +F 0 "v2" H 5350 3100 60 0000 C CNN +F 1 "dc" H 5350 2950 60 0000 C CNN +F 2 "R1" H 5250 3000 60 0000 C CNN +F 3 "" H 5550 3000 60 0000 C CNN + 1 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 565DC87E +P 6400 2100 +F 0 "U1" H 6850 2400 60 0000 C CNN +F 1 "aswitch" H 6850 2300 60 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 1 6400 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2000 6650 2000 +$Comp +L R R1 +U 1 1 5666B019 +P 3550 2950 +F 0 "R1" H 3600 3080 50 0000 C CNN +F 1 "50" H 3600 3000 50 0000 C CNN +F 2 "" H 3600 2930 30 0000 C CNN +F 3 "" V 3600 3000 30 0000 C CNN + 1 3550 2950 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5666B17A +P 4200 5300 +F 0 "R2" H 4250 5430 50 0000 C CNN +F 1 "1" H 4250 5350 50 0000 C CNN +F 2 "" H 4250 5280 30 0000 C CNN +F 3 "" V 4250 5350 30 0000 C CNN + 1 4200 5300 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/scr/scr.cir b/src/SubcircuitLibrary/scr/scr.cir new file mode 100644 index 00000000..4b279764 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir @@ -0,0 +1,20 @@ +* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:47:20 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 3 7 1 PORT +F2 3 9 2 3 100 +D1 5 2 D +C1 3 9 10u +F1 3 9 4 3 10 +v1 8 4 dc +v2 6 5 dc +U1 9 1 6 aswitch +R1 7 8 50 +R2 3 9 1 + +.end diff --git a/src/SubcircuitLibrary/scr/scr.cir.ckt b/src/SubcircuitLibrary/scr/scr.cir.ckt new file mode 100644 index 00000000..ec994b75 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir.ckt @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22 +.include diode.lib + +u2 5 8 1 port +* f2 +* Analog Switch analogswitch +d1 4 2 diode +v2 3 4 dc 0 +c1 5 6 10u +r2 5 6 1 +* f1 +v1 9 7 dc 0 +r1 8 9 50 +Vf2 2 5 0 +f2 5 6 Vf2 100 +Vf1 7 5 0 +f1 5 6 Vf1 10 +a1 6 (1 3) u1 +.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000) diff --git a/src/SubcircuitLibrary/scr/scr.cir.out b/src/SubcircuitLibrary/scr/scr.cir.out new file mode 100644 index 00000000..d600f25d --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir.out @@ -0,0 +1,29 @@ +* /opt/esim/src/subcircuitlibrary/scr/scr.cir + +.include PowerDiode.lib +* u2 3 7 1 port +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro new file mode 100644 index 00000000..ca0df803 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.pro @@ -0,0 +1,45 @@ +update=Wed Jul 31 19:51:09 2019 +last_client=kicad +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=scr-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Sources +LibName8=eSim_Subckt +LibName9=eSim_User +LibName10=power +LibName11=device +LibName12=transistors +LibName13=conn +LibName14=linear +LibName15=regul +LibName16=74xx +LibName17=cmos4000 +LibName18=adc-dac +LibName19=memory +LibName20=xilinx +LibName21=special +LibName22=microcontrollers +LibName23=dsp +LibName24=microchip +LibName25=analog_switches +LibName26=motorola +LibName27=texas +LibName28=intel +LibName29=audio +LibName30=interface +LibName31=digital-audio +LibName32=philips +LibName33=display +LibName34=cypress +LibName35=siliconi +LibName36=opto +LibName37=atmel +LibName38=contrib +LibName39=valves diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch new file mode 100644 index 00000000..69244f56 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.sch @@ -0,0 +1,242 @@ +EESchema Schematic File Version 2 +LIBS:scr-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:scr-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 aug 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3600 3250 3600 3150 +Connection ~ 5550 4950 +Wire Wire Line + 5800 3900 5800 3850 +Wire Wire Line + 5800 3850 6150 3850 +Wire Wire Line + 6150 3850 6150 4950 +Wire Wire Line + 6150 4950 3600 4950 +Connection ~ 4300 4950 +Wire Wire Line + 4300 4950 4300 4050 +Wire Wire Line + 4300 4050 3850 4050 +Wire Wire Line + 4700 5400 4700 5950 +Wire Wire Line + 4250 5950 4250 5500 +Connection ~ 4250 4950 +Wire Wire Line + 4250 4950 4250 5200 +Wire Wire Line + 5550 3600 5550 3450 +Wire Wire Line + 5550 4950 5550 4250 +Wire Wire Line + 3600 4950 3600 4400 +Wire Wire Line + 3600 2300 3600 2850 +Wire Wire Line + 3600 2300 3150 2300 +Wire Wire Line + 3600 4150 3600 4300 +Wire Wire Line + 5550 4150 5550 4000 +Wire Wire Line + 5550 2550 5550 2250 +Wire Wire Line + 4700 4950 4700 5100 +Connection ~ 4700 4950 +Wire Wire Line + 6650 2000 6650 5950 +Connection ~ 4700 5950 +Wire Wire Line + 3850 4650 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 4250 5950 +Wire Wire Line + 5800 4500 5800 5950 +Connection ~ 5800 5950 +$Comp +L PORT U2 +U 3 1 53F4C93D +P 6650 2250 +F 0 "U2" H 6650 2200 30 0000 C CNN +F 1 "PORT" H 6650 2250 30 0000 C CNN +F 2 "" H 6650 2250 60 0001 C CNN +F 3 "" H 6650 2250 60 0001 C CNN + 3 6650 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 53F4C934 +P 2900 2300 +F 0 "U2" H 2900 2250 30 0000 C CNN +F 1 "PORT" H 2900 2300 30 0000 C CNN +F 2 "" H 2900 2300 60 0001 C CNN +F 3 "" H 2900 2300 60 0001 C CNN + 2 2900 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 1 1 53F4C92A +P 6400 4950 +F 0 "U2" H 6400 4900 30 0000 C CNN +F 1 "PORT" H 6400 4950 30 0000 C CNN +F 2 "" H 6400 4950 60 0001 C CNN +F 3 "" H 6400 4950 60 0001 C CNN + 1 6400 4950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 53F4C735 +P 5750 4200 +F 0 "F2" H 5550 4300 50 0000 C CNN +F 1 "100" H 5550 4150 50 0000 C CNN +F 2 "" H 5750 4200 60 0001 C CNN +F 3 "" H 5750 4200 60 0001 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 53F4C6D9 +P 5550 3800 +F 0 "D1" H 5550 3900 40 0000 C CNN +F 1 "D" H 5550 3700 40 0000 C CNN +F 2 "" H 5550 3800 60 0001 C CNN +F 3 "" H 5550 3800 60 0001 C CNN + 1 5550 3800 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 53F4C6C2 +P 4700 5250 +F 0 "C1" H 4750 5350 50 0000 L CNN +F 1 "10u" H 4750 5150 50 0000 L CNN +F 2 "" H 4700 5250 60 0001 C CNN +F 3 "" H 4700 5250 60 0001 C CNN + 1 4700 5250 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 53F4C67F +P 3800 4350 +F 0 "F1" H 3600 4450 50 0000 C CNN +F 1 "10" H 3600 4300 50 0000 C CNN +F 2 "" H 3800 4350 60 0001 C CNN +F 3 "" H 3800 4350 60 0001 C CNN + 1 3800 4350 + 0 1 1 0 +$EndComp +$Comp +L dc-RESCUE-scr v1 +U 1 1 565DBF58 +P 3600 3700 +F 0 "v1" H 3400 3800 60 0000 C CNN +F 1 "dc" H 3400 3650 60 0000 C CNN +F 2 "R1" H 3300 3700 60 0000 C CNN +F 3 "" H 3600 3700 60 0000 C CNN + 1 3600 3700 + 1 0 0 -1 +$EndComp +$Comp +L dc-RESCUE-scr v2 +U 1 1 565DC066 +P 5550 3000 +F 0 "v2" H 5350 3100 60 0000 C CNN +F 1 "dc" H 5350 2950 60 0000 C CNN +F 2 "R1" H 5250 3000 60 0000 C CNN +F 3 "" H 5550 3000 60 0000 C CNN + 1 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 565DC87E +P 6400 2100 +F 0 "U1" H 6850 2400 60 0000 C CNN +F 1 "aswitch" H 6850 2300 60 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 1 6400 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2000 6650 2000 +$Comp +L R-RESCUE-scr R1 +U 1 1 5666B019 +P 3550 2950 +F 0 "R1" H 3600 3080 50 0000 C CNN +F 1 "50" H 3600 3000 50 0000 C CNN +F 2 "" H 3600 2930 30 0000 C CNN +F 3 "" V 3600 3000 30 0000 C CNN + 1 3550 2950 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-scr R2 +U 1 1 5666B17A +P 4200 5300 +F 0 "R2" H 4250 5430 50 0000 C CNN +F 1 "1" H 4250 5350 50 0000 C CNN +F 2 "" H 4250 5280 30 0000 C CNN +F 3 "" V 4250 5350 30 0000 C CNN + 1 4200 5300 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/scr/scr.sub b/src/SubcircuitLibrary/scr/scr.sub new file mode 100644 index 00000000..398c8921 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.sub @@ -0,0 +1,23 @@ +* Subcircuit scr +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.include PowerDiode.lib +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr diff --git a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml new file mode 100644 index 00000000..8ff6e8d3 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/analysis b/src/SubcircuitLibrary/ua741/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/ua741/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/ua741.cir b/src/SubcircuitLibrary/ua741/ua741.cir new file mode 100644 index 00000000..de797429 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.out b/src/SubcircuitLibrary/ua741/ua741.cir.out new file mode 100644 index 00000000..72e68514 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +* u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro new file mode 100644 index 00000000..5dbb81a5 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/src/SubcircuitLibrary/ua741/ua741.sch b/src/SubcircuitLibrary/ua741/ua741.sch new file mode 100644 index 00000000..7dfc5e1a --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ua741/ua741.sub b/src/SubcircuitLibrary/ua741/ua741.sub new file mode 100644 index 00000000..ad26c001 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.sub @@ -0,0 +1,12 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/D.lib b/src/SubcircuitLibrary/ujt/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/src/SubcircuitLibrary/ujt/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/SubcircuitLibrary/ujt/analysis b/src/SubcircuitLibrary/ujt/analysis new file mode 100644 index 00000000..ffc57a6b --- /dev/null +++ b/src/SubcircuitLibrary/ujt/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/emitter.lib b/src/SubcircuitLibrary/ujt/emitter.lib new file mode 100644 index 00000000..3e78b1ee --- /dev/null +++ b/src/SubcircuitLibrary/ujt/emitter.lib @@ -0,0 +1,11 @@ +.model emitter D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=21.3P ++ M=1.959E-01 ++ N=1.8 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +) diff --git a/src/SubcircuitLibrary/ujt/plot_data_i.txt b/src/SubcircuitLibrary/ujt/plot_data_i.txt new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/SubcircuitLibrary/ujt/plot_data_i.txt diff --git a/src/SubcircuitLibrary/ujt/plot_data_v.txt b/src/SubcircuitLibrary/ujt/plot_data_v.txt new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/SubcircuitLibrary/ujt/plot_data_v.txt diff --git a/src/SubcircuitLibrary/ujt/ujt-cache.lib b/src/SubcircuitLibrary/ujt/ujt-cache.lib new file mode 100644 index 00000000..ff75f664 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt-cache.lib @@ -0,0 +1,137 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CCVS +# +DEF CCVS H 0 40 Y Y 1 F N +F0 "H" 0 150 50 H V C CNN +F1 "CCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# NLDS +# +DEF NLDS BB 0 40 Y Y 1 F N +F0 "BB" 0 0 60 H V C CNN +F1 "NLDS" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 0 141 0 1 0 N +X 1 1 0 350 200 D 50 50 1 1 B +X 2 2 0 -350 200 U 50 50 1 1 B +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/ujt/ujt.bak b/src/SubcircuitLibrary/ujt/ujt.bak new file mode 100644 index 00000000..f1171104 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.bak @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:ujt-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 5CF5F733 +P 6650 3400 +F 0 "R3" H 6700 3530 50 0000 C CNN +F 1 "1000k" H 6700 3450 50 0000 C CNN +F 2 "" H 6700 3380 30 0000 C CNN +F 3 "" V 6700 3450 30 0000 C CNN + 1 6650 3400 + 0 1 -1 0 +$EndComp +$Comp +L CCVS H1 +U 1 1 5CF5F77B +P 6150 3350 +F 0 "H1" H 6150 3500 50 0000 C CNN +F 1 "1k" H 5950 3300 50 0000 C CNN +F 2 "" H 6150 3350 60 0000 C CNN +F 3 "" H 6150 3350 60 0000 C CNN + 1 6150 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CF61B3A +P 5150 4700 +F 0 "C1" H 5175 4800 50 0000 L CNN +F 1 "35p" H 5175 4600 50 0000 L CNN +F 2 "" H 5188 4550 30 0000 C CNN +F 3 "" H 5150 4700 60 0000 C CNN + 1 5150 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF6211F +P 4300 4850 +F 0 "R1" H 4350 4980 50 0000 C CNN +F 1 "38.15k" H 4350 4900 50 0000 C CNN +F 2 "" H 4350 4830 30 0000 C CNN +F 3 "" V 4350 4900 30 0000 C CNN + 1 4300 4850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF6218A +P 4550 3650 +F 0 "R2" H 4600 3780 50 0000 C CNN +F 1 "2.518k" H 4600 3700 50 0000 C CNN +F 2 "" H 4600 3630 30 0000 C CNN +F 3 "" V 4600 3700 30 0000 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF6830A +P 4250 4150 +F 0 "U1" H 4300 4250 30 0000 C CNN +F 1 "PORT" H 4250 4150 30 0000 C CNN +F 2 "" H 4250 4150 60 0000 C CNN +F 3 "" H 4250 4150 60 0000 C CNN + 2 4250 4150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF689AD +P 5950 2200 +F 0 "U1" H 6000 2300 30 0000 C CNN +F 1 "PORT" H 5950 2200 30 0000 C CNN +F 2 "" H 5950 2200 60 0000 C CNN +F 3 "" H 5950 2200 60 0000 C CNN + 1 5950 2200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF69586 +P 4600 3000 +F 0 "U1" H 4650 3100 30 0000 C CNN +F 1 "PORT" H 4600 3000 30 0000 C CNN +F 2 "" H 4600 3000 60 0000 C CNN +F 3 "" H 4600 3000 60 0000 C CNN + 3 4600 3000 + 0 1 1 0 +$EndComp +Text Label 5600 4100 0 60 ~ 0 +5 +Text Label 5950 3150 0 60 ~ 0 +4 +Text Label 5950 2600 0 60 ~ 0 +1 +Text Label 6450 3050 0 60 ~ 0 +6 +Text Label 6450 3650 0 60 ~ 0 +0 +$Comp +L NLDS B1 +U 1 1 5CFD2C88 +P 5950 4800 +F 0 "B1" H 5950 4800 60 0000 C CNN +F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60 0000 C CNN +F 2 "" H 5950 4800 60 0000 C CNN +F 3 "" H 5950 4800 60 0000 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +Text Label 5350 5250 0 60 ~ 0 +7 +Text Label 4600 3450 0 60 ~ 0 +3 +Text Label 4250 4500 0 60 ~ 0 +2 +$Comp +L eSim_Diode D1 +U 1 1 5CFF8BB7 +P 5950 2850 +F 0 "D1" H 5950 2950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 2750 50 0000 C CNN +F 2 "" H 5950 2850 60 0000 C CNN +F 3 "" H 5950 2850 60 0000 C CNN + 1 5950 2850 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 3050 6700 3050 +Wire Wire Line + 6700 3050 6700 3200 +Wire Wire Line + 6200 3650 6700 3650 +Wire Wire Line + 5950 2450 5950 2700 +Wire Wire Line + 5950 3000 5950 3300 +Wire Wire Line + 5950 3400 5950 4450 +Wire Wire Line + 5150 4100 5150 4550 +Wire Wire Line + 4600 4100 5950 4100 +Connection ~ 5950 4100 +Wire Wire Line + 5150 4850 5150 5250 +Wire Wire Line + 4250 5250 5950 5250 +Wire Wire Line + 4250 5250 4250 4950 +Wire Wire Line + 4600 4100 4600 3850 +Connection ~ 5150 4100 +Wire Wire Line + 4250 4650 4250 4400 +Wire Wire Line + 4600 3550 4600 3250 +Wire Wire Line + 5950 5250 5950 5150 +Connection ~ 5150 5250 +Wire Wire Line + 6700 3650 6700 3500 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ujt/ujt.cir b/src/SubcircuitLibrary/ujt/ujt.cir new file mode 100644 index 00000000..e0e911d7 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.cir @@ -0,0 +1,18 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 /0 /6 1000k +H1 /6 /0 /4 /5 1k +C1 /5 /7 35p +R1 /7 /2 38.15k +R2 /3 /5 2.518k +U1 /1 /2 /3 PORT +B1 /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) +D1 /1 /4 eSim_Diode + +.end diff --git a/src/SubcircuitLibrary/ujt/ujt.cir.out b/src/SubcircuitLibrary/ujt/ujt.cir.out new file mode 100644 index 00000000..2045c539 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.cir.out @@ -0,0 +1,22 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir + +.include emitter.lib +r3 /0 /6 1000k +* h1 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +* u1 /1 /2 /3 port +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/ujt/ujt.pro b/src/SubcircuitLibrary/ujt/ujt.pro new file mode 100644 index 00000000..24c5e186 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.pro @@ -0,0 +1,44 @@ +update=Tue Jun 11 16:36:40 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName3=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName4=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources +LibName5=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power +LibName6=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot +LibName7=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous +LibName8=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid +LibName9=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital +LibName10=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices +LibName11=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog diff --git a/src/SubcircuitLibrary/ujt/ujt.sch b/src/SubcircuitLibrary/ujt/ujt.sch new file mode 100644 index 00000000..a82bddf7 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:ujt-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 5CF5F733 +P 6650 3400 +F 0 "R3" H 6700 3530 50 0000 C CNN +F 1 "1000k" H 6700 3450 50 0000 C CNN +F 2 "" H 6700 3380 30 0000 C CNN +F 3 "" V 6700 3450 30 0000 C CNN + 1 6650 3400 + 0 1 -1 0 +$EndComp +$Comp +L CCVS H1 +U 1 1 5CF5F77B +P 6150 3350 +F 0 "H1" H 6150 3500 50 0000 C CNN +F 1 "1k" H 5950 3300 50 0000 C CNN +F 2 "" H 6150 3350 60 0000 C CNN +F 3 "" H 6150 3350 60 0000 C CNN + 1 6150 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CF61B3A +P 5150 4700 +F 0 "C1" H 5175 4800 50 0000 L CNN +F 1 "35p" H 5175 4600 50 0000 L CNN +F 2 "" H 5188 4550 30 0000 C CNN +F 3 "" H 5150 4700 60 0000 C CNN + 1 5150 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF6211F +P 4300 4850 +F 0 "R1" H 4350 4980 50 0000 C CNN +F 1 "38.15k" H 4350 4900 50 0000 C CNN +F 2 "" H 4350 4830 30 0000 C CNN +F 3 "" V 4350 4900 30 0000 C CNN + 1 4300 4850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF6218A +P 4550 3650 +F 0 "R2" H 4600 3780 50 0000 C CNN +F 1 "2.518k" H 4600 3700 50 0000 C CNN +F 2 "" H 4600 3630 30 0000 C CNN +F 3 "" V 4600 3700 30 0000 C CNN + 1 4550 3650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF6830A +P 4250 4150 +F 0 "U1" H 4300 4250 30 0000 C CNN +F 1 "PORT" H 4250 4150 30 0000 C CNN +F 2 "" H 4250 4150 60 0000 C CNN +F 3 "" H 4250 4150 60 0000 C CNN + 2 4250 4150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF689AD +P 5950 2200 +F 0 "U1" H 6000 2300 30 0000 C CNN +F 1 "PORT" H 5950 2200 30 0000 C CNN +F 2 "" H 5950 2200 60 0000 C CNN +F 3 "" H 5950 2200 60 0000 C CNN + 1 5950 2200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF69586 +P 4600 3000 +F 0 "U1" H 4650 3100 30 0000 C CNN +F 1 "PORT" H 4600 3000 30 0000 C CNN +F 2 "" H 4600 3000 60 0000 C CNN +F 3 "" H 4600 3000 60 0000 C CNN + 3 4600 3000 + 0 1 1 0 +$EndComp +Text Label 5600 4100 0 60 ~ 0 +5 +Text Label 5950 3150 0 60 ~ 0 +4 +Text Label 5950 2600 0 60 ~ 0 +1 +Text Label 6450 3050 0 60 ~ 0 +6 +Text Label 6450 3650 0 60 ~ 0 +0 +$Comp +L NLDS B1 +U 1 1 5CFD2C88 +P 5950 4800 +F 0 "B1" H 5950 4800 60 0000 C CNN +F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60 0000 C CNN +F 2 "" H 5950 4800 60 0000 C CNN +F 3 "" H 5950 4800 60 0000 C CNN + 1 5950 4800 + 1 0 0 -1 +$EndComp +Text Label 5350 5250 0 60 ~ 0 +7 +Text Label 4600 3450 0 60 ~ 0 +3 +Text Label 4250 4500 0 60 ~ 0 +2 +$Comp +L eSim_Diode D1 +U 1 1 5CFF8BB7 +P 5950 2850 +F 0 "D1" H 5950 2950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 2750 50 0000 C CNN +F 2 "" H 5950 2850 60 0000 C CNN +F 3 "" H 5950 2850 60 0000 C CNN + 1 5950 2850 + 0 1 1 0 +$EndComp +Wire Wire Line + 6200 3050 6700 3050 +Wire Wire Line + 6700 3050 6700 3200 +Wire Wire Line + 6200 3650 6300 3650 +Wire Wire Line + 6300 3650 6700 3650 +Wire Wire Line + 5950 2450 5950 2700 +Wire Wire Line + 5950 3000 5950 3300 +Wire Wire Line + 5950 3400 5950 3850 +Wire Wire Line + 5950 3850 5950 4100 +Wire Wire Line + 5950 4100 5950 4450 +Wire Wire Line + 5150 4100 5150 4550 +Wire Wire Line + 4600 4100 5150 4100 +Wire Wire Line + 5150 4100 5950 4100 +Connection ~ 5950 4100 +Wire Wire Line + 5150 4850 5150 5250 +Wire Wire Line + 4250 5250 5150 5250 +Wire Wire Line + 5150 5250 5950 5250 +Wire Wire Line + 4250 5250 4250 4950 +Wire Wire Line + 4600 4100 4600 3850 +Connection ~ 5150 4100 +Wire Wire Line + 4250 4650 4250 4400 +Wire Wire Line + 4600 3550 4600 3250 +Wire Wire Line + 5950 5250 5950 5150 +Connection ~ 5150 5250 +Wire Wire Line + 6700 3650 6700 3500 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ujt/ujt.sub b/src/SubcircuitLibrary/ujt/ujt.sub new file mode 100644 index 00000000..2fb1db35 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt.sub @@ -0,0 +1,16 @@ +* Subcircuit ujt +.subckt ujt /1 /2 /3 +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir +.include emitter.lib +r3 /0 /6 1000k +* h1 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +* Control Statements + +.ends ujt
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml new file mode 100644 index 00000000..4468b395 --- /dev/null +++ b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/browser/UserManual.py b/src/browser/UserManual.py new file mode 100644 index 00000000..bcff4f97 --- /dev/null +++ b/src/browser/UserManual.py @@ -0,0 +1,17 @@ +from PyQt4 import QtGui +import webbrowser + +class UserManual(QtGui.QWidget): + """ + This class creates Welcome page of eSim. + """ + def __init__(self): + QtGui.QWidget.__init__(self) + + self.vlayout = QtGui.QVBoxLayout() + + self.url = "../browser/pages/User-Manual/eSim.html" + self.test = webbrowser.open("../browser/pages/User-Manual/eSim.html",new=2) + + self.setLayout(self.vlayout) + self.show()
\ No newline at end of file diff --git a/src/browser/UserManual.pyc b/src/browser/UserManual.pyc Binary files differnew file mode 100644 index 00000000..e6e83e3b --- /dev/null +++ b/src/browser/UserManual.pyc diff --git a/src/browser/Welcome.py b/src/browser/Welcome.py new file mode 100644 index 00000000..0f50e153 --- /dev/null +++ b/src/browser/Welcome.py @@ -0,0 +1,19 @@ +from PyQt4 import QtGui,QtCore + + +class Welcome(QtGui.QWidget): + """ + This class creates Welcome page of eSim. + """ + def __init__(self): + QtGui.QWidget.__init__(self) + self.vlayout = QtGui.QVBoxLayout() + + self.browser = QtGui.QTextBrowser() + self.browser.setSource(QtCore.QUrl("../browser/pages/welcome.html")) + self.browser.setOpenExternalLinks(True) + self.browser.setVerticalScrollBarPolicy(QtCore.Qt.ScrollBarAlwaysOff) + + self.vlayout.addWidget(self.browser) + self.setLayout(self.vlayout) + self.show() diff --git a/src/browser/Welcome.pyc b/src/browser/Welcome.pyc Binary files differnew file mode 100644 index 00000000..1e07844a --- /dev/null +++ b/src/browser/Welcome.pyc diff --git a/src/browser/__init__.py b/src/browser/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/browser/__init__.py diff --git a/src/browser/__init__.pyc b/src/browser/__init__.pyc Binary files differnew file mode 100644 index 00000000..685c51aa --- /dev/null +++ b/src/browser/__init__.pyc diff --git a/src/browser/pages/User-Manual/eSim.html b/src/browser/pages/User-Manual/eSim.html new file mode 100644 index 00000000..a2a970e4 --- /dev/null +++ b/src/browser/pages/User-Manual/eSim.html @@ -0,0 +1,3675 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" + "http://www.w3.org/TR/html4/loose.dtd"> +<html > +<head><title></title> +<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> +<meta name="generator" content="TeX4ht (http://www.cse.ohio-state.edu/~gurari/TeX4ht/)"> +<meta name="originator" content="TeX4ht (http://www.cse.ohio-state.edu/~gurari/TeX4ht/)"> +<!-- html --> +<meta name="src" content="esim.tex"> +<meta name="date" content="2015-09-15 14:59:00"> +<link rel="stylesheet" type="text/css" href="esim.css"> +</head><body +> + +<div class="center" +> +<!--l. 1--><p class="noindent" > +<!--l. 2--><p class="noindent" ><span +class="cmbx-12x-x-207">eSim</span><br /><br /> +<span +class="cmbx-12x-x-144">An open source EDA tool for circuit design,</span> +<span +class="cmbx-12x-x-144">simulation, analysis and PCB design</span><br /> + +<img +src="figures/logo-trimmed.png" alt="PIC" +> +<span +class="cmbx-12x-x-144">eSim User Manual</span><br /> +<span +class="cmr-10">version 1.0.0</span><br /> +<span +class="cmbx-10">Prepared By:</span><br /> +<span +class="cmr-10">eSim Team</span><br /> +<span +class="cmr-10">FOSSEE at IIT,Bombay</span> + +<!--l. 17--><p class="noindent" ><img +src="figures/iitblogo.png" alt="PIC" +><br /> +<span +class="cmr-10">Indian Institute of Technology Bombay</span><br /> +<img +src="esim0x.png" alt="○BY:" class="oalign" > <img +src="esim1x.png" alt="○$\" class="oalign" > <img +src="esim2x.png" alt="○=" class="oalign" > <br /> +<span +class="cmr-10">August 2015</span></div> + + + <h2 class="likechapterHead"><a + id="x1-1000"></a>Contents</h2> <div class="tableofcontents"> + <span class="chapterToc" >1 <a +href="#x1-20001" id="QQ2-1-2">Introduction</a></span> +<br /> <span class="chapterToc" >2 <a +href="#x1-30002" id="QQ2-1-3">Installing eSim</a></span> +<br /> <span class="chapterToc" >3 <a +href="#x1-40003" id="QQ2-1-4">Architecture of eSim</a></span> +<br />  <span class="sectionToc" >3.1 <a +href="#x1-50003.1" id="QQ2-1-5">Modules used in eSim</a></span> +<br />   <span class="subsectionToc" >3.1.1 <a +href="#x1-60003.1.1" id="QQ2-1-6">Eeschema</a></span> +<br />   <span class="subsectionToc" >3.1.2 <a +href="#x1-70003.1.2" id="QQ2-1-7">CvPcb</a></span> +<br />   <span class="subsectionToc" >3.1.3 <a +href="#x1-80003.1.3" id="QQ2-1-8">Pcbnew</a></span> +<br />   <span class="subsectionToc" >3.1.4 <a +href="#x1-90003.1.4" id="QQ2-1-9">KiCad to Ngspice converter</a></span> +<br />   <span class="subsectionToc" >3.1.5 <a +href="#x1-100003.1.5" id="QQ2-1-10">Model Builder</a></span> +<br />   <span class="subsectionToc" >3.1.6 <a +href="#x1-110003.1.6" id="QQ2-1-11">Subcircuit Builder</a></span> +<br />   <span class="subsectionToc" >3.1.7 <a +href="#x1-120003.1.7" id="QQ2-1-12">Ngspice</a></span> +<br />  <span class="sectionToc" >3.2 <a +href="#x1-130003.2" id="QQ2-1-13">Work flow of eSim</a></span> +<br /> <span class="chapterToc" >4 <a +href="#x1-140004" id="QQ2-1-15">Getting Started</a></span> +<br />  <span class="sectionToc" >4.1 <a +href="#x1-150004.1" id="QQ2-1-16">eSim Main Window</a></span> +<br />   <span class="subsectionToc" >4.1.1 <a +href="#x1-160004.1.1" id="QQ2-1-17">How to launch eSim in Ubuntu?</a></span> +<br />   <span class="subsectionToc" >4.1.2 <a +href="#x1-170004.1.2" id="QQ2-1-19">Main-GUI</a></span> +<br /> <span class="chapterToc" >5 <a +href="#x1-280005" id="QQ2-1-33">Schematic Creation</a></span> +<br />  <span class="sectionToc" >5.1 <a +href="#x1-290005.1" id="QQ2-1-34">Familiarizing the Schematic Editor interface</a></span> +<br />   <span class="subsectionToc" >5.1.1 <a +href="#x1-300005.1.1" id="QQ2-1-36">Top menu bar</a></span> +<br />   <span class="subsectionToc" >5.1.2 <a +href="#x1-310005.1.2" id="QQ2-1-38">Top toolbar</a></span> +<br />   <span class="subsectionToc" >5.1.3 <a +href="#x1-320005.1.3" id="QQ2-1-40">Toolbar on the right</a></span> +<br />   <span class="subsectionToc" >5.1.4 <a +href="#x1-330005.1.4" id="QQ2-1-42">Toolbar on the left</a></span> +<br />   <span class="subsectionToc" >5.1.5 <a +href="#x1-340005.1.5" id="QQ2-1-44">Hotkeys</a></span> +<br />  <span class="sectionToc" >5.2 <a +href="#x1-350005.2" id="QQ2-1-45">Schematic creation for simulation</a></span> +<br />   <span class="subsectionToc" >5.2.1 <a +href="#x1-360005.2.1" id="QQ2-1-47">Selection and placement of components</a></span> +<br />   <span class="subsectionToc" >5.2.2 <a +href="#x1-370005.2.2" id="QQ2-1-51">Wiring the circuit</a></span> +<br />   <span class="subsectionToc" >5.2.3 <a +href="#x1-380005.2.3" id="QQ2-1-53">Assigning values to components</a></span> +<br />   <span class="subsectionToc" >5.2.4 <a +href="#x1-390005.2.4" id="QQ2-1-55">Annotation and ERC</a></span> +<br />   <span class="subsectionToc" >5.2.5 <a +href="#x1-400005.2.5" id="QQ2-1-59">Netlist generation</a></span> +<br /> <span class="chapterToc" >6 <a +href="#x1-410006" id="QQ2-1-61">PCB Design</a></span> +<br />  <span class="sectionToc" >6.1 <a +href="#x1-420006.1" id="QQ2-1-62">Schematic creation for PCB design</a></span> +<br />   <span class="subsectionToc" >6.1.1 <a +href="#x1-430006.1.1" id="QQ2-1-64">Netlist generation for PCB</a></span> + +<br />   <span class="subsectionToc" >6.1.2 <a +href="#x1-440006.1.2" id="QQ2-1-66">Mapping of components using Footprint Editor</a></span> +<br />   <span class="subsectionToc" >6.1.3 <a +href="#x1-450006.1.3" id="QQ2-1-67">Familiarising the Footprint Editor tool</a></span> +<br />   <span class="subsectionToc" >6.1.4 <a +href="#x1-470006.1.4" id="QQ2-1-71">Viewing footprints in 2D and 3D</a></span> +<br />   <span class="subsectionToc" >6.1.5 <a +href="#x1-480006.1.5" id="QQ2-1-75">Mapping of components in the RC circuit</a></span> +<br />  <span class="sectionToc" >6.2 <a +href="#x1-490006.2" id="QQ2-1-77">Creation of PCB layout</a></span> +<br />   <span class="subsectionToc" >6.2.1 <a +href="#x1-500006.2.1" id="QQ2-1-78">Familiarizing the Layout Editor tool</a></span> +<br />   <span class="subsectionToc" >6.2.2 <a +href="#x1-520006.2.2" id="QQ2-1-82">Hotkeys</a></span> +<br />   <span class="subsectionToc" >6.2.3 <a +href="#x1-530006.2.3" id="QQ2-1-83">PCB design example using RC circuit</a></span> +<br /> <span class="chapterToc" >7 <a +href="#x1-540007" id="QQ2-1-98">Model Editor</a></span> +<br />  <span class="sectionToc" >7.1 <a +href="#x1-550007.1" id="QQ2-1-100">Creating New Model Library </a></span> +<br />  <span class="sectionToc" >7.2 <a +href="#x1-560007.2" id="QQ2-1-105">Editing Current Model Library</a></span> +<br />  <span class="sectionToc" >7.3 <a +href="#x1-570007.3" id="QQ2-1-107">Uploading external .lib file to eSim repository</a></span> +<br /> <span class="chapterToc" >8 <a +href="#x1-580008" id="QQ2-1-108">SubCircuit Builder</a></span> +<br />  <span class="sectionToc" >8.1 <a +href="#x1-590008.1" id="QQ2-1-110">Creating a SubCircuit</a></span> +<br />  <span class="sectionToc" >8.2 <a +href="#x1-600008.2" id="QQ2-1-118">Edit a Subcircuit</a></span> +<br /> <span class="chapterToc" >9 <a +href="#x1-610009" id="QQ2-1-119">Solved Examples</a></span> +<br />  <span class="sectionToc" >9.1 <a +href="#x1-620009.1" id="QQ2-1-120">Solved Examples</a></span> +<br />   <span class="subsectionToc" >9.1.1 <a +href="#x1-630009.1.1" id="QQ2-1-121">Basic RC Circuit</a></span> +<br />   <span class="subsectionToc" >9.1.2 <a +href="#x1-660009.1.2" id="QQ2-1-136">Half Wave Rectifier</a></span> +<br />   <span class="subsectionToc" >9.1.3 <a +href="#x1-690009.1.3" id="QQ2-1-143">Precision Rectifier</a></span> +<br />   <span class="subsectionToc" >9.1.4 <a +href="#x1-720009.1.4" id="QQ2-1-150">Inverting Amplifier</a></span> +<br />   <span class="subsectionToc" >9.1.5 <a +href="#x1-750009.1.5" id="QQ2-1-157">Half Adder Example</a></span> +<br /> <span class="chapterToc" > <a +href="#Q1-1-166">References </a></span> + </div> + + + <h2 class="chapterHead"><span class="titlemark">Chapter 1</span><br /><a + id="x1-20001"></a>Introduction</h2> Electronic systems are an integral part of human life. They have +simplified our lives to a great extent. Starting from small systems made of a few +discrete components to the present day integrated circuits (ICs) with millions of +logic gates, electronic systems have undergone a sea change. As a result, design of +electronic systems too have become extremely difficult and time consuming. Thanks to +a host of computer aided design tools, we have been able to come up with quick +and efficient designs. These are called <span +class="cmtt-10x-x-109">Electronic Design Automation </span>or <span +class="cmtt-10x-x-109">EDA</span> +<a + id="dx1-2001"></a>tools. +<!--l. 20--><p class="noindent" >Let us see the steps involved in EDA.<a + id="dx1-2002"></a> In the first stage, the specifications of the system are +laid out. These specifications are then converted to a design. The design could be in +the form of a circuit schematic, logical description using an HDL language, etc. +The design is then simulated and re-designed, if needed, to achieve the desired +results. Once simulation achieves the specifications, the design is either converted to +a PCB, a chip layout, or ported to an FPGA. The final product is again tested +for specifications. The whole cycle is repeated until desired results are obtained +<span class="cite"> [<a +href="#Xeda">9</a>]</span>. +<!--l. 31--><p class="indent" > A person who builds an electronic system has to first design the circuit, produce a virtual +representation of it through a schematic for easy comprehension, simulate it and finally +convert it into a Printed Circuit Board (PCB). <a + id="dx1-2003"></a>There are various tools available that will help +us do this. Some of the popular EDA tools are those of <span +class="cmtt-10x-x-109">Cadence</span>, <span +class="cmtt-10x-x-109">Synopys</span>, <span +class="cmtt-10x-x-109">Mentor Graphics</span> +and <span +class="cmtt-10x-x-109">Xilinx</span>. Although these are fairly comprehensive and high end, their licenses are +expensive, being proprietary. +<!--l. 40--><p class="indent" > There are some free and open source EDA tools like <span +class="cmtt-10x-x-109">gEDA</span>, <span +class="cmtt-10x-x-109">KiCad </span>and <span +class="cmtt-10x-x-109">Ngspice</span>. The main +drawback of these open source tools is that they are not comprehensive. Some of them are +capable of PCB design (e.g. <span +class="cmtt-10x-x-109">KiCad</span>) while some of them are capable of performing simulations +(e.g. <span +class="cmtt-10x-x-109">gEDA</span>). To the best of our knowledge, there is no open source software that can perform +circuit design, simulation and layout design together. eSim is capable of doing all of the +above. +<!--l. 49--><p class="indent" > eSim is a free and open source EDA tool. It is an acronym for <span +class="cmbx-10x-x-109">E</span>lectronics <span +class="cmbx-10x-x-109">Sim</span>ulation. +eSim is created using open source software packages, such as KiCad, Ngspice and Python. <a + id="dx1-2004"></a><a + id="dx1-2005"></a> +<a + id="dx1-2006"></a>Using eSim, one can create circuit schematics, perform simulations and design PCB +layouts. It can create or edit new device models, and create or edit subcircuits for +simulation. +<!--l. 57--><p class="indent" > Because of these reasons, eSim is expected to be useful for students, teachers and other +professionals who would want to study and/or design electronic systems. eSim is also useful +for entrepreneurs and small scale enterprises who do not have the capability to invest in +heavily priced proprietary tools. +<!--l. 63--><p class="indent" > This book introduces eSim to the reader and illustrates all the features of eSim with +examples. Chapter <a +href="#x1-30002">2<!--tex4ht:ref: chap2 --></a> gives step by step instructions to install eSim on a typical computer +system and to validate the installation. The software architecture of eSim is presented in +Chapter <a +href="#x1-40003">3<!--tex4ht:ref: chap3 --></a>. Chapter <a +href="#x1-140004">4<!--tex4ht:ref: chap4 --></a> gets the user started with eSim. It takes them through a tour + +of eSim with the help of a simple RC circuit example. Chapter 5 illustrates how +to simulate circuits. Chapter 6 explains PCB design using eSim, in detail. The +advanced features of eSim such as Model Builder covered in Chapter 7 and Sub +circuiting is covered in Chapter 8. Chapter <a +href="#x1-610009">9<!--tex4ht:ref: chap5 --></a> illustrates how to use eSim for solving +problems. +<!--l. 73--><p class="indent" > The following convention has been adopted throughout this manual.All the +menu names, options under each menu item, tool names, certain points to be noted, +etc., are given in <span +class="cmti-10x-x-109">italics</span>. Some keywords, names of certain windows/dialog boxes, +names of some files/projects/folders, messages displayed during an activity, names +of websites, component references, etc., are given in <span +class="cmtt-10x-x-109">typewriter </span>font. Some key +presses, e.g. <span +class="cmtt-10x-x-109">Enter </span>key, <span +class="cmtt-10x-x-109">F1 </span>key, <span +class="cmtt-10x-x-109">y </span>for yes, etc., are also mentioned in <span +class="cmtt-10x-x-109">typewriter</span> +font. + + <h2 class="chapterHead"><span class="titlemark">Chapter 2</span><br /><a + id="x1-30002"></a>Installing eSim</h2> + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate"><span +class="cmbx-10x-x-109">eSim installation in Ubuntu:</span><br +class="newline" />After downloading the zip file from https://github.com/FOSSEE/eSim to a local + directory unpack it using:<br +class="newline" />      <span +class="cmbx-10x-x-109">$ unzip eSim.zip </span><br +class="newline" />Now change directories in to the top-level source directory (where this INSTALL + file can be found). + <!--l. 13--><p class="noindent" >To install eSim and other dependecies run the following command. <br +class="newline" />      <span +class="cmbx-10x-x-109">$ ../install-linux.sh –install </span><br +class="newline" />Above script will install eSim along with dependencies. + <!--l. 19--><p class="noindent" >eSim will be installed to /opt/eSim + <!--l. 21--><p class="noindent" >To run eSim you can directly run it from terminal as <br +class="newline" />      <span +class="cmbx-10x-x-109">$ esim </span><br +class="newline" />or you can double click on eSim icon created on desktop after installation.</dd></dl> + + <h2 class="chapterHead"><span class="titlemark">Chapter 3</span><br /><a + id="x1-40003"></a>Architecture of eSim</h2> +<!--l. 6--><p class="noindent" >eSim is a CAD <a + id="dx1-4001"></a>tool that helps electronic system designers to design, test and analyse their +circuits. But the important feature of this tool is that it is open source and hence the user can +modify the source as per his/her need. The software provides a generic, modular and +extensible platform for experiment with electronic circuits. This software runs on all +Ubuntu Linux distributions and some flavours of Windows. It uses <span +class="cmtt-10x-x-109">Python</span>, <span +class="cmtt-10x-x-109">KiCad </span>and +<span +class="cmtt-10x-x-109">Ngspice</span>. +<!--l. 13--><p class="indent" > The objective behind the development of eSim is to provide an open source EDA solution +for electronics and electrical engineers. The software should be capable of performing +schematic creation, PCB design and circuit simulation (analog, digital and mixed signal). It +should provide facilities to create new models and components. The architecture of eSim has +been designed by keeping these objectives in mind. + <h3 class="sectionHead"><span class="titlemark">3.1 </span> <a + id="x1-50003.1"></a>Modules used in eSim</h3> +<!--l. 21--><p class="noindent" >Various open-source tools have been used for the underlying build-up of eSim. In this section +we will give a brief idea about all the modules used in eSim. +<!--l. 23--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.1 </span> <a + id="x1-60003.1.1"></a>Eeschema</h4> +<a + id="dx1-6001"></a> +<a + id="dx1-6002"></a> +<!--l. 24--><p class="noindent" >Eeschema is an integrated software where all functions of circuit drawing, control, layout, +library management and access to the PCB design software are carried out. It is the +schematic editor tool used in KiCad <span class="cite"> [<a +href="#Xeeschema">11</a>]</span>. Eeschema is intended to work with PCB layout +software such as Pcbnew. It provides netlist that describes the electrical connections of the +PCB. Eeschema also integrates a component editor which allows the creation, editing and +visualization of components. It also allows the user to effectively handle the symbol +libraries i.e; import, export, addition and deletion of library components. Eeschema +also integrates the following additional but essential functions needed for a modern +schematic capture software: <a + id="x1-6003r1"></a>1. Design rules check <a + id="dx1-6004"></a>(<span +class="cmtt-10x-x-109">DRC</span>) for the automatic control of +incorrect connections and inputs of components left unconnected. <a + id="x1-6005r2"></a>2. Generation of +layout files in <span +class="cmtt-10x-x-109">POSTSCRIPT</span> <a + id="dx1-6006"></a>or <span +class="cmtt-10x-x-109">HPGL</span> <a + id="dx1-6007"></a>format. <a + id="x1-6008r3"></a>3. Generation of layout files printable via +printer. <a + id="x1-6009r4"></a>4. Bill of material generation. <a + id="x1-6010r5"></a>5. Netlist generation for PCB layout or for +simulation. +This module is indicated by the label 1 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 45--><p class="indent" > As Eeschema is originally intended for PCB Design, there are no fictitious + +components<span class="footnote-mark"><a +href="esim2.html#fn1x3"><sup class="textsuperscript">1</sup></a></span><a + id="x1-6011f1"></a> +such as voltage or current sources. Thus, we have added a new library for different types of +voltage and current sources such as sine, pulse and square wave. We have also built a library +which gives printing and plotting solutions. This extension, developed by us for eSim, is +indicated by the label 2 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. + <h4 class="subsectionHead"><span class="titlemark">3.1.2 </span> <a + id="x1-70003.1.2"></a>CvPcb</h4> +<a + id="dx1-7001"></a> +<!--l. 58--><p class="noindent" >CvPcb is a tool that allows the user to associate components in the schematic to component +footprints when designing the printed circuit board. CvPcb is the footprint editor tool in +KiCad <span class="cite"> [<a +href="#Xeeschema">11</a>]</span>. Typically the netlist file generated by Eeschema does not specify which printed +circuit board footprint is associated with each component in the schematic. However, this is +not always the case as component footprints can be associated during schematic capture by +setting the component’s footprint field. CvPcb provides a convenient method of associating +footprints to components. It provides footprint list filtering, footprint viewing, and 3D +component model viewing to help ensure that the correct footprint is associated with each +component. Components can be assigned to their corresponding footprints manually or +automatically by creating equivalence files. Equivalence files are look up tables +associating each component with its footprint. This interactive approach is simpler +and less error prone than directly associating footprints in the schematic editor. +This is because CvPcb not only allows automatic association, but also allows to +see the list of available footprints and displays them on the screen to ensure the +correct footprint is being associated. This module is indicated by the label 3 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 80--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.3 </span> <a + id="x1-80003.1.3"></a>Pcbnew</h4> +<a + id="dx1-8001"></a> +<!--l. 81--><p class="noindent" >Pcbnew is a powerful printed circuit board software tool. It is the layout editor tool +used in KiCad <span class="cite"> [<a +href="#Xeeschema">11</a>]</span>. It is used in association with the schematic capture software +Eeschema, which provides the netlist. Netlist describes the electrical connections of +the circuit. CvPcb is used to assign each component, in the netlist produced by +Eeschema, to a module that is used by Pcbnew. The features of Pcbnew are given +below: + + <ul class="itemize1"> + <li class="itemize">It manages libraries of modules. Each module is a drawing of the physical + component including its footprint<a + id="dx1-8002"></a> - the layout of pads providing connections to the + component. The required modules are automatically loaded during the reading of + the netlist produced by CvPcb. + </li> + <li class="itemize">Pcbnew integrates automatically and immediately any circuit modification by + removal of any erroneous tracks, addition of new components, or by modifying + any value (and under certain conditions any reference) of old or new modules, + according to the electrical connections appearing in the schematic. + </li> + <li class="itemize">This tool provides a rats nest display, a hairline connecting the pads of modules + connected on the schematic. These connections move dynamically as track and + module movements are made. + </li> + <li class="itemize">It has an active Design Rules Check (<span +class="cmtt-10x-x-109">DRC</span>) which automatically indicates any error + of track layout in real time. + </li> + <li class="itemize">It automatically generates a copper plane, with or without thermal breaks on the + pads. + </li> + <li class="itemize">It has a simple but effective auto router to assist in the production of the + circuit. An export/import in <span +class="cmtt-10x-x-109">SPECCTRA </span>dsn format allows to use more advanced + auto-routers. + </li> + <li class="itemize">It provides options specifically for the production of ultra high frequency circuits + (such as pads of trapezoidal and complex form, automatic layout of coils on the + printed circuit). + </li> + <li class="itemize">Pcbnew displays the elements (tracks, pads, texts, drawings and more) as actual size + and according to personal preferences such as: + <ul class="itemize2"> + <li class="itemize">display in full or outline. + </li> + <li class="itemize">display the track/pad clearance.</li></ul> + + </li></ul> +<!--l. 121--><p class="noindent" >This module is indicated by the label 4 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. + <h4 class="subsectionHead"><span class="titlemark">3.1.4 </span> <a + id="x1-90003.1.4"></a>KiCad to Ngspice converter</h4> +<!--l. 124--><p class="noindent" >We can provide analysis parameters, and the source details through this module. It also +allows us to add and edit the device models and subcircuits, included in the circuit +schematic. Finally, this module facilitates the conversion of KiCad netlist to Ngspice +compatible ones. It is developed by us for eSim and it is indicated by the label 7 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 149--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.5 </span> <a + id="x1-100003.1.5"></a>Model Builder</h4> +<a + id="dx1-10001"></a> +<!--l. 150--><p class="noindent" >This tool provides the facility to define a new model for devices such as, <a + id="x1-10002r1"></a>1. Diode <a + id="x1-10003r2"></a>2. Bipolar +Junction Transistor (BJT) <a + id="x1-10004r3"></a>3. Metal Oxide Semiconductor Field Effect Transistor +(MOSFET) <a + id="x1-10005r4"></a>4. Junction Field Effect Transistor (JFET) <a + id="x1-10006r5"></a>5. IGBT and <a + id="x1-10007r6"></a>6. Magnetic +core. +This module also helps edit existing models. It is developed by us for eSim and it is indicated +by the label 5 in Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 164--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.6 </span> <a + id="x1-110003.1.6"></a>Subcircuit Builder</h4> +<a + id="dx1-11001"></a> +<!--l. 164--><p class="noindent" >This module allows the user to create a subcircuit for a component. Once the subcircuit for a +component is created, the user can use it in other circuits. It has the facility to define new +components such as, Op-amps and IC-555. This component also helps edit existing +subcircuits. This module is developed by us for eSim and it is indicated by the label 6 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 172--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">3.1.7 </span> <a + id="x1-120003.1.7"></a>Ngspice</h4> +<a + id="dx1-12001"></a> +<!--l. 173--><p class="noindent" >Ngspice is a general purpose circuit simulation program for nonlinear dc, nonlinear transient, +and linear ac analysis <span class="cite"> [<a +href="#Xngspice-web">12</a>]</span>. Circuits may contain resistors, capacitors, inductors, mutual +inductors, independent voltage and current sources, four types of dependent sources, lossless +and lossy transmission lines (two separate implementations), switches, uniform + +distributed RC lines, and the five most common semiconductor devices: diodes, +<a + id="dx1-12002"></a>BJTs, <a + id="dx1-12003"></a>JFETs, MESFETs, and MOSFET. <a + id="dx1-12004"></a>This module is indicated by the label 9 in +Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a>. +<!--l. 184--><p class="noindent" > + <h3 class="sectionHead"><span class="titlemark">3.2 </span> <a + id="x1-130003.2"></a>Work flow of eSim</h3> +<!--l. 185--><p class="noindent" >Fig. <a +href="#x1-130011">3.1<!--tex4ht:ref: blockd --></a> shows the work flow in eSim. The block diagram consists of mainly three +parts: + <ul class="itemize1"> + <li class="itemize">Schematic Editor + </li> + <li class="itemize">PCB Layout Editor + </li> + <li class="itemize">Circuit Simulators</li></ul> +<!--l. 193--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-130011"></a> + + +<!--l. 196--><p class="noindent" ><img +src="figures/blockdiagram.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 3.1: </span><span +class="content">Work flow in eSim. (Boxes with dotted lines denote the modules developed +in this work).</span></div><!--tex4ht:label?: x1-130011 --> + +<!--l. 201--><p class="indent" > </div><hr class="endfigure"> +<!--l. 203--><p class="indent" > Here we explain the role of each block in designing electronic systems. Circuit design is the +first step in the design of an electronic circuit. Generally a circuit diagram is drawn on a +paper, and then entered into a computer using a schematic editor. Eeschema is the schematic +editor for eSim. Thus all the functionalities of Eeschema are naturally available in eSim. +<a + id="dx1-13002"></a> +<!--l. 210--><p class="indent" > Libraries for components, explicitly or implicitly supported by Ngspice, have been created +using the features of Eeschema. As Eeschema is originally intended for PCB design, there are +no fictitious components such as voltage or current sources. Thus, a new library for different +types of voltage and current sources such as sine, pulse and square wave, has been added in +eSim. A library which gives the functionality of printing and plotting has also been +created. +<!--l. 219--><p class="indent" > The schematic editor provides a netlist file, which describes the electrical connections of +the design. In order to create a PCB layout, physical components are required to be mapped +into their footprints. To perform component to footprint mapping, CvPcb is used. Footprints +have been created for the components in the newly created libraries. Pcbnew is used to draw +a PCB layout. +<!--l. 227--><p class="indent" > After designing a circuit, it is essential to check the integrity of the circuit design. In the +case of large electronic circuits, breadboard testing is impractical. In such cases, electronic +system designers rely heavily on simulation. The accuracy of the simulation results can be +increased by accurate modeling of the circuit elements. Model Builder provides the facility to +define a new model for devices and edit existing models. Complex circuit elements can be +created by hierarchical modeling. Subcircuit Builder provides an easy way to create a +subcircuit. +<!--l. 238--><p class="indent" > The netlist generated by Schematic Editor cannot be directly used for simulation due to +compatibility issues. Netlist Converter converts it into Ngspice compatible format. The +type of simulation to be performed and the corresponding options are provided +through a graphical user interface (GUI). This is called KiCad to Ngspice Converter in +eSim. +<!--l. 245--><p class="indent" > eSim uses Ngspice for analog, digital, mixed-level/mixed-signal circuit simulation. Ngspice +is based on three open source software packages<span class="cite"> [<a +href="#Xspice">14</a>]</span>: + <ul class="itemize1"> + <li class="itemize">Spice3f5 (analog circuit simulator) + </li> + <li class="itemize">Cider1b1 (couples Spice3f5 circuit simulator to DSIM device simulator) + </li> + <li class="itemize">Xspice (code modeling support and simulation of digital components through an + event driven algorithm)</li></ul> +<!--l. 253--><p class="noindent" >It is a part of gEDA <a + id="dx1-13003"></a>project. Ngspice is capable of simulating devices with BSIM, <a + id="dx1-13004"></a>EKV, HICUM, <a + id="dx1-13005"></a><a + id="dx1-13006"></a> + +HiSim, <a + id="dx1-13007"></a>PSP, <a + id="dx1-13008"></a>and PTM <a + id="dx1-13009"></a>models. It is widely used due to its accuracy even for the latest +technology devices. + + <h2 class="chapterHead"><span class="titlemark">Chapter 4</span><br /><a + id="x1-140004"></a>Getting Started</h2> +<!--l. 5--><p class="noindent" >In this chapter we will get started with eSim. We will run through the various options +available with an example circuit. Referring to this chapter will make one familiar with +eSim and will help plan the project before actually designing a circuit. Lets get +started. + <h3 class="sectionHead"><span class="titlemark">4.1 </span> <a + id="x1-150004.1"></a>eSim Main Window</h3> +<!--l. 12--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">4.1.1 </span> <a + id="x1-160004.1.1"></a>How to launch eSim in Ubuntu?</h4> +<!--l. 13--><p class="noindent" >After installation is completed, to launch eSim 1. Go to terminal.<br +class="newline" />2. Type <span +class="cmbx-10x-x-109">esim </span>and hit enter.<br +class="newline" />The first window that appears is workspace dialog as shown in Fig. <a +href="#x1-160011">4.1<!--tex4ht:ref: workspace --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-160011"></a> + + +<!--l. 19--><p class="noindent" ><img +src="figures/workspace.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.1: </span><span +class="content">eSim-Workspace</span></div><!--tex4ht:label?: x1-160011 --> + +<!--l. 22--><p class="indent" > </div><hr class="endfigure"> +<!--l. 24--><p class="indent" > The default workspace is eSim-Workspace under home directory. To create new workspace +use <span +class="cmti-10x-x-109">browse </span>option. + <h4 class="subsectionHead"><span class="titlemark">4.1.2 </span> <a + id="x1-170004.1.2"></a>Main-GUI</h4> +<!--l. 27--><p class="noindent" >The main GUI window of eSim is as shown in Fig. <a +href="#x1-170012">4.2<!--tex4ht:ref: maingui --></a> <hr class="figure"><div class="figure" +> + +<a + id="x1-170012"></a> + + +<!--l. 30--><p class="noindent" ><img +src="figures/maingui.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.2: </span><span +class="content">eSim Main GUI</span></div><!--tex4ht:label?: x1-170012 --> + +<!--l. 33--><p class="indent" > </div><hr class="endfigure"> +<!--l. 34--><p class="indent" > The eSim main window consists of the following symbols. + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate">Toolbar + </dd><dt class="enumerate"> + 2. </dt><dd +class="enumerate">Menubar + </dd><dt class="enumerate"> + 3. </dt><dd +class="enumerate">Project explorer + </dd><dt class="enumerate"> + 4. </dt><dd +class="enumerate">Dockarea + </dd><dt class="enumerate"> + 5. </dt><dd +class="enumerate">Console area</dd></dl> + <h5 class="subsubsectionHead"><a + id="x1-180004.1.2"></a>Toolbar</h5> +<!--l. 44--><p class="noindent" ><hr class="figure"><div class="figure" +> + +<a + id="x1-180013"></a> + + +<!--l. 46--><p class="noindent" ><img +src="figures/guitoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.3: </span><span +class="content">Toolbar</span></div><!--tex4ht:label?: x1-180013 --> + +<!--l. 49--><p class="noindent" ></div><hr class="endfigure"> + <ul class="itemize1"> + <li class="itemize">Open Schematic: The first tool on the toolbar i.e. <span +class="cmti-10x-x-109">Schematic Editor</span><a + id="dx1-18002"></a>. Clicking on + this button will open Eeschema, the KiCad schematic editor. + </li> + <li class="itemize">Convert KiCad to Ngspice: This converter converts KiCad spice netlist into + Ngspice compatible netlist. The KiCad to Ngspice window consists of total five + tabs as namely <span +class="cmti-10x-x-109">Analysis, Device Model, Source Details, Model Library, Subcircuits</span>. + Once the values have been entered, press the <span +class="cmtt-10x-x-109">Convert </span>key. It will generate + <span +class="cmtt-10x-x-109">.cir.out </span>file in the same project directory.<br +class="newline" />Note that <span +class="cmti-10x-x-109">KiCad to Ngspice Converter </span>can only be used if current project has + created the KiCad spice netlist file <span +class="cmtt-10x-x-109">.cir</span>.<br +class="newline" /> + <!--l. 62--><p class="noindent" >The details of tabs under KiCad to Ngspice converter are as follows:<br +class="newline" /> + <h5 class="subsubsectionHead"><a + id="x1-190004.1.2"></a>Analysis</h5> + <!--l. 65--><p class="noindent" >This feature helps the user to perform different types of analysis such as Operating + point analysis, <a + id="dx1-19001"></a>DC analysis, <a + id="dx1-19002"></a>AC analysis, <a + id="dx1-19003"></a>transient analysis. <a + id="dx1-19004"></a>It has the facility + to + <ul class="itemize2"> + <li class="itemize">Insert type of analysis such as AC or DC or Transient + </li> + <li class="itemize">Insert values for analysis</li></ul> + <!--l. 73--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-200004.1.2"></a>Source Details</h5> + <!--l. 74--><p class="noindent" >eSim sources are added from <span +class="cmtt-10x-x-109">eSim</span><span +class="cmtt-10x-x-109">_Sources </span>library. Source such as <span +class="cmti-10x-x-109">SINE, AC, DC,</span> + <span +class="cmti-10x-x-109">PULSE </span>are in this library. The parameter values to all the sources added in the + shcematic can be given through ’Source Details’. + + <!--l. 76--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-210004.1.2"></a>Ngspice Model</h5> + <!--l. 77--><p class="noindent" >Ngspice has in built model such as <span +class="cmti-10x-x-109">flipflop(D,SR,JK,T),gain,summer </span>etc. which can be + utilised while building a circuit. eSim allows to add and modify Ngspice model + parameter through Ngspice Model tab. + <!--l. 80--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-220004.1.2"></a>Device Modeling</h5> + <!--l. 81--><p class="noindent" >Devices like <span +class="cmti-10x-x-109">Diode, JFET, MOSFET, IGBT, MOS </span>etc used in the circuit can be + modeled using device model libraries. eSim also provides editing and adding new model + libraries. While converting KiCad to Ngspice, these library files are added to the + corresponding devices used in the circuit. + <!--l. 83--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-230004.1.2"></a>Subcircuits</h5> + <!--l. 84--><p class="noindent" >Subcircuits are circuits within circuit. Subcircuiting helps to reuse the parts of the + circuits. The subcircuits in the main circuits are added using this facility. Also, eSim + provides us with the facility to edit already existing subcircuits. + </li> + <li class="itemize">Simulation: The netlist generated using the <span +class="cmti-10x-x-109">KiCad to Ngspice </span>converter is + simulated using simulation button. Clicking on the <span +class="cmti-10x-x-109">Simulation </span>button will run + the Ngspice simulation for current project. Python plotting window will open, as + shown in Fig. <a +href="#x1-230014">4.4<!--tex4ht:ref: simulation-op --></a>. It shows the output waveform of current project. In the + Ngspice tab we can view the output plotted by Ngspice. <hr class="figure"><div class="figure" +><a + id="x1-230014"></a> <img +src="figures/simulation-op.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 4.4: </span><span +class="content">Simulation Output in Python Plotting Window</span></div><!--tex4ht:label?: x1-230014 --> + <!--l. 94--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Foot Print Editor: Clicking on the <span +class="cmti-10x-x-109">Footprint Editor </span>tool will open the <span +class="cmtt-10x-x-109">CvPcb</span> + <a + id="dx1-23002"></a>window. This window will ideally open the .net file for the current project. So, + before using this tool, one should have the netlist for PCB design (a .net + file). + </li> + <li class="itemize">PCB Layout: Clicking on the <span +class="cmti-10x-x-109">Layout Editor </span>tool will open <span +class="cmtt-10x-x-109">Pcbnew</span><a + id="dx1-23003"></a>, the layout editor + + used in eSim. In this window, one will create the PCB. It involves laying + tracks and vias, performing optimum routing of tracks, creating one or more + copper layers for PCB, etc. It will be saved as a <span +class="cmtt-10x-x-109">.brd </span>file in the current project + directory. + </li> + <li class="itemize">Model Editor: eSim also gives an option to re-configure the model library of a device. It + facilitates the user to change model library of devices such as diode, transistor, + MOSFET, etc. + </li> + <li class="itemize">Subcircuit: eSim has an option to build subcircuits. The subcircuits can again have + components having subcircuits and so on. This enables users to build commonly used + circuits as subcircuits and then use it across circuits. For example, one can build a 12 + Volt power supply as a subcircuit and then use it as just a single component across + circuits without having to recreate it. Clicking on <span +class="cmti-10x-x-109">Subcircuit Builder </span>tool will allow one + to edit or create a subcircuit. + <!--l. 126--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-240004.1.2"></a>Menubar</h5> + <ul class="itemize2"> + <li class="itemize">New Project: New projects are created in the eSim-workspace. When this + menu is selected, a new window opens up with <span +class="cmtt-10x-x-109">Enter Project name </span>field. + Type the name of the new project and click on OK. A project directory will + be created in eSim-Workspace. The name of this folder will be the same as + that of the project created. Make sure project name does not have any spaces. + </li> + <li class="itemize">Open Project: This opens the file dialog of defalut workspace where the + projects are stored. The project can be selected which is then added in the + project explorer. + </li> + <li class="itemize">Exit: This button closes the project window and exits. + </li> + <li class="itemize">Help: It opens user manual in the dockarea.</li></ul> + + <!--l. 141--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-250004.1.2"></a>Project Explorer</h5> + <!--l. 142--><p class="noindent" >Project explorer has tree of all the project previously added in it. On right clicking the + project we can simply remove or refresh the project in the explorer. Also on + double/right clicking, the project file can be opened in the text editor which can then be + edited. + <!--l. 145--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-260004.1.2"></a>Dockarea</h5> + <!--l. 146--><p class="noindent" >This area is used to open the following windows. + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate">KiCad to Ngspice converter + </dd><dt class="enumerate"> + 2. </dt><dd +class="enumerate">Ngspice plotting + </dd><dt class="enumerate"> + 3. </dt><dd +class="enumerate">Python plotting + </dd><dt class="enumerate"> + 4. </dt><dd +class="enumerate">Model builder + </dd><dt class="enumerate"> + 5. </dt><dd +class="enumerate">Subcircuit builder</dd></dl> + <!--l. 155--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-270004.1.2"></a>Console Area</h5> + <!--l. 156--><p class="noindent" >Console area provides information about the activity done in current project. + </li></ul> + + <h2 class="chapterHead"><span class="titlemark">Chapter 5</span><br /><a + id="x1-280005"></a>Schematic Creation</h2> The first step in the design of an electronic system is the +design of its circuit. This circuit is usually created using a <span +class="cmtt-10x-x-109">Schematic Editor</span><a + id="dx1-28001"></a> and is called a +<span +class="cmtt-10x-x-109">Schematic</span>. <a + id="dx1-28002"></a>eSim uses <span +class="cmtt-10x-x-109">Eeschema</span> <a + id="dx1-28003"></a>as its schematic editor. Eeschema is the schematic editor of +KiCad. <a + id="dx1-28004"></a>It is a powerful schematic editor software. It allows the creation and modification of +components and symbol libraries and supports multiple hierarchical layers of printed circuit +design. + <h3 class="sectionHead"><span class="titlemark">5.1 </span> <a + id="x1-290005.1"></a>Familiarizing the Schematic Editor interface</h3> +<!--l. 22--><p class="noindent" >Fig. <a +href="#x1-290011">5.1<!--tex4ht:ref: eesch1 --></a> shows the schematic editor and the various menu and toolbars. We will explain them +briefly in this section. <hr class="figure"><div class="figure" +> + +<a + id="x1-290011"></a> + +<div class="center" +> +<!--l. 25--><p class="noindent" > + +<!--l. 26--><p class="noindent" ><img +src="figures/schematic1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.1: </span><span +class="content">Schematic editor with the menu bar and toolbars marked</span></div><!--tex4ht:label?: x1-290011 --> +</div> + +<!--l. 30--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">5.1.1 </span> <a + id="x1-300005.1.1"></a>Top menu bar</h4> +<!--l. 35--><p class="noindent" >The top menu bar will be available at the top left corner. Some of the important menu +options in the top menu bar are: + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">File - The file menu items are given below: + <dl class="compactenum"><dt class="compactenum"> + (a) </dt><dd +class="compactenum">New - Clear current schematic and start a new one + </dd><dt class="compactenum"> + (b) </dt><dd +class="compactenum">Open - Open a schematic + </dd><dt class="compactenum"> + (c) </dt><dd +class="compactenum">Open Recent - A list of recently opened files for loading + </dd><dt class="compactenum"> + (d) </dt><dd +class="compactenum">Save Whole Schematic project - Save current sheet and all its hierarchy. + </dd><dt class="compactenum"> + (e) </dt><dd +class="compactenum">Save Current Sheet Only - Save current sheet, but not others in a hierarchy. + </dd><dt class="compactenum"> + (f) </dt><dd +class="compactenum">Save Current sheet as - Save current sheet with a new name. + </dd><dt class="compactenum"> + (g) </dt><dd +class="compactenum">Print - Access to print menu (See Fig. <a +href="#x1-300112">5.2<!--tex4ht:ref: print --></a>). + </dd><dt class="compactenum"> + (h) </dt><dd +class="compactenum">Plot - Plot the schematic in Postscript, HPGL, SVF or DXF format + </dd><dt class="compactenum"> + (i) </dt><dd +class="compactenum">Quit - Quit the schematic editor.</dd></dl> + <!--l. 53--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-300112"></a> +<div class="center" +> +<!--l. 54--><p class="noindent" > + +<!--l. 55--><p class="noindent" ><img +src="figures/print.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.2: </span><span +class="content">Print options</span></div><!--tex4ht:label?: x1-300112 --> +</div> + <!--l. 59--><p class="noindent" ></div><hr class="endfigure"> + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Place - The place menu has shortcuts for placing various items like components, wire + and junction, on to the schematic editor window. See Sec. <a +href="#x1-340005.1.5">5.1.5<!--tex4ht:ref: short --></a> to know more about + various shortcut keys (hotkeys). + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Preferences - The preferences menu has the following options: + <dl class="compactenum"><dt class="compactenum"> + + (a) </dt><dd +class="compactenum">Library - Select libraries and library paths + </dd><dt class="compactenum"> + (b) </dt><dd +class="compactenum">Colors - Select colors for various items. + </dd><dt class="compactenum"> + (c) </dt><dd +class="compactenum">Options - Display schematic editor options (Units, Grid size). + </dd><dt class="compactenum"> + (d) </dt><dd +class="compactenum">Language - Shows the current list of translations. Use default. + </dd><dt class="compactenum"> + (e) </dt><dd +class="compactenum">Hotkeys - Access to the hot keys menu. See Sec. <a +href="#x1-340005.1.5">5.1.5<!--tex4ht:ref: short --></a> about hotkeys. + </dd><dt class="compactenum"> + (f) </dt><dd +class="compactenum">Read preferences - Read configuration file. + </dd><dt class="compactenum"> + (g) </dt><dd +class="compactenum">Save preferences - Save configuration file.</dd></dl> + </dd></dl> +<!--l. 79--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">5.1.2 </span> <a + id="x1-310005.1.2"></a>Top toolbar</h4> +<a + id="dx1-31001"></a> +<a + id="dx1-31002"></a> +<!--l. 80--><p class="noindent" >Some of the important tools in the top toolbar are discussed below. They are marked in +Fig. <a +href="#x1-310033">5.3<!--tex4ht:ref: eeschem2 --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-310033"></a> + + +<!--l. 84--><p class="noindent" ><img +src="figures/toptoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.3: </span><span +class="content">Toolbar on top with important tools marked</span></div><!--tex4ht:label?: x1-310033 --> + +<!--l. 87--><p class="indent" > </div><hr class="endfigure"> + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Save - Save the current schematic + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Library Editor - Create or edit components. + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Library Browser - Browse through the various component libraries available + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Navigate schematic hierarchy - Navigate among the root and sub-sheets in the + hierarchy + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Print - Print the schematic + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Generate netlist - Generate a netlist for PCB design or for simulation. + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">Annotate - Annotate the schematic + </dd><dt class="compactenum"> + 8. </dt><dd +class="compactenum">Check ERC - Do Electric Rules Check for the schematic + </dd><dt class="compactenum"> + 9. </dt><dd +class="compactenum">Create BOM - Create a Bill of Materials of the schematic</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">5.1.3 </span> <a + id="x1-320005.1.3"></a>Toolbar on the right</h4> +<a + id="dx1-32001"></a> +<a + id="dx1-32002"></a> +<!--l. 104--><p class="noindent" >The toolbar on the right side of the schematic editor window has many important tools. Some +of them are marked in Fig. <a +href="#x1-320034">5.4<!--tex4ht:ref: eeschem3 --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-320034"></a> + + +<!--l. 108--><p class="noindent" ><img +src="figures/rightoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.4: </span><span +class="content">Toolbar on right with important tools marked</span></div><!--tex4ht:label?: x1-320034 --> + +<!--l. 111--><p class="indent" > </div><hr class="endfigure"> +<!--l. 112--><p class="indent" > Let us now look at each of these tools and their uses. + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Place a component - Load a component to the schematic. See Sec. <a +href="#x1-360005.2.1">5.2.1<!--tex4ht:ref: selplace --></a> for more + details. + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Place a power port - Load a power port (Vcc, ground) to the schematic + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Place wire - Draw wires to connect components in schematic + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Place bus - Place a bus on the schematic + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Place a no connect - Place a no connect flag, particularly useful in ICs + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Place a local label - Place a label or node name which is local to the schematic + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">Place a global label - Place a global label (these are connected across all schematic + diagrams in the hierarchy) + </dd><dt class="compactenum"> + 8. </dt><dd +class="compactenum">Place a text or comment - Place a text or comment in the schematic</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">5.1.4 </span> <a + id="x1-330005.1.4"></a>Toolbar on the left</h4> +<a + id="dx1-33001"></a> +<a + id="dx1-33002"></a> +<!--l. 126--><p class="noindent" >Some of the important tools in the toolbar on the left are discussed below. They are marked +in Fig. <a +href="#x1-330035">5.5<!--tex4ht:ref: eeschem4 --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-330035"></a> + + +<!--l. 130--><p class="noindent" ><img +src="figures/lefttoolbar.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.5: </span><span +class="content">Toolbar on left with important tools marked</span></div><!--tex4ht:label?: x1-330035 --> + +<!--l. 133--><p class="indent" > </div><hr class="endfigure"> + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Show/Hide grid - Show or Hide the grid in the schematic editor. Pressing the tool + again hides (shows) the grid if it was shown (hidden) earlier. + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Show hidden pins - Show hidden pins of certain components, for example, power + pins of certain ICs.</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">5.1.5 </span> <a + id="x1-340005.1.5"></a>Hotkeys</h4> +<!--l. 142--><p class="noindent" >A set of keyboard keys are associated with various operations in the schematic editor. These +keys save time and make it easy to switch from one operation to another. The list of hotkeys +can be viewed by going to Preferences in the top menu bar. Choose <span +class="cmti-10x-x-109">Hotkeys </span>and +select <span +class="cmti-10x-x-109">List current keys</span>. The hotkeys can also be edited by selecting the option +<span +class="cmti-10x-x-109">Edit Hotkeys</span>. Some frequently used hotkeys, along with their functions, are given +below: + <ul> + <li class="compactitem">F1 - Zoom in + </li> + <li class="compactitem">F2 - Zoom out + </li> + <li class="compactitem">Ctrl + Z - Undo + </li> + <li class="compactitem">Delete - Delete item + </li> + <li class="compactitem">M - Move item + </li> + <li class="compactitem">C - Copy item + </li> + <li class="compactitem">A - Add/place component + </li> + <li class="compactitem">P - Place power component + </li> + <li class="compactitem">R - Rotate item + </li> + <li class="compactitem">X - Mirror component about X axis + </li> + <li class="compactitem">Y - Mirror component about Y axis + </li> + <li class="compactitem">E - Edit schematic component + </li> + + <li class="compactitem">W - Place wire + </li> + <li class="compactitem">T - Add text + </li> + <li class="compactitem">S - Add sheet</li></ul> +<!--l. 166--><p class="noindent" ><span +class="cmti-10x-x-109">Note: Both lower and upper-case keys will work as hotkeys</span>. +<!--l. 168--><p class="noindent" > + <h3 class="sectionHead"><span class="titlemark">5.2 </span> <a + id="x1-350005.2"></a>Schematic creation for simulation</h3> +<a + id="dx1-35001"></a> +<!--l. 170--><p class="noindent" >There are certain differences between the schematic created for simulation and that created +for PCB design. We need certain components like plots and current sources. For simulation +whereas these are not needed for PCB design. For PCB design, we would require connectors +(e.g. DB15 and 2 pin connector) for taking signals in and out of the PCB whereas +these have no meaning in simulation. This section covers schematic creation for +simulation. +<!--l. 177--><p class="indent" > The first step in the creation of circuit schematic is the selection and placement of +required components. The components are grouped under eSim-libraries as shown in Fig. <a +href="#x1-350026">5.6<!--tex4ht:ref: libraries --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-350026"></a> + + +<!--l. 181--><p class="noindent" ><img +src="figures/libraries.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.6: </span><span +class="content">eSim-Components Libraries</span></div><!--tex4ht:label?: x1-350026 --> + +<!--l. 184--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">5.2.1 </span> <a + id="x1-360005.2.1"></a>Selection and placement of components</h4> +<a + id="dx1-36001"></a> +<!--l. 189--><p class="noindent" >We would need a resistor, a capacitor, a voltage source, ground terminal. To place a resistor +on the schematic editor window, select the <span +class="cmti-10x-x-109">Place a component </span>tool from the toolbar +on the right side and click anywhere on the schematic editor. This opens up the +component selection window. Resistor component can be found under <span +class="cmti-10x-x-109">eSim</span><span +class="cmti-10x-x-109">_Devices</span> +library. Fig. <a +href="#x1-360027">5.7<!--tex4ht:ref: resistor --></a> shows the selection of resistor component. Click on OK. A resistor +will be tied to the cursor. Place the resistor on the schematic editor by a single +click. +<!--l. 196--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-360027"></a> + + +<!--l. 198--><p class="noindent" ><img +src="figures/resistor.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.7: </span><span +class="content">Placing a resistor using the Place a Component tool</span></div><!--tex4ht:label?: x1-360027 --> + +<!--l. 201--><p class="indent" > </div><hr class="endfigure"> +<!--l. 202--><p class="indent" > To place the next component, i.e., capacitor, click again on the schematic editor.Similarly, +Capacitor component is found under <span +class="cmti-10x-x-109">eSim</span><span +class="cmti-10x-x-109">_Devices </span>library. Click on OK. Place the capacitor +on the schematic editor by a single click. Let us now place a sinusoidal voltage source. This is +required for performing transient analysis. To place it, click again on the schematic editor. On +the component selection window, choose the library <span +class="cmti-10x-x-109">eSim</span><span +class="cmti-10x-x-109">_source </span>by double clicking on it. +Select the component <span +class="cmtt-10x-x-109">SINE </span>and click on OK. Place the sine source on the schematic editor by +a single click. +<!--l. 211--><p class="indent" > Place the component by clicking on the schematic editor. Similarly place <span +class="cmtt-10x-x-109">gnd</span>, a ground +terminal and <span +class="cmtt-10x-x-109">power</span><span +class="cmtt-10x-x-109">_flag </span>under <span +class="cmtt-10x-x-109">power </span>library. Once all the components are placed, the +schematic editor would look like the Fig. <a +href="#x1-360038">5.8<!--tex4ht:ref: afterplace --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-360038"></a> + + +<!--l. 216--><p class="noindent" ><img +src="figures/afterplace.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.8: </span><span +class="content">All RC circuit components placed</span></div><!--tex4ht:label?: x1-360038 --> + +<!--l. 219--><p class="indent" > </div><hr class="endfigure"> +<!--l. 220--><p class="indent" > Let us rotate the resistor to complete the circuit. To rotate the resistor, place the cursor +on the resistor and press the key <span +class="cmtt-10x-x-109">R</span>. Note that if the cursor is placed above the letter <span +class="cmtt-10x-x-109">R </span>(not +<span +class="cmtt-10x-x-109">R?</span>) on the resistor, it asks to clarify selection. Choose the option <span +class="cmti-10x-x-109">Component R</span>. This can be +avoided by placing the cursor slightly away from the letter R as shown in Fig. <a +href="#x1-360059">5.9<!--tex4ht:ref: rotate --></a>. This +applies to all components.<a + id="dx1-36004"></a> <hr class="figure"><div class="figure" +> + +<a + id="x1-360059"></a> + + +<!--l. 228--><p class="noindent" ><img +src="figures/rotate.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.9: </span><span +class="content">Placing the cursor (cross mark) slightly away from the letter R</span></div><!--tex4ht:label?: x1-360059 --> + +<!--l. 231--><p class="indent" > </div><hr class="endfigure"> +<!--l. 232--><p class="indent" > If one wants to move a component, place the cursor on top of the component and press the +key <span +class="cmtt-10x-x-109">M</span>. The component will be tied to the cursor and can be moved in any direction. +<a + id="dx1-36006"></a> + <h4 class="subsectionHead"><span class="titlemark">5.2.2 </span> <a + id="x1-370005.2.2"></a>Wiring the circuit</h4> +<a + id="dx1-37001"></a> +<!--l. 238--><p class="noindent" >The next step is to wire the connections. Let us connect the resistor to the capacitor. +To do so, point the cursor to the terminal of resistor to be connected and press +the key <span +class="cmtt-10x-x-109">W</span>. It has now changed to the wiring mode. Move the cursor towards the +terminal of the capacitor and click on it. A wire is formed as shown in Fig. <a +href="#x1-37002r1">5.10a<!--tex4ht:ref: wire1 --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-3700510"></a> + +<a + id="x1-37002r1"></a> +<!--l. 248--><p class="noindent" > <img +src="figures/wire1.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Initial</span> +<span +class="cmr-9">stages</span> <a + id="x1-37003r2"></a> <img +src="figures/wirefin.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Wiring</span> + <span +class="cmr-9">done</span> <a + id="x1-37004r3"></a> <img +src="figures/schemfin.png" alt="PIC" +> + <span +class="cmr-9">(c)</span> + <span +class="cmr-9">Final</span> + <span +class="cmr-9">schematic</span> + <span +class="cmr-9">with</span> + <span +class="cmr-9">PWR</span><span +class="cmr-9">_FLAG</span> +<br /> <div class="caption" +><span class="id">Figure 5.10: </span><span +class="content">Various stages of wiring</span></div><!--tex4ht:label?: x1-3700510 --> + +<!--l. 256--><p class="indent" > </div><hr class="endfigure"> +<!--l. 257--><p class="indent" > Similarly connect the wires between all terminals and the final schematic would look like +Fig. <a +href="#x1-37003r2">5.10b<!--tex4ht:ref: wirefin --></a>. + <h4 class="subsectionHead"><span class="titlemark">5.2.3 </span> <a + id="x1-380005.2.3"></a>Assigning values to components</h4> +<a + id="dx1-38001"></a> +<!--l. 261--><p class="noindent" >We need to assign values to the components in our circuit i.e., resistor and capacitor. Note +that the sine voltage source has been placed for simulation. The specifications of sine source +will be given during simulation. To assign value to the resistor, place the cursor above the +letter <span +class="cmtt-10x-x-109">R </span>(not <span +class="cmtt-10x-x-109">R?</span>) and press the key <span +class="cmtt-10x-x-109">E</span>. Choose <span +class="cmti-10x-x-109">Field value</span>. Type <span +class="cmtt-10x-x-109">1k </span>in the <span +class="cmti-10x-x-109">Edit value field </span>box +as shown in Fig. <a +href="#x1-3800211">5.11<!--tex4ht:ref: field --></a>. 1k means 1<span +class="cmmi-10x-x-109">k</span>Ω. Similarly give the value <span +class="cmtt-10x-x-109">1u </span>for the capacitor. 1u means +1<span +class="cmmi-10x-x-109">μF</span>. +<!--l. 271--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-3800211"></a> + + +<!--l. 273--><p class="noindent" ><img +src="figures/field.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.11: </span><span +class="content">Editing value of resistor</span></div><!--tex4ht:label?: x1-3800211 --> + +<!--l. 276--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">5.2.4 </span> <a + id="x1-390005.2.4"></a>Annotation and ERC</h4> +<a + id="dx1-39001"></a> +<a + id="dx1-39002"></a> +<a + id="dx1-39003"></a> +<a + id="dx1-39004"></a> +<!--l. 280--><p class="noindent" >The next step is to annotate the schematic. Annotation gives unique references to the +components. To annotate the schematic, click on <span +class="cmti-10x-x-109">Annotate schematic </span>tool from the +top toolbar. Click on <span +class="cmtt-10x-x-109">annotation</span>, then click on <span +class="cmtt-10x-x-109">OK </span>and finally click on close as +shown in Fig. <a +href="#x1-3900813">5.13<!--tex4ht:ref: anno --></a>. The schematic is now annotated. The question marks next to +component references have been replaced by unique numbers. If there are more than +one instance of a component (say resistor), the annotation will be done as R1, R2, +etc. +<!--l. 289--><p class="indent" > Let us now do <span +class="cmtt-10x-x-109">ERC </span>or <span +class="cmtt-10x-x-109">Electric Rules Check</span>. To do so, click on <span +class="cmti-10x-x-109">Perform electric rules</span> +<span +class="cmti-10x-x-109">check </span>tool from the top toolbar. Click on <span +class="cmti-10x-x-109">Test Erc </span>button. The error as shown in Fig. <a +href="#x1-3900712">5.12<!--tex4ht:ref: erc --></a> +may be displayed. Click on close in the test erc<a + id="dx1-39005"></a> window. <a + id="dx1-39006"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-3900712"></a> + + +<!--l. 296--><p class="noindent" ><img +src="figures/erc2.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.12: </span><span +class="content">ERC error</span></div><!--tex4ht:label?: x1-3900712 --> + +<!--l. 299--><p class="indent" > </div><hr class="endfigure"> +<!--l. 300--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-3900813"></a> + + +<!--l. 302--><p class="noindent" ><img +src="figures/anno.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.13: </span><span +class="content">Steps in annotating a schematic: 1. First click on Annotation then 2. Click +on Ok then 3. Click on close</span></div><!--tex4ht:label?: x1-3900813 --> + +<!--l. 305--><p class="indent" > </div><hr class="endfigure"> +<!--l. 306--><p class="indent" > There will be a green arrow pointing to the source of error in the schematic. Here it points +to the ground terminal. This is shown in Fig. <a +href="#x1-3900914">5.14<!--tex4ht:ref: ercgnd --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-3900914"></a> + + +<!--l. 311--><p class="noindent" ><img +src="figures/ercgnd.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.14: </span><span +class="content">Green arrow pointing to Ground terminal indicating an ERC error</span></div><!--tex4ht:label?: x1-3900914 --> + +<!--l. 314--><p class="indent" > </div><hr class="endfigure"> +<!--l. 315--><p class="indent" > To correct this error, place a <span +class="cmtt-10x-x-109">PWR</span><span +class="cmtt-10x-x-109">_FLAG </span>from the Eeschema library <span +class="cmti-10x-x-109">power</span>. <a + id="dx1-39010"></a>Connect the +power flag to the ground terminal as shown in Fig. <a +href="#x1-37004r3">5.10c<!--tex4ht:ref: schemfin --></a>. One needs to place <span +class="cmtt-10x-x-109">PWR</span><span +class="cmtt-10x-x-109">_FLAG</span> +wherever the error shown in Fig. <a +href="#x1-3900712">5.12<!--tex4ht:ref: erc --></a> is obtained. Repeat the ERC. Now there are no errors. +With this we have created the schematic for simulation. + <h4 class="subsectionHead"><span class="titlemark">5.2.5 </span> <a + id="x1-400005.2.5"></a>Netlist generation</h4> +<a + id="dx1-40001"></a> +<!--l. 326--><p class="noindent" >To simulate the circuit that has been created in the previous section, we need to generate its +netlist. <span +class="cmtt-10x-x-109">Netlist </span>is a list of components in the schematic along with their connection +information. <a + id="dx1-40002"></a>To do so, click on the <span +class="cmti-10x-x-109">Generate netlist </span>tool from the top toolbar. Click on spice +from the window that opens up. Check the option <span +class="cmtt-10x-x-109">Default Format</span>. Then click on <span +class="cmti-10x-x-109">Generate</span>. +This is shown in Fig. <a +href="#x1-4000315">5.15<!--tex4ht:ref: chap5net --></a>. Save the netlist. This will be a <span +class="cmtt-10x-x-109">.cir </span>file. Do not change the +directory while saving. <hr class="figure"><div class="figure" +> + +<a + id="x1-4000315"></a> + + +<!--l. 337--><p class="noindent" ><img +src="figures/netlist.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 5.15: </span><span +class="content">Steps in generating a Netlist for simulation: 1. Click on Spice then 2. +Check the option <span +class="cmtt-10x-x-109">Default Format </span>then 3. Click on Generate </span></div><!--tex4ht:label?: x1-4000315 --> + +<!--l. 340--><p class="indent" > </div><hr class="endfigure"> +<!--l. 341--><p class="indent" > Now the netlist is ready to be simulated. Refer to <span class="cite"> [<a +href="#Xkicad">15</a>]</span> or <span class="cite"> [<a +href="#Xkicad2">16</a>]</span> to know more about +Eeschema. + + <h2 class="chapterHead"><span class="titlemark">Chapter 6</span><br /><a + id="x1-410006"></a>PCB Design</h2> Printed Circuit Board (PCB) <a + id="dx1-41001"></a>design is an important step in +electronic system design. Every component of the circuit needs to be placed and connections +routed to minimise delay and area. Each component has an associated footprint. Footprint +refers to the physical layout of a component that is required to mount it on the PCB.<a + id="dx1-41002"></a> <a + id="dx1-41003"></a>PCB +design involves associating footprints to all components, placing them appropriately to +minimise wire length and area, connecting the footprints using tracks/vias and finally +extracting the required files needed for printing the PCB. Let us see the steps to design PCB +using eSim. + <h3 class="sectionHead"><span class="titlemark">6.1 </span> <a + id="x1-420006.1"></a>Schematic creation for PCB design</h3> +<!--l. 16--><p class="noindent" >In Chapter <a +href="#x1-610009">9<!--tex4ht:ref: chap5 --></a>, we will see the differences between schematic for simulation and schematic for +PCB design. Let us design the PCB for a RC circuit. A resistor, capacitor, ground, power flag +and a connector are required. Connectors are used to take signals in and out of the +PCB. +<!--l. 22--><p class="indent" > Create the circuit schematic as shown in Fig. <a +href="#x1-420011">6.1<!--tex4ht:ref: pcbschfin --></a>. The two pin connector (<span +class="cmti-10x-x-109">CONN</span><span +class="cmti-10x-x-109">_2</span>) can +be placed from the Eeschema library <span +class="cmti-10x-x-109">conn</span>. Do the annotation and test for ERC. Refer to +Chapter <a +href="#x1-610009">9<!--tex4ht:ref: chap5 --></a> to know more about basic steps in schematic creation. +<!--l. 28--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-420011"></a> + + +<!--l. 30--><p class="noindent" ><img +src="figures/pcbschfin.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.1: </span><span +class="content">Final circuit schematic for RC low pass circuit</span></div><!--tex4ht:label?: x1-420011 --> + +<!--l. 33--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">6.1.1 </span> <a + id="x1-430006.1.1"></a>Netlist generation for PCB</h4> +<a + id="dx1-43001"></a> +<a + id="dx1-43002"></a> +<!--l. 38--><p class="noindent" >The netlist for PCB is different from that for simulation. To generate netlist for PCB, click on +the <span +class="cmti-10x-x-109">Generate netlist </span>tool from the top toolbar in Schematic editor. In the Netlist window, +under the tab <span +class="cmti-10x-x-109">Pcbnew</span>, <a + id="dx1-43003"></a>click on the button <span +class="cmti-10x-x-109">Netlist</span>. This is shown in Fig. <a +href="#x1-430042">6.2<!--tex4ht:ref: netlistpcb --></a>. Click on +<span +class="cmti-10x-x-109">Save </span>in the Save netlist file dialog box that opens up. Do not change the directory +or the name of the netlist file. Save the schematic and close the schematic editor. +<hr class="figure"><div class="figure" +> + +<a + id="x1-430042"></a> + + +<!--l. 48--><p class="noindent" ><img +src="figures/netlistpcb.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.2: </span><span +class="content">Netlist generation for PCB</span></div><!--tex4ht:label?: x1-430042 --> + +<!--l. 51--><p class="indent" > </div><hr class="endfigure"> +<!--l. 52--><p class="indent" > <span +class="cmti-10x-x-109">Note that the netlist for PCB has an extension </span><span +class="cmtt-10x-x-109">.net</span><span +class="cmti-10x-x-109">. The netlist created for simulation</span> +<span +class="cmti-10x-x-109">has an extension </span><span +class="cmtt-10x-x-109">.cir</span>. + <h4 class="subsectionHead"><span class="titlemark">6.1.2 </span> <a + id="x1-440006.1.2"></a>Mapping of components using Footprint Editor</h4> +<a + id="dx1-44001"></a> +<a + id="dx1-44002"></a> +<a + id="dx1-44003"></a> +<!--l. 59--><p class="noindent" >Once the netlist for PCB is created, one needs to map each component in the netlist to a +footprint. The tool <span +class="cmti-10x-x-109">Footprint Editor </span>is used for this. eSim uses <span +class="cmtt-10x-x-109">CvPcb </span>as its footprint editor. +<span +class="cmtt-10x-x-109">CvPcb </span>is the footprint editor tool in KiCad. <a + id="dx1-44004"></a> +<!--l. 64--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.1.3 </span> <a + id="x1-450006.1.3"></a>Familiarising the Footprint Editor tool</h4> +<a + id="dx1-45001"></a> +<!--l. 67--><p class="noindent" >If one opens the <span +class="cmti-10x-x-109">Footprint Editor </span>after creating the <span +class="cmtt-10x-x-109">.net </span>netlist file, the Footprint editor as +shown in Fig. <a +href="#x1-450023">6.3<!--tex4ht:ref: fe --></a> will be obtained. The menu bar and toolbars and the panes are marked in +this figure. The menu bar will be available in the top left corner. The left pane has a list of +components in the netlist file and the right pane has a list of available footprints for each +component. <hr class="figure"><div class="figure" +> + +<a + id="x1-450023"></a> + + +<!--l. 75--><p class="noindent" ><img +src="figures/fe.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.3: </span><span +class="content">Footprint editor with the menu bar, toolbar, left pane and right pane +marked</span></div><!--tex4ht:label?: x1-450023 --> + +<!--l. 78--><p class="indent" > </div><hr class="endfigure"> +<!--l. 79--><p class="indent" > <span +class="cmti-10x-x-109">Note that if the Footprint Editor is opened before creating a ‘.net’ file, then the left and</span> +<span +class="cmti-10x-x-109">right panes will be empty</span>. + <h5 class="subsubsectionHead"><a + id="x1-460006.1.3"></a>Toolbar</h5> +<!--l. 82--><p class="noindent" >Some of the important tools in the toolbar are shown in Fig. <a +href="#x1-460014">6.4<!--tex4ht:ref: tb_fe --></a>. They are explained below: +<hr class="figure"><div class="figure" +> + +<a + id="x1-460014"></a> + + +<!--l. 86--><p class="noindent" ><img +src="figures/tb_fe.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.4: </span><span +class="content">Some important tools in the toolbar</span></div><!--tex4ht:label?: x1-460014 --> + +<!--l. 89--><p class="indent" > </div><hr class="endfigure"> + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Save netlist and footprint files - Save the netlist and the footprints that are + associated with it. + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">View selected footprint - View the selected footprint in 2D. See Sec. <a +href="#x1-470006.1.4">6.1.4<!--tex4ht:ref: viewfp --></a> for more + details. + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Automatic footprint association - Perform footprint association for each + component automatically. Footprints will be selected from the list of footprints + available. + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Delete all associations - Delete all the footprint associations made + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Display filtered footprint list - Display a filtered list of footprints suitable to the + selected component + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Display full footprint list - Display the list of all footprints available (without + filtering)</dd></dl> + <h4 class="subsectionHead"><span class="titlemark">6.1.4 </span> <a + id="x1-470006.1.4"></a>Viewing footprints in 2D and 3D</h4> +<a + id="dx1-47001"></a> +<a + id="dx1-47002"></a> +<!--l. 110--><p class="noindent" >To view a footprint in 2D, select it from the right pane and click on <span +class="cmti-10x-x-109">View selected footprint</span> +from the menu bar. Let us view the footprint for <span +class="cmtt-10x-x-109">SM1210</span>. Choose SM1210 from +the right pane as shown in Fig. <a +href="#x1-470035">6.5<!--tex4ht:ref: sm --></a>. On clicking the <span +class="cmti-10x-x-109">View selected footprint </span>tool, +the <span +class="cmtt-10x-x-109">Footprint </span>window with the view in 2D will be displayed. Click on the <span +class="cmti-10x-x-109">3D</span> +tool in the <span +class="cmtt-10x-x-109">Footprint </span>window, as shown in Fig. <a +href="#x1-470046">6.6<!--tex4ht:ref: 3d --></a>. A top view of the selected +footprint in 3D is obtained. Click on the footprint and rotate it using mouse to get 3D +views from various angles. One such side view of the footprint in 3D is shown in +Fig. <a +href="#x1-470057">6.7<!--tex4ht:ref: 3dv --></a>. +<!--l. 121--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-470035"></a> + + +<!--l. 123--><p class="noindent" ><img +src="figures/sm.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.5: </span><span +class="content">Viewing footprint for SM1210: 1. Choose the footprint SM1210 from the +right pane, 2. Click on <span +class="cmti-10x-x-109">View selected footprint</span></span></div><!--tex4ht:label?: x1-470035 --> + +<!--l. 127--><p class="indent" > </div><hr class="endfigure"> +<!--l. 128--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-470046"></a> + + +<!--l. 130--><p class="noindent" ><img +src="figures/3d.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.6: </span><span +class="content">Footprint view in 2D. Click on <span +class="cmti-10x-x-109">3D </span>to get 3D view</span></div><!--tex4ht:label?: x1-470046 --> + +<!--l. 133--><p class="indent" > </div><hr class="endfigure"> +<!--l. 134--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-470057"></a> + + +<!--l. 136--><p class="noindent" ><img +src="figures/3dv.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.7: </span><span +class="content">Side view of the footprint in 3D</span></div><!--tex4ht:label?: x1-470057 --> + +<!--l. 139--><p class="indent" > </div><hr class="endfigure"> + <h4 class="subsectionHead"><span class="titlemark">6.1.5 </span> <a + id="x1-480006.1.5"></a>Mapping of components in the RC circuit</h4> +<!--l. 142--><p class="noindent" >Click on <span +class="cmtt-10x-x-109">C1 </span>from the left pane. Choose the footprint <span +class="cmti-10x-x-109">C1 </span>from the right pane by double +clicking on it. Click on connector <span +class="cmtt-10x-x-109">P1 </span>from the left pane. Choose the footprint <span +class="cmti-10x-x-109">SIL-2 </span>from the +right pane by double clicking on it. Similarly choose the footprint <span +class="cmti-10x-x-109">R3 </span>for the resistor <span +class="cmtt-10x-x-109">R1</span>. The +footprint mapping is shown in Fig. <a +href="#x1-480018">6.8<!--tex4ht:ref: map --></a>. Save the footprint association by clicking on the <span +class="cmti-10x-x-109">Save</span> +<span +class="cmti-10x-x-109">netlist and footprint files </span>tool from the <span +class="cmtt-10x-x-109">CvPcb </span>toolbar. The <span +class="cmtt-10x-x-109">Save Net and component List</span> +window appears. Browse to the directory where the schematic file for this project is saved and +click on <span +class="cmti-10x-x-109">Save</span>. The netlist gets saved and the <span +class="cmti-10x-x-109">Footprint Editor </span>window closes automatically. +<hr class="figure"><div class="figure" +> + +<a + id="x1-480018"></a> + + +<!--l. 155--><p class="noindent" ><img +src="figures/map.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.8: </span><span +class="content">Footprint mapping done</span></div><!--tex4ht:label?: x1-480018 --> + +<!--l. 158--><p class="indent" > </div><hr class="endfigure"> +<!--l. 159--><p class="indent" > <span +class="cmti-10x-x-109">Note that one needs to browse to the directory where the schematic file is saved and save</span> +<span +class="cmti-10x-x-109">the ‘.net’ file in the same directory</span>. + <h3 class="sectionHead"><span class="titlemark">6.2 </span> <a + id="x1-490006.2"></a>Creation of PCB layout</h3> +<a + id="dx1-49001"></a> +<a + id="dx1-49002"></a> +<!--l. 164--><p class="noindent" >The next step is to place the footprints and lay tracks between them to get the layout. This is +done using the <span +class="cmti-10x-x-109">Layout Editor </span>tool. eSim uses <span +class="cmtt-10x-x-109">Pcbnew</span>, the layout creation tool in KiCad, as its +layout editor. +<!--l. 169--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.2.1 </span> <a + id="x1-500006.2.1"></a>Familiarizing the Layout Editor tool</h4> +<a + id="dx1-50001"></a> +<!--l. 172--><p class="noindent" >The layout editor with the various menu bar and toolbars is shown in Fig. <a +href="#x1-500029">6.9<!--tex4ht:ref: pcbnew --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-500029"></a> + + +<!--l. 176--><p class="noindent" ><img +src="figures/pcbnew.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.9: </span><span +class="content">Layout editor with menu bar, toolbars and layer options marked</span></div><!--tex4ht:label?: x1-500029 --> + +<!--l. 179--><p class="indent" > </div><hr class="endfigure"> +<!--l. 180--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5000310"></a> + + +<!--l. 182--><p class="noindent" ><img +src="figures/toptble.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.10: </span><span +class="content">Top toolbar with important tools marked</span></div><!--tex4ht:label?: x1-5000310 --> + +<!--l. 185--><p class="indent" > </div><hr class="endfigure"> + <h5 class="subsubsectionHead"><a + id="x1-510006.2.1"></a>Top toolbar</h5> +<!--l. 188--><p class="noindent" >Some of the important menu options in the top menu bar are shown in Fig. <a +href="#x1-5000310">6.10<!--tex4ht:ref: toptble --></a>. They are +explained below: + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">Save board - Save the printed circuit board + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">Module editor - Open module editor to edit footprint modules or libraries + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Read netlist - Import the netlist whose layout needs to be created. + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">Perform design rules check - Check for design rules, unconnected nets, etc., in the + layout. + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">Select working layer - Selection of working layer + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">Show active layer selections and select layer pair for route and place - Select layer + in top and bottom layers. It also shows the currently active layer selections. + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">Mode footprint: Manual/automatic move and place - Move and place modules</dd></dl> +<!--l. 206--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.2.2 </span> <a + id="x1-520006.2.2"></a>Hotkeys</h4> +<a + id="dx1-52001"></a> +<!--l. 208--><p class="noindent" >A list of hotkeys are given below: + <dl class="compactenum"><dt class="compactenum"> + 1. </dt><dd +class="compactenum">F1 - Zoom in + </dd><dt class="compactenum"> + 2. </dt><dd +class="compactenum">F2 - Zoom out + </dd><dt class="compactenum"> + 3. </dt><dd +class="compactenum">Delete - Delete Track or Footprint + </dd><dt class="compactenum"> + 4. </dt><dd +class="compactenum">X - Add new track + </dd><dt class="compactenum"> + 5. </dt><dd +class="compactenum">V - Add Via + </dd><dt class="compactenum"> + 6. </dt><dd +class="compactenum">M - Move Item + + </dd><dt class="compactenum"> + 7. </dt><dd +class="compactenum">F - Flip Footprint + </dd><dt class="compactenum"> + 8. </dt><dd +class="compactenum">R - Rotate Item + </dd><dt class="compactenum"> + 9. </dt><dd +class="compactenum">G - Drag Footprint + </dd><dt class="compactenum"> + 10. </dt><dd +class="compactenum">Ctrl+Z - Undo + </dd><dt class="compactenum"> + 11. </dt><dd +class="compactenum">E - Edit Item</dd></dl> +<!--l. 222--><p class="noindent" >The list can be viewed by selecting <span +class="cmti-10x-x-109">Preferences </span>from the top menu bar and choosing <span +class="cmti-10x-x-109">List Current</span> +<span +class="cmti-10x-x-109">Keys </span>from the option <span +class="cmti-10x-x-109">Hotkeys</span>. +<!--l. 226--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">6.2.3 </span> <a + id="x1-530006.2.3"></a>PCB design example using RC circuit</h4> +<a + id="dx1-53001"></a> +<!--l. 227--><p class="noindent" >Click on <span +class="cmti-10x-x-109">Layout Editor </span>from the eSim toolbar. Click on <span +class="cmti-10x-x-109">Read Netlist </span>tool from the top +toolbar. Click on <span +class="cmti-10x-x-109">Browse Netlist files </span>on the Netlist window that opens up. Select the <span +class="cmtt-10x-x-109">.net </span>file +that was modified after assigning footprints. Click on <span +class="cmti-10x-x-109">Open</span>. Now Click on <span +class="cmti-10x-x-109">Read Current</span> +<span +class="cmti-10x-x-109">Netlist </span>on the Netlist window. The message area in the Netlist window says that +the RC_pcb.net has been read. The sequence of operations is shown in Fig. <a +href="#x1-5300411">6.11<!--tex4ht:ref: brnet --></a>. +<a + id="dx1-53002"></a><a + id="dx1-53003"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5300411"></a> + + +<!--l. 238--><p class="noindent" ><img +src="figures/rcpcb.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.11: </span><span +class="content">Importing netlist file to layout editor: 1. Browse netlist Files, 2. Choose +the RC_pcb.net file, 3. Read Netlist file, 4. Close</span></div><!--tex4ht:label?: x1-5300411 --> + +<!--l. 242--><p class="indent" > </div><hr class="endfigure"> +<!--l. 243--><p class="indent" > The footprint modules will now be imported to the top left hand corner of the layout +editor window. This is shown in Fig. <a +href="#x1-5300512">6.12<!--tex4ht:ref: netlisttop --></a>. <hr class="figure"><div class="figure" +> + +<a + id="x1-5300512"></a> + + +<!--l. 247--><p class="noindent" ><img +src="figures/netlisttop.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.12: </span><span +class="content">Footprint modules imported to top left corner of layout editor window</span></div><!--tex4ht:label?: x1-5300512 --> + +<!--l. 250--><p class="indent" > </div><hr class="endfigure"> +<!--l. 251--><p class="indent" > Zoom in to the top left corner by pressing the key <span +class="cmtt-10x-x-109">F1 </span>or using the scroll button of the +mouse. The zoomed in version of the imported netlist is shown in Fig. <a +href="#x1-5300613">6.13<!--tex4ht:ref: zoom --></a>. +<!--l. 255--><p class="indent" > Let us now place this in the center of the layout editor window. <hr class="figure"><div class="figure" +> + +<a + id="x1-5300613"></a> + + +<!--l. 259--><p class="noindent" ><img +src="figures/zoom.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.13: </span><span +class="content">Zoomed in version of the imported netlist</span></div><!--tex4ht:label?: x1-5300613 --> + +<!--l. 262--><p class="indent" > </div><hr class="endfigure"> +<!--l. 263--><p class="indent" > Click on <span +class="cmti-10x-x-109">Mode footprint: Manual/automatic move and place </span>tool from the top toolbar. +Place the cursor near the center of the layout editor window. Right click and choose <span +class="cmti-10x-x-109">Glob</span> +<span +class="cmti-10x-x-109">move and place</span>. Choose <span +class="cmti-10x-x-109">move all modules</span>. The sequence of operations is shown in Fig. <a +href="#x1-5300714">6.14<!--tex4ht:ref: movep --></a>. +Click on <span +class="cmti-10x-x-109">Yes </span>on the confirmation window to move the modules. Zoom in using the F1 key. +The current placement of components after zooming in is shown in Fig. <a +href="#x1-53008r1">6.15a<!--tex4ht:ref: curplace --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-5300714"></a> + + +<!--l. 272--><p class="noindent" ><img +src="figures/movep.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.14: </span><span +class="content">Moving and placing modules to the center of layout editor. 1. Click on +<span +class="cmti-10x-x-109">Mode footprint: Manual/automatic move and place</span>, 2. Place cursor at center of layout +editor and right click on it 3. Choose <span +class="cmti-10x-x-109">Glob Move and Place </span>and then choose <span +class="cmti-10x-x-109">Move All</span> +<span +class="cmti-10x-x-109">Modules.</span></span></div><!--tex4ht:label?: x1-5300714 --> + +<!--l. 279--><p class="indent" > </div><hr class="endfigure"> +<!--l. 286--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5301015"></a> + +<a + id="x1-53008r1"></a> +<!--l. 290--><p class="noindent" > <img +src="figures/curplace.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Zoomed</span> +<span +class="cmr-9">in</span> +<span +class="cmr-9">version</span> +<span +class="cmr-9">of the</span> +<span +class="cmr-9">current</span> +<span +class="cmr-9">placement</span> +<span +class="cmr-9">after</span> +<span +class="cmr-9">moving</span> +<span +class="cmr-9">modules</span> +<span +class="cmr-9">to the</span> +<span +class="cmr-9">center</span> +<span +class="cmr-9">of the</span> +<span +class="cmr-9">layout</span> +<span +class="cmr-9">editor</span> <a + id="x1-53009r2"></a> <img +src="figures/fplace.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Final</span> + <span +class="cmr-9">placement</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">footprints</span> + <span +class="cmr-9">after</span> + <span +class="cmr-9">rotating</span> + <span +class="cmr-9">and</span> + <span +class="cmr-9">moving</span> + <span +class="cmr-9">P1</span> +<br /> <div class="caption" +><span class="id">Figure 6.15: </span><span +class="content">Different stages of placement of modules on PCB</span></div><!--tex4ht:label?: x1-5301015 --> + +<!--l. 295--><p class="indent" > </div><hr class="endfigure"> +<!--l. 296--><p class="indent" > We need to arrange the modules properly to lay tracks. Rotate the connector P1 by +placing the cursor on top of P1 and pressing R. Move it by placing the cursor on top of it and +pressing M. The final placement is shown in Fig. <a +href="#x1-53009r2">6.15b<!--tex4ht:ref: fplace --></a>. <a + id="dx1-53011"></a> +<!--l. 302--><p class="indent" > Let us now lay the tracks. Let us first change the track width. Click on <span +class="cmti-10x-x-109">Design rules </span>from +the top menu bar. Click on <span +class="cmti-10x-x-109">Design rules</span>. This is shown in Fig. <a +href="#x1-5301416">6.16<!--tex4ht:ref: drules --></a>. The <span +class="cmti-10x-x-109">Design Rules Editor</span> +window opens up. Here one can edit the various design rules. Double click on the track width +field to edit it. Type 0.8 and press <span +class="cmtt-10x-x-109">Enter</span>. Click on OK. Fig. <a +href="#x1-5301517">6.17<!--tex4ht:ref: druleedit --></a> shows the sequence of +operations. <a + id="dx1-53012"></a><a + id="dx1-53013"></a> <hr class="figure"><div class="figure" +> + +<a + id="x1-5301416"></a> + + +<!--l. 312--><p class="noindent" ><img +src="figures/drules.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.16: </span><span +class="content">Choose <span +class="cmti-10x-x-109">Design Rules </span>from the top menu bar and <span +class="cmti-10x-x-109">Design Rules </span>again</span></div><!--tex4ht:label?: x1-5301416 --> + +<!--l. 316--><p class="indent" > </div><hr class="endfigure"> +<!--l. 317--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5301517"></a> + + +<!--l. 319--><p class="noindent" ><img +src="figures/druleedit.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.17: </span><span +class="content">Changing the track width: 1. Double click on <span +class="cmti-10x-x-109">Track Width </span>field and type +0.8, 2. Click on <span +class="cmti-10x-x-109">OK</span></span></div><!--tex4ht:label?: x1-5301517 --> + +<!--l. 323--><p class="indent" > </div><hr class="endfigure"> +<!--l. 325--><p class="indent" > Click on <span +class="cmti-10x-x-109">Back </span>from the <span +class="cmti-10x-x-109">Layer </span>options as shown in Fig. <a +href="#x1-5301718">6.18<!--tex4ht:ref: layer --></a>. <a + id="dx1-53016"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5301718"></a> + + +<!--l. 329--><p class="noindent" ><img +src="figures/layer.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.18: </span><span +class="content">Choosing the copper layer <span +class="cmti-10x-x-109">Back</span></span></div><!--tex4ht:label?: x1-5301718 --> + +<!--l. 332--><p class="indent" > </div><hr class="endfigure"> +<!--l. 333--><p class="indent" > Let us now start laying the tracks. Place the cursor above the left terminal of R1 +in the layout editor window. Press the key <span +class="cmtt-10x-x-109">x</span>. Move the cursor down and double +click on the left terminal of C1. A track is formed. This is shown in Fig. <a +href="#x1-53018r1">6.19a<!--tex4ht:ref: track1 --></a>. +<hr class="figure"><div class="figure" +> + +<a + id="x1-5302119"></a> + +<a + id="x1-53018r1"></a> +<!--l. 341--><p class="noindent" > <img +src="figures/track1.png" alt="PIC" +> +<span +class="cmr-9">(a) A</span> +<span +class="cmr-9">track</span> +<span +class="cmr-9">formed</span> +<span +class="cmr-9">between</span> +<span +class="cmr-9">resistor</span> +<span +class="cmr-9">and</span> +<span +class="cmr-9">capacitor</span> <a + id="x1-53019r2"></a> <img +src="figures/track2.png" alt="PIC" +> + <span +class="cmr-9">(b) A</span> + <span +class="cmr-9">track</span> + <span +class="cmr-9">formed</span> + <span +class="cmr-9">between</span> + <span +class="cmr-9">capacitor</span> + <span +class="cmr-9">and</span> + <span +class="cmr-9">connector</span> <a + id="x1-53020r3"></a> <img +src="figures/track3.png" alt="PIC" +> + <span +class="cmr-9">(c) A</span> + <span +class="cmr-9">track</span> + <span +class="cmr-9">formed</span> + <span +class="cmr-9">between</span> + <span +class="cmr-9">connector</span> + <span +class="cmr-9">and</span> + <span +class="cmr-9">resistor</span> +<br /> <div class="caption" +><span class="id">Figure 6.19: </span><span +class="content">Different stages of laying tracks during PCB design</span></div><!--tex4ht:label?: x1-5302119 --> + +<!--l. 349--><p class="indent" > </div><hr class="endfigure"> +<!--l. 350--><p class="indent" > Similarly lay the track between capacitor C1 and connector P1 as shown in +Fig. <a +href="#x1-53019r2">6.19b<!--tex4ht:ref: track2 --></a>. The last track needs to be laid at an angle. To do so, place the cursor +above the second terminal of R1. Press the key x and move the cursor diagonally +down. Double click on the other terminal of the connector. The track will be laid +as shown in Fig. <a +href="#x1-53020r3">6.19c<!--tex4ht:ref: track3 --></a>. All tracks are now laid. The next step is to create PCB +edges. +<!--l. 358--><p class="indent" > Choose <span +class="cmti-10x-x-109">PCB</span><span +class="cmti-10x-x-109">_edges </span>from the <span +class="cmti-10x-x-109">Layer </span>options to add edges. Click on <span +class="cmti-10x-x-109">Add graphic line or</span> +<span +class="cmti-10x-x-109">polygon </span>from the toolbar on the left. Fig. <a +href="#x1-5302320">6.20<!--tex4ht:ref: pcbedges --></a> shows the sequence of operations. Let us now +start drawing edges for PCB. <a + id="dx1-53022"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5302320"></a> + + +<!--l. 365--><p class="noindent" ><img +src="figures/pcbedges.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.20: </span><span +class="content">Creating PCB edges: 1. Choose <span +class="cmti-10x-x-109">PCB</span><span +class="cmti-10x-x-109">_Edges </span>from <span +class="cmti-10x-x-109">Layer </span>options 2. Choose +<span +class="cmti-10x-x-109">Add graphic line or polygon </span>from left toolbar</span></div><!--tex4ht:label?: x1-5302320 --> + +<!--l. 370--><p class="indent" > </div><hr class="endfigure"> +<!--l. 371--><p class="indent" > Click to the left of the layout. Move cursor horizontally to the right. Click once to change +orientation. Move cursor vertically down. Draw the edges as shown in Fig. <a +href="#x1-5302421">6.21<!--tex4ht:ref: pcbed --></a>. Double click +to finish drawing the edges. <hr class="figure"><div class="figure" +> + +<a + id="x1-5302421"></a> + + +<!--l. 377--><p class="noindent" ><img +src="figures/pcbed.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.21: </span><span +class="content">PCB edges drawn</span></div><!--tex4ht:label?: x1-5302421 --> + +<!--l. 380--><p class="indent" > </div><hr class="endfigure"> +<!--l. 382--><p class="indent" > Click on <span +class="cmti-10x-x-109">Perform design rules check </span>from the top toolbar to check for design rules. The +<span +class="cmti-10x-x-109">DRC Control </span>window opens up. Click on <span +class="cmti-10x-x-109">Start DRC</span>. There are no errors under the <span +class="cmtt-10x-x-109">Error</span> +<span +class="cmtt-10x-x-109">messages </span>tab. Click on <span +class="cmti-10x-x-109">OK </span>to close DRC control window. Fig. <a +href="#x1-5302622">6.22<!--tex4ht:ref: drc --></a> shows the sequence of +operations. <a + id="dx1-53025"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5302622"></a> + + +<!--l. 390--><p class="noindent" ><img +src="figures/drc.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.22: </span><span +class="content">Performing design rules check: 1. Click on <span +class="cmti-10x-x-109">Start DRC</span>, 2. Click on <span +class="cmti-10x-x-109">Ok</span></span></div><!--tex4ht:label?: x1-5302622 --> + +<!--l. 394--><p class="indent" > </div><hr class="endfigure"> +<!--l. 395--><p class="indent" > Click on <span +class="cmti-10x-x-109">Save board </span>on the top toolbar. +<!--l. 397--><p class="indent" > To generate Gerber files, click on <span +class="cmti-10x-x-109">File </span>from the top menu bar. Click on <span +class="cmti-10x-x-109">Plot</span>. This is shown +in Fig. <a +href="#x1-5302823">6.23<!--tex4ht:ref: plot --></a>. The plot window opens up. One can choose which layers to plot by +selecting/deselecting them from the <span +class="cmtt-10x-x-109">Layers </span>pane on the left side. One can also choose the +format used to plot them. Choose <span +class="cmti-10x-x-109">Gerber</span>. The output directory of the plots created +can also be chosen. By default, it is the project directory. Some more options can +be chosen in this window. Click on <span +class="cmti-10x-x-109">Plot</span>. The message window shows the location +in which the Gerber files are created. Click on <span +class="cmti-10x-x-109">Close</span>. This is shown in Fig. <a +href="#x1-5302924">6.24<!--tex4ht:ref: plot2 --></a>. +<a + id="dx1-53027"></a><hr class="figure"><div class="figure" +> + +<a + id="x1-5302823"></a> + + +<!--l. 410--><p class="noindent" ><img +src="figures/plot.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.23: </span><span +class="content">Choosing <span +class="cmti-10x-x-109">Plot </span>from the <span +class="cmti-10x-x-109">File </span>menu</span></div><!--tex4ht:label?: x1-5302823 --> + +<!--l. 413--><p class="indent" > </div><hr class="endfigure"> +<!--l. 414--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-5302924"></a> + + +<!--l. 416--><p class="noindent" ><img +src="figures/plot2.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 6.24: </span><span +class="content">Creating Gerber files: 1. Choose <span +class="cmti-10x-x-109">Gerber </span>as the plot format, 2. Click on +<span +class="cmti-10x-x-109">Plot</span>. Message window shows location in which Gerber files are created, 3. Click on <span +class="cmti-10x-x-109">Close</span></span></div><!--tex4ht:label?: x1-5302924 --> + +<!--l. 421--><p class="indent" > </div><hr class="endfigure"> +<!--l. 422--><p class="indent" > The PCB design of RC circuit is now complete. To know more about Pcbnew, refer to +<span class="cite"> [<a +href="#Xkicad">15</a>]</span> or <span class="cite"> [<a +href="#Xkicad2">16</a>]</span>. + + <h2 class="chapterHead"><span class="titlemark">Chapter 7</span><br /><a + id="x1-540007"></a>Model Editor</h2> +<!--l. 4--><p class="noindent" >Spice based simulators include a feature which allows accurate modeling of semiconductor +devices such as diodes, transistors etc. eSim Model Editor provides a facility to define a new +model for devices such as <span +class="cmti-10x-x-109">diodes, MOSFET, BJT, JFET, IGBT, Magnetic core </span>etc. Model +Editor in eSim lets the user enter the values of parameters depending on the type of +device for which a model is required. The parameter values can be obtained from the +data-sheet of the device. A newly created model can be exported to the model library +and one can import it for different projects, whenever required. Model Editor also +provides a facility to edit existing models. The GUI of the model editor is as shown in +Fig. <a +href="#x1-540011">7.1<!--tex4ht:ref: modeleditor --></a> +<!--l. 15--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-540011"></a> + + +<!--l. 17--><p class="noindent" ><img +src="figures/modeleditor_new.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.1: </span><span +class="content">Model Editor</span></div><!--tex4ht:label?: x1-540011 --> + +<!--l. 20--><p class="indent" > </div><hr class="endfigure"> + <h3 class="sectionHead"><span class="titlemark">7.1 </span> <a + id="x1-550007.1"></a>Creating New Model Library </h3> +<!--l. 24--><p class="noindent" >eSim lets us create new model libraries based on the template model libraries. On selecting +<span +class="cmtt-10x-x-109">New </span>button the window is popped as shown in Fig. <a +href="#x1-550012">7.2<!--tex4ht:ref: modeleditor_new --></a>. The name has to be unique otherwise +the error message appears on the window. +<!--l. 27--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-550012"></a> + + +<!--l. 29--><p class="noindent" ><img +src="figures/modeleditor.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.2: </span><span +class="content">Creating New Model Library</span></div><!--tex4ht:label?: x1-550012 --> + +<!--l. 32--><p class="indent" > </div><hr class="endfigure"> +<!--l. 33--><p class="indent" > After the OK button is pressed the type of model library to be created is chosen by +selecting one of the types on the left hand side i.e. <span +class="cmtt-10x-x-109">Diode, BJT, MOS, JFET, IGBT,</span> +<span +class="cmtt-10x-x-109">Magnetic Core</span>. The template model library opens up in a tabular form as shown in Fig. <a +href="#x1-550023">7.3<!--tex4ht:ref: modelnew --></a> +<hr class="figure"><div class="figure" +> + +<a + id="x1-550023"></a> + + +<!--l. 36--><p class="noindent" ><img +src="figures/modelnew.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.3: </span><span +class="content">Choosing the Template Model Library </span></div><!--tex4ht:label?: x1-550023 --> + +<!--l. 39--><p class="indent" > </div><hr class="endfigure"> + +<!--l. 43--><p class="indent" > New parameters can be added or current parameters can be removed using <span +class="cmtt-10x-x-109">ADD</span> +and <span +class="cmtt-10x-x-109">REMOVE </span>buttons. Also the values of parameters can be changed in the table. +Adding and removing the parameters in library files is shown in the Fig. <a +href="#x1-550034">7.4<!--tex4ht:ref: modeladd --></a> and +Fig. <a +href="#x1-550045">7.5<!--tex4ht:ref: modelremove --></a> +<!--l. 45--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-550034"></a> + + +<!--l. 47--><p class="noindent" ><img +src="figures/modeladd.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.4: </span><span +class="content">Adding the Parameter in a Library</span></div><!--tex4ht:label?: x1-550034 --> + +<!--l. 50--><p class="indent" > </div><hr class="endfigure"> +<!--l. 52--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-550045"></a> + + +<!--l. 54--><p class="noindent" ><img +src="figures/modelremove.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.5: </span><span +class="content">Removing a Parameter from a Library </span></div><!--tex4ht:label?: x1-550045 --> + +<!--l. 57--><p class="indent" > </div><hr class="endfigure"> +<!--l. 59--><p class="indent" > After the editing of the model library is done, the file can be saved by selecting the <span +class="cmtt-10x-x-109">SAVE</span> +button. These libraries are saved in the <span +class="cmti-10x-x-109">User Libraries </span>folder under <span +class="cmti-10x-x-109">deviceModelLibrary</span> +repository. + <h3 class="sectionHead"><span class="titlemark">7.2 </span> <a + id="x1-560007.2"></a>Editing Current Model Library</h3> +<!--l. 62--><p class="noindent" >The existing model library can be modified using <span +class="cmtt-10x-x-109">EDIT </span>option. On clicking the <span +class="cmtt-10x-x-109">EDIT </span>button +the file dialog opens where all the library files are saved as shown in Fig. <a +href="#x1-560016">7.6<!--tex4ht:ref: modeledit --></a>. You can select +the library you want to edit. Once you are done with the editing, click on <span +class="cmtt-10x-x-109">SAVE</span> +button. +<!--l. 65--><p class="indent" > <hr class="figure"><div class="figure" +> + +<a + id="x1-560016"></a> + + +<!--l. 67--><p class="noindent" ><img +src="figures/modeledit.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 7.6: </span><span +class="content">Editing Existing Model Library</span></div><!--tex4ht:label?: x1-560016 --> + +<!--l. 70--><p class="indent" > </div><hr class="endfigure"> + <h3 class="sectionHead"><span class="titlemark">7.3 </span> <a + id="x1-570007.3"></a>Uploading external .lib file to eSim repository</h3> +<!--l. 73--><p class="noindent" >eSim directly cannot use the external .lib file. It has to be uploaded to eSim repository before +using it in a circuit. eSim provides the facility to upload library files. They are then converted +into xml format, which can be easily modified from the eSim interface. On clicking <span +class="cmtt-10x-x-109">UPLOAD</span> +button the library can be uploaded from any location. The model library will be +saved with the name you have provided, in the <span +class="cmti-10x-x-109">User Libraries </span>folder of repository +<span +class="cmti-10x-x-109">deviceModelLibrary</span>. + + <h2 class="chapterHead"><span class="titlemark">Chapter 8</span><br /><a + id="x1-580008"></a>SubCircuit Builder</h2> Subcircuit is a way to implement hierarchical modeling. +Once a subcircuit for a compo- nent is created, it can be used in other circuits. +eSim provides an easy way to create a subcircuit. The following Fig. <a +href="#x1-580011">8.1<!--tex4ht:ref: subcircuit_mainwin --></a> shows +the window that is opened when the SubCircuit tool is chosen from the toolbar. +<hr class="figure"><div class="figure" +> + +<a + id="x1-580011"></a> + + +<!--l. 8--><p class="noindent" ><img +src="figures/subcirciut_window.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.1: </span><span +class="content">Subcircuit Window</span></div><!--tex4ht:label?: x1-580011 --> + +<!--l. 11--><p class="noindent" ></div><hr class="endfigure"> + + <h3 class="sectionHead"><span class="titlemark">8.1 </span> <a + id="x1-590008.1"></a>Creating a SubCircuit</h3> +<!--l. 32--><p class="noindent" >The steps to create subcircuit are as follows. + <ul class="itemize1"> + <li class="itemize">After opening the Subcircuit tool, click on <span +class="cmtt-10x-x-109">New Subcircuit Schematic </span>button. + It will ask the name of the subcircuit. Enter the name of subcircuit (without any + spaces) and click <span +class="cmtt-10x-x-109">OK </span>as shown in Fig. <a +href="#x1-590012">8.2<!--tex4ht:ref: newsubcktschematic --></a>. + <!--l. 39--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590012"></a> <img +src="figures/newsubcktschematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.2: </span><span +class="content">New Sub circuit Window</span></div><!--tex4ht:label?: x1-590012 --> + <!--l. 44--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">After clicking <span +class="cmtt-10x-x-109">OK </span>button it will open KiCad schematic. Draw your circuit + which will be later used as a subcircuit. e.g the Fig. <a +href="#x1-590023">8.3<!--tex4ht:ref: createsubcktsch --></a> shows the half adder + circuit. + <!--l. 49--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590023"></a> <img +src="figures/createsubcktsch.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.3: </span><span +class="content">New Sub circuit Window</span></div><!--tex4ht:label?: x1-590023 --> + <!--l. 54--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Once you complete the circuit, assign port to the node of your circuit which will be + used to connect with the main circuit. The circuit will look like Fig. <a +href="#x1-590034">8.4<!--tex4ht:ref: halfadder --></a> after + adding PORT to it. The PORT symbol can be found in Eeschema as shown in + Fig. <a +href="#x1-590045">8.5<!--tex4ht:ref: port --></a>. + <!--l. 61--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590034"></a> <img +src="figures/ha_sub.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.4: </span><span +class="content">Half-Adder Subcircuit </span></div><!--tex4ht:label?: x1-590034 --> + <!--l. 66--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 69--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590045"></a> <img +src="figures/port_lib.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.5: </span><span +class="content">Selection of PORT component</span></div><!--tex4ht:label?: x1-590045 --> + <!--l. 74--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Next step is to save the schematic and generate KiCad netlist as explained in Chapter + 5. + </li> + <li class="itemize">To use this as a subcircuit, create a block in KiCad Eeschema by following steps given + below: + <dl class="enumerate"><dt class="enumerate"> + 1. </dt><dd +class="enumerate">Go to library browser of Eeschema. + </dd><dt class="enumerate"> + 2. </dt><dd +class="enumerate">Select the working library as eSim_Subckt as shown in Fig. <a +href="#x1-590076">8.6<!--tex4ht:ref: esimsubckt --></a> <hr class="figure"><div class="figure" +><a + id="x1-590076"></a> <img +src="figures/esim-subckt.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.6: </span><span +class="content">Selecting Working Library</span></div><!--tex4ht:label?: x1-590076 --> + <!--l. 90--><p class="noindent" ></div><hr class="endfigure"> + + </dd><dt class="enumerate"> + 3. </dt><dd +class="enumerate">Click on create a new component with reference X as shown in Fig. <a +href="#x1-590097">8.7<!--tex4ht:ref: subcktnewcomp --></a> <hr class="figure"><div class="figure" +><a + id="x1-590097"></a> + <img +src="figures/subcktnewcomp.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.7: </span><span +class="content">Creating New Component</span></div><!--tex4ht:label?: x1-590097 --> + <!--l. 99--><p class="noindent" ></div><hr class="endfigure"> + </dd><dt class="enumerate"> + 4. </dt><dd +class="enumerate">Start drawing the subcircuit block. Update and save it as shown in Fig. <a +href="#x1-590118">8.8<!--tex4ht:ref: block --></a>. + <!--l. 104--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-590118"></a> <img +src="figures/halfadderblock.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 8.8: </span><span +class="content">Half-Adder Subcircuit Block</span></div><!--tex4ht:label?: x1-590118 --> + <!--l. 109--><p class="noindent" ></div><hr class="endfigure"> + </dd></dl> + + </li> + <li class="itemize">Close the Eeschema window and click on Convert KiCad to Ngspice button in subcircuit + builder tool. This will convert the KiCad spice netlist to Ngspice netlist. And it will + save your subcircuit into eSim repository, which you can add in your main + circuit. + </li></ul> +<!--l. 120--><p class="noindent" > + <h3 class="sectionHead"><span class="titlemark">8.2 </span> <a + id="x1-600008.2"></a>Edit a Subcircuit</h3> +<!--l. 121--><p class="noindent" >The steps to edit a subcircuit are as follows. + <ul class="itemize1"> + <li class="itemize">After opening the Subcircuit tool, click on <span +class="cmtt-10x-x-109">Edit Subcircuit Schematic </span>button. + It will open a dialog box where you can select any subcircuit for editing. + </li> + <li class="itemize">After selecting the subcircuit it will open it in KiCad Eeschema, where you can + edit the subcircuit. + </li> + <li class="itemize">Next step is to save the schematic and generate KiCad netlist. + </li> + <li class="itemize">If you have edited the number of ports then you have to change the block in KiCad + Eeschema accordingly. + </li> + <li class="itemize">Close the Eeschema window and click on <span +class="cmtt-10x-x-109">Convert KiCad to Ngspice </span>button in + subcircuit builder tool to convert the edited subcircuit KiCad netlist into Ngspice + netlist. + </li></ul> + + <h2 class="chapterHead"><span class="titlemark">Chapter 9</span><br /><a + id="x1-610009"></a>Solved Examples</h2> + <h3 class="sectionHead"><span class="titlemark">9.1 </span> <a + id="x1-620009.1"></a>Solved Examples</h3> +<!--l. 8--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.1 </span> <a + id="x1-630009.1.1"></a>Basic RC Circuit</h4> +<!--l. 9--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-640009.1.1"></a>Problem Statement:</h5> +<!--l. 9--><p class="noindent" >Plot the Input and Output Waveform of an RC circuit whose input voltage (Vs) is 50Hz, +3V peak to peak. The values of Resistor (R) and Capacitor(C) are 1<span +class="cmmi-10x-x-109">k </span>and 1<span +class="cmmi-10x-x-109">uf</span> +respectively. + <h5 class="subsubsectionHead"><a + id="x1-650009.1.1"></a>Solution:</h5> + <ul class="itemize1"> + <li class="itemize">Creating a Project: The new project is created by clicking the <span +class="cmtt-10x-x-109">New </span>icon on the + menubar. The name of the project is given in the pop up window as shown in + Fig. <a +href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. <hr class="figure"><div class="figure" +><a + id="x1-650011"></a> <img +src="figures/rc1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.1: </span><span +class="content">Creating New Project</span></div><!--tex4ht:label?: x1-650011 --> + <!--l. 20--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Creating the Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema. + <!--l. 25--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650022"></a> <img +src="figures/rc2.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.2: </span><span +class="content">Open Schematic Editor</span></div><!--tex4ht:label?: x1-650022 --> + <!--l. 31--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 33--><p class="noindent" >To create a schematic in KiCad, we need to place the required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> + shows the icon on the right toolbar which opens the component library. + <!--l. 35--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650033"></a> <img +src="figures/rc_component.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.3: </span><span +class="content">Place Component Icon</span></div><!--tex4ht:label?: x1-650033 --> + <!--l. 41--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 45--><p class="noindent" >After all the required components of the simple RC circuit are placed, wiring is done + using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a> + <!--l. 47--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650044"></a> <img +src="figures/rc_wire.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.4: </span><span +class="content">Place Wire Icon</span></div><!--tex4ht:label?: x1-650044 --> + <!--l. 53--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 55--><p class="noindent" >Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. + <!--l. 57--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650055"></a> <img +src="figures/erc1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.5: </span><span +class="content">Electric Rules Check Icon</span></div><!--tex4ht:label?: x1-650055 --> + <!--l. 63--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 65--><p class="noindent" >Fig. <a +href="#x1-650066">9.6<!--tex4ht:ref: rc_complete1 --></a> shows the RC circuit after connecting the components by wire. + <!--l. 67--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650066"></a> <img +src="figures/rc_complete1.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.6: </span><span +class="content">RC circuit</span></div><!--tex4ht:label?: x1-650066 --> + <!--l. 72--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 76--><p class="noindent" >After clicking the <span +class="cmtt-10x-x-109">ERC </span>icon a window opens up. Click the <span +class="cmtt-10x-x-109">Run </span>button to run rules check. + The errors are listed in as shown in Fig. <a +href="#x1-65007r1">9.7a<!--tex4ht:ref: erc2 --></a>. This error is handled by adding <span +class="cmtt-10x-x-109">Power</span> + <span +class="cmtt-10x-x-109">Flag </span>as shown in Fig. <a +href="#x1-65008r2">9.7b<!--tex4ht:ref: rc_pwr --></a>. + <!--l. 78--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650097"></a> <a + id="x1-65007r1"></a> <img +src="figures/erc2.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">ERC</span> + <span +class="cmr-9">Run</span> <a + id="x1-65008r2"></a> <img +src="figures/rc_pwr.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Power</span> + <span +class="cmr-9">Flag</span> +<br /> <div class="caption" +><span class="id">Figure 9.7: </span><span +class="content">ERC check and POWER FLAG</span></div><!--tex4ht:label?: x1-650097 --> + <!--l. 87--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 89--><p class="noindent" >After adding the <span +class="cmtt-10x-x-109">Power Flag </span>the completed RC circuit is shown in Fig. <a +href="#x1-65010r1">9.8a<!--tex4ht:ref: rc_schematic --></a> and the + netlist is generated as shown in Fig. <a +href="#x1-65011r2">9.8b<!--tex4ht:ref: rc_netlist --></a>. + <!--l. 92--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650128"></a> <a + id="x1-65010r1"></a> <img +src="figures/rc_schematic.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Schematic</span> + <span +class="cmr-9">of RC</span> + <span +class="cmr-9">circuit</span> <a + id="x1-65011r2"></a> <img +src="figures/rc_netlistgeneration.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Generating</span> + <span +class="cmr-9">KiCad</span> + <span +class="cmr-9">Netlist</span> + <span +class="cmr-9">of RC</span> + <span +class="cmr-9">circuit</span> +<br /> <div class="caption" +><span class="id">Figure 9.8: </span><span +class="content">RC Schematic and Netlist Generation</span></div><!--tex4ht:label?: x1-650128 --> + <!--l. 101--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Convert KiCad to Ngspice: To convert KiCad netlist of RC circuit to NgSpice + compatible netlist click on KiCad to Ngspice icon as shown in Fig. <a +href="#x1-650139">9.9<!--tex4ht:ref: rcki2ng --></a>. + <!--l. 107--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-650139"></a> <img +src="figures/rc_ki2ng.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.9: </span><span +class="content">Convert KiCad to Ngspice Icon</span></div><!--tex4ht:label?: x1-650139 --> + <!--l. 112--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 114--><p class="noindent" >Now you can enter the type of analysis and source details as shown in Fig. <a +href="#x1-65014r1">9.10a<!--tex4ht:ref: rc_analysistab --></a> and + Fig. <a +href="#x1-65015r2">9.10b<!--tex4ht:ref: rc_sourcedetailstab --></a> respectively. + <!--l. 116--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6501610"></a> <a + id="x1-65014r1"></a> <img +src="figures/rc_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">RC</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-65015r2"></a> <img +src="figures/rc_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">RC</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<br /> <div class="caption" +><span class="id">Figure 9.10: </span><span +class="content">RC Analysis and Source Detail</span></div><!--tex4ht:label?: x1-6501610 --> + <!--l. 125--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 126--><p class="noindent" >The other tab will be empty as RC circuit do not use any Ngspice model, device library + and subcircuit. + <!--l. 128--><p class="noindent" >After entering the value, press the convert button. It will convert the netlist into + Ngspice compatible netlist. + + </li> + <li class="itemize">Simulation: To run Ngspice simulation click the simulation icon in the tool bar + as shown in the Fig. <a +href="#x1-6501711">9.11<!--tex4ht:ref: rcplot --></a>. <hr class="figure"><div class="figure" +><a + id="x1-6501711"></a> <img +src="figures/rc_plot.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.11: </span><span +class="content">Simulation Icon</span></div><!--tex4ht:label?: x1-6501711 --> + <!--l. 139--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 141--><p class="noindent" >In eSim, there are two types of plot. First is normal Ngspice plot and second is + interactive python plot as shown in Fig. <a +href="#x1-65018r1">9.12a<!--tex4ht:ref: rc_ngspiceplot --></a> and Fig. <a +href="#x1-65019r2">9.12b<!--tex4ht:ref: rc_pythonplot --></a> respectively. + <!--l. 143--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6502012"></a> <a + id="x1-65018r1"></a> <img +src="figures/rc_ngspiceplot.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Ngspice</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of RC</span> <a + id="x1-65019r2"></a> <img +src="figures/rc_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of RC</span> +<br /> <div class="caption" +><span class="id">Figure 9.12: </span><span +class="content">Ngspice and Interactive Python Plotting</span></div><!--tex4ht:label?: x1-6502012 --> + <!--l. 152--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 154--><p class="noindent" >In the interactive python plot you can select any node or branch to plot voltage or + current across it. Also it has the facility to plot basic functions across the node like + addition, substraction, multiplication, division and v/s. + </li></ul> + +<!--l. 160--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.2 </span> <a + id="x1-660009.1.2"></a>Half Wave Rectifier</h4> +<!--l. 162--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-670009.1.2"></a>Problem Statement:</h5> +<!--l. 162--><p class="noindent" >Plot the Input and Output Waveform of Half Wave Rectifier circuit where the input voltage +(Vs) is 50Hz, 2V peak to peak. The value for Resistor (R) is 1k. +<!--l. 164--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-680009.1.2"></a>Solution:</h5> +<!--l. 165--><p class="noindent" >The new project is created by clicking the <span +class="cmtt-10x-x-109">New </span>icon on the menubar. The name of the project +is given in the window shown in Fig. <a +href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" /> + <!--l. 171--><p class="noindent" >After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" /> + <!--l. 174--><p class="noindent" >After all the required components of the simple Half Wave rectifier circuits are + placed, wiring is done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a><br +class="newline" /> + <!--l. 176--><p class="noindent" >Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. After + completing all the above steps the final Half Wave Rectifier schematic will look + like Fig. <a +href="#x1-6800113">9.13<!--tex4ht:ref: hwr_schematic --></a>.<br +class="newline" /> + <!--l. 178--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6800113"></a> <img +src="figures/hwr_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.13: </span><span +class="content">Schematic of Half Wave Rectifier circuit</span></div><!--tex4ht:label?: x1-6800113 --> + <!--l. 183--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 187--><p class="noindent" >KiCad netlist is generated as shown in the Fig. <a +href="#x1-6800214">9.14<!--tex4ht:ref: hwr_netlistgeneration --></a> <br +class="newline" /> + <!--l. 189--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6800214"></a> <img +src="figures/hwr_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.14: </span><span +class="content">Half Wave Rectifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-6800214 --> + <!--l. 194--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on the <span +class="cmtt-10x-x-109">KiCad-Ngspice</span> + <span +class="cmtt-10x-x-109">converter </span>button. This will open converter window where you can enter details of + Analysis, Source values and Device library. + <!--l. 198--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-6800615"></a> <a + id="x1-68003r1"></a> <img +src="figures/hwr_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-68004r2"></a> <img +src="figures/hwr_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> <a + id="x1-68005r3"></a> <img +src="figures/hwr_devicemodelingtab.png" alt="PIC" +> + <span +class="cmr-9">(c)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Device</span> + <span +class="cmr-9">Modeling</span> +<br /> <div class="caption" +><span class="id">Figure 9.15: </span><span +class="content">Analysis, Source and Device Tab</span></div><!--tex4ht:label?: x1-6800615 --> + <!--l. 210--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 212--><p class="noindent" >Under device library you can add the library for diode used in the circuit. If you do not + add any library it will take default Ngspice model. + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-6800916"></a> <a + id="x1-68007r1"></a> <img +src="figures/hwr_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> +<span +class="cmr-9">of</span> +<span +class="cmr-9">Half</span> +<span +class="cmr-9">Wave</span> +<span +class="cmr-9">Rectifier</span> <a + id="x1-68008r2"></a> <img +src="figures/hwr_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Wave</span> + <span +class="cmr-9">Rectifier</span> +<br /> <div class="caption" +><span class="id">Figure 9.16: </span><span +class="content">Half Wave Rectifier Simulation Output</span></div><!--tex4ht:label?: x1-6800916 --> + <!--l. 225--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + +<!--l. 232--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.3 </span> <a + id="x1-690009.1.3"></a>Precision Rectifier</h4> +<!--l. 233--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-700009.1.3"></a>Problem Statement:</h5> +<!--l. 233--><p class="noindent" >Plot the input and output waveform of the Precision Rectifier circuit where input voltage +(Vs) is 50<span +class="cmmi-10x-x-109">Hz </span>, 3<span +class="cmmi-10x-x-109">V </span>peak to peak. +<!--l. 235--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-710009.1.3"></a>Solution:</h5> +<!--l. 236--><p class="noindent" >The new project is created by clicking the <span +class="cmtt-10x-x-109">New </span>icon on the menubar. The name of the project +is given as shown in the Fig. <a +href="#x1-650011">9.1<!--tex4ht:ref: rc1 --></a>. + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" />After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" />After all the required components of the precision rectifier circuit are placed, + wiring is done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br +class="newline" />Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. The + Fig. <a +href="#x1-7100117">9.17<!--tex4ht:ref: pr_schematic --></a> shows the complete Precision Rectifier schematic after removing the + errors. + <!--l. 246--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7100117"></a> <img +src="figures/pr_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.17: </span><span +class="content">Schematic of Precision Rectifier circuit</span></div><!--tex4ht:label?: x1-7100117 --> + <!--l. 251--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 253--><p class="noindent" >The KiCad netlist is generated as shown in Fig. <a +href="#x1-7100218">9.18<!--tex4ht:ref: pr_netlistgeneration --></a>.<br +class="newline" /> + <!--l. 255--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7100218"></a> <img +src="figures/pr_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.18: </span><span +class="content">Precision Rectifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7100218 --> + <!--l. 260--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice + converter button.<br +class="newline" /> + <!--l. 266--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values, + Device library and Subcircuit. + <!--l. 268--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7100719"></a> <a + id="x1-71003r1"></a> <img +src="figures/pr_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-71004r2"></a> <img +src="figures/pr_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<a + id="x1-71005r3"></a> +<!--l. 278--><p class="noindent" > <img +src="figures/pr_devicemodelingtab.png" alt="PIC" +> +<span +class="cmr-9">(c)</span> +<span +class="cmr-9">Precision</span> +<span +class="cmr-9">Rectifier</span> +<span +class="cmr-9">Device</span> +<span +class="cmr-9">Modeling</span> <a + id="x1-71006r4"></a> <img +src="figures/pr_subcircuitstab.png" alt="PIC" +> + <span +class="cmr-9">(d)</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> + <span +class="cmr-9">Subcircuit</span> +<br /> <div class="caption" +><span class="id">Figure 9.19: </span><span +class="content">Analysis, Source, Device library and Subcircuit tab</span></div><!--tex4ht:label?: x1-7100719 --> + <!--l. 283--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 285--><p class="noindent" >Under device library you can add the library for the diode used in the circuit. If you do + not add any library it will take default Ngspice model for diode.<br +class="newline" /> + <!--l. 288--><p class="noindent" >Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to + add subcircuit it will throw an error. + + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run the + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-7101020"></a> <a + id="x1-71008r1"></a> <img +src="figures/pr_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> +<span +class="cmr-9">of</span> +<span +class="cmr-9">Precision</span> +<span +class="cmr-9">Rectifier</span> <a + id="x1-71009r2"></a> <img +src="figures/pr_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">Precision</span> + <span +class="cmr-9">Rectifier</span> +<br /> <div class="caption" +><span class="id">Figure 9.20: </span><span +class="content">Precision Rectifier Simulation Output</span></div><!--tex4ht:label?: x1-7101020 --> + <!--l. 302--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + +<!--l. 309--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.4 </span> <a + id="x1-720009.1.4"></a>Inverting Amplifier</h4> +<!--l. 310--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-730009.1.4"></a>Problem Statement:</h5> +<!--l. 311--><p class="noindent" >Plot the Input and Output Waveform of Inverting Amplifier circuit where the input voltage +(Vs) is 50<span +class="cmmi-10x-x-109">Hz</span>, 2<span +class="cmmi-10x-x-109">V </span>peak to peak and gain is 2. + <h5 class="subsubsectionHead"><a + id="x1-740009.1.4"></a>Solution:</h5> + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" />After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" />After all the required components of the inverting amplifier circuit are placed, + wiring is done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br +class="newline" />Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. + <!--l. 321--><p class="noindent" >The Fig. <a +href="#x1-7400121">9.21<!--tex4ht:ref: ia_schematic --></a> shows the complete Precision Rectifier schematic after removing + the errors. + <!--l. 323--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7400121"></a> <img +src="figures/ia_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.21: </span><span +class="content">Schematic of Inverting Amplifier circuit</span></div><!--tex4ht:label?: x1-7400121 --> + <!--l. 328--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 330--><p class="noindent" >The KiCad netlist is generated as shown in Fig. <a +href="#x1-7400222">9.22<!--tex4ht:ref: ia_netlistgeneration --></a>.<br +class="newline" /><hr class="figure"><div class="figure" +><a + id="x1-7400222"></a> <img +src="figures/ia_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.22: </span><span +class="content">Inverting Amplifier circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7400222 --> + <!--l. 336--><p class="noindent" ></div><hr class="endfigure"> + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice + converter button.<br +class="newline" /> + <!--l. 342--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values, + Device library and Subcircuit. + + <!--l. 344--><p class="noindent" >Subcircuit of Op-Amp is shown in Fig. <a +href="#x1-74006r4">9.23d<!--tex4ht:ref: ia_sub --></a> <hr class="figure"><div class="figure" +><a + id="x1-7400723"></a> <a + id="x1-74003r1"></a> <img +src="figures/ia_analysistab.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Analysis</span> <a + id="x1-74004r2"></a> <img +src="figures/ia_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Inverting</span> + <span +class="cmr-9">Amplifier</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<a + id="x1-74005r3"></a> +<!--l. 355--><p class="noindent" > <img +src="figures/ia_subcircuitstab.png" alt="PIC" +> +<span +class="cmr-9">(c)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Subcircuit</span> <a + id="x1-74006r4"></a> <img +src="figures/ia_sub.png" alt="PIC" +> + <span +class="cmr-9">(d)</span> + <span +class="cmr-9">Sub-Circuit</span> + <span +class="cmr-9">of</span> + <span +class="cmr-9">Op-Amp</span> +<br /> <div class="caption" +><span class="id">Figure 9.23: </span><span +class="content">Analysis, Source, and Subcircuit tab</span></div><!--tex4ht:label?: x1-7400723 --> + <!--l. 360--><p class="noindent" ></div><hr class="endfigure"> + + <!--l. 363--><p class="noindent" >Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to + add subcircuit, it will throw an error.<br +class="newline" /> + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-7401024"></a> <a + id="x1-74008r1"></a> <img +src="figures/ia_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> +<a + id="x1-74009r2"></a> +<!--l. 374--><p class="noindent" > <img +src="figures/ia_pythonplot.png" alt="PIC" +> +<span +class="cmr-9">(b)</span> +<span +class="cmr-9">Inverting</span> +<span +class="cmr-9">Amplifier</span> +<span +class="cmr-9">Python</span> +<span +class="cmr-9">Plot</span> +<br /> <div class="caption" +><span class="id">Figure 9.24: </span><span +class="content">Inverting Amplifier Simulation Output</span></div><!--tex4ht:label?: x1-7401024 --> + <!--l. 376--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + +<!--l. 386--><p class="noindent" > + <h4 class="subsectionHead"><span class="titlemark">9.1.5 </span> <a + id="x1-750009.1.5"></a>Half Adder Example</h4> +<!--l. 388--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-760009.1.5"></a>Problem Statement:</h5> +<!--l. 388--><p class="noindent" >Plot the Input and Output Waveform of Half Adder circuit. +<!--l. 390--><p class="noindent" > + <h5 class="subsubsectionHead"><a + id="x1-770009.1.5"></a>Solution:</h5> + <ul class="itemize1"> + <li class="itemize">Creating Schematic: To create the schematic, click the very first icon of the left + toolbar as shown in the Fig. <a +href="#x1-650022">9.2<!--tex4ht:ref: rc2 --></a>. This will open KiCad Eeschema.<br +class="newline" />After the KiCad window is opened, to create a schematic we need to place the + required components. Fig. <a +href="#x1-650033">9.3<!--tex4ht:ref: rc_component --></a> shows the icon on the right toolbar which opens + the component library.<br +class="newline" />After all the required components of the Half Adder circuit are placed, wiring is + done using the <span +class="cmtt-10x-x-109">Place Wire </span>option as shown in the Fig. <a +href="#x1-650044">9.4<!--tex4ht:ref: rc_wire --></a>.<br +class="newline" />Next step is <span +class="cmtt-10x-x-109">ERC (Electric Rules Check)</span>. Fig. <a +href="#x1-650055">9.5<!--tex4ht:ref: erc1 --></a> shows the icon for <span +class="cmtt-10x-x-109">ERC</span>. + <!--l. 399--><p class="noindent" >The Fig. <a +href="#x1-7700125">9.25<!--tex4ht:ref: ha_schematic --></a> shows the complete Half Adder schematic after removing the + errors. <hr class="figure"><div class="figure" +><a + id="x1-7700125"></a> <img +src="figures/ha_schematic.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.25: </span><span +class="content">Schematic of Half Adder circuit</span></div><!--tex4ht:label?: x1-7700125 --> + <!--l. 405--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 407--><p class="noindent" >The KiCad netlist is generated as shown in Fig. <a +href="#x1-7700226">9.26<!--tex4ht:ref: ha_netlistgeneration --></a>.<br +class="newline" /><hr class="figure"><div class="figure" +><a + id="x1-7700226"></a> <img +src="figures/ha_netlistgeneration.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.26: </span><span +class="content">Half Adder circuit Netlist Generation</span></div><!--tex4ht:label?: x1-7700226 --> + <!--l. 413--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Convert KiCad to Ngspice: After creating KiCad netlist click on KiCad-Ngspice + converter button.<br +class="newline" /> + <!--l. 420--><p class="noindent" >This will open converter window where you can enter details of Analysis, Source values, + Ngspice model and Subcircuit. + <!--l. 422--><p class="noindent" ><hr class="figure"><div class="figure" +><a + id="x1-7700727"></a> <a + id="x1-77003r1"></a> <img +src="figures/ha_analysistab.png" alt="PIC" +> + <span +class="cmr-9">(a)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Analysis</span> <a + id="x1-77004r2"></a> <img +src="figures/ha_sourcedetailstab.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Source</span> + <span +class="cmr-9">Details</span> +<a + id="x1-77005r3"></a> +<!--l. 432--><p class="noindent" > <img +src="figures/ha_ngspicemodeltab.png" alt="PIC" +> +<span +class="cmr-9">(c)</span> +<span +class="cmr-9">Half</span> +<span +class="cmr-9">Adder</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Model</span> <a + id="x1-77006r4"></a> <img +src="figures/ha_subcircuitstab.png" alt="PIC" +> + <span +class="cmr-9">(d)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Subcircuit</span> + <span +class="cmr-9">Model</span> +<br /> <div class="caption" +><span class="id">Figure 9.27: </span><span +class="content">Analysis, Source, Ngspice Model and Subcircuit tab</span></div><!--tex4ht:label?: x1-7700727 --> + <!--l. 437--><p class="noindent" ></div><hr class="endfigure"> + <!--l. 439--><p class="noindent" >Subcircuit of Half Adder in Fig. <a +href="#x1-7700828">9.28<!--tex4ht:ref: ha_sub --></a> <hr class="figure"><div class="figure" +><a + id="x1-7700828"></a> <img +src="figures/ha_sub.png" alt="PIC" +> +<br /> <div class="caption" +><span class="id">Figure 9.28: </span><span +class="content">Half Adder Subcircuit</span></div><!--tex4ht:label?: x1-7700828 --> + <!--l. 445--><p class="noindent" ></div><hr class="endfigure"> + + </li> + <li class="itemize">Simulation: Once the KiCad-Ngspice converter runs successfully, you can run + simulation by clicking the simulation button in the toolbar. <hr class="figure"><div class="figure" +><a + id="x1-7701129"></a> <a + id="x1-77009r1"></a> <img +src="figures/ha_ngspiceplot.png" alt="PIC" +> +<span +class="cmr-9">(a)</span> +<span +class="cmr-9">Half</span> +<span +class="cmr-9">Adder</span> +<span +class="cmr-9">Ngspice</span> +<span +class="cmr-9">Plot</span> <a + id="x1-77010r2"></a> <img +src="figures/ha_pythonplot.png" alt="PIC" +> + <span +class="cmr-9">(b)</span> + <span +class="cmr-9">Half</span> + <span +class="cmr-9">Adder</span> + <span +class="cmr-9">Python</span> + <span +class="cmr-9">Plot</span> +<br /> <div class="caption" +><span class="id">Figure 9.29: </span><span +class="content">Half Adder Simulation Output</span></div><!--tex4ht:label?: x1-7701129 --> + <!--l. 459--><p class="noindent" ></div><hr class="endfigure"> + </li></ul> + + <h2 class="likechapterHead"><a + id="x1-780009.1.5"></a>References</h2><a + id="Q1-1-166"></a> + <div class="thebibliography"> + <p class="bibitem" ><span class="biblabel"> + [1]<span class="bibsp">   </span></span><a + id="Xsedra"></a>A. S. Sedra and K. C. Smith, <span +class="cmti-10x-x-109">Microelectronic Circuits - Theory and</span> + <span +class="cmti-10x-x-109">Applications</span>. Oxford University Press, 2009. + </p> + <p class="bibitem" ><span class="biblabel"> + [2]<span class="bibsp">   </span></span><a + id="Xkmm11-csi"></a>K. M. Moudgalya, “Spoken Tutorial: A Collaborative and Scalable Education + Technology,” <span +class="cmti-10x-x-109">CSI Communications</span>, vol. 35, no. 6, pp. 10–12, September 2011, + available at <a +href="http://spoken-tutorial.org/CSI.pdf" class="url" >http://spoken-tutorial.org/CSI.pdf</a>. + </p> + <p class="bibitem" ><span class="biblabel"> + [3]<span class="bibsp">   </span></span><a + id="Xscilab"></a>(2013, May). [Online]. Available: <a +href="http://www.scilab.org/" class="url" >http://www.scilab.org/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [4]<span class="bibsp">   </span></span><a + id="XGARUDA"></a>(2013, May). [Online]. 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http://scilab-test.garudaindia.in/cloud" class="url" >http://scilab-test.garudaindia.in/scilab_in/,http://scilab-test.garudaindia.in/cloud</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [5]<span class="bibsp">   </span></span><a + id="XT10KT"></a>D. B. Phatak. (2013, May) Teach 10,000 teacher programme. [Online]. + Available: <a +href="http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do" class="url" >http://www.it.iitb.ac.in/nmeict/MegaWorkshop.do</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [6]<span class="bibsp">   </span></span><a + id="XT10KT-kal"></a>K. Kannan and K. Narayanan, “Ict-enabled scalable workshops for engineering + college teachers in india,” in <span +class="cmti-10x-x-109">Post-Secondary Education and Technology: A Global</span> + <span +class="cmti-10x-x-109">Perspective on Opportunities and Obstacles to Development (International and</span> + <span +class="cmti-10x-x-109">Development Education)</span>, R. Clohey, S. Austin-Li, and J. C. Weldman, Eds. + Palgrave Macmillan, 2012. + + </p> + <p class="bibitem" ><span class="biblabel"> + [7]<span class="bibsp">   </span></span><a + id="XT10KT-kgp"></a>(2013, May) Teach 10,000 teacher programme on analog electronics. [Online]. + Available: <a +href="http://www.nmeict.iitkgp.ernet.in/Analogmain.htm" class="url" >http://www.nmeict.iitkgp.ernet.in/Analogmain.htm</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [8]<span class="bibsp">   </span></span><a + id="Xaakash"></a>(2013, May). [Online]. Available: <a +href="http://www.aakashlabs.org/" class="url" >http://www.aakashlabs.org/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [9]<span class="bibsp">   </span></span><a + id="Xeda"></a>(2013, May). [Online]. Available: + <a +href="http://en.wikipedia.org/wiki/Electronic_design_automation" class="url" >http://en.wikipedia.org/wiki/Electronic_design_automation</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [10]<span class="bibsp">   </span></span><a + id="Xsynaptic"></a>(2013, May) Synaptic Package Manager Spoken Tutorial. [Online]. Available: + <a +href="http://www.spoken-tutorial.org/list_videos?view=1&foss=Linux&language=English" class="url" >http://www.spoken-tutorial.org/list_videos?view=1&foss=Linux&language=English</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [11]<span class="bibsp">   </span></span><a + id="Xeeschema"></a>(2013, May). [Online]. Available: + <a +href="http://www.kicad-pcb.org/display/KICAD/KiCad+EDA+Software+Suite" class="url" >http://www.kicad-pcb.org/display/KICAD/KiCad+EDA+Software+Suite</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [12]<span class="bibsp">   </span></span><a + id="Xngspice-web"></a>(2013, May). [Online]. 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Available: + <a +href="http://www.kicad-pcb.org/display/KICAD/KiCad+Documentation" class="url" >http://www.kicad-pcb.org/display/KICAD/KiCad+Documentation</a> + + </p> + <p class="bibitem" ><span class="biblabel"> + [16]<span class="bibsp">   </span></span><a + id="Xkicad2"></a>D. Jahshan and P. Hutchinson. (2013, May). [Online]. Available: + <a +href="http://bazaar.launchpad.net/~kicad-developers/kicad/doc/files/head:/doc/tutorials/" class="url" >http://bazaar.launchpad.net/<span +class="cmsy-8">∼</span>kicad-developers/kicad/doc/files/head:/doc/tutorials/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [17]<span class="bibsp">   </span></span><a + id="Xngspice"></a>P. Nenzi and H. Vogt. (2013) Ngspice users manual version 25plus. [Online]. + Available: <a +href="http://ngspice.sourceforge.net/docs/ngspice-manual.pdf" class="url" >http://ngspice.sourceforge.net/docs/ngspice-manual.pdf</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [18]<span class="bibsp">   </span></span><a + id="Xkmm11-TUGboat"></a>K. M. Moudgalya, “<span class="LATEX">L<span class="A">A</span><span class="TEX">T<span +class="E">E</span>X</span></span> Training through Spoken Tutorials,” <span +class="cmti-10x-x-109">TUGboat</span>, + vol. 32, no. 3, pp. 251–257, 2011. + </p> + <p class="bibitem" ><span class="biblabel"> + [19]<span class="bibsp">   </span></span><a + id="Xst"></a>(2013, May). [Online]. Available: <a +href="http://www.spoken-tutorial.org/" class="url" >http://www.spoken-tutorial.org/</a> + </p> + <p class="bibitem" ><span class="biblabel"> + [20]<span class="bibsp">   </span></span><a + id="Xoscad"></a>(2013, May). [Online]. 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#eeeeee; + padding: 10px; + background-color: #165982; + border: 4px outset #0E324B; +} + +p{ + margin: 0px 10px 0px 10px; +} + +pre{ + margin: 0px 10px 0px 10px; + font-family: monospaced; + font-size: 10pt; +} +#license{ + font-size:8pt; +} + +</style> +<head> + +<body> +<h1>About eSim</h1> +<center><img src="../../../images/logo.png" alt="eSim logo" height="100" width="100"></center> +<br/> +<p> +<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>) and Ngspice(<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>). eSim source is released under <b>GNU General Public License.</b> +</p> +<br/> +<p> +This tool is developed by the <b>FOSSEE team at IIT Bombay</b>. To know more about eSim, please visit: <a href=http://esim.fossee.in>http://esim.fossee.in</a>. + </p> +<br/> +<p> +To discuss more about eSim please visits at <a href=http://forums.fossee.in>http://forums.fossee.in</a> +</p> +<br /> +</body> + +</html> diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py new file mode 100644 index 00000000..d9479137 --- /dev/null +++ b/src/configuration/Appconfig.py @@ -0,0 +1,85 @@ +#=============================================================================== +# +# FILE: Appconfig.py +# +# USAGE: --- +# +# DESCRIPTION: This define all configuration used in Application. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Wednesday 04 February 2015 +# REVISION: --- +#=============================================================================== + + +from PyQt4 import QtGui +import os +import json +from ConfigParser import SafeConfigParser + + +class Appconfig(QtGui.QWidget): + """ + All configuration goes here. + May change in future for code optimization. + """ + + #Home directory + home = os.path.join(os.path.expanduser("~"),"eSim-Workspace") + default_workspace = {"workspace":home} + #Current Project detail + current_project = {"ProjectName":None} + #Current Subcircuit detail + current_subcircuit = {"SubcircuitName":None} + #Workspace detail + workspace_text = '''eSim stores your project in a folder called a eSim-Workspace. You can choose a different workspace folder to use for this session.''' + procThread_list = [] + proc_dict={} #holds the pids of all external windows corresponds to the current project + dock_dict={} #holds all dockwidgets + dictPath = os.path.join(os.path.expanduser("~"), ".projectExplorer.txt") + noteArea = {} + + parser_esim = SafeConfigParser() + parser_esim.read(os.path.join(os.path.expanduser("~"), os.path.join('.esim','config.ini'))) + modelica_map_json = parser_esim.get('eSim', 'MODELICA_MAP_JSON') + try: + project_explorer = json.load(open(dictPath)) + except: + project_explorer= {} + process_obj = [] + + def __init__(self): + super(Appconfig, self).__init__() + #Application Details + self._APPLICATION = 'eSim' + self._VERSION = 'v1.1' + self._AUTHOR = 'Fahim' + + #Application geometry setting + self._app_xpos = 100 + self._app_ypos = 100 + self._app_width = 600 + self._app_heigth = 400 + + + def print_info(self, info): + self.noteArea['Note'].append('[INFO]: ' + info) + + + def print_warning(self, warning): + self.noteArea['Note'].append('[WARNING]: ' + warning) + + + def print_error(self, error): + self.noteArea['Note'].append('[ERROR]: ' + error) + + + + + + diff --git a/src/configuration/Appconfig.pyc b/src/configuration/Appconfig.pyc Binary files differnew file mode 100644 index 00000000..acbb0429 --- /dev/null +++ b/src/configuration/Appconfig.pyc diff --git a/src/configuration/__init__.py b/src/configuration/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/configuration/__init__.py diff --git a/src/configuration/__init__.pyc b/src/configuration/__init__.pyc Binary files differnew file mode 100644 index 00000000..cf504365 --- /dev/null +++ b/src/configuration/__init__.pyc diff --git a/src/deviceModelLibrary/Diode/D.lib b/src/deviceModelLibrary/Diode/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/src/deviceModelLibrary/Diode/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/deviceModelLibrary/Diode/D.xml b/src/deviceModelLibrary/Diode/D.xml new file mode 100644 index 00000000..8b6b14c8 --- /dev/null +++ b/src/deviceModelLibrary/Diode/D.xml @@ -0,0 +1,15 @@ +<library> +<model_name>D</model_name> +<ref_model>1N4148</ref_model> +<param> + <Is>2.495E-09</Is> + <Rs>4.755E-01</Rs> + <N>1.679E+00</N> + <tt>3.030E-09</tt> + <Cjo>1.700E-12</Cjo> + <M>1.959E-01</M> + <Vj>1</Vj> + <Bv>1.000E+02</Bv> + <Ibv>1.000E-04</Ibv> +</param> +</library> diff --git a/src/deviceModelLibrary/Diode/LED.lib b/src/deviceModelLibrary/Diode/LED.lib new file mode 100644 index 00000000..000831b2 --- /dev/null +++ b/src/deviceModelLibrary/Diode/LED.lib @@ -0,0 +1,2 @@ +.model LED D(is=4.36625E-25 rs=3.00014 n=1.38167 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/deviceModelLibrary/Diode/LED.xml b/src/deviceModelLibrary/Diode/LED.xml new file mode 100644 index 00000000..91eb9169 --- /dev/null +++ b/src/deviceModelLibrary/Diode/LED.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>LED</ref_model><param><cjo>1.700E-12</cjo><rs>4.755E-01</rs><is>2.495E-09</is><m>1.959E-01</m><n>1.679E00</n><bv>1.000E02</bv><ibv>1.000E-04</ibv><tt>3.030E-09</tt><vj>1</vj></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Diode/PowerDiode.lib b/src/deviceModelLibrary/Diode/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/src/deviceModelLibrary/Diode/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/Diode/PowerDiode.xml b/src/deviceModelLibrary/Diode/PowerDiode.xml new file mode 100644 index 00000000..06dceda1 --- /dev/null +++ b/src/deviceModelLibrary/Diode/PowerDiode.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>PowerDiode</ref_model><param><Vj>.75</Vj><Nbvl>14.976</Nbvl><Cjo>175p</Cjo><Rs>.25</Rs><Isr>1.859n</Isr><Eg>1.11</Eg><M>.5516</M><Nbv>1.6989</Nbv><N>1</N><Tbv1>-21.277u</Tbv1><bv>1800</bv><Fc>.5</Fc><Ikf>0</Ikf><Nr>2</Nr><Ibv>20.245m</Ibv><Is>2.2E-15</Is><Xti>3</Xti><Ibvl>1.9556m</Ibvl></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Diode/ZenerD1N750.lib b/src/deviceModelLibrary/Diode/ZenerD1N750.lib new file mode 100644 index 00000000..890c37fe --- /dev/null +++ b/src/deviceModelLibrary/Diode/ZenerD1N750.lib @@ -0,0 +1,3 @@ +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/src/deviceModelLibrary/Diode/ZenerD1N750.xml b/src/deviceModelLibrary/Diode/ZenerD1N750.xml new file mode 100644 index 00000000..546d1156 --- /dev/null +++ b/src/deviceModelLibrary/Diode/ZenerD1N750.xml @@ -0,0 +1,24 @@ +<library> +<model_name>D</model_name> +<ref_model>D1N750</ref_model> +<param> + <Is>880.5E-18</Is> + <Rs>.25</Rs> + <Ikf>0</Ikf> + <N>1</N> + <Xti>3</Xti> + <Eg>1.11</Eg> + <Cjo>175p</Cjo> + <M>.5516</M> + <Vj>.75</Vj> + <Fc>.5</Fc> + <Isr>1.859n</Isr> + <Nr>2</Nr> + <Bv>8.1</Bv> + <Ibv>20.245m</Ibv> + <Nbv>1.6989</Nbv> + <Ibvl>1.9556m</Ibvl> + <Nbvl>14.976</Nbvl> + <Tbv1>-21.277u</Tbv1> +</param> +</library> diff --git a/src/deviceModelLibrary/IGBT/NIGBT.lib b/src/deviceModelLibrary/IGBT/NIGBT.lib new file mode 100644 index 00000000..86cd1b4e --- /dev/null +++ b/src/deviceModelLibrary/IGBT/NIGBT.lib @@ -0,0 +1,11 @@ +.MODEL IXGH40N60 NIGBT( ++ TAU=287.56E-9 ++ KF=.36047 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ KP=50.034 ++ VT=4.1822 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570 +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/IGBT/NIGBT.xml b/src/deviceModelLibrary/IGBT/NIGBT.xml new file mode 100644 index 00000000..38d9d094 --- /dev/null +++ b/src/deviceModelLibrary/IGBT/NIGBT.xml @@ -0,0 +1,4 @@ +<library> +<model_name>NIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param><TAU>287.56E-9</TAU><KF>.36047</KF><AREA>37.500E-6</AREA><AGD>18.750E-6</AGD><KP>50.034</KP><VT>4.1822</VT><CGS>31.942E-9</CGS><COXD>53.188E-9</COXD><VTD>2.6570</VTD></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/IGBT/PIGBT.lib b/src/deviceModelLibrary/IGBT/PIGBT.lib new file mode 100644 index 00000000..d4f9e814 --- /dev/null +++ b/src/deviceModelLibrary/IGBT/PIGBT.lib @@ -0,0 +1,10 @@ +.MODEL IXGH40N60 PIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/src/deviceModelLibrary/IGBT/PIGBT.xml b/src/deviceModelLibrary/IGBT/PIGBT.xml new file mode 100644 index 00000000..1e57f2e3 --- /dev/null +++ b/src/deviceModelLibrary/IGBT/PIGBT.xml @@ -0,0 +1,15 @@ +<library> +<model_name>PIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param> +<TAU>287.56E-9</TAU> +<KP>50.034</KP> +<AREA>37.500E-6</AREA> +<AGD>18.750E-6</AGD> +<VT>4.1822</VT> +<KF>.36047</KF> +<CGS>31.942E-9</CGS> +<COXD>53.188E-9</COXD> +<VTD>2.6570 </VTD> +</param> +</library> diff --git a/src/deviceModelLibrary/JFET/NJF.lib b/src/deviceModelLibrary/JFET/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/src/deviceModelLibrary/JFET/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/src/deviceModelLibrary/JFET/NJF.xml b/src/deviceModelLibrary/JFET/NJF.xml new file mode 100644 index 00000000..94753691 --- /dev/null +++ b/src/deviceModelLibrary/JFET/NJF.xml @@ -0,0 +1,29 @@ +<library> +<model_name>NJF</model_name> +<ref_model>J2N3819</ref_model> +<param> +<Beta>1.304m</Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m</Vtotc> +<Is>33.57f </Is> +<Isr>322.4f </Isr> +<N>1</N> +<Nr>2</Nr> +<Xti>3</Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1</Pb> +<Fc>.5</Fc> +<Cgs>2.414p</Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> + + +</param> +</library> diff --git a/src/deviceModelLibrary/JFET/PJF.lib b/src/deviceModelLibrary/JFET/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/src/deviceModelLibrary/JFET/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/src/deviceModelLibrary/JFET/PJF.xml b/src/deviceModelLibrary/JFET/PJF.xml new file mode 100644 index 00000000..f682f8cb --- /dev/null +++ b/src/deviceModelLibrary/JFET/PJF.xml @@ -0,0 +1,27 @@ +<library> +<model_name>PJF</model_name> +<ref_model>J2N3820</ref_model> +<param> +<Beta>1.304m </Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m </Vtotc> +<Is>33.57f </Is> +<Isr>322.4f</Isr> +<N>1 </N> +<Nr>2 </Nr> +<Xti>3 </Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1 </Pb> +<Fc>.5 </Fc> +<Cgs>2.414p </Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> +</param> +</library> diff --git a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib new file mode 100644 index 00000000..2e6f4635 --- /dev/null +++ b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/MOS/NMOS-0.5um.xml b/src/deviceModelLibrary/MOS/NMOS-0.5um.xml new file mode 100644 index 00000000..08fdf0e3 --- /dev/null +++ b/src/deviceModelLibrary/MOS/NMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<TPG>1</TPG> +<TOX>9.5n </TOX> +<CJ>550u </CJ> +<ETA>0.02125 </ETA> +<VMAX>1.8E05</VMAX> +<GAMMA>0.62</GAMMA> +<CGSO>0.3n </CGSO> +<LD>50n </LD> +<MJSW>0.35 </MJSW> +<PB>1.1</PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.3n </CGDO> +<KAPPA>0.1 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>0.6 </VTO> +<NFS>7.20E11 </NFS> +<THETA>0.23 </THETA> +<CJSW>0.3n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.0 </RSH> +<MJ>0.6 </MJ> +<UO>420</UO> +<KP>156u </KP> +<DELTA>0.88</DELTA> +<NSUB>1.40E17</NSUB> +</param> +</library> diff --git a/src/deviceModelLibrary/MOS/NMOS-180nm.lib b/src/deviceModelLibrary/MOS/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/src/deviceModelLibrary/MOS/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/src/deviceModelLibrary/MOS/NMOS-180nm.xml b/src/deviceModelLibrary/MOS/NMOS-180nm.xml new file mode 100644 index 00000000..d0249bb6 --- /dev/null +++ b/src/deviceModelLibrary/MOS/NMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>CMOSN</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>2.3549E17 </NCH> +<VTH0>0.3823463 </VTH0> +<K1>0.5810697 </K1> +<K2>4.774618E-3 </K2> +<K3>0.0431669 </K3> +<K3B>1.1498346</K3B> +<W0>1E-7 </W0> +<NLX>1.910552E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>1.2894824 </DVT0> +<DVT1>0.3622063 </DVT1> +<DVT2>0.0713729 </DVT2> +<U0>280.633249 </U0> +<UA>-1.208537E-9 </UA> +<UB>2.158625E-18</UB> +<UC>5.342807E-11 </UC> +<VSAT>9.366802E4</VSAT> +<A0>1.7593146 </A0> +<AGS>0.3939741 </AGS> +<B0>-6.413949E-9 </B0> +<B1>-1E-7 </B1> +<KETA>-5.180424E-4</KETA> +<A1>0 </A1> +<A2>1 </A2> +<RDSW>105.5517558</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.1998871 </PRWB> +<WR>1 </WR> +<WINT>7.904732E-10 </WINT> +<LINT>1.571424E-8 </LINT> +<XL>0</XL> +<XW>-1E-8 </XW> +<DWG>1.297221E-9 </DWG> +<DWB>1.479041E-9</DWB> +<VOFF>-0.0955434 </VOFF> +<NFACTOR>2.4358891 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0</CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>=3.104851E-3 </ETA0> +<ETAB>-2.512384E-5 </ETAB> +<DSUB>0.0167075 </DSUB> +<PCLM>0.8073191 </PCLM> +<PDIBLC1>0.1666161 </PDIBLC1> +<PDIBLC2>3.112892E-3 </PDIBLC2> +<PDIBLCB>-0.1 </PDIBLCB> +<DROUT>0.7875618 </DROUT> +<PSCBE1>8E10 </PSCBE1> +<PSCBE2>9.213635E-10 </PSCBE2> +<PVAG>3.85243E-3 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>6.7 </RSH> +<MOBMOD>1</MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9 </UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1</WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5 </XPART> +<CGDO>7.08E-10 </CGDO> +<CGSO>7.08E-10 </CGSO>/ +<CGBO>1E-12</CGBO> +<CJ>9.68858E-4 </CJ> +<PB>0.8 </PB> +<MJ>0.3864502 </MJ> +<CJSW>2.512138E-10 </CJSW> +<PBSW>0.809286 </PBSW> +<MJSW>0.1060414 </MJSW> +<CJSWG>3.3E-10 </CJSWG> +<PBSWG>0.809286 </PBSWG> +<MJSWG>0.1060414 </MJSWG> +<CF>0 </CF> +<PVTH0>-1.192722E-3 </PVTH0> +<PRDSW>-5 </PRDSW> +<PK2>6.450505E-5 </PK2> +<WKETA>-4.27294E-4 </WKETA> +<LKETA>-0.0104078 </LKETA> +<PU0>6.3268729 </PU0> +<PUA>2.226552E-11 </PUA> +<PUB>0 </PUB> +<PVSAT>969.1480157</PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-1.049509E-3</PKETA> +</param> +</library> diff --git a/src/deviceModelLibrary/MOS/NMOS-5um.lib b/src/deviceModelLibrary/MOS/NMOS-5um.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/src/deviceModelLibrary/MOS/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/MOS/NMOS-5um.xml b/src/deviceModelLibrary/MOS/NMOS-5um.xml new file mode 100644 index 00000000..358fbdbe --- /dev/null +++ b/src/deviceModelLibrary/MOS/NMOS-5um.xml @@ -0,0 +1,24 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<Cgso>0.4n</Cgso> +<Tox>85n</Tox> +<Vto>1</Vto> +<phi>0.7</phi> +<Level>1</Level> +<Mj>.5</Mj> +<UO>750</UO> +<Cgdo>0.4n</Cgdo> +<Gamma>1.4</Gamma> +<LAMBDA>0.01 </LAMBDA> +<LD>0.7u </LD> +<JS>1u </JS> +<CJ>0.4m</CJ> +<CJSW>0.8n</CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7</PB> +<CGBO>0.2n</CGBO> + +</param> +</library> diff --git a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib new file mode 100644 index 00000000..848e8b05 --- /dev/null +++ b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/MOS/PMOS-0.5um.xml b/src/deviceModelLibrary/MOS/PMOS-0.5um.xml new file mode 100644 index 00000000..013d461c --- /dev/null +++ b/src/deviceModelLibrary/MOS/PMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<TPG>-1 </TPG> +<TOX>9.5n </TOX> +<CJ>950u </CJ> +<ETA>0.025 </ETA> +<VMAX>0.3u </VMAX> +<GAMMA>0.52 </GAMMA> +<CGSO>0.35n </CGSO> +<LD>70n </LD> +<MJSW>0.25 </MJSW> +<PB>1 </PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.35n </CGDO> +<KAPPA>8.0 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>-0.6 </VTO> +<NFS>6.50E11 </NFS> +<THETA>0.2 </THETA> +<CJSW>0.2n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.5 </RSH> +<MJ>0.5</MJ> +<UO>130 </UO> +<KP>48u </KP> +<DELTA>0.25 </DELTA> +<NSUB>1.0E17</NSUB> +</param> +</library> diff --git a/src/deviceModelLibrary/MOS/PMOS-180nm.lib b/src/deviceModelLibrary/MOS/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/src/deviceModelLibrary/MOS/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/src/deviceModelLibrary/MOS/PMOS-180nm.xml b/src/deviceModelLibrary/MOS/PMOS-180nm.xml new file mode 100644 index 00000000..6696752d --- /dev/null +++ b/src/deviceModelLibrary/MOS/PMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>CMOSP</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>4.1589E17 </NCH> +<VTH0>-0.3938813 </VTH0> +<K1>0.5479015</K1> +<K2>0.0360586 </K2> +<K3>0.0993095 </K3> +<K3B>5.7086622</K3B> +<W0>1E-6 </W0> +<NLX>1.313191E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>0.4911363</DVT0> +<DVT1>0.2227356</DVT1> +<DVT2>0.1 </DVT2> +<U0>115.6852975 </U0> +<UA>1.505832E-9</UA> +<UB>1E-21 </UB> +<UC>-1E-10 </UC> +<VSAT>1.329694E5 </VSAT> +<A0>1.7590478 </A0> +<AGS>0.3641621 </AGS> +<B0>3.427126E-7 </B0> +<B1>1.062928E-6 </B1> +<KETA>0.0134667 </KETA> +<A1>0.6859506 </A1> +<A2>0.3506788 </A2> +<RDSW>168.5705677</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.4987371 </PRWB> +<WR>1 </WR> +<WINT>0 </WINT> +<LINT>3.028832E-8 </LINT> +<XL>0 </XL> +<XW>-1E-8 </XW> +<DWG>-2.349633E-8 </DWG> +<DWB>-7.152486E-9 </DWB> +<VOFF>-0.0994037 </VOFF> +<NFACTOR>1.9424315 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0 </CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>0.0608072 </ETA0> +<ETAB>-0.0426148</ETAB> +<DSUB>0.7343015 </DSUB> +<PCLM>3.2579974 </PCLM> +<PDIBLC1>7.229527E-6 </PDIBLC1> +<PDIBLC2>0.025389 </PDIBLC2> +<PDIBLCB>-1E-3 </PDIBLCB> +<DROUT>0 </DROUT> +<PSCBE1>1.454878E10</PSCBE1> +<PSCBE2>4.202027E-9 </PSCBE2> +<PVAG>15 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>7.8 </RSH> +<MOBMOD>1 </MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9</UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1 </WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5</XPART> +<CGDO>6.32E-10 </CGDO> +<CGSO>6.32E-10 </CGSO> +<CGBO>1E-12 </CGBO> +<CJ>1.172138E-3 </CJ> +<PB>0.8421173 </PB> +<MJ>0.4109788 </MJ> +<CJSW>2.242609E-10 </CJSW> +<PBSW>0.8</PBSW> +<MJSW>0.3752089 </MJSW> +<CJSWG>4.22E-10 </CJSWG> +<PBSWG>0.8 </PBSWG> +<MJSWG>0.3752089 </MJSWG> +<CF>0 </CF> +<PVTH0>1.888482E-3 </PVTH0> +<PRDSW>11.5315407 </PRDSW> +<PK2>1.559399E-3 </PK2> +<WKETA>0.0319301 </WKETA> +<LKETA>2.955547E-3 </LKETA> +<PU0>-1.1105313 </PU0> +<PUA>-4.62102E-11</PUA> +<PUB>1E-21 </PUB> +<PVSAT>50 </PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-4.346368E-3 </PKETA> +</param> +</library> diff --git a/src/deviceModelLibrary/MOS/PMOS-5um.lib b/src/deviceModelLibrary/MOS/PMOS-5um.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/src/deviceModelLibrary/MOS/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/MOS/PMOS-5um.xml b/src/deviceModelLibrary/MOS/PMOS-5um.xml new file mode 100644 index 00000000..f68bada2 --- /dev/null +++ b/src/deviceModelLibrary/MOS/PMOS-5um.xml @@ -0,0 +1,23 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<Cgso>0.4n </Cgso> +<Tox>85n </Tox> +<Vto>-1 </Vto> +<phi>0.65</phi> +<Level>1</Level> +<Mj>.5 </Mj> +<UO>250 </UO> +<Cgdo>0.4n </Cgdo> +<Gamma>0.65 </Gamma> +<LAMBDA>0.03 </LAMBDA> +<LD>0.6u </LD> +<JS>1u </JS> +<CJ>0.18m </CJ> +<CJSW>0.6n </CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7 </PB> +<CGBO>0.2n</CGBO> +</param> +</library> diff --git a/src/deviceModelLibrary/Misc/CORE.lib b/src/deviceModelLibrary/Misc/CORE.lib new file mode 100644 index 00000000..a7581029 --- /dev/null +++ b/src/deviceModelLibrary/Misc/CORE.lib @@ -0,0 +1,9 @@ +.MODEL K3019PL_3C8 Core( ++ A=44.82 ++ C=.4112 ++ abc=123 ++ Area=1.38 ++ K=25.74 ++ MS=415.2K ++ Path=4.52 +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/Misc/CORE.xml b/src/deviceModelLibrary/Misc/CORE.xml new file mode 100644 index 00000000..c95d9db0 --- /dev/null +++ b/src/deviceModelLibrary/Misc/CORE.xml @@ -0,0 +1,4 @@ +<library> +<model_name>Core</model_name> +<ref_model>K3019PL_3C8</ref_model> +<param><A>44.82 </A><C>.4112</C><abc>123</abc><Area>1.38</Area><K>25.74</K><MS>415.2K</MS><Path>4.52</Path></param></library> diff --git a/src/deviceModelLibrary/Templates/CORE.lib b/src/deviceModelLibrary/Templates/CORE.lib new file mode 100644 index 00000000..a7581029 --- /dev/null +++ b/src/deviceModelLibrary/Templates/CORE.lib @@ -0,0 +1,9 @@ +.MODEL K3019PL_3C8 Core( ++ A=44.82 ++ C=.4112 ++ abc=123 ++ Area=1.38 ++ K=25.74 ++ MS=415.2K ++ Path=4.52 +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/CORE.xml b/src/deviceModelLibrary/Templates/CORE.xml new file mode 100644 index 00000000..c95d9db0 --- /dev/null +++ b/src/deviceModelLibrary/Templates/CORE.xml @@ -0,0 +1,4 @@ +<library> +<model_name>Core</model_name> +<ref_model>K3019PL_3C8</ref_model> +<param><A>44.82 </A><C>.4112</C><abc>123</abc><Area>1.38</Area><K>25.74</K><MS>415.2K</MS><Path>4.52</Path></param></library> diff --git a/src/deviceModelLibrary/Templates/D.lib b/src/deviceModelLibrary/Templates/D.lib new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/src/deviceModelLibrary/Templates/D.lib @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/deviceModelLibrary/Templates/D.xml b/src/deviceModelLibrary/Templates/D.xml new file mode 100644 index 00000000..8b6b14c8 --- /dev/null +++ b/src/deviceModelLibrary/Templates/D.xml @@ -0,0 +1,15 @@ +<library> +<model_name>D</model_name> +<ref_model>1N4148</ref_model> +<param> + <Is>2.495E-09</Is> + <Rs>4.755E-01</Rs> + <N>1.679E+00</N> + <tt>3.030E-09</tt> + <Cjo>1.700E-12</Cjo> + <M>1.959E-01</M> + <Vj>1</Vj> + <Bv>1.000E+02</Bv> + <Ibv>1.000E-04</Ibv> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/NIGBT.lib b/src/deviceModelLibrary/Templates/NIGBT.lib new file mode 100644 index 00000000..8c09dcbc --- /dev/null +++ b/src/deviceModelLibrary/Templates/NIGBT.lib @@ -0,0 +1,10 @@ +.MODEL IXGH40N60 NIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/src/deviceModelLibrary/Templates/NIGBT.xml b/src/deviceModelLibrary/Templates/NIGBT.xml new file mode 100644 index 00000000..97f33196 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NIGBT.xml @@ -0,0 +1,15 @@ +<library> +<model_name>NIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param> +<TAU>287.56E-9</TAU> +<KP>50.034</KP> +<AREA>37.500E-6</AREA> +<AGD>18.750E-6</AGD> +<VT>4.1822</VT> +<KF>.36047</KF> +<CGS>31.942E-9</CGS> +<COXD>53.188E-9</COXD> +<VTD>2.6570</VTD> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/NJF.lib b/src/deviceModelLibrary/Templates/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/src/deviceModelLibrary/Templates/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/src/deviceModelLibrary/Templates/NJF.xml b/src/deviceModelLibrary/Templates/NJF.xml new file mode 100644 index 00000000..94753691 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NJF.xml @@ -0,0 +1,29 @@ +<library> +<model_name>NJF</model_name> +<ref_model>J2N3819</ref_model> +<param> +<Beta>1.304m</Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m</Vtotc> +<Is>33.57f </Is> +<Isr>322.4f </Isr> +<N>1</N> +<Nr>2</Nr> +<Xti>3</Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1</Pb> +<Fc>.5</Fc> +<Cgs>2.414p</Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> + + +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib new file mode 100644 index 00000000..2e6f4635 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/NMOS-0.5um.xml b/src/deviceModelLibrary/Templates/NMOS-0.5um.xml new file mode 100644 index 00000000..08fdf0e3 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<TPG>1</TPG> +<TOX>9.5n </TOX> +<CJ>550u </CJ> +<ETA>0.02125 </ETA> +<VMAX>1.8E05</VMAX> +<GAMMA>0.62</GAMMA> +<CGSO>0.3n </CGSO> +<LD>50n </LD> +<MJSW>0.35 </MJSW> +<PB>1.1</PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.3n </CGDO> +<KAPPA>0.1 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>0.6 </VTO> +<NFS>7.20E11 </NFS> +<THETA>0.23 </THETA> +<CJSW>0.3n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.0 </RSH> +<MJ>0.6 </MJ> +<UO>420</UO> +<KP>156u </KP> +<DELTA>0.88</DELTA> +<NSUB>1.40E17</NSUB> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/NMOS-180nm.lib b/src/deviceModelLibrary/Templates/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/src/deviceModelLibrary/Templates/NMOS-180nm.xml b/src/deviceModelLibrary/Templates/NMOS-180nm.xml new file mode 100644 index 00000000..d0249bb6 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>CMOSN</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>2.3549E17 </NCH> +<VTH0>0.3823463 </VTH0> +<K1>0.5810697 </K1> +<K2>4.774618E-3 </K2> +<K3>0.0431669 </K3> +<K3B>1.1498346</K3B> +<W0>1E-7 </W0> +<NLX>1.910552E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>1.2894824 </DVT0> +<DVT1>0.3622063 </DVT1> +<DVT2>0.0713729 </DVT2> +<U0>280.633249 </U0> +<UA>-1.208537E-9 </UA> +<UB>2.158625E-18</UB> +<UC>5.342807E-11 </UC> +<VSAT>9.366802E4</VSAT> +<A0>1.7593146 </A0> +<AGS>0.3939741 </AGS> +<B0>-6.413949E-9 </B0> +<B1>-1E-7 </B1> +<KETA>-5.180424E-4</KETA> +<A1>0 </A1> +<A2>1 </A2> +<RDSW>105.5517558</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.1998871 </PRWB> +<WR>1 </WR> +<WINT>7.904732E-10 </WINT> +<LINT>1.571424E-8 </LINT> +<XL>0</XL> +<XW>-1E-8 </XW> +<DWG>1.297221E-9 </DWG> +<DWB>1.479041E-9</DWB> +<VOFF>-0.0955434 </VOFF> +<NFACTOR>2.4358891 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0</CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>=3.104851E-3 </ETA0> +<ETAB>-2.512384E-5 </ETAB> +<DSUB>0.0167075 </DSUB> +<PCLM>0.8073191 </PCLM> +<PDIBLC1>0.1666161 </PDIBLC1> +<PDIBLC2>3.112892E-3 </PDIBLC2> +<PDIBLCB>-0.1 </PDIBLCB> +<DROUT>0.7875618 </DROUT> +<PSCBE1>8E10 </PSCBE1> +<PSCBE2>9.213635E-10 </PSCBE2> +<PVAG>3.85243E-3 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>6.7 </RSH> +<MOBMOD>1</MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9 </UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1</WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5 </XPART> +<CGDO>7.08E-10 </CGDO> +<CGSO>7.08E-10 </CGSO>/ +<CGBO>1E-12</CGBO> +<CJ>9.68858E-4 </CJ> +<PB>0.8 </PB> +<MJ>0.3864502 </MJ> +<CJSW>2.512138E-10 </CJSW> +<PBSW>0.809286 </PBSW> +<MJSW>0.1060414 </MJSW> +<CJSWG>3.3E-10 </CJSWG> +<PBSWG>0.809286 </PBSWG> +<MJSWG>0.1060414 </MJSWG> +<CF>0 </CF> +<PVTH0>-1.192722E-3 </PVTH0> +<PRDSW>-5 </PRDSW> +<PK2>6.450505E-5 </PK2> +<WKETA>-4.27294E-4 </WKETA> +<LKETA>-0.0104078 </LKETA> +<PU0>6.3268729 </PU0> +<PUA>2.226552E-11 </PUA> +<PUB>0 </PUB> +<PVSAT>969.1480157</PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-1.049509E-3</PKETA> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/NMOS-5um.lib b/src/deviceModelLibrary/Templates/NMOS-5um.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/src/deviceModelLibrary/Templates/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/Templates/NMOS-5um.xml b/src/deviceModelLibrary/Templates/NMOS-5um.xml new file mode 100644 index 00000000..358fbdbe --- /dev/null +++ b/src/deviceModelLibrary/Templates/NMOS-5um.xml @@ -0,0 +1,24 @@ +<library> +<model_name>NMOS</model_name> +<ref_model>mos_n</ref_model> +<param> +<Cgso>0.4n</Cgso> +<Tox>85n</Tox> +<Vto>1</Vto> +<phi>0.7</phi> +<Level>1</Level> +<Mj>.5</Mj> +<UO>750</UO> +<Cgdo>0.4n</Cgdo> +<Gamma>1.4</Gamma> +<LAMBDA>0.01 </LAMBDA> +<LD>0.7u </LD> +<JS>1u </JS> +<CJ>0.4m</CJ> +<CJSW>0.8n</CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7</PB> +<CGBO>0.2n</CGBO> + +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/NPN.lib b/src/deviceModelLibrary/Templates/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/deviceModelLibrary/Templates/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/deviceModelLibrary/Templates/NPN.xml b/src/deviceModelLibrary/Templates/NPN.xml new file mode 100644 index 00000000..b2698bb1 --- /dev/null +++ b/src/deviceModelLibrary/Templates/NPN.xml @@ -0,0 +1,33 @@ +<library> +<model_name>NPN</model_name> +<ref_model>Q2N2222</ref_model> +<param> +<Is>14.34f </Is> +<Xti>3 </Xti> +<Eg>1.11 </Eg> +<Vaf>74.03 </Vaf> +<Bf>400 </Bf> +<Ne>1.307 </Ne> +<Ise>14.34f </Ise> +<Ikf>.2847 </Ikf> +<Xtb>1.5 </Xtb> +<Br>6.092 </Br> +<Nc>2 </Nc> +<Isc>0 </Isc> +<Ikr>0 </Ikr> +<Rc>1 </Rc> +<Cjc>7.306p </Cjc> +<Mjc>.3416 </Mjc> +<Vjc>.75 </Vjc> +<Fc>.5 </Fc> +<Cje>22.01p </Cje> +<Mje>.377 </Mje> +<Vje>.75 </Vje> +<Tr>46.91n </Tr> +<Tf>411.1p </Tf> +<Itf>.6 </Itf> +<Vtf>1.7 </Vtf> +<Xtf>3 </Xtf> +<Rb>10 </Rb> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/PIGBT.lib b/src/deviceModelLibrary/Templates/PIGBT.lib new file mode 100644 index 00000000..d4f9e814 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PIGBT.lib @@ -0,0 +1,10 @@ +.MODEL IXGH40N60 PIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/src/deviceModelLibrary/Templates/PIGBT.xml b/src/deviceModelLibrary/Templates/PIGBT.xml new file mode 100644 index 00000000..1e57f2e3 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PIGBT.xml @@ -0,0 +1,15 @@ +<library> +<model_name>PIGBT</model_name> +<ref_model>IXGH40N60</ref_model> +<param> +<TAU>287.56E-9</TAU> +<KP>50.034</KP> +<AREA>37.500E-6</AREA> +<AGD>18.750E-6</AGD> +<VT>4.1822</VT> +<KF>.36047</KF> +<CGS>31.942E-9</CGS> +<COXD>53.188E-9</COXD> +<VTD>2.6570 </VTD> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/PJF.lib b/src/deviceModelLibrary/Templates/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/src/deviceModelLibrary/Templates/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/src/deviceModelLibrary/Templates/PJF.xml b/src/deviceModelLibrary/Templates/PJF.xml new file mode 100644 index 00000000..f682f8cb --- /dev/null +++ b/src/deviceModelLibrary/Templates/PJF.xml @@ -0,0 +1,27 @@ +<library> +<model_name>PJF</model_name> +<ref_model>J2N3820</ref_model> +<param> +<Beta>1.304m </Beta> +<Betatce>-.5</Betatce> +<Rd>1 </Rd> +<Rs>1 </Rs> +<Lambda>2.25m</Lambda> +<Vto>-3</Vto> +<Vtotc>-2.5m </Vtotc> +<Is>33.57f </Is> +<Isr>322.4f</Isr> +<N>1 </N> +<Nr>2 </Nr> +<Xti>3 </Xti> +<Alpha>311.7u</Alpha> +<Vk>243.6 </Vk> +<Cgd>1.6p </Cgd> +<M>.3622 </M> +<Pb>1 </Pb> +<Fc>.5 </Fc> +<Cgs>2.414p </Cgs> +<Kf>9.882E-18</Kf> +<Af>1</Af> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib new file mode 100644 index 00000000..848e8b05 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/PMOS-0.5um.xml b/src/deviceModelLibrary/Templates/PMOS-0.5um.xml new file mode 100644 index 00000000..013d461c --- /dev/null +++ b/src/deviceModelLibrary/Templates/PMOS-0.5um.xml @@ -0,0 +1,32 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<TPG>-1 </TPG> +<TOX>9.5n </TOX> +<CJ>950u </CJ> +<ETA>0.025 </ETA> +<VMAX>0.3u </VMAX> +<GAMMA>0.52 </GAMMA> +<CGSO>0.35n </CGSO> +<LD>70n </LD> +<MJSW>0.25 </MJSW> +<PB>1 </PB> +<CGBO>0.45n </CGBO> +<XJ>0.2U </XJ> +<CGDO>0.35n </CGDO> +<KAPPA>8.0 </KAPPA> +<LEVEL>3 </LEVEL> +<VTO>-0.6 </VTO> +<NFS>6.50E11 </NFS> +<THETA>0.2 </THETA> +<CJSW>0.2n </CJSW> +<PHI>0.7 </PHI> +<RSH>2.5 </RSH> +<MJ>0.5</MJ> +<UO>130 </UO> +<KP>48u </KP> +<DELTA>0.25 </DELTA> +<NSUB>1.0E17</NSUB> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/PMOS-180nm.lib b/src/deviceModelLibrary/Templates/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/src/deviceModelLibrary/Templates/PMOS-180nm.xml b/src/deviceModelLibrary/Templates/PMOS-180nm.xml new file mode 100644 index 00000000..6696752d --- /dev/null +++ b/src/deviceModelLibrary/Templates/PMOS-180nm.xml @@ -0,0 +1,112 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>CMOSP</ref_model> +<param> +<LEVEL>8 </LEVEL> +<VERSION>3.2 </VERSION> +<TNOM>27 </TNOM> +<TOX>4.1E-9 </TOX> +<XJ>1E-7 </XJ> +<NCH>4.1589E17 </NCH> +<VTH0>-0.3938813 </VTH0> +<K1>0.5479015</K1> +<K2>0.0360586 </K2> +<K3>0.0993095 </K3> +<K3B>5.7086622</K3B> +<W0>1E-6 </W0> +<NLX>1.313191E-7 </NLX> +<DVT0W>0 </DVT0W> +<DVT1W>0 </DVT1W> +<DVT2W>0 </DVT2W> +<DVT0>0.4911363</DVT0> +<DVT1>0.2227356</DVT1> +<DVT2>0.1 </DVT2> +<U0>115.6852975 </U0> +<UA>1.505832E-9</UA> +<UB>1E-21 </UB> +<UC>-1E-10 </UC> +<VSAT>1.329694E5 </VSAT> +<A0>1.7590478 </A0> +<AGS>0.3641621 </AGS> +<B0>3.427126E-7 </B0> +<B1>1.062928E-6 </B1> +<KETA>0.0134667 </KETA> +<A1>0.6859506 </A1> +<A2>0.3506788 </A2> +<RDSW>168.5705677</RDSW> +<PRWG>0.5 </PRWG> +<PRWB>-0.4987371 </PRWB> +<WR>1 </WR> +<WINT>0 </WINT> +<LINT>3.028832E-8 </LINT> +<XL>0 </XL> +<XW>-1E-8 </XW> +<DWG>-2.349633E-8 </DWG> +<DWB>-7.152486E-9 </DWB> +<VOFF>-0.0994037 </VOFF> +<NFACTOR>1.9424315 </NFACTOR> +<CIT>0 </CIT> +<CDSC>2.4E-4 </CDSC> +<CDSCD>0 </CDSCD> +<CDSCB>0 </CDSCB> +<ETA0>0.0608072 </ETA0> +<ETAB>-0.0426148</ETAB> +<DSUB>0.7343015 </DSUB> +<PCLM>3.2579974 </PCLM> +<PDIBLC1>7.229527E-6 </PDIBLC1> +<PDIBLC2>0.025389 </PDIBLC2> +<PDIBLCB>-1E-3 </PDIBLCB> +<DROUT>0 </DROUT> +<PSCBE1>1.454878E10</PSCBE1> +<PSCBE2>4.202027E-9 </PSCBE2> +<PVAG>15 </PVAG> +<DELTA>0.01 </DELTA> +<RSH>7.8 </RSH> +<MOBMOD>1 </MOBMOD> +<PRT>0 </PRT> +<UTE>-1.5 </UTE> +<KT1>-0.11 </KT1> +<KT1L>0 </KT1L> +<KT2>0.022 </KT2> +<UA1>4.31E-9</UA1> +<UB1>-7.61E-18 </UB1> +<UC1>-5.6E-11 </UC1> +<AT>3.3E4 </AT> +<WL>0 </WL> +<WLN>1 </WLN> +<WW>0 </WW> +<WWN>1 </WWN> +<WWL>0 </WWL> +<LL>0 </LL> +<LLN>1 </LLN> +<LW>0 </LW> +<LWN>1 </LWN> +<LWL>0 </LWL> +<CAPMOD>2 </CAPMOD> +<XPART>0.5</XPART> +<CGDO>6.32E-10 </CGDO> +<CGSO>6.32E-10 </CGSO> +<CGBO>1E-12 </CGBO> +<CJ>1.172138E-3 </CJ> +<PB>0.8421173 </PB> +<MJ>0.4109788 </MJ> +<CJSW>2.242609E-10 </CJSW> +<PBSW>0.8</PBSW> +<MJSW>0.3752089 </MJSW> +<CJSWG>4.22E-10 </CJSWG> +<PBSWG>0.8 </PBSWG> +<MJSWG>0.3752089 </MJSWG> +<CF>0 </CF> +<PVTH0>1.888482E-3 </PVTH0> +<PRDSW>11.5315407 </PRDSW> +<PK2>1.559399E-3 </PK2> +<WKETA>0.0319301 </WKETA> +<LKETA>2.955547E-3 </LKETA> +<PU0>-1.1105313 </PU0> +<PUA>-4.62102E-11</PUA> +<PUB>1E-21 </PUB> +<PVSAT>50 </PVSAT> +<PETA0>1E-4 </PETA0> +<PKETA>-4.346368E-3 </PKETA> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/PMOS-5um.lib b/src/deviceModelLibrary/Templates/PMOS-5um.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/Templates/PMOS-5um.xml b/src/deviceModelLibrary/Templates/PMOS-5um.xml new file mode 100644 index 00000000..f68bada2 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PMOS-5um.xml @@ -0,0 +1,23 @@ +<library> +<model_name>PMOS</model_name> +<ref_model>mos_p</ref_model> +<param> +<Cgso>0.4n </Cgso> +<Tox>85n </Tox> +<Vto>-1 </Vto> +<phi>0.65</phi> +<Level>1</Level> +<Mj>.5 </Mj> +<UO>250 </UO> +<Cgdo>0.4n </Cgdo> +<Gamma>0.65 </Gamma> +<LAMBDA>0.03 </LAMBDA> +<LD>0.6u </LD> +<JS>1u </JS> +<CJ>0.18m </CJ> +<CJSW>0.6n </CJSW> +<MJSW>0.5 </MJSW> +<PB>0.7 </PB> +<CGBO>0.2n</CGBO> +</param> +</library> diff --git a/src/deviceModelLibrary/Templates/PNP.lib b/src/deviceModelLibrary/Templates/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/deviceModelLibrary/Templates/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/deviceModelLibrary/Templates/PNP.xml b/src/deviceModelLibrary/Templates/PNP.xml new file mode 100644 index 00000000..681b3fd9 --- /dev/null +++ b/src/deviceModelLibrary/Templates/PNP.xml @@ -0,0 +1,33 @@ +<library> +<model_name>PNP</model_name> +<ref_model>Q2N2907A</ref_model> +<param> +<Is>650.6E-18</Is> +<Xti>3 </Xti> +<Eg>1.11 </Eg> +<Vaf>115.7 </Vaf> +<Bf>231.7 </Bf> +<Ne>1.829</Ne> +<Ise>54.81f </Ise> +<Ikf>1.079 </Ikf> +<Xtb>1.5 </Xtb> +<Br>3.563 </Br> +<Nc>2 </Nc> +<Isc>0 </Isc> +<Ikr>0</Ikr> +<Rc>.715</Rc> +<Cjc>14.76p </Cjc> +<Mjc>.5383 </Mjc> +<Vjc>.75 </Vjc> +<Fc>.5 </Fc> +<Cje>19.82p </Cje> +<Mje>.3357 </Mje> +<Vje>.75</Vje> +<Tr>111.3n </Tr> +<Tf>603.7p </Tf> +<Itf>.65 </Itf> +<Vtf>5 </Vtf> +<Xtf>1.7 </Xtf> +<Rb>10</Rb> +</param> +</library> diff --git a/src/deviceModelLibrary/Transistor/BC547B.lib b/src/deviceModelLibrary/Transistor/BC547B.lib new file mode 100644 index 00000000..723537a7 --- /dev/null +++ b/src/deviceModelLibrary/Transistor/BC547B.lib @@ -0,0 +1 @@ +.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8) diff --git a/src/deviceModelLibrary/Transistor/BC547B.xml b/src/deviceModelLibrary/Transistor/BC547B.xml new file mode 100644 index 00000000..da06e5c4 --- /dev/null +++ b/src/deviceModelLibrary/Transistor/BC547B.xml @@ -0,0 +1 @@ +<library><model_name>NPN</model_name><ref_model>BC547B</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Isc>0 </Isc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400 </Bf><Fc>.5 </Fc><Ise>14.34f </Ise><Br>6.092 </Br><Ikf>.2847 </Ikf><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Vjc>.75 </Vjc><Vje>.75 </Vje><Xtf>3 </Xtf><Itf>.6 </Itf><Is>14.34f </Is><Eg>1.11 </Eg></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Transistor/NPN.lib b/src/deviceModelLibrary/Transistor/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/deviceModelLibrary/Transistor/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/deviceModelLibrary/Transistor/NPN.xml b/src/deviceModelLibrary/Transistor/NPN.xml new file mode 100644 index 00000000..ee2abcbc --- /dev/null +++ b/src/deviceModelLibrary/Transistor/NPN.xml @@ -0,0 +1 @@ +<library><model_name>NPN</model_name><ref_model>Q2N2222</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400</Bf><Fc>.5 </Fc><Ikf>.2847 </Ikf><Br>6.092 </Br><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Isc>0 </Isc><Ise>14.34f </Ise><Xtf>3 </Xtf><Vje>.75 </Vje><Is>14.34f </Is><Itf>.6 </Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Transistor/PNP.lib b/src/deviceModelLibrary/Transistor/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/deviceModelLibrary/Transistor/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/deviceModelLibrary/Transistor/PNP.xml b/src/deviceModelLibrary/Transistor/PNP.xml new file mode 100644 index 00000000..681b3fd9 --- /dev/null +++ b/src/deviceModelLibrary/Transistor/PNP.xml @@ -0,0 +1,33 @@ +<library> +<model_name>PNP</model_name> +<ref_model>Q2N2907A</ref_model> +<param> +<Is>650.6E-18</Is> +<Xti>3 </Xti> +<Eg>1.11 </Eg> +<Vaf>115.7 </Vaf> +<Bf>231.7 </Bf> +<Ne>1.829</Ne> +<Ise>54.81f </Ise> +<Ikf>1.079 </Ikf> +<Xtb>1.5 </Xtb> +<Br>3.563 </Br> +<Nc>2 </Nc> +<Isc>0 </Isc> +<Ikr>0</Ikr> +<Rc>.715</Rc> +<Cjc>14.76p </Cjc> +<Mjc>.5383 </Mjc> +<Vjc>.75 </Vjc> +<Fc>.5 </Fc> +<Cje>19.82p </Cje> +<Mje>.3357 </Mje> +<Vje>.75</Vje> +<Tr>111.3n </Tr> +<Tf>603.7p </Tf> +<Itf>.65 </Itf> +<Vtf>5 </Vtf> +<Xtf>1.7 </Xtf> +<Rb>10</Rb> +</param> +</library> diff --git a/src/deviceModelLibrary/User Libraries/userDiode.lib b/src/deviceModelLibrary/User Libraries/userDiode.lib new file mode 100644 index 00000000..ef18bb50 --- /dev/null +++ b/src/deviceModelLibrary/User Libraries/userDiode.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/User Libraries/userDiode.xml b/src/deviceModelLibrary/User Libraries/userDiode.xml new file mode 100644 index 00000000..d8584e1d --- /dev/null +++ b/src/deviceModelLibrary/User Libraries/userDiode.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>D1N750</ref_model><param><Is>880.5E-18</Is><Nbvl>14.976</Nbvl><Cjo>175p</Cjo><Rs>.25</Rs><Isr>1.859n</Isr><Eg>1.11</Eg><M>.5516</M><Nbv>1.6989</Nbv><N>1</N><Tbv1>-21.277u</Tbv1><Bv>8.1</Bv><Fc>.5</Fc><Ikf>0</Ikf><Xti>3</Xti><Nr>2</Nr><Vj>.75</Vj><Ibv>20.245m</Ibv><Ibvl>1.9556m</Ibvl></param></library>
\ No newline at end of file diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py new file mode 100755 index 00000000..a6c5feb5 --- /dev/null +++ b/src/frontEnd/Application.py @@ -0,0 +1,502 @@ + +#=============================================================================== +# +# FILE: Application.py +# +# USAGE: --- +# +# DESCRIPTION: This main file use to start the Application +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, Rahul Paknikar +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Friday 23 August 2019 +# REVISION: --- +#=============================================================================== +import os +import sys +#Setting PYTHONPATH +cwd = os.getcwd() +(setPath,fronEnd) = os.path.split(cwd) +sys.path.append(setPath) + +from PyQt4 import QtGui, QtCore +from configuration.Appconfig import Appconfig +from projManagement.openProject import OpenProjectInfo +from projManagement.newProject import NewProjectInfo +from projManagement.Kicad import Kicad +from projManagement.Validation import Validation +from projManagement import Worker +from frontEnd import ProjectExplorer +from frontEnd import Workspace +from frontEnd import DockArea +import time +from PyQt4.Qt import QSize + + +class Application(QtGui.QMainWindow): + global project_name + """ + Its our main window of application + """ + def __init__(self,*args): + """ + Initialize main Application window + """ + #Calling __init__ of super class + QtGui.QMainWindow.__init__(self,*args) + + + #Flag for online-offline mode. Default is set offline mode. + #Mode gets updated dynamically from the previous eSim session. + self.online_flag = False + + + #Creating require Object + self.obj_workspace = Workspace.Workspace() + self.obj_Mainview = MainView() + self.obj_kicad = Kicad(self.obj_Mainview.obj_dockarea) + self.obj_appconfig = Appconfig() + self.obj_validation = Validation() + #Initialize all widget + self.setCentralWidget(self.obj_Mainview) + self.initToolBar() + + self.setGeometry(self.obj_appconfig._app_xpos, + self.obj_appconfig._app_ypos, + self.obj_appconfig._app_width, + self.obj_appconfig._app_heigth) + self.setWindowTitle(self.obj_appconfig._APPLICATION) + self.showMaximized() + self.setWindowIcon(QtGui.QIcon('../../images/logo.png')) + #self.show() + self.systemTrayIcon = QtGui.QSystemTrayIcon(self) + self.systemTrayIcon.setIcon(QtGui.QIcon('../../images/logo.png')) + self.systemTrayIcon.setVisible(True) + + + def initToolBar(self): + """ + This function initialize Tool Bar + """ + #Top Tool bar + self.newproj = QtGui.QAction(QtGui.QIcon('../../images/newProject.png'),'<b>New Project</b>',self) + self.newproj.setShortcut('Ctrl+N') + self.newproj.triggered.connect(self.new_project) + #self.newproj.connect(self.newproj,QtCore.SIGNAL('triggered()'),self,QtCore.SLOT(self.new_project())) + + self.openproj = QtGui.QAction(QtGui.QIcon('../../images/openProject.png'),'<b>Open Project</b>',self) + self.openproj.setShortcut('Ctrl+O') + self.openproj.triggered.connect(self.open_project) + + self.closeproj = QtGui.QAction(QtGui.QIcon('../../images/closeProject.png'),'<b>Close Project</b>',self) + self.closeproj.setShortcut('Ctrl+X') + self.closeproj.triggered.connect(self.close_project) + + + + for file in os.listdir("../../../../.config/kicad"): + if file.startswith("fp-lib-table"): + if file.endswith("offline"): + self.webConnect = QtGui.QAction(QtGui.QIcon('../../images/online.png'),'<b>Go Offline</b>',self) + self.online_flag = True + break + elif file.endswith("online"): + self.webConnect = QtGui.QAction(QtGui.QIcon('../../images/offline.png'),'<b>Go Online</b>',self) + self.online_flag = False + break + + self.webConnect.setShortcut('Ctrl+G') + self.webConnect.triggered.connect(self.go_online_offline) + + # try: + # self.webConnect.setShortcut('Ctrl+G') + # self.webConnect.triggered.connect(self.go_online_offline) + # except AttributeError as e: + # self.webConnect = QtGui.QAction(QtGui.QIcon('../../images/offline.png'),'<b>Go Online</b>',self) + # self.webConnect.setShortcut('Ctrl+G') + # self.webConnect.triggered.connect(self.go_online_offline) + # self.online_flag = False + + + + self.helpfile = QtGui.QAction(QtGui.QIcon('../../images/helpProject.png'),'<b>Help</b>',self) + self.helpfile.setShortcut('Ctrl+H') + self.helpfile.triggered.connect(self.help_project) + + self.topToolbar = self.addToolBar('Top Tool Bar') + self.topToolbar.addAction(self.newproj) + self.topToolbar.addAction(self.openproj) + + self.topToolbar.addAction(self.closeproj) + self.topToolbar.addAction(self.webConnect) + self.topToolbar.addAction(self.helpfile) + + self.spacer = QtGui.QWidget() + self.spacer.setSizePolicy(QtGui.QSizePolicy.Expanding,QtGui.QSizePolicy.Expanding) + self.topToolbar.addWidget(self.spacer) + self.logo = QtGui.QLabel() + self.logopic = QtGui.QPixmap(os.path.join(os.path.abspath('../..'),'images','fosseeLogo.png')) + self.logopic = self.logopic.scaled(QSize(150,150),QtCore.Qt.KeepAspectRatio) + self.logo.setPixmap(self.logopic) + self.logo.setStyleSheet("padding:0 15px 0 0;") + self.topToolbar.addWidget(self.logo) + + #Left Tool bar Action Widget + self.kicad = QtGui.QAction(QtGui.QIcon('../../images/kicad.png'),'<b>Open Schematic</b>',self) + self.kicad.triggered.connect(self.obj_kicad.openSchematic) + + self.conversion = QtGui.QAction(QtGui.QIcon('../../images/ki-ng.png'),'<b>Convert Kicad to Ngspice</b>',self) + self.conversion.triggered.connect(self.obj_kicad.openKicadToNgspice) + + self.ngspice = QtGui.QAction(QtGui.QIcon('../../images/ngspice.png'), '<b>Simulation</b>', self) + self.ngspice.triggered.connect(self.open_ngspice) + + self.model = QtGui.QAction(QtGui.QIcon('../../images/model.png'),'<b>Model Editor</b>',self) + self.model.triggered.connect(self.open_modelEditor) + + self.subcircuit=QtGui.QAction(QtGui.QIcon('../../images/subckt.png'),'<b>Subcircuit</b>',self) + self.subcircuit.triggered.connect(self.open_subcircuit) + + self.nghdl = QtGui.QAction(QtGui.QIcon('../../images/nghdl.png'), '<b>Nghdl</b>', self) + self.nghdl.triggered.connect(self.open_nghdl) + + self.omedit = QtGui.QAction(QtGui.QIcon('../../images/omedit.png'),'<b>Modelica Converter</b>',self) + self.omedit.triggered.connect(self.open_OMedit) + + self.omoptim=QtGui.QAction(QtGui.QIcon('../../images/omoptim.png'),'<b>OM Optimisation</b>',self) + self.omoptim.triggered.connect(self.open_OMoptim) + + #Adding Action Widget to tool bar + self.lefttoolbar = QtGui.QToolBar('Left ToolBar') + self.addToolBar(QtCore.Qt.LeftToolBarArea, self.lefttoolbar) + self.lefttoolbar.addAction(self.kicad) + self.lefttoolbar.addAction(self.conversion) + self.lefttoolbar.addAction(self.ngspice) + self.lefttoolbar.addAction(self.model) + self.lefttoolbar.addAction(self.subcircuit) + self.lefttoolbar.addAction(self.nghdl) + self.lefttoolbar.addAction(self.omedit) + self.lefttoolbar.addAction(self.omoptim) + self.lefttoolbar.setOrientation(QtCore.Qt.Vertical) + self.lefttoolbar.setIconSize(QSize(40,40)) + + def closeEvent(self, event): + exit_msg = "Are you sure you want to exit the program ? All unsaved data will be lost." + reply = QtGui.QMessageBox.question(self, 'Message', + exit_msg, QtGui.QMessageBox.Yes, QtGui.QMessageBox.No) + + if reply == QtGui.QMessageBox.Yes: + for proc in self.obj_appconfig.procThread_list: + try: + proc.terminate() + except: + pass + try: + for process_object in self.obj_appconfig.process_obj: + try: + process_object.close() + except: + pass + except: + pass + ##Just checking if open project and New project window is open. If yes just close it when application is closed + try: + self.project.close() + except: + pass + event.accept() + self.systemTrayIcon.showMessage('Exit', 'eSim is Closed.') + + elif reply == QtGui.QMessageBox.No: + event.ignore() + + + def close_project(self): + print "Function : Close Project" + current_project = self.obj_appconfig.current_project['ProjectName'] + if current_project==None: + pass + else: + for pid in self.obj_appconfig.proc_dict[self.obj_appconfig.current_project['ProjectName']]: + try: + os.kill(pid, 9) + except: + pass + self.obj_Mainview.obj_dockarea.closeDock() + self.obj_appconfig.current_project['ProjectName'] = None + self.systemTrayIcon.showMessage('Close', 'Current project '+os.path.basename(current_project)+' is Closed.') + + def new_project(self): + """ + This function call New Project Info class. + """ + text, ok = QtGui.QInputDialog.getText(self, 'New Project Info','Enter Project Name:') + if ok: + self.projname = (str(text)) + self.project = NewProjectInfo() + directory, filelist =self.project.createProject(self.projname) + + self.obj_Mainview.obj_projectExplorer.addTreeNode(directory, filelist) + + else: + print "No new project created" + self.obj_appconfig.print_info('No new project created') + try: + self.obj_appconfig.print_info('Current project is : ' + self.obj_appconfig.current_project["ProjectName"]) + except: + pass + + def open_project(self): + """ + This project call Open Project Info class + """ + print "Function : Open Project" + self.project = OpenProjectInfo() + + try: + directory, filelist = self.project.body() + self.obj_Mainview.obj_projectExplorer.addTreeNode(directory, filelist) + except: + pass + + def help_project(self): + print "Function : Help" + self.obj_appconfig.print_info('Help is called') + print "Current Project is : ",self.obj_appconfig.current_project + self.obj_Mainview.obj_dockarea.usermanual() + + + + def go_online_offline(self): + if self.online_flag: + os.rename("../../../../.config/kicad/fp-lib-table", "../../../../.config/kicad/fp-lib-table-online") + os.rename("../../../../.config/kicad/fp-lib-table-offline", "../../../../.config/kicad/fp-lib-table") + self.webConnect.setIcon(QtGui.QIcon('../../images/offline.png')) + self.webConnect.setText('<b>Go Online</b>') + self.online_flag = False + else: + os.rename("../../../../.config/kicad/fp-lib-table", "../../../../.config/kicad/fp-lib-table-offline") + os.rename("../../../../.config/kicad/fp-lib-table-online", "../../../../.config/kicad/fp-lib-table") + self.webConnect.setIcon(QtGui.QIcon('../../images/online.png')) + self.webConnect.setText('<b>Go Offline</b>') + self.online_flag = True + + + + def open_ngspice(self): + """ + This Function execute ngspice on current project + """ + + self.projDir = self.obj_appconfig.current_project["ProjectName"] + + if self.projDir != None: + self.obj_Mainview.obj_dockarea.ngspiceEditor(self.projDir) + time.sleep(2) #Need permanent solution + #Calling Python Plotting + + try: + self.obj_Mainview.obj_dockarea.plottingEditor() + except Exception as e: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Error while opening python plotting Editor. Please look at console for more details ') + print "Exception Message:",str(e) + self.obj_appconfig.print_error('Exception Message : ' + str(e)) + self.msg.setWindowTitle("Error Message") + + else: + self.msg = QtGui.QErrorMessage() + self.msg.showMessage('Please select the project first. You can either create new project or open existing project') + self.msg.setWindowTitle("Error Message") + + def open_subcircuit(self): + print "Function : Subcircuit editor" + self.obj_appconfig.print_info('Subcircuit editor is called') + self.obj_Mainview.obj_dockarea.subcircuiteditor() + + def open_nghdl(self): + print "Function : Nghdl" + self.obj_appconfig.print_info('Nghdl is called') + + if self.obj_validation.validateTool('nghdl'): + self.cmd = 'nghdl -e' + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Error while opening nghdl. Please make sure nghdl is installed') + self.obj_appconfig.print_error('Error while opening nghdl. Please make sure nghdl is installed') + self.msg.setWindowTitle('nghdl Error Message') + + + def open_modelEditor(self): + print "Function : Model editor" + self.obj_appconfig.print_info('Model editor is called') + self.obj_Mainview.obj_dockarea.modelEditor() + + + def open_OMedit(self): + """ + This function call ngspice to OM edit converter and then launch OM edit. + """ + self.obj_appconfig.print_info('OM edit is called') + self.projDir = self.obj_appconfig.current_project["ProjectName"] + + if self.projDir != None: + if self.obj_validation.validateCirOut(self.projDir): + self.projName = os.path.basename(self.projDir) + self.ngspiceNetlist = os.path.join(self.projDir,self.projName+".cir.out") + self.modelicaNetlist = os.path.join(self.projDir,self.projName+".mo") + + """ + try: + #Creating a command for Ngspice to Modelica converter + self.cmd1 = "python ../ngspicetoModelica/NgspicetoModelica.py "+self.ngspiceNetlist + self.obj_workThread1 = Worker.WorkerThread(self.cmd1) + self.obj_workThread1.start() + + + if self.obj_validation.validateTool("OMEdit"): + #Creating command to run OMEdit + self.cmd2 = "OMEdit "+self.modelicaNetlist + self.obj_workThread2 = Worker.WorkerThread(self.cmd2) + self.obj_workThread2.start() + else: + self.msg = QtGui.QMessageBox() + self.msgContent = "There was an error while opening OMEdit.<br/>\ + Please make sure OpenModelica is installed in your system. <br/>\ + To install it on Linux : Go to <a href=https://www.openmodelica.org/download/download-linux>OpenModelica Linux</a> and install nigthly build release.<br/>\ + To install it on Windows : Go to <a href=https://www.openmodelica.org/download/download-windows>OpenModelica Windows</a> and install latest version.<br/>" + self.msg.setTextFormat(QtCore.Qt.RichText) + self.msg.setText(self.msgContent) + self.msg.setWindowTitle("Missing OpenModelica") + self.obj_appconfig.print_info(self.msgContent) + self.msg.exec_() + + except Exception as e: + self.msg = QtGui.QErrorMessage() + self.msg.showMessage('Unable to convert NgSpice netlist to Modelica netlist :'+str(e)) + self.msg.setWindowTitle("Ngspice to Modelica conversion error") + self.obj_appconfig.print_error(str(e)) + """ + + self.obj_Mainview.obj_dockarea.modelicaEditor(self.projDir) + + else: + self.msg = QtGui.QErrorMessage() + self.msg.showMessage('Current project does not contain any ngspice file. Please create ngspice file with extension .cir.out') + self.msg.setWindowTitle("Missing Ngspice netlist") + else: + self.msg = QtGui.QErrorMessage() + self.msg.showMessage('Please select the project first. You can either create new project or open existing project') + self.msg.setWindowTitle("Error Message") + + + def open_OMoptim(self): + print "Function : OM Optim" + self.obj_appconfig.print_info('OM Optim is called') + #Check if OMOptim is installed + if self.obj_validation.validateTool("OMOptim"): + #Creating a command to run + self.cmd = "OMOptim" + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + else: + self.msg = QtGui.QMessageBox() + self.msgContent = "There was an error while opening OMOptim.<br/>\ + Please make sure OpenModelica is installed in your system. <br/>\ + To install it on Linux : Go to <a href=https://www.openmodelica.org/download/download-linux>OpenModelica Linux</a> and install nigthly build release.<br/>\ + To install it on Windows : Go to <a href=https://www.openmodelica.org/download/download-windows>OpenModelica Windows</a> and install latest version.<br/>" + self.msg.setTextFormat(QtCore.Qt.RichText) + self.msg.setText(self.msgContent) + self.msg.setWindowTitle("Error Message") + self.obj_appconfig.print_info(self.msgContent) + self.msg.exec_() + +class MainView(QtGui.QWidget): + """ + This class initialize the Main View of Application + """ + def __init__(self, *args): + # call init method of superclass + QtGui.QWidget.__init__(self, *args) + + self.obj_appconfig = Appconfig() + + self.leftSplit = QtGui.QSplitter() + self.middleSplit = QtGui.QSplitter() + + self.mainLayout = QtGui.QVBoxLayout() + #Intermediate Widget + self.middleContainer = QtGui.QWidget() + self.middleContainerLayout = QtGui.QVBoxLayout() + + #Area to be included in MainView + self.noteArea = QtGui.QTextEdit() + self.noteArea.setReadOnly(True) + self.obj_appconfig.noteArea['Note'] = self.noteArea + self.obj_appconfig.noteArea['Note'].append(' eSim Started......') + self.obj_appconfig.noteArea['Note'].append('Project Selected : None') + self.obj_appconfig.noteArea['Note'].append('\n') + + #CSS + self.noteArea.setStyleSheet(" \ + QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; } \ + ") + + self.obj_dockarea = DockArea.DockArea() + self.obj_projectExplorer = ProjectExplorer.ProjectExplorer() + + #Adding content to vertical middle Split. + self.middleSplit.setOrientation(QtCore.Qt.Vertical) + self.middleSplit.addWidget(self.obj_dockarea) + self.middleSplit.addWidget(self.noteArea) + + #Adding middle split to Middle Container Widget + self.middleContainerLayout.addWidget(self.middleSplit) + self.middleContainer.setLayout(self.middleContainerLayout) + + #Adding content of left split + self.leftSplit.addWidget(self.obj_projectExplorer) + self.leftSplit.addWidget(self.middleContainer) + + + #Adding to main Layout + self.mainLayout.addWidget(self.leftSplit) + self.leftSplit.setSizes([self.width()/4.5,self.height()]) + self.middleSplit.setSizes([self.width(),self.height()/2]) + self.setLayout(self.mainLayout) + + +def main(args): + """ + It is main function of the module.It starts the application + """ + print "Starting eSim......" + app = QtGui.QApplication(args) + + splash_pix = QtGui.QPixmap('../../images/splash_screen_esim.png') + splash = QtGui.QSplashScreen(splash_pix,QtCore.Qt.WindowStaysOnTopHint) + splash.setMask(splash_pix.mask()) + splash.show() + appView = Application() + appView.splash=splash + appView.obj_workspace.returnWhetherClickedOrNot(appView) + appView.hide() + appView.obj_workspace.show() + sys.exit(app.exec_()) + + + +# Call main function +if __name__ == '__main__': + # Create and display the splash screen + main(sys.argv) + + + diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py new file mode 100644 index 00000000..073072bf --- /dev/null +++ b/src/frontEnd/DockArea.py @@ -0,0 +1,308 @@ +from PyQt4 import QtGui,QtCore +from ngspiceSimulation.pythonPlotting import plotWindow +from ngspiceSimulation.NgspiceWidget import NgspiceWidget +from configuration.Appconfig import Appconfig +from modelEditor.ModelEditor import ModelEditorclass +from subcircuit.Subcircuit import Subcircuit +from kicadtoNgspice.KicadtoNgspice import MainWindow +from browser.Welcome import Welcome +from browser.UserManual import UserManual +from ngspicetoModelica.ModelicaUI import OpenModelicaEditor +import os + +dockList = ['Welcome'] +count = 1 +dock = {} + +class DockArea(QtGui.QMainWindow): + + def __init__(self): + QtGui.QMainWindow.__init__(self) + self.obj_appconfig = Appconfig() + + for dockName in dockList: + dock[dockName] = QtGui.QDockWidget(dockName) + self.welcomeWidget = QtGui.QWidget() + self.welcomeLayout = QtGui.QVBoxLayout() + self.welcomeLayout.addWidget(Welcome()) ##Call browser + + #Adding to main Layout + self.welcomeWidget.setLayout(self.welcomeLayout) + dock[dockName].setWidget(self.welcomeWidget) + #CSS + dock[dockName].setStyleSheet(" \ + QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock[dockName]) + + #self.tabifyDockWidget(dock['Notes'],dock['Blank']) + self.show() + + ''' + def __init__(self): + QtGui.QMainWindow.__init__(self) + self.obj_appconfig = Appconfig() + + for dockName in dockList: + dock[dockName] = QtGui.QDockWidget(dockName) + self.welcome = QtGui.QTextEdit() + self.welcome.setReadOnly(True) + dock[dockName].setWidget(self.welcome) + #CSS + dock[dockName].setStyleSheet(" \ + QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock[dockName]) + + #self.tabifyDockWidget(dock['Notes'],dock['Blank']) + self.show() + ''' + + def createTestEditor(self): + """ + This function create widget for Library Editor + """ + global count + + self.testWidget = QtGui.QWidget() + self.testArea = QtGui.QTextEdit() + self.testLayout = QtGui.QVBoxLayout() + self.testLayout.addWidget(self.testArea) + + #Adding to main Layout + self.testWidget.setLayout(self.testLayout) + dock['Tips-'+str(count)] = QtGui.QDockWidget('Tips-'+str(count)) + dock['Tips-'+str(count)].setWidget(self.testWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['Tips-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['Tips-'+str(count)]) + + """ + #CSS + dock['Tips-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + """ + + dock['Tips-'+str(count)].setVisible(True) + dock['Tips-'+str(count)].setFocus() + """ + dock['Tips-'+str(count)].setStyleSheet(" \ + :hover { background-color: yellow; } \ + ") + """ + dock['Tips-'+str(count)].raise_() + + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['Tips-'+str(count)]) + count = count + 1 + + def plottingEditor(self): + """ + This function create widget for interactive PythonPlotting + """ + self.projDir = self.obj_appconfig.current_project["ProjectName"] + self.projName = os.path.basename(self.projDir) + #self.project = os.path.join(self.projDir,self.projName) + + + global count + self.plottingWidget = QtGui.QWidget() + + self.plottingLayout = QtGui.QVBoxLayout() + self.plottingLayout.addWidget(plotWindow(self.projDir,self.projName)) + + #Adding to main Layout + self.plottingWidget.setLayout(self.plottingLayout) + dock['Plotting-'+str(count)] = QtGui.QDockWidget('Plotting-'+str(count)) + dock['Plotting-'+str(count)].setWidget(self.plottingWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['Plotting-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['Plotting-'+str(count)]) + + """ + #CSS + dock['Plotting-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + """ + dock['Plotting-'+str(count)].setVisible(True) + dock['Plotting-'+str(count)].setFocus() + dock['Plotting-'+str(count)].raise_() + + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['Plotting-'+str(count)]) + count = count + 1 + + def ngspiceEditor(self,projDir): + """ + This function creates widget for NgSpice window + """ + + + self.projDir = projDir + self.projName = os.path.basename(self.projDir) + self.ngspiceNetlist = os.path.join(self.projDir,self.projName+".cir.out") + + + + global count + self.ngspiceWidget = QtGui.QWidget() + + self.ngspiceLayout = QtGui.QVBoxLayout() + self.ngspiceLayout.addWidget(NgspiceWidget(self.ngspiceNetlist,self.projDir)) + + #Adding to main Layout + self.ngspiceWidget.setLayout(self.ngspiceLayout) + dock['NgSpice-'+str(count)] = QtGui.QDockWidget('NgSpice-'+str(count)) + dock['NgSpice-'+str(count)].setWidget(self.ngspiceWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['NgSpice-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['NgSpice-'+str(count)]) + + #CSS + dock['NgSpice-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 0px; width: 200px; height: 150px; } \ + ") + + dock['NgSpice-'+str(count)].setVisible(True) + dock['NgSpice-'+str(count)].setFocus() + dock['NgSpice-'+str(count)].raise_() + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['NgSpice-'+str(count)]) + count = count + 1 + + def modelEditor(self): + print"in model editor" + global count + self.modelwidget = QtGui.QWidget() + + self.modellayout = QtGui.QVBoxLayout() + self.modellayout.addWidget(ModelEditorclass()) + + #Adding to main Layout + self.modelwidget.setLayout(self.modellayout) + + dock['Model Editor-'+str(count)] = QtGui.QDockWidget('Model Editor-'+str(count)) + dock['Model Editor-'+str(count)].setWidget(self.modelwidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['Model Editor-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['Model Editor-'+str(count)]) + + #CSS + dock['Model Editor-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + + dock['Model Editor-'+str(count)].setVisible(True) + dock['Model Editor-'+str(count)].setFocus() + dock['Model Editor-'+str(count)].raise_() + + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['Model Editor-'+str(count)]) + count = count + 1 + + def kicadToNgspiceEditor(self,clarg1,clarg2=None): + global count + self.kicadToNgspiceWidget=QtGui.QWidget() + self.kicadToNgspiceLayout=QtGui.QVBoxLayout() + self.kicadToNgspiceLayout.addWidget(MainWindow(clarg1,clarg2)) + + self.kicadToNgspiceWidget.setLayout(self.kicadToNgspiceLayout) + dock['kicadToNgspice-'+str(count)] = QtGui.QDockWidget('kicadToNgspice-'+str(count)) + dock['kicadToNgspice-'+str(count)].setWidget(self.kicadToNgspiceWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['kicadToNgspice-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['kicadToNgspice-'+str(count)]) + + #CSS + dock['kicadToNgspice-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + + dock['kicadToNgspice-'+str(count)].setVisible(True) + dock['kicadToNgspice-'+str(count)].setFocus() + dock['kicadToNgspice-'+str(count)].raise_() + + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['kicadToNgspice-'+str(count)]) + count = count + 1 + + + def subcircuiteditor(self): + """ + This function creates a widget for different subcircuit options + """ + + global count + self.subcktWidget=QtGui.QWidget() + self.subcktLayout=QtGui.QVBoxLayout() + self.subcktLayout.addWidget(Subcircuit(self)) + + self.subcktWidget.setLayout(self.subcktLayout) + dock['Subcircuit-'+str(count)] = QtGui.QDockWidget('Subcircuit-'+str(count)) + dock['Subcircuit-'+str(count)].setWidget(self.subcktWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['Subcircuit-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['Subcircuit-'+str(count)]) + + #CSS + dock['Subcircuit-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + + dock['Subcircuit-'+str(count)].setVisible(True) + dock['Subcircuit-'+str(count)].setFocus() + dock['Subcircuit-'+str(count)].raise_() + + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['Subcircuit-'+str(count)]) + count = count + 1 + + def usermanual(self): + """ + This function creates a widget for different subcircuit options + """ + + global count + self.usermanualWidget=QtGui.QWidget() + self.usermanualLayout=QtGui.QVBoxLayout() + self.usermanualLayout.addWidget(UserManual()) + + self.usermanualWidget.setLayout(self.usermanualLayout) + dock['User Manual-'+str(count)] = QtGui.QDockWidget('User Manual-'+str(count)) + dock['User Manual-'+str(count)].setWidget(self.usermanualWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['User Manual-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['User Manual-'+str(count)]) + + #CSS + dock['User Manual-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + + dock['User Manual-'+str(count)].setVisible(True) + dock['User Manual-'+str(count)].setFocus() + dock['User Manual-'+str(count)].raise_() + + count = count + 1 + + def modelicaEditor(self, projDir): + """ + This function sets up the UI for ngspice to modelica conversion + """ + + global count + self.modelicaWidget = QtGui.QWidget() + self.modelicaLayout = QtGui.QVBoxLayout() + self.modelicaLayout.addWidget(OpenModelicaEditor(projDir)) + + self.modelicaWidget.setLayout(self.modelicaLayout) + dock['Modelica-'+str(count)] = QtGui.QDockWidget('Modelica-'+str(count)) + dock['Modelica-'+str(count)].setWidget(self.modelicaWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['Modelica-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['Modelica-'+str(count)]) + + dock['Modelica-'+str(count)].setVisible(True) + dock['Modelica-'+str(count)].setFocus() + dock['Modelica-'+str(count)].raise_() + + #CSS + dock['Modelica-'+str(count)].setStyleSheet(" \ + .QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(dock['Modelica-'+str(count)]) + + count = count + 1 + + def closeDock (self): + for dockwidget in self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']]: + dockwidget.close() diff --git a/src/frontEnd/DockArea.pyc b/src/frontEnd/DockArea.pyc Binary files differnew file mode 100644 index 00000000..d699a73a --- /dev/null +++ b/src/frontEnd/DockArea.pyc diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py new file mode 100644 index 00000000..146b6d0f --- /dev/null +++ b/src/frontEnd/ProjectExplorer.py @@ -0,0 +1,147 @@ +from PyQt4 import QtGui,QtCore +import os +import json +from configuration.Appconfig import Appconfig + + +class ProjectExplorer(QtGui.QWidget): + def __init__(self): + QtGui.QWidget.__init__(self) + self.obj_appconfig = Appconfig() + self.treewidget = QtGui.QTreeWidget() + self.window= QtGui.QVBoxLayout() + header = QtGui.QTreeWidgetItem(["Projects","path"]) + self.treewidget.setHeaderItem(header) + self.treewidget.setColumnHidden(1,True) + + #CSS + self.treewidget.setStyleSheet(" \ + QTreeView { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + QTreeView::branch:has-siblings:!adjoins-item { border-image: url(../../images/vline.png) 0; } \ + QTreeView::branch:has-siblings:adjoins-item { border-image: url(../../images/branch-more.png) 0; } \ + QTreeView::branch:!has-children:!has-siblings:adjoins-item { border-image: url(../../images/branch-end.png) 0; } \ + QTreeView::branch:has-children:!has-siblings:closed, \ + QTreeView::branch:closed:has-children:has-siblings { border-image: none; image: url(../../images/branch-closed.png); } \ + QTreeView::branch:open:has-children:!has-siblings, \ + QTreeView::branch:open:has-children:has-siblings { border-image: none; image: url(../../images/branch-open.png); } \ + ") + + for parents, children in self.obj_appconfig.project_explorer.items(): + os.path.join(parents) + if os.path.exists(parents): + pathlist= parents.split(os.sep) + parentnode = QtGui.QTreeWidgetItem(self.treewidget, [pathlist[-1],parents]) + for files in children: + childnode = QtGui.QTreeWidgetItem(parentnode, [files, os.path.join(parents,files)]) + self.window.addWidget(self.treewidget) + + self.treewidget.doubleClicked.connect(self.openProject) + self.treewidget.setContextMenuPolicy(QtCore.Qt.CustomContextMenu) + self.treewidget.customContextMenuRequested.connect(self.openMenu) + self.setLayout(self.window) + self.show() + + def addTreeNode(self, parents, children): + os.path.join(parents) + pathlist= parents.split(os.sep) + parentnode = QtGui.QTreeWidgetItem(self.treewidget, [pathlist[-1], parents]) + for files in children: + childnode = QtGui.QTreeWidgetItem(parentnode, [files, os.path.join(parents,files)]) + self.obj_appconfig.proc_dict[self.obj_appconfig.current_project['ProjectName']] = [] + self.oj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']] = [] + + def openMenu(self, position): + + indexes = self.treewidget.selectedIndexes() + if len(indexes) > 0: + + level = 0 + index = indexes[0] + while index.parent().isValid(): + index = index.parent() + level += 1 + + menu = QtGui.QMenu() + if level == 0: + deleteproject = menu.addAction(self.tr("Remove Project")) + deleteproject.triggered.connect(self.removeProject) + refreshproject= menu.addAction(self.tr("Refresh")) + refreshproject.triggered.connect(self.refreshProject) + elif level == 1: + openfile = menu.addAction(self.tr("Open")) + openfile.triggered.connect(self.openProject) + + menu.exec_(self.treewidget.viewport().mapToGlobal(position)) + + def openProject(self): + self.indexItem =self.treewidget.currentIndex() + filename= self.indexItem.data().toString() + self.filePath= self.indexItem.sibling(self.indexItem.row(), 1).data().toString() + self.obj_appconfig.print_info('The current project is ' + self.filePath) + + self.textwindow = QtGui.QWidget() + self.textwindow.setMinimumSize(600, 500) + self.textwindow.setGeometry(QtCore.QRect(400,150,400,400)) + self.textwindow.setWindowTitle(filename) + + self.text = QtGui.QTextEdit() + self.save = QtGui.QPushButton('Save and Exit') + self.save.setDisabled(True) + self.windowgrid = QtGui.QGridLayout() + if (os.path.isfile(str(self.filePath)))== True: + self.fopen = open(str(self.filePath), 'r') + lines = self.fopen.read() + self.text.setText(lines) + + QtCore.QObject.connect(self.text,QtCore.SIGNAL("textChanged()"), self.enable_save) + + vbox_main = QtGui.QVBoxLayout(self.textwindow) + vbox_main.addWidget(self.text) + vbox_main.addWidget(self.save) + self.save.clicked.connect(self.save_data) + #self.connect(exit,QtCore.SIGNAL('close()'), self.onQuit) + + self.textwindow.show() + else: + self.obj_appconfig.current_project["ProjectName"]= str(self.filePath) + self.obj_appconfig.proc_dict[self.obj_appconfig.current_project['ProjectName']] = [] + if self.obj_appconfig.current_project['ProjectName'] not in self.obj_appconfig.dock_dict: + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']] = [] + + def enable_save(self): + self.save.setEnabled(True) + + def save_data(self): + self.fopen=open(self.filePath, 'w') + self.fopen.write(self.text.toPlainText()) + self.fopen.close() + self.textwindow.close() + + def removeProject(self): + self.indexItem =self.treewidget.currentIndex() + filename= self.indexItem.data().toString() + self.filePath= self.indexItem.sibling(self.indexItem.row(), 1).data().toString() + self.int = self.indexItem.row() + self.treewidget.takeTopLevelItem(self.int) + + if self.obj_appconfig.current_project["ProjectName"] == self.filePath: + self.obj_appconfig.current_project["ProjectName"] = None + + del self.obj_appconfig.project_explorer[str(self.filePath)] + json.dump(self.obj_appconfig.project_explorer, open(self.obj_appconfig.dictPath,'w')) + + def refreshProject(self): + self.indexItem =self.treewidget.currentIndex() + filename= self.indexItem.data().toString() + self.filePath= str(self.indexItem.sibling(self.indexItem.row(), 1).data().toString()) + filelistnew= os.listdir(os.path.join(self.filePath)) + parentnode = self.treewidget.currentItem() + count = parentnode.childCount() + for i in range(count): + for items in self.treewidget.selectedItems(): + items.removeChild(items.child(0)) + for files in filelistnew: + childnode= QtGui.QTreeWidgetItem(parentnode, [files, os.path.join(self.filePath,files)]) + + self.obj_appconfig.project_explorer[self.filePath]= filelistnew + json.dump(self.obj_appconfig.project_explorer, open(self.obj_appconfig.dictPath,'w')) diff --git a/src/frontEnd/ProjectExplorer.pyc b/src/frontEnd/ProjectExplorer.pyc Binary files differnew file mode 100644 index 00000000..1fb43ac0 --- /dev/null +++ b/src/frontEnd/ProjectExplorer.pyc diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py new file mode 100644 index 00000000..7cefa6c6 --- /dev/null +++ b/src/frontEnd/Workspace.py @@ -0,0 +1,121 @@ +#=============================================================================== +# +# FILE: Workspace.py +# +# USAGE: --- +# +# DESCRIPTION: This define all configuration used in Application. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Wednesday 05 February 2015 +# REVISION: --- +#=============================================================================== +from PyQt4 import QtCore, QtGui +from configuration.Appconfig import Appconfig +import time +import os + + +class Workspace(QtGui.QWidget): + """ + This class creates Workspace GUI. + """ + def __init__(self,parent=None): + super(Workspace, self).__init__() + self.obj_appconfig = Appconfig() + + #Initializing Workspace directory for project + self.initWorkspace() + + + def initWorkspace(self): + #print "Calling workspace" + + self.mainwindow = QtGui.QVBoxLayout() + self.split = QtGui.QSplitter() + self.split.setOrientation(QtCore.Qt.Vertical) + + self.grid = QtGui.QGridLayout() + self.note = QtGui.QTextEdit(self) + self.workspace_label = QtGui.QLabel(self) + self.workspace_loc = QtGui.QLineEdit(self) + + self.note.append(self.obj_appconfig.workspace_text) + self.workspace_label.setText("Workspace:") + self.workspace_loc.setText(self.obj_appconfig.home) + + #Buttons + self.browsebtn = QtGui.QPushButton('Browse') + self.browsebtn.clicked.connect(self.browseLocation) + self.okbtn = QtGui.QPushButton('OK') + self.okbtn.clicked.connect(self.createWorkspace) + self.cancelbtn = QtGui.QPushButton('Cancel') + self.cancelbtn.clicked.connect(self.defaultWorkspace) + #Layout + self.grid.addWidget(self.note, 0,0,1,15) + self.grid.addWidget(self.workspace_label, 2,1) + self.grid.addWidget(self.workspace_loc,2,2,2,12) + self.grid.addWidget(self.browsebtn, 2,14) + self.grid.addWidget(self.okbtn, 4,13) + self.grid.addWidget(self.cancelbtn, 4,14) + + self.setGeometry(QtCore.QRect(500,250,400,400)) + self.setMaximumSize(4000, 200) + self.setWindowTitle("eSim") + self.setWindowFlags(QtCore.Qt.WindowStaysOnTopHint) + self.note.setReadOnly(True) + self.setWindowIcon(QtGui.QIcon('../../images/logo.png')) + self.setLayout(self.grid) + self.show() + + + def defaultWorkspace(self): + print "Default workspace selected : "+self.obj_appconfig.default_workspace["workspace"] + self.imp_var=1 + self.obj_appconfig.print_info('Default workspace selected : ' + self.obj_appconfig.default_workspace["workspace"]) + self.close() + var_appView.show() + time.sleep(1) + var_appView.splash.close() + + + + + def close(self, *args, **kwargs): + self.window_open_close=1 + self.close_var=1 + return QtGui.QWidget.close(self, *args, **kwargs) + + + def returnWhetherClickedOrNot(self,appView): + global var_appView + var_appView=appView + + + def createWorkspace(self): + print "Function : Create workspace" + self.create_workspace = str(self.workspace_loc.text()) + self.obj_appconfig.print_info('Workspace : ' + self.create_workspace) + #Checking if Workspace already exist or not + if os.path.isdir(self.create_workspace): + self.obj_appconfig.default_workspace["workspace"] = self.create_workspace + else: + os.mkdir(self.create_workspace) + self.obj_appconfig.default_workspace["workspace"] = self.create_workspace + self.imp_var=1 + self.close() + var_appView.show() + time.sleep(1) + var_appView.splash.close() + + + def browseLocation(self): + print "Function : Browse Location" + self.workspace_directory = QtGui.QFileDialog.getExistingDirectory(self, "Browse Location",os.path.expanduser("~")) + self.workspace_loc.setText(self.workspace_directory) +
\ No newline at end of file diff --git a/src/frontEnd/Workspace.pyc b/src/frontEnd/Workspace.pyc Binary files differnew file mode 100644 index 00000000..eb6e473c --- /dev/null +++ b/src/frontEnd/Workspace.pyc diff --git a/src/frontEnd/__init__.py b/src/frontEnd/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/frontEnd/__init__.py diff --git a/src/frontEnd/__init__.pyc b/src/frontEnd/__init__.pyc Binary files differnew file mode 100644 index 00000000..708ce1aa --- /dev/null +++ b/src/frontEnd/__init__.pyc diff --git a/src/kicadtoNgspice/Analysis.py b/src/kicadtoNgspice/Analysis.py new file mode 100644 index 00000000..a573c540 --- /dev/null +++ b/src/kicadtoNgspice/Analysis.py @@ -0,0 +1,641 @@ + +from PyQt4 import QtGui +import TrackWidget +import os +from xml.etree import ElementTree as ET + +class Analysis(QtGui.QWidget): + """ + This class create Analysis Tab in KicadtoNgspice Window. + """ + def __init__(self,clarg1): + self.clarg1=clarg1 + QtGui.QWidget.__init__(self) + self.track_obj= TrackWidget.TrackWidget() + self.count =0 + self.parameter_cnt=0 + self.ac_entry_var={} + self.dc_entry_var={} + self.tran_entry_var={} + self.ac_parameter={} + self.dc_parameter={} + self.tran_parameter= {} + self.createAnalysisWidget() + + + + def createAnalysisWidget(self): + self.grid = QtGui.QGridLayout() + self.grid.addWidget(self.createCheckBox(),0,0) + self.grid.addWidget(self.createACgroup(),1,0) + self.grid.addWidget(self.createDCgroup(),2,0) + self.grid.addWidget(self.createTRANgroup(),3,0) + + try: + kicadFile = self.clarg1 + (projpath,filename)=os.path.split(kicadFile) + if os.path.isfile(os.path.join(projpath, 'analysis')): + print "Analysis file is present" + analysisfile = open(os.path.join(projpath,'analysis')) + content = analysisfile.readline() + print "Content of Analysis file :", content + contentlist= content.split() + if contentlist[0]== '.ac': + self.checkAC.setChecked(True) + self.acbox.setDisabled(False) + self.dcbox.setDisabled(True) + self.trbox.setDisabled(True) + self.track_obj.set_CheckBox["ITEMS"]="AC" + if contentlist[1]== 'lin': + self.Lin.setChecked(True) + self.track_obj.AC_type["ITEMS"]="lin" + elif contentlist[1]== 'dec': + self.Dec.setChecked(True) + self.track_obj.AC_type["ITEMS"]="dec" + elif contentlist[1]== 'oct': + self.Oct.setChecked(True) + self.track_obj.AC_type["ITEMS"]="oct" + + elif contentlist[0]== '.dc': + self.checkDC.setChecked(True) + self.dcbox.setDisabled(False) + self.acbox.setDisabled(True) + self.trbox.setDisabled(True) + self.track_obj.set_CheckBox["ITEMS"]="DC" + + elif contentlist[0]== '.tran': + self.checkTRAN.setChecked(True) + self.trbox.setDisabled(False) + self.acbox.setDisabled(True) + self.dcbox.setDisabled(True) + self.track_obj.set_CheckBox["ITEMS"]="TRAN" + + elif contentlist[0]== '.op': + self.checkDC.setChecked(True) + self.dcbox.setDisabled(False) + self.acbox.setDisabled(True) + self.trbox.setDisabled(True) + self.check.setChecked(True) + except: + self.checkTRAN.setChecked(True) + self.track_obj.set_CheckBox["ITEMS"]="TRAN" + + self.setLayout(self.grid) + self.show() + + def createCheckBox(self): + self.checkbox = QtGui.QGroupBox() + self.checkbox.setTitle("Select Analysis Type") + self.checkgrid = QtGui.QGridLayout() + + self.checkgroupbtn = QtGui.QButtonGroup() + self.checkAC = QtGui.QCheckBox("AC") + self.checkDC = QtGui.QCheckBox("DC") + self.checkTRAN = QtGui.QCheckBox("TRANSIENT") + self.checkgroupbtn.addButton(self.checkAC) + self.checkgroupbtn.addButton(self.checkDC) + self.checkgroupbtn.addButton(self.checkTRAN) + self.checkgroupbtn.setExclusive(True) + self.checkgroupbtn.buttonClicked.connect(self.enableBox) + + self.checkgrid.addWidget(self.checkAC,0,0) + self.checkgrid.addWidget(self.checkDC,0,1) + self.checkgrid.addWidget(self.checkTRAN,0,2) + self.checkbox.setLayout(self.checkgrid) + + return self.checkbox + + + def enableBox(self): + if self.checkAC.isChecked(): + self.acbox.setDisabled(False) + self.dcbox.setDisabled(True) + self.trbox.setDisabled(True) + self.track_obj.set_CheckBox["ITEMS"]="AC" + + elif self.checkDC.isChecked(): + self.dcbox.setDisabled(False) + self.acbox.setDisabled(True) + self.trbox.setDisabled(True) + self.track_obj.set_CheckBox["ITEMS"]="DC" + + elif self.checkTRAN.isChecked(): + self.trbox.setDisabled(False) + self.acbox.setDisabled(True) + self.dcbox.setDisabled(True) + self.track_obj.set_CheckBox["ITEMS"]="TRAN" + + def createACgroup(self): + kicadFile = self.clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="analysis": + root=child + except: + check=0 + print "AC Previous Values XML is Empty" + + self.acbox = QtGui.QGroupBox() + self.acbox.setTitle("AC Analysis") + self.acbox.setDisabled(True) + self.acgrid = QtGui.QGridLayout() + self.radiobuttongroup= QtGui.QButtonGroup() + self.Lin = QtGui.QRadioButton("Lin") + self.Dec = QtGui.QRadioButton("Dec") + self.Oct = QtGui.QRadioButton("Oct") + self.radiobuttongroup.addButton(self.Lin) + self.radiobuttongroup.addButton(self.Dec) + self.radiobuttongroup.addButton(self.Oct) + self.radiobuttongroup.setExclusive(True) + self.Lin.setChecked(True) + self.track_obj.AC_type["ITEMS"]="lin" + self.radiobuttongroup.buttonClicked.connect(self.set_ac_type) + self.acgrid.addWidget(self.Lin,1,1) + self.acgrid.addWidget(self.Dec,1,2) + self.acgrid.addWidget(self.Oct,1,3) + self.acbox.setLayout(self.acgrid) + + self.scale = QtGui.QLabel("Scale") + self.start_fre_lable = QtGui.QLabel("Start Frequency") + self.stop_fre_lable = QtGui.QLabel("Stop Frequency") + self.no_of_points = QtGui.QLabel("No.of Points") + self.acgrid.addWidget(self.scale,1,0) + self.acgrid.addWidget(self.start_fre_lable,2,0) + self.acgrid.addWidget(self.stop_fre_lable,3,0) + self.acgrid.addWidget(self.no_of_points,4,0) + + self.count=0 + self.ac_entry_var[self.count] = QtGui.QLineEdit()#start + self.acgrid.addWidget(self.ac_entry_var[self.count],2,1) + self.ac_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.ac_entry_var[self.count] = QtGui.QLineEdit()#stop + self.acgrid.addWidget(self.ac_entry_var[self.count],3,1) + self.ac_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.ac_entry_var[self.count] = QtGui.QLineEdit()#no of pts + self.acgrid.addWidget(self.ac_entry_var[self.count],4,1) + self.ac_entry_var[self.count].setMaximumWidth(150) + + self.parameter_cnt=0 + self.start_fre_combo = QtGui.QComboBox() + self.start_fre_combo.addItem("Hz",) + self.start_fre_combo.addItem("KHz") + self.start_fre_combo.addItem("Meg") + self.start_fre_combo.addItem("GHz") + self.start_fre_combo.addItem("THz") + self.start_fre_combo.setMaximumWidth(150) + self.acgrid.addWidget(self.start_fre_combo,2,2) + self.ac_parameter[0]= "Hz" + try: + self.ac_parameter[self.parameter_cnt]= str(root[0][6].text) + except: + self.ac_parameter[self.parameter_cnt]= "Hz" + self.start_fre_combo.activated[str].connect(self.start_combovalue) + + self.parameter_cnt=self.parameter_cnt + 1 + self.stop_fre_combo = QtGui.QComboBox() + self.stop_fre_combo.addItem("Hz") + self.stop_fre_combo.addItem("KHz") + self.stop_fre_combo.addItem("Meg") + self.stop_fre_combo.addItem("GHz") + self.stop_fre_combo.addItem("THz") + self.stop_fre_combo.setMaximumWidth(150) + self.acgrid.addWidget(self.stop_fre_combo,3,2) + self.ac_parameter[1]= "Hz" + try: + self.ac_parameter[self.parameter_cnt]= str(root[0][7].text) + except: + self.ac_parameter[self.parameter_cnt]= "Hz" + self.stop_fre_combo.activated[str].connect(self.stop_combovalue) + + + self.track_obj.AC_entry_var["ITEMS"]=self.ac_entry_var + self.track_obj.AC_Parameter["ITEMS"]=self.ac_parameter + + #CSS + self.acbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + if check: + try: + if root[0][0].text=="true": + self.Lin.setChecked(True) + self.Dec.setChecked(False) + self.Oct.setChecked(False) + elif root[0][1].text=="true": + self.Lin.setChecked(False) + self.Dec.setChecked(True) + self.Oct.setChecked(False) + elif root[0][2].text=="true": + self.Lin.setChecked(False) + self.Dec.setChecked(False) + self.Oct.setChecked(True) + else: + pass + self.ac_entry_var[0].setText(root[0][3].text) + self.ac_entry_var[1].setText(root[0][4].text) + self.ac_entry_var[2].setText(root[0][5].text) + index=self.start_fre_combo.findText(root[0][6].text) + self.start_fre_combo.setCurrentIndex(index) + index=self.stop_fre_combo.findText(root[0][7].text) + self.stop_fre_combo.setCurrentIndex(index) + except: + print "AC Analysis XML Parse Error" + + return self.acbox + + def start_combovalue(self, text): + self.ac_parameter[0]= str(text) + + def stop_combovalue(self, text): + self.ac_parameter[1]= str(text) + + def set_ac_type(self): + self.parameter_cnt=0 + if self.Lin.isChecked(): + self.track_obj.AC_type["ITEMS"]="lin" + elif self.Dec.isChecked(): + self.track_obj.AC_type["ITEMS"]= "dec" + elif self.Oct.isChecked(): + self.track_obj.AC_type["ITEMS"]="oct" + else: + pass + + def createDCgroup(self): + kicadFile = self.clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="analysis": + root=child + except: + check=0 + print "DC Previous Values XML is empty" + + self.dcbox = QtGui.QGroupBox() + self.dcbox.setTitle("DC Analysis") + self.dcbox.setDisabled(True) + self.dcgrid = QtGui.QGridLayout() + self.dcbox.setLayout(self.dcgrid) + + self.source_name= QtGui.QLabel('Enter Source 1',self) + self.source_name.setMaximumWidth(150) + self.start= QtGui.QLabel('Start', self) + self.start.setMaximumWidth(150) + self.increment=QtGui.QLabel('Increment',self) + self.increment.setMaximumWidth(150) + self.stop=QtGui.QLabel('Stop',self) + self.stop.setMaximumWidth(150) + + self.source_name2= QtGui.QLabel('Enter Source 2',self) + self.source_name2.setMaximumWidth(150) + self.start2= QtGui.QLabel('Start', self) + self.start2.setMaximumWidth(150) + self.increment2=QtGui.QLabel('Increment',self) + self.increment2.setMaximumWidth(150) + self.stop2=QtGui.QLabel('Stop',self) + self.stop2.setMaximumWidth(150) + + self.dcgrid.addWidget(self.source_name,1,0) + self.dcgrid.addWidget(self.start,2,0) + self.dcgrid.addWidget(self.increment,3,0) + self.dcgrid.addWidget(self.stop,4,0) + + self.dcgrid.addWidget(self.source_name2,5,0) + self.dcgrid.addWidget(self.start2,6,0) + self.dcgrid.addWidget(self.increment2,7,0) + self.dcgrid.addWidget(self.stop2,8,0) + + self.count=0 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#source + self.dcgrid.addWidget(self.dc_entry_var[self.count],1,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#start + self.dcgrid.addWidget(self.dc_entry_var[self.count],2,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#increment + self.dcgrid.addWidget(self.dc_entry_var[self.count],3,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#stop + self.dcgrid.addWidget(self.dc_entry_var[self.count],4,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count=self.count+1 + + self.dc_entry_var[self.count] = QtGui.QLineEdit()#source + self.dcgrid.addWidget(self.dc_entry_var[self.count],5,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#start + self.dcgrid.addWidget(self.dc_entry_var[self.count],6,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#increment + self.dcgrid.addWidget(self.dc_entry_var[self.count],7,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.dc_entry_var[self.count] = QtGui.QLineEdit()#stop + self.dcgrid.addWidget(self.dc_entry_var[self.count],8,1) + self.dc_entry_var[self.count].setMaximumWidth(150) + + self.parameter_cnt=0 + self.start_combo=QtGui.QComboBox(self) + self.start_combo.setMaximumWidth(150) + self.start_combo.addItem('Volts or Amperes') + self.start_combo.addItem('mV or mA') + self.start_combo.addItem('uV or uA') + self.start_combo.addItem("nV or nA") + self.start_combo.addItem("pV or pA") + self.dcgrid.addWidget(self.start_combo,2,2) + try: + self.dc_parameter[self.parameter_cnt]= str(root[1][5].text) + except: + self.dc_parameter[self.parameter_cnt]= "Volts or Amperes" + self.start_combo.activated[str].connect(self.start_changecombo) + self.parameter_cnt= self.parameter_cnt+1 + + self.increment_combo=QtGui.QComboBox(self) + self.increment_combo.setMaximumWidth(150) + self.increment_combo.addItem("Volts or Amperes") + self.increment_combo.addItem("mV or mA") + self.increment_combo.addItem("uV or uA") + self.increment_combo.addItem("nV or nA") + self.increment_combo.addItem("pV or pA") + self.dcgrid.addWidget(self.increment_combo,3,2) + try: + self.dc_parameter[self.parameter_cnt]= str(root[1][6].text) + except: + self.dc_parameter[self.parameter_cnt]= "Volts or Amperes" + self.increment_combo.activated[str].connect(self.increment_changecombo) + self.parameter_cnt= self.parameter_cnt+1 + + self.stop_combo=QtGui.QComboBox(self) + self.stop_combo.setMaximumWidth(150) + self.stop_combo.addItem("Volts or Amperes") + self.stop_combo.addItem("mV or mA") + self.stop_combo.addItem("uV or uA") + self.stop_combo.addItem("nV or nA") + self.stop_combo.addItem("pV or pA") + self.dcgrid.addWidget(self.stop_combo,4,2) + try: + self.dc_parameter[self.parameter_cnt]= str(root[1][7].text) + except: + self.dc_parameter[self.parameter_cnt]= "Volts or Amperes" + self.stop_combo.activated[str].connect(self.stop_changecombo) + self.parameter_cnt= self.parameter_cnt+1 + + self.start_combo2=QtGui.QComboBox(self) + self.start_combo2.setMaximumWidth(150) + self.start_combo2.addItem('Volts or Amperes') + self.start_combo2.addItem('mV or mA') + self.start_combo2.addItem('uV or uA') + self.start_combo2.addItem("nV or nA") + self.start_combo2.addItem("pV or pA") + self.dcgrid.addWidget(self.start_combo2,6,2) + try: + self.dc_parameter[self.parameter_cnt]= str(root[1][12].text) + except: + self.dc_parameter[self.parameter_cnt]= "Volts or Amperes" + self.start_combo2.activated[str].connect(self.start_changecombo2) + self.parameter_cnt= self.parameter_cnt+1 + + self.increment_combo2=QtGui.QComboBox(self) + self.increment_combo2.setMaximumWidth(150) + self.increment_combo2.addItem("Volts or Amperes") + self.increment_combo2.addItem("mV or mA") + self.increment_combo2.addItem("uV or uA") + self.increment_combo2.addItem("nV or nA") + self.increment_combo2.addItem("pV or pA") + self.dcgrid.addWidget(self.increment_combo2,7,2) + try: + self.dc_parameter[self.parameter_cnt]= str(root[1][13].text) + except: + self.dc_parameter[self.parameter_cnt]= "Volts or Amperes" + self.increment_combo2.activated[str].connect(self.increment_changecombo2) + self.parameter_cnt= self.parameter_cnt+1 + + self.stop_combo2=QtGui.QComboBox(self) + self.stop_combo2.setMaximumWidth(150) + self.stop_combo2.addItem("Volts or Amperes") + self.stop_combo2.addItem("mV or mA") + self.stop_combo2.addItem("uV or uA") + self.stop_combo2.addItem("nV or nA") + self.stop_combo2.addItem("pV or pA") + self.dcgrid.addWidget(self.stop_combo2,8,2) + try: + self.dc_parameter[self.parameter_cnt]= str(root[1][14].text) + + except: + self.dc_parameter[self.parameter_cnt]= "Volts or Amperes" + self.stop_combo2.activated[str].connect(self.stop_changecombo2) + self.parameter_cnt= self.parameter_cnt+1 + + self.check=QtGui.QCheckBox('Operating Point Analysis',self) + try: + self.track_obj.op_check.append(str(root[1][4].text())) + except: + self.track_obj.op_check.append(0) + #QtCore.QObject.connect(check,SIGNAL("stateChanged()"),check,SLOT("checkedSlot")) + self.check.stateChanged.connect(self.setflag) + #self.flagcheck = 1 + #self.flagcheck= 2 + self.dcgrid.addWidget(self.check,9,1,9,2) + self.track_obj.DC_entry_var["ITEMS"]=self.dc_entry_var + self.track_obj.DC_Parameter["ITEMS"]=self.dc_parameter + + #CSS + self.dcbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + if check: + try: + self.dc_entry_var[0].setText(root[1][0].text) + self.dc_entry_var[1].setText(root[1][1].text) + self.dc_entry_var[2].setText(root[1][2].text) + self.dc_entry_var[3].setText(root[1][3].text) + index=self.start_combo.findText(root[1][5].text) + self.start_combo.setCurrentIndex(index) + index=self.increment_combo.findText(root[1][6].text) + self.increment_combo.setCurrentIndex(index) + index=self.stop_combo.findText(root[1][7].text) + self.stop_combo.setCurrentIndex(index) + self.dc_entry_var[4].setText(root[1][8].text) + self.dc_entry_var[5].setText(root[1][9].text) + self.dc_entry_var[6].setText(root[1][10].text) + self.dc_entry_var[7].setText(root[1][11].text) + index=self.start_combo2.findText(root[1][12].text) + self.start_combo2.setCurrentIndex(index) + index=self.increment_combo2.findText(root[1][13].text) + self.increment_combo2.setCurrentIndex(index) + index=self.stop_combo2.findText(root[1][14].text) + self.stop_combo2.setCurrentIndex(index) + + if root[1][4].text== 1: + self.check.setChecked(True) + else: + self.check.setChecked(False) + except: + print "DC Analysis XML Parse Error" + + return self.dcbox + + def start_changecombo(self,text): + self.dc_parameter[0]=str(text) + + def increment_changecombo(self,text): + self.dc_parameter[1]=str(text) + + def stop_changecombo(self,text): + self.dc_parameter[2]=str(text) + + def start_changecombo2(self,text): + self.dc_parameter[3]=str(text) + + def increment_changecombo2(self,text): + self.dc_parameter[4]=str(text) + + def stop_changecombo2(self,text): + self.dc_parameter[5]=str(text) + + def setflag(self): + if self.check.isChecked(): + self.track_obj.op_check.append(1) + else: + self.track_obj.op_check.append(0) + + def createTRANgroup(self): + kicadFile = self.clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="analysis": + root=child + except: + check=0 + print "Transient Previous Values XML is Empty" + + self.trbox = QtGui.QGroupBox() + self.trbox.setTitle("Transient Analysis") + #self.trbox.setDisabled(True) + self.trgrid = QtGui.QGridLayout() + self.trbox.setLayout(self.trgrid) + + self.start = QtGui.QLabel("Start Time") + self.step = QtGui.QLabel("Step Time") + self.stop = QtGui.QLabel("Stop Time") + self.trgrid.addWidget(self.start,1,0) + self.trgrid.addWidget(self.step,2,0) + self.trgrid.addWidget(self.stop,3,0) + self.count=0 + + self.tran_entry_var[self.count] = QtGui.QLineEdit() + self.trgrid.addWidget(self.tran_entry_var[self.count],1,1) + self.tran_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.tran_entry_var[self.count] = QtGui.QLineEdit() + self.trgrid.addWidget(self.tran_entry_var[self.count],2,1) + self.tran_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + self.tran_entry_var[self.count] = QtGui.QLineEdit() + self.trgrid.addWidget(self.tran_entry_var[self.count],3,1) + self.tran_entry_var[self.count].setMaximumWidth(150) + self.count= self.count+1 + + self.parameter_cnt=0 + self.start_combobox = QtGui.QComboBox() + self.start_combobox.addItem("Sec") + self.start_combobox.addItem("ms") + self.start_combobox.addItem("us") + self.start_combobox.addItem("ns") + self.start_combobox.addItem("ps") + self.trgrid.addWidget(self.start_combobox,1,3) + try: + self.tran_parameter[self.parameter_cnt]= str(root[2][3].text) + except: + self.tran_parameter[self.parameter_cnt]= "Sec" + self.start_combobox.activated[str].connect(self.start_combo_change) + self.parameter_cnt= self.parameter_cnt+1 + + self.step_combobox = QtGui.QComboBox() + self.step_combobox.addItem("Sec") + self.step_combobox.addItem("ms") + self.step_combobox.addItem("us") + self.step_combobox.addItem("ns") + self.step_combobox.addItem("ps") + self.trgrid.addWidget(self.step_combobox,2,3) + try: + self.tran_parameter[self.parameter_cnt]= str(root[2][4].text) + except: + self.tran_parameter[self.parameter_cnt]= "Sec" + self.step_combobox.activated[str].connect(self.step_combo_change) + self.parameter_cnt= self.parameter_cnt+1 + + self.stop_combobox = QtGui.QComboBox() + self.stop_combobox.addItem("Sec") + self.stop_combobox.addItem("ms") + self.stop_combobox.addItem("us") + self.stop_combobox.addItem("ns") + self.stop_combobox.addItem("ps") + self.trgrid.addWidget(self.stop_combobox,3,3) + try: + self.tran_parameter[self.parameter_cnt]= str(root[2][5].text) + except: + self.tran_parameter[self.parameter_cnt]= "Sec" + self.stop_combobox.activated[str].connect(self.stop_combo_change) + self.parameter_cnt= self.parameter_cnt+1 + + self.track_obj.TRAN_entry_var["ITEMS"]=self.tran_entry_var + self.track_obj.TRAN_Parameter["ITEMS"]=self.tran_parameter + + #CSS + self.trbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + if check: + try: + self.tran_entry_var[0].setText(root[2][0].text) + self.tran_entry_var[1].setText(root[2][1].text) + self.tran_entry_var[2].setText(root[2][2].text) + index=self.start_combobox.findText(root[2][3].text) + self.start_combobox.setCurrentIndex(index) + index=self.step_combobox.findText(root[2][4].text) + self.step_combobox.setCurrentIndex(index) + + index=self.stop_combobox.findText(root[2][5].text) + self.stop_combobox.setCurrentIndex(index) + except: + print "Transient Analysis XML Parse Error" + + + return self.trbox + + def start_combo_change(self,text): + self.tran_parameter[0]=str(text) + + def step_combo_change(self,text): + self.tran_parameter[1]=str(text) + + def stop_combo_change(self,text): + self.tran_parameter[2]=str(text) diff --git a/src/kicadtoNgspice/Analysis.pyc b/src/kicadtoNgspice/Analysis.pyc Binary files differnew file mode 100644 index 00000000..20c0689e --- /dev/null +++ b/src/kicadtoNgspice/Analysis.pyc diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py new file mode 100644 index 00000000..f02435d2 --- /dev/null +++ b/src/kicadtoNgspice/Convert.py @@ -0,0 +1,454 @@ +from PyQt4 import QtGui + +import os +import shutil +import TrackWidget +from xml.etree import ElementTree as ET + +class Convert: + """ + This class has all the necessary function required to convert kicad netlist to ngspice netlist. + """ + def __init__(self,sourcelisttrack,source_entry_var,schematicInfo,clarg1): + self.sourcelisttrack = sourcelisttrack + self.schematicInfo = schematicInfo + self.entry_var = source_entry_var + self.sourcelistvalue = [] + self.clarg1=clarg1 + + + def addSourceParameter(self): + """ + This function add the source details to schematicInfo + """ + + self.start = 0 + self.end = 0 + + for compline in self.sourcelisttrack: + self.index = compline[0] + self.addline = self.schematicInfo[self.index] + if compline[1] == 'sine': + try: + self.start = compline[2] + self.end = compline[3] + vo_val = str(self.entry_var[self.start].text()) if len(str(self.entry_var[self.start].text())) > 0 else '0' + va_val = str(self.entry_var[self.start+1].text()) if len(str(self.entry_var[self.start+1].text())) > 0 else '0' + freq_val = str(self.entry_var[self.start+2].text()) if len(str(self.entry_var[self.start+2].text())) > 0 else '0' + td_val = str(self.entry_var[self.start+3].text()) if len(str(self.entry_var[self.start+3].text())) > 0 else '0' + theta_val = str(self.entry_var[self.end].text()) if len(str(self.entry_var[self.end].text())) > 0 else '0' + self.addline = self.addline.partition('(')[0] + "("+vo_val+" "+va_val+" "+freq_val+" "+td_val+" "+theta_val+")" + self.sourcelistvalue.append([self.index,self.addline]) + except: + print "Caught an exception in sine voltage source ",self.addline + + elif compline[1] == 'pulse': + try: + self.start = compline[2] + self.end = compline[3] + v1_val = str(self.entry_var[self.start].text()) if len(str(self.entry_var[self.start].text())) > 0 else '0' + v2_val = str(self.entry_var[self.start+1].text()) if len(str(self.entry_var[self.start+1].text())) > 0 else '0' + td_val = str(self.entry_var[self.start+2].text()) if len(str(self.entry_var[self.start+2].text())) > 0 else '0' + tr_val = str(self.entry_var[self.start+3].text()) if len(str(self.entry_var[self.start+3].text())) > 0 else '0' + tf_val = str(self.entry_var[self.start+4].text()) if len(str(self.entry_var[self.start+4].text())) > 0 else '0' + pw_val = str(self.entry_var[self.start+5].text()) if len(str(self.entry_var[self.start+5].text())) > 0 else '0' + tp_val = str(self.entry_var[self.end].text()) if len(str(self.entry_var[self.end].text())) > 0 else '0' + + self.addline = self.addline.partition('(')[0] + "("+v1_val+" "+v2_val+" "+td_val+" "+tr_val+" "+tf_val+" "+pw_val+" "+tp_val+")" + self.sourcelistvalue.append([self.index,self.addline]) + except: + print "Caught an exception in pulse voltage source ",self.addline + + elif compline[1] == 'pwl': + try: + self.start = compline[2] + self.end = compline[3] + t_v_val = str(self.entry_var[self.start].text()) if len(str(self.entry_var[self.start].text())) > 0 else '0 0' + self.addline = self.addline.partition('(')[0] + "("+t_v_val+")" + self.sourcelistvalue.append([self.index,self.addline]) + except: + print "Caught an exception in pwl voltage source ",self.addline + + elif compline[1] == 'ac': + try: + self.start = compline[2] + self.end = compline[3] + va_val=str(self.entry_var[self.start].text()) if len(str(self.entry_var[self.start].text())) > 0 else '0' + ph_val=str(self.entry_var[self.start+1].text()) if len(str(self.entry_var[self.start+1].text())) > 0 else '0' + self.addline = ' '.join(self.addline.split()) + self.addline = self.addline.partition('ac')[0] +" "+'ac'+" "+ va_val+" "+ph_val + self.sourcelistvalue.append([self.index,self.addline]) + except: + print "Caught an exception in ac voltage source ",self.addline + + elif compline[1] == 'dc': + try: + self.start = compline[2] + self.end = compline[3] + v1_val = str(self.entry_var[self.start].text()) if len(str(self.entry_var[self.start].text())) > 0 else '0' + self.addline = ' '.join(self.addline.split()) + self.addline = self.addline.partition('dc')[0] + " " +'dc'+ " "+v1_val + self.sourcelistvalue.append([self.index,self.addline]) + except: + print "Caught an exception in dc voltage source",self.addline + + elif compline[1] == 'exp': + try: + self.start = compline[2] + self.end = compline[3] + v1_val = str(self.entry_var[self.start].text()) if len(str(self.entry_var[self.start].text())) > 0 else '0' + v2_val = str(self.entry_var[self.start+1].text()) if len(str(self.entry_var[self.start+1].text())) > 0 else '0' + td1_val = str(self.entry_var[self.start+2].text()) if len(str(self.entry_var[self.start+2].text())) > 0 else '0' + tau1_val = str(self.entry_var[self.start+3].text()) if len(str(self.entry_var[self.start+3].text())) > 0 else '0' + td2_val = str(self.entry_var[self.start+4].text()) if len(str(self.entry_var[self.start+4].text())) > 0 else '0' + tau2_val = str(self.entry_var[self.end].text()) if len(str(self.entry_var[self.end].text())) > 0 else '0' + + self.addline = self.addline.partition('(')[0] + "("+v1_val+" "+v2_val+" "+td1_val+" "+tau1_val+" "+td2_val+" "+tau2_val+")" + self.sourcelistvalue.append([self.index,self.addline]) + except: + print "Caught an exception in exp voltage source ",self.addline + + #Updating Schematic with source value + for item in self.sourcelistvalue: + del self.schematicInfo[item[0]] + self.schematicInfo.insert(item[0],item[1]) + + return self.schematicInfo + + + def analysisInsertor(self,ac_entry_var,dc_entry_var, tran_entry_var,set_checkbox,ac_parameter,dc_parameter,tran_parameter,ac_type,op_check): + """ + This function creates an analysis file in current project + """ + self.ac_entry_var = ac_entry_var + self.dc_entry_var = dc_entry_var + self.tran_entry_var = tran_entry_var + self.set_checkbox = set_checkbox + self.ac_parameter= ac_parameter + self.dc_parameter= dc_parameter + self.trans_parameter = tran_parameter + self.ac_type= ac_type + self.op_check = op_check + self.no=0 + + self.variable=self.set_checkbox + self.direct= self.clarg1 + (filepath, filemname)= os.path.split(self.direct) + self.Fileopen = os.path.join(filepath, "analysis") + self.writefile= open(self.Fileopen,"w") + if self.variable== 'AC': + self.no=0 + self.writefile.write(".ac"+' ' + self.ac_type + ' '+ str(self.defaultvalue(self.ac_entry_var[self.no+2].text()))+' ' + str(self.defaultvalue(self.ac_entry_var[self.no].text())) + self.ac_parameter[self.no]+ ' ' + str(self.defaultvalue(self.ac_entry_var[self.no+1].text())) + self.ac_parameter[self.no+1] ) + + elif self.variable=='DC': + if self.op_check[-1] == 1: + self.no=0 + self.writefile.write(".op") + elif self.op_check[-1] == 0: + self.no=0 + self.writefile.write(".dc" +' '+ str(self.dc_entry_var[self.no].text())+ ' '+ str(self.defaultvalue(self.dc_entry_var[self.no+1].text())) + self.converttosciform(self.dc_parameter[self.no]) + ' '+ str(self.defaultvalue(self.dc_entry_var[self.no+3].text()))+ self.converttosciform(self.dc_parameter[self.no+2]) + ' '+ str(self.defaultvalue(self.dc_entry_var[self.no+2].text())) + self.converttosciform(self.dc_parameter[self.no+1])) + + if self.dc_entry_var[self.no+4].text(): + self.writefile.write(' '+ str(self.defaultvalue(self.dc_entry_var[self.no+4].text()))+ ' '+ str(self.defaultvalue(self.dc_entry_var[self.no+5].text())) + self.converttosciform(self.dc_parameter[self.no+3])+ ' '+ str(self.defaultvalue(self.dc_entry_var[self.no+7].text()))+ self.converttosciform(self.dc_parameter[self.no+5])+ ' ' + str(self.defaultvalue(self.dc_entry_var[self.no+6].text()))+ self.converttosciform(self.dc_parameter[self.no+4])) + + elif self.variable == 'TRAN': + self.no= 0 + self.writefile.write(".tran" + ' '+ str(self.defaultvalue(self.tran_entry_var[self.no+1].text())) + self.converttosciform(self.trans_parameter[self.no+1]) + ' ' + str(self.defaultvalue(self.tran_entry_var[self.no+2].text())) + self.converttosciform(self.trans_parameter[self.no+2])+' '+ str(self.defaultvalue(self.tran_entry_var[self.no].text()))+ self.converttosciform(self.trans_parameter[self.no])) + + else: + pass + self.writefile.close() + + def converttosciform(self, string_obj): + """ + This function is used for scientific conversion. + """ + self.string_obj = string_obj + if self.string_obj[0] == 'm': + return "e-03" + elif self.string_obj[0] == 'u': + return "e-06" + elif self.string_obj[0] == 'n': + return "e-09" + elif self.string_obj[0] == 'p': + return "e-12" + else: + return "e-00" + + def defaultvalue(self, value): + """ + This function select default value as 0 if Analysis widget do not hold any value. + """ + self.value= value + if self.value == '': + return 0 + else: + return self.value + + + def addModelParameter(self,schematicInfo): + """ + This function add the Ngspice Model details to schematicInfo + """ + + #Create object of TrackWidget + self.obj_track = TrackWidget.TrackWidget() + + #List to store model line + addmodelLine = [] + modelParamValue = [] + + for line in self.obj_track.modelTrack: + #print "Model Track :",line + if line[2] == 'transfo': + try: + start=line[7] + end=line[8] + num_turns=str(self.obj_track.model_entry_var[start+1].text()) + + if num_turns=="": num_turns="310" + h_array= "H_array = [ " + b_array = "B_array = [ " + h1=str(self.obj_track.model_entry_var[start].text()) + b1=str(self.obj_track.model_entry_var[start+5].text()) + + if len(h1)!=0 and len(b1)!=0: + h_array=h_array+h1+" " + b_array=b_array+b1+" " + bh_array = h_array+" ] " + b_array+" ]" + else: + bh_array = "H_array = [-1000 -500 -375 -250 -188 -125 -63 0 63 125 188 250 375 500 1000] B_array = [-3.13e-3 -2.63e-3 -2.33e-3 -1.93e-3 -1.5e-3 -6.25e-4 -2.5e-4 0 2.5e-4 6.25e-4 1.5e-3 1.93e-3 2.33e-3 2.63e-3 3.13e-3]" + area=str(self.obj_track.model_entry_var[start+2].text()) + length=str(self.obj_track.model_entry_var[start+3].text()) + if area=="": area="1" + if length=="":length="0.01" + num_turns2=str(self.obj_track.model_entry_var[start+4].text()) + if num_turns2=="": num_turns2="620" + addmodelLine=".model "+line[3]+"_primary lcouple (num_turns= "+num_turns+")" + modelParamValue.append([line[0],addmodelLine,"*primary lcouple"]) + addmodelLine=".model "+line[3]+"_iron_core core ("+bh_array+" area = "+area+" length ="+length +")" + modelParamValue.append([line[0],addmodelLine,"*iron core"]) + addmodelLine=".model "+line[3]+"_secondary lcouple (num_turns ="+num_turns2+ ")" + modelParamValue.append([line[0],addmodelLine,"*secondary lcouple"]) + except Exception as e: + print "Caught an exception in transfo model ",line[1] + print "Exception Message : ",str(e) + + elif line[2] == 'ic': + try: + start=line[7] + end=line[8] + for key,value in line[9].iteritems(): + initVal = str(self.obj_track.model_entry_var[value].text()) + if initVal=="":initVal="0" + node = line[1].split()[1] #Extracting node from model line + addmodelLine = ".ic v("+node+")="+initVal + modelParamValue.append([line[0],addmodelLine,line[4]]) + except Exception as e: + print "Caught an exception in initial condition ",line[1] + print "Exception Message : ",str(e) + + + else: + try: + start = line[7] + end = line[8] + addmodelLine=".model "+ line[3]+" "+line[2]+"(" + for key,value in line[9].iteritems(): + #print "Tags: ",key + #print "Value: ",value + #Checking for default value and accordingly assign param and default. + if ':' in key: + key = key.split(':') + param = key[0] + default = key[1] + else: + param = key + default = 0 + #Cheking if value is iterable.its for vector + if hasattr(value, '__iter__'): + addmodelLine += param+"=[" + for lineVar in value: + if str(self.obj_track.model_entry_var[lineVar].text()) == "": + paramVal = default + else: + paramVal = str(self.obj_track.model_entry_var[lineVar].text()) + addmodelLine += paramVal+" " + addmodelLine += "] " + else: + if str(self.obj_track.model_entry_var[value].text()) == "": + paramVal = default + else: + paramVal = str(self.obj_track.model_entry_var[value].text()) + + addmodelLine += param+"="+paramVal+" " + + + addmodelLine += ") " + modelParamValue.append([line[0],addmodelLine,line[4]]) + except Exception as e: + print "Caught an exception in model ",line[1] + print "Exception Message : ",str(e) + + + #Adding it to schematic + for item in modelParamValue: + if ".ic" in item[1]: + schematicInfo.insert(0,item[1]) + schematicInfo.insert(0,item[2]) + else: + schematicInfo.append(item[2]) #Adding Comment + schematicInfo.append(item[1]) #Adding model line + + return schematicInfo + + def addDeviceLibrary(self,schematicInfo,kicadFile): + """ + This function add the library details to schematicInfo + """ + + (projpath,filename) = os.path.split(kicadFile) + + + deviceLibList = self.obj_track.deviceModelTrack + deviceLine = {} #Key:Index, Value:with its updated line in the form of list + includeLine = [] #All .include line list + + if not deviceLibList: + print "No Library Added in the schematic" + pass + else: + for eachline in schematicInfo: + words = eachline.split() + if words[0] in deviceLibList: + print "Found Library line" + index = schematicInfo.index(eachline) + completeLibPath = deviceLibList[words[0]] + (libpath,libname) = os.path.split(completeLibPath) + print "Library Path :",libpath + #Copying library from devicemodelLibrary to Project Path + #Special case for MOSFET + if eachline[0] == 'm': + #For mosfet library name come along with MOSFET dimension information + tempStr = libname.split(':') + libname = tempStr[0] + dimension = tempStr[1] + #Replace last word with library name + #words[-1] = libname.split('.')[0] + words[-1] = self.getRefrenceName(libname,libpath) + #Appending Dimension of MOSFET + words.append(dimension) + deviceLine[index] = words + includeLine.append(".include "+libname) + + #src = completeLibPath.split(':')[0] # <----- Not working in Windows + + (src_path,src_lib) = os.path.split(completeLibPath) + src_lib = src_lib.split(':')[0] + src = os.path.join(src_path,src_lib) + dst = projpath + shutil.copy2(src, dst) + else: + #Replace last word with library name + #words[-1] = libname.split('.')[0] + words[-1] = self.getRefrenceName(libname,libpath) + deviceLine[index] = words + includeLine.append(".include "+libname) + + src = completeLibPath + dst = projpath + shutil.copy2(src,dst) + + else: + pass + + + #Adding device line to schematicInfo + for index,value in deviceLine.iteritems(): + #Update the device line + strLine = " ".join(str(item) for item in value) + schematicInfo[index] = strLine + + #This has to be second i.e after deviceLine details + #Adding .include line to Schematic Info at the start of line + for item in list(set(includeLine)): + schematicInfo.insert(0,item) + + + return schematicInfo + + def addSubcircuit(self,schematicInfo,kicadFile): + """ + This function add the subcircuit to schematicInfo + """ + + (projpath,filename) = os.path.split(kicadFile) + + subList = self.obj_track.subcircuitTrack + subLine = {} #Key:Index, Value:with its updated line in the form of list + includeLine = [] #All .include line list + + if len(self.obj_track.subcircuitList) != len(self.obj_track.subcircuitTrack): + self.msg = QtGui.QErrorMessage() + self.msg.showMessage("Conversion failed. Please add all Subcircuits.") + self.msg.setWindowTitle("Error Message") + self.msg.show() + raise Exception('All subcircuit directories need to be specified.') + elif not subList: + print "No Subcircuit Added in the schematic" + pass + else: + for eachline in schematicInfo: + words = eachline.split() + if words[0] in subList: + print "Found Subcircuit line" + index = schematicInfo.index(eachline) + completeSubPath = subList[words[0]] + (subpath,subname) = os.path.split(completeSubPath) + print "Library Path :",subpath + #Copying library from devicemodelLibrary to Project Path + + #Replace last word with library name + words[-1] = subname.split('.')[0] + subLine[index] = words + includeLine.append(".include "+subname+".sub") + + src = completeSubPath + dst = projpath + print os.listdir(src) + for files in os.listdir(src): + if os.path.isfile(os.path.join(src,files)): + if files != "analysis": + shutil.copy2(os.path.join(src,files),dst) + else: + pass + + + #Adding subcircuit line to schematicInfo + for index,value in subLine.iteritems(): + #Update the subcircuit line + strLine = " ".join(str(item) for item in value) + schematicInfo[index] = strLine + + #This has to be second i.e after subcircuitLine details + #Adding .include line to Schematic Info at the start of line + for item in list(set(includeLine)): + schematicInfo.insert(0,item) + + return schematicInfo + + def getRefrenceName(self,libname,libpath): + libname = libname.replace('.lib','.xml') + library = os.path.join(libpath,libname) + + #Extracting Value from XML + libtree = ET.parse(library) + for child in libtree.iter(): + if child.tag == 'ref_model': + retVal = child.text + else: + pass + return retVal + + + diff --git a/src/kicadtoNgspice/Convert.pyc b/src/kicadtoNgspice/Convert.pyc Binary files differnew file mode 100644 index 00000000..4f80394c --- /dev/null +++ b/src/kicadtoNgspice/Convert.pyc diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py new file mode 100644 index 00000000..a982d05f --- /dev/null +++ b/src/kicadtoNgspice/DeviceModel.py @@ -0,0 +1,357 @@ +from PyQt4 import QtGui +import os +from xml.etree import ElementTree as ET + +import TrackWidget + + +class DeviceModel(QtGui.QWidget): + """ + This class creates Device Library Tab in KicadtoNgspice Window + It dynamically creates the widget for device like diode,mosfet,transistor and jfet. + """ + + def __init__(self,schematicInfo,clarg1): + + self.clarg1=clarg1 + kicadFile = self.clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="devicemodel": + root=child + except: + check=0 + print "Device Model Previous XML is Empty" + + + QtGui.QWidget.__init__(self) + + #Creating track widget object + self.obj_trac = TrackWidget.TrackWidget() + + #Row and column count + self.row = 0 + self.count = 1 #Entry count + self.entry_var = {} + + #For MOSFET + self.widthLabel = {} + self.lengthLabel = {} + self.multifactorLable = {} + self.devicemodel_dict_beg={} + self.devicemodel_dict_end={} + #List to hold information about device + self.deviceDetail = {} + + #Set Layout + self.grid = QtGui.QGridLayout() + self.setLayout(self.grid) + print "Reading Device model details from Schematic" + + for eachline in schematicInfo: + words = eachline.split() + if eachline[0] == 'q': + print "Device Model Transistor: ",words[0] + self.devicemodel_dict_beg[words[0]]=self.count + transbox=QtGui.QGroupBox() + transgrid=QtGui.QGridLayout() + transbox.setTitle("Add library for Transistor "+words[0]+" : "+words[4]) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + global path_name + try: + for child in root: + if child.tag[0]==eachline[0] and child.tag[1]==eachline[1]: + #print "DEVICE MODEL MATCHING---",child.tag[0],child.tag[1],eachline[0],eachline[1] + try: + if os.path.exists(child[0].text): + self.entry_var[self.count].setText(child[0].text) + path_name=child[0].text + else: + self.entry_var[self.count].setText("") + except: + print "Error when set text of device model transistor" + except: + pass + transgrid.addWidget(self.entry_var[self.count],self.row,1) + self.addbtn = QtGui.QPushButton("Add") + self.addbtn.setObjectName("%d" %self.count) + self.addbtn.clicked.connect(self.trackLibrary) + self.deviceDetail[self.count] = words[0] + if self.entry_var[self.count].text()=="": + pass + else: + self.trackLibraryWithoutButton(self.count,path_name) + transgrid.addWidget(self.addbtn,self.row,2) + transbox.setLayout(transgrid) + + #CSS + transbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(transbox) + + #Adding Device Details + + + #Increment row and widget count + self.row = self.row+1 + self.devicemodel_dict_end[words[0]]=self.count + self.count = self.count+1 + + elif eachline[0] == 'd': + print "Device Model Diode:",words[0] + self.devicemodel_dict_beg[words[0]]=self.count + diodebox=QtGui.QGroupBox() + diodegrid=QtGui.QGridLayout() + diodebox.setTitle("Add library for Diode "+words[0]+" : "+words[3]) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + #global path_name + try: + for child in root: + if child.tag[0]==eachline[0] and child.tag[1]==eachline[1]: + #print "DEVICE MODEL MATCHING---",child.tag[0],child.tag[1],eachline[0],eachline[1] + try: + if os.path.exists(child[0].text): + path_name=child[0].text + self.entry_var[self.count].setText(child[0].text) + else: + self.entry_var[self.count].setText("") + except: + print "Error when set text of device model diode" + except: + pass + diodegrid.addWidget(self.entry_var[self.count],self.row,1) + self.addbtn = QtGui.QPushButton("Add") + self.addbtn.setObjectName("%d" %self.count) + self.addbtn.clicked.connect(self.trackLibrary) + self.deviceDetail[self.count] = words[0] + if self.entry_var[self.count].text()=="": + pass + else: + self.trackLibraryWithoutButton(self.count,path_name) + diodegrid.addWidget(self.addbtn,self.row,2) + diodebox.setLayout(diodegrid) + + #CSS + diodebox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(diodebox) + + #Adding Device Details + + + #Increment row and widget count + self.row = self.row+1 + self.devicemodel_dict_end[words[0]]=self.count + self.count = self.count+1 + + elif eachline[0] == 'j': + print "Device Model JFET:",words[0] + self.devicemodel_dict_beg[words[0]]=self.count + jfetbox=QtGui.QGroupBox() + jfetgrid=QtGui.QGridLayout() + jfetbox.setTitle("Add library for JFET "+words[0]+" : "+words[4]) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + #global path_name + try: + for child in root: + if child.tag[0]==eachline[0] and child.tag[1]==eachline[1]: + #print "DEVICE MODEL MATCHING---",child.tag[0],child.tag[1],eachline[0],eachline[1] + try: + if os.path.exists(child[0].text): + self.entry_var[self.count].setText(child[0].text) + path_name=child[0].text + else: + self.entry_var[self.count].setText("") + except: + print "Error when set text of Device Model JFET " + except: + pass + jfetgrid.addWidget(self.entry_var[self.count],self.row,1) + self.addbtn = QtGui.QPushButton("Add") + self.addbtn.setObjectName("%d" %self.count) + self.addbtn.clicked.connect(self.trackLibrary) + self.deviceDetail[self.count] = words[0] + if self.entry_var[self.count].text()=="": + pass + else: + self.trackLibraryWithoutButton(self.count,path_name) + jfetgrid.addWidget(self.addbtn,self.row,2) + jfetbox.setLayout(jfetgrid) + + #CSS + jfetbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(jfetbox) + + #Adding Device Details + + + #Increment row and widget count + self.row = self.row+1 + self.devicemodel_dict_end[words[0]]=self.count + self.count = self.count+1 + + + + elif eachline[0] == 'm': + self.devicemodel_dict_beg[words[0]]=self.count + mosfetbox=QtGui.QGroupBox() + mosfetgrid=QtGui.QGridLayout() + i=self.count + beg=self.count + mosfetbox.setTitle("Add library for MOSFET "+words[0]+" : "+words[5]) + self.entry_var[self.count] =QtGui.QLineEdit() + self.entry_var[self.count].setText("") + mosfetgrid.addWidget(self.entry_var[self.count],self.row,1) + self.addbtn = QtGui.QPushButton("Add") + self.addbtn.setObjectName("%d" %self.count) + self.addbtn.clicked.connect(self.trackLibrary) + mosfetgrid.addWidget(self.addbtn,self.row,2) + + #Adding Device Details + self.deviceDetail[self.count] = words[0] + + #Increment row and widget count + self.row = self.row+1 + self.count = self.count+1 + + #Adding to get MOSFET dimension + self.widthLabel[self.count] = QtGui.QLabel("Enter width of MOSFET "+words[0]+"(default=100u):") + mosfetgrid.addWidget(self.widthLabel[self.count],self.row,0) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + self.entry_var[self.count].setMaximumWidth(150) + mosfetgrid.addWidget(self.entry_var[self.count],self.row,1) + self.row = self.row + 1 + self.count = self.count+1 + + self.lengthLabel[self.count] = QtGui.QLabel("Enter length of MOSFET "+words[0]+"(default=100u):") + mosfetgrid.addWidget(self.lengthLabel[self.count],self.row,0) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + self.entry_var[self.count].setMaximumWidth(150) + mosfetgrid.addWidget(self.entry_var[self.count],self.row,1) + self.row = self.row + 1 + self.count = self.count+1 + + + self.multifactorLable[self.count] = QtGui.QLabel("Enter multiplicative factor of MOSFET "+words[0]+"(default=1):") + mosfetgrid.addWidget(self.multifactorLable[self.count],self.row,0) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + end=self.count + self.entry_var[self.count].setMaximumWidth(150) + mosfetgrid.addWidget(self.entry_var[self.count],self.row,1) + self.row = self.row + 1 + self.devicemodel_dict_end[words[0]]=self.count + self.count = self.count+1 + mosfetbox.setLayout(mosfetgrid) + #global path_name + try: + for child in root: + if child.tag[0]==eachline[0] and child.tag[1]==eachline[1]: + #print "DEVICE MODEL MATCHING---",child.tag[0],child.tag[1],eachline[0],eachline[1] + while i<=end: + self.entry_var[i].setText(child[i-beg].text) + if (i-beg)==0: + if os.path.exists(child[0].text): + self.entry_var[i].setText(child[i-beg].text) + path_name=child[i-beg].text + else: + self.entry_var[i].setText("") + i=i+1 + except: + pass + #CSS + mosfetbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + if self.entry_var[beg].text()=="": + pass + else: + self.trackLibraryWithoutButton(beg,path_name) + self.grid.addWidget(mosfetbox) + + + self.show() + + + def trackLibrary(self): + """ + This function is use to keep track of all Device Model widget + """ + print "Calling Track Device Model Library funtion" + sending_btn = self.sender() + #print "Object Called is ",sending_btn.objectName() + self.widgetObjCount = int(sending_btn.objectName()) + + self.libfile = str(QtGui.QFileDialog.getOpenFileName(self,"Open Library Directory","../deviceModelLibrary","*.lib")) + #print "Selected Library File :",self.libfile + + #Setting Library to Text Edit Line + self.entry_var[self.widgetObjCount].setText(self.libfile) + self.deviceName = self.deviceDetail[self.widgetObjCount] + + #Storing to track it during conversion + + + if self.deviceName[0] == 'm': + width = str(self.entry_var[self.widgetObjCount+1].text()) + length = str(self.entry_var[self.widgetObjCount+2].text()) + multifactor = str(self.entry_var[self.widgetObjCount+3].text()) + if width == "" : width="100u" + if length == "": length="100u" + if multifactor == "": multifactor="1" + + self.obj_trac.deviceModelTrack[self.deviceName] = self.libfile+":"+"W="+width+" L="+length+" M="+multifactor + + else: + self.obj_trac.deviceModelTrack[self.deviceName] = self.libfile + def trackLibraryWithoutButton(self,iter_value,path_value): + """ + This function is use to keep track of all Device Model widget + """ + print "Calling Track Library function Without Button" + #print "Object Called is ",sending_btn.objectName() + self.widgetObjCount = iter_value + print "self.widgetObjCount-----",self.widgetObjCount + self.libfile = path_value + #print "Selected Library File :",self.libfile + + #Setting Library to Text Edit Line + self.entry_var[self.widgetObjCount].setText(self.libfile) + self.deviceName = self.deviceDetail[self.widgetObjCount] + + #Storing to track it during conversion + + + if self.deviceName[0] == 'm': + width = str(self.entry_var[self.widgetObjCount+1].text()) + length = str(self.entry_var[self.widgetObjCount+2].text()) + multifactor = str(self.entry_var[self.widgetObjCount+3].text()) + if width == "" : width="100u" + if length == "": length="100u" + if multifactor == "": multifactor="1" + self.obj_trac.deviceModelTrack[self.deviceName] = self.libfile+":"+"W="+width+" L="+length+" M="+multifactor + else: + self.obj_trac.deviceModelTrack[self.deviceName] = self.libfile + diff --git a/src/kicadtoNgspice/DeviceModel.pyc b/src/kicadtoNgspice/DeviceModel.pyc Binary files differnew file mode 100644 index 00000000..6ac8f337 --- /dev/null +++ b/src/kicadtoNgspice/DeviceModel.pyc diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py new file mode 100644 index 00000000..4215f6f8 --- /dev/null +++ b/src/kicadtoNgspice/KicadtoNgspice.py @@ -0,0 +1,646 @@ +#=============================================================================== +# +# FILE: kicadtoNgspice.py +# +# USAGE: --- +# +# DESCRIPTION: This define all configuration used in Application. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Wednesday 04 March 2015 +# REVISION: --- +#=============================================================================== +import sys +import os +from PyQt4 import QtGui +from Processing import PrcocessNetlist +import Analysis +import Source +import Model +import DeviceModel +import SubcircuitTab +import Convert +import TrackWidget + +from xml.etree import ElementTree as ET + + + +class MainWindow(QtGui.QWidget): + """ + This class create KicadtoNgspice window. + And Call Convert function if convert button is pressed. + The convert function takes all the value entered by user and create a final netlist "*.cir.out". + This final netlist is compatible with NgSpice. + """ + def __init__(self,clarg1,clarg2=None): + QtGui.QWidget.__init__(self) + + print "==================================" + print "Kicad to Ngspice netlist converter " + print "==================================" + global kicadNetlist,schematicInfo + global infoline,optionInfo + self.kicadFile = clarg1 + self.clarg1=clarg1 + self.clarg2=clarg2 + + #Create object of track widget + self.obj_track = TrackWidget.TrackWidget() + + #Clear Dictionary/List item of sub circuit and ngspice model + #Dictionary + self.obj_track.subcircuitList.clear() + self.obj_track.subcircuitTrack.clear() + self.obj_track.model_entry_var.clear() + #List + self.obj_track.modelTrack[:]=[] + + #Object of Processing + obj_proc = PrcocessNetlist() + + # Read the netlist + kicadNetlist = obj_proc.readNetlist(self.kicadFile) + + print "Given Kicad Schematic Netlist Info :",kicadNetlist + + # Construct parameter information + param = obj_proc.readParamInfo(kicadNetlist) + + # Replace parameter with values + netlist,infoline = obj_proc.preprocessNetlist(kicadNetlist,param) + + print "Schematic Info after processing Kicad Netlist: ",netlist + #print "INFOLINE",infoline + + # Separate option and schematic information + optionInfo, schematicInfo = obj_proc.separateNetlistInfo(netlist) + + print "OPTIONINFO in the Netlist",optionInfo + + #List for storing source and its value + global sourcelist, sourcelisttrack + sourcelist=[] + sourcelisttrack=[] + schematicInfo,sourcelist = obj_proc.insertSpecialSourceParam(schematicInfo,sourcelist) + + #List storing model detail + global modelList,outputOption,unknownModelList,multipleModelList,plotText + + modelList = [] + outputOption = [] + plotText = [] + schematicInfo,outputOption,modelList,unknownModelList,multipleModelList,plotText = obj_proc.convertICintoBasicBlocks(schematicInfo,outputOption,modelList,plotText) + + print "Model available in the Schematic :",modelList + + """ + Checking if any unknown model is used in schematic which is not recognized by NgSpice. + Also if the two model of same name is present under modelParamXML directory + """ + if unknownModelList: + print "Unknown Model List is : ",unknownModelList + self.msg = QtGui.QErrorMessage() + self.content = "Your schematic contain unknown model "+', '.join(unknownModelList) + self.msg.showMessage(self.content) + self.msg.setWindowTitle("Unknown Models") + + elif multipleModelList: + self.msg = QtGui.QErrorMessage() + self.mcontent = "Look like you have duplicate model in modelParamXML directory "+', '.join(multipleModelList[0]) + self.msg.showMessage(self.mcontent) + self.msg.setWindowTitle("Multiple Models") + + else: + self.createMainWindow() + + + def createMainWindow(self): + """ + This function create main window of Kicad to Ngspice converter + """ + + self.vbox = QtGui.QVBoxLayout(self) + self.hbox=QtGui.QHBoxLayout(self) + self.hbox.addStretch(1) + self.convertbtn = QtGui.QPushButton("Convert") + self.convertbtn.clicked.connect(self.callConvert) + self.hbox.addWidget(self.convertbtn) + self.vbox.addWidget(self.createcreateConvertWidget()) + self.vbox.addLayout(self.hbox) + + self.setLayout(self.vbox) + self.setWindowTitle("Kicad To NgSpice Converter") + self.show() + + def createcreateConvertWidget(self): + global obj_analysis + self.convertWindow = QtGui.QWidget() + self.analysisTab = QtGui.QScrollArea() + obj_analysis=Analysis.Analysis(self.clarg1) + self.analysisTab.setWidget(obj_analysis) + #self.analysisTabLayout = QtGui.QVBoxLayout(self.analysisTab.widget()) + self.analysisTab.setWidgetResizable(True) + global obj_source + self.sourceTab = QtGui.QScrollArea() + obj_source=Source.Source(sourcelist,sourcelisttrack,self.clarg1) + self.sourceTab.setWidget(obj_source) + #self.sourceTabLayout = QtGui.QVBoxLayout(self.sourceTab.widget()) + self.sourceTab.setWidgetResizable(True) + global obj_model + self.modelTab = QtGui.QScrollArea() + obj_model=Model.Model(schematicInfo,modelList,self.clarg1) + self.modelTab.setWidget(obj_model) + #self.modelTabLayout = QtGui.QVBoxLayout(self.modelTab.widget()) + self.modelTab.setWidgetResizable(True) + global obj_devicemodel + self.deviceModelTab = QtGui.QScrollArea() + obj_devicemodel=DeviceModel.DeviceModel(schematicInfo,self.clarg1) + self.deviceModelTab.setWidget(obj_devicemodel) + self.deviceModelTab.setWidgetResizable(True) + global obj_subcircuitTab + self.subcircuitTab = QtGui.QScrollArea() + obj_subcircuitTab = SubcircuitTab.SubcircuitTab(schematicInfo,self.clarg1) + self.subcircuitTab.setWidget(obj_subcircuitTab) + self.subcircuitTab.setWidgetResizable(True) + + self.tabWidget = QtGui.QTabWidget() + #self.tabWidget.TabShape(QtGui.QTabWidget.Rounded) + self.tabWidget.addTab(self.analysisTab,"Analysis") + self.tabWidget.addTab(self.sourceTab,"Source Details") + self.tabWidget.addTab(self.modelTab,"NgSpice Model") + self.tabWidget.addTab(self.deviceModelTab,"Device Modeling") + self.tabWidget.addTab(self.subcircuitTab,"Subcircuits") + self.mainLayout = QtGui.QVBoxLayout() + self.mainLayout.addWidget(self.tabWidget) + #self.mainLayout.addStretch(1) + self.convertWindow.setLayout(self.mainLayout) + self.convertWindow.show() + + return self.convertWindow + + def callConvert(self): + """ + Calling Convert Class Constructor + """ + global schematicInfo + global analysisoutput + global kicad + store_schematicInfo = list(schematicInfo) + (projpath,filename)=os.path.split(self.kicadFile) + project_name=os.path.basename(projpath) + + check=1 + try: + fr=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + temp_tree=ET.parse(fr) + temp_root=temp_tree.getroot() + except: + check=0 + + + fw=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'w') + if check==0: + attr_parent=ET.Element("KicadtoNgspice") + if check==1: + attr_parent=temp_root + + for child in attr_parent: + if child.tag=="analysis": + attr_parent.remove(child) + + attr_analysis=ET.SubElement(attr_parent,"analysis") + attr_ac=ET.SubElement(attr_analysis,"ac") + if obj_analysis.Lin.isChecked(): + ET.SubElement(attr_ac,"field1",name="Lin").text="true" + ET.SubElement(attr_ac,"field2",name="Dec").text="false" + ET.SubElement(attr_ac,"field3",name="Oct").text="false" + elif obj_analysis.Dec.isChecked(): + ET.SubElement(attr_ac,"field1",name="Lin").text="false" + ET.SubElement(attr_ac,"field2",name="Dec").text="true" + ET.SubElement(attr_ac,"field3",name="Oct").text="false" + if obj_analysis.Oct.isChecked(): + ET.SubElement(attr_ac,"field1",name="Lin").text="false" + ET.SubElement(attr_ac,"field2",name="Dec").text="false" + ET.SubElement(attr_ac,"field3",name="Oct").text="true" + else: + pass + ET.SubElement(attr_ac,"field4",name="Start Frequency").text= str(obj_analysis.ac_entry_var[0].text()) + ET.SubElement(attr_ac,"field5",name="Stop Frequency").text= str(obj_analysis.ac_entry_var[1].text()) + ET.SubElement(attr_ac,"field6",name="No. of points").text= str(obj_analysis.ac_entry_var[2].text()) + ET.SubElement(attr_ac,"field7",name="Start Fre Combo").text= obj_analysis.ac_parameter[0] + ET.SubElement(attr_ac,"field8",name="Stop Fre Combo").text= obj_analysis.ac_parameter[1] + attr_dc=ET.SubElement(attr_analysis,"dc") + ET.SubElement(attr_dc,"field1",name="Source 1").text= str(obj_analysis.dc_entry_var[0].text()) + ET.SubElement(attr_dc,"field2",name="Start").text= str(obj_analysis.dc_entry_var[1].text()) + ET.SubElement(attr_dc,"field3",name="Increment").text= str(obj_analysis.dc_entry_var[2].text()) + ET.SubElement(attr_dc,"field4",name="Stop").text= str(obj_analysis.dc_entry_var[3].text()) + #print "OBJ_ANALYSIS.CHECK -----",self.obj_track.op_check[-1] + ET.SubElement(attr_dc,"field5",name="Operating Point").text=str(self.obj_track.op_check[-1]) + ET.SubElement(attr_dc,"field6",name="Start Combo").text= obj_analysis.dc_parameter[0] + ET.SubElement(attr_dc,"field7",name="Increment Combo").text=obj_analysis.dc_parameter[1] + ET.SubElement(attr_dc,"field8",name="Stop Combo").text= obj_analysis.dc_parameter[2] + ET.SubElement(attr_dc,"field9",name="Source 2").text= str(obj_analysis.dc_entry_var[4].text()) + ET.SubElement(attr_dc,"field10",name="Start").text= str(obj_analysis.dc_entry_var[5].text()) + ET.SubElement(attr_dc,"field11",name="Increment").text= str(obj_analysis.dc_entry_var[6].text()) + ET.SubElement(attr_dc,"field12",name="Stop").text= str(obj_analysis.dc_entry_var[7].text()) + ET.SubElement(attr_dc,"field13",name="Start Combo").text= obj_analysis.dc_parameter[3] + ET.SubElement(attr_dc,"field14",name="Increment Combo").text=obj_analysis.dc_parameter[4] + ET.SubElement(attr_dc,"field15",name="Stop Combo").text= obj_analysis.dc_parameter[5] + + + attr_tran=ET.SubElement(attr_analysis,"tran") + ET.SubElement(attr_tran,"field1",name="Start Time").text= str(obj_analysis.tran_entry_var[0].text()) + ET.SubElement(attr_tran,"field2",name="Step Time").text= str(obj_analysis.tran_entry_var[1].text()) + ET.SubElement(attr_tran,"field3",name="Stop Time").text= str(obj_analysis.tran_entry_var[2].text()) + ET.SubElement(attr_tran,"field4",name="Start Combo").text= obj_analysis.tran_parameter[0] + ET.SubElement(attr_tran,"field5",name="Step Combo").text= obj_analysis.tran_parameter[1] + ET.SubElement(attr_tran,"field6",name="Stop Combo").text= obj_analysis.tran_parameter[2] + #print "TRAN PARAMETER 2-----",obj_analysis.tran_parameter[2] + + if check==0: + attr_source=ET.SubElement(attr_parent,"source") + if check==1: + for child in attr_parent: + if child.tag=="source": + attr_source=child + count=1 + grand_child_count=1 + + for i in store_schematicInfo: + tmp_check=0 + words=i.split(' ') + wordv=words[0] + for child in attr_source: + if child.tag==wordv and child.text==words[len(words)-1]: + tmp_check=1 + for grand_child in child: + grand_child.text=str(obj_source.entry_var[grand_child_count].text()) + grand_child_count=grand_child_count+1 + grand_child_count=grand_child_count+1 + if tmp_check==0: + words=i.split(' ') + wordv=words[0] + if wordv[0]=="v" or wordv[0]=="i": + attr_var=ET.SubElement(attr_source,words[0],name="Source type") + attr_var.text=words[len(words)-1] + #ET.SubElement(attr_ac,"field1",name="Lin").text="true" + if words[len(words)-1]=="ac": + #attr_ac=ET.SubElement(attr_var,"ac") + ET.SubElement(attr_var,"field1",name="Amplitude").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var, "field2", name = "Phase").text = str(obj_source.entry_var[count].text()) + count=count+2 + elif words[len(words)-1]=="dc": + #attr_dc=ET.SubElement(attr_var,"dc") + ET.SubElement(attr_var,"field1",name="Value").text=str(obj_source.entry_var[count].text()) + count=count+2 + elif words[len(words)-1]=="sine": + #attr_sine=ET.SubElement(attr_var,"sine") + ET.SubElement(attr_var,"field1",name="Offset Value").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field2",name="Amplitude").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field3",name="Frequency").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field4",name="Delay Time").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field5",name="Damping Factor").text=str(obj_source.entry_var[count].text()) + count=count+2 + elif words[len(words)-1]=="pulse": + #attr_pulse=ET.SubElement(attr_var,"pulse") + ET.SubElement(attr_var,"field1",name="Initial Value").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field2",name="Pulse Value").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field3",name="Delay Time").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field4",name="Rise Time").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field5",name="Fall Time").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field5",name="Pulse width").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field5",name="Period").text=str(obj_source.entry_var[count].text()) + count=count+2 + elif words[len(words)-1]=="pwl": + #attr_pwl=ET.SubElement(attr_var,"pwl") + ET.SubElement(attr_var,"field1",name="Enter in pwl format").text=str(obj_source.entry_var[count].text()) + count=count+2 + elif words[len(words)-1]=="exp": + #attr_exp=ET.SubElement(attr_var,"exp") + ET.SubElement(attr_var,"field1",name="Initial Value").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field2",name="Pulsed Value").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field3",name="Rise Delay Time").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field4",name="Rise Time Constant").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field5",name="Fall TIme").text=str(obj_source.entry_var[count].text()) + count=count+1 + ET.SubElement(attr_var,"field6",name="Fall Time Constant").text=str(obj_source.entry_var[count].text()) + count=count+2 + else: + pass + + + if check==0: + attr_model=ET.SubElement(attr_parent,"model") + if check==1: + for child in attr_parent: + if child.tag=="model": + attr_model=child + i=0 + #tmp_check is a variable to check for duplicates in the xml file + tmp_check=0 + #tmp_i is the iterator in case duplicates are there; then in that case we need to replace only the child node and not create a new parent node + + for line in modelList: + tmp_check=0 + for rand_itr in obj_model.obj_trac.modelTrack: + if rand_itr[2]==line[2] and rand_itr[3]==line[3]: + start=rand_itr[7] + end=rand_itr[8] + i=start + for child in attr_model: + if child.text==line[2] and child.tag==line[3]: + for grand_child in child: + if i<=end: + grand_child.text=str(obj_model.obj_trac.model_entry_var[i].text()) + i=i+1 + else: + pass + tmp_check=1 + + if tmp_check==0: + attr_ui=ET.SubElement(attr_model,line[3],name="type") + attr_ui.text=line[2] + for key,value in line[7].iteritems(): + if hasattr(value, '__iter__') and i<=end: + for item in value: + ET.SubElement(attr_ui,"field"+str(i+1),name=item).text=str(obj_model.obj_trac.model_entry_var[i].text()) + i=i+1 + + else: + ET.SubElement(attr_ui,"field"+str(i+1),name=value).text=str(obj_model.obj_trac.model_entry_var[i].text()) + + i=i+1 + + if check==0: + attr_devicemodel=ET.SubElement(attr_parent,"devicemodel") + if check==1: + for child in attr_parent: + if child.tag=="devicemodel": + del child[:] + attr_devicemodel=child + + + for i in obj_devicemodel.devicemodel_dict_beg: + attr_var=ET.SubElement(attr_devicemodel,i) + it=obj_devicemodel.devicemodel_dict_beg[i] + end=obj_devicemodel.devicemodel_dict_end[i] + while it<=end: + ET.SubElement(attr_var,"field").text=str(obj_devicemodel.entry_var[it].text()) + it=it+1 + + if check==0: + attr_subcircuit=ET.SubElement(attr_parent,"subcircuit") + if check==1: + for child in attr_parent: + if child.tag=="subcircuit": + del child[:] + attr_subcircuit=child + + for i in obj_subcircuitTab.subcircuit_dict_beg: + attr_var=ET.SubElement(attr_subcircuit,i) + it=obj_subcircuitTab.subcircuit_dict_beg[i] + end=obj_subcircuitTab.subcircuit_dict_end[i] + + while it<=end: + ET.SubElement(attr_var,"field").text=str(obj_subcircuitTab.entry_var[it].text()) + it=it+1 + + + tree=ET.ElementTree(attr_parent) + tree.write(fw) + + + self.obj_convert = Convert.Convert(self.obj_track.sourcelisttrack["ITEMS"], + self.obj_track.source_entry_var["ITEMS"], + store_schematicInfo,self.clarg1) + + try: + #Adding Source Value to Schematic Info + store_schematicInfo = self.obj_convert.addSourceParameter() + print "Netlist After Adding Source details :",store_schematicInfo + + #Adding Model Value to store_schematicInfo + store_schematicInfo = self.obj_convert.addModelParameter(store_schematicInfo) + print "Netlist After Adding Ngspice Model :",store_schematicInfo + + #Adding Device Library to SchematicInfo + store_schematicInfo = self.obj_convert.addDeviceLibrary(store_schematicInfo,self.kicadFile) + print "Netlist After Adding Device Model Library :",store_schematicInfo + + #Adding Subcircuit Library to SchematicInfo + store_schematicInfo = self.obj_convert.addSubcircuit(store_schematicInfo, self.kicadFile) + print "Netlist After Adding subcircuits :",store_schematicInfo + + analysisoutput = self.obj_convert.analysisInsertor(self.obj_track.AC_entry_var["ITEMS"], + self.obj_track.DC_entry_var["ITEMS"], + self.obj_track.TRAN_entry_var["ITEMS"], + self.obj_track.set_CheckBox["ITEMS"], + self.obj_track.AC_Parameter["ITEMS"], + self.obj_track.DC_Parameter["ITEMS"], + self.obj_track.TRAN_Parameter["ITEMS"], + self.obj_track.AC_type["ITEMS"], + self.obj_track.op_check) + + print "Analysis OutPut ",analysisoutput + + #Calling netlist file generation function + self.createNetlistFile(store_schematicInfo,plotText) + + self.msg = "The Kicad to Ngspice Conversion completed successfully!!!!!!" + QtGui.QMessageBox.information(self, "Information", self.msg, QtGui.QMessageBox.Ok) + + except Exception as e: + print "Exception Message: ",e + print "There was error while converting kicad to ngspice" + self.close() + + # Generate .sub file from .cir.out file if it is a subcircuit + subPath = os.path.splitext(self.kicadFile)[0] + + if self.clarg2 == "sub": + self.createSubFile(subPath) + + def createNetlistFile(self,store_schematicInfo,plotText): + print "Creating Final netlist" + #print "INFOLINE",infoline + #print "OPTIONINFO",optionInfo + #print "Device MODEL LIST ",devicemodelList + #print "SUBCKT ",subcktList + #print "OUTPUTOPTION",outputOption + #print "KicadfIle",kicadFile + store_optionInfo = list(optionInfo) #To avoid writing optionInfo twice in final netlist + + #checking if analysis files is present + (projpath,filename) = os.path.split(self.kicadFile) + analysisFileLoc = os.path.join(projpath,"analysis") + #print "Analysis File Location",analysisFileLoc + if os.path.exists(analysisFileLoc): + try: + f = open(analysisFileLoc) + #Read data + data = f.read() + # Close the file + f.close() + + except : + print "Error While opening Project Analysis file. Please check it" + sys.exit() + else: + print analysisFileLoc + " does not exist" + sys.exit() + + #Adding analysis file info to optionInfo + analysisData=data.splitlines() + for eachline in analysisData: + eachline=eachline.strip() + if len(eachline)>1: + if eachline[0]=='.': + store_optionInfo.append(eachline) + else: + pass + + #print "Option Info",optionInfo + analysisOption = [] + initialCondOption=[] + simulatorOption =[] + #includeOption=[] #Don't know why to use it + #model = [] #Don't know why to use it + + for eachline in store_optionInfo: + words=eachline.split() + option=words[0] + if (option=='.ac' or option=='.dc' or option=='.disto' or option=='.noise' or + option=='.op' or option=='.pz' or option=='.sens' or option=='.tf' or + option=='.tran'): + analysisOption.append(eachline+'\n') + + elif (option=='.save' or option=='.print' or option=='.plot' or option=='.four'): + eachline=eachline.strip('.') + outputOption.append(eachline+'\n') + elif (option=='.nodeset' or option=='.ic'): + initialCondOption.append(eachline+'\n') + elif option=='.option': + simulatorOption.append(eachline+'\n') + #elif (option=='.include' or option=='.lib'): + # includeOption.append(eachline+'\n') + #elif (option=='.model'): + # model.append(eachline+'\n') + elif option=='.end': + continue; + + + #Start creating final netlist cir.out file + outfile = self.kicadFile+".out" + out=open(outfile,"w") + out.writelines(infoline) + out.writelines('\n') + sections=[simulatorOption, initialCondOption, store_schematicInfo, analysisOption] + + for section in sections: + if len(section) == 0: + continue + else: + for line in section: + out.writelines('\n') + out.writelines(line) + + out.writelines('\n* Control Statements \n') + out.writelines('.control\n') + out.writelines('run\n') + #out.writelines(outputOption) + out.writelines('print allv > plot_data_v.txt\n') + out.writelines('print alli > plot_data_i.txt\n') + for item in plotText: + out.writelines(item+'\n') + out.writelines('.endc\n') + out.writelines('.end\n') + out.close() + + + + def createSubFile(self,subPath): + self.project = subPath + self.projName = os.path.basename(self.project) + if os.path.exists(self.project+".cir.out"): + try: + f = open(self.project+".cir.out") + except : + print("Error in opening .cir.out file.") + else: + print self.projName + ".cir.out does not exist. Please create a spice netlist." + + # Read the data from file + data=f.read() + # Close the file + + f.close() + newNetlist=[] + netlist=iter(data.splitlines()) + for eachline in netlist: + eachline=eachline.strip() + if len(eachline)<1: + continue + words=eachline.split() + if eachline[2] == 'u': + if words[len(words)-1] == "port": + subcktInfo = ".subckt "+self.projName+" " + for i in range(2,len(words)-1): + subcktInfo+=words[i]+" " + continue + if words[0] == ".end" or words[0] == ".ac" or words[0] == ".dc" or words[0] == ".tran" or words[0] == '.disto' or words[0] == '.noise' or words[0] == '.op' or words[0] == '.pz' or words[0] == '.sens' or words[0] == '.tf': + continue + elif words[0] == ".control": + while words[0] != ".endc": + eachline=netlist.next() + eachline=eachline.strip() + if len(eachline)<1: + continue + words=eachline.split() + else: + newNetlist.append(eachline) + + outfile=self.project+".sub" + out=open(outfile,"w") + out.writelines("* Subcircuit " + self.projName) + out.writelines('\n') + out.writelines(subcktInfo) + out.writelines('\n') + + for i in range(len(newNetlist),0,-1): + newNetlist.insert(i,'\n') + + out.writelines(newNetlist) + out.writelines('\n') + + out.writelines('.ends ' + self.projName) + print "The subcircuit has been written in "+self.projName+".sub" + + + + + + + + +
\ No newline at end of file diff --git a/src/kicadtoNgspice/KicadtoNgspice.pyc b/src/kicadtoNgspice/KicadtoNgspice.pyc Binary files differnew file mode 100644 index 00000000..ecfae361 --- /dev/null +++ b/src/kicadtoNgspice/KicadtoNgspice.pyc diff --git a/src/kicadtoNgspice/Model.py b/src/kicadtoNgspice/Model.py new file mode 100644 index 00000000..25a23d8c --- /dev/null +++ b/src/kicadtoNgspice/Model.py @@ -0,0 +1,140 @@ + +from PyQt4 import QtGui + +import TrackWidget +from xml.etree import ElementTree as ET +import os + + +class Model(QtGui.QWidget): + """ + This class creates Model Tab of KicadtoNgspice window. + The widgets are created dynamically in the Model Tab. + """ + + def __init__(self,schematicInfo,modelList,clarg1): + + QtGui.QWidget.__init__(self) + + #Processing for getting previous values + kicadFile = clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="model": + root=child + except: + check=0 + print "Model Previous Values XML is Empty" + + + + #Creating track widget object + self.obj_trac = TrackWidget.TrackWidget() + + #for increasing row and counting/tracking line edit widget + self.nextrow = 0 + self.nextcount = 0 + + #for storing line edit details position details + self.start = 0 + self.end = 0 + + #Creating GUI dynamically for Model tab + self.grid = QtGui.QGridLayout() + self.setLayout(self.grid) + + for line in modelList: + #print "ModelList Item:",line + #Adding title label for model + #Key: Tag name,Value:Entry widget number + tag_dict = {} + modelbox=QtGui.QGroupBox() + modelgrid=QtGui.QGridLayout() + modelbox.setTitle(line[5]) + self.start=self.nextcount + #line[7] is parameter dictionary holding parameter tags. + i=0 + for key,value in line[7].iteritems(): + #print "Key : ",key + #print "Value : ",value + #Check if value is iterable + if hasattr(value, '__iter__'): + #For tag having vector value + temp_tag = [] + for item in value: + paramLabel = QtGui.QLabel(item) + modelgrid.addWidget(paramLabel,self.nextrow,0) + self.obj_trac.model_entry_var[self.nextcount]= QtGui.QLineEdit() + modelgrid.addWidget(self.obj_trac.model_entry_var[self.nextcount],self.nextrow,1) + try: + for child in root: + if child.text==line[2] and child.tag==line[3]: + self.obj_trac.model_entry_var[self.nextcount].setText(child[i].text) + i=i+1 + except: + pass + temp_tag.append(self.nextcount) + self.nextcount = self.nextcount+1 + self.nextrow = self.nextrow+1 + tag_dict[key] = temp_tag + else: + paramLabel = QtGui.QLabel(value) + modelgrid.addWidget(paramLabel,self.nextrow,0) + self.obj_trac.model_entry_var[self.nextcount]= QtGui.QLineEdit() + modelgrid.addWidget(self.obj_trac.model_entry_var[self.nextcount],self.nextrow,1) + try: + for child in root: + if child.text==line[2] and child.tag==line[3]: + self.obj_trac.model_entry_var[self.nextcount].setText(child[i].text) + i=i+1 + except: + pass + tag_dict[key] = self.nextcount + self.nextcount = self.nextcount+1 + self.nextrow = self.nextrow+1 + self.end= self.nextcount-1 + #print "End",self.end + modelbox.setLayout(modelgrid) + + #CSS + modelbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(modelbox) + + ''' + Listing all + line[0] = index + line[1] = compLine + line[2] = modelname #Change from compType to modelname + line[3] = compName + line[4] = comment + line[5] = title + line[6] = type i.e analog or digital + Now adding start,end and tag_dict which will be line[7],line[8] and line[9] respectively + ''' + + #This keeps the track of Model Tab Widget + lst=[line[0],line[1],line[2],line[3],line[4],line[5],line[6],self.start,self.end,tag_dict] + check=0 + for itr in self.obj_trac.modelTrack: + if itr==lst: + check=1 + + if check==0: + self.obj_trac.modelTrack.append(lst) + + #print "The tag dictionary : ",tag_dict + + + + self.show() + diff --git a/src/kicadtoNgspice/Model.pyc b/src/kicadtoNgspice/Model.pyc Binary files differnew file mode 100644 index 00000000..0d93058f --- /dev/null +++ b/src/kicadtoNgspice/Model.pyc diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py new file mode 100644 index 00000000..09544f19 --- /dev/null +++ b/src/kicadtoNgspice/Processing.py @@ -0,0 +1,380 @@ +import sys +import os +from xml.etree import ElementTree as ET + + + +class PrcocessNetlist: + """ + This class include all the function required for pre-proccessing of netlist + before converting to Ngspice Netlist. + """ + modelxmlDIR = '../modelParamXML' + def __init__(self): + pass + + def readNetlist(self,filename): + f = open(filename) + data=f.read() + f.close() + return data.splitlines() + + def readParamInfo(self,kicadNetlis): + """Read Parameter information and store it into dictionary""" + param={} + for eachline in kicadNetlis: + print eachline + eachline=eachline.strip() + if len(eachline)>1: + words=eachline.split() + option=words[0].lower() + if option=='.param': + for i in range(1, len(words), 1): + paramList=words[i].split('=') + param[paramList[0]]=paramList[1] + return param + + def preprocessNetlist(self,kicadNetlis,param): + """Preprocess netlist (replace parameters)""" + netlist=[] + for eachline in kicadNetlis: + # Remove leading and trailing blanks spaces from line + eachline=eachline.strip() + # Remove special character $ + eachline=eachline.replace('$','') + # Replace parameter with values + for subParam in eachline.split(): + if '}' in subParam: + key=subParam.split()[0] + key=key.strip('{') + key=key.strip('}') + if key in param: + eachline=eachline.replace('{'+key+'}',param[key]) + else: + print "Parameter " + key +" does not exists" + value=raw_input('Enter parameter value: ') + eachline=eachline.replace('{'+key+'}',value) + #Convert netlist into lower case letter + eachline=eachline.lower() + # Construct netlist + if len(eachline)>1: + if eachline[0]=='+': + netlist.append(netlist.pop()+eachline.replace('+',' ')) + else: + netlist.append(eachline) + #Copy information line + infoline=netlist[0] + netlist.remove(netlist[0]) + return netlist,infoline + + def separateNetlistInfo(self,netlist): + optionInfo=[] + schematicInfo=[] + for eachline in netlist: + if eachline[0]=='*': + continue + elif eachline[0]=='.': + optionInfo.append(eachline) + else: + schematicInfo.append(eachline) + return optionInfo,schematicInfo + + + def insertSpecialSourceParam(self,schematicInfo,sourcelist): + #Inser Special source parameter + schematicInfo1=[] + + print "Reading schematic info for source details" + + for compline in schematicInfo: + words=compline.split() + compName=words[0] + # Ask for parameters of source + if compName[0]=='v' or compName[0]=='i': + # Find the index component from circuit + index=schematicInfo.index(compline) + if words[3]=="pulse": + Title="Add parameters for pulse source "+compName + v1=' Enter initial value(Volts/Amps): ' + v2=' Enter pulsed value(Volts/Amps): ' + td=' Enter delay time (seconds): ' + tr=' Enter rise time (seconds): ' + tf=' Enter fall time (seconds): ' + pw=' Enter pulse width (seconds): ' + tp=' Enter period (seconds): ' + sourcelist.append([index,compline,words[3],Title,v1,v2,td,tr,tf,pw,tp]) + + elif words[3]=="sine": + Title="Add parameters for sine source "+compName + vo=' Enter offset value (Volts/Amps): ' + va=' Enter amplitude (Volts/Amps): ' + freq=' Enter frequency (Hz): ' + td=' Enter delay time (seconds): ' + theta=' Enter damping factor (1/seconds): ' + sourcelist.append([index,compline,words[3],Title,vo,va,freq,td,theta]) + + elif words[3]=="pwl": + Title="Add parameters for pwl source "+compName + t_v=' Enter in pwl format without bracket i.e t1 v1 t2 v2.... ' + sourcelist.append([index,compline,words[3],Title,t_v]) + + elif words[3]=="ac": + Title="Add parameters for ac source "+compName + v_a=' Enter amplitude (Volts/Amps): ' + p_a =' Enter Phase Shift: ' + sourcelist.append([index,compline,words[3],Title,v_a,p_a]) + + elif words[3]=="exp": + Title="Add parameters for exponential source "+compName + v1=' Enter initial value(Volts/Amps): ' + v2=' Enter pulsed value(Volts/Amps): ' + td1=' Enter rise delay time (seconds): ' + tau1=' Enter rise time constant (seconds): ' + td2=' Enter fall time (seconds): ' + tau2=' Enter fall time constant (seconds): ' + sourcelist.append([index,compline,words[3],Title,v1,v2,td1,tau1,td2,tau2]) + + elif words[3]=="dc": + Title="Add parameters for DC source "+compName + v1=' Enter value(Volts/Amps): ' + v2=' Enter zero frequency: ' + sourcelist.append([index,compline,words[3],Title,v1,v2]) + + elif compName[0]=='h' or compName[0]=='f': + # Find the index component from the circuit + index=schematicInfo.index(compline) + schematicInfo.remove(compline) + schematicInfo.insert(index,"* "+compName) + schematicInfo1.append("V"+compName+" "+words[3]+" "+words[4]+" 0") + schematicInfo1.append(compName+" "+words[1]+" "+words[2]+" "+"V"+compName+" "+words[5]) + + schematicInfo=schematicInfo+schematicInfo1 + print "Source List : ",sourcelist + #print schematicInfo + return schematicInfo,sourcelist + + + def convertICintoBasicBlocks(self,schematicInfo,outputOption,modelList,plotText): + print "Reading Schematic info for Model" + #Insert details of Ngspice model + unknownModelList = [] + multipleModelList = [] + plotList = ['plot_v1','plot_v2','plot_i2','plot_log','plot_db','plot_phase'] + interMediateNodeCount=1 + k = 1 + for compline in schematicInfo: + words = compline.split() + compName = words[0] + #print "Compline----------------->",compline + #print "compName-------------->",compName + # Find the IC from schematic + if compName[0]=='u' or compName[0] == 'U': + # Find the component from the circuit + index=schematicInfo.index(compline) + compType=words[len(words)-1]; + schematicInfo.remove(compline) + paramDict = {} + #e.g compLine : u1 1 2 gain + #compType : gain + #compName : u1 + #print "Compline",compline + #print "CompType",compType + #print "Words",words + #print "compName",compName + #Looking if model file is present + if compType != "port" and compType != "ic" and compType not in plotList and compType != 'transfo': + xmlfile = compType+".xml" #XML Model File + count = 0 #Check if model of same name is present + modelPath = [] + all_dir = [x[0] for x in os.walk(PrcocessNetlist.modelxmlDIR)] + for each_dir in all_dir: + all_file = os.listdir(each_dir) + if xmlfile in all_file: + count += 1 + modelPath.append(os.path.join(each_dir,xmlfile)) + + if count > 1: + multipleModelList.append(modelPath) + elif count == 0: + unknownModelList.append(compType) + elif count == 1: + try: + print "Start Parsing Previous Values XML for ngspice model :",modelPath + tree = ET.parse(modelPath[0]) + + root = tree.getroot() + #Getting number of nodes for model and title + for child in tree.iter(): + if child.tag == 'node_number': + num_of_nodes = int(child.text) + elif child.tag == 'title': + title = child.text+" "+compName + elif child.tag == 'name': + modelname = child.text + elif child.tag == 'type': + #Checking for Analog and Digital + type = child.text + elif child.tag == 'split': + splitDetail = child.text + + + for param in tree.findall('param'): + for item in param: + #print "Tags ",item.tag + #print "Value",item.text + if 'vector'in item.attrib: + #print "Tag having vector attribute",item.tag,item.attrib['vector'] + temp_count = 1 + temp_list = [] + for i in range(0,int(item.attrib['vector'])): + temp_list.append(item.text+" "+str(temp_count)) + temp_count += 1 + if 'default' in item.attrib: + paramDict[item.tag+":"+item.attrib['default']] = temp_list + else: + paramDict[item.tag] = item.text + + else: + if 'default' in item.attrib: + paramDict[item.tag+":"+item.attrib['default']] = item.text + else: + paramDict[item.tag] = item.text + + + #print "Number of Nodes : ",num_of_nodes + #print "Title : ",title + #print "Parameters",paramDict + #Creating line for adding model line in schematic + if splitDetail == 'None': + modelLine = "a"+str(k)+" " + for i in range(1,num_of_nodes+1): + modelLine += words[i]+" " + modelLine += compName + + else: + print "Split Details :",splitDetail + modelLine = "a"+str(k)+" " + vectorDetail = splitDetail.split(':') + #print "Vector Details",vectorDetail + pos = 1 #Node position + for item in vectorDetail: + try: + if item.split("-")[1] == 'V': + #print "Vector" + if compType == "aswitch": + modelLine += "(" + for i in range(0,int(item.split("-")[0])): + modelLine += words[pos]+" " + pos += 1 + modelLine += ") " + else: + modelLine += "[" + for i in range(0,int(item.split("-")[0])): + modelLine += words[pos]+" " + pos += 1 + modelLine += "] " + elif item.split("-")[1] == 'NV': + #print "Non Vector" + for i in range(0,int(item.split("-")[0])): + modelLine += words[pos]+" " + pos += 1 + + except: + print "There is error while processing Vector Details" + sys.exit(2) + modelLine += compName + + #print "Final Model Line :",modelLine + try: + schematicInfo.append(modelLine) + k=k+1 + except Exception as e: + print "Error while appending ModelLine ",modelLine + print "Exception Message : ",str(e) + #Insert comment at remove line + schematicInfo.insert(index,"* "+compline) + comment = "* Schematic Name: "+compType+", NgSpice Name: "+modelname + #Here instead of adding compType(use for XML), added modelName(Unique Model Name) + modelList.append([index,compline,modelname,compName,comment,title,type,paramDict]) + except Exception as e: + print "Unable to parse the model, Please check your your XML file" + print "Exception Message : ",str(e) + sys.exit(2) + elif compType == "ic": + schematicInfo.insert(index,"* "+compline) + modelname = "ic" + comment = "* "+compline + title = "Initial Condition for "+compName + type = "NA" #Its is not model + text = "Enter initial voltage at node for "+compline + paramDict[title] = text + modelList.append([index,compline,modelname,compName,comment,title,type,paramDict]) + + elif compType in plotList: + schematicInfo.insert(index,"* "+compline) + if compType == 'plot_v1': + words = compline.split() + plotText.append("plot v("+words[1]+")") + elif compType == 'plot_v2': + words = compline.split() + plotText.append("plot v("+words[1]+","+words[2]+")") + elif compType == 'plot_i2': + words = compline.split() + #Adding zero voltage source to netlist + schematicInfo.append("v_"+words[0]+" "+words[1]+" "+words[2]+" "+"0") + plotText.append("plot i(v_"+words[0]+")") + elif compType == 'plot_log': + words = compline.split() + plotText.append("plot log("+words[1]+")") + elif compType == 'plot_db': + words = compline.split() + plotText.append("plot db("+words[1]+")") + elif compType == 'plot_phase': + words = compline.split() + plotText.append("plot phase("+words[1]+")") + + elif compType == 'transfo': + schematicInfo.insert(index,"* "+compline) + + #For Primary Couple + modelLine = "a"+str(k)+" ("+words[1]+" "+words[2]+") (interNode_"+str(interMediateNodeCount)+" "+words[3]+") " + modelLine += compName+"_primary" + schematicInfo.append(modelLine) + k=k+1 + #For iron core + modelLine = "a"+str(k)+" ("+words[4]+" "+words[2]+") (interNode_"+str(interMediateNodeCount+1)+" "+words[3]+") " + modelLine += compName+"_secondary" + schematicInfo.append(modelLine) + k=k+1 + #For Secondary Couple + modelLine = "a"+str(k)+" (interNode_"+str(interMediateNodeCount)+" interNode_"+str(interMediateNodeCount+1)+") " + modelLine += compName+"_iron_core" + schematicInfo.append(modelLine) + k=k+1 + interMediateNodeCount += 2 + + modelname = "transfo" + comment = "* "+compline + title = "Transformer details for model "+compName + type = "NA" #It is model but do not load from xml and lib file + paramDict['h1_array'] = "Enter the H1 array " + paramDict['primary_turns'] = "Enter the primary number of turns (default=310) " + paramDict['area'] = "Enter iron core area (default=1)" + paramDict['secondar_turns'] = "Enter the secondary number of turns (default=620)" + paramDict['length'] = "Enter iron core length (default=0.01)" + paramDict['b1_array'] = "Enter the B1 array " + + + modelList.append([index,compline,modelname,compName,comment,title,type,paramDict]) + + else: + schematicInfo.insert(index,"* "+compline) + + print "UnknownModelList Used in the Schematic",unknownModelList + print "Multiple Model XML file with same name ",multipleModelList + print "Model List Details : ",modelList + + return schematicInfo,outputOption,modelList,unknownModelList,multipleModelList,plotText + + + diff --git a/src/kicadtoNgspice/Processing.pyc b/src/kicadtoNgspice/Processing.pyc Binary files differnew file mode 100644 index 00000000..92c86492 --- /dev/null +++ b/src/kicadtoNgspice/Processing.pyc diff --git a/src/kicadtoNgspice/Source.py b/src/kicadtoNgspice/Source.py new file mode 100644 index 00000000..1cf1487d --- /dev/null +++ b/src/kicadtoNgspice/Source.py @@ -0,0 +1,305 @@ +import os +from PyQt4 import QtGui +import TrackWidget +from xml.etree import ElementTree as ET + +class Source(QtGui.QWidget): + """ + This class create Source Tab of KicadtoNgSpice Window. + """ + + def __init__(self,sourcelist,sourcelisttrack,clarg1): + QtGui.QWidget.__init__(self) + self.obj_track = TrackWidget.TrackWidget() + #Variable + self.count = 1 + self.clarg1=clarg1 + self.start = 0 + self.end = 0 + self.row = 0 + self.entry_var = {} + #self.font = QtGui.QFont("Times",20,QtGui.QFont.Bold,True) + + #Creating Source Widget + self.createSourceWidget(sourcelist,sourcelisttrack) + + + + def createSourceWidget(self,sourcelist,sourcelisttrack): + """ + This function dynamically create source widget in the Source tab of KicadtoNgSpice window + """ + kicadFile = self.clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="source": + root=child + except: + check=0 + print "Source Previous Values XML is Empty" + + self.grid = QtGui.QGridLayout() + self.setLayout(self.grid) + xml_num=0 + + if sourcelist: + for line in sourcelist: + #print "Voltage source line index: ",line[0] + print "SourceList line: ",line + track_id=line[0] + #print "track_id is ",track_id + if line[2]=='ac': + acbox=QtGui.QGroupBox() + acbox.setTitle(line[3]) + acgrid=QtGui.QGridLayout() + self.start=self.count + label1=QtGui.QLabel(line[4]) + label2 = QtGui.QLabel(line[5]) + acgrid.addWidget(label1,self.row,0) + acgrid.addWidget(label2, self.row+1, 0) + self.entry_var[self.count]=QtGui.QLineEdit() + self.entry_var[self.count].setMaximumWidth(150) + acgrid.addWidget(self.entry_var[self.count],self.row,1) + self.entry_var[self.count+1]=QtGui.QLineEdit() + self.entry_var[self.count+1].setMaximumWidth(150) + acgrid.addWidget(self.entry_var[self.count+1],self.row+1,1) + self.entry_var[self.count].setText("") + self.entry_var[self.count+1].setText("") + try: + for child in root: + templist1=line[1] + templist2=templist1.split(' ') + + if child.tag==templist2[0] and child.text==line[2]: + self.entry_var[self.count].setText(child[0].text) + self.entry_var[self.count+1].setText(child[1].text) + except: + pass + #Value Need to check previuouse value + #self.entry_var[self.count].setText("") + self.row=self.row+1 + self.end=self.count+1 + self.count=self.count+1 + acbox.setLayout(acgrid) + + #CSS + acbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(acbox) + sourcelisttrack.append([track_id,'ac',self.start,self.end]) + + + elif line[2]=='dc': + dcbox=QtGui.QGroupBox() + dcbox.setTitle(line[3]) + dcgrid=QtGui.QGridLayout() + self.row=self.row+1 + self.start=self.count + label=QtGui.QLabel(line[4]) + dcgrid.addWidget(label,self.row,0) + self.entry_var[self.count]=QtGui.QLineEdit() + self.entry_var[self.count].setMaximumWidth(150) + dcgrid.addWidget(self.entry_var[self.count],self.row,1) + self.entry_var[self.count].setText("") + try: + for child in root: + templist1=line[1] + templist2=templist1.split(' ') + + if child.tag==templist2[0] and child.text==line[2]: + self.entry_var[self.count].setText(child[0].text) + except: + pass + + self.row=self.row+1 + self.end=self.count + self.count=self.count+1 + dcbox.setLayout(dcgrid) + + #CSS + dcbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(dcbox) + sourcelisttrack.append([track_id,'dc',self.start,self.end]) + + elif line[2]=='sine': + sinebox=QtGui.QGroupBox() + sinebox.setTitle(line[3]) + sinegrid=QtGui.QGridLayout() + self.row=self.row+1 + self.start=self.count + + for it in range(4,9): + label=QtGui.QLabel(line[it]) + sinegrid.addWidget(label,self.row,0) + self.entry_var[self.count]=QtGui.QLineEdit() + self.entry_var[self.count].setMaximumWidth(150) + sinegrid.addWidget(self.entry_var[self.count],self.row,1) + self.entry_var[self.count].setText("") + try: + for child in root: + templist1=line[1] + templist2=templist1.split(' ') + if child.tag==templist2[0] and child.text==line[2]: + self.entry_var[self.count].setText(child[it-4].text) + except: + pass + + + self.row=self.row+1 + self.count=self.count+1 + self.end=self.count-1 + sinebox.setLayout(sinegrid) + + #CSS + sinebox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(sinebox) + sourcelisttrack.append([track_id,'sine',self.start,self.end]) + + elif line[2]=='pulse': + pulsebox=QtGui.QGroupBox() + pulsebox.setTitle(line[3]) + pulsegrid=QtGui.QGridLayout() + self.start=self.count + for it in range(4,11): + label=QtGui.QLabel(line[it]) + pulsegrid.addWidget(label,self.row,0) + self.entry_var[self.count]=QtGui.QLineEdit() + self.entry_var[self.count].setMaximumWidth(150) + pulsegrid.addWidget(self.entry_var[self.count],self.row,1) + self.entry_var[self.count].setText("") + + try: + for child in root: + templist1=line[1] + templist2=templist1.split(' ') + if child.tag==templist2[0] and child.text==line[2]: + self.entry_var[self.count].setText(child[it-4].text) + except: + pass + + + self.row=self.row+1 + self.count=self.count+1 + self.end=self.count-1 + pulsebox.setLayout(pulsegrid) + + #CSS + pulsebox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(pulsebox) + sourcelisttrack.append([track_id,'pulse',self.start,self.end]) + + elif line[2]=='pwl': + pwlbox=QtGui.QGroupBox() + pwlbox.setTitle(line[3]) + self.start=self.count + pwlgrid=QtGui.QGridLayout() + self.start=self.count + label=QtGui.QLabel(line[4]) + pwlgrid.addWidget(label,self.row,0) + self.entry_var[self.count]=QtGui.QLineEdit() + self.entry_var[self.count].setMaximumWidth(150) + pwlgrid.addWidget(self.entry_var[self.count],self.row,1) + self.entry_var[self.count].setText("") + + try: + for child in root: + templist1=line[1] + templist2=templist1.split(' ') + if child.tag==templist2[0] and child.text==line[2]: + self.entry_var[self.count].setText(child[0].text) + except: + pass + + + self.row=self.row+1 + self.end=self.count + self.count=self.count+1 + pwlbox.setLayout(pwlgrid) + + #CSS + pwlbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(pwlbox) + sourcelisttrack.append([track_id,'pwl',self.start,self.end]) + + elif line[2]=='exp': + expbox=QtGui.QGroupBox() + expbox.setTitle(line[3]) + expgrid=QtGui.QGridLayout() + self.start=self.count + for it in range(4,10): + label=QtGui.QLabel(line[it]) + expgrid.addWidget(label,self.row,0) + self.entry_var[self.count]=QtGui.QLineEdit() + self.entry_var[self.count].setMaximumWidth(150) + expgrid.addWidget(self.entry_var[self.count],self.row,1) + self.entry_var[self.count].setText("") + + try: + for child in root: + templist1=line[1] + templist2=templist1.split(' ') + if child.tag==templist2[0] and child.text==line[2]: + self.entry_var[self.count].setText(child[it-4].text) + except: + pass + + + self.row=self.row+1 + self.count=self.count+1 + self.end=self.count-1 + expbox.setLayout(expgrid) + + #CSS + expbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(expbox) + sourcelisttrack.append([track_id,'exp',self.start,self.end]) + + + self.count=self.count+1 + xml_num=xml_num+1 + + + else: + print "No source is present in your circuit" + + + #This is used to keep the track of dynamically created widget + self.obj_track.sourcelisttrack["ITEMS"] = sourcelisttrack + self.obj_track.source_entry_var["ITEMS"] = self.entry_var + self.show() + + + + + + + diff --git a/src/kicadtoNgspice/Source.pyc b/src/kicadtoNgspice/Source.pyc Binary files differnew file mode 100644 index 00000000..fe03449f --- /dev/null +++ b/src/kicadtoNgspice/Source.pyc diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py new file mode 100644 index 00000000..e7a9ed66 --- /dev/null +++ b/src/kicadtoNgspice/SubcircuitTab.py @@ -0,0 +1,170 @@ +from PyQt4 import QtGui + +import TrackWidget +from projManagement import Validation +import os +from xml.etree import ElementTree as ET + +class SubcircuitTab(QtGui.QWidget): + """ + This class creates Subcircuit Tab in KicadtoNgspice Window + It dynamically creates the widget for subcircuits. + """ + + def __init__(self,schematicInfo,clarg1): + kicadFile = clarg1 + (projpath,filename)=os.path.split(kicadFile) + project_name=os.path.basename(projpath) + check=1 + try: + f=open(os.path.join(projpath,project_name+"_Previous_Values.xml"),'r') + tree=ET.parse(f) + parent_root=tree.getroot() + for child in parent_root: + if child.tag=="subcircuit": + root=child + except: + check=0 + print "Subcircuit Previous values XML is Empty" + + QtGui.QWidget.__init__(self) + + #Creating track widget object + self.obj_trac = TrackWidget.TrackWidget() + + #Creating validation object + self.obj_validation = Validation.Validation() + #Row and column count + self.row = 0 + self.count = 1 #Entry count + self.entry_var = {} + self.subcircuit_dict_beg={} + self.subcircuit_dict_end={} + #List to hold information about subcircuit + self.subDetail = {} + + #Stores the number of ports in each subcircuit + self.numPorts = [] + + #Set Layout + self.grid = QtGui.QGridLayout() + self.setLayout(self.grid) + + for eachline in schematicInfo: + words = eachline.split() + if eachline[0] == 'x': + print "Subcircuit : Words",words[0] + self.obj_trac.subcircuitList[project_name+words[0]]=words + self.subcircuit_dict_beg[words[0]]=self.count + subbox=QtGui.QGroupBox() + subgrid=QtGui.QGridLayout() + subbox.setTitle("Add subcircuit for "+words[len(words)-1]) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + + global path_name + try: + for child in root: + if child.tag[0]==eachline[0] and child.tag[1]==eachline[1]: + print "Subcircuit MATCHING---",child.tag[0],child.tag[1],eachline[0],eachline[1] + try: + if os.path.exists(child[0].text): + self.entry_var[self.count].setText(child[0].text) + path_name=child[0].text + else: + self.entry_var[self.count].setText("") + except: + print "Error when set text of subcircuit" + except: + print "Error before subcircuit" + + + subgrid.addWidget(self.entry_var[self.count],self.row,1) + self.addbtn = QtGui.QPushButton("Add") + self.addbtn.setObjectName("%d" %self.count) + #Send the number of ports specified with the given subcircuit for verification. + #eg. If the line is 'x1 4 0 3 ua741', there are 3 ports(4, 0 and 3). + self.numPorts.append(len(words)-2) + print "Number of ports of sub circuit : ",self.numPorts + self.addbtn.clicked.connect(self.trackSubcircuit) + subgrid.addWidget(self.addbtn,self.row,2) + subbox.setLayout(subgrid) + + #CSS + subbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(subbox) + + #Adding Subcircuit Details + self.subDetail[self.count] = words[0] + + #Increment row and widget count + + if self.entry_var[self.count].text()=="": + pass + else: + self.trackSubcircuitWithoutButton(self.count,path_name) + + self.subcircuit_dict_end[words[0]]=self.count + self.row = self.row+1 + self.count = self.count+1 + + self.show() + + + def trackSubcircuit(self): + """ + This function is use to keep track of all Subcircuit widget + """ + sending_btn = self.sender() + #print "Object Called is ",sending_btn.objectName() + self.widgetObjCount = int(sending_btn.objectName()) + + self.subfile = str(QtGui.QFileDialog.getExistingDirectory(self,"Open Subcircuit","../SubcircuitLibrary")) + self.reply = self.obj_validation.validateSub(self.subfile,self.numPorts[self.widgetObjCount - 1]) + if self.reply == "True": + #Setting Library to Text Edit Line + self.entry_var[self.widgetObjCount].setText(self.subfile) + self.subName = self.subDetail[self.widgetObjCount] + + #Storing to track it during conversion + + self.obj_trac.subcircuitTrack[self.subName] = self.subfile + elif self.reply == "PORT": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("Please select a Subcircuit with correct number of ports.") + self.msg.setWindowTitle("Error Message") + self.msg.show() + elif self.reply == "DIREC": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("Please select a valid Subcircuit directory (Containing '.sub' file).") + self.msg.setWindowTitle("Error Message") + self.msg.show() + + def trackSubcircuitWithoutButton(self,iter_value,path_value): + + self.widgetObjCount = iter_value + + self.subfile = path_value + self.reply = self.obj_validation.validateSub(self.subfile,self.numPorts[self.widgetObjCount - 1]) + if self.reply == "True": + #Setting Library to Text Edit Line + self.entry_var[self.widgetObjCount].setText(self.subfile) + self.subName = self.subDetail[self.widgetObjCount] + + #Storing to track it during conversion + + self.obj_trac.subcircuitTrack[self.subName] = self.subfile + elif self.reply == "PORT": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("Please select a Subcircuit with correct number of ports.") + self.msg.setWindowTitle("Error Message") + self.msg.show() + elif self.reply == "DIREC": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("Please select a valid Subcircuit directory (Containing '.sub' file).") + self.msg.setWindowTitle("Error Message") + self.msg.show()
\ No newline at end of file diff --git a/src/kicadtoNgspice/SubcircuitTab.pyc b/src/kicadtoNgspice/SubcircuitTab.pyc Binary files differnew file mode 100644 index 00000000..23f27032 --- /dev/null +++ b/src/kicadtoNgspice/SubcircuitTab.pyc diff --git a/src/kicadtoNgspice/TrackWidget.py b/src/kicadtoNgspice/TrackWidget.py new file mode 100644 index 00000000..56e84ce3 --- /dev/null +++ b/src/kicadtoNgspice/TrackWidget.py @@ -0,0 +1,29 @@ +class TrackWidget: + """ + This Class track the dynamically created widget of KicadtoNgSpice Window. + """ + #Track widget list for Source details + sourcelisttrack = {"ITEMS":"None"} + source_entry_var = {"ITEMS":"None"} + + #Track widget for analysis inserter details + AC_entry_var = {"ITEMS":"None"} + AC_Parameter = {"ITEMS":"None"} + DC_entry_var = {"ITEMS":"None"} + DC_Parameter = {"ITEMS":"None"} + TRAN_entry_var = {"ITEMS":"None"} + TRAN_Parameter = {"ITEMS":"None"} + set_CheckBox = {"ITEMS":"None"} + AC_type = {"ITEMS":"None"} + op_check = [] + #Track widget for Model detail + modelTrack = [] + model_entry_var = {} + + #Track Widget for Device Model detail + deviceModelTrack = {} + + #Track Widget for Subcircuits where directory has been selected + subcircuitTrack = {} + #Track subcircuits which are specified in .cir file + subcircuitList = {}
\ No newline at end of file diff --git a/src/kicadtoNgspice/TrackWidget.pyc b/src/kicadtoNgspice/TrackWidget.pyc Binary files differnew file mode 100644 index 00000000..40e0d68a --- /dev/null +++ b/src/kicadtoNgspice/TrackWidget.pyc diff --git a/src/kicadtoNgspice/__init__.py b/src/kicadtoNgspice/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/kicadtoNgspice/__init__.py diff --git a/src/kicadtoNgspice/__init__.pyc b/src/kicadtoNgspice/__init__.pyc Binary files differnew file mode 100644 index 00000000..a4a908e0 --- /dev/null +++ b/src/kicadtoNgspice/__init__.pyc diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py new file mode 100644 index 00000000..9ad7c662 --- /dev/null +++ b/src/modelEditor/ModelEditor.py @@ -0,0 +1,552 @@ +from PyQt4 import QtGui, QtCore +from PyQt4.Qt import QTableWidgetItem +import xml.etree.ElementTree as ET +from configuration.Appconfig import Appconfig +import os + + +class ModelEditorclass(QtGui.QWidget): + def __init__(self): + QtGui.QWidget.__init__(self) + self.savepathtest = '../deviceModelLibrary' + self.obj_appconfig = Appconfig() + self.newflag=0 + self.layout = QtGui.QVBoxLayout() + self.splitter= QtGui.QSplitter() + self.grid= QtGui.QGridLayout() + self.splitter.setOrientation(QtCore.Qt.Vertical) + + self.modeltable = QtGui.QTableWidget() + + self.newbtn = QtGui.QPushButton('New') + self.newbtn.setToolTip('<b>Creating new Model Library</b>') + self.newbtn.clicked.connect(self.opennew) + self.editbtn = QtGui.QPushButton('Edit') + self.editbtn.setToolTip('<b>Editing current Model Library</b>') + self.editbtn.clicked.connect(self.openedit) + self.savebtn = QtGui.QPushButton('Save') + self.savebtn.setToolTip('<b>Saves the Model Library</b>') + self.savebtn.setDisabled(True) + self.savebtn.clicked.connect(self.savemodelfile) + self.removebtn = QtGui.QPushButton('Remove') + self.removebtn.setHidden(True) + self.removebtn.clicked.connect(self.removeparameter) + self.addbtn = QtGui.QPushButton('Add') + self.addbtn.setHidden(True) + self.addbtn.clicked.connect(self.addparameters) + self.uploadbtn = QtGui.QPushButton('Upload') + self.uploadbtn.setToolTip('<b>Uploading external .lib file to eSim</b>') + self.uploadbtn.clicked.connect(self.converttoxml) + self.grid.addWidget(self.newbtn, 1,2) + self.grid.addWidget(self.editbtn, 1,3) + self.grid.addWidget(self.savebtn, 1,4) + self.grid.addWidget(self.uploadbtn, 1,5) + self.grid.addWidget(self.removebtn, 8,4) + self.grid.addWidget(self.addbtn, 5,4) + + self.radiobtnbox = QtGui.QButtonGroup() + self.diode = QtGui.QRadioButton('Diode') + self.diode.setDisabled(True) + self.bjt = QtGui.QRadioButton('BJT') + self.bjt.setDisabled(True) + self.mos = QtGui.QRadioButton('MOS') + self.mos.setDisabled(True) + self.jfet = QtGui.QRadioButton('JFET') + self.jfet.setDisabled(True) + self.igbt = QtGui.QRadioButton('IGBT') + self.igbt.setDisabled(True) + self.magnetic = QtGui.QRadioButton('Magnetic Core') + self.magnetic.setDisabled(True) + + self.radiobtnbox.addButton(self.diode) + self.diode.clicked.connect(self.diode_click) + self.radiobtnbox.addButton(self.bjt) + self.bjt.clicked.connect(self.bjt_click) + self.radiobtnbox.addButton(self.mos) + self.mos.clicked.connect(self.mos_click) + self.radiobtnbox.addButton(self.jfet) + self.jfet.clicked.connect(self.jfet_click) + self.radiobtnbox.addButton(self.igbt) + self.igbt.clicked.connect(self.igbt_click) + self.radiobtnbox.addButton(self.magnetic) + self.magnetic.clicked.connect(self.magnetic_click) + + self.types= QtGui.QComboBox() + self.types.setHidden(True) + + self.grid.addWidget(self.types,2,2,2,3) + self.grid.addWidget(self.diode, 3,1) + self.grid.addWidget(self.bjt,4,1) + self.grid.addWidget(self.mos,5,1) + self.grid.addWidget(self.jfet,6,1) + self.grid.addWidget(self.igbt,7,1) + self.grid.addWidget(self.magnetic,8,1) + self.setLayout(self.grid) + self.show() + + '''To create New Model file ''' + def opennew(self): + self.addbtn.setHidden(True) + try: + self.removebtn.setHidden(True) + self.modeltable.setHidden(True) + except: + pass + os.chdir(self.savepathtest) + text, ok = QtGui.QInputDialog.getText(self, 'New Model','Enter Model Name:') + if ok: + self.newflag=1 + self.diode.setDisabled(False) + self.bjt.setDisabled(False) + self.mos.setDisabled(False) + self.jfet.setDisabled(False) + self.igbt.setDisabled(False) + self.magnetic.setDisabled(False) + self.modelname = (str(text)) + else: + pass + + self.validation(text) + + def diode_click(self): + self.openfiletype('Diode') + self.types.setHidden(True) + + def bjt_click(self): + self.types.setHidden(False) + self.types.clear() + self.types.addItem('NPN') + self.types.addItem('PNP') + filetype = str(self.types.currentText()) + self.openfiletype(filetype) + self.types.activated[str].connect(self.setfiletype) + + def mos_click(self): + self.types.setHidden(False) + self.types.clear() + self.types.addItem('NMOS(Level-1 5um)') + self.types.addItem('NMOS(Level-3 0.5um)') + self.types.addItem('NMOS(Level-8 180um)') + self.types.addItem('PMOS(Level-1 5um)') + self.types.addItem('PMOS(Level-3 0.5um)') + self.types.addItem('PMOS(Level-8 180um)') + filetype = str(self.types.currentText()) + self.openfiletype(filetype) + self.types.activated[str].connect(self.setfiletype) + + def jfet_click(self): + self.types.setHidden(False) + self.types.clear() + self.types.addItem('N-JFET') + self.types.addItem('P-JFET') + filetype = str(self.types.currentText()) + self.openfiletype(filetype) + self.types.activated[str].connect(self.setfiletype) + + def igbt_click(self): + self.types.setHidden(False) + self.types.clear() + self.types.addItem('N-IGBT') + self.types.addItem('P-IGBT') + filetype = str(self.types.currentText()) + self.openfiletype(filetype) + self.types.activated[str].connect(self.setfiletype) + + def magnetic_click(self): + self.openfiletype('Magnetic Core') + self.types.setHidden(True) + + def setfiletype(self,text): + self.filetype = str(text) + self.openfiletype(self.filetype) + + def openfiletype(self,filetype): + ''' + Select the path of the file to be opened depending upon selected file type + ''' + self.path = '../deviceModelLibrary/Templates' + if self.diode.isChecked(): + if filetype == 'Diode': + path = os.path.join(self.path,'D.xml') + self.createtable(path) + if self.bjt.isChecked(): + if filetype == 'NPN': + path = os.path.join(self.path,'NPN.xml') + self.createtable(path) + elif filetype == 'PNP': + path = os.path.join(self.path, 'PNP.xml') + self.createtable(path) + if self.mos.isChecked(): + if filetype == 'NMOS(Level-1 5um)': + path = os.path.join(self.path, 'NMOS-5um.xml') + self.createtable(path) + elif filetype == 'NMOS(Level-3 0.5um)': + path = os.path.join(self.path, 'NMOS-0.5um.xml') + self.createtable(path) + elif filetype == 'NMOS(Level-8 180um)': + path = os.path.join(self.path, 'NMOS-180nm.xml') + self.createtable(path) + elif filetype == 'PMOS(Level-1 5um)': + path = os.path.join(self.path, 'PMOS-5um.xml') + self.createtable(path) + elif filetype == 'PMOS(Level-3 0.5um)': + path = os.path.join(self.path, 'PMOS-0.5um.xml') + self.createtable(path) + elif filetype == 'PMOS(Level-8 180um)': + path = os.path.join(self.path, 'PMOS-180nm.xml') + self.createtable(path) + if self.jfet.isChecked(): + if filetype == 'N-JFET': + path = os.path.join(self.path, 'NJF.xml') + self.createtable(path) + elif filetype == 'P-JFET': + path = os.path.join(self.path, 'PJF.xml') + self.createtable(path) + if self.igbt.isChecked(): + if filetype == 'N-IGBT': + path = os.path.join(self.path, 'NIGBT.xml') + self.createtable(path) + elif filetype == 'P-IGBT': + path = os.path.join(self.path, 'PIGBT.xml') + self.createtable(path) + if self.magnetic.isChecked(): + if filetype == 'Magnetic Core': + path = os.path.join(self.path, 'CORE.xml') + self.createtable(path) + else : + pass + + def openedit(self): + os.chdir(self.savepathtest) + self.newflag=0 + self.addbtn.setHidden(True) + self.types.setHidden(True) + self.diode.setDisabled(True) + self.mos.setDisabled(True) + self.jfet.setDisabled(True) + self.igbt.setDisabled(True) + self.bjt.setDisabled(True) + self.magnetic.setDisabled(True) + try: + self.editfile=str(QtGui.QFileDialog.getOpenFileName(self,"Open Library Directory","../deviceModelLibrary","*.lib")) + self.createtable(self.editfile) + except: + print"No File selected for edit" + pass + + def createtable(self, modelfile): + ''' + This function Creates the model table by parsing the .xml file + ''' + self.savebtn.setDisabled(False) + self.addbtn.setHidden(False) + self.removebtn.setHidden(False) + self.modelfile = modelfile + self.modeldict = {} + self.modeltable = QtGui.QTableWidget() + self.modeltable.resizeColumnsToContents() + self.modeltable.setColumnCount(2) + self.modeltable.resizeRowsToContents() + self.modeltable.resize(200,200) + self.grid.addWidget(self.modeltable, 3,2,8,2) + filepath, filename = os.path.split(self.modelfile) + base, ext= os.path.splitext(filename) + self.modelfile = os.path.join(filepath, base+'.xml') + print"Model File used for creating table : ",self.modelfile + self.tree = ET.parse(self.modelfile) + self.root= self.tree.getroot() + for elem in self.tree.iter(tag='ref_model'): + self.ref_model = elem.text + for elem in self.tree.iter(tag='model_name'): + self.model_name = elem.text + row=0 + for params in self.tree.findall('param'): + for paramlist in params: + self.modeldict[paramlist.tag]= paramlist.text + row= row+1 + self.modeltable.setRowCount(row) + count =0 + for tags, values in self.modeldict.items(): + self.modeltable.setItem(count,0, QTableWidgetItem(tags)) + try: + valueitem = QTableWidgetItem(values) + except: + pass + self.modeltable.setItem(count,1, valueitem) + count= count +1 + self.modeltable.setHorizontalHeaderLabels(QtCore.QString("Parameters;Values").split(";")) + self.modeltable.show() + self.modeltable.itemChanged.connect(self.edit_modeltable) + + def edit_modeltable(self): + self.savebtn.setDisabled(False) + try: + indexitem = self.modeltable.currentItem() + name = str(indexitem.data(0).toString()) + rowno = indexitem.row() + para = self.modeltable.item(rowno,0) + val = str(para.data(0).toString()) + self.modeldict[val]= name + except: + pass + + + def addparameters(self): + ''' + This function is used to add new parameter in the table + ''' + text1, ok = QtGui.QInputDialog.getText(self, 'Parameter','Enter Parameter') + if ok: + if text1 in self.modeldict.keys(): + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("The paramaeter " + text1 + " is already in the list") + self.msg.setWindowTitle("Error Message") + return + text2, ok = QtGui.QInputDialog.getText(self, 'Value','Enter Value') + if ok : + currentRowCount = self.modeltable.rowCount() + self.modeltable.insertRow(currentRowCount) + self.modeltable.setItem(currentRowCount, 0, QTableWidgetItem(text1)) + self.modeltable.setItem(currentRowCount, 1, QTableWidgetItem(text2)) + self.modeldict[str(text1)]= str(text2) + else: + pass + else: + pass + + + def savemodelfile(self): + if self.newflag== 1: + self.createXML(self.model_name) + else: + self.savethefile(self.editfile) + + + def createXML(self,model_name): + ''' + This function creates .xml and .lib files from the model table + ''' + root = ET.Element("library") + ET.SubElement(root, "model_name").text = model_name + ET.SubElement(root, "ref_model").text = self.modelname + param = ET.SubElement(root, "param") + for tags, text in self.modeldict.items(): + ET.SubElement(param, tags).text = text + tree = ET.ElementTree(root) + defaultcwd = os.getcwd() + self.savepath = '../deviceModelLibrary' + if self.diode.isChecked(): + savepath = os.path.join(self.savepath, 'Diode') + os.chdir(savepath) + txtfile = open(self.modelname+'.lib', 'w') + txtfile.write('.MODEL ' + self.modelname +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + txtfile.write('+ ' + tags + '=' + text +'\n') + txtfile.write(')') + tree.write(self.modelname +".xml") + self.obj_appconfig.print_info('New ' + self.modelname + ' ' + self.model_name + ' library created at ' + os.getcwd()) + if self.mos.isChecked(): + savepath = os.path.join(self.savepath, 'MOS') + os.chdir(savepath) + txtfile = open(self.modelname+'.lib', 'w') + txtfile.write('.MODEL ' + self.modelname +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + txtfile.write('+ ' + tags + '=' + text +'\n') + txtfile.write(')') + tree.write(self.modelname +".xml") + self.obj_appconfig.print_info('New ' + self.modelname + ' ' + self.model_name + ' library created at ' + os.getcwd()) + if self.jfet.isChecked(): + savepath = os.path.join(self.savepath, 'JFET') + os.chdir(savepath) + txtfile = open(self.modelname+'.lib', 'w') + txtfile.write('.MODEL ' + self.modelname +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + txtfile.write('+ ' + tags + '=' + text +'\n') + txtfile.write(')') + tree.write(self.modelname +".xml") + self.obj_appconfig.print_info('New ' + self.modelname + ' ' + self.model_name + ' library created at ' + os.getcwd()) + if self.igbt.isChecked(): + savepath = os.path.join(self.savepath, 'IGBT') + os.chdir(savepath) + txtfile = open(self.modelname+'.lib', 'w') + txtfile.write('.MODEL ' + self.modelname +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + txtfile.write('+ ' + tags + '=' + text +'\n') + txtfile.write(')') + tree.write(self.modelname +".xml") + self.obj_appconfig.print_info('New ' + self.modelname + ' ' + self.model_name + ' library created at ' + os.getcwd()) + if self.magnetic.isChecked(): + savepath = os.path.join(self.savepath, 'Misc') + os.chdir(savepath) + txtfile = open(self.modelname+'.lib', 'w') + txtfile.write('.MODEL ' + self.modelname +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + txtfile.write('+ ' + tags + '=' + text +'\n') + txtfile.write(')') + tree.write(self.modelname +".xml") + self.obj_appconfig.print_info('New ' + self.modelname + ' ' + self.model_name + ' library created at ' + os.getcwd()) + if self.bjt.isChecked(): + savepath = os.path.join(self.savepath, 'Transistor') + os.chdir(savepath) + txtfile = open(self.modelname+'.lib', 'w') + txtfile.write('.MODEL ' + self.modelname +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + txtfile.write('+ ' + tags + '=' + text +'\n') + txtfile.write(')') + tree.write(self.modelname +".xml") + self.obj_appconfig.print_info('New ' + self.modelname + ' ' + self.model_name + ' library created at ' + os.getcwd()) + txtfile.close() + os.chdir(defaultcwd) + + + def validation(self,text): + ''' + This function checks if the file with the name already exists + ''' + newfilename = text+'.xml' + + all_dir = [x[0] for x in os.walk(self.savepathtest)] + for each_dir in all_dir: + all_files = os.listdir(each_dir) + if newfilename in all_files: + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The file with name ' + text+ ' already exists.') + self.msg.setWindowTitle("Error Message") + + + def savethefile(self,editfile): + ''' + This function save the editing in the model table + ''' + xmlpath, file = os.path.split(editfile) + filename = os.path.splitext(file)[0] + libpath = os.path.join(xmlpath,filename+'.lib') + libfile = open(libpath, 'w') + libfile.write('.MODEL ' + self.ref_model +' ' + self.model_name + '(\n' ) + for tags, text in self.modeldict.items(): + libfile.write('+ ' + tags + '=' + text +'\n') + libfile.write(')') + libfile.close() + + root = ET.Element("library") + ET.SubElement(root, "model_name").text = self.model_name + ET.SubElement(root, "ref_model").text = self.ref_model + param = ET.SubElement(root, "param") + for tags, text in self.modeldict.items(): + ET.SubElement(param, tags).text = text + tree = ET.ElementTree(root) + + tree.write(os.path.join(xmlpath,filename +".xml")) + + self.obj_appconfig.print_info('Updated library ' + libpath) + + def removeparameter(self): + self.savebtn.setDisabled(False) + index = self.modeltable.currentIndex() + param = index.data().toString() + remove_item = self.modeltable.item(index.row(),0).text() + self.modeltable.removeRow(index.row()) + del self.modeldict[str(remove_item)] + + def converttoxml(self): + os.chdir(self.savepathtest) + self.addbtn.setHidden(True) + self.removebtn.setHidden(True) + self.modeltable.setHidden(True) + model_dict = {} + stringof = [] + self.libfile = str(QtGui.QFileDialog.getOpenFileName(self,"Open Library Directory","../deviceModelLibrary","*.lib")) + libopen = open(self.libfile) + filedata = libopen.read().split() + modelcount=0 + for words in filedata: + modelcount= modelcount +1 + if words.lower() == '.model': + break + ref_model = filedata[modelcount] + model_name = filedata[modelcount+1] + model_name = list(model_name) + modelnamecnt= 0 + flag= 0 + for chars in model_name: + modelnamecnt = modelnamecnt +1 + if chars == '(': + flag = 1 + break + if flag == 1 : + model_name = ''.join(model_name[0:modelnamecnt-1]) + else: + model_name = ''.join(model_name) + + libopen1 = open(self.libfile) + while True: + char = libopen1.read(1) + if not char: + break + stringof.append(char) + + count = 0 + for chars in stringof: + count = count +1 + if chars == '(': + break + count1=0 + for chars in stringof: + count1 = count1 +1 + if chars == ')': + break + stringof = stringof[count:count1-1] + stopcount=[] + listofname = [] + stopcount.append(0) + count = 0 + for chars in stringof: + count = count +1 + if chars == '=': + stopcount.append(count) + stopcount.append(count) + + i = 0 + for no in stopcount: + try: + listofname.append(''.join(stringof[int(stopcount[i]):int(stopcount[i+1])])) + i = i +1 + except: + pass + listoflist =[] + listofname2 = [el.replace('\t', '').replace('\n', ' ').replace('+', '').replace(')', '').replace('=', '') for el in listofname] + listofname=[] + for item in listofname2: + listofname.append(item.rstrip().lstrip()) + for values in listofname: + valuelist = values.split(' ') + listoflist.append(valuelist) + for i in range(1, len(listoflist)): + model_dict[listoflist[0][0]]=listoflist[1][0] + try: + model_dict[listoflist[i][-1]]= listoflist[i+1][0] + except: + pass + root = ET.Element("library") + ET.SubElement(root, "model_name").text = model_name + ET.SubElement(root, "ref_model").text = ref_model + param = ET.SubElement(root, "param") + for tags, text in model_dict.items(): + ET.SubElement(param, tags).text = text + tree = ET.ElementTree(root) + + defaultcwd = os.getcwd() + savepath = os.path.join(self.savepathtest, 'User Libraries') + savefilepath= os.path.join(savepath, model_name +".xml") + os.chdir(savepath) + text, ok1 = QtGui.QInputDialog.getText(self, 'Model Name','Enter Model Library Name') + if ok1: + tree.write(text+".xml") + fileopen = open(text+".lib",'w') + f = open(self.libfile) + fileopen.write(f.read()) + f.close() + fileopen.close() + os.chdir(defaultcwd) + libopen.close() + libopen1.close()
\ No newline at end of file diff --git a/src/modelEditor/ModelEditor.pyc b/src/modelEditor/ModelEditor.pyc Binary files differnew file mode 100644 index 00000000..878e8a25 --- /dev/null +++ b/src/modelEditor/ModelEditor.pyc diff --git a/src/modelEditor/__init__.py b/src/modelEditor/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/modelEditor/__init__.py diff --git a/src/modelEditor/__init__.pyc b/src/modelEditor/__init__.pyc Binary files differnew file mode 100644 index 00000000..901c2016 --- /dev/null +++ b/src/modelEditor/__init__.pyc diff --git a/src/modelParamXML/Analog/aswitch.xml b/src/modelParamXML/Analog/aswitch.xml new file mode 100644 index 00000000..fe50ecd3 --- /dev/null +++ b/src/modelParamXML/Analog/aswitch.xml @@ -0,0 +1,14 @@ +<model> +<name>aswitch</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Analog Switch</title> +<split>1-NV:2-V</split> +<param> + <cntl_off default="0.0">Enter Control OFF value (default=0.0)</cntl_off> + <cntl_on default="1.0">Enter Control ON value(default=1.0)</cntl_on> + <r_off default="1.0e12">Enter OFF Resistance (default=1.0e12)</r_off> + <r_on default="1.0">Enter ON Resistance (default=1.0)</r_on> + <log default="TRUE">Enter Log (default=TRUE)</log> +</param> +</model> diff --git a/src/modelParamXML/Analog/climit.xml b/src/modelParamXML/Analog/climit.xml new file mode 100644 index 00000000..0d1f9c7e --- /dev/null +++ b/src/modelParamXML/Analog/climit.xml @@ -0,0 +1,15 @@ +<model> +<name>climit</name> +<type>Analog</type> +<node_number>4</node_number> +<title>Add Parameters for Controlled Limiter</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <upper_delta default="0.0">Enter Output Upper Delta (default=0.0)</upper_delta> + <lower_delta default="0.0">Enter Output Lower Delta (default=0.0)</lower_delta> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> + <fraction default="false">Enter Fraction (default=false)</fraction> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Analog/d_dt.xml b/src/modelParamXML/Analog/d_dt.xml new file mode 100644 index 00000000..65494392 --- /dev/null +++ b/src/modelParamXML/Analog/d_dt.xml @@ -0,0 +1,14 @@ +<model> +<name>d_dt</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Differentiator</title> +<split>None</split> +<param> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <out_offset default="0.0">Enter offset for Output (default=0.0)</out_offset> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> +</param> +</model> diff --git a/src/modelParamXML/Analog/divide.xml b/src/modelParamXML/Analog/divide.xml new file mode 100644 index 00000000..d501ae4e --- /dev/null +++ b/src/modelParamXML/Analog/divide.xml @@ -0,0 +1,18 @@ +<model> +<name>divide</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Multiplier</title> +<split>None</split> +<param> + <num_offset default="0.0">Enter offset for Numerator (default=0.0)</num_offset> + <num_gain default="1.0">Enter gain for Numerator (default=1.0)</num_gain> + <den_offset default="0.0">Enter offset for Denominator (default=0.0)</den_offset> + <den_gain default="1.0">Enter gain for Denominator (default=1.0)</den_gain> + <den_lower_limit default="1.0e-10">Enter Denominator Lower Limit (default=1.0e-10)</den_lower_limit> + <den_domain default="1.0e-10">Enter Denominator Domain (default=1.0e-10)</den_domain> + <fraction default="false">Enter Fraction (default=false)</fraction> + <out_gain default="1.0">Enter gain for output (default=1.0)</out_gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model> diff --git a/src/modelParamXML/Analog/gain.xml b/src/modelParamXML/Analog/gain.xml new file mode 100644 index 00000000..ff71d46a --- /dev/null +++ b/src/modelParamXML/Analog/gain.xml @@ -0,0 +1,12 @@ +<model> +<name>gain</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for model Gain</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for input (default=0.0)</in_offset> + <gain vector="2" default="1.0">Enter gain (default=1.0)</gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Analog/hyst.xml b/src/modelParamXML/Analog/hyst.xml new file mode 100644 index 00000000..56a60c0f --- /dev/null +++ b/src/modelParamXML/Analog/hyst.xml @@ -0,0 +1,16 @@ +<model> +<name>hyst</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Hysteresis</title> +<split>None</split> +<param> + <in_low default="0.0">Enter Input Low Value (default=0.0)</in_low> + <in_high default="1.0">Enter Input High Value (default=1.0)</in_high> + <hyst default="0.1">Enter Hysteresis (default=0.1)</hyst> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <input_domain default="0.01">Enter Input Domain Value (default=0.01)</input_domain> + <fraction default="TRUE">Enter Fraction (default=TRUE)</fraction> +</param> +</model> diff --git a/src/modelParamXML/Analog/ilimit.xml b/src/modelParamXML/Analog/ilimit.xml new file mode 100644 index 00000000..32b2149f --- /dev/null +++ b/src/modelParamXML/Analog/ilimit.xml @@ -0,0 +1,19 @@ +<model> +<name>ilimit</name> +<type>Analog</type> +<node_number>4</node_number> +<title>Add Parameters for Current Limiter </title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <r_out_source default="1.0">Enter value for Sourcing Resistance (default=1.0)</r_out_source> + <r_out_sink default="1.0">Enter value for Sinking Resistance (default=1.0)</r_out_sink> + <i_limit_source default="1.0e-12">Enter Current Sourcing Limit (default=1.0e-12)</i_limit_source> + <i_limit_sink default="1.0e-12">Enter Current Sinking Limit (default=1.0e-12)</i_limit_sink> + <v_pwr_range default="1.0e-6">Enter Power Supply Range (default=1.0e-6)</v_pwr_range> + <i_source_range default="1.0e-9">Enter Current Sourcing Range (default=1.0e-9)</i_source_range> + <i_sink_range default="1.0e-9">Enter Current Sinking Range (default=1.0e-9)</i_sink_range> + <r_out_domain default="1.0e-9">Enter Voltage Delta Range (default=1.0e-9)</r_out_domain> +</param> +</model> diff --git a/src/modelParamXML/Analog/int.xml b/src/modelParamXML/Analog/int.xml new file mode 100644 index 00000000..6ccec625 --- /dev/null +++ b/src/modelParamXML/Analog/int.xml @@ -0,0 +1,15 @@ +<model> +<name>int</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for int</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> + <out_ic default="0.0">Enter Output Initial Condition (default=0.0)</out_ic> +</param> +</model> diff --git a/src/modelParamXML/Analog/limit.xml b/src/modelParamXML/Analog/limit.xml new file mode 100644 index 00000000..c2a1f382 --- /dev/null +++ b/src/modelParamXML/Analog/limit.xml @@ -0,0 +1,15 @@ +<model> +<name>limit</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Limiter</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for Input (default=0.0)</in_offset> + <gain default="1.0">Enter value for Gain (default=1.0)</gain> + <out_lower_limit default="0.0">Enter Output Lower Limit (default=0.0)</out_lower_limit> + <out_upper_limit default="1.0">Enter Output Upper Limit (default=1.0)</out_upper_limit> + <limit_range default="1.0e-6">Enter Limit Range (default=1.0e-6)</limit_range> + <fraction default="false">Enter Fraction (default=false)</fraction> +</param> +</model> diff --git a/src/modelParamXML/Analog/mult.xml b/src/modelParamXML/Analog/mult.xml new file mode 100644 index 00000000..e41463ff --- /dev/null +++ b/src/modelParamXML/Analog/mult.xml @@ -0,0 +1,13 @@ +<model> +<name>mult</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Multiplier</title> +<split>2-V:1-NV</split> +<param> + <in_offset vector="2" default="0.0">Enter offset for input (default=0.0)</in_offset> + <in_gain vector="2" default="1.0">Enter gain for input(default=1.0)</in_gain> + <out_gain default="1.0">Enter gain for output (default=1.0)</out_gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model> diff --git a/src/modelParamXML/Analog/slew.xml b/src/modelParamXML/Analog/slew.xml new file mode 100644 index 00000000..2eafde2d --- /dev/null +++ b/src/modelParamXML/Analog/slew.xml @@ -0,0 +1,12 @@ +<model> +<name>slew</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for slew</title> +<split>None</split> +<param> + <rise_slope default="1.0e9">Enter Rising Slope Value (default=1.0e9)</rise_slope> + <fall_slop default="1.0e9">Enter Falling Slope Value (default=1.0e9)</fall_slop> + <range default="0.1">Enter Range (default=0.1)</range> +</param> +</model> diff --git a/src/modelParamXML/Analog/summer.xml b/src/modelParamXML/Analog/summer.xml new file mode 100644 index 00000000..d9856b62 --- /dev/null +++ b/src/modelParamXML/Analog/summer.xml @@ -0,0 +1,13 @@ +<model> +<name>summer</name> +<type>Analog</type> +<node_number>3</node_number> +<title>Add Parameters for Summer</title> +<split>2-V:1-NV</split> +<param> + <in_offset vector="2" default="0.0">Enter offset for input (default=0.0)</in_offset> + <in_gain vector="2" default="1.0">Enter gain for input(default=1.0)</in_gain> + <out_gain default="1.0">Enter gain for output (default=1.0)</out_gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model> diff --git a/src/modelParamXML/Analog/temp.xml b/src/modelParamXML/Analog/temp.xml new file mode 100644 index 00000000..20f00004 --- /dev/null +++ b/src/modelParamXML/Analog/temp.xml @@ -0,0 +1,12 @@ +<model> +<name>gain</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameter for model gain</title> +<split>None</split> +<param> + <in_offset default="0.0">Enter offset for input (default=0.0)</in_offset> + <gain vector="2" default="1.0">Enter gain (default=1.0)</gain> + <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Analog/zener.xml b/src/modelParamXML/Analog/zener.xml new file mode 100644 index 00000000..c6e32c36 --- /dev/null +++ b/src/modelParamXML/Analog/zener.xml @@ -0,0 +1,14 @@ +<model> +<name>zener</name> +<type>Analog</type> +<node_number>2</node_number> +<title>Add Parameters for Zener Diode</title> +<split>None</split> +<param> + <v_breakdown default="5.6">Enter Breakdown Voltage (default=5.6)</v_breakdown> + <i_breakdown default="2.0e-2">Enter Breakdown Current (default=2.0e-2)</i_breakdown> + <i_sat default="1.0e-12">Enter Saturation Current (default=1.0e-12)</i_sat> + <n_forward default="1.0">Enter Forward Emission Coefficient (default=1.0)</n_forward> + <limit_switch default="FALSE">Enter Switch for Limiting (default=FALSE)</limit_switch> +</param> +</model> diff --git a/src/modelParamXML/Digital/d_and.xml b/src/modelParamXML/Digital/d_and.xml new file mode 100644 index 00000000..cd4a1c76 --- /dev/null +++ b/src/modelParamXML/Digital/d_and.xml @@ -0,0 +1,12 @@ +<model> +<name>d_and</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for And Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_buffer.xml b/src/modelParamXML/Digital/d_buffer.xml new file mode 100644 index 00000000..e0661910 --- /dev/null +++ b/src/modelParamXML/Digital/d_buffer.xml @@ -0,0 +1,12 @@ +<model> +<name>d_buffer</name> +<type>Digital</type> +<node_number>2</node_number> +<title>Add Parameters for Buffer</title> +<split>None</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_dff.xml b/src/modelParamXML/Digital/d_dff.xml new file mode 100644 index 00000000..d5010e02 --- /dev/null +++ b/src/modelParamXML/Digital/d_dff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_dff</name> +<type>Digital</type> +<node_number>6</node_number> +<title>Add Parameters for D Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_dlatch.xml b/src/modelParamXML/Digital/d_dlatch.xml new file mode 100644 index 00000000..34e26418 --- /dev/null +++ b/src/modelParamXML/Digital/d_dlatch.xml @@ -0,0 +1,20 @@ +<model> +<name>d_dlatch</name> +<type>Digital</type> +<node_number>6</node_number> +<title>Add Parameters for D Latch</title> +<split>None</split> +<param> + <data_delay default ="1.0e-9">Enter Data Delay (default=1.0e-9)</data_delay> + <enable_delay default ="1.0e-9">Enter Enable Delay (default=1.0e-9)</enable_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load> + <enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_fdiv.xml b/src/modelParamXML/Digital/d_fdiv.xml new file mode 100644 index 00000000..bab4f0d6 --- /dev/null +++ b/src/modelParamXML/Digital/d_fdiv.xml @@ -0,0 +1,15 @@ +<model> +<name>d_fdiv</name> +<type>Digital</type> +<node_number>2</node_number> +<title>Add Parameters for Frequency Divider</title> +<split>None</split> +<param> + <div_factor default ="2">Enter Divide Factor (default=2)</div_factor> + <high_cycles default ="1">Enter value for High Cycles (default=1)</high_cycles> + <i_count default = "0">Enter Initial Count (default=0)</i_count> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <freq_in_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</freq_in_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_inverter.xml b/src/modelParamXML/Digital/d_inverter.xml new file mode 100644 index 00000000..e104712a --- /dev/null +++ b/src/modelParamXML/Digital/d_inverter.xml @@ -0,0 +1,12 @@ +<model> +<name>d_inverter</name> +<type>Digital</type> +<node_number>2</node_number> +<title>Add Parameters for Inverter</title> +<split>None</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_jkff.xml b/src/modelParamXML/Digital/d_jkff.xml new file mode 100644 index 00000000..78ce59cd --- /dev/null +++ b/src/modelParamXML/Digital/d_jkff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_jkff</name> +<type>Digital</type> +<node_number>7</node_number> +<title>Add Parameters for JK Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <jk_load default ="1.0e-12">Enter value for JK Load (default=1.0e-12)</jk_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_nand.xml b/src/modelParamXML/Digital/d_nand.xml new file mode 100644 index 00000000..0041419a --- /dev/null +++ b/src/modelParamXML/Digital/d_nand.xml @@ -0,0 +1,12 @@ +<model> +<name>d_nand</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Nand Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_nor.xml b/src/modelParamXML/Digital/d_nor.xml new file mode 100644 index 00000000..17a60fd5 --- /dev/null +++ b/src/modelParamXML/Digital/d_nor.xml @@ -0,0 +1,12 @@ +<model> +<name>d_nor</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Nor Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_or.xml b/src/modelParamXML/Digital/d_or.xml new file mode 100644 index 00000000..8362e1b3 --- /dev/null +++ b/src/modelParamXML/Digital/d_or.xml @@ -0,0 +1,12 @@ +<model> +<name>d_or</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Or Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_pulldown.xml b/src/modelParamXML/Digital/d_pulldown.xml new file mode 100644 index 00000000..affd1745 --- /dev/null +++ b/src/modelParamXML/Digital/d_pulldown.xml @@ -0,0 +1,10 @@ +<model> +<name>d_pulldown</name> +<type>Digital</type> +<node_number>1</node_number> +<title>Add Parameters for Pulldown</title> +<split>None</split> +<param> + <load default="1.0e-12">Enter value of Load</load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_pullup.xml b/src/modelParamXML/Digital/d_pullup.xml new file mode 100644 index 00000000..1ce491ff --- /dev/null +++ b/src/modelParamXML/Digital/d_pullup.xml @@ -0,0 +1,10 @@ +<model> +<name>d_pullup</name> +<type>Digital</type> +<node_number>1</node_number> +<title>Add Parameters for Pullup</title> +<split>None</split> +<param> + <load default="1.0e-12">Enter value of Load</load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_ram.xml b/src/modelParamXML/Digital/d_ram.xml new file mode 100644 index 00000000..73074201 --- /dev/null +++ b/src/modelParamXML/Digital/d_ram.xml @@ -0,0 +1,16 @@ +<model> +<name>d_ram</name> +<type>Digital</type> +<node_number>5</node_number> +<title>Add Parameters for RAM</title> +<split>4-V:4-V:8-V:1-NV:3-V</split> +<param> + <select_value default ="1">Enter Select Value (default=1)</select_value> + <ic default ="2">Enter IC (default=2)</ic> + <read_delay default ="100.0e-9">Enter Read Delay (default=100.0e-9)</read_delay> + <data_load default ="1.0e-12">Enter value for Data Load (default=1.0e-12)</data_load> + <address_load default ="1.0e-12">Enter value for Address Load (default=1.0e-12)</address_load> + <select_load default ="1.0e-12">Enter value for Select Load (default=1.0e-12)</select_load> + <enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_source.xml b/src/modelParamXML/Digital/d_source.xml new file mode 100644 index 00000000..9bd4347c --- /dev/null +++ b/src/modelParamXML/Digital/d_source.xml @@ -0,0 +1,11 @@ +<model> +<name>d_source</name> +<type>Digital</type> +<node_number>1</node_number> +<title>Add Parameters for Digital Source</title> +<split>4-V</split> +<param> + <input_file default ="source.txt">Enter Input File (default=source.txt)</input_file> + <input_load default ="1.0e-12">Enter Input Load</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_srff.xml b/src/modelParamXML/Digital/d_srff.xml new file mode 100644 index 00000000..9eb65175 --- /dev/null +++ b/src/modelParamXML/Digital/d_srff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_srff</name> +<type>Digital</type> +<node_number>7</node_number> +<title>Add Parameters for SR Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <sr_load default ="1.0e-12">Enter value for SR Load (default=1.0e-12)</sr_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_srlatch.xml b/src/modelParamXML/Digital/d_srlatch.xml new file mode 100644 index 00000000..35dbc061 --- /dev/null +++ b/src/modelParamXML/Digital/d_srlatch.xml @@ -0,0 +1,20 @@ +<model> +<name>d_srlatch</name> +<type>Digital</type> +<node_number>7</node_number> +<title>Add Parameters for SR Latch</title> +<split>None</split> +<param> + <sr_delay default ="1.0e-9">Enter SR Delay (default=1.0e-9)</sr_delay> + <enable_delay default ="1.0e-9">Enter Enable Delay (default=1.0e-9)</enable_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <sr_load default ="1.0e-12">Enter value for SR Load (default=1.0e-12)</sr_load> + <enable_load default ="1.0e-12">Enter value for Enable Load (default=1.0e-12)</enable_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_state.xml b/src/modelParamXML/Digital/d_state.xml new file mode 100644 index 00000000..2290a117 --- /dev/null +++ b/src/modelParamXML/Digital/d_state.xml @@ -0,0 +1,16 @@ +<model> +<name>d_state</name> +<type>Digital</type> +<node_number>4</node_number> +<title>Add Parameters for State Machine</title> +<split>4-V:2-NV:8-V</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <reset_delay default ="1.0e-9">Enter Reset Delay (default=1.0e-9)</reset_delay> + <state_file default ="state.txt">Enter State File (default=state.txt)</state_file> + <reset_state default ="0">Enter Reset Value (default=0)</reset_state> + <input_load default ="1.0e-12">Enter value for Input Load (default=1.0e-12)</input_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_tff.xml b/src/modelParamXML/Digital/d_tff.xml new file mode 100644 index 00000000..ed519d2c --- /dev/null +++ b/src/modelParamXML/Digital/d_tff.xml @@ -0,0 +1,19 @@ +<model> +<name>d_tff</name> +<type>Digital</type> +<node_number>6</node_number> +<title>Add Parameters for T Flipflop</title> +<split>None</split> +<param> + <clk_delay default ="1.0e-9">Enter Clk Delay (default=1.0e-9)</clk_delay> + <set_delay default ="1.0e-9">Enter Set Delay (default=1.0e-9)</set_delay> + <reset_delay default ="1.0">Enter Reset Delay (default=1.0)</reset_delay> + <ic default ="0">Enter IC (default=0)</ic> + <t_load default ="1.0e-12">Enter value for T Load (default=1.0e-12)</t_load> + <clk_load default ="1.0e-12">Enter value for Clk Load (default=1.0e-12)</clk_load> + <set_load default ="1.0e-12">Enter value for Set Load (default=1.0e-12)</set_load> + <reset_load default ="1.0e-12">Enter value for Reset Load (default=1.0e-12)</reset_load> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_tristate.xml b/src/modelParamXML/Digital/d_tristate.xml new file mode 100644 index 00000000..2835da30 --- /dev/null +++ b/src/modelParamXML/Digital/d_tristate.xml @@ -0,0 +1,12 @@ +<model> +<name>d_tristate</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Tristate Buffer</title> +<split>None</split> +<param> + <delay default ="1.0e-9">Enter Delay (default=1.0e-9)</delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> + <enable_load default ="1.0e-12">Enter Enable Load (default=1.0e-12)</enable_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_xnor.xml b/src/modelParamXML/Digital/d_xnor.xml new file mode 100644 index 00000000..4b27bc4c --- /dev/null +++ b/src/modelParamXML/Digital/d_xnor.xml @@ -0,0 +1,12 @@ +<model> +<name>d_xnor</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Xnor Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Digital/d_xor.xml b/src/modelParamXML/Digital/d_xor.xml new file mode 100644 index 00000000..ab238c6d --- /dev/null +++ b/src/modelParamXML/Digital/d_xor.xml @@ -0,0 +1,12 @@ +<model> +<name>d_xor</name> +<type>Digital</type> +<node_number>3</node_number> +<title>Add Parameters for Xor Gate</title> +<split>2-V:1-NV</split> +<param> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> + <input_load default ="1.0e-12">Enter Input Load (default=1.0e-12)</input_load> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_1.xml b/src/modelParamXML/Hybrid/adc_bridge_1.xml new file mode 100644 index 00000000..8d84cd01 --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_1.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>1-V:1-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model> diff --git a/src/modelParamXML/Hybrid/adc_bridge_2.xml b/src/modelParamXML/Hybrid/adc_bridge_2.xml new file mode 100644 index 00000000..1e0ced95 --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_2.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>2-V:2-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_3.xml b/src/modelParamXML/Hybrid/adc_bridge_3.xml new file mode 100644 index 00000000..09d41850 --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_3.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>3-V:3-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_4.xml b/src/modelParamXML/Hybrid/adc_bridge_4.xml new file mode 100644 index 00000000..b29201f5 --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_4.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>4-V:4-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_5.xml b/src/modelParamXML/Hybrid/adc_bridge_5.xml new file mode 100644 index 00000000..bdacf1db --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_5.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>5-V:5-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_6.xml b/src/modelParamXML/Hybrid/adc_bridge_6.xml new file mode 100644 index 00000000..ee60247f --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_6.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>6-V:6-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_7.xml b/src/modelParamXML/Hybrid/adc_bridge_7.xml new file mode 100644 index 00000000..df96b366 --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_7.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>7-V:7-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/adc_bridge_8.xml b/src/modelParamXML/Hybrid/adc_bridge_8.xml new file mode 100644 index 00000000..cdd7afaa --- /dev/null +++ b/src/modelParamXML/Hybrid/adc_bridge_8.xml @@ -0,0 +1,13 @@ +<model> +<name>adc_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for ADC</title> +<split>8-V:8-V</split> +<param> + <in_low default ="1.0">Enter value for in_low (default=1.0)</in_low> + <in_high default ="2.0">Enter value for in_high (default=2.0)</in_high> + <rise_delay default ="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay> + <fall_delay default ="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_1.xml b/src/modelParamXML/Hybrid/dac_bridge_1.xml new file mode 100644 index 00000000..c9e4eed1 --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_1.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>1-V:1-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model> diff --git a/src/modelParamXML/Hybrid/dac_bridge_2.xml b/src/modelParamXML/Hybrid/dac_bridge_2.xml new file mode 100644 index 00000000..c67b22bf --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_2.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>2-V:2-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_3.xml b/src/modelParamXML/Hybrid/dac_bridge_3.xml new file mode 100644 index 00000000..d080f94d --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_3.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>3-V:3-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_4.xml b/src/modelParamXML/Hybrid/dac_bridge_4.xml new file mode 100644 index 00000000..988b575a --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_4.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>4-V:4-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_5.xml b/src/modelParamXML/Hybrid/dac_bridge_5.xml new file mode 100644 index 00000000..39d8f2d2 --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_5.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>5-V:5-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_6.xml b/src/modelParamXML/Hybrid/dac_bridge_6.xml new file mode 100644 index 00000000..2016f971 --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_6.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>6-V:6-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_7.xml b/src/modelParamXML/Hybrid/dac_bridge_7.xml new file mode 100644 index 00000000..37fb936b --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_7.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>7-V:7-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Hybrid/dac_bridge_8.xml b/src/modelParamXML/Hybrid/dac_bridge_8.xml new file mode 100644 index 00000000..72644ad9 --- /dev/null +++ b/src/modelParamXML/Hybrid/dac_bridge_8.xml @@ -0,0 +1,15 @@ +<model> +<name>dac_bridge</name> +<type>Hybrid</type> +<node_number>2</node_number> +<title>Add Parameters for DAC</title> +<split>8-V:8-V</split> +<param> + <out_low default ="0.0">Enter value for out_low (default=0.0)</out_low> + <out_high default ="5.0">Enter value for out_high (default=5.0)</out_high> + <out_undef default ="0.5">Enter value for out_undef (default=0.5)</out_undef> + <input_load default ="1.0e-12">Enter value for input load (default=1.0e-12)</input_load> + <t_rise default ="1.0e-9">Enter the Rise Time (default=1.0e-9)</t_rise> + <t_fall default ="1.0e-9">Enter the Fall Time (default=1.0e-9)</t_fall> +</param> +</model>
\ No newline at end of file diff --git a/src/modelParamXML/Nghdl/inverter.xml b/src/modelParamXML/Nghdl/inverter.xml new file mode 100644 index 00000000..df705ccc --- /dev/null +++ b/src/modelParamXML/Nghdl/inverter.xml @@ -0,0 +1 @@ +<model><name>inverter</name><type>Nghdl</type><node_number>2</node_number><title>Add parameters for inverter</title><split>1-V:1-V</split><param><rise_delay default="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay><fall_delay default="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay><input_load default="1.0e-12">Enter Input Load (default=1.0e-12)</input_load><instance_id default="1">Enter Instance ID (Between 0-99)</instance_id><stop_time default="90e-9">Enter the stop time to end the simulation (default=90e-9)</stop_time></param></model>
\ No newline at end of file diff --git a/src/modelParamXML/Nghdl/myxor.xml b/src/modelParamXML/Nghdl/myxor.xml new file mode 100644 index 00000000..c245879e --- /dev/null +++ b/src/modelParamXML/Nghdl/myxor.xml @@ -0,0 +1 @@ +<model><name>myxor</name><type>Nghdl</type><node_number>3</node_number><title>Add parameters for myxor</title><split>1-V:1-V:1-V</split><param><rise_delay default="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay><fall_delay default="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay><input_load default="1.0e-12">Enter Input Load (default=1.0e-12)</input_load><instance_id default="1">Enter Instance ID (Between 0-99)</instance_id></param></model>
\ No newline at end of file diff --git a/src/ngspiceSimulation/NgspiceWidget.py b/src/ngspiceSimulation/NgspiceWidget.py new file mode 100644 index 00000000..310cbe3c --- /dev/null +++ b/src/ngspiceSimulation/NgspiceWidget.py @@ -0,0 +1,37 @@ +from PyQt4 import QtGui,QtCore +from configuration.Appconfig import Appconfig +import platform +import os + +class NgspiceWidget(QtGui.QWidget): + """ + This Class creates NgSpice Window + """ + def __init__(self,command,projPath): + QtGui.QWidget.__init__(self) + self.obj_appconfig = Appconfig() + self.process = QtCore.QProcess(self) + self.terminal = QtGui.QWidget(self) + self.layout = QtGui.QVBoxLayout(self) + self.layout.addWidget(self.terminal) + + print "Argument to ngspice command : ",command + + if platform.system() == 'Linux': + self.command = "cd "+projPath+";ngspice "+command + #Creating argument for process + #self.args = ['-into', str(self.terminal.winId()),'-hold','-e', self.command] + self.args = ['-hold','-e', self.command] + self.process.start('xterm', self.args) + self.obj_appconfig.process_obj.append(self.process) + self.obj_appconfig.proc_dict[self.obj_appconfig.current_project['ProjectName']].append(self.process.pid()) + + elif platform.system() == 'Windows': + tempdir= os.getcwd() + projPath = self.obj_appconfig.current_project["ProjectName"] + os.chdir(projPath) + self.command = "ngspice "+command + self.process.start(self.command) + os.chdir(tempdir) + + diff --git a/src/ngspiceSimulation/NgspiceWidget.pyc b/src/ngspiceSimulation/NgspiceWidget.pyc Binary files differnew file mode 100644 index 00000000..45245b0b --- /dev/null +++ b/src/ngspiceSimulation/NgspiceWidget.pyc diff --git a/src/ngspiceSimulation/__init__.py b/src/ngspiceSimulation/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/ngspiceSimulation/__init__.py diff --git a/src/ngspiceSimulation/__init__.pyc b/src/ngspiceSimulation/__init__.pyc Binary files differnew file mode 100644 index 00000000..4382078b --- /dev/null +++ b/src/ngspiceSimulation/__init__.pyc diff --git a/src/ngspiceSimulation/pythonPlotting.py b/src/ngspiceSimulation/pythonPlotting.py new file mode 100644 index 00000000..295c0a1d --- /dev/null +++ b/src/ngspiceSimulation/pythonPlotting.py @@ -0,0 +1,746 @@ +from __future__ import division # Used for decimal division eg 2/3=0.66 and not '0' 6/2=3.0 and 6//2=3 +import os +from PyQt4 import QtGui, QtCore +from decimal import Decimal,getcontext +from matplotlib.backends.backend_qt4agg import FigureCanvasQTAgg as FigureCanvas +from matplotlib.backends.backend_qt4agg import NavigationToolbar2QT as NavigationToolbar +from matplotlib.figure import Figure +from configuration.Appconfig import Appconfig +import numpy as np + +class plotWindow(QtGui.QMainWindow): + def __init__(self,fpath,projectName): + QtGui.QMainWindow.__init__(self) + self.fpath = fpath + self.projectName = projectName + self.obj_appconfig = Appconfig() + print "Complete Project Path : ",self.fpath + print "Project Name : ",self.projectName + self.obj_appconfig.print_info('Ngspice simulation is called : ' + self.fpath) + self.obj_appconfig.print_info('PythonPlotting is called : ' + self.fpath) + self.combo = [] + self.combo1 = [] + self.combo1_rev = [] + #Creating Frame + self.createMainFrame() + + def createMainFrame(self): + self.mainFrame = QtGui.QWidget() + self.dpi = 100 + self.fig = Figure((7.0, 7.0), dpi=self.dpi) + #Creating Canvas which will figure + self.canvas = FigureCanvas(self.fig) + self.canvas.setParent(self.mainFrame) + self.axes = self.fig.add_subplot(111) + self.navToolBar = NavigationToolbar(self.canvas, self.mainFrame) + + #LeftVbox hold navigation tool bar and canvas + self.left_vbox = QtGui.QVBoxLayout() + self.left_vbox.addWidget(self.navToolBar) + self.left_vbox.addWidget(self.canvas) + + #right VBOX is main Layout which hold right grid(bottom part) and top grid(top part) + self.right_vbox = QtGui.QVBoxLayout() + self.right_grid = QtGui.QGridLayout() + self.top_grid = QtGui.QGridLayout() + + #Get DataExtraction Details + self.obj_dataext = DataExtraction() + self.plotType = self.obj_dataext.openFile(self.fpath) + + self.obj_dataext.computeAxes() + self.a = self.obj_dataext.numVals() + + self.chkbox=[] + + ########### Generating list of colors : + self.full_colors = ['r','b','g','y','c','m','k']#,(0.4,0.5,0.2),(0.1,0.4,0.9),(0.4,0.9,0.2),(0.9,0.4,0.9)] + self.color = [] + for i in range(0,self.a[0]-1): + if i%7 == 0: + self.color.append(self.full_colors[0]) + elif (i-1)%7 == 0: + self.color.append(self.full_colors[1]) + elif (i-2)%7 == 0: + self.color.append(self.full_colors[2]) + elif (i-3)%7 == 0: + self.color.append(self.full_colors[3]) + elif (i-4)%7 == 0: + self.color.append(self.full_colors[4]) + elif (i-5)%7 == 0: + self.color.append(self.full_colors[5]) + elif (i-6)%7 == 0: + self.color.append(self.full_colors[6]) + + ###########Color generation ends here + + + #Total number of voltage source + self.volts_length = self.a[1] + self.analysisType = QtGui.QLabel() + self.top_grid.addWidget(self.analysisType,0,0) + self.listNode = QtGui.QLabel() + self.top_grid.addWidget(self.listNode,1,0) + self.listBranch = QtGui.QLabel() + self.top_grid.addWidget(self.listBranch,self.a[1]+2,0) + for i in range(0,self.a[1]):#a[0]-1 + self.chkbox.append(QtGui.QCheckBox(self.obj_dataext.NBList[i])) + self.chkbox[i].setStyleSheet('color') + self.chkbox[i].setToolTip('<b>Check To Plot</b>' ) + self.top_grid.addWidget(self.chkbox[i],i+2,0) + self.colorLab = QtGui.QLabel() + self.colorLab.setText('____') + self.colorLab.setStyleSheet(self.colorName(self.color[i])+'; font-weight = bold;') + self.top_grid.addWidget(self.colorLab,i+2,1) + + for i in range(self.a[1],self.a[0]-1):#a[0]-1 + self.chkbox.append(QtGui.QCheckBox(self.obj_dataext.NBList[i])) + self.chkbox[i].setToolTip('<b>Check To Plot</b>' ) + self.top_grid.addWidget(self.chkbox[i],i+3,0) + self.colorLab = QtGui.QLabel() + self.colorLab.setText('____') + self.colorLab.setStyleSheet(self.colorName(self.color[i])+'; font-weight = bold;') + self.top_grid.addWidget(self.colorLab,i+3,1) + + self.clear = QtGui.QPushButton("Clear") + self.warnning = QtGui.QLabel() + self.funcName = QtGui.QLabel() + self.funcExample = QtGui.QLabel() + + self.plotbtn = QtGui.QPushButton("Plot") + self.plotbtn.setToolTip('<b>Press</b> to Plot' ) + self.multimeterbtn = QtGui.QPushButton("Multimeter") + self.multimeterbtn.setToolTip('<b>RMS</b> value of the current and voltage is displayed' ) + self.text = QtGui.QLineEdit() + self.funcLabel = QtGui.QLabel() + self.palette1 = QtGui.QPalette() + self.palette2 = QtGui.QPalette() + self.plotfuncbtn = QtGui.QPushButton("Plot Function") + self.plotfuncbtn.setToolTip('<b>Press</b> to Plot the function' ) + + self.palette1.setColor(QtGui.QPalette.Foreground,QtCore.Qt.blue) + self.palette2.setColor(QtGui.QPalette.Foreground,QtCore.Qt.red) + self.funcName.setPalette(self.palette1) + self.funcExample.setPalette(self.palette2) + + self.right_vbox.addLayout(self.top_grid) + self.right_vbox.addWidget(self.plotbtn) + self.right_vbox.addWidget(self.multimeterbtn) + + self.right_grid.addWidget(self.funcLabel,1,0) + self.right_grid.addWidget(self.text,1,1) + self.right_grid.addWidget(self.plotfuncbtn,2,1) + self.right_grid.addWidget(self.clear,2,0) + self.right_grid.addWidget(self.warnning,3,0) + self.right_grid.addWidget(self.funcName,4,0) + self.right_grid.addWidget(self.funcExample,4,1) + self.right_vbox.addLayout(self.right_grid) + + self.hbox = QtGui.QHBoxLayout() + self.hbox.addLayout(self.left_vbox) + self.hbox.addLayout(self.right_vbox) + + self.widget = QtGui.QWidget() + self.widget.setLayout(self.hbox)#finalvbox + self.scrollArea = QtGui.QScrollArea() + self.scrollArea.setWidgetResizable(True) + self.scrollArea.setWidget(self.widget) + + self.finalhbox = QtGui.QHBoxLayout() + self.finalhbox.addWidget(self.scrollArea) + + self.mainFrame.setLayout(self.finalhbox) + self.showMaximized() + + self.listNode.setText("<font color='indigo'>List of Nodes:</font>") + self.listBranch.setText("<font color='indigo'>List of Branches:</font>") + self.funcLabel.setText("<font color='indigo'>Function:</font>") + self.funcName.setText("<font color='indigo'>Standard functions</font>\ + <br><br>Addition:<br>Subtraction:<br>Multiplication:<br>Division:<br>Comparison:") + self.funcExample.setText("\n\nNode1 + Node2\nNode1 - Node2\nNode1 * Node2\nNode1 / Node2\nNode1 vs Node2") + + #Connecting to plot and clear function + self.connect(self.clear,QtCore.SIGNAL('clicked()'),self.pushedClear) + self.connect(self.plotfuncbtn,QtCore.SIGNAL('clicked()'), self.pushedPlotFunc) + self.connect(self.multimeterbtn,QtCore.SIGNAL('clicked()'), self.multiMeter) + + + if self.plotType[0]==0: + self.analysisType.setText("<b>AC Analysis</b>") + if self.plotType[1]==1: + self.connect(self.plotbtn, QtCore.SIGNAL('clicked()'), self.onPush_decade) + else: + self.connect(self.plotbtn, QtCore.SIGNAL('clicked()'), self.onPush_ac) + + elif self.plotType[0]==1: + self.analysisType.setText("<b>Transient Analysis</b>") + self.connect(self.plotbtn, QtCore.SIGNAL('clicked()'), self.onPush_trans) + + else: + self.analysisType.setText("<b>DC Analysis</b>") + self.connect(self.plotbtn, QtCore.SIGNAL('clicked()'), self.onPush_dc) + + self.setCentralWidget(self.mainFrame) + + def pushedClear(self): + self.text.clear() + self.axes.cla() + self.canvas.draw() + QtCore.SLOT('quit()') + + def pushedPlotFunc(self): + self.parts = str(self.text.text()) + self.parts = self.parts.split(" ") + + if self.parts[len(self.parts)-1] == '': + self.parts = self.parts[0:-1] + + self.values = self.parts + self.comboAll = [] + self.axes.cla() + + self.plotType2 = self.obj_dataext.openFile(self.fpath) + + if len(self.parts) <= 2: + self.warnning.setText("Too few arguments!\nRefer syntax below!") + QtGui.QMessageBox.about(self, "Warning!!", "Too Few Arguments/SYNTAX Error!\n Refer Examples") + else: + self.warnning.setText("") + + a = [] + finalResult = [] + p = 0 + + for i in range(len(self.parts)): + #print "I",i + if i%2 == 0: + #print "I'm in:" + for j in range(len(self.obj_dataext.NBList)): + if self.parts[i]==self.obj_dataext.NBList[j]: + #print "I got you:",self.parts[i] + a.append(j) + + if len(a) != len(self.parts)//2 + 1: + QtGui.QMessageBox.about(self, "Warning!!", "One of the operands doesn't belong to the above list of Nodes!!") + + for i in a: + self.comboAll.append(self.obj_dataext.y[i]) + + + for i in range(len(a)): + + if a[i] == len(self.obj_dataext.NBList): + QtGui.QMessageBox.about(self, "Warning!!", "One of the operands doesn't belong to the above list!!") + self.warnning.setText("<font color='red'>To Err Is Human!<br>One of the operands doesn't belong to the above list!!</font>") + + if self.parts[1] == 'vs': + if len(self.parts) > 3: + self.warnning.setText("Enter two operands only!!") + QtGui.QMessageBox.about(self, "Warning!!", "Recheck the expression syntax!") + + else: + self.axes.cla() + + for i in range(len(self.obj_dataext.y[a[0]])): + self.combo.append(self.obj_dataext.y[a[0]][i]) + self.combo1.append(self.obj_dataext.y[a[1]][i]) + + self.axes.plot(self.combo,self.combo1,c=self.color[1],label=str(2))#_rev + + if max(a) < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + self.axes.set_xlabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + self.axes.set_ylabel('Current(I)-->') + + elif max(a) >= self.volts_length and min(a) < self.volts_length: + QtGui.QMessageBox.about(self, "Warning!!", "Do not combine Voltage and Current!!") + + else: + for j in range(len(self.comboAll[0])): + for i in range(len(self.values)): + if i%2==0: + self.values[i] = str(self.comboAll[i//2][j]) + re = " ".join(self.values[:]) + try: + finalResult.append(eval(re)) + except ArithmeticError: + QtGui.QMessageBox.about(self, "Warning!!", "Dividing by zero!!") + + if self.plotType2[0]==0: + #self.setWindowTitle('AC Analysis') + if self.plotType2[1]==1: + self.axes.semilogx(self.obj_dataext.x,finalResult,c=self.color[0],label=str(1)) + else: + self.axes.plot(self.obj_dataext.x,finalResult,c=self.color[0],label=str(1)) + + self.axes.set_xlabel('freq-->') + + if max(a) < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + + elif self.plotType2[0]==1: + #self.setWindowTitle('Transient Analysis') + self.axes.plot(self.obj_dataext.x,finalResult,c=self.color[0],label=str(1)) + self.axes.set_xlabel('time-->') + if max(a) < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + + else: + #self.setWindowTitle('DC Analysis') + self.axes.plot(self.obj_dataext.x,finalResult,c=self.color[0],label=str(1)) + self.axes.set_xlabel('I/P Voltage-->') + if max(a) < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + + + self.axes.grid(True) + self.canvas.draw() + self.combo = [] + self.combo1 = [] + self.combo1_rev = [] + + + + + def onPush_decade(self): + #print "Calling on push Decade" + boxCheck = 0 + self.axes.cla() + + for i,j in zip(self.chkbox,range(len(self.chkbox))): + if i.isChecked(): + boxCheck += 1 + self.axes.semilogx(self.obj_dataext.x,self.obj_dataext.y[j],c=self.color[j],label=str(j+1)) + self.axes.set_xlabel('freq-->') + if j < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + + self.axes.grid(True) + if boxCheck == 0: + QtGui.QMessageBox.about(self, "Warning!!","Please select at least one Node OR Branch") + self.canvas.draw() + + + def onPush_ac(self): + self.axes.cla() + boxCheck = 0 + for i,j in zip(self.chkbox,range(len(self.chkbox))): + if i.isChecked(): + boxCheck += 1 + self.axes.plot(self.obj_dataext.x,self.obj_dataext.y[j],c=self.color[j],label=str(j+1)) + self.axes.set_xlabel('freq-->') + if j < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + self.axes.grid(True) + if boxCheck == 0: + QtGui.QMessageBox.about(self, "Warning!!","Please select at least one Node OR Branch") + self.canvas.draw() + + def onPush_trans(self): + self.axes.cla() + boxCheck = 0 + for i,j in zip(self.chkbox,range(len(self.chkbox))): + if i.isChecked(): + boxCheck += 1 + self.axes.plot(self.obj_dataext.x,self.obj_dataext.y[j],c=self.color[j],label=str(j+1)) + self.axes.set_xlabel('time-->') + if j < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + self.axes.grid(True) + if boxCheck == 0: + QtGui.QMessageBox.about(self, "Warning!!","Please select at least one Node OR Branch") + self.canvas.draw() + + + def onPush_dc(self): + boxCheck = 0 + self.axes.cla() + for i,j in zip(self.chkbox,range(len(self.chkbox))): + if i.isChecked(): + boxCheck += 1 + self.axes.plot(self.obj_dataext.x,self.obj_dataext.y[j],c=self.color[j],label=str(j+1)) + self.axes.set_xlabel('Voltage Sweep(V)-->') + + if j < self.volts_length: + self.axes.set_ylabel('Voltage(V)-->') + else: + self.axes.set_ylabel('Current(I)-->') + self.axes.grid(True) + if boxCheck == 0: + QtGui.QMessageBox.about(self,"Warning!!", "Please select atleast one Node OR Branch") + self.canvas.draw() + + def colorName(self,letter): + return { + 'r':'color:red', + 'b':'color:blue', + 'g':'color:green', + 'y':'color:yellow', + 'c':'color:cyan', + 'm':'color:magenta', + 'k':'color:black' + }[letter] + + def multiMeter(self): + print "Function : MultiMeter" + self.obj = {} + boxCheck = 0 + loc_x = 300 + loc_y = 300 + + for i,j in zip(self.chkbox,range(len(self.chkbox))): + if i.isChecked(): + print "Check box",self.obj_dataext.NBList[j] + boxCheck += 1 + if self.obj_dataext.NBList[j] in self.obj_dataext.NBIList: + voltFlag = False + else: + voltFlag = True + #Initializing Multimeter + self.obj[j] = MultimeterWidgetClass(self.obj_dataext.NBList[j],self.getRMSValue(self.obj_dataext.y[j]),loc_x,loc_y,voltFlag) + loc_x += 50 + loc_y += 50 + ## Adding object of multimeter to dictionary + self.obj_appconfig.dock_dict[self.obj_appconfig.current_project['ProjectName']].append(self.obj[j]) + + if boxCheck == 0: + QtGui.QMessageBox.about(self, "Warning!!","Please select at least one Node OR Branch") + + + def getRMSValue(self,dataPoints): + getcontext().prec = 5 + return np.sqrt(np.mean(np.square(dataPoints))) + +class MultimeterWidgetClass(QtGui.QWidget): + def __init__(self,node_branch,rmsValue,loc_x,loc_y,voltFlag): + QtGui.QWidget.__init__(self) + + self.multimeter = QtGui.QWidget(self) + if voltFlag: + self.node_branchLabel = QtGui.QLabel("Node") + self.rmsValue = QtGui.QLabel(str(rmsValue)+" Volts") + else: + self.node_branchLabel = QtGui.QLabel("Branch") + self.rmsValue = QtGui.QLabel(str(rmsValue)+" Amp") + + self.rmsLabel = QtGui.QLabel("RMS Value") + self.nodeBranchValue = QtGui.QLabel(str(node_branch)) + + + self.layout = QtGui.QGridLayout(self) + self.layout.addWidget(self.node_branchLabel,0,0) + self.layout.addWidget(self.rmsLabel,0,1) + self.layout.addWidget(self.nodeBranchValue,1,0) + self.layout.addWidget(self.rmsValue,1,1) + + self.multimeter.setLayout(self.layout) + self.setGeometry(loc_x,loc_y,200,100) + self.setGeometry(loc_x,loc_y,300,100) + self.setWindowTitle("MultiMeter") + self.setWindowFlags(QtCore.Qt.WindowStaysOnTopHint) + self.show() + + +class DataExtraction: + def __init__(self): + self.obj_appconfig = Appconfig() + self.data=[] #consists of all the columns of data belonging to nodes and branches + self.y=[] #stores y-axis data + self.x=[] #stores x-axis data + + + def numberFinder(self,fpath): + #Opening ANalysis file + with open(os.path.join(fpath,"analysis")) as f3: + self.analysisInfo = f3.read() + self.analysisInfo = self.analysisInfo.split(" ") + + + #Reading data file for voltage + with open(os.path.join(fpath,"plot_data_v.txt")) as f2: + self.voltData = f2.read() + + self.voltData = self.voltData.split("\n") + + #Initializing variable + #'p' gives no. of lines of data for each node/branch + # 'l' gives the no of partitions for a single voltage node + #'vnumber' gives total number of voltage + #'inumber' gives total number of current + + p = l = vnumber = inumber = 0 + #print "VoltsData : ",self.voltData + + #Finding totla number of voltage node + for i in self.voltData[3:]: + #it has possible names of voltage nodes in NgSpice + if "Index" in i:#"V(" in i or "x1" in i or "u3" in i: + vnumber+=1 + + #print "Voltage Number :",vnumber + + #Reading Current Source Data + with open (os.path.join(fpath,"plot_data_i.txt")) as f1: + self.currentData = f1.read() + self.currentData = self.currentData.split("\n") + + #print "CurrentData : ",self.currentData + + #Finding Number of Branch + for i in self.currentData[3:]: + if "#branch" in i: + inumber+=1 + + #print "Current Number :",inumber + + self.dec = 0 + + #For AC + if self.analysisInfo[0][-3:]==".ac": + self.analysisType = 0 + if "dec" in self.analysisInfo: + self.dec = 1 + + for i in self.voltData[3:]: + p+=1 #'p' gives no. of lines of data for each node/branch + if "Index" in i: + l+=1 # 'l' gives the no of partitions for a single voltage node + #print "l:",l + if "AC" in i: #DC for dc files and AC for ac ones + break + + elif ".tran" in self.analysisInfo: + self.analysisType = 1 + for i in self.voltData[3:]: + p+=1 + if "Index" in i: + l+=1 # 'l' gives the no of partitions for a single voltage node + #print "l:",l + if "Transient" in i: #DC for dc files and AC for ac ones + break + + + # For DC: + else: + self.analysisType = 2 + for i in self.voltData[3:]: + p+=1 + if "Index" in i: + l+=1 # 'l' gives the no of partitions for a single voltage node + #print "l:",l + if "DC" in i: #DC for dc files and AC for ac ones + break + + + + + #print "VoltNumber",vnumber + #print "CurrentNumber",inumber + vnumber = vnumber//l #vnumber gives the no of voltage nodes + inumber = inumber//l #inumber gives the no of branches + + #print "VoltNumber",vnumber + #print "CurrentNumber",inumber + + p=[p,vnumber,self.analysisType,self.dec,inumber] + + return p + + def openFile(self,fpath): + try: + with open (os.path.join(fpath,"plot_data_i.txt")) as f2: + alli = f2.read() + + alli = alli.split("\n") + self.NBIList = [] + + with open (os.path.join(fpath,"plot_data_v.txt")) as f1: + allv = f1.read() + + except Exception as e: + print "Exception Message : ",str(e) + self.obj_appconfig.print_error('Exception Message :' + str(e)) + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Unable to open plot data files.') + self.msg.setWindowTitle("Error Message:openFile") + + try: + for l in alli[3].split(" "): + if len(l)>0: + self.NBIList.append(l) + self.NBIList = self.NBIList[2:] + len_NBIList = len(self.NBIList) + #print "NBILIST : ",self.NBIList + except Exception as e: + print "Exception Message : ",str(e) + self.obj_appconfig.print_error('Exception Message :' + str(e)) + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Error in Analysis File.') + self.msg.setWindowTitle("Error Message:openFile") + + + d = self.numberFinder(fpath) + d1 = int(d[0] + 1) + d2 = int(d[1]) + d3 = d[2] + d4 = d[4] + + dec = [d3,d[3]] + #print "No. of Nodes:", d2 + self.NBList = [] + allv=allv.split("\n") + for l in allv[3].split(" "): + if len(l)>0: + self.NBList.append(l) + self.NBList=self.NBList[2:] + len_NBList = len(self.NBList) + print "NBLIST",self.NBList + + ivals=[] + inum = len(allv[5].split("\t")) + inum_i = len(alli[5].split("\t")) + + + + full_data = [] + + # Creating list of data: + if d3 < 3 : + for i in range(1,d2): + for l in allv[3+i*d1].split(" "): + if len(l)>0: + self.NBList.append(l) + self.NBList.pop(len_NBList) + self.NBList.pop(len_NBList) + len_NBList = len(self.NBList) + + for n in range(1,d4): + for l in alli[3+n*d1].split(" "): + if len(l)>0: + self.NBIList.append(l) + self.NBIList.pop(len_NBIList) + self.NBIList.pop(len_NBIList) + len_NBIList = len(self.NBIList) + + p=0 + k = 0 + m=0 + + for i in alli[5:d1-1]: + if len(i.split("\t"))==inum_i: + j2=i.split("\t") + #print j2 + j2.pop(0) + j2.pop(0) + j2.pop() + if d3 == 0: #not in trans + j2.pop() + #print j2 + + for l in range(1,d4): + j3 = alli[5+l*d1+k].split("\t") + j3.pop(0) + j3.pop(0) + if d3==0: + j3.pop() #not required for dc + j3.pop() + j2 = j2 + j3 + #print j2 + + + full_data.append(j2) + + k+=1 + + #print "FULL DATA :",full_data + + + for i in allv[5:d1-1]: + if len(i.split("\t"))==inum: + j=i.split("\t") + j.pop() + if d3==0: + j.pop() + for l in range(1,d2): + j1 = allv[5+l*d1+p].split("\t") + j1.pop(0) + j1.pop(0) + if d3==0: + j1.pop() #not required for dc + if self.NBList[len(self.NBList)-1] == 'v-sweep': + self.NBList.pop() + j1.pop() + + j1.pop() + j = j + j1 + j = j + full_data[m] + #print j + m+=1 + #print j[:20] + j = "\t".join(j[1:]) + j = j.replace(",","") + ivals.append(j) + + p+=1 + + self.data = ivals + + #print "volts:",self.butnames + self.volts_length = len(self.NBList) + self.NBList = self.NBList + self.NBIList + + + print dec + return dec + + + def numVals(self): + a = self.volts_length # No of voltage nodes + b = len(self.data[0].split("\t")) + #print "numvals:",b + return [b,a] + + + def computeAxes(self): + nums = len(self.data[0].split("\t")) + #print "i'm nums:",nums + self.y=[] + var=self.data[0].split("\t") + for i in range(1,nums): + self.y.append([Decimal(var[i])]) + for i in self.data[1:]: + temp=i.split("\t") + for j in range(1,nums): + self.y[j-1].append(Decimal(temp[j])) + for i in self.data: + temp=i.split("\t") + self.x.append(Decimal(temp[0])) + + + + + + + + + + + + + + + diff --git a/src/ngspiceSimulation/pythonPlotting.pyc b/src/ngspiceSimulation/pythonPlotting.pyc Binary files differnew file mode 100644 index 00000000..fef621b9 --- /dev/null +++ b/src/ngspiceSimulation/pythonPlotting.pyc diff --git a/src/ngspicetoModelica/Mapping.json b/src/ngspicetoModelica/Mapping.json new file mode 100644 index 00000000..e254d66a --- /dev/null +++ b/src/ngspicetoModelica/Mapping.json @@ -0,0 +1,281 @@ +{ + "Components":{ + "R" : "Analog.Basic.Resistor", + "C" : "Analog.Basic.Capacitor", + "L" : "Analog.Basic.Inductor", + "e" : "Analog.Basic.VCV", + "g" : "Analog.Basic.VCC", + "f" : "Analog.Basic.CCC", + "h" : "Analog.Basic.CCV", + "0" : "Analog.Basic.Ground", + "gnd" : "Analog.Basic.Ground" + + }, + "Sources":{ + "v":{ + "pulse":"Analog.Sources.TrapezoidVoltage", + "sine":"Analog.Sources.SineVoltage", + "pwl" : "Analog.Sources.TableVoltage", + "dc" : "Analog.Sources.ConstantVoltage" + }, + + "i":{ + "dc":"Analog.Sources.ConstantCurrent" + } + + }, + "Devices":{ + "d":{ + "import":"Analog.Semiconductors.Diode", + "mapping":{ + + "is":"Ids" + }, + "default":{ + "Ids":"880.5e-18", + "Vt":"0.025", + "R":"1e12" + } + + }, + + "m":{ + "import":"BondLib.Electrical.Analog.Spice", + "mapping":{ + "tnom":"Tnom", + "vto":"VT0", + "gamma":"GAMMA", + "phi":"PHI", + "ld":"LD", + "uo":"U0", + "lambda":"LAMBDA", + "tox":"TOX", + "pb":"PB", + "cj":"CJ", + "cjsw":"CJSW", + "mj":"MJ", + "mjsw":"MJSW", + "cgdo":"CGD0", + "js":"JS", + "cgbo":"CGB0", + "cgso":"CGS0" + + + }, + "default":{ + "Tnom":"300", + "VT0":"0", + "GAMMA":"0", + "PHI":"0", + "LD":"0", + "U0":"0", + "LAMBDA":"0", + "TOX":"3e-9", + "PB":"0.8", + "CJ":"0", + "CJSW":"1e-9", + "MJ":"0.33", + "MJSW":"0.33", + "CGD0":"0", + "JS":"0", + "CGB0":"0", + "CGS0":"0" + + + } + + }, + "q":{ + "import":"Analog.Semiconductors", + "mapping":{ + "bf":"Bf", + "br":"Br", + "is":"Is", + "vak":"Vak", + "tf":"Tauf", + "tr":"Taur", + "cjs":"Ccs", + "cje":"Cje", + "cjc":"Cjc", + "vje":"Phie", + "mje":"Me", + "vjc":"Phic", + "mjc":"Mc" + }, + "default":{ + "Bf":"50", + "Br":"0.1", + "Is":"1e-16", + "Tauf":"1.2e-10", + "Taur":"5e-9", + "Vak":"0.02", + "Ccs":"1e-12", + "Cje":"4e-12", + "Cjc":"5e-13", + "Phie":"0.8", + "Me":"0.4", + "Phic":"0.8", + "Mc":"0.333" + + } + + }, + + "j":{ + "import":"Spice3.Internal.JFET", + "mapping":{ + "kf":"KF", + "rs":"RS", + "is":"IS", + "cgd":"CGD", + "vto":"VTO", + "rd":"RD", + "pb":"PB", + "beta":"BETA", + "fc":"FC", + "af":"AF", + "cgs":"CGS", + "lambda":"LAMBDA", + "b" : "B" + + }, + + "default":{ + "KF":"0", + "RS":"0", + "IS":"1e-14", + "CGD":"0", + "VTO":"-2", + "RD":"0", + "PB":"1", + "BETA":"1e-4", + "FC":"0.5", + "AF":"1", + "CGS":"0", + "LAMBDA":"0", + "B":"1" + + + } + } + + }, + + + "Models":{ + "zener":{ + "import":"Analog.Semiconductors.ZDiode", + "mapping":{ + "v_breakdown":"Bv", + "i_breakdown":"Ibv", + "i_sat":"Ids", + "n_forward":"Nbv" + + }, + "default":{ + "Ids":"880.5e-18", + "Vt":"0.025", + "R":"1e12", + "Bv":"8.1", + "Ibv":"0.020245", + "Nbv":"1.6989" + + } + + } + }, + + "Units":{ + "k":"e3", + "u":"e-6", + "p":"e-12", + "t":"e12", + "f":"e-15", + "g":"e9", + "m":"e-3", + "meg":"e6", + "n":"e-9", + + "v":"", + "a":"", + "s":"", + "hz":"", + "ohm":"", + "mho":"", + "h":"", + + + "kv":"e3", + "ka":"e3", + "ks":"e3", + "khz":"e3", + "kohm":"e3", + "kmho":"e3", + "kh":"e3", + + + "uv":"e-06", + "ua":"e-06", + "us":"e-06", + "uhz":"e-06", + "uohm":"e-06", + "umho":"e-06", + "uh":"e-06", + + "pv":"e-12", + "pa":"e-12", + "ps":"e-12", + "phz":"e-12", + "pohm":"e-12", + "pmho":"e-12", + "ph":"e-12", + + + "tv":"e12", + "ta":"e12", + "ts":"e12", + "thz":"e12", + "tohm":"e12", + "tmho":"e12", + "th":"e12", + + + "gv":"e9", + "ga":"e9", + "gs":"e9", + "ghz":"e9", + "gohm":"e9", + "gmho":"e9", + "gh":"e9", + + + "mv":"e-03", + "ma":"e-03", + "ms":"e-03", + "mhz":"e-03", + "mohm":"e-03", + "mmho":"e-03", + "mh":"e-03", + + + "megv":"e06", + "mega":"e06", + "megs":"e06", + "meghz":"e06", + "megohm":"e06", + "megmho":"e06", + "megh":"e06", + + + + "nv":"e-09", + "na":"e-09", + "ns":"e-09", + "nhz":"e-09", + "nohm":"e-09", + "nmho":"e-09", + "nh":"e-09" + + } + +} diff --git a/src/ngspicetoModelica/ModelicaUI.py b/src/ngspicetoModelica/ModelicaUI.py new file mode 100644 index 00000000..e4079562 --- /dev/null +++ b/src/ngspicetoModelica/ModelicaUI.py @@ -0,0 +1,95 @@ +import os +import sys +from subprocess import Popen, PIPE, STDOUT +from PyQt4 import QtGui, QtCore +from configuration.Appconfig import Appconfig +from projManagement import Worker +from projManagement.Validation import Validation + +BROWSE_LOCATION = '/home' + +class OpenModelicaEditor(QtGui.QWidget): + + def __init__(self, dir=None): + QtGui.QWidget.__init__(self) + self.obj_validation = Validation() + self.obj_appconfig = Appconfig() + self.projDir = dir + self.projName = os.path.basename(self.projDir) + self.ngspiceNetlist = os.path.join(self.projDir,self.projName+".cir.out") + self.modelicaNetlist = os.path.join(self.projDir,self.projName+".mo") + self.map_json = Appconfig.modelica_map_json + + self.grid = QtGui.QGridLayout() + self.FileEdit = QtGui.QLineEdit() + self.FileEdit.setText(self.ngspiceNetlist) + self.grid.addWidget(self.FileEdit, 0, 0) + + self.browsebtn = QtGui.QPushButton("Browse") + self.browsebtn.clicked.connect(self.browseFile) + self.grid.addWidget(self.browsebtn, 0, 1) + + self.convertbtn = QtGui.QPushButton("Convert") + self.convertbtn.clicked.connect(self.callConverter) + self.grid.addWidget(self.convertbtn, 2, 1) + + self.loadOMbtn = QtGui.QPushButton("Load OMEdit") + self.loadOMbtn.clicked.connect(self.callOMEdit) + self.grid.addWidget(self.loadOMbtn, 3, 1) + + #self.setGeometry(300, 300, 350, 300) + self.setLayout(self.grid) + self.show() + + def browseFile(self): + + self.ngspiceNetlist = QtGui.QFileDialog.getOpenFileName(self, 'Open Ngspice file', BROWSE_LOCATION) + self.FileEdit.setText(self.ngspiceNetlist) + + def callConverter(self): + + try: + self.cmd1 = "python ../ngspicetoModelica/NgspicetoModelica.py " + self.ngspiceNetlist + ' ' + self.map_json + #self.obj_workThread1 = Worker.WorkerThread(self.cmd1) + #self.obj_workThread1.start() + convert_process = Popen(self.cmd1, shell=True, stdin=PIPE, stdout=PIPE, stderr=STDOUT, close_fds=True) + error_code = convert_process.stdout.read() + if not error_code: + self.msg = QtGui.QMessageBox() + self.msg.setText("Ngspice netlist successfully converted to OpenModelica netlist") + self.obj_appconfig.print_info("Ngspice netlist successfully converted to OpenModelica netlist") + self.msg.exec_() + + else: + self.err_msg = QtGui.QErrorMessage() + self.err_msg.showMessage('Unable to convert NgSpice netlist to Modelica netlist. Check the netlist :'+ error_code) + self.err_msg.setWindowTitle("Ngspice to Modelica conversion error") + self.obj_appconfig.print_error(error_code) + + except Exception as e: + self.msg = QtGui.QErrorMessage() + self.msg.showMessage('Unable to convert NgSpice netlist to Modelica netlist. Check the netlist :'+str(e)) + self.msg.setWindowTitle("Ngspice to Modelica conversion error") + + + def callOMEdit(self): + + if self.obj_validation.validateTool("OMEdit"): + self.cmd2 = "OMEdit " + self.modelicaNetlist + self.obj_workThread2 = Worker.WorkerThread(self.cmd2) + self.obj_workThread2.start() + print "OMEdit called" + self.obj_appconfig.print_info("OMEdit called") + + else: + self.msg = QtGui.QMessageBox() + self.msgContent = "There was an error while opening OMEdit.<br/>\ + Please make sure OpenModelica is installed in your system. <br/>\ + To install it on Linux : Go to <a href=https://www.openmodelica.org/download/download-linux>OpenModelica Linux</a> and install nigthly build release.<br/>\ + To install it on Windows : Go to <a href=https://www.openmodelica.org/download/download-windows>OpenModelica Windows</a> and install latest version.<br/>" + self.msg.setTextFormat(QtCore.Qt.RichText) + self.msg.setText(self.msgContent) + self.msg.setWindowTitle("Missing OpenModelica") + self.obj_appconfig.print_info(self.msgContent) + self.msg.exec_() + diff --git a/src/ngspicetoModelica/ModelicaUI.pyc b/src/ngspicetoModelica/ModelicaUI.pyc Binary files differnew file mode 100644 index 00000000..0f185bd2 --- /dev/null +++ b/src/ngspicetoModelica/ModelicaUI.pyc diff --git a/src/ngspicetoModelica/NgspicetoModelica.py b/src/ngspicetoModelica/NgspicetoModelica.py new file mode 100644 index 00000000..7b7e4527 --- /dev/null +++ b/src/ngspicetoModelica/NgspicetoModelica.py @@ -0,0 +1,1123 @@ +import sys +import os +import re +import json +from string import maketrans + +class NgMoConverter: + + + def __init__(self, map_json): + #Loading JSON file which hold the mapping information between ngspice and Modelica. + with open(map_json) as mappingFile: + self.mappingData = json.load(mappingFile) + + self.ifMOS = False + self.sourceDetail = [] + self.deviceDetail = [] + self.subCktDetail = [] + self.deviceList = ['d','D','j','J','q','Q','m','M'] + self.sourceList = ['v','V','i','I'] + + + + + + def readNetlist(self,filename): + """ + Read Ngspice Netlist + """ + netlist = [] + if os.path.exists(filename): + try: + f = open(filename) + except Exception as e: + print("Error in opening file") + print(str(e)) + sys.exit() + else: + print filename + " does not exist" + sys.exit() + + data = f.read() + data = data.splitlines() + f.close() + for eachline in data: + eachline=eachline.strip() + if len(eachline)>1: + if eachline[0]=='+': + netlist.append(netlist.pop()+eachline.replace('+',' ',1)) + else: + netlist.append(eachline) + + return netlist + + def separateNetlistInfo(self,netlist): + """ + Separate schematic data and option data + """ + optionInfo = [] + schematicInfo = [] + + + + for eachline in netlist: + + if len(eachline) > 1: + if eachline[0]=='*': + continue + elif eachline[0]=='.': + optionInfo.append(eachline) + #optionInfo.append(eachline.lower()) + elif eachline[0] in self.deviceList: + if eachline[0]=='m' or eachline[0]=='M': + self.ifMOS = True + schematicInfo.append(eachline) + self.deviceDetail.append(eachline) + elif eachline[0]=='x' or eachline[0]=='X': + schematicInfo.append(eachline) + self.subCktDetail.append(eachline) + elif eachline[0] in self.sourceList: + schematicInfo.append(eachline) + self.sourceDetail.append(eachline) + elif eachline[0]=='a' or eachline[0]=='A': + schematicInfo.append(eachline) + else: + schematicInfo.append(eachline) + ##No need of making it lower case as netlist is already converted to ngspice + #schematicInfo.append(eachline.lower()) + + + return optionInfo,schematicInfo + + def addModel(self,optionInfo): + """ + Add model parameters in the modelica file and create dictionary of model parameters + This function extract model and subckt information along with their parameters with the help of optionInfo + """ + modelName = [] + modelInfo = {} + subcktName = [] + paramInfo = [] + transInfo = {} + inbuiltModelDict = {} + + for eachline in optionInfo: + words = eachline.split() + if words[0] == '.include': + name = words[1].split('.') + if name[1] == 'lib': + modelName.append(name[0]) + if name[1] == 'sub': + subcktName.append(name[0]) + elif words[0] == '.param': + paramInfo.append(eachline) + elif words[0] == '.model': + model = words[1] + modelInfo[model] = {} + eachline = eachline.replace(' = ','=').replace('= ','=').replace(' =','=') + eachline = eachline.split('(') + templine = eachline[0].split() + trans = templine[1] + transInfo[trans] = [] + templine[2] = templine[2].lower() + if templine[2] in ['npn', 'pnp', 'pmos', 'nmos','njf','pjf']: + transInfo[trans] = templine[2] + else: + inbuiltModelDict[model]=templine[2] + eachline[1] = eachline[1].lower() + eachline = eachline[1].split() + for eachitem in eachline: + if len(eachitem) > 1: + eachitem = eachitem.replace(')','') + iteminfo = eachitem.split('=') + for each in iteminfo: + modelInfo[model][iteminfo[0]] = iteminfo[1] + + #Adding details of model(external) and subckt into modelInfo and subcktInfo + for eachmodel in modelName: + filename = eachmodel + '.lib' + if os.path.exists(filename): + try: + f = open(filename) + except: + print("Error in opening file") + sys.exit() + else: + print filename + " does not exist" + sys.exit() + data = f.read() + data = data.replace('+', '').replace('\n','').replace(' = ','=').replace('= ','=').replace(' =','=') + #data = data.lower() #Won't work if Reference model name is Upper Case + newdata = data.split('(') + templine_f = newdata[0].split() + trans_f = templine_f[1] + transInfo[trans_f] = [] + templine_f[2] = templine_f[2].lower() + if templine_f[2] in ['npn', 'pnp', 'pmos', 'nmos','njf','pjf']: + transInfo[trans_f] = templine_f[2] + + refModelName = trans_f + newdata[1] = newdata[1].lower() + modelParameter = newdata[1].split() + + modelInfo[refModelName] = {} + + for eachline in modelParameter: + if len(eachline) > 1: + eachline = eachline.replace(')','') + info = eachline.split('=') + for eachitem in info: + modelInfo[refModelName][info[0]] = info[1] + f.close() + + + + + return modelName, modelInfo, subcktName, paramInfo ,transInfo,inbuiltModelDict + + def processParam(self,paramInfo): + """ + Process parameter info and update in Modelica syntax + """ + modelicaParam = [] + for eachline in paramInfo: + eachline = eachline.split('.param') + #Include ',' in between parameter + #Removing leading and trailing space + line = eachline[1].strip() + line = line.split() + final_line = ','.join(line) + stat = 'parameter Real ' + final_line + ';' + stat = stat.translate(maketrans('{}', ' ')) + modelicaParam.append(stat) + return modelicaParam + + + def separatePlot(self,schematicInfo): + """ + separate print plot and component statements + """ + compInfo = [] + plotInfo = [] + for eachline in schematicInfo: + words = eachline.split() + if words[0] == 'run': + continue + elif words[0] == 'plot' or words[0] == 'print': + plotInfo.append(eachline) + else: + compInfo.append(eachline) + return compInfo, plotInfo + + def separateSource(self,compInfo): + """ + Find if dependent sources are present in the schematic and if so make a dictionary with source details + """ + sourceInfo = {} + source = [] + for eachline in compInfo: + words = eachline.split() ##This line need to be confirmed with Manas + if eachline[0] in ['f', 'h']: + source.append(words[3]) + if len(source) > 0: + for eachline in compInfo: + words_s = eachline.split() + if words_s[0] in source: + sourceInfo[words_s[0]] = words_s[1:3] + return sourceInfo + + def getUnitVal(self,compValue): + #regExp = re.compile("([0-9]+)([a-zA-Z]+)") + #Remove '(' and ')' if any + compValue = compValue.replace('(','').replace(')','') + compValue = compValue.lower() + #regExp = re.compile("([-])?([0-9]+)\.?([0-9]+)?([a-zA-Z])?") + regExp = re.compile("([-])?([0-9]+)\.?([0-9]+)?(\w+)?") + matchString = regExp.match(str(compValue)) #separating number and string + try: + signVal = matchString.group(1) + valBeforeDecimal = matchString.group(2) + valAfterDecimal = matchString.group(3) + unitValue = matchString.group(4) + modifiedcompValue = "" + if str(signVal)=='None': + pass + else: + modifiedcompValue += signVal + + modifiedcompValue += valBeforeDecimal + + if str(valAfterDecimal)=='None': + pass + else: + modifiedcompValue += '.'+valAfterDecimal + + if str(unitValue)=='None': + pass + else: + modifiedcompValue += self.mappingData["Units"][unitValue] + + return modifiedcompValue + except: + return compValue + + + def compInit(self,compInfo, node, modelInfo, subcktName,dir_name,transInfo,inbuiltModelDict): + """ + For each component in the netlist initialize it according to Modelica format + """ + #print "CompInfo inside compInit function : compInit------->",compInfo + #### initial processing to check if MOs is present. If so, library to be used is BondLib + modelicaCompInit = [] + numNodesSub = {} + mosInfo = {} + IfMOS = '0' + + for eachline in compInfo: + #words = eachline.split() + if eachline[0] == 'm': + IfMOS = '1' + break + if len(subcktName) > 0: + subOptionInfo = [] + subSchemInfo = [] + for eachsub in subcktName: + filename_tem = eachsub + '.sub' + filename_tem = os.path.join(dir_name, filename_tem) + data = self.readNetlist(filename_tem) + subOptionInfo, subSchemInfo = self.separateNetlistInfo(data) + + for eachline in subSchemInfo: + #words = eachline.split() + if eachline[0] == 'm': + IfMOS = '1' + break + + #Lets Start with Source details + for eachline in self.sourceDetail: + words = eachline.split() + #Preserve component name from lower case function + compName = words[0] + #Now Lower case all other + words = eachline.lower().split() + words[0] = compName + typ = words[3].split('(') + + sourceType = compName[0].lower() + + if sourceType == 'v': + if typ[0] == "pulse": + per = words[9].split(')') + stat = self.mappingData["Sources"][sourceType][typ[0]]+' '+compName+'(rising = '+self.getUnitVal(words[6])+', V = '+self.getUnitVal(words[4])\ + +', width = '+self.getUnitVal(words[8])+', period = '+self.getUnitVal(per[0])+', offset = '+self.getUnitVal(typ[1])+', startTime = '+self.getUnitVal(words[5])+', falling = '+self.getUnitVal(words[7])+');' + modelicaCompInit.append(stat) + if typ[0] == "sine": + theta = words[7].split(')') + stat = self.mappingData["Sources"][sourceType][typ[0]]+' '+compName+'(offset = '+self.getUnitVal(typ[1])+', V = '+self.getUnitVal(words[4])+', freqHz = '+self.getUnitVal(words[5])+', startTime = '+self.getUnitVal(words[6])+', phase = '+self.getUnitVal(theta[0])+');' + modelicaCompInit.append(stat) + if typ[0] == "pwl": + keyw = self.mappingData["Sources"][sourceType][typ[0]]+' ' + stat = keyw + compName + '(table = [' + self.getUnitVal(typ[1]) + ',' + self.getUnitVal(words[4]) + ';' + length = len(words); + for i in range(6,length,2): + if i == length-2: + w = words[i].split(')') + stat = stat + self.getUnitVal(words[i-1]) + ',' + self.getUnitVal(w[0]) + else: + stat = stat + self.getUnitVal(words[i-1]) + ',' + self.getUnitVal(words[i]) + ';' + stat = stat + ']);' + modelicaCompInit.append(stat) + if typ[0] == words[3] and typ[0] != "dc": + #It is DC constant but no dc keyword + val_temp = typ[0].split('v') + stat = self.mappingData["Sources"][sourceType]["dc"]+' ' + compName + '(V = ' + self.getUnitVal(val_temp[0]) + ');' + modelicaCompInit.append(stat) + elif typ[0] == words[3] and typ[0] == "dc": + stat = self.mappingData["Sources"][sourceType][typ[0]]+' ' + compName + '(V = ' + self.getUnitVal(words[4]) + ');' ### check this + modelicaCompInit.append(stat) + + elif sourceType=='i': + stat = self.mappingData["Sources"][sourceType]["dc"]+' '+compName+'(I='+self.getUnitVal(words[3])+');' + modelicaCompInit.append(stat) + + #Now empty the source list as it may be used by subcircuit + self.sourceDetail[:] = [] + + #print "Source Detail after processing-------->",self.sourceDetail + + #Lets start for device + for eachline in self.deviceDetail: + words=eachline.split() + deviceName = eachline[0].lower() + if deviceName=='d': + if len(words)>3: + if modelInfo[words[3]].has_key('n'): + n = float(modelInfo[words[3]]['n']) + else: + n = 1.0 + vt = str(float(0.025*n)) + #stat = self.mappingData["Devices"][deviceName]["import"]+' '+ words[0] + '(Ids = ' + modelInfo[words[3]]['is'] + ', Vt = ' + vt + ', R = 1e12' +');' + start = self.mappingData["Devices"][deviceName]["import"] + stat = start+" "+words[0]+"(" + tempstatList=[] + userDeviceParamList=[] + refName = words[-1] + for key in modelInfo[refName]: + #If parameter is not mapped then it will just pass + try: + actualModelicaParam = self.mappingData["Devices"][deviceName]["mapping"][key] + tempstatList.append(actualModelicaParam+"="+self.getUnitVal(modelInfo[refName][key])+" ") + userDeviceParamList.append(str(actualModelicaParam)) + except: + pass + #Adding Vt and R + userDeviceParamList.append("Vt") + tempstatList.append("Vt="+vt) + #Running loop over default parameter of OpenModelica + for default in self.mappingData["Devices"][deviceName]["default"]: + if default in userDeviceParamList: + continue + else: + defaultValue = self.mappingData["Devices"][deviceName]["default"][default] + tempstatList.append(default+"="+self.getUnitVal(defaultValue)+" ") + + stat += ",".join(str(item) for item in tempstatList)+");" + + else: + stat = self.mappingData["Devices"][deviceName]["import"]+" "+ words[0] +";" + modelicaCompInit.append(stat) + + elif deviceName=='q': + trans = transInfo[words[4]] + if trans == 'npn': + start = self.mappingData["Devices"][deviceName]["import"]+".NPN" + elif trans == 'pnp': + start = self.mappingData["Devices"][deviceName]["import"]+".PNP" + else: + print "Transistor "+str(trans)+" Not found" + sys.exit(1) + + stat = start+" "+words[0]+"(" + tempstatList=[] + userDeviceParamList=[] + refName = words[4] + for key in modelInfo[refName]: + #If parameter is not mapped then it will just pass + try: + if key=="vaf": + inv_vak = float(self.getUnitVal(modelInfo[refName][key])) + vak_temp = 1/inv_vak + vak = str(vak_temp) + tempstatList.append("Vak="+vak+" ") + userDeviceParamList.append(str("Vak")) + else: + actualModelicaParam = self.mappingData["Devices"][deviceName]["mapping"][key] + tempstatList.append(actualModelicaParam+"="+self.getUnitVal(modelInfo[refName][key])+" ") + userDeviceParamList.append(str(actualModelicaParam)) + except: + pass + #Running loop over default parameter of OpenModelica + for default in self.mappingData["Devices"][deviceName]["default"]: + if default in userDeviceParamList: + continue + else: + defaultValue = self.mappingData["Devices"][deviceName]["default"][default] + tempstatList.append(default+"="+self.getUnitVal(defaultValue)+" ") + + stat += ",".join(str(item) for item in tempstatList)+");" + modelicaCompInit.append(stat) + + elif deviceName=='m': + eachline = eachline.split(words[5]) + eachline = eachline[1] + eachline = eachline.strip() + eachline = eachline.replace(' = ', '=').replace('= ','=').replace(' =','=').replace(' * ', '*').replace(' + ', '+').replace(' { ', '').replace(' } ', '') + eachline = eachline.split() + mosInfo[words[0]] = {} + for each in eachline: + if len(each) > 1: + each = each.split('=') + mosInfo[words[0]][each[0]] = each[1] + trans = transInfo[words[5]] + + if trans == 'nmos': + start = self.mappingData["Devices"][deviceName]["import"]+".Mn" + elif trans=='pmos' : + start = self.mappingData["Devices"][deviceName]["import"]+".Mp" + else: + print "MOSFET "+str(trans)+" not found" + sys.exit(1) + + + stat = start+" "+words[0]+"(" + tempstatList=[] + userDeviceParamList=[] + refName = words[5] + + for key in modelInfo[refName]: + #If parameter is not mapped then it will just pass + try: + if key=="uo": + U0 = str(float(self.getUnitVal(modelInfo[refName][key]))*0.0001) + tempstatList.append("U0="+U0+" ") + userDeviceParamList.append(str("U0")) + else: + actualModelicaParam = self.mappingData["Devices"][deviceName]["mapping"][key] + tempstatList.append(actualModelicaParam+"="+self.getUnitVal(modelInfo[refName][key])+" ") + userDeviceParamList.append(str(actualModelicaParam)) + except Exception as err: + print str(err) + + #Running loop over default parameter of OpenModelica + for default in self.mappingData["Devices"][deviceName]["default"]: + if default in userDeviceParamList: + continue + else: + defaultValue = self.mappingData["Devices"][deviceName]["default"][default] + tempstatList.append(default+"="+self.getUnitVal(defaultValue)+" ") + + + #Adding LEVEL(This is constant not the device level) + tempstatList.append("Level=1"+" ") + + try: + l = mosInfo[words[0]]['l'] + tempstatList.append("L="+self.getUnitVal(l)+" ") + except KeyError: + tempstatList.append("L=1e-6"+" ") + try: + w = mosInfo[words[0]]['w'] + tempstatList.append("W="+self.getUnitVal(w)+" ") + except KeyError: + tempstatList.append("W=100e-6"+" ") + try: + As = mosInfo[words[0]]['as'] + ad = mosInfo[words[0]]['ad'] + tempstatList.append("AS="+self.getUnitVal(As)+" ") + tempstatList.append("AD="+self.getUnitVal(ad)+" ") + except KeyError: + tempstatList.append("AS=0"+" ") + tempstatList.append("AD=0"+" ") + try: + ps = mosInfo[words[0]]['ps'] + pd = mosInfo[words[0]]['pd'] + tempstatList.append("PS="+self.getUnitVal(ps)+" ") + tempstatList.append("PD="+self.getUnitVal(pd)+" ") + except KeyError: + tempstatList.append("PS=0"+" ") + tempstatList.append("PD=0"+" ") + + stat += ",".join(str(item) for item in tempstatList)+");" + modelicaCompInit.append(stat) + + elif deviceName=='j': + trans = transInfo[words[4]] + """ + if trans == 'njf': + start = self.mappingData["Devices"][deviceName]["import"]+".J_NJFJFET" + elif trans == 'pjf': + start = self.mappingData["Devices"][deviceName]["import"]+".J_PJFJFET" + else: + print "JFET "+str(trans)+" Not found" + sys.exit(1) + """ + start = self.mappingData["Devices"][deviceName]["import"] + + stat = start+" "+words[0]+"(modelcard(" + tempstatList=[] + userDeviceParamList=[] + refName = words[4] + for key in modelInfo[refName]: + #If parameter is not mapped then it will just pass + try: + actualModelicaParam = self.mappingData["Devices"][deviceName]["mapping"][key] + tempstatList.append(actualModelicaParam+"="+self.getUnitVal(modelInfo[refName][key])+" ") + userDeviceParamList.append(str(actualModelicaParam)) + except: + pass + #Running loop over default parameter of OpenModelica + for default in self.mappingData["Devices"][deviceName]["default"]: + if default in userDeviceParamList: + continue + else: + defaultValue = self.mappingData["Devices"][deviceName]["default"][default] + tempstatList.append(default+"="+self.getUnitVal(defaultValue)+" ") + + stat += ",".join(str(item) for item in tempstatList)+"));" + modelicaCompInit.append(stat) + + + + #Empty device details as well + self.deviceDetail[:]=[] + + #Lets start for Subcircuit + for eachline in self.subCktDetail: + global point + global subname + temp_line = eachline.split() + temp = temp_line[0].split('x') + index = temp[1] + for i in range(0,len(temp_line),1): + if temp_line[i] in subcktName: + subname = temp_line[i] + numNodesSub[subname] = i - 1 + point = i + if len(temp_line) > point + 1: + rem = temp_line[point+1:len(temp_line)] + rem_new = ','.join(rem) + stat = subname + ' ' + subname +'_instance' + index + '(' + rem_new + ');' + else: + stat = subname + ' ' + subname +'_instance' + index + ';' + modelicaCompInit.append(stat) + + #Empty Sub Circuit Detail + self.subCktDetail[:] = [] + + #Lets start for inbuilt model of ngspice + for eachline in compInfo: + words=eachline.split() + value = self.getUnitVal(words[-1]) + if eachline[0] == 'a' or eachline[0] == 'A': + userModelParamList = [] + refName = words[-1] + actualModelName = inbuiltModelDict[refName] + + start = self.mappingData["Models"][actualModelName]["import"] + stat = start +" "+ words[0]+"(" + tempstatList=[] + + for key in modelInfo[refName]: + #If parameter is not mapped then it will just pass + try: + actualModelicaParam = self.mappingData["Models"][actualModelName]["mapping"][key] + tempstatList.append(actualModelicaParam+"="+self.getUnitVal(modelInfo[refName][key])+" ") + userModelParamList.append(str(actualModelicaParam)) + except: + pass + + #Running loop over default parameter of OpenModelica + for default in self.mappingData["Models"][actualModelName]["default"]: + if default in userModelParamList: + continue + else: + defaultValue = self.mappingData["Models"][actualModelName]["default"][default] + tempstatList.append(default+"="+self.getUnitVal(defaultValue)+" ") + + stat += ",".join(str(item) for item in tempstatList)+");" + modelicaCompInit.append(stat) + + elif eachline[0] == 'r': + stat = 'Analog.Basic.Resistor ' + words[0] + '(R = ' + value + ');' + modelicaCompInit.append(stat) + elif eachline[0] == 'c': + stat = 'Analog.Basic.Capacitor ' + words[0] + '(C = ' + value + ');' + modelicaCompInit.append(stat) + elif eachline[0] == 'l': + stat = 'Analog.Basic.Inductor ' + words[0] + '(L = ' + value + ');' + modelicaCompInit.append(stat) + elif eachline[0] == 'e': + stat = 'Analog.Basic.VCV ' + words[0] + '(gain = ' + self.getUnitVal(words[5]) + ');' + modelicaCompInit.append(stat) + elif eachline[0] == 'g': + stat = 'Analog.Basic.VCC ' + words[0] + '(transConductance = ' + self.getUnitVal(words[5]) + ');' + modelicaCompInit.append(stat) + elif eachline[0] == 'f': + stat = 'Analog.Basic.CCC ' + words[0] + '(gain = ' + self.getUnitVal(words[4]) + ');' + modelicaCompInit.append(stat) + elif eachline[0] == 'h': + stat = 'Analog.Basic.CCV ' + words[0] + '(transResistance = ' + self.getUnitVal(words[4]) + ');' + modelicaCompInit.append(stat) + else: + continue + + + if '0' or 'gnd' in node: + modelicaCompInit.append('Analog.Basic.Ground g;') + return modelicaCompInit, numNodesSub + + def getSubInterface(self,subname,numNodesSub): + """ + Get the list of nodes for subcircuit in .subckt line + """ + subOptionInfo_p = [] + subSchemInfo_p = [] + filename_t = subname + '.sub' + data_p = self.readNetlist(filename_t) + subOptionInfo_p, subSchemInfo_p = self.separateNetlistInfo(data_p) + if len(subOptionInfo_p) > 0: + newline = subOptionInfo_p[0] + newline = newline.split('.subckt '+ subname) + intLine = newline[1].split() + newindex = numNodesSub[subname] + nodesInfoLine = intLine[0:newindex] + return nodesInfoLine + + def getSubParamLine(self,subname, numNodesSub, subParamInfo,dir_name): + """ + Take subcircuit name and give the info related to parameters in the first line and initialize it in + """ + #nodeSubInterface = [] + subOptionInfo_p = [] + subSchemInfo_p = [] + filename_t = subname + '.sub' + filename_t = os.path.join(dir_name, filename_t) + data_p = self.readNetlist(filename_t) + subOptionInfo_p, subSchemInfo_p = self.separateNetlistInfo(data_p) + + if len(subOptionInfo_p) > 0: + newline = subOptionInfo_p[0] + newline = newline.split('.subckt '+ subname) + intLine = newline[1].split() + newindex = numNodesSub[subname] + appen_line = intLine[newindex:len(intLine)] + appen_param = ','.join(appen_line) + paramLine = 'parameter Real ' + appen_param + ';' + paramLine = paramLine.translate(maketrans('{}', ' ')) + subParamInfo.append(paramLine) + return subParamInfo + + def nodeSeparate(self,compInfo, ifSub, subname, subcktName,numNodesSub): + """ + separate the node numbers and create nodes in modelica file; + the nodes in the subckt line should not be inside protected keyword. pinInit is the one that goes under protected keyword. + """ + node = [] + nodeTemp = [] + nodeDic = {} + pinInit = 'Modelica.Electrical.Analog.Interfaces.Pin ' + pinProtectedInit = 'Modelica.Electrical.Analog.Interfaces.Pin ' + protectedNode = [] + #print "CompInfo coming to nodeSeparate function: compInfo",compInfo + + #Removing '[' and ']' from compInfo for Digital node + for i in range(0,len(compInfo),1): + compInfo[i] = compInfo[i].replace("[","").replace("]","") + + + for eachline in compInfo: + words = eachline.split() + + if eachline[0] in ['m', 'e', 'g', 't','M','E','G','T']: + nodeTemp.append(words[1]) + nodeTemp.append(words[2]) + nodeTemp.append(words[3]) + nodeTemp.append(words[4]) + elif eachline[0] in ['q', 'j','J','Q']: + nodeTemp.append(words[1]) + nodeTemp.append(words[2]) + nodeTemp.append(words[3]) + elif eachline[0]=='x' or eachline[0]=='X': + templine = eachline.split() + for i in range(0,len(templine),1): + if templine[i] in subcktName: + point = i + #print "Added in node----->",words[1:point] + nodeTemp.extend(words[1:point]) + else: + nodeTemp.append(words[1]) + nodeTemp.append(words[2]) + + + + #Replace hyphen '-' from node + for i in nodeTemp: + if i not in node: + i = i.replace("-","") + node.append(i) + + + for i in range(0, len(node),1): + nodeDic[node[i]] = 'n' + node[i] + if ifSub == '0': + if i != len(node)-1: + pinInit = pinInit + nodeDic[node[i]] + ', ' + else: + pinInit = pinInit + nodeDic[node[i]] + else: + nonprotectedNode = self.getSubInterface(subname, numNodesSub) + if node[i] in nonprotectedNode: + continue + else: + protectedNode.append(node[i]) + if ifSub == '1': + if len(nonprotectedNode) > 0: + for i in range(0, len(nonprotectedNode),1): + if i != len(nonprotectedNode)-1: + pinProtectedInit = pinProtectedInit + nodeDic[nonprotectedNode[i]] + ',' + else: + pinProtectedInit = pinProtectedInit + nodeDic[nonprotectedNode[i]] + if len(protectedNode) > 0: + for i in range(0, len(protectedNode),1): + if i != len(protectedNode)-1: + pinInit = pinInit + nodeDic[protectedNode[i]] + ',' + else: + pinInit = pinInit + nodeDic[protectedNode[i]] + pinInit = pinInit + ';' + pinProtectedInit = pinProtectedInit + ';' + #print "Node---->",node + #print "nodeDic----->",nodeDic + #print "PinInit----->",pinInit + #print "pinProtectedinit--->",pinProtectedInit + return node, nodeDic, pinInit, pinProtectedInit + + + def connectInfo(self,compInfo, node, nodeDic, numNodesSub,subcktName): + """ + Make node connections in the modelica netlist + """ + connInfo = [] + sourcesInfo = self.separateSource(compInfo) + for eachline in compInfo: + words = eachline.split() + + #Remove '-' from compInfo + for i in range(0,len(words),1): + words[i] = words[i].replace("-","") + + if eachline[0]=='r' or eachline[0]=='R' or eachline[0]=='c' or eachline[0]=='C' or eachline[0]=='d' or eachline[0]=='D' \ + or eachline[0]=='l' or eachline[0]=='L' or eachline[0]=='v' or eachline[0]=='V' or eachline[0]=='i' or eachline[0]=='I': + conn = 'connect(' + words[0] + '.p,' + nodeDic[words[1]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.n,' + nodeDic[words[2]] + ');' + connInfo.append(conn) + elif eachline[0]=='q' or eachline[0]=='Q': + conn = 'connect(' + words[0] + '.C,' + nodeDic[words[1]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.B,' + nodeDic[words[2]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.E,' + nodeDic[words[3]] + ');' + connInfo.append(conn) + elif eachline[0]=='j' or eachline[0]=='J': + conn = 'connect('+words[0]+'.D,' + nodeDic[words[1]]+');' + connInfo.append(conn) + conn = 'connect('+words[0]+'.G,' + nodeDic[words[2]]+');' + connInfo.append(conn) + conn = 'connect('+words[0]+'.S,' + nodeDic[words[3]]+');' + connInfo.append(conn) + elif eachline[0]=='m' or eachline[0]=='M': + conn = 'connect(' + words[0] + '.D,' + nodeDic[words[1]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.G,' + nodeDic[words[2]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.S,' + nodeDic[words[3]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.B,' + nodeDic[words[4]] + ');' + connInfo.append(conn) + elif eachline[0] in ['f','h','F','H']: + vsource = words[3] + sourceNodes = sourcesInfo[vsource] + #print "Source Nodes------>",sourceNodes + #print "Source Info------->",sourcesInfo + #sourceNodes = sourceNodes.split() #No need to split as it is in the form of list + conn = 'connect(' + words[0] + '.p1,'+ nodeDic[sourceNodes[0]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.n1,'+ nodeDic[sourceNodes[1]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.p2,'+ nodeDic[words[1]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.n2,'+ nodeDic[words[2]] + ');' + connInfo.append(conn) + elif eachline[0] in ['g','e','G','E']: + conn = 'connect(' + words[0] + '.p1,'+ nodeDic[words[3]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.n1,'+ nodeDic[words[4]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.p2,'+ nodeDic[words[1]] + ');' + connInfo.append(conn) + conn = 'connect(' + words[0] + '.n2,'+ nodeDic[words[2]] + ');' + connInfo.append(conn) + elif eachline[0]=='x' or eachline[0]=='X': + templine = eachline.split() + temp = templine[0].split('x') + index = temp[1] + for i in range(0,len(templine),1): + if templine[i] in subcktName: + subname = templine[i] + nodeNumInfo = self.getSubInterface(subname, numNodesSub) + for i in range(0, numNodesSub[subname], 1): + conn = 'connect(' + subname + '_instance' + index + '.' + 'n'+ nodeNumInfo[i] + ',' + nodeDic[words[i+1]] + ');' + connInfo.append(conn) + else: + continue + if '0' in node: + conn = 'connect(g.p,n0);' + connInfo.append(conn) + elif 'gnd' in node: + conn = 'connect(g.p,ngnd);' + connInfo.append(conn) + + + + + return connInfo + + + def procesSubckt(self,subcktName,numNodesSub,dir_name): + + #Process the subcircuit file .sub in the project folder + + #subcktDic = {} + subOptionInfo = [] + subSchemInfo = [] + subModel = [] + subModelInfo = {} + subsubName = [] + subParamInfo = [] + nodeSubInterface = [] + nodeSub = [] + nodeDicSub = {} + pinInitsub = [] + connSubInfo = [] + if len(subcktName) > 0: + for eachsub in subcktName: + filename = eachsub + '.sub' + basename = filename + filename = os.path.join(dir_name, filename) + data = self.readNetlist(filename) + #print "Data-------------------->",data + subOptionInfo, subSchemInfo = self.separateNetlistInfo(data) + #print "SubOptionInfo------------------->",subOptionInfo + #print "SubSchemInfo-------------------->",subSchemInfo + if len(subOptionInfo) > 0: + newline = subOptionInfo[0] + subInitLine = newline + newline = newline.split('.subckt') + intLine = newline[1].split() + for i in range(0,len(intLine),1): + nodeSubInterface.append(intLine[i]) + + subModel, subModelInfo, subsubName, subParamInfo,subtransInfo,subInbuiltModelDict = self.addModel(subOptionInfo) + #print "Sub Model------------------------------------>",subModel + #print "SubModelInfo---------------------------------->",subModelInfo + #print "subsubName------------------------------------->",subsubName + #print "subParamInfo----------------------------------->",subParamInfo + #print "subtransInfo----------------------------------->",subtransInfo + #print "subInbuiltModel----------------------------------->",subInbuiltModelDict + + IfMOSsub = '0' + for eachline in subSchemInfo: + #words = eachline.split() + if eachline[0] == 'm': + IfMOSsub = '1' + break + subsubOptionInfo = [] + subsubSchemInfo = [] + if len(subsubName) > 0: + #subsubOptionInfo = [] + #subsubSchemInfo = [] + for eachsub in subsubName: + filename_st = eachsub + '.sub' + filename_stemp = os.path.join(dir_name, filename_st) + data = self.readNetlist(filename_stemp) + subsubOptionInfo, subsubSchemInfo = self.separateNetlistInfo(data) + for eachline in subsubSchemInfo: + #words = eachline.split() + if eachline[0] == 'm': + IfMOSsub = '1' + break + #print "subsubOptionInfo-------------------------->",subsubOptionInfo + #print "subsubSchemInfo-------------------------->",subsubSchemInfo + + modelicaSubParam = self.processParam(subParamInfo) + #print "modelicaSubParam------------------->",modelicaSubParam + nodeSub, nodeDicSub, pinInitSub, pinProtectedInitSub = self.nodeSeparate(subSchemInfo, '1', eachsub, subsubName,numNodesSub) + #print "NodeSub------------------------->",nodeSub + #print "NodeDicSub-------------------------->",nodeDicSub + #print "PinInitSub-------------------------->",pinInitSub + #print "PinProtectedInitSub------------------->",pinProtectedInitSub + modelicaSubCompInit, numNodesSubsub = self.compInit(subSchemInfo, nodeSub, subModelInfo, subsubName,dir_name,subtransInfo,subInbuiltModelDict) + #print "modelicaSubCompInit--------------------->",modelicaSubCompInit + #print "numNodesSubsub-------------------------->",numNodesSubsub + modelicaSubParamNew = self.getSubParamLine(eachsub, numNodesSub, modelicaSubParam,dir_name) ###Ask Manas + #print "modelicaSubParamNew----------------->",modelicaSubParamNew + connSubInfo = self.connectInfo(subSchemInfo, nodeSub, nodeDicSub, numNodesSubsub,subcktName) + #print "connSubInfo----------------->",connSubInfo + newname = basename.split('.') + newfilename = newname[0] + outfilename = newfilename+ ".mo" + outfilename = os.path.join(dir_name, outfilename) + out = open(outfilename,"w") + out.writelines('model ' + newfilename) + out.writelines('\n') + if IfMOSsub == '0': + out.writelines('import Modelica.Electrical.*;') + elif IfMOSsub == '1': + out.writelines('import BondLib.Electrical.*;') + out.writelines('\n') + for eachline in modelicaSubParamNew: + if len(subParamInfo) == 0: + continue + else: + out.writelines(eachline) + out.writelines('\n') + for eachline in modelicaSubCompInit: + if len(subSchemInfo) == 0: + continue + else: + out.writelines(eachline) + out.writelines('\n') + + out.writelines(pinProtectedInitSub) + out.writelines('\n') + if pinInitSub != 'Modelica.Electrical.Analog.Interfaces.Pin ;': + out.writelines('protected') + out.writelines('\n') + out.writelines(pinInitSub) + out.writelines('\n') + out.writelines('equation') + out.writelines('\n') + for eachline in connSubInfo: + if len(connSubInfo) == 0: + continue + else: + out.writelines(eachline) + out.writelines('\n') + out.writelines('end '+ newfilename + ';') + out.writelines('\n') + out.close() + + return data, subOptionInfo, subSchemInfo, subModel, subModelInfo, subsubName, \ + subParamInfo, modelicaSubCompInit, modelicaSubParam, nodeSubInterface, nodeSub, nodeDicSub, pinInitSub, connSubInfo + + + +def main(args): + """ + It is main function of module Ngspice to Modelica converter + """ + if len(sys.argv) == 3: + filename = sys.argv[1] + map_json = sys.argv[2] + else: + print "USAGE:" + print "python NgspicetoModelica.py <filename>" + sys.exit() + + dir_name = os.path.dirname(os.path.realpath(filename)) + file_basename = os.path.basename(filename) + + cwd = os.getcwd() + os.chdir(dir_name) + + obj_NgMoConverter = NgMoConverter(map_json) + + #Getting all the require information + lines = obj_NgMoConverter.readNetlist(filename) + #print "Complete Lines of Ngspice netlist :lines ---------------->",lines + optionInfo, schematicInfo = obj_NgMoConverter.separateNetlistInfo(lines) + #print "All option details like analysis,subckt,.ic,.model : OptionInfo------------------->",optionInfo + #print "Schematic connection info :schematicInfo",schematicInfo + modelName, modelInfo, subcktName, paramInfo,transInfo,inbuiltModelDict = obj_NgMoConverter.addModel(optionInfo) + #print "Name of Model : modelName-------------------->",modelName + #print "Model Information :modelInfo--------------------->",modelInfo + #print "Subcircuit Name :subcktName------------------------>",subcktName + #print "Parameter Information :paramInfo---------------------->",paramInfo + #print "InBuilt Model ---------------------->",inbuiltModelDict + + + + modelicaParamInit = obj_NgMoConverter.processParam(paramInfo) + #print "Make modelicaParamInit from paramInfo : processParamInit------------->",modelicaParamInit + compInfo, plotInfo = obj_NgMoConverter.separatePlot(schematicInfo) + #print "Plot info like plot,print etc :plotInfo",plotInfo + IfMOS = '0' + + for eachline in compInfo: + words = eachline.split() + if eachline[0] == 'm': + IfMOS = '1' + break + + subOptionInfo = [] + subSchemInfo = [] + if len(subcktName) > 0: + #subOptionInfo = [] + #subSchemInfo = [] + for eachsub in subcktName: + filename_temp = eachsub + '.sub' + data = obj_NgMoConverter.readNetlist(filename_temp) + #print "Data---------->",data + subOptionInfo, subSchemInfo = obj_NgMoConverter.separateNetlistInfo(data) + for eachline in subSchemInfo: + words = eachline.split() + if eachline[0] == 'm': + IfMOS = '1' + break + #print "Subcircuit OptionInfo : subOptionInfo------------------->",subOptionInfo + #print "Subcircuit Schematic Info :subSchemInfo-------------------->",subSchemInfo + + node, nodeDic, pinInit, pinProtectedInit = obj_NgMoConverter.nodeSeparate(compInfo, '0', [], subcktName,[]) + #print "All nodes in the netlist :node---------------->",node + #print "NodeDic which will be used for modelica : nodeDic------------->",nodeDic + #print "PinInit-------------->",pinInit + #print "pinProtectedInit----------->",pinProtectedInit + + modelicaCompInit, numNodesSub = obj_NgMoConverter.compInit(compInfo,node, modelInfo, subcktName,dir_name,transInfo,inbuiltModelDict) + #print "ModelicaComponents : modelicaCompInit----------->",modelicaCompInit + #print "SubcktNumNodes : numNodesSub---------------->",numNodesSub + + connInfo = obj_NgMoConverter.connectInfo(compInfo, node, nodeDic, numNodesSub,subcktName) + + #print "ConnInfo------------------>",connInfo + + + ###After Sub Ckt Func + if len(subcktName) > 0: + data, subOptionInfo, subSchemInfo, subModel, subModelInfo, subsubName,subParamInfo, modelicaSubCompInit, modelicaSubParam,\ + nodeSubInterface,nodeSub, nodeDicSub, pinInitSub, connSubInfo = obj_NgMoConverter.procesSubckt(subcktName,numNodesSub,dir_name) #Adding 'numNodesSub' by Fahim + + #Creating Final Output file + newfile = filename.split('.') + newfilename = newfile[0] + outfile = newfilename + ".mo" + out = open(outfile,"w") + out.writelines('model ' + os.path.basename(newfilename)) + out.writelines('\n') + if IfMOS == '0': + out.writelines('import Modelica.Electrical.*;') + elif IfMOS == '1': + out.writelines('import BondLib.Electrical.*;') + #out.writelines('import Modelica.Electrical.*;') + out.writelines('\n') + + for eachline in modelicaParamInit: + if len(paramInfo) == 0: + continue + else: + out.writelines(eachline) + out.writelines('\n') + for eachline in modelicaCompInit: + if len(compInfo) == 0: + continue + else: + out.writelines(eachline) + out.writelines('\n') + + out.writelines('protected') + out.writelines('\n') + out.writelines(pinInit) + out.writelines('\n') + out.writelines('equation') + out.writelines('\n') + + for eachline in connInfo: + if len(connInfo) == 0: + continue + else: + out.writelines(eachline) + out.writelines('\n') + + out.writelines('end '+ os.path.basename(newfilename) + ';') + out.writelines('\n') + + + out.close() + + os.chdir(cwd) + + +# Call main function +if __name__ == '__main__': + main(sys.argv) diff --git a/src/ngspicetoModelica/__init__.py b/src/ngspicetoModelica/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/ngspicetoModelica/__init__.py diff --git a/src/ngspicetoModelica/__init__.pyc b/src/ngspicetoModelica/__init__.pyc Binary files differnew file mode 100644 index 00000000..a74969f5 --- /dev/null +++ b/src/ngspicetoModelica/__init__.pyc diff --git a/src/projManagement/Kicad.py b/src/projManagement/Kicad.py new file mode 100644 index 00000000..a80f6259 --- /dev/null +++ b/src/projManagement/Kicad.py @@ -0,0 +1,164 @@ +#=============================================================================== +# +# FILE: openKicad.py +# +# USAGE: --- +# +# DESCRIPTION: It calls kicad schematic +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Tuesday 17 Feb 2015 +# REVISION: --- +#=============================================================================== + +import os +import Validation +from configuration.Appconfig import Appconfig +import Worker +from PyQt4 import QtGui + +class Kicad: + """ + This class called the Kicad Schematic,KicadtoNgspice Converter,Layout editor and Footprint Editor + """ + def __init__(self,dockarea): + self.obj_validation = Validation.Validation() + self.obj_appconfig = Appconfig() + self.obj_dockarea= dockarea + + def openSchematic(self): + """ + This function create command to open Kicad schematic + """ + print "Function : Open Kicad Schematic" + self.projDir = self.obj_appconfig.current_project["ProjectName"] + try: + self.obj_appconfig.print_info('Kicad Schematic is called for project ' + self.projDir) + except: + pass + #Validating if current project is available or not + + if self.obj_validation.validateKicad(self.projDir): + #print "calling Kicad schematic ",self.projDir + self.projName = os.path.basename(self.projDir) + self.project = os.path.join(self.projDir,self.projName) + + #Creating a command to run + self.cmd = "eeschema "+self.project+".sch " + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Please select the project first. You can either create new project or open existing project') + self.obj_appconfig.print_warning('Please select the project first. You can either create new project or open existing project') + self.msg.setWindowTitle("Error Message") + + + ''' + #Commenting as it is no longer needed as PBC and Layout will open from eeschema + def openFootprint(self): + """ + This function create command to open Footprint editor + """ + print "Kicad Foot print Editor called" + self.projDir = self.obj_appconfig.current_project["ProjectName"] + try: + self.obj_appconfig.print_info('Kicad Footprint Editor is called for project : ' + self.projDir) + except: + pass + #Validating if current project is available or not + + if self.obj_validation.validateKicad(self.projDir): + #print "calling Kicad FootPrint Editor ",self.projDir + self.projName = os.path.basename(self.projDir) + self.project = os.path.join(self.projDir,self.projName) + + #Creating a command to run + self.cmd = "cvpcb "+self.project+".net " + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Please select the project first. You can either create new project or open existing project') + self.obj_appconfig.print_warning('Please select the project first. You can either create new project or open existing project') + self.msg.setWindowTitle("Error Message") + + def openLayout(self): + """ + This function create command to open Layout editor + """ + print "Kicad Layout is called" + self.projDir = self.obj_appconfig.current_project["ProjectName"] + try: + self.obj_appconfig.print_info('PCB Layout is called for project : ' + self.projDir) + except: + pass + #Validating if current project is available or not + if self.obj_validation.validateKicad(self.projDir): + print "calling Kicad schematic ",self.projDir + self.projName = os.path.basename(self.projDir) + self.project = os.path.join(self.projDir,self.projName) + + #Creating a command to run + self.cmd = "pcbnew "+self.project+".net " + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Please select the project first. You can either create new project or open existing project') + self.obj_appconfig.print_warning('Please select the project first. You can either create new project or open existing project') + self.msg.setWindowTitle("Error Message") + + ''' + + def openKicadToNgspice(self): + """ + This function create command to call kicad to Ngspice converter. + """ + print "Function: Open Kicad to Ngspice Converter" + + self.projDir = self.obj_appconfig.current_project["ProjectName"] + try: + self.obj_appconfig.print_info('Kicad to Ngspice Conversion is called') + self.obj_appconfig.print_info('Current Project is ' + self.projDir) + except: + pass + #Validating if current project is available or not + if self.obj_validation.validateKicad(self.projDir): + #Cheking if project has .cir file or not + if self.obj_validation.validateCir(self.projDir): + self.projName = os.path.basename(self.projDir) + self.project = os.path.join(self.projDir,self.projName) + + #Creating a command to run + """ + self.cmd = "python ../kicadtoNgspice/KicadtoNgspice.py " +self.project+".cir " + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + """ + var=self.project+".cir" + self.obj_dockarea.kicadToNgspiceEditor(var) + + + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('The project does not contain any Kicad netlist file for conversion.') + self.obj_appconfig.print_error('The project does not contain any Kicad netlist file for conversion.') + self.msg.setWindowTitle("Error Message") + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Please select the project first. You can either create new project or open existing project') + self.obj_appconfig.print_warning('Please select the project first. You can either create new project or open existing project') + self.msg.setWindowTitle("Error Message") + + diff --git a/src/projManagement/Kicad.pyc b/src/projManagement/Kicad.pyc Binary files differnew file mode 100644 index 00000000..73b9f257 --- /dev/null +++ b/src/projManagement/Kicad.pyc diff --git a/src/projManagement/Validation.py b/src/projManagement/Validation.py new file mode 100644 index 00000000..a582cab5 --- /dev/null +++ b/src/projManagement/Validation.py @@ -0,0 +1,134 @@ + +#=============================================================================== +# +# FILE: Validation.py +# +# USAGE: --- +# +# DESCRIPTION: This module is use to create validation for openProject,newProject and other activity. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Wednesday 12 February 2015 +# REVISION: --- +#=============================================================================== +import os +import re +import distutils.spawn + + +class Validation: + """ + This is Validation class use for validating Project. + e.g if .proj is present in project directory + or if new project name is already exist in workspace etc + """ + def __init__(self): + pass + + def validateOpenproj(self,projDir): + """ + This function validate Open Project Information. + """ + print "Function: Validating Open Project Information" + projName = os.path.basename(str(projDir)) + lookProj = os.path.join(str(projDir),projName+".proj") + #Check existence of project + if os.path.exists(lookProj): + return True + else: + return False + + + + def validateNewproj(self,projDir): + """ + This Project Validate New Project Information + """ + print "Function: Validating New Project Information" + + #Checking existence of project with same name + if os.path.exists(projDir): + return "CHECKEXIST" #Project with name already exist + else: + #Check Proper name for project. It should not have space + if re.search(r"\s",projDir ): + return "CHECKNAME" + else: + return "VALID" + + def validateKicad(self,projDir): + """ + This function validate if Kicad components are present + """ + print "FUnction : Validating for Kicad components" + if projDir == None: + return False + else: + return True + + def validateCir(self,projDir): + """ + This function checks if ".cir" file is present. + """ + projName = os.path.basename(str(projDir)) + lookCir = os.path.join(str(projDir),projName+".cir") + #Check existence of project + if os.path.exists(lookCir): + return True + else: + return False + + def validateSub(self,subDir,givenNum): + """ + This function checks if ".sub" file is present. + """ + subName = os.path.basename(str(subDir)) + lookSub = os.path.join(str(subDir),subName+".sub") + #Check existence of project + if os.path.exists(lookSub): + f = open(lookSub) + data=f.read() + f.close() + netlist=data.splitlines() + for eachline in netlist: + eachline=eachline.strip() + if len(eachline)<1: + continue + words=eachline.split() + if words[0] == '.subckt': + #The number of ports is specified in this line + #eg. '.subckt ua741 6 7 3' has 3 ports (6, 7 and 3). + numPorts = len(words) - 2 + print "Looksub : ",lookSub + print "Given Number of ports : ",givenNum + print "Actual Number of ports :",numPorts + if numPorts != givenNum: + return "PORT" + else: + return "True" + else: + return "DIREC" + + def validateCirOut(self,projDir): + """ + This function checks if ".cir.out" file is present. + """ + projName = os.path.basename(str(projDir)) + lookCirOut = os.path.join(str(projDir),projName+".cir.out") + #Check existence of project + if os.path.exists(lookCirOut): + return True + else: + return False + + def validateTool(self,toolName): + """ + This function check if tool is present in the system + """ + return distutils.spawn.find_executable(toolName) is not None +
\ No newline at end of file diff --git a/src/projManagement/Validation.pyc b/src/projManagement/Validation.pyc Binary files differnew file mode 100644 index 00000000..4b9b74b2 --- /dev/null +++ b/src/projManagement/Validation.pyc diff --git a/src/projManagement/Worker.py b/src/projManagement/Worker.py new file mode 100644 index 00000000..6befca65 --- /dev/null +++ b/src/projManagement/Worker.py @@ -0,0 +1,46 @@ +#=============================================================================== +# +# FILE: WorkerThread.py +# +# USAGE: --- +# +# DESCRIPTION: This class open all third party application using QT Thread +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Tuesday 24 Feb 2015 +# REVISION: --- +#=============================================================================== +from PyQt4 import QtCore +import subprocess +from configuration.Appconfig import Appconfig + +class WorkerThread(QtCore.QThread): + """ + This is Thread class use to run the command + """ + def __init__(self,args): + QtCore.QThread.__init__(self) + self.args = args + + + def __del__(self): + self.wait() + + def run(self): + print "Worker Thread Calling Command :",self.args + self.call_system(self.args) + + def call_system(self,command): + procThread = Appconfig() + proc = subprocess.Popen(command.split()) + procThread.procThread_list.append(proc) + procThread.proc_dict[procThread.current_project['ProjectName']].append(proc.pid) + + + + diff --git a/src/projManagement/Worker.pyc b/src/projManagement/Worker.pyc Binary files differnew file mode 100644 index 00000000..9175b3aa --- /dev/null +++ b/src/projManagement/Worker.pyc diff --git a/src/projManagement/__init__.py b/src/projManagement/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/projManagement/__init__.py diff --git a/src/projManagement/__init__.pyc b/src/projManagement/__init__.pyc Binary files differnew file mode 100644 index 00000000..40d18ce7 --- /dev/null +++ b/src/projManagement/__init__.pyc diff --git a/src/projManagement/newProject.py b/src/projManagement/newProject.py new file mode 100644 index 00000000..5b4af49a --- /dev/null +++ b/src/projManagement/newProject.py @@ -0,0 +1,109 @@ + +#=============================================================================== +# +# FILE: newProject.py +# +# USAGE: --- +# +# DESCRIPTION: It is called whenever new project is being called. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Wednesday 12 February 2015 +# REVISION: --- +#=============================================================================== +from PyQt4 import QtGui +from Validation import Validation +from configuration.Appconfig import Appconfig +import os +import json + +class NewProjectInfo(QtGui.QWidget): + """ + This class is called when User create new Project. + """ + + def __init__(self): + super(NewProjectInfo, self).__init__() + self.obj_validation = Validation() + self.obj_appconfig = Appconfig() + + + def createProject(self,projName): + """ + This function create Project related directories and files + """ + #print "Create Project Called" + self.projName= projName + self.workspace = self.obj_appconfig.default_workspace['workspace'] + #self.projName = self.projEdit.text() + self.projName = str(self.projName).rstrip().lstrip() #Remove leading and trailing space + + self.projDir = os.path.join(self.workspace,str(self.projName)) + + + #Validation for newProject + if self.projName == "": + self.reply = "NONE" + else: + self.reply = self.obj_validation.validateNewproj(str(self.projDir)) + + #Checking Validations Response + if self.reply == "VALID": + #create project directory + try: + os.mkdir(self.projDir) + self.close() + self.projFile = os.path.join(self.projDir,self.projName+".proj") + f = open(self.projFile,"w") + except: + #print "Some Thing Went Wrong" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('Unable to create project. Please make sure you have write permission on '+self.workspace) + self.msg.setWindowTitle("Error Message") + f.write("schematicFile " + self.projName+".sch\n") + f.close() + + #Now Change the current working project + newprojlist = [] + #self.obj_appconfig = Appconfig() + self.obj_appconfig.current_project['ProjectName'] = self.projDir + newprojlist.append(self.projName+'.proj') + self.obj_appconfig.project_explorer[self.projDir] = newprojlist + + self.obj_appconfig.print_info('New project created : ' + self.projName) + self.obj_appconfig.print_info('Current project is : ' + self.projDir) + + json.dump(self.obj_appconfig.project_explorer, open(self.obj_appconfig.dictPath,'w')) + return self.projDir, newprojlist + + elif self.reply == "CHECKEXIST": + #print "Project already exist" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The project "'+self.projName+'" already exist.Please select the different name or delete existing project') + self.msg.setWindowTitle("Error Message") + + + elif self.reply == "CHECKNAME": + #print "Name is not proper" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The project name should not contain space between them') + self.msg.setWindowTitle("Error Message") + + elif self.reply == "NONE": + #print "Empty Project Name" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The project name cannot be empty') + self.msg.setWindowTitle("Error Message") + + def cancelProject(self): + self.close() + + + + +
\ No newline at end of file diff --git a/src/projManagement/newProject.pyc b/src/projManagement/newProject.pyc Binary files differnew file mode 100644 index 00000000..5dfbe736 --- /dev/null +++ b/src/projManagement/newProject.pyc diff --git a/src/projManagement/openProject.py b/src/projManagement/openProject.py new file mode 100644 index 00000000..d980d914 --- /dev/null +++ b/src/projManagement/openProject.py @@ -0,0 +1,72 @@ + +#=============================================================================== +# +# FILE: openProject.py +# +# USAGE: --- +# +# DESCRIPTION: It is called whenever new project is being called. +# +# OPTIONS: --- +# REQUIREMENTS: --- +# BUGS: --- +# NOTES: --- +# AUTHOR: Fahim Khan, fahim.elex@gmail.com +# ORGANIZATION: eSim team at FOSSEE, IIT Bombay. +# CREATED: Wednesday 12 February 2015 +# REVISION: --- +#=============================================================================== + +from PyQt4 import QtGui +from Validation import Validation +from configuration.Appconfig import Appconfig +import os +import json + + +class OpenProjectInfo(QtGui.QWidget): + """ + This class is called when User click on Open Project Button + """ + def __init__(self): + super(OpenProjectInfo, self).__init__() + self.obj_validation = Validation() + + def body(self): + self.obj_Appconfig = Appconfig() + self.openDir = self.obj_Appconfig.default_workspace["workspace"] + self.projDir=QtGui.QFileDialog.getExistingDirectory(self,"open",self.openDir) + + if self.obj_validation.validateOpenproj(self.projDir) == True: + self.obj_Appconfig.current_project['ProjectName'] = str(self.projDir) + if os.path.isdir(self.projDir): + print "true" + + for dirs, subdirs, filelist in os.walk(self.obj_Appconfig.current_project["ProjectName"]): + directory = dirs + files = filelist + self.obj_Appconfig.project_explorer[dirs] = filelist + json.dump(self.obj_Appconfig.project_explorer, open(self.obj_Appconfig.dictPath,'w')) + self.obj_Appconfig.print_info('Open Project called') + self.obj_Appconfig.print_info('Current Project is ' + self.projDir) + return dirs, filelist + + else: + self.obj_Appconfig.print_error("The project doesn't contain .proj file. Please select the proper directory else you won't be able to perform any operation") + reply = QtGui.QMessageBox.critical(None, "Error Message",'''<b> Error: The project doesn't contain .proj file.</b><br/> + <b>Please select the proper project directory else you won't be able to perform any operation</b>''',QtGui.QMessageBox.Ok|QtGui.QMessageBox.Cancel) + + if reply == QtGui.QMessageBox.Ok: + self.body() + self.obj_Appconfig.print_info('Open Project called') + self.obj_Appconfig.print_info('Current Project is ' + self.projDir) + elif reply == QtGui.QMessageBox.Cancel: + self.obj_Appconfig.print_info('No Project opened') + else: + pass + + + + + +
\ No newline at end of file diff --git a/src/projManagement/openProject.pyc b/src/projManagement/openProject.pyc Binary files differnew file mode 100644 index 00000000..f9886c3e --- /dev/null +++ b/src/projManagement/openProject.pyc diff --git a/src/subcircuit/Subcircuit.py b/src/subcircuit/Subcircuit.py new file mode 100644 index 00000000..f53acc6a --- /dev/null +++ b/src/subcircuit/Subcircuit.py @@ -0,0 +1,65 @@ +from PyQt4 import QtCore, QtGui +from configuration.Appconfig import Appconfig +from projManagement.Validation import Validation +from subcircuit.newSub import NewSub +from subcircuit.openSub import openSub +from subcircuit.convertSub import convertSub + +class Subcircuit(QtGui.QWidget): + """ + This class creates Subcircuit GUI. + """ + def __init__(self,parent=None): + super(Subcircuit, self).__init__() + QtGui.QWidget.__init__(self) + self.obj_appconfig=Appconfig() + self.obj_validation=Validation() + self.obj_dockarea=parent + self.layout = QtGui.QVBoxLayout() + self.splitter= QtGui.QSplitter() + self.splitter.setOrientation(QtCore.Qt.Vertical) + + self.newbtn = QtGui.QPushButton('New Subcircuit Schematic') + self.newbtn.setToolTip('<b>To create new Subcircuit Schematic</b>') + self.newbtn.setFixedSize(200,40) + self.newbtn.clicked.connect(self.newsch) + self.editbtn = QtGui.QPushButton('Edit Subcircuit Schematic') + self.editbtn.setToolTip('<b>To edit existing Subcircuit Schematic</b>') + self.editbtn.setFixedSize(200,40) + self.editbtn.clicked.connect(self.editsch) + self.convertbtn = QtGui.QPushButton('Convert Kicad to Ngspice') + self.convertbtn.setToolTip('<b>To convert Subcircuit Kicad Netlist to Ngspice Netlist</b>') + self.convertbtn.setFixedSize(200,40) + self.convertbtn.clicked.connect(self.convertsch) + + self.hbox = QtGui.QHBoxLayout() + self.hbox.addWidget(self.newbtn) + self.hbox.addWidget(self.editbtn) + self.hbox.addWidget(self.convertbtn) + self.hbox.addStretch(1) + + self.vbox = QtGui.QVBoxLayout() + self.vbox.addLayout(self.hbox) + self.vbox.addStretch(1) + + self.setLayout(self.vbox) + self.show() + + def newsch(self): + text,ok = QtGui.QInputDialog.getText(self, 'New Schematic','Enter Schematic Name:') + if ok: + self.schematic_name = (str(text)) + self.subcircuit = NewSub() + self.subcircuit.createSubcircuit(self.schematic_name) + + else: + print "Sub circuit creation cancelled" + + + def editsch(self): + self.obj_opensubcircuit = openSub() + self.obj_opensubcircuit.body() + + def convertsch(self): + self.obj_convertsubcircuit = convertSub(self.obj_dockarea) + self.obj_convertsubcircuit.createSub()
\ No newline at end of file diff --git a/src/subcircuit/Subcircuit.pyc b/src/subcircuit/Subcircuit.pyc Binary files differnew file mode 100644 index 00000000..9f02e7d1 --- /dev/null +++ b/src/subcircuit/Subcircuit.pyc diff --git a/src/subcircuit/__init__.py b/src/subcircuit/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/subcircuit/__init__.py diff --git a/src/subcircuit/__init__.pyc b/src/subcircuit/__init__.pyc Binary files differnew file mode 100644 index 00000000..13e58047 --- /dev/null +++ b/src/subcircuit/__init__.pyc diff --git a/src/subcircuit/convertSub.py b/src/subcircuit/convertSub.py new file mode 100644 index 00000000..358028ed --- /dev/null +++ b/src/subcircuit/convertSub.py @@ -0,0 +1,41 @@ +from PyQt4 import QtGui +from projManagement.Validation import Validation +from configuration.Appconfig import Appconfig +import os + +class convertSub(QtGui.QWidget): + """ + This class is called when User create new Project. + """ + + def __init__(self,dockarea): + super(convertSub, self).__init__() + self.obj_validation = Validation() + self.obj_appconfig=Appconfig() + self.obj_dockarea=dockarea + + def createSub(self): + """ + This function create command to call kicad to Ngspice converter. + """ + print "Openinig Kicad-to-Ngspice converter from Subcircuit Module" + self.projDir = self.obj_appconfig.current_subcircuit["SubcircuitName"] + #Validating if current project is available or not + if self.obj_validation.validateKicad(self.projDir): + #Checking if project has .cir file or not + if self.obj_validation.validateCir(self.projDir): + #print "CIR file present" + self.projName = os.path.basename(self.projDir) + self.project = os.path.join(self.projDir,self.projName) + + var1=self.project+".cir" + var2="sub" + self.obj_dockarea.kicadToNgspiceEditor(var1,var2) + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('The subcircuit does not contain any Kicad netlist file for conversion.') + self.msg.setWindowTitle("Error Message") + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Please select the subcircuit first. You can either create new subcircuit or open existing subcircuit') + self.msg.setWindowTitle("Error Message")
\ No newline at end of file diff --git a/src/subcircuit/convertSub.pyc b/src/subcircuit/convertSub.pyc Binary files differnew file mode 100644 index 00000000..3f92df82 --- /dev/null +++ b/src/subcircuit/convertSub.pyc diff --git a/src/subcircuit/newSub.py b/src/subcircuit/newSub.py new file mode 100644 index 00000000..7ea247ab --- /dev/null +++ b/src/subcircuit/newSub.py @@ -0,0 +1,65 @@ +from PyQt4 import QtGui,QtCore +from projManagement.Validation import Validation +from configuration.Appconfig import Appconfig +from projManagement import Worker +import os + +class NewSub(QtGui.QWidget): + """ + This class is called when User create new Project. + """ + + def __init__(self): + super(NewSub, self).__init__() + self.obj_validation = Validation() + self.obj_appconfig = Appconfig() + + + def createSubcircuit(self,subName): + """ + This function create Subcircuit related directories and files + """ + self.create_schematic = subName + #Checking if Workspace already exist or not + self.schematic_path = (os.path.join(os.path.abspath('..'),'SubcircuitLibrary',self.create_schematic)) + + #Validation for new subcircuit + if self.schematic_path == "": + self.reply = "NONE" + else: + self.reply = self.obj_validation.validateNewproj(str(self.schematic_path)) + + #Checking Validations Response + if self.reply == "VALID": + print "Validated : Creating subcircuit directory" + try: + os.mkdir(self.schematic_path) + self.schematic = os.path.join(self.schematic_path,self.create_schematic) + self.cmd = "eeschema "+self.schematic+".sch" + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + self.close() + except: + #print "Some Thing Went Wrong" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('Unable to create subcircuit. Please make sure you have write permission on '+self.schematic_path) + self.msg.setWindowTitle("Error Message") + + self.obj_appconfig.current_subcircuit['SubcircuitName'] = self.schematic_path + + elif self.reply == "CHECKEXIST": + #print "Project already exist" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The subcircuit "'+self.create_schematic+'" already exist.Please select the different name or delete existing subcircuit') + self.msg.setWindowTitle("Error Message") + + elif self.reply == "CHECKNAME": + #print "Name is not proper" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The subcircuit name should not contain space between them') + self.msg.setWindowTitle("Error Message") + + elif self.reply == "NONE": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The subcircuit name cannot be empty') + self.msg.setWindowTitle("Error Message")
\ No newline at end of file diff --git a/src/subcircuit/newSub.pyc b/src/subcircuit/newSub.pyc Binary files differnew file mode 100644 index 00000000..f99577ec --- /dev/null +++ b/src/subcircuit/newSub.pyc diff --git a/src/subcircuit/openSub.py b/src/subcircuit/openSub.py new file mode 100644 index 00000000..fb349f0a --- /dev/null +++ b/src/subcircuit/openSub.py @@ -0,0 +1,24 @@ +from PyQt4 import QtGui +from configuration.Appconfig import Appconfig +from projManagement.Worker import WorkerThread +import os + + +class openSub(QtGui.QWidget): + """ + This class is called when User click on Open Project Button + """ + def __init__(self): + super(openSub, self).__init__() + self.obj_appconfig = Appconfig() + + def body(self): + self.editfile = str(QtGui.QFileDialog.getExistingDirectory(None,"Open File","../SubcircuitLibrary")) + if self.editfile: + self.obj_Appconfig = Appconfig() + self.obj_Appconfig.current_subcircuit['SubcircuitName'] = self.editfile + self.schname = os.path.basename(self.editfile) + self.editfile = os.path.join(self.editfile,self.schname) + self.cmd = "eeschema "+self.editfile+".sch " + self.obj_workThread = WorkerThread(self.cmd) + self.obj_workThread.start()
\ No newline at end of file diff --git a/src/subcircuit/openSub.pyc b/src/subcircuit/openSub.pyc Binary files differnew file mode 100644 index 00000000..d81da0e8 --- /dev/null +++ b/src/subcircuit/openSub.pyc |
