summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorFahim2016-02-12 15:10:50 +0530
committerFahim2016-02-12 15:10:50 +0530
commit1aaa791497cd672a547351936422246efdb758fd (patch)
tree67e3793b35b9384270393f77ba2a128e9f0039f1 /src
parent60c46f180d10cfc1eef68422f603b6ef528db7c3 (diff)
downloadeSim-1aaa791497cd672a547351936422246efdb758fd.tar.gz
eSim-1aaa791497cd672a547351936422246efdb758fd.tar.bz2
eSim-1aaa791497cd672a547351936422246efdb758fd.zip
Added phase plot
Diffstat (limited to 'src')
-rw-r--r--src/kicadtoNgspice/Processing.py7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py
index 123dce1e..0eaf6d2f 100644
--- a/src/kicadtoNgspice/Processing.py
+++ b/src/kicadtoNgspice/Processing.py
@@ -156,7 +156,7 @@ class PrcocessNetlist:
#Insert details of Ngspice model
unknownModelList = []
multipleModelList = []
- plotList = ['plot_v1','plot_v2','plot_i2','plot_log','plot_db']
+ plotList = ['plot_v1','plot_v2','plot_i2','plot_log','plot_db','plot_phase']
k = 1
for compline in schematicInfo:
@@ -327,6 +327,9 @@ class PrcocessNetlist:
elif compType == 'plot_db':
words = compline.split()
plotText.append("plot db("+words[1]+")")
+ elif compType == 'plot_phase':
+ words = compline.split()
+ plotText.append("plot phase("+words[1]+")")
else:
schematicInfo.insert(index,"* "+compline)
@@ -340,4 +343,4 @@ class PrcocessNetlist:
return schematicInfo,outputOption,modelList,unknownModelList,multipleModelList,plotText
- \ No newline at end of file
+