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| author | Tanay Mathur | 2015-06-23 11:50:52 +0530 |
|---|---|---|
| committer | Tanay Mathur | 2015-06-23 11:50:52 +0530 |
| commit | 39fecda9f1be8b1007552437d53c06bdc02f4b47 (patch) | |
| tree | 3f4bffd09e28240509a215a4b00b3f8b4dda712a /src | |
| parent | f47a744451fe634efb487023f073321ceed4664c (diff) | |
| download | eSim-39fecda9f1be8b1007552437d53c06bdc02f4b47.tar.gz eSim-39fecda9f1be8b1007552437d53c06bdc02f4b47.tar.bz2 eSim-39fecda9f1be8b1007552437d53c06bdc02f4b47.zip | |
Added subcircuit functionality
Diffstat (limited to 'src')
37 files changed, 2485 insertions, 125 deletions
diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/lm555n.bak b/src/SubcircuitLibrary/lm555n/lm555n.bak new file mode 100644 index 00000000..92d1f7a7 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.bak @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:48:46 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir new file mode 100644 index 00000000..8f6f81c6 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir @@ -0,0 +1,25 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 21 D_INVERTER +U6 1 4 5 21 21 8 10 D_SRLATCH +E2 18 0 23 14 10000 +*U4 19 20 11 12 LIMIT8 +*U3 8 10 7 9 DAC8 +*U2 11 12 6 4 1 5 ADC8 +U1 22 14 7 6 15 16 3 13 PORT +R8 9 2 1500 +Q1 22 2 3 QNOM +R7 18 20 25 +R6 17 19 25 +E1 17 0 16 15 10000 +R4 16 15 2E6 +R5 23 14 2E6 +R3 23 22 5000 +R2 15 23 5000 +R1 13 15 5000 + +.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt new file mode 100644 index 00000000..90f04a32 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt @@ -0,0 +1,35 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out new file mode 100644 index 00000000..f25b1e46 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -0,0 +1,31 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* u5 5 21 d_inverter +* u6 1 4 5 21 21 8 10 d_srlatch +e2 18 0 23 14 10000 +* u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 22 2 3 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +a2 1 4 5 21 21 8 10 u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_srlatch, NgSpice Name: d_srlatch +.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out~ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~ new file mode 100644 index 00000000..bc50c640 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~ @@ -0,0 +1,30 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist + +* u5 5 21 d_inverter +* u6 1 4 5 21 21 8 10 d_srlatch +e2 18 0 23 14 10000 +r8 9 2 1500 +q1 22 2 3 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +a2 1 4 5 21 21 8 10 u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_srlatch, NgSpice Name: d_srlatch +.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir~ b/src/SubcircuitLibrary/lm555n/lm555n.cir~ new file mode 100644 index 00000000..7ef9e6a5 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir~ @@ -0,0 +1,25 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U5 5 21 D_INVERTER +U6 1 4 5 21 21 8 10 D_SRLATCH +E2 18 0 23 14 10000 +*U4 19 20 11 12 LIMIT8 +*U3 8 10 7 9 DAC8 +*U2 11 12 6 4 1 5 ADC8 +*U1 22 14 7 6 15 16 3 13 PORT +R8 9 2 1500 +Q1 22 2 3 QNOM +R7 18 20 25 +R6 17 19 25 +E1 17 0 16 15 10000 +R4 16 15 2E6 +R5 23 14 2E6 +R3 23 22 5000 +R2 15 23 5000 +R1 13 15 5000 + +.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro new file mode 100644 index 00000000..c8e151fb --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.pro @@ -0,0 +1,73 @@ +update=Monday 19 November 2012 04:56:38 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=analogXSpice +LibName33=converterSpice +LibName34=digitalSpice +LibName35=linearSpice +LibName36=measurementSpice +LibName37=portSpice +LibName38=sourcesSpice +LibName39=digitalXSpice diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch new file mode 100644 index 00000000..fabbb666 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.sch @@ -0,0 +1,435 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 10:57:52 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:digitalXSpice +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L D_INVERTER U5 +U 1 1 50CEA9C5 +P 6700 4050 +F 0 "U5" H 6550 4150 40 0000 C CNN +F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN + 1 6700 4050 + 1 0 0 -1 +$EndComp +$Comp +L D_SRLATCH U6 +U 1 1 50CEA9AE +P 7100 3400 +F 0 "U6" H 6900 3650 60 0000 C CNN +F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN + 1 7100 3400 + 1 0 0 -1 +$EndComp +Text Notes 5750 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 4700 3000 4900 3000 +Wire Wire Line + 4700 4750 4700 4650 +Connection ~ 4400 3550 +Connection ~ 4400 4900 +Wire Wire Line + 4300 4900 7700 4900 +Wire Wire Line + 4400 4200 4400 4100 +Wire Wire Line + 7700 4900 7700 4800 +Wire Wire Line + 7700 3250 7850 3250 +Wire Wire Line + 7400 4600 7100 4600 +Wire Wire Line + 7100 4600 7100 4250 +Wire Wire Line + 7700 3650 7700 3550 +Wire Wire Line + 6350 4050 6450 4050 +Wire Wire Line + 6950 3900 6950 4000 +Wire Wire Line + 7150 4000 7150 4050 +Wire Wire Line + 7150 4050 6950 4050 +Wire Wire Line + 6500 3550 6200 3550 +Wire Wire Line + 6350 3250 6500 3250 +Wire Wire Line + 5400 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3750 +Wire Wire Line + 5550 4500 5550 4350 +Wire Wire Line + 5700 3550 5800 3550 +Wire Wire Line + 5900 3250 6000 3250 +Wire Wire Line + 6000 3850 6350 3850 +Wire Wire Line + 5800 4150 6200 4150 +Wire Wire Line + 5200 3550 5200 3700 +Wire Wire Line + 5200 3700 5550 3700 +Wire Wire Line + 5550 3700 5550 3750 +Connection ~ 5550 4450 +Wire Wire Line + 5750 4400 5750 4450 +Wire Wire Line + 5100 4350 5100 4450 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6500 3400 6450 3400 +Wire Wire Line + 6450 3400 6450 4050 +Wire Wire Line + 6950 4000 7250 4000 +Wire Wire Line + 7250 4000 7250 3900 +Connection ~ 7150 4000 +Wire Wire Line + 7600 4250 7700 4250 +Wire Wire Line + 7700 4400 7700 4350 +Wire Wire Line + 7700 4350 7800 4350 +Wire Wire Line + 7850 3850 7900 3850 +Wire Wire Line + 4400 4900 4400 4700 +Wire Wire Line + 4400 3600 4400 3500 +Wire Wire Line + 4300 3000 4400 3000 +Wire Wire Line + 4400 4150 4700 4150 +Connection ~ 4400 4150 +Wire Wire Line + 4300 3550 4700 3550 +Wire Wire Line + 4700 3550 4700 3500 +Wire Wire Line + 6350 4750 6350 4650 +Text Label 4850 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 5050 4050 +F 0 "E2" H 4850 4150 50 0000 C CNN +F 1 "10000" H 4850 4000 50 0000 C CNN + 1 5050 4050 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 2 1 50B4E21B +P 6000 3550 +F 0 "U4" H 6000 3650 30 0000 C CNN +F 1 "LIMIT8" H 6000 3550 30 0000 C CNN + 2 6000 3550 + 0 1 1 0 +$EndComp +$Comp +L LIMIT8 U4 +U 1 1 50B4E215 +P 5800 3850 +F 0 "U4" H 5800 3950 30 0000 C CNN +F 1 "LIMIT8" H 5800 3850 30 0000 C CNN + 1 5800 3850 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 2 1 50AAFCE7 +P 7700 3950 +F 0 "U3" H 7600 4050 40 0000 C CNN +F 1 "DAC8" H 7700 3950 40 0000 C CNN + 2 7700 3950 + 0 1 1 0 +$EndComp +$Comp +L DAC8 U3 +U 1 1 50AAFC9A +P 7850 3550 +F 0 "U3" H 7750 3650 40 0000 C CNN +F 1 "DAC8" H 7850 3550 40 0000 C CNN + 1 7850 3550 + 0 1 1 0 +$EndComp +$Comp +L ADC8 U2 +U 3 1 50AAFB76 +P 6350 4350 +F 0 "U2" H 6250 4450 40 0000 C CNN +F 1 "ADC8" H 6350 4350 40 0000 C CNN + 3 6350 4350 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 2 1 50AAFB64 +P 6350 3550 +F 0 "U2" H 6250 3650 40 0000 C CNN +F 1 "ADC8" H 6350 3550 40 0000 C CNN + 2 6350 3550 + 0 -1 -1 0 +$EndComp +$Comp +L ADC8 U2 +U 1 1 50AAFB55 +P 6200 3850 +F 0 "U2" H 6100 3950 40 0000 C CNN +F 1 "ADC8" H 6200 3850 40 0000 C CNN + 1 6200 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 5750 4400 +F 0 "#FLG01" H 5750 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 5750 4630 30 0000 C CNN + 1 5750 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 4050 3550 +F 0 "U1" H 4050 3500 30 0000 C CNN +F 1 "PORT" H 4050 3550 30 0000 C CNN + 5 4050 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 4050 4900 +F 0 "U1" H 4050 4850 30 0000 C CNN +F 1 "PORT" H 4050 4900 30 0000 C CNN + 1 4050 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 4700 5000 +F 0 "U1" H 4700 4950 30 0000 C CNN +F 1 "PORT" H 4700 5000 30 0000 C CNN + 2 4700 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 6350 5000 +F 0 "U1" H 6350 4950 30 0000 C CNN +F 1 "PORT" H 6350 5000 30 0000 C CNN + 4 6350 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 8050 4350 +F 0 "U1" H 8050 4300 30 0000 C CNN +F 1 "PORT" H 8050 4350 30 0000 C CNN + 7 8050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 8150 3850 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8150 3850 30 0000 C CNN + 3 8150 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 5150 3000 +F 0 "U1" H 5150 2950 30 0000 C CNN +F 1 "PORT" H 5150 3000 30 0000 C CNN + 6 5150 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 4050 3000 +F 0 "U1" H 4050 2950 30 0000 C CNN +F 1 "PORT" H 4050 3000 30 0000 C CNN + 8 4050 3000 + 1 0 0 -1 +$EndComp +$Comp +L R R8 +U 1 1 50AA20DA +P 7350 4250 +F 0 "R8" V 7430 4250 50 0000 C CNN +F 1 "1500" V 7350 4250 50 0000 C CNN + 1 7350 4250 + 0 1 1 0 +$EndComp +$Comp +L NPN Q1 +U 1 1 50AA2050 +P 7600 4600 +F 0 "Q1" H 7600 4450 50 0000 R CNN +F 1 "QNOM" H 7600 4750 50 0000 R CNN + 1 7600 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50AA140C +P 5550 4500 +F 0 "#PWR02" H 5550 4500 30 0001 C CNN +F 1 "GND" H 5550 4430 30 0001 C CNN + 1 5550 4500 + 1 0 0 -1 +$EndComp +Text Label 4850 4000 0 60 ~ 0 +c +Text Label 4700 4650 0 60 ~ 0 +d +Text Label 4700 4150 0 60 ~ 0 +c +$Comp +L R R7 +U 1 1 50AA12F7 +P 5650 3250 +F 0 "R7" V 5730 3250 50 0000 C CNN +F 1 "25" V 5650 3250 50 0000 C CNN + 1 5650 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R R6 +U 1 1 50AA12B0 +P 5450 3550 +F 0 "R6" V 5530 3550 50 0000 C CNN +F 1 "25" V 5450 3550 50 0000 C CNN + 1 5450 3550 + 0 -1 -1 0 +$EndComp +Text Label 5300 4000 0 60 ~ 0 +b +Text Label 5300 4100 0 60 ~ 0 +a +Text Label 4700 3000 0 60 ~ 0 +b +Text Label 4700 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 5500 4050 +F 0 "E1" H 5300 4150 50 0000 C CNN +F 1 "10000" H 5300 4000 50 0000 C CNN + 1 5500 4050 + 0 1 1 0 +$EndComp +$Comp +L R R4 +U 1 1 50A9E00B +P 4700 3250 +F 0 "R4" V 4780 3250 50 0000 C CNN +F 1 "2E6" V 4700 3250 50 0000 C CNN + 1 4700 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 50A9E001 +P 4700 4400 +F 0 "R5" V 4780 4400 50 0000 C CNN +F 1 "2E6" V 4700 4400 50 0000 C CNN + 1 4700 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 50A9DF09 +P 4400 4450 +F 0 "R3" V 4480 4450 50 0000 C CNN +F 1 "5000" V 4400 4450 50 0000 C CNN + 1 4400 4450 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 50A9DF03 +P 4400 3850 +F 0 "R2" V 4480 3850 50 0000 C CNN +F 1 "5000" V 4400 3850 50 0000 C CNN + 1 4400 3850 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 50A9DEFE +P 4400 3250 +F 0 "R1" V 4480 3250 50 0000 C CNN +F 1 "5000" V 4400 3250 50 0000 C CNN + 1 4400 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub new file mode 100644 index 00000000..862626ea --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n.sub @@ -0,0 +1,25 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist +* u5 5 21 d_inverter +* u6 1 4 5 21 21 8 10 d_srlatch +e2 18 0 23 14 10000 +r8 9 2 1500 +q1 22 2 3 qnom +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +a2 1 4 5 21 21 8 10 u6 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_srlatch, NgSpice Name: d_srlatch +.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) +* Control Statements + +.ends lm555n
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml new file mode 100644 index 00000000..7d81146a --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/analysis b/src/SubcircuitLibrary/ua741/analysis new file mode 100644 index 00000000..52ccc5ec --- /dev/null +++ b/src/SubcircuitLibrary/ua741/analysis @@ -0,0 +1 @@ +.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.bak b/src/SubcircuitLibrary/ua741/ua741-cache.bak new file mode 100644 index 00000000..eaad34ad --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741-cache.bak @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 21 October 2012 01:22:10 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 I +X ~ 2 250 0 100 L 30 30 2 1 I +X ~ 3 250 0 100 L 30 30 3 1 I +X ~ 4 250 0 100 L 30 30 4 1 I +X ~ 5 250 0 100 L 30 30 5 1 I +X ~ 6 250 0 100 L 30 30 6 1 I +X ~ 7 250 0 100 L 30 30 7 1 I +X ~ 8 250 0 100 L 30 30 8 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.lib b/src/SubcircuitLibrary/ua741/ua741-cache.lib new file mode 100644 index 00000000..9114d342 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 Date: Saturday 17 November 2012 08:10:48 AM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 0 -50 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 I +X ~ 2 250 0 100 L 30 30 2 1 I +X ~ 3 250 0 100 L 30 30 3 1 I +X ~ 4 250 0 100 L 30 30 4 1 I +X ~ 5 250 0 100 L 30 30 5 1 I +X ~ 6 250 0 100 L 30 30 6 1 I +X ~ 7 250 0 100 L 30 30 7 1 I +X ~ 8 250 0 100 L 30 30 8 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" -200 100 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/ua741/ua741.bak b/src/SubcircuitLibrary/ua741/ua741.bak new file mode 100644 index 00000000..6be92803 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 date Monday 17 December 2012 11:17:01 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "20 oct 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 3 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 1 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 2 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ua741/ua741.cir b/src/SubcircuitLibrary/ua741/ua741.cir new file mode 100644 index 00000000..de797429 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U1 6 7 3 PORT +Rout1 3 2 75 +Eout1 2 0 1 0 1 +Cbw1 1 0 31.85e-9 +Rbw1 1 4 0.5e6 +Ein1 4 0 7 6 100e3 +Rin1 7 6 2e6 + +.end diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.ckt b/src/SubcircuitLibrary/ua741/ua741.cir.ckt new file mode 100644 index 00000000..3661a9a2 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.out b/src/SubcircuitLibrary/ua741/ua741.cir.out new file mode 100644 index 00000000..72e68514 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist + +* u1 6 7 3 port +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro new file mode 100644 index 00000000..5dbb81a5 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.pro @@ -0,0 +1,72 @@ +update=Monday 17 December 2012 06:14:06 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=converterSpice +LibName33=digitalSpice +LibName34=linearSpice +LibName35=measurementSpice +LibName36=portSpice +LibName37=sourcesSpice +LibName38=analogXSpice diff --git a/src/SubcircuitLibrary/ua741/ua741.sch b/src/SubcircuitLibrary/ua741/ua741.sch new file mode 100644 index 00000000..7dfc5e1a --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.sch @@ -0,0 +1,219 @@ +EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:analogXSpice +LIBS:ua741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3800 2400 0 60 ~ 0 +Op-Amp +Text Notes 3750 2850 0 60 ~ 0 +VCCS +Text Notes 5800 2500 0 60 ~ 0 +out +Text Notes 2750 3100 0 60 ~ 0 +- +Text Notes 2700 2600 0 60 ~ 0 ++ +$Comp +L PORT U1 +U 6 1 5082C027 +P 6250 2500 +F 0 "U1" H 6250 2450 30 0000 C CNN +F 1 "PORT" H 6250 2500 30 0000 C CNN + 6 6250 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5082C011 +P 2300 3100 +F 0 "U1" H 2300 3050 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN + 2 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5082C00B +P 2250 2600 +F 0 "U1" H 2250 2550 30 0000 C CNN +F 1 "PORT" H 2250 2600 30 0000 C CNN + 3 2250 2600 + 1 0 0 -1 +$EndComp +Connection ~ 3700 3200 +Wire Wire Line + 3450 3200 3700 3200 +Connection ~ 5000 3300 +Wire Wire Line + 3700 3300 5250 3300 +Wire Wire Line + 5250 3300 5250 3200 +Connection ~ 4550 3300 +Wire Wire Line + 5000 3300 5000 2950 +Connection ~ 3700 3300 +Wire Wire Line + 4550 3300 4550 3100 +Wire Wire Line + 3900 2500 3700 2500 +Wire Wire Line + 3700 2500 3700 2550 +Wire Wire Line + 3450 2900 3300 2900 +Wire Wire Line + 3300 2900 3300 3200 +Wire Wire Line + 3300 3200 2950 3200 +Connection ~ 2950 3100 +Wire Wire Line + 2950 3200 2950 3100 +Wire Wire Line + 3000 2600 2500 2600 +Wire Wire Line + 2550 3100 3000 3100 +Wire Wire Line + 2950 2600 2950 2500 +Connection ~ 2950 2600 +Wire Wire Line + 2950 2500 3300 2500 +Wire Wire Line + 3300 2500 3300 2800 +Wire Wire Line + 3300 2800 3450 2800 +Wire Wire Line + 3700 3150 3700 3400 +Wire Wire Line + 4550 2500 4550 2700 +Wire Wire Line + 4400 2500 5000 2500 +Wire Wire Line + 5000 2500 5000 2850 +Connection ~ 4550 2500 +Wire Wire Line + 5250 2600 5250 2500 +Wire Wire Line + 5250 2500 5350 2500 +Wire Wire Line + 5850 2500 6000 2500 +$Comp +L PWR_FLAG #FLG01 +U 1 1 508152A0 +P 3450 3200 +F 0 "#FLG01" H 3450 3470 30 0001 C CNN +F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN + 1 3450 3200 + 1 0 0 -1 +$EndComp +$Comp +L R Rout1 +U 1 1 50813F5B +P 5600 2500 +F 0 "Rout1" V 5680 2500 50 0000 C CNN +F 1 "75" V 5600 2500 50 0000 C CNN + 1 5600 2500 + 0 1 1 0 +$EndComp +$Comp +L VCVS Eout1 +U 1 1 50813F0F +P 5200 2900 +F 0 "Eout1" H 5000 3000 50 0000 C CNN +F 1 "1" H 5000 2850 50 0000 C CNN + 1 5200 2900 + 0 1 1 0 +$EndComp +$Comp +L C Cbw1 +U 1 1 50813EE0 +P 4550 2900 +F 0 "Cbw1" H 4600 3000 50 0000 L CNN +F 1 "31.85e-9" H 4600 2800 50 0000 L CNN + 1 4550 2900 + 1 0 0 -1 +$EndComp +$Comp +L R Rbw1 +U 1 1 50813EAB +P 4150 2500 +F 0 "Rbw1" V 4230 2500 50 0000 C CNN +F 1 "0.5e6" V 4150 2500 50 0000 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 50813E0D +P 3700 3400 +F 0 "#PWR02" H 3700 3400 30 0001 C CNN +F 1 "GND" H 3700 3330 30 0001 C CNN + 1 3700 3400 + 1 0 0 -1 +$EndComp +$Comp +L VCVS Ein1 +U 1 1 50813D7C +P 3650 2850 +F 0 "Ein1" H 3450 2950 50 0000 C CNN +F 1 "100e3" H 3450 2800 50 0000 C CNN + 1 3650 2850 + 0 1 1 0 +$EndComp +$Comp +L R Rin1 +U 1 1 50813C57 +P 3000 2850 +F 0 "Rin1" V 3080 2850 50 0000 C CNN +F 1 "2e6" V 3000 2850 50 0000 C CNN + 1 3000 2850 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ua741/ua741.sub b/src/SubcircuitLibrary/ua741/ua741.sub new file mode 100644 index 00000000..ad26c001 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741.sub @@ -0,0 +1,12 @@ +* Subcircuit ua741 +.subckt ua741 6 7 3 +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist +rout1 3 2 75 +eout1 2 0 1 0 1 +cbw1 1 0 31.85e-9 +rbw1 1 4 0.5e6 +ein1 4 0 7 6 100e3 +rin1 7 6 2e6 +* Control Statements + +.ends ua741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml b/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml new file mode 100644 index 00000000..9c7bb530 --- /dev/null +++ b/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py index bcc0fd95..16e440ab 100644 --- a/src/configuration/Appconfig.py +++ b/src/configuration/Appconfig.py @@ -33,6 +33,8 @@ class Appconfig(QtGui.QWidget): default_workspace = {"workspace":home} #Current Project detail current_project = {"ProjectName":None} + #Current Subcircuit detail + current_subcircuit = {"SubcircuitName":None} #Workspace detail workspace_text = '''eSim stores your project in a folder called a eSim-Workspace. You can choose a different workspace folder to use for this session.''' procThread_list = [] diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py index 01e445a9..9fce17b0 100755 --- a/src/frontEnd/Application.py +++ b/src/frontEnd/Application.py @@ -109,6 +109,9 @@ class Application(QtGui.QMainWindow): self.model = QtGui.QAction(QtGui.QIcon('../../images/model.png'),'<b>Model Editor</b>',self) self.model.triggered.connect(self.open_modelEditor) + self.subcircuit=QtGui.QAction(QtGui.QIcon('../../images/subckt.png'),'<b>Subcircuit</b>',self) + self.subcircuit.triggered.connect(self.open_subcircuit) + #Adding Action Widget to tool bar self.lefttoolbar = QtGui.QToolBar('Left ToolBar') self.addToolBar(QtCore.Qt.LeftToolBarArea, self.lefttoolbar) @@ -118,6 +121,7 @@ class Application(QtGui.QMainWindow): self.lefttoolbar.addAction(self.footprint) self.lefttoolbar.addAction(self.pcb) self.lefttoolbar.addAction(self.model) + self.lefttoolbar.addAction(self.subcircuit) self.lefttoolbar.setOrientation(QtCore.Qt.Vertical) self.lefttoolbar.setIconSize(QSize(40,40)) @@ -179,6 +183,11 @@ class Application(QtGui.QMainWindow): self.msg = QtGui.QErrorMessage() self.msg.showMessage('Please select the project first. You can either create new project or open existing project') self.msg.setWindowTitle("Error Message") + + def open_subcircuit(self): + print "Subcircuit editor is called" + self.obj_appconfig.print_info('Subcircuit editor is called') + self.obj_Mainview.obj_dockarea.subcircuiteditor() def exit_project(self): diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py index e700dbd6..e87fea99 100644 --- a/src/frontEnd/DockArea.py +++ b/src/frontEnd/DockArea.py @@ -3,6 +3,7 @@ from ngspiceSimulation.pythonPlotting import plotWindow from ngspiceSimulation.NgspiceWidget import NgspiceWidget from configuration.Appconfig import Appconfig from modelEditor.ModelEditor import ModelEditorclass +from subcircuit.Subcircuit import Subcircuit import os dockList = ['Welcome'] @@ -153,9 +154,29 @@ class DockArea(QtGui.QMainWindow): count = count + 1 + def subcircuiteditor(self): + """ + This function creates a widget for different subcircuit options + """ + global count + self.subcktWidget=QtGui.QWidget() + self.subcktLayout=QtGui.QVBoxLayout() + self.subcktLayout.addWidget(Subcircuit()) + + self.subcktWidget.setLayout(self.subcktLayout) + dock['Subcircuit-'+str(count)] = QtGui.QDockWidget('Subcircuit-'+str(count)) + dock['Subcircuit-'+str(count)].setWidget(self.subcktWidget) + self.addDockWidget(QtCore.Qt.TopDockWidgetArea, dock['Subcircuit-'+str(count)]) + self.tabifyDockWidget(dock['Welcome'],dock['Subcircuit-'+str(count)]) + """ + #CSS + dock['Plotting-'+str(count)].setStyleSheet(" \ + QWidget { border-radius: 15px; border: 1px solid gray; padding: 5px; width: 200px; height: 150px; } \ + ") + """ + dock['Subcircuit-'+str(count)].setVisible(True) + dock['Subcircuit-'+str(count)].setFocus() + dock['Subcircuit-'+str(count)].raise_() - - - -
\ No newline at end of file + count = count + 1
\ No newline at end of file diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py index 96d00a08..035a8688 100644 --- a/src/frontEnd/Workspace.py +++ b/src/frontEnd/Workspace.py @@ -69,7 +69,7 @@ class Workspace(QtGui.QWidget): self.setWindowTitle("eSim") self.setWindowFlags(QtCore.Qt.WindowStaysOnTopHint) self.note.setReadOnly(True) - self.setWindowIcon(QtGui.QIcon('../images/logo.png')) + self.setWindowIcon(QtGui.QIcon('../../images/logo.png')) self.setLayout(self.grid) self.show() diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py index 739963ba..baf842d9 100644 --- a/src/kicadtoNgspice/Convert.py +++ b/src/kicadtoNgspice/Convert.py @@ -1,3 +1,5 @@ +from PyQt4 import QtGui + import os import sys import shutil @@ -352,11 +354,69 @@ class Convert: #Adding .include line to Schematic Info at the start of line for item in list(set(includeLine)): schematicInfo.insert(0,item) - - - + return schematicInfo + def addSubcircuit(self,schematicInfo,kicadFile): + """ + This function add the subcircuit to schematicInfo + """ + print "Adding Subcircuit to Schematic info file" + + (projpath,filename) = os.path.split(kicadFile) + + subList = self.obj_track.subcircuitTrack + subLine = {} #Key:Index, Value:with its updated line in the form of list + includeLine = [] #All .include line list + if len(self.obj_track.subcircuitList) != len(self.obj_track.subcircuitTrack): + self.msg = QtGui.QErrorMessage() + self.msg.showMessage("Conversion failed. Please add all Subcircuits.") + self.msg.setWindowTitle("Error Message") + self.msg.show() + raise Exception('All subcircuit directories need to be specified.') + elif not subList: + print "No Subcircuit Added in the schematic" + pass + else: + for eachline in schematicInfo: + words = eachline.split() + if words[0] in subList: + print "Found Subcircuit line" + index = schematicInfo.index(eachline) + completeSubPath = subList[words[0]] + (subpath,subname) = os.path.split(completeSubPath) + print "Library Path :",subpath + #Copying library from devicemodelLibrary to Project Path + + #Replace last word with library name + words[-1] = subname.split('.')[0] + subLine[index] = words + includeLine.append(".include "+subname+".sub") + + src = completeSubPath + dst = projpath + print os.listdir(src) + for files in os.listdir(src): + if os.path.isfile(os.path.join(src,files)): + if files != "analysis": + shutil.copy2(os.path.join(src,files),dst) + else: + pass + + + #Adding subcircuit line to schematicInfo + for index,value in subLine.iteritems(): + #Update the subcircuit line + strLine = " ".join(str(item) for item in value) + schematicInfo[index] = strLine + + #This has to be second i.e after subcircuitLine details + #Adding .include line to Schematic Info at the start of line + for item in list(set(includeLine)): + schematicInfo.insert(0,item) + + return schematicInfo + def getRefrenceName(self,libname,libpath): libname = libname.replace('.lib','.xml') library = os.path.join(libpath,libname) diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py index cf70eab9..7e8617ae 100644 --- a/src/kicadtoNgspice/KicadtoNgspice.py +++ b/src/kicadtoNgspice/KicadtoNgspice.py @@ -23,6 +23,7 @@ import Analysis import Source import Model import DeviceModel +import SubcircuitTab import Convert import TrackWidget @@ -107,8 +108,11 @@ class MainWindow(QtGui.QWidget): obj_devicemodel=DeviceModel.DeviceModel(schematicInfo) self.deviceModelTab.setWidget(obj_devicemodel) self.deviceModelTab.setWidgetResizable(True) - - + global obj_subcircuitTab + self.subcircuitTab = QtGui.QScrollArea() + obj_subcircuitTab = SubcircuitTab.SubcircuitTab(schematicInfo) + self.subcircuitTab.setWidget(obj_subcircuitTab) + self.subcircuitTab.setWidgetResizable(True) self.tabWidget = QtGui.QTabWidget() #self.tabWidget.TabShape(QtGui.QTabWidget.Rounded) @@ -116,6 +120,7 @@ class MainWindow(QtGui.QWidget): self.tabWidget.addTab(self.sourceTab,"Source Details") self.tabWidget.addTab(self.modelTab,"NgSpice Model") self.tabWidget.addTab(self.deviceModelTab,"Device Modeling") + self.tabWidget.addTab(self.subcircuitTab,"Subcircuits") self.mainLayout = QtGui.QVBoxLayout() self.mainLayout.addWidget(self.tabWidget) #self.mainLayout.addStretch(1) @@ -388,7 +393,9 @@ class MainWindow(QtGui.QWidget): #Adding Device Library to SchematicInfo schematicInfo = self.obj_convert.addDeviceLibrary(schematicInfo,kicadFile) - + #Adding Subcircuit Library to SchematicInfo + schematicInfo = self.obj_convert.addSubcircuit(schematicInfo, kicadFile) + analysisoutput = self.obj_convert.analysisInsertor(self.obj_track.AC_entry_var["ITEMS"], self.obj_track.DC_entry_var["ITEMS"], self.obj_track.TRAN_entry_var["ITEMS"], @@ -411,8 +418,12 @@ class MainWindow(QtGui.QWidget): print "There was error while converting kicad to ngspice" self.close() - - + # Generate .sub file from .cir.out file if it is a subcircuit + subPath = os.path.splitext(kicadFile)[0] + + if len(sys.argv)>2: + if sys.argv[2] == "sub": + self.createSubFile(subPath) def createNetlistFile(self,schematicInfo): print "Creating Final netlist" @@ -508,7 +519,63 @@ class MainWindow(QtGui.QWidget): out.close() - + def createSubFile(self,subPath): + self.project = subPath + self.projName = os.path.basename(self.project) + if os.path.exists(self.project+".cir.out"): + try: + f = open(self.project+".cir.out") + except : + print("Error in opening circuit file.") + else: + print self.projName + ".cir.out does not exist. Please create a spice netlist." + + # Read the data from file + data=f.read() + # Close the file + + f.close() + newNetlist=[] + netlist=iter(data.splitlines()) + for eachline in netlist: + eachline=eachline.strip() + if len(eachline)<1: + continue + words=eachline.split() + if eachline[2] == 'u': + if words[len(words)-1] == "port": + subcktInfo = ".subckt "+self.projName+" " + for i in range(2,len(words)-1): + subcktInfo+=words[i]+" " + continue + if words[0] == ".end" or words[0] == ".ac" or words[0] == ".dc" or words[0] == ".tran" or words[0] == '.disto' or words[0] == '.noise' or words[0] == '.op' or words[0] == '.pz' or words[0] == '.sens' or words[0] == '.tf': + continue + elif words[0] == ".control": + while words[0] != ".endc": + eachline=netlist.next() + eachline=eachline.strip() + if len(eachline)<1: + continue + words=eachline.split() + else: + newNetlist.append(eachline) + + outfile=self.project+".sub" + out=open(outfile,"w") + out.writelines("* Subcircuit " + self.projName) + out.writelines('\n') + out.writelines(subcktInfo) + out.writelines('\n') + + for i in range(len(newNetlist),0,-1): + newNetlist.insert(i,'\n') + + out.writelines(newNetlist) + out.writelines('\n') + + out.writelines('.ends ' + self.projName) + print "The subcircuit has been written in "+self.projName+".sub" + #Main Function diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py index 9295a058..fa75320f 100644 --- a/src/kicadtoNgspice/Processing.py +++ b/src/kicadtoNgspice/Processing.py @@ -174,116 +174,118 @@ class PrcocessNetlist: print "Words",words print "compName",compName #Looking if model file is present - xmlfile = compType+".xml" #XML Model File - count = 0 #Check if model of same name is present - modelPath = [] - all_dir = [x[0] for x in os.walk(PrcocessNetlist.modelxmlDIR)] - for each_dir in all_dir: - all_file = os.listdir(each_dir) - if xmlfile in all_file: - count += 1 - modelPath.append(os.path.join(each_dir,xmlfile)) - - if count > 1: - multipleModelList.append(modelPath) - elif count == 0: - unknownModelList.append(compType) - elif count == 1: - try: - print "Start Parsing :",modelPath - tree = ET.parse(modelPath[0]) - - root = tree.getroot() - #Getting number of nodes for model and title - for child in tree.iter(): - if child.tag == 'node_number': - num_of_nodes = int(child.text) - elif child.tag == 'title': - title = child.text+" "+compName - elif child.tag == 'name': - modelname = child.text - elif child.tag == 'type': - #Checking for Analog and Digital - type = child.text - elif child.tag == 'split': - splitDetail = child.text - + if compType != "port": + xmlfile = compType+".xml" #XML Model File + count = 0 #Check if model of same name is present + modelPath = [] + all_dir = [x[0] for x in os.walk(PrcocessNetlist.modelxmlDIR)] + for each_dir in all_dir: + all_file = os.listdir(each_dir) + if xmlfile in all_file: + count += 1 + modelPath.append(os.path.join(each_dir,xmlfile)) + + if count > 1: + multipleModelList.append(modelPath) + elif count == 0: + unknownModelList.append(compType) + elif count == 1: + try: + print "Start Parsing :",modelPath + tree = ET.parse(modelPath[0]) - for param in tree.findall('param'): - for item in param: - #print "Tags ",item.tag - #print "Value",item.text - if 'vector'in item.attrib: - print "Tag having vector attribute",item.tag,item.attrib['vector'] - temp_count = 1 - temp_list = [] - for i in range(0,int(item.attrib['vector'])): - temp_list.append(item.text+" "+str(temp_count)) - temp_count += 1 - if 'default' in item.attrib: - paramDict[item.tag+":"+item.attrib['default']] = temp_list - else: - paramDict[item.tag] = item.text - - else: - if 'default' in item.attrib: - paramDict[item.tag+":"+item.attrib['default']] = item.text + root = tree.getroot() + #Getting number of nodes for model and title + for child in tree.iter(): + if child.tag == 'node_number': + num_of_nodes = int(child.text) + elif child.tag == 'title': + title = child.text+" "+compName + elif child.tag == 'name': + modelname = child.text + elif child.tag == 'type': + #Checking for Analog and Digital + type = child.text + elif child.tag == 'split': + splitDetail = child.text + + + for param in tree.findall('param'): + for item in param: + #print "Tags ",item.tag + #print "Value",item.text + if 'vector'in item.attrib: + print "Tag having vector attribute",item.tag,item.attrib['vector'] + temp_count = 1 + temp_list = [] + for i in range(0,int(item.attrib['vector'])): + temp_list.append(item.text+" "+str(temp_count)) + temp_count += 1 + if 'default' in item.attrib: + paramDict[item.tag+":"+item.attrib['default']] = temp_list + else: + paramDict[item.tag] = item.text + else: - paramDict[item.tag] = item.text + if 'default' in item.attrib: + paramDict[item.tag+":"+item.attrib['default']] = item.text + else: + paramDict[item.tag] = item.text + - - print "Number of Nodes : ",num_of_nodes - print "Title : ",title - print "Parameters",paramDict - #Creating line for adding model line in schematic - if splitDetail == 'None': - modelLine = "a"+str(k)+" " - for i in range(1,num_of_nodes+1): - modelLine += words[i]+" " - modelLine += compName - - else: - print "Split Details :",splitDetail - modelLine = "a"+str(k)+" " - vectorDetail = splitDetail.split(':') - print "Vector Details",vectorDetail - pos = 1 #Node position - for item in vectorDetail: - try: - if item.split("-")[1] == 'V': - print "Vector" - modelLine += "[" - for i in range(0,int(item.split("-")[0])): - modelLine += words[pos]+" " - pos += 1 - modelLine += "] " - elif item.split("-")[1] == 'NV': - print "Non Vector" - for i in range(0,int(item.split("-")[0])): - modelLine += words[pos]+" " - pos += 1 + print "Number of Nodes : ",num_of_nodes + print "Title : ",title + print "Parameters",paramDict + #Creating line for adding model line in schematic + if splitDetail == 'None': + modelLine = "a"+str(k)+" " + for i in range(1,num_of_nodes+1): + modelLine += words[i]+" " + modelLine += compName - except: - print "There is error while processing Vector Details" - sys.exit(2) - modelLine += compName - - print "Final Model Line :",modelLine - try: - schematicInfo.append(modelLine) - k=k+1 - except Exception as e: - print "Error while appending ModelLine ",modelLine - print "Exception Message : ",str(e) - #Insert comment at remove line - schematicInfo.insert(index,"* "+compline) - comment = "* Schematic Name: "+compType+", NgSpice Name: "+modelname - #Here instead of adding compType(use for XML), added modelName(Unique Model Name) - modelList.append([index,compline,modelname,compName,comment,title,type,paramDict]) - except: - print "Unable to parse the model, Please check your your XML file" - sys.exit(2) - + else: + print "Split Details :",splitDetail + modelLine = "a"+str(k)+" " + vectorDetail = splitDetail.split(':') + print "Vector Details",vectorDetail + pos = 1 #Node position + for item in vectorDetail: + try: + if item.split("-")[1] == 'V': + print "Vector" + modelLine += "[" + for i in range(0,int(item.split("-")[0])): + modelLine += words[pos]+" " + pos += 1 + modelLine += "] " + elif item.split("-")[1] == 'NV': + print "Non Vector" + for i in range(0,int(item.split("-")[0])): + modelLine += words[pos]+" " + pos += 1 + + except: + print "There is error while processing Vector Details" + sys.exit(2) + modelLine += compName + + print "Final Model Line :",modelLine + try: + schematicInfo.append(modelLine) + k=k+1 + except Exception as e: + print "Error while appending ModelLine ",modelLine + print "Exception Message : ",str(e) + #Insert comment at remove line + schematicInfo.insert(index,"* "+compline) + comment = "* Schematic Name: "+compType+", NgSpice Name: "+modelname + #Here instead of adding compType(use for XML), added modelName(Unique Model Name) + modelList.append([index,compline,modelname,compName,comment,title,type,paramDict]) + except: + print "Unable to parse the model, Please check your your XML file" + sys.exit(2) + else: + schematicInfo.insert(index,"* "+compline) #print "Count",count #print "UnknownModelList",unknownModelList #print "MultipleModelList",multipleModelList diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py new file mode 100644 index 00000000..2614d75a --- /dev/null +++ b/src/kicadtoNgspice/SubcircuitTab.py @@ -0,0 +1,103 @@ +from PyQt4 import QtGui + +import TrackWidget +from projManagement import Validation + + +class SubcircuitTab(QtGui.QWidget): + """ + This class creates Subcircuit Tab in KicadtoNgspice Window + It dynamically creates the widget for subcircuits. + """ + + def __init__(self,schematicInfo): + QtGui.QWidget.__init__(self) + + #Creating track widget object + self.obj_trac = TrackWidget.TrackWidget() + + #Creating validation object + self.obj_validation = Validation.Validation() + #Row and column count + self.row = 0 + self.count = 1 #Entry count + self.entry_var = {} + + #List to hold information about device + self.subDetail = {} + + #Stores the number of ports in each subcircuit + self.numPorts = [] + + #Set Layout + self.grid = QtGui.QGridLayout() + self.setLayout(self.grid) + + for eachline in schematicInfo: + words = eachline.split() + if eachline[0] == 'x': + print "Words",words[0] + self.obj_trac.subcircuitList.append(words) + subbox=QtGui.QGroupBox() + subgrid=QtGui.QGridLayout() + subbox.setTitle("Add subcircuit for "+words[len(words)-1]) + self.entry_var[self.count] = QtGui.QLineEdit() + self.entry_var[self.count].setText("") + subgrid.addWidget(self.entry_var[self.count],self.row,1) + self.addbtn = QtGui.QPushButton("Add") + self.addbtn.setObjectName("%d" %self.count) + #Send the number of ports specified with the given subcircuit for verification. + #eg. If the line is 'x1 4 0 3 ua741', there are 3 ports(4, 0 and 3). + self.numPorts.append(len(words)-2) + print "NUMPORTS",self.numPorts + self.addbtn.clicked.connect(self.trackSubcircuit) + subgrid.addWidget(self.addbtn,self.row,2) + subbox.setLayout(subgrid) + + #CSS + subbox.setStyleSheet(" \ + QGroupBox { border: 1px solid gray; border-radius: 9px; margin-top: 0.5em; } \ + QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px 0 3px; } \ + ") + + self.grid.addWidget(subbox) + + #Adding Device Details + self.subDetail[self.count] = words[0] + + #Increment row and widget count + self.row = self.row+1 + self.count = self.count+1 + + self.show() + + + def trackSubcircuit(self): + """ + This function is use to keep track of all Device Model widget + """ + print "Calling Track Subcircuit function" + sending_btn = self.sender() + #print "Object Called is ",sending_btn.objectName() + self.widgetObjCount = int(sending_btn.objectName()) + + self.subfile = str(QtGui.QFileDialog.getExistingDirectory(self,"Open Subcircuit","../SubcircuitLibrary")) + self.reply = self.obj_validation.validateSub(self.subfile,self.numPorts[self.widgetObjCount - 1]) + if self.reply == "True": + #Setting Library to Text Edit Line + self.entry_var[self.widgetObjCount].setText(self.subfile) + self.subName = self.subDetail[self.widgetObjCount] + + #Storing to track it during conversion + + self.obj_trac.subcircuitTrack[self.subName] = self.subfile + elif self.reply == "PORT": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("Please select a Subcircuit with correct number of ports.") + self.msg.setWindowTitle("Error Message") + self.msg.show() + elif self.reply == "DIREC": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage("Please select a valid Subcircuit directory (Containing '.sub' file).") + self.msg.setWindowTitle("Error Message") + self.msg.show()
\ No newline at end of file diff --git a/src/kicadtoNgspice/TrackWidget.py b/src/kicadtoNgspice/TrackWidget.py index 23991a37..e97b317d 100644 --- a/src/kicadtoNgspice/TrackWidget.py +++ b/src/kicadtoNgspice/TrackWidget.py @@ -21,4 +21,9 @@ class TrackWidget: model_entry_var = {} #Track Widget for Device Model detail - deviceModelTrack = {}
\ No newline at end of file + deviceModelTrack = {} + + #Track Widget for Subcircuits where directory has been selected + subcircuitTrack = {} + #Track subcircuits which are specified in .cir file + subcircuitList = []
\ No newline at end of file diff --git a/src/projManagement/Validation.py b/src/projManagement/Validation.py index a3d84979..ac0473af 100644 --- a/src/projManagement/Validation.py +++ b/src/projManagement/Validation.py @@ -83,7 +83,31 @@ class Validation: else: return False - - - -
\ No newline at end of file + def validateSub(self,subDir,givenNum): + """ + This function checks if ".sub" file is present. + """ + subName = os.path.basename(str(subDir)) + lookSub = os.path.join(str(subDir),subName+".sub") + #Check existence of project + if os.path.exists(lookSub): + f = open(lookSub) + data=f.read() + f.close() + netlist=data.splitlines() + for eachline in netlist: + eachline=eachline.strip() + if len(eachline)<1: + continue + words=eachline.split() + if words[0] == '.subckt': + #The number of ports is specified in this line + #eg. '.subckt ua741 6 7 3' has 3 ports (6, 7 and 3). + numPorts = len(words) - 2 + print "Looksub",lookSub,givenNum,numPorts + if numPorts != givenNum: + return "PORT" + else: + return "True" + else: + return "DIREC"
\ No newline at end of file diff --git a/src/subcircuit/Subcircuit.py b/src/subcircuit/Subcircuit.py new file mode 100644 index 00000000..94ca37e4 --- /dev/null +++ b/src/subcircuit/Subcircuit.py @@ -0,0 +1,62 @@ +from PyQt4 import QtCore, QtGui +from configuration.Appconfig import Appconfig +from projManagement.Validation import Validation +from subcircuit.newSub import NewSub +from subcircuit.openSub import openSub +from subcircuit.convertSub import convertSub + +class Subcircuit(QtGui.QWidget): + """ + This class creates Subcircuit GUI. + """ + def __init__(self,parent=None): + super(Subcircuit, self).__init__() + QtGui.QWidget.__init__(self) + self.obj_appconfig=Appconfig() + self.obj_validation=Validation() + + self.layout = QtGui.QVBoxLayout() + self.splitter= QtGui.QSplitter() + self.splitter.setOrientation(QtCore.Qt.Vertical) + + self.newbtn = QtGui.QPushButton('New Subcircuit Schematic') + self.newbtn.setFixedSize(200,40) + self.newbtn.clicked.connect(self.newsch) + self.editbtn = QtGui.QPushButton('Edit Subcircuit Schematic') + self.editbtn.setFixedSize(200,40) + self.editbtn.clicked.connect(self.editsch) + self.convertbtn = QtGui.QPushButton('Convert Kicad to Ngspice') + self.convertbtn.setFixedSize(200,40) + self.convertbtn.clicked.connect(self.convertsch) + + self.hbox = QtGui.QHBoxLayout() + self.hbox.addWidget(self.newbtn) + self.hbox.addWidget(self.editbtn) + self.hbox.addWidget(self.convertbtn) + self.hbox.addStretch(1) + + self.vbox = QtGui.QVBoxLayout() + self.vbox.addLayout(self.hbox) + self.vbox.addStretch(1) + + self.setLayout(self.vbox) + self.show() + + def newsch(self): + text,ok = QtGui.QInputDialog.getText(self, 'New Schematic','Enter Schematic Name:') + if ok: + self.schematic_name = (str(text)) + self.subcircuit = NewSub() + self.subcircuit.createSubcircuit(self.schematic_name) + + else: + print "No subcircuit created" + + + def editsch(self): + self.obj_opensubcircuit = openSub() + self.obj_opensubcircuit.body() + + def convertsch(self): + self.obj_convertsubcircuit = convertSub() + self.obj_convertsubcircuit.createSub()
\ No newline at end of file diff --git a/src/subcircuit/__init__.py b/src/subcircuit/__init__.py new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/src/subcircuit/__init__.py diff --git a/src/subcircuit/convertSub.py b/src/subcircuit/convertSub.py new file mode 100644 index 00000000..bb045e3b --- /dev/null +++ b/src/subcircuit/convertSub.py @@ -0,0 +1,45 @@ +from PyQt4 import QtGui,QtCore +from projManagement.Validation import Validation +from projManagement import Worker +from configuration.Appconfig import Appconfig +import os + +class convertSub(QtGui.QWidget): + """ + This class is called when User create new Project. + """ + + def __init__(self): + super(convertSub, self).__init__() + self.obj_validation = Validation() + self.obj_appconfig=Appconfig() + + def createSub(self): + """ + This function create command to call kicad to Ngspice converter. + """ + print "Open Kicad to Ngspice Conversion" + self.projDir = self.obj_appconfig.current_subcircuit["SubcircuitName"] + #Validating if current project is available or not + if self.obj_validation.validateKicad(self.projDir): + #print "Project is present" + #Checking if project has .cir file or not + if self.obj_validation.validateCir(self.projDir): + #print "CIR file present" + self.projName = os.path.basename(self.projDir) + self.project = os.path.join(self.projDir,self.projName) + + #Creating a command to run + self.cmd = "python ../kicadtoNgspice/KicadtoNgspice.py "+self.project+".cir "+"sub" + os.system(self.cmd) +# self.obj_workThread = Worker.WorkerThread(self.cmd) +# self.obj_workThread.start() + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('The subcircuit does not contain any Kicad netlist file for conversion.') + self.msg.setWindowTitle("Error Message") + + else: + self.msg = QtGui.QErrorMessage(None) + self.msg.showMessage('Please select the subcircuit first. You can either create new subcircuit or open existing subcircuit') + self.msg.setWindowTitle("Error Message")
\ No newline at end of file diff --git a/src/subcircuit/newSub.py b/src/subcircuit/newSub.py new file mode 100644 index 00000000..7ea247ab --- /dev/null +++ b/src/subcircuit/newSub.py @@ -0,0 +1,65 @@ +from PyQt4 import QtGui,QtCore +from projManagement.Validation import Validation +from configuration.Appconfig import Appconfig +from projManagement import Worker +import os + +class NewSub(QtGui.QWidget): + """ + This class is called when User create new Project. + """ + + def __init__(self): + super(NewSub, self).__init__() + self.obj_validation = Validation() + self.obj_appconfig = Appconfig() + + + def createSubcircuit(self,subName): + """ + This function create Subcircuit related directories and files + """ + self.create_schematic = subName + #Checking if Workspace already exist or not + self.schematic_path = (os.path.join(os.path.abspath('..'),'SubcircuitLibrary',self.create_schematic)) + + #Validation for new subcircuit + if self.schematic_path == "": + self.reply = "NONE" + else: + self.reply = self.obj_validation.validateNewproj(str(self.schematic_path)) + + #Checking Validations Response + if self.reply == "VALID": + print "Validated : Creating subcircuit directory" + try: + os.mkdir(self.schematic_path) + self.schematic = os.path.join(self.schematic_path,self.create_schematic) + self.cmd = "eeschema "+self.schematic+".sch" + self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.start() + self.close() + except: + #print "Some Thing Went Wrong" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('Unable to create subcircuit. Please make sure you have write permission on '+self.schematic_path) + self.msg.setWindowTitle("Error Message") + + self.obj_appconfig.current_subcircuit['SubcircuitName'] = self.schematic_path + + elif self.reply == "CHECKEXIST": + #print "Project already exist" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The subcircuit "'+self.create_schematic+'" already exist.Please select the different name or delete existing subcircuit') + self.msg.setWindowTitle("Error Message") + + elif self.reply == "CHECKNAME": + #print "Name is not proper" + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The subcircuit name should not contain space between them') + self.msg.setWindowTitle("Error Message") + + elif self.reply == "NONE": + self.msg = QtGui.QErrorMessage(self) + self.msg.showMessage('The subcircuit name cannot be empty') + self.msg.setWindowTitle("Error Message")
\ No newline at end of file diff --git a/src/subcircuit/openSub.py b/src/subcircuit/openSub.py new file mode 100644 index 00000000..fb349f0a --- /dev/null +++ b/src/subcircuit/openSub.py @@ -0,0 +1,24 @@ +from PyQt4 import QtGui +from configuration.Appconfig import Appconfig +from projManagement.Worker import WorkerThread +import os + + +class openSub(QtGui.QWidget): + """ + This class is called when User click on Open Project Button + """ + def __init__(self): + super(openSub, self).__init__() + self.obj_appconfig = Appconfig() + + def body(self): + self.editfile = str(QtGui.QFileDialog.getExistingDirectory(None,"Open File","../SubcircuitLibrary")) + if self.editfile: + self.obj_Appconfig = Appconfig() + self.obj_Appconfig.current_subcircuit['SubcircuitName'] = self.editfile + self.schname = os.path.basename(self.editfile) + self.editfile = os.path.join(self.editfile,self.schname) + self.cmd = "eeschema "+self.editfile+".sch " + self.obj_workThread = WorkerThread(self.cmd) + self.obj_workThread.start()
\ No newline at end of file |