diff options
| author | rahulp13 | 2020-02-14 15:16:35 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
| commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
| tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /src | |
| parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
| download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip | |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'src')
358 files changed, 20310 insertions, 11622 deletions
diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib index 9d70ade9..e16831e4 100644 --- a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib +++ b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib @@ -1,77 +1,77 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_adder
-#
-DEF half_adder X 0 40 Y Y 1 F N
-F0 "X" 900 500 60 H V C CNN
-F1 "half_adder" 900 400 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S 500 800 1250 0 0 1 0 N
-X IN1 1 300 700 200 R 50 50 1 1 I
-X IN2 2 300 100 200 R 50 50 1 1 I
-X SUM 3 1450 700 200 L 50 50 1 1 O
-X COUT 4 1450 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir index 08e3ccc8..0f4deb6c 100644 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir @@ -1,17 +1,17 @@ -* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and
-U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and
-U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and
-U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and
-X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder
-X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and +U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and +U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and +X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder +X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT + +.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out index 351629fd..71766bd8 100644 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out @@ -1,31 +1,31 @@ -* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-
-.include half_adder.sub
-* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir + +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro index 944ec056..eafbfb80 100644 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.pro +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.pro @@ -1,74 +1,74 @@ -update=03/07/19 09:55:40
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=adc-dac
-LibName2=memory
-LibName3=xilinx
-LibName4=microcontrollers
-LibName5=dsp
-LibName6=microchip
-LibName7=analog_switches
-LibName8=motorola
-LibName9=texas
-LibName10=intel
-LibName11=audio
-LibName12=interface
-LibName13=digital-audio
-LibName14=philips
-LibName15=display
-LibName16=cypress
-LibName17=siliconi
-LibName18=opto
-LibName19=atmel
-LibName20=contrib
-LibName21=power
-LibName22=device
-LibName23=transistors
-LibName24=conn
-LibName25=linear
-LibName26=regul
-LibName27=74xx
-LibName28=cmos4000
-LibName29=eSim_Analog
-LibName30=eSim_Devices
-LibName31=eSim_Digital
-LibName32=eSim_Hybrid
-LibName33=eSim_Miscellaneous
-LibName34=eSim_Power
-LibName35=eSim_Sources
-LibName36=eSim_Subckt
-LibName37=eSim_User
-LibName38=eSim_Plot
-LibName39=eSim_PSpice
-LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt
-
+update=03/07/19 09:55:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot +LibName39=eSim_PSpice +LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch index 2629beec..0ba61912 100644 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.sch +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sch @@ -1,284 +1,284 @@ -EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:2bitmul-cache
-EELAYER 25 0
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- 6 7300 5300
- 0 -1 -1 0
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C7FC641
-P 6750 5150
-F 0 "U1" H 6800 5250 30 0000 C CNN
-F 1 "PORT" H 6750 5150 30 0000 C CNN
-F 2 "" H 6750 5150 60 0000 C CNN
-F 3 "" H 6750 5150 60 0000 C CNN
- 7 6750 5150
- 0 -1 -1 0
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C7FC698
-P 6150 5250
-F 0 "U1" H 6200 5350 30 0000 C CNN
-F 1 "PORT" H 6150 5250 30 0000 C CNN
-F 2 "" H 6150 5250 60 0000 C CNN
-F 3 "" H 6150 5250 60 0000 C CNN
- 8 6150 5250
- 0 -1 -1 0
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C7FC6EC
-P 8250 850
-F 0 "U1" H 8300 950 30 0000 C CNN
-F 1 "PORT" H 8250 850 30 0000 C CNN
-F 2 "" H 8250 850 60 0000 C CNN
-F 3 "" H 8250 850 60 0000 C CNN
- 1 8250 850
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C7FC815
-P 7900 850
-F 0 "U1" H 7950 950 30 0000 C CNN
-F 1 "PORT" H 7900 850 30 0000 C CNN
-F 2 "" H 7900 850 60 0000 C CNN
-F 3 "" H 7900 850 60 0000 C CNN
- 2 7900 850
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C7FC857
-P 7550 850
-F 0 "U1" H 7600 950 30 0000 C CNN
-F 1 "PORT" H 7550 850 30 0000 C CNN
-F 2 "" H 7550 850 60 0000 C CNN
-F 3 "" H 7550 850 60 0000 C CNN
- 3 7550 850
- 0 1 1 0
-$EndComp
-Connection ~ 8250 2250
-Wire Wire Line
- 7900 1100 7900 2150
-Wire Wire Line
- 7900 2150 7550 2150
-Connection ~ 7550 2450
-Wire Wire Line
- 7550 1100 7550 2100
-Wire Wire Line
- 7550 2100 7450 2100
-Connection ~ 7450 2350
-Wire Wire Line
- 7200 1050 7200 2100
-Wire Wire Line
- 7200 2100 6800 2100
-Wire Wire Line
- 6800 2100 6800 2350
-Connection ~ 6800 2350
-Wire Wire Line
- 8200 3400 8200 5050
-$Comp
-L PORT U1
-U 4 1 5C7FC898
-P 7200 800
-F 0 "U1" H 7250 900 30 0000 C CNN
-F 1 "PORT" H 7200 800 30 0000 C CNN
-F 2 "" H 7200 800 60 0000 C CNN
-F 3 "" H 7200 800 60 0000 C CNN
- 4 7200 800
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 7300 5050 7300 4850
-Wire Wire Line
- 7300 4850 7900 4850
-Wire Wire Line
- 7900 4850 7900 4800
-Wire Wire Line
- 6750 4800 6750 4900
-Wire Wire Line
- 6150 4800 6150 5000
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:2bitmul-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U5 +U 1 1 5C7FC048 +P 8150 2950 +F 0 "U5" H 8150 2950 60 0000 C CNN +F 1 "d_and" H 8200 3050 60 0000 C CNN +F 2 "" H 8150 2950 60 0000 C CNN +F 3 "" H 8150 2950 60 0000 C CNN + 1 8150 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C7FC0BC +P 7450 2950 +F 0 "U4" H 7450 2950 60 0000 C CNN +F 1 "d_and" H 7500 3050 60 0000 C CNN +F 2 "" H 7450 2950 60 0000 C CNN +F 3 "" H 7450 2950 60 0000 C CNN + 1 7450 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C7FC0F4 +P 6950 2950 +F 0 "U3" H 6950 2950 60 0000 C CNN +F 1 "d_and" H 7000 3050 60 0000 C CNN +F 2 "" H 6950 2950 60 0000 C CNN +F 3 "" H 6950 2950 60 0000 C CNN + 1 6950 2950 + 0 1 1 0 +$EndComp +$Comp +L d_and U2 +U 1 1 5C7FC11D +P 6400 2950 +F 0 "U2" H 6400 2950 60 0000 C CNN +F 1 "d_and" H 6450 3050 60 0000 C CNN +F 2 "" H 6400 2950 60 0000 C CNN +F 3 "" H 6400 2950 60 0000 C CNN + 1 6400 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 8150 2500 8150 2350 +Wire Wire Line + 8150 2350 7450 2350 +Wire Wire Line + 7450 2100 7450 2500 +Wire Wire Line + 6950 2500 6950 2350 +Wire Wire Line + 6950 2350 6400 2350 +Wire Wire Line + 6400 2350 6400 2500 +Wire Wire Line + 8250 1100 8250 2500 +Wire Wire Line + 8250 2250 7050 2250 +Wire Wire Line + 7050 2250 7050 2500 +Wire Wire Line + 7550 2150 7550 2500 +Wire Wire Line + 7550 2450 6500 2450 +Wire Wire Line + 6500 2450 6500 2500 +$Comp +L half_adder X2 +U 1 1 5C7FC23A +P 7200 3350 +F 0 "X2" H 8100 3850 60 0000 C CNN +F 1 "half_adder" H 8100 3750 60 0000 C CNN +F 2 "" H 7200 3350 60 0000 C CNN +F 3 "" H 7200 3350 60 0000 C CNN + 1 7200 3350 + 0 1 1 0 +$EndComp +$Comp +L half_adder X1 +U 1 1 5C7FC324 +P 6050 3350 +F 0 "X1" H 6950 3850 60 0000 C CNN +F 1 "half_adder" H 6950 3750 60 0000 C CNN +F 2 "" H 6050 3350 60 0000 C CNN +F 3 "" H 6050 3350 60 0000 C CNN + 1 6050 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 7500 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 3650 +Wire Wire Line + 7000 3400 7300 3400 +Wire Wire Line + 7300 3400 7300 3650 +Wire Wire Line + 7300 4800 7050 4800 +Wire Wire Line + 7050 4800 7050 3600 +Wire Wire Line + 7050 3600 6750 3600 +Wire Wire Line + 6750 3600 6750 3650 +Wire Wire Line + 6450 3400 6450 3650 +Wire Wire Line + 6450 3650 6150 3650 +$Comp +L PORT U1 +U 5 1 5C7FC4F8 +P 8200 5300 +F 0 "U1" H 8250 5400 30 0000 C CNN +F 1 "PORT" H 8200 5300 30 0000 C CNN +F 2 "" H 8200 5300 60 0000 C CNN +F 3 "" H 8200 5300 60 0000 C CNN + 5 8200 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 5C7FC5D7 +P 7300 5300 +F 0 "U1" H 7350 5400 30 0000 C CNN +F 1 "PORT" H 7300 5300 30 0000 C CNN +F 2 "" H 7300 5300 60 0000 C CNN +F 3 "" H 7300 5300 60 0000 C CNN + 6 7300 5300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 5C7FC641 +P 6750 5150 +F 0 "U1" H 6800 5250 30 0000 C CNN +F 1 "PORT" H 6750 5150 30 0000 C CNN +F 2 "" H 6750 5150 60 0000 C CNN +F 3 "" H 6750 5150 60 0000 C CNN + 7 6750 5150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 5C7FC698 +P 6150 5250 +F 0 "U1" H 6200 5350 30 0000 C CNN +F 1 "PORT" H 6150 5250 30 0000 C CNN +F 2 "" H 6150 5250 60 0000 C CNN +F 3 "" H 6150 5250 60 0000 C CNN + 8 6150 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 5C7FC6EC +P 8250 850 +F 0 "U1" H 8300 950 30 0000 C CNN +F 1 "PORT" H 8250 850 30 0000 C CNN +F 2 "" H 8250 850 60 0000 C CNN +F 3 "" H 8250 850 60 0000 C CNN + 1 8250 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 5C7FC815 +P 7900 850 +F 0 "U1" H 7950 950 30 0000 C CNN +F 1 "PORT" H 7900 850 30 0000 C CNN +F 2 "" H 7900 850 60 0000 C CNN +F 3 "" H 7900 850 60 0000 C CNN + 2 7900 850 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 5C7FC857 +P 7550 850 +F 0 "U1" H 7600 950 30 0000 C CNN +F 1 "PORT" H 7550 850 30 0000 C CNN +F 2 "" H 7550 850 60 0000 C CNN +F 3 "" H 7550 850 60 0000 C CNN + 3 7550 850 + 0 1 1 0 +$EndComp +Connection ~ 8250 2250 +Wire Wire Line + 7900 1100 7900 2150 +Wire Wire Line + 7900 2150 7550 2150 +Connection ~ 7550 2450 +Wire Wire Line + 7550 1100 7550 2100 +Wire Wire Line + 7550 2100 7450 2100 +Connection ~ 7450 2350 +Wire Wire Line + 7200 1050 7200 2100 +Wire Wire Line + 7200 2100 6800 2100 +Wire Wire Line + 6800 2100 6800 2350 +Connection ~ 6800 2350 +Wire Wire Line + 8200 3400 8200 5050 +$Comp +L PORT U1 +U 4 1 5C7FC898 +P 7200 800 +F 0 "U1" H 7250 900 30 0000 C CNN +F 1 "PORT" H 7200 800 30 0000 C CNN +F 2 "" H 7200 800 60 0000 C CNN +F 3 "" H 7200 800 60 0000 C CNN + 4 7200 800 + 0 1 1 0 +$EndComp +Wire Wire Line + 7300 5050 7300 4850 +Wire Wire Line + 7300 4850 7900 4850 +Wire Wire Line + 7900 4850 7900 4800 +Wire Wire Line + 6750 4800 6750 4900 +Wire Wire Line + 6150 4800 6150 5000 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub index ce0d022d..e77495a6 100644 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.sub +++ b/src/SubcircuitLibrary/2bitmul/2bitmul.sub @@ -1,25 +1,25 @@ -* Subcircuit 2bitmul
-.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_
-* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir
-.include half_adder.sub
-* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and
-* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and
-* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and
-x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder
-x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder
-a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 2bitmul +.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir +.include half_adder.sub +* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and +* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and +* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and +x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder +x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder +a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 +a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 +a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 2bitmul
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and-cache.lib b/src/SubcircuitLibrary/3_and/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/3_and/3_and-cache.lib +++ b/src/SubcircuitLibrary/3_and/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/3_and/3_and.cir b/src/SubcircuitLibrary/3_and/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/3_and/3_and.cir +++ b/src/SubcircuitLibrary/3_and/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/3_and/3_and.cir.out b/src/SubcircuitLibrary/3_and/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/3_and/3_and.cir.out +++ b/src/SubcircuitLibrary/3_and/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/3_and/3_and.pro b/src/SubcircuitLibrary/3_and/3_and.pro index 0fdf4d25..76df4655 100644 --- a/src/SubcircuitLibrary/3_and/3_and.pro +++ b/src/SubcircuitLibrary/3_and/3_and.pro @@ -1,44 +1,44 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
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-[eeschema/libraries]
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-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/3_and/3_and.sch b/src/SubcircuitLibrary/3_and/3_and.sch index c853bf49..d6ac89f9 100644 --- a/src/SubcircuitLibrary/3_and/3_and.sch +++ b/src/SubcircuitLibrary/3_and/3_and.sch @@ -1,130 +1,130 @@ -EESchema Schematic File Version 2
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-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
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-LIBS:eSim_Power
-LIBS:eSim_PSpice
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-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
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-EELAYER END
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-$EndDescr
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-L d_and U2
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-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
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-$Comp
-L d_and U3
-U 1 1 5C9A2538
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-F 0 "U3" H 5150 2900 60 0000 C CNN
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-F 2 "" H 5150 2900 60 0000 C CNN
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-$Comp
-L PORT U1
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-F 0 "U1" H 3100 2700 30 0000 C CNN
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- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
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-F 0 "U1" H 3100 2900 30 0000 C CNN
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-$Comp
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/3_and/3_and.sub b/src/SubcircuitLibrary/3_and/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/3_and/3_and.sub +++ b/src/SubcircuitLibrary/3_and/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/4002-cache.lib b/src/SubcircuitLibrary/4002/4002-cache.lib new file mode 100644 index 00000000..677411a9 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4002/4002.cir b/src/SubcircuitLibrary/4002/4002.cir new file mode 100644 index 00000000..5d5c1ed7 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor + +.end diff --git a/src/SubcircuitLibrary/4002/4002.cir.out b/src/SubcircuitLibrary/4002/4002.cir.out new file mode 100644 index 00000000..e9cc6862 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir + +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4002/4002.pro b/src/SubcircuitLibrary/4002/4002.pro new file mode 100644 index 00000000..225ef82a --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog +LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices +LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital +LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid +LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous +LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot +LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power +LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources +LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt +LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User +LibName11=power diff --git a/src/SubcircuitLibrary/4002/4002.sch b/src/SubcircuitLibrary/4002/4002.sch new file mode 100644 index 00000000..545f46fe --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5CEE059A +P 4750 2900 +F 0 "U2" H 4750 2900 60 0000 C CNN +F 1 "d_or" H 4750 3000 60 0000 C CNN +F 2 "" H 4750 2900 60 0000 C CNN +F 3 "" H 4750 2900 60 0000 C CNN + 1 4750 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5CEE0629 +P 4750 3450 +F 0 "U3" H 4750 3450 60 0000 C CNN +F 1 "d_or" H 4750 3550 60 0000 C CNN +F 2 "" H 4750 3450 60 0000 C CNN +F 3 "" H 4750 3450 60 0000 C CNN + 1 4750 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CEE0663 +P 6000 3100 +F 0 "U6" H 6000 3100 60 0000 C CNN +F 1 "d_nor" H 6050 3200 60 0000 C CNN +F 2 "" H 6000 3100 60 0000 C CNN +F 3 "" H 6000 3100 60 0000 C CNN + 1 6000 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 2850 5400 2850 +Wire Wire Line + 5400 2850 5400 3000 +Wire Wire Line + 5400 3000 5550 3000 +Wire Wire Line + 5200 3400 5400 3400 +Wire Wire Line + 5400 3400 5400 3100 +Wire Wire Line + 5400 3100 5550 3100 +Wire Wire Line + 5650 5350 6050 5350 +Wire Wire Line + 5650 5550 6050 5550 +Wire Wire Line + 5650 5800 6050 5800 +Wire Wire Line + 5650 6000 6050 6000 +NoConn ~ 5650 5350 +NoConn ~ 5650 5550 +NoConn ~ 5650 5800 +NoConn ~ 5650 6000 +$Comp +L PORT U1 +U 2 1 5CEE1C41 +P 3850 2800 +F 0 "U1" H 3900 2900 30 0000 C CNN +F 1 "PORT" H 3850 2800 30 0000 C CNN +F 2 "" H 3850 2800 60 0000 C CNN +F 3 "" H 3850 2800 60 0000 C CNN + 2 3850 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE22EE +P 3900 3050 +F 0 "U1" H 3950 3150 30 0000 C CNN +F 1 "PORT" H 3900 3050 30 0000 C CNN +F 2 "" H 3900 3050 60 0000 C CNN +F 3 "" H 3900 3050 60 0000 C CNN + 3 3900 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE2322 +P 3900 3250 +F 0 "U1" H 3950 3350 30 0000 C CNN +F 1 "PORT" H 3900 3250 30 0000 C CNN +F 2 "" H 3900 3250 60 0000 C CNN +F 3 "" H 3900 3250 60 0000 C CNN + 5 3900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE2351 +P 3900 3550 +F 0 "U1" H 3950 3650 30 0000 C CNN +F 1 "PORT" H 3900 3550 30 0000 C CNN +F 2 "" H 3900 3550 60 0000 C CNN +F 3 "" H 3900 3550 60 0000 C CNN + 4 3900 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE2387 +P 6950 3050 +F 0 "U1" H 7000 3150 30 0000 C CNN +F 1 "PORT" H 6950 3050 30 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 4100 2800 4300 2800 +Wire Wire Line + 4150 3050 4150 2900 +Wire Wire Line + 4150 2900 4300 2900 +Wire Wire Line + 4150 3250 4300 3250 +Wire Wire Line + 4300 3250 4300 3350 +Wire Wire Line + 4150 3550 4150 3450 +Wire Wire Line + 4150 3450 4300 3450 +Wire Wire Line + 6700 3050 6450 3050 +$Comp +L d_or U4 +U 1 1 5CEE4ED7 +P 4900 4100 +F 0 "U4" H 4900 4100 60 0000 C CNN +F 1 "d_or" H 4900 4200 60 0000 C CNN +F 2 "" H 4900 4100 60 0000 C CNN +F 3 "" H 4900 4100 60 0000 C CNN + 1 4900 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U5 +U 1 1 5CEE4EDD +P 4900 4650 +F 0 "U5" H 4900 4650 60 0000 C CNN +F 1 "d_or" H 4900 4750 60 0000 C CNN +F 2 "" H 4900 4650 60 0000 C CNN +F 3 "" H 4900 4650 60 0000 C CNN + 1 4900 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CEE4EE3 +P 6150 4300 +F 0 "U7" H 6150 4300 60 0000 C CNN +F 1 "d_nor" H 6200 4400 60 0000 C CNN +F 2 "" H 6150 4300 60 0000 C CNN +F 3 "" H 6150 4300 60 0000 C CNN + 1 6150 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 4050 5550 4050 +Wire Wire Line + 5550 4050 5550 4200 +Wire Wire Line + 5550 4200 5700 4200 +Wire Wire Line + 5350 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 4300 +Wire Wire Line + 5550 4300 5700 4300 +$Comp +L PORT U1 +U 9 1 5CEE4EEF +P 4000 4000 +F 0 "U1" H 4050 4100 30 0000 C CNN +F 1 "PORT" H 4000 4000 30 0000 C CNN +F 2 "" H 4000 4000 60 0000 C CNN +F 3 "" H 4000 4000 60 0000 C CNN + 9 4000 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE4EF5 +P 4050 4250 +F 0 "U1" H 4100 4350 30 0000 C CNN +F 1 "PORT" H 4050 4250 30 0000 C CNN +F 2 "" H 4050 4250 60 0000 C CNN +F 3 "" H 4050 4250 60 0000 C CNN + 10 4050 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE4EFB +P 4050 4450 +F 0 "U1" H 4100 4550 30 0000 C CNN +F 1 "PORT" H 4050 4450 30 0000 C CNN +F 2 "" H 4050 4450 60 0000 C CNN +F 3 "" H 4050 4450 60 0000 C CNN + 11 4050 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE4F01 +P 4050 4750 +F 0 "U1" H 4100 4850 30 0000 C CNN +F 1 "PORT" H 4050 4750 30 0000 C CNN +F 2 "" H 4050 4750 60 0000 C CNN +F 3 "" H 4050 4750 60 0000 C CNN + 12 4050 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE4F07 +P 7100 4250 +F 0 "U1" H 7150 4350 30 0000 C CNN +F 1 "PORT" H 7100 4250 30 0000 C CNN +F 2 "" H 7100 4250 60 0000 C CNN +F 3 "" H 7100 4250 60 0000 C CNN + 13 7100 4250 + -1 0 0 1 +$EndComp +Wire Wire Line + 4250 4000 4450 4000 +Wire Wire Line + 4300 4250 4300 4100 +Wire Wire Line + 4300 4100 4450 4100 +Wire Wire Line + 4300 4450 4450 4450 +Wire Wire Line + 4450 4450 4450 4550 +Wire Wire Line + 4300 4750 4300 4650 +Wire Wire Line + 4300 4650 4450 4650 +Wire Wire Line + 6850 4250 6600 4250 +$Comp +L PORT U1 +U 6 1 5CEE51A5 +P 6300 5350 +F 0 "U1" H 6350 5450 30 0000 C CNN +F 1 "PORT" H 6300 5350 30 0000 C CNN +F 2 "" H 6300 5350 60 0000 C CNN +F 3 "" H 6300 5350 60 0000 C CNN + 6 6300 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE522C +P 6300 5550 +F 0 "U1" H 6350 5650 30 0000 C CNN +F 1 "PORT" H 6300 5550 30 0000 C CNN +F 2 "" H 6300 5550 60 0000 C CNN +F 3 "" H 6300 5550 60 0000 C CNN + 7 6300 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5276 +P 6300 5800 +F 0 "U1" H 6350 5900 30 0000 C CNN +F 1 "PORT" H 6300 5800 30 0000 C CNN +F 2 "" H 6300 5800 60 0000 C CNN +F 3 "" H 6300 5800 60 0000 C CNN + 8 6300 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE52C5 +P 6300 6000 +F 0 "U1" H 6350 6100 30 0000 C CNN +F 1 "PORT" H 6300 6000 30 0000 C CNN +F 2 "" H 6300 6000 60 0000 C CNN +F 3 "" H 6300 6000 60 0000 C CNN + 14 6300 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4002/4002.sub b/src/SubcircuitLibrary/4002/4002.sub new file mode 100644 index 00000000..b9726625 --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002 +.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or +* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor +a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 +a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4002
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/analysis b/src/SubcircuitLibrary/4002/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4002/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/4012-cache.lib b/src/SubcircuitLibrary/4012/4012-cache.lib new file mode 100644 index 00000000..ea0d2d70 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4012/4012.cir b/src/SubcircuitLibrary/4012/4012.cir new file mode 100644 index 00000000..a88a9da4 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter +U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and +U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and + +.end diff --git a/src/SubcircuitLibrary/4012/4012.cir.out b/src/SubcircuitLibrary/4012/4012.cir.out new file mode 100644 index 00000000..c43dda8c --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir + +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4012/4012.pro b/src/SubcircuitLibrary/4012/4012.pro new file mode 100644 index 00000000..0f76f4bb --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_User +LibName11=eSim_Subckt diff --git a/src/SubcircuitLibrary/4012/4012.sch b/src/SubcircuitLibrary/4012/4012.sch new file mode 100644 index 00000000..b3320871 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4012-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3350 2600 2550 2600 +Wire Wire Line + 3350 2700 3150 2700 +Wire Wire Line + 3150 2700 3150 2850 +Wire Wire Line + 3150 2850 2550 2850 +Wire Wire Line + 3350 3200 3150 3200 +Wire Wire Line + 3150 3200 3150 3100 +Wire Wire Line + 3150 3100 2550 3100 +Wire Wire Line + 3350 3300 2550 3300 +Wire Wire Line + 5200 2950 5500 2950 +$Comp +L d_inverter U8 +U 1 1 5CEE55AB +P 5800 2950 +F 0 "U8" H 5800 2850 60 0000 C CNN +F 1 "d_inverter" H 5800 3100 60 0000 C CNN +F 2 "" H 5850 2900 60 0000 C CNN +F 3 "" H 5850 2900 60 0000 C CNN + 1 5800 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 2950 6500 2950 +Wire Wire Line + 3400 3950 2600 3950 +Wire Wire Line + 3400 4050 3200 4050 +Wire Wire Line + 3200 4050 3200 4200 +Wire Wire Line + 3200 4200 2600 4200 +Wire Wire Line + 3400 4550 3200 4550 +Wire Wire Line + 3200 4550 3200 4450 +Wire Wire Line + 3200 4450 2600 4450 +Wire Wire Line + 3400 4650 2600 4650 +Wire Wire Line + 5250 4300 5550 4300 +$Comp +L d_inverter U9 +U 1 1 5CEE5715 +P 5850 4300 +F 0 "U9" H 5850 4200 60 0000 C CNN +F 1 "d_inverter" H 5850 4450 60 0000 C CNN +F 2 "" H 5900 4250 60 0000 C CNN +F 3 "" H 5900 4250 60 0000 C CNN + 1 5850 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 4300 6550 4300 +$Comp +L PORT U1 +U 2 1 5CEE57D6 +P 2300 2600 +F 0 "U1" H 2350 2700 30 0000 C CNN +F 1 "PORT" H 2300 2600 30 0000 C CNN +F 2 "" H 2300 2600 60 0000 C CNN +F 3 "" H 2300 2600 60 0000 C CNN + 2 2300 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CEE587B +P 2300 2850 +F 0 "U1" H 2350 2950 30 0000 C CNN +F 1 "PORT" H 2300 2850 30 0000 C CNN +F 2 "" H 2300 2850 60 0000 C CNN +F 3 "" H 2300 2850 60 0000 C CNN + 3 2300 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CEE58AF +P 2300 3100 +F 0 "U1" H 2350 3200 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0000 C CNN +F 3 "" H 2300 3100 60 0000 C CNN + 4 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CEE58E6 +P 6800 4300 +F 0 "U1" H 6850 4400 30 0000 C CNN +F 1 "PORT" H 6800 4300 30 0000 C CNN +F 2 "" H 6800 4300 60 0000 C CNN +F 3 "" H 6800 4300 60 0000 C CNN + 13 6800 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CEE5922 +P 2300 3300 +AR Path="/5CEE58E6" Ref="U1" Part="1" +AR Path="/5CEE5922" Ref="U1" Part="5" +F 0 "U1" H 2350 3400 30 0000 C CNN +F 1 "PORT" H 2300 3300 30 0000 C CNN +F 2 "" H 2300 3300 60 0000 C CNN +F 3 "" H 2300 3300 60 0000 C CNN + 5 2300 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CEE596F +P 2350 3950 +AR Path="/5CEE5922" Ref="U1" Part="5" +AR Path="/5CEE596F" Ref="U1" Part="9" +F 0 "U1" H 2400 4050 30 0000 C CNN +F 1 "PORT" H 2350 3950 30 0000 C CNN +F 2 "" H 2350 3950 60 0000 C CNN +F 3 "" H 2350 3950 60 0000 C CNN + 9 2350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CEE59AF +P 2350 4200 +AR Path="/5CEE596F" Ref="U1" Part="6" +AR Path="/5CEE59AF" Ref="U1" Part="10" +F 0 "U1" H 2400 4300 30 0000 C CNN +F 1 "PORT" H 2350 4200 30 0000 C CNN +F 2 "" H 2350 4200 60 0000 C CNN +F 3 "" H 2350 4200 60 0000 C CNN + 10 2350 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CEE59F6 +P 2350 4450 +AR Path="/5CEE59AF" Ref="U1" Part="7" +AR Path="/5CEE59F6" Ref="U1" Part="11" +F 0 "U1" H 2400 4550 30 0000 C CNN +F 1 "PORT" H 2350 4450 30 0000 C CNN +F 2 "" H 2350 4450 60 0000 C CNN +F 3 "" H 2350 4450 60 0000 C CNN + 11 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CEE5A6A +P 2350 4650 +AR Path="/5CEE59F6" Ref="U1" Part="8" +AR Path="/5CEE5A6A" Ref="U1" Part="12" +F 0 "U1" H 2400 4750 30 0000 C CNN +F 1 "PORT" H 2350 4650 30 0000 C CNN +F 2 "" H 2350 4650 60 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 12 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CEE5BF8 +P 6750 2950 +AR Path="/5CEE5A6A" Ref="U1" Part="9" +AR Path="/5CEE5BF8" Ref="U1" Part="1" +F 0 "U1" H 6800 3050 30 0000 C CNN +F 1 "PORT" H 6750 2950 30 0000 C CNN +F 2 "" H 6750 2950 60 0000 C CNN +F 3 "" H 6750 2950 60 0000 C CNN + 1 6750 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CEE5C72 +P 7850 1450 +F 0 "U1" H 7900 1550 30 0000 C CNN +F 1 "PORT" H 7850 1450 30 0000 C CNN +F 2 "" H 7850 1450 60 0000 C CNN +F 3 "" H 7850 1450 60 0000 C CNN + 6 7850 1450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CEE5D23 +P 7850 1700 +F 0 "U1" H 7900 1800 30 0000 C CNN +F 1 "PORT" H 7850 1700 30 0000 C CNN +F 2 "" H 7850 1700 60 0000 C CNN +F 3 "" H 7850 1700 60 0000 C CNN + 7 7850 1700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CEE5D75 +P 7850 1950 +F 0 "U1" H 7900 2050 30 0000 C CNN +F 1 "PORT" H 7850 1950 30 0000 C CNN +F 2 "" H 7850 1950 60 0000 C CNN +F 3 "" H 7850 1950 60 0000 C CNN + 14 7850 1950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CEE5DCA +P 7850 2250 +F 0 "U1" H 7900 2350 30 0000 C CNN +F 1 "PORT" H 7850 2250 30 0000 C CNN +F 2 "" H 7850 2250 60 0000 C CNN +F 3 "" H 7850 2250 60 0000 C CNN + 8 7850 2250 + -1 0 0 1 +$EndComp +NoConn ~ 7600 1450 +NoConn ~ 7600 1700 +NoConn ~ 7600 1950 +NoConn ~ 7600 2250 +$Comp +L d_and U4 +U 1 1 5CEE56F6 +P 3850 4050 +F 0 "U4" H 3850 4050 60 0000 C CNN +F 1 "d_and" H 3900 4150 60 0000 C CNN +F 2 "" H 3850 4050 60 0000 C CNN +F 3 "" H 3850 4050 60 0000 C CNN + 1 3850 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5CEE56FC +P 3850 4650 +F 0 "U5" H 3850 4650 60 0000 C CNN +F 1 "d_and" H 3900 4750 60 0000 C CNN +F 2 "" H 3850 4650 60 0000 C CNN +F 3 "" H 3850 4650 60 0000 C CNN + 1 3850 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4600 4300 4600 +Wire Wire Line + 4350 4350 4350 4600 +Wire Wire Line + 4350 4000 4350 4250 +Wire Wire Line + 4300 4000 4350 4000 +$Comp +L d_and U7 +U 1 1 5CEE5702 +P 4800 4350 +F 0 "U7" H 4800 4350 60 0000 C CNN +F 1 "d_and" H 4850 4450 60 0000 C CNN +F 2 "" H 4800 4350 60 0000 C CNN +F 3 "" H 4800 4350 60 0000 C CNN + 1 4800 4350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4250 2650 4300 2650 +Wire Wire Line + 4300 3250 4250 3250 +Wire Wire Line + 4300 2650 4300 2900 +Wire Wire Line + 4300 3000 4300 3250 +$Comp +L d_and U6 +U 1 1 5CEE5432 +P 4750 3000 +F 0 "U6" H 4750 3000 60 0000 C CNN +F 1 "d_and" H 4800 3100 60 0000 C CNN +F 2 "" H 4750 3000 60 0000 C CNN +F 3 "" H 4750 3000 60 0000 C CNN + 1 4750 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5CEE540C +P 3800 3300 +F 0 "U3" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5CEE53DC +P 3800 2700 +F 0 "U2" H 3800 2700 60 0000 C CNN +F 1 "d_and" H 3850 2800 60 0000 C CNN +F 2 "" H 3800 2700 60 0000 C CNN +F 3 "" H 3800 2700 60 0000 C CNN + 1 3800 2700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4012/4012.sub b/src/SubcircuitLibrary/4012/4012.sub new file mode 100644 index 00000000..65263f03 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012 +.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir +* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter +* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter +* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and +* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and +a1 net-_u6-pad3_ net-_u1-pad1_ u8 +a2 net-_u7-pad3_ net-_u1-pad13_ u9 +a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 +a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 +a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4012
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/analysis b/src/SubcircuitLibrary/4012/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4012/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/4017-cache.lib b/src/SubcircuitLibrary/4017/4017-cache.lib new file mode 100644 index 00000000..efa6746f --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4017/4017.cir b/src/SubcircuitLibrary/4017/4017.cir new file mode 100644 index 00000000..67ac9971 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.cir @@ -0,0 +1,26 @@ +* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff +U11 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff +U15 Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff +U19 Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff +U22 Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and +U3 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and +U4 Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and +U5 Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and +U6 Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and +U8 Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and +U9 Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and + +.end diff --git a/src/SubcircuitLibrary/4017/4017.cir.out b/src/SubcircuitLibrary/4017/4017.cir.out new file mode 100644 index 00000000..e3a384c5 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.cir.out @@ -0,0 +1,72 @@ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir + +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 5e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4017/4017.pro b/src/SubcircuitLibrary/4017/4017.pro new file mode 100644 index 00000000..8cdecd6c --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.pro @@ -0,0 +1,72 @@ +update=Fri Jun 14 10:14:54 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_User +LibName38=eSim_Plot + diff --git a/src/SubcircuitLibrary/4017/4017.sch b/src/SubcircuitLibrary/4017/4017.sch new file mode 100644 index 00000000..05549a32 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.sch @@ -0,0 +1,580 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:4017-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U7 +U 1 1 5C7B9B95 +P 2300 4100 +F 0 "U7" H 2300 4100 60 0000 C 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H 4650 1050 30 0000 C CNN +F 1 "PORT" H 4600 950 30 0000 C CNN +F 2 "" H 4600 950 60 0000 C CNN +F 3 "" H 4600 950 60 0000 C CNN + 5 4600 950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 5C7BD0A5 +P 7750 1000 +F 0 "U1" H 7800 1100 30 0000 C CNN +F 1 "PORT" H 7750 1000 30 0000 C CNN +F 2 "" H 7750 1000 60 0000 C CNN +F 3 "" H 7750 1000 60 0000 C CNN + 10 7750 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 5C7BD5BB +P 850 6700 +F 0 "U1" H 900 6800 30 0000 C CNN +F 1 "PORT" H 850 6700 30 0000 C CNN +F 2 "" H 850 6700 60 0000 C CNN +F 3 "" H 850 6700 60 0000 C CNN + 11 850 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 1200 2050 1400 +Wire Wire Line + 2700 1250 2700 1400 +Wire Wire Line + 3400 1200 3400 1400 +Wire Wire Line + 3950 1200 3950 1400 +Wire Wire Line + 4600 1200 4600 1400 +Wire Wire Line + 5850 1200 5850 1400 +Wire Wire Line + 6400 1250 6400 1400 +Wire Wire Line + 7050 1250 7050 1400 +Wire Wire Line + 7750 1250 7750 1400 +$Comp +L PORT U1 +U 12 1 5C8A0119 +P 2450 7200 +F 0 "U1" H 2500 7300 30 0000 C CNN +F 1 "PORT" H 2450 7200 30 0000 C CNN +F 2 "" H 2450 7200 60 0000 C CNN +F 3 "" H 2450 7200 60 0000 C CNN + 12 2450 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C89F7BC +P 2100 1850 +F 0 "U2" H 2100 1850 60 0000 C CNN +F 1 "d_and" H 2150 1950 60 0000 C CNN +F 2 "" H 2100 1850 60 0000 C CNN +F 3 "" H 2100 1850 60 0000 C CNN + 1 2100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U3 +U 1 1 5C89FA46 +P 2750 1850 +F 0 "U3" H 2750 1850 60 0000 C CNN +F 1 "d_and" H 2800 1950 60 0000 C CNN +F 2 "" H 2750 1850 60 0000 C CNN +F 3 "" H 2750 1850 60 0000 C CNN + 1 2750 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U4 +U 1 1 5C89FAD5 +P 3450 1850 +F 0 "U4" H 3450 1850 60 0000 C CNN +F 1 "d_and" H 3500 1950 60 0000 C CNN +F 2 "" H 3450 1850 60 0000 C CNN +F 3 "" H 3450 1850 60 0000 C CNN + 1 3450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 5C89FB62 +P 4000 1850 +F 0 "U5" H 4000 1850 60 0000 C CNN +F 1 "d_and" H 4050 1950 60 0000 C CNN +F 2 "" H 4000 1850 60 0000 C CNN +F 3 "" H 4000 1850 60 0000 C CNN + 1 4000 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U6 +U 1 1 5C89FEBF +P 4650 1850 +F 0 "U6" H 4650 1850 60 0000 C CNN +F 1 "d_and" H 4700 1950 60 0000 C CNN +F 2 "" H 4650 1850 60 0000 C CNN +F 3 "" H 4650 1850 60 0000 C CNN + 1 4650 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U8 +U 1 1 5C89FF2C +P 5350 1850 +F 0 "U8" H 5350 1850 60 0000 C CNN +F 1 "d_and" H 5400 1950 60 0000 C CNN +F 2 "" H 5350 1850 60 0000 C CNN +F 3 "" H 5350 1850 60 0000 C CNN + 1 5350 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U9 +U 1 1 5C89FF96 +P 5900 1850 +F 0 "U9" H 5900 1850 60 0000 C CNN +F 1 "d_and" H 5950 1950 60 0000 C CNN +F 2 "" H 5900 1850 60 0000 C CNN +F 3 "" H 5900 1850 60 0000 C CNN + 1 5900 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 5C8A066D +P 6450 1850 +F 0 "U10" H 6450 1850 60 0000 C CNN +F 1 "d_and" H 6500 1950 60 0000 C CNN +F 2 "" H 6450 1850 60 0000 C CNN +F 3 "" H 6450 1850 60 0000 C CNN + 1 6450 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 5C8A06D8 +P 7100 1850 +F 0 "U12" H 7100 1850 60 0000 C CNN +F 1 "d_and" H 7150 1950 60 0000 C CNN +F 2 "" H 7100 1850 60 0000 C CNN +F 3 "" H 7100 1850 60 0000 C CNN + 1 7100 1850 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 5C8A12F5 +P 7800 1850 +F 0 "U13" H 7800 1850 60 0000 C CNN +F 1 "d_and" H 7850 1950 60 0000 C CNN +F 2 "" H 7800 1850 60 0000 C CNN +F 3 "" H 7800 1850 60 0000 C CNN + 1 7800 1850 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4017/4017.sub b/src/SubcircuitLibrary/4017/4017.sub new file mode 100644 index 00000000..2e27ab61 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017.sub @@ -0,0 +1,66 @@ +* Subcircuit 4017 +.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir +* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff +* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff +* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff +* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff +* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and +* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and +* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and +* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and +* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and +* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and +* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and +a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 +a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 +a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 +a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 +a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 +a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 +a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 +a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 +a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 +a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 +a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 +a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 +a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4017
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml new file mode 100644 index 00000000..9dfd97a3 --- /dev/null +++ b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/D.lib b/src/SubcircuitLibrary/4017/D.lib new file mode 100644 index 00000000..adbdfb35 --- /dev/null +++ b/src/SubcircuitLibrary/4017/D.lib @@ -0,0 +1,11 @@ +.MODEL 1N4148 D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=2.495E-09 ++ M=1.959E-01 ++ N=1.679E+00 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/analysis b/src/SubcircuitLibrary/4017/analysis new file mode 100644 index 00000000..40bd9d97 --- /dev/null +++ b/src/SubcircuitLibrary/4017/analysis @@ -0,0 +1 @@ +.tran 5e-03 100e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/3_and-cache.lib b/src/SubcircuitLibrary/4023/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4023/3_and.cir b/src/SubcircuitLibrary/4023/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4023/3_and.cir.out b/src/SubcircuitLibrary/4023/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4023/3_and.pro b/src/SubcircuitLibrary/4023/3_and.pro new file mode 100644 index 00000000..76df4655 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4023/3_and.sch b/src/SubcircuitLibrary/4023/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/3_and.sub b/src/SubcircuitLibrary/4023/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/4023-cache.lib b/src/SubcircuitLibrary/4023/4023-cache.lib new file mode 100644 index 00000000..c989d8c7 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4023/4023.cir b/src/SubcircuitLibrary/4023/4023.cir new file mode 100644 index 00000000..6aad9b84 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.cir @@ -0,0 +1,17 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and +U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter + +.end diff --git a/src/SubcircuitLibrary/4023/4023.cir.out b/src/SubcircuitLibrary/4023/4023.cir.out new file mode 100644 index 00000000..7f48d16f --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir + +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4023/4023.pro b/src/SubcircuitLibrary/4023/4023.pro new file mode 100644 index 00000000..5a5ce355 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:32:35 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4023/4023.sch b/src/SubcircuitLibrary/4023/4023.sch new file mode 100644 index 00000000..57dd7868 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.sch @@ -0,0 +1,309 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X3 +U 1 1 5CF0FA82 +P 4800 2500 +F 0 "X3" H 4900 2450 60 0000 C CNN +F 1 "3_and" H 4950 2650 60 0000 C CNN +F 2 "" H 4800 2500 60 0000 C CNN +F 3 "" H 4800 2500 60 0000 C CNN + 1 4800 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF0FB13 +P 6150 2450 +F 0 "U4" H 6150 2350 60 0000 C CNN +F 1 "d_inverter" H 6150 2600 60 0000 C CNN +F 2 "" H 6200 2400 60 0000 C CNN +F 3 "" H 6200 2400 60 0000 C CNN + 1 6150 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF0FB34 +P 3100 1950 +F 0 "U1" H 3150 2050 30 0000 C CNN +F 1 "PORT" H 3100 1950 30 0000 C CNN +F 2 "" H 3100 1950 60 0000 C CNN +F 3 "" H 3100 1950 60 0000 C CNN + 11 3100 1950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF0FB90 +P 3100 2350 +F 0 "U1" H 3150 2450 30 0000 C CNN +F 1 "PORT" H 3100 2350 30 0000 C CNN +F 2 "" H 3100 2350 60 0000 C CNN +F 3 "" H 3100 2350 60 0000 C CNN + 12 3100 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF0FBB8 +P 3100 2750 +F 0 "U1" H 3150 2850 30 0000 C CNN +F 1 "PORT" H 3100 2750 30 0000 C CNN +F 2 "" H 3100 2750 60 0000 C CNN +F 3 "" H 3100 2750 60 0000 C CNN + 13 3100 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF0FBED +P 7800 2450 +F 0 "U1" H 7850 2550 30 0000 C CNN +F 1 "PORT" H 7800 2450 30 0000 C CNN +F 2 "" H 7800 2450 60 0000 C CNN +F 3 "" H 7800 2450 60 0000 C CNN + 10 7800 2450 + -1 0 0 1 +$EndComp +Wire Wire Line + 7550 2450 6450 2450 +Wire Wire Line + 5850 2450 5300 2450 +Wire Wire Line + 4450 2350 4450 1950 +Wire Wire Line + 4450 1950 3350 1950 +Wire Wire Line + 4450 2450 4100 2450 +Wire Wire Line + 4100 2450 4100 2350 +Wire Wire Line + 4100 2350 3350 2350 +Wire Wire Line + 3350 2750 3950 2750 +Wire Wire Line + 3950 2750 3950 2550 +Wire Wire Line + 3950 2550 4450 2550 +$Comp +L 3_and X2 +U 1 1 5CF0FF35 +P 4700 3800 +F 0 "X2" H 4800 3750 60 0000 C CNN +F 1 "3_and" H 4850 3950 60 0000 C CNN +F 2 "" H 4700 3800 60 0000 C CNN +F 3 "" H 4700 3800 60 0000 C CNN + 1 4700 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF0FF3B +P 6050 3750 +F 0 "U3" H 6050 3650 60 0000 C CNN +F 1 "d_inverter" H 6050 3900 60 0000 C CNN +F 2 "" H 6100 3700 60 0000 C CNN +F 3 "" H 6100 3700 60 0000 C CNN + 1 6050 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF0FF41 +P 3000 3250 +F 0 "U1" H 3050 3350 30 0000 C CNN +F 1 "PORT" H 3000 3250 30 0000 C CNN +F 2 "" H 3000 3250 60 0000 C CNN +F 3 "" H 3000 3250 60 0000 C CNN + 4 3000 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF0FF47 +P 3000 3650 +F 0 "U1" H 3050 3750 30 0000 C CNN +F 1 "PORT" H 3000 3650 30 0000 C CNN +F 2 "" H 3000 3650 60 0000 C CNN +F 3 "" H 3000 3650 60 0000 C CNN + 5 3000 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF0FF4D +P 3000 4050 +F 0 "U1" H 3050 4150 30 0000 C CNN +F 1 "PORT" H 3000 4050 30 0000 C CNN +F 2 "" H 3000 4050 60 0000 C CNN +F 3 "" H 3000 4050 60 0000 C CNN + 3 3000 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF0FF53 +P 7700 3750 +F 0 "U1" H 7750 3850 30 0000 C CNN +F 1 "PORT" H 7700 3750 30 0000 C CNN +F 2 "" H 7700 3750 60 0000 C CNN +F 3 "" H 7700 3750 60 0000 C CNN + 6 7700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7450 3750 6350 3750 +Wire Wire Line + 5750 3750 5200 3750 +Wire Wire Line + 4350 3650 4350 3250 +Wire Wire Line + 4350 3250 3250 3250 +Wire Wire Line + 4350 3750 4000 3750 +Wire Wire Line + 4000 3750 4000 3650 +Wire Wire Line + 4000 3650 3250 3650 +Wire Wire Line + 3250 4050 3850 4050 +Wire Wire Line + 3850 4050 3850 3850 +Wire Wire Line + 3850 3850 4350 3850 +$Comp +L 3_and X1 +U 1 1 5CF100B9 +P 4650 5100 +F 0 "X1" H 4750 5050 60 0000 C CNN +F 1 "3_and" H 4800 5250 60 0000 C CNN +F 2 "" H 4650 5100 60 0000 C CNN +F 3 "" H 4650 5100 60 0000 C CNN + 1 4650 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF100BF +P 6000 5050 +F 0 "U2" H 6000 4950 60 0000 C CNN +F 1 "d_inverter" H 6000 5200 60 0000 C CNN +F 2 "" H 6050 5000 60 0000 C CNN +F 3 "" H 6050 5000 60 0000 C CNN + 1 6000 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF100C5 +P 2950 4550 +F 0 "U1" H 3000 4650 30 0000 C CNN +F 1 "PORT" H 2950 4550 30 0000 C CNN +F 2 "" H 2950 4550 60 0000 C CNN +F 3 "" H 2950 4550 60 0000 C CNN + 1 2950 4550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF100CB +P 2950 4950 +F 0 "U1" H 3000 5050 30 0000 C CNN +F 1 "PORT" H 2950 4950 30 0000 C CNN +F 2 "" H 2950 4950 60 0000 C CNN +F 3 "" H 2950 4950 60 0000 C CNN + 2 2950 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF100D1 +P 2950 5350 +F 0 "U1" H 3000 5450 30 0000 C CNN +F 1 "PORT" H 2950 5350 30 0000 C CNN +F 2 "" H 2950 5350 60 0000 C CNN +F 3 "" H 2950 5350 60 0000 C CNN + 8 2950 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF100D7 +P 7650 5050 +F 0 "U1" H 7700 5150 30 0000 C CNN +F 1 "PORT" H 7650 5050 30 0000 C CNN +F 2 "" H 7650 5050 60 0000 C CNN +F 3 "" H 7650 5050 60 0000 C CNN + 9 7650 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 7400 5050 6300 5050 +Wire Wire Line + 5700 5050 5150 5050 +Wire Wire Line + 4300 4950 4300 4550 +Wire Wire Line + 4300 4550 3200 4550 +Wire Wire Line + 4300 5050 3950 5050 +Wire Wire Line + 3950 5050 3950 4950 +Wire Wire Line + 3950 4950 3200 4950 +Wire Wire Line + 3200 5350 3800 5350 +Wire Wire Line + 3800 5350 3800 5150 +Wire Wire Line + 3800 5150 4300 5150 +$Comp +L PORT U1 +U 7 1 5CF101BF +P 9950 3350 +F 0 "U1" H 10000 3450 30 0000 C CNN +F 1 "PORT" H 9950 3350 30 0000 C CNN +F 2 "" H 9950 3350 60 0000 C CNN +F 3 "" H 9950 3350 60 0000 C CNN + 7 9950 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF1025C +P 9950 3900 +F 0 "U1" H 10000 4000 30 0000 C CNN +F 1 "PORT" H 9950 3900 30 0000 C CNN +F 2 "" H 9950 3900 60 0000 C CNN +F 3 "" H 9950 3900 60 0000 C CNN + 14 9950 3900 + -1 0 0 1 +$EndComp +NoConn ~ 9700 3350 +NoConn ~ 9700 3900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/4023.sub b/src/SubcircuitLibrary/4023/4023.sub new file mode 100644 index 00000000..b953da2e --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023.sub @@ -0,0 +1,22 @@ +* Subcircuit 4023 +.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir +.include 3_and.sub +x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and +* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter +a1 net-_u4-pad1_ net-_u1-pad10_ u4 +a2 net-_u3-pad1_ net-_u1-pad6_ u3 +a3 net-_u2-pad1_ net-_u1-pad9_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4023
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml new file mode 100644 index 00000000..ad900de2 --- /dev/null +++ b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/analysis b/src/SubcircuitLibrary/4023/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4023/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/4028-cache.lib b/src/SubcircuitLibrary/4028/4028-cache.lib new file mode 100644 index 00000000..5b7e8ebd --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4028/4028.cir b/src/SubcircuitLibrary/4028/4028.cir new file mode 100644 index 00000000..ff25eb55 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor +U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor +U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor +U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor +U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor +U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter +U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter +U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and +U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and +U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and +U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and +U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and +U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and +U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and + +.end diff --git a/src/SubcircuitLibrary/4028/4028.cir.out b/src/SubcircuitLibrary/4028/4028.cir.out new file mode 100644 index 00000000..882115b7 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir + +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4028/4028.pro b/src/SubcircuitLibrary/4028/4028.pro new file mode 100644 index 00000000..a63207b3 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4028/4028.sch b/src/SubcircuitLibrary/4028/4028.sch new file mode 100644 index 00000000..373a95e6 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nor U9 +U 1 1 5CF0FE64 +P 3750 2500 +F 0 "U9" H 3750 2500 60 0000 C CNN +F 1 "d_nor" H 3800 2600 60 0000 C CNN +F 2 "" H 3750 2500 60 0000 C CNN +F 3 "" H 3750 2500 60 0000 C CNN + 1 3750 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U10 +U 1 1 5CF0FEA4 +P 3750 3050 +F 0 "U10" H 3750 3050 60 0000 C CNN +F 1 "d_nor" H 3800 3150 60 0000 C CNN +F 2 "" H 3750 3050 60 0000 C CNN +F 3 "" H 3750 3050 60 0000 C CNN + 1 3750 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U11 +U 1 1 5CF0FECC +P 3750 3550 +F 0 "U11" H 3750 3550 60 0000 C CNN +F 1 "d_nor" H 3800 3650 60 0000 C CNN +F 2 "" H 3750 3550 60 0000 C CNN +F 3 "" H 3750 3550 60 0000 C CNN + 1 3750 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 5CF0FEF5 +P 3750 4150 +F 0 "U12" H 3750 4150 60 0000 C CNN +F 1 "d_nor" H 3800 4250 60 0000 C CNN +F 2 "" H 3750 4150 60 0000 C CNN +F 3 "" H 3750 4150 60 0000 C CNN + 1 3750 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U6 +U 1 1 5CF0FF23 +P 3700 4750 +F 0 "U6" H 3700 4750 60 0000 C CNN +F 1 "d_nor" H 3750 4850 60 0000 C CNN +F 2 "" H 3700 4750 60 0000 C CNN +F 3 "" H 3700 4750 60 0000 C CNN + 1 3700 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 5CF0FF59 +P 3700 5250 +F 0 "U7" H 3700 5250 60 0000 C CNN +F 1 "d_nor" H 3750 5350 60 0000 C CNN +F 2 "" H 3700 5250 60 0000 C CNN +F 3 "" H 3700 5250 60 0000 C CNN + 1 3700 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U8 +U 1 1 5CF0FFA9 +P 3750 2000 +F 0 "U8" H 3750 2000 60 0000 C CNN +F 1 "d_nor" H 3800 2100 60 0000 C CNN +F 2 "" H 3750 2000 60 0000 C CNN +F 3 "" H 3750 2000 60 0000 C CNN + 1 3750 2000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 5CF1003A +P 2150 2400 +F 0 "U2" H 2150 2300 60 0000 C CNN +F 1 "d_inverter" H 2150 2550 60 0000 C CNN +F 2 "" H 2200 2350 60 0000 C CNN +F 3 "" H 2200 2350 60 0000 C CNN + 1 2150 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5CF1007F +P 2150 3300 +F 0 "U3" H 2150 3200 60 0000 C CNN +F 1 "d_inverter" H 2150 3450 60 0000 C CNN +F 2 "" H 2200 3250 60 0000 C CNN +F 3 "" H 2200 3250 60 0000 C CNN + 1 2150 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5CF100CC +P 2150 4150 +F 0 "U4" H 2150 4050 60 0000 C CNN +F 1 "d_inverter" H 2150 4300 60 0000 C CNN +F 2 "" H 2200 4100 60 0000 C CNN +F 3 "" H 2200 4100 60 0000 C CNN + 1 2150 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5CF10114 +P 2150 4900 +F 0 "U5" H 2150 4800 60 0000 C CNN +F 1 "d_inverter" H 2150 5050 60 0000 C CNN +F 2 "" H 2200 4850 60 0000 C CNN +F 3 "" H 2200 4850 60 0000 C CNN + 1 2150 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 2400 1850 2400 +Wire Wire Line + 1400 3300 1850 3300 +Wire Wire Line + 1450 4150 1850 4150 +Wire Wire Line + 1450 4900 1850 4900 +Wire Wire Line + 2450 4900 2500 4900 +Wire Wire Line + 2500 4900 2500 5250 +Wire Wire Line + 2500 5250 3250 5250 +Wire Wire Line + 2450 4150 2550 4150 +Wire Wire Line + 2550 4150 2550 4650 +Wire Wire Line + 2550 4650 3250 4650 +Wire Wire Line + 2450 3300 2550 3300 +Wire Wire Line + 2550 3300 2550 3550 +Wire Wire Line + 2550 3550 3300 3550 +Wire Wire Line + 2450 2400 2450 2500 +Wire Wire Line + 2450 2500 3300 2500 +Wire Wire Line + 2800 2500 2800 3450 +Wire Wire Line + 2800 3450 3300 3450 +Connection ~ 2800 2500 +Wire Wire Line + 1650 2400 1650 1900 +Wire Wire Line + 1650 1900 3300 1900 +Connection ~ 1650 2400 +Wire Wire Line + 3300 2000 2850 2000 +Wire Wire Line + 2850 2000 2850 3000 +Wire Wire Line + 2850 3000 1650 3000 +Wire Wire Line + 1650 3000 1650 3300 +Connection ~ 1650 3300 +Wire Wire Line + 2850 2400 3300 2400 +Connection ~ 2850 2400 +Wire Wire Line + 2950 1900 2950 2950 +Wire Wire Line + 2950 2950 3300 2950 +Connection ~ 2950 1900 +Wire Wire Line + 3100 3550 3100 3050 +Wire Wire Line + 3100 3050 3300 3050 +Connection ~ 3100 3550 +Wire Wire Line + 1650 3900 1650 4150 +Wire Wire Line + 1650 3900 3050 3900 +Wire Wire Line + 3050 3900 3050 5150 +Wire Wire Line + 3050 4050 3300 4050 +Connection ~ 1650 4150 +Wire Wire Line + 1750 4900 1750 5150 +Wire Wire Line + 1750 5150 2750 5150 +Connection ~ 1750 4900 +Wire Wire Line + 2750 5150 2750 4150 +Wire Wire Line + 2750 4150 3300 4150 +Wire Wire Line + 2750 4750 3250 4750 +Connection ~ 2750 4750 +Wire Wire Line + 3050 5150 3250 5150 +Connection ~ 3050 4050 +$Comp +L d_and U15 +U 1 1 5CF106B1 +P 6600 1850 +F 0 "U15" H 6600 1850 60 0000 C CNN +F 1 "d_and" H 6650 1950 60 0000 C CNN +F 2 "" H 6600 1850 60 0000 C CNN +F 3 "" H 6600 1850 60 0000 C CNN + 1 6600 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 5CF10756 +P 6600 2350 +F 0 "U16" H 6600 2350 60 0000 C CNN +F 1 "d_and" H 6650 2450 60 0000 C CNN +F 2 "" H 6600 2350 60 0000 C CNN +F 3 "" H 6600 2350 60 0000 C CNN + 1 6600 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 5CF107A1 +P 6600 2800 +F 0 "U17" H 6600 2800 60 0000 C CNN +F 1 "d_and" H 6650 2900 60 0000 C CNN +F 2 "" H 6600 2800 60 0000 C CNN +F 3 "" H 6600 2800 60 0000 C CNN + 1 6600 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5CF107E9 +P 6600 3200 +F 0 "U18" H 6600 3200 60 0000 C CNN +F 1 "d_and" H 6650 3300 60 0000 C CNN +F 2 "" H 6600 3200 60 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5CF10834 +P 6600 3650 +F 0 "U19" H 6600 3650 60 0000 C CNN +F 1 "d_and" H 6650 3750 60 0000 C CNN +F 2 "" H 6600 3650 60 0000 C CNN +F 3 "" H 6600 3650 60 0000 C CNN + 1 6600 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5CF1087E +P 6600 4050 +F 0 "U20" H 6600 4050 60 0000 C CNN +F 1 "d_and" H 6650 4150 60 0000 C CNN +F 2 "" H 6600 4050 60 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5CF108F9 +P 6600 4450 +F 0 "U21" H 6600 4450 60 0000 C CNN +F 1 "d_and" H 6650 4550 60 0000 C CNN +F 2 "" H 6600 4450 60 0000 C CNN +F 3 "" H 6600 4450 60 0000 C CNN + 1 6600 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5CF1094D +P 6550 4900 +F 0 "U13" H 6550 4900 60 0000 C CNN +F 1 "d_and" H 6600 5000 60 0000 C CNN +F 2 "" H 6550 4900 60 0000 C CNN +F 3 "" H 6550 4900 60 0000 C CNN + 1 6550 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 5CF109A6 +P 6550 5350 +F 0 "U14" H 6550 5350 60 0000 C CNN +F 1 "d_and" H 6600 5450 60 0000 C CNN +F 2 "" H 6550 5350 60 0000 C CNN +F 3 "" H 6550 5350 60 0000 C CNN + 1 6550 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF11966 +P 1150 2400 +F 0 "U1" H 1200 2500 30 0000 C CNN +F 1 "PORT" H 1150 2400 30 0000 C CNN +F 2 "" H 1150 2400 60 0000 C CNN +F 3 "" H 1150 2400 60 0000 C CNN + 10 1150 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF119D4 +P 1150 3300 +F 0 "U1" H 1200 3400 30 0000 C CNN +F 1 "PORT" H 1150 3300 30 0000 C CNN +F 2 "" H 1150 3300 60 0000 C CNN +F 3 "" H 1150 3300 60 0000 C CNN + 13 1150 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF11AFC +P 1200 4150 +F 0 "U1" H 1250 4250 30 0000 C CNN +F 1 "PORT" H 1200 4150 30 0000 C CNN +F 2 "" H 1200 4150 60 0000 C CNN +F 3 "" H 1200 4150 60 0000 C CNN + 12 1200 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF11B6B +P 1200 4900 +F 0 "U1" H 1250 5000 30 0000 C CNN +F 1 "PORT" H 1200 4900 30 0000 C CNN +F 2 "" H 1200 4900 60 0000 C CNN +F 3 "" H 1200 4900 60 0000 C CNN + 11 1200 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF11BDB +P 8000 1800 +F 0 "U1" H 8050 1900 30 0000 C CNN +F 1 "PORT" H 8000 1800 30 0000 C CNN +F 2 "" H 8000 1800 60 0000 C CNN +F 3 "" H 8000 1800 60 0000 C CNN + 3 8000 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11F59 +P 8000 2300 +F 0 "U1" H 8050 2400 30 0000 C CNN +F 1 "PORT" H 8000 2300 30 0000 C CNN +F 2 "" H 8000 2300 60 0000 C CNN +F 3 "" H 8000 2300 60 0000 C CNN + 14 8000 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF11FC5 +P 8000 2750 +F 0 "U1" H 8050 2850 30 0000 C CNN +F 1 "PORT" H 8000 2750 30 0000 C CNN +F 2 "" H 8000 2750 60 0000 C CNN +F 3 "" H 8000 2750 60 0000 C CNN + 2 8000 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 5CF1204F +P 8000 3150 +F 0 "U1" H 8050 3250 30 0000 C CNN +F 1 "PORT" H 8000 3150 30 0000 C CNN +F 2 "" H 8000 3150 60 0000 C CNN +F 3 "" H 8000 3150 60 0000 C CNN + 15 8000 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF120C5 +P 7950 3600 +F 0 "U1" H 8000 3700 30 0000 C CNN +F 1 "PORT" H 7950 3600 30 0000 C CNN +F 2 "" H 7950 3600 60 0000 C CNN +F 3 "" H 7950 3600 60 0000 C CNN + 1 7950 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF1213C +P 7950 4000 +F 0 "U1" H 8000 4100 30 0000 C CNN +F 1 "PORT" H 7950 4000 30 0000 C CNN +F 2 "" H 7950 4000 60 0000 C CNN +F 3 "" H 7950 4000 60 0000 C CNN + 6 7950 4000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CF121B2 +P 7900 4400 +F 0 "U1" H 7950 4500 30 0000 C CNN +F 1 "PORT" H 7900 4400 30 0000 C CNN +F 2 "" H 7900 4400 60 0000 C CNN +F 3 "" H 7900 4400 60 0000 C CNN + 7 7900 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF1223D +P 7900 4850 +F 0 "U1" H 7950 4950 30 0000 C CNN +F 1 "PORT" H 7900 4850 30 0000 C CNN +F 2 "" H 7900 4850 60 0000 C CNN +F 3 "" H 7900 4850 60 0000 C CNN + 4 7900 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF1237B +P 7900 5300 +F 0 "U1" H 7950 5400 30 0000 C CNN +F 1 "PORT" H 7900 5300 30 0000 C CNN +F 2 "" H 7900 5300 60 0000 C CNN +F 3 "" H 7900 5300 60 0000 C CNN + 9 7900 5300 + -1 0 0 1 +$EndComp +Wire Wire Line + 7750 1800 7050 1800 +Wire Wire Line + 7050 2300 7750 2300 +Wire Wire Line + 7750 2750 7050 2750 +Wire Wire Line + 7050 3150 7750 3150 +Wire Wire Line + 7700 3600 7050 3600 +Wire Wire Line + 7050 4000 7700 4000 +Wire Wire Line + 7650 4400 7050 4400 +Wire Wire Line + 7000 4850 7650 4850 +Wire Wire Line + 7650 5300 7000 5300 +$Comp +L d_and U22 +U 1 1 5CF14904 +P 6550 5800 +F 0 "U22" H 6550 5800 60 0000 C CNN +F 1 "d_and" H 6600 5900 60 0000 C CNN +F 2 "" H 6550 5800 60 0000 C CNN +F 3 "" H 6550 5800 60 0000 C CNN + 1 6550 5800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 1950 4600 1950 +Wire Wire Line + 4600 1750 4600 5250 +Wire Wire Line + 4600 1750 6150 1750 +Wire Wire Line + 4600 5250 6100 5250 +Connection ~ 4600 1950 +Wire Wire Line + 6100 5800 5900 5800 +Wire Wire Line + 5900 5800 5900 5350 +Wire Wire Line + 5900 5350 6100 5350 +Wire Wire Line + 5850 4900 6100 4900 +Wire Wire Line + 5850 3650 5850 4900 +Wire Wire Line + 5850 4450 6150 4450 +Wire Wire Line + 5850 4050 6150 4050 +Connection ~ 5850 4450 +Wire Wire Line + 5850 3650 6150 3650 +Connection ~ 5850 4050 +Wire Wire Line + 5050 3200 6150 3200 +Wire Wire Line + 5850 1850 5850 3200 +Wire Wire Line + 5850 2800 6150 2800 +Wire Wire Line + 5850 2350 6150 2350 +Connection ~ 5850 2800 +Wire Wire Line + 5850 1850 6150 1850 +Connection ~ 5850 2350 +Wire Wire Line + 4200 2450 4700 2450 +Wire Wire Line + 4700 2250 4700 5700 +Wire Wire Line + 4700 2250 6150 2250 +Wire Wire Line + 4200 3000 4800 3000 +Wire Wire Line + 4800 2700 4800 4350 +Wire Wire Line + 4800 2700 6150 2700 +Wire Wire Line + 4700 5700 6100 5700 +Connection ~ 4700 2450 +Wire Wire Line + 6150 3550 4600 3550 +Connection ~ 4600 3550 +Wire Wire Line + 6150 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4800 4350 6150 4350 +Connection ~ 4800 3000 +Wire Wire Line + 4200 3500 4900 3500 +Wire Wire Line + 4900 3100 4900 4800 +Wire Wire Line + 4900 3100 6150 3100 +Wire Wire Line + 4900 4800 6100 4800 +Connection ~ 4900 3500 +Wire Wire Line + 4200 4100 5050 4100 +Wire Wire Line + 5050 4100 5050 3200 +Connection ~ 5850 3200 +Wire Wire Line + 4150 4700 5850 4700 +Connection ~ 5850 4700 +Wire Wire Line + 4150 5200 4500 5200 +Wire Wire Line + 4500 5200 4500 5550 +Wire Wire Line + 4500 5550 5900 5550 +Connection ~ 5900 5550 +$Comp +L PORT U1 +U 5 1 5CF1563E +P 7950 5750 +F 0 "U1" H 8000 5850 30 0000 C CNN +F 1 "PORT" H 7950 5750 30 0000 C CNN +F 2 "" H 7950 5750 60 0000 C CNN +F 3 "" H 7950 5750 60 0000 C CNN + 5 7950 5750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7700 5750 7000 5750 +$Comp +L PORT U1 +U 8 1 5CF15953 +P 9550 4800 +F 0 "U1" H 9600 4900 30 0000 C CNN +F 1 "PORT" H 9550 4800 30 0000 C CNN +F 2 "" H 9550 4800 60 0000 C CNN +F 3 "" H 9550 4800 60 0000 C CNN + 8 9550 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 5CF15A07 +P 9550 5250 +F 0 "U1" H 9600 5350 30 0000 C CNN +F 1 "PORT" H 9550 5250 30 0000 C CNN +F 2 "" H 9550 5250 60 0000 C CNN +F 3 "" H 9550 5250 60 0000 C CNN + 16 9550 5250 + -1 0 0 1 +$EndComp +NoConn ~ 9300 4800 +NoConn ~ 9300 5250 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4028/4028.sub b/src/SubcircuitLibrary/4028/4028.sub new file mode 100644 index 00000000..828e0b67 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028 +.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir +* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor +* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor +* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor +* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor +* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor +* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor +* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter +* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and +* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and +* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and +* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and +* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and +* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and +* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and +* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and +a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 +a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 +a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 +a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 +a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 +a8 net-_u1-pad10_ net-_u11-pad1_ u2 +a9 net-_u1-pad13_ net-_u10-pad2_ u3 +a10 net-_u1-pad12_ net-_u4-pad2_ u4 +a11 net-_u1-pad11_ net-_u5-pad2_ u5 +a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 +a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 +a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 +a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 +a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 +a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 +a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 +a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 +a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 +a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4028
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/analysis b/src/SubcircuitLibrary/4028/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/4028/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and-cache.lib b/src/SubcircuitLibrary/4073/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/4073/3_and-cache.lib +++ b/src/SubcircuitLibrary/4073/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4073/3_and.cir b/src/SubcircuitLibrary/4073/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/4073/3_and.cir +++ b/src/SubcircuitLibrary/4073/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4073/3_and.cir.out b/src/SubcircuitLibrary/4073/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/4073/3_and.cir.out +++ b/src/SubcircuitLibrary/4073/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4073/3_and.pro b/src/SubcircuitLibrary/4073/3_and.pro index 0fdf4d25..76df4655 100644 --- a/src/SubcircuitLibrary/4073/3_and.pro +++ b/src/SubcircuitLibrary/4073/3_and.pro @@ -1,44 +1,44 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4073/3_and.sch b/src/SubcircuitLibrary/4073/3_and.sch index c853bf49..d6ac89f9 100644 --- a/src/SubcircuitLibrary/4073/3_and.sch +++ b/src/SubcircuitLibrary/4073/3_and.sch @@ -1,130 +1,130 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/3_and.sub b/src/SubcircuitLibrary/4073/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/4073/3_and.sub +++ b/src/SubcircuitLibrary/4073/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073-cache.lib b/src/SubcircuitLibrary/4073/4073-cache.lib index e316d596..4ee605a2 100644 --- a/src/SubcircuitLibrary/4073/4073-cache.lib +++ b/src/SubcircuitLibrary/4073/4073-cache.lib @@ -1,62 +1,62 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0 -150 200 200 200 N
-P 3 0 1 0 -150 200 -150 -100 200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4073/4073.cir b/src/SubcircuitLibrary/4073/4073.cir index 7afe79fe..e159f055 100644 --- a/src/SubcircuitLibrary/4073/4073.cir +++ b/src/SubcircuitLibrary/4073/4073.cir @@ -1,14 +1,14 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
-X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and
-X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and + +.end diff --git a/src/SubcircuitLibrary/4073/4073.cir.out b/src/SubcircuitLibrary/4073/4073.cir.out index d22d0923..b25337cd 100644 --- a/src/SubcircuitLibrary/4073/4073.cir.out +++ b/src/SubcircuitLibrary/4073/4073.cir.out @@ -1,16 +1,16 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
-x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4073/4073.pro b/src/SubcircuitLibrary/4073/4073.pro index 7ed8e96e..94cd9bd4 100644 --- a/src/SubcircuitLibrary/4073/4073.pro +++ b/src/SubcircuitLibrary/4073/4073.pro @@ -1,43 +1,43 @@ -update=05/31/19 16:37:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_Subckt
-LibName10=eSim_User
+update=05/31/19 16:37:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4073/4073.sch b/src/SubcircuitLibrary/4073/4073.sch index ff6d873a..045208e6 100644 --- a/src/SubcircuitLibrary/4073/4073.sch +++ b/src/SubcircuitLibrary/4073/4073.sch @@ -1,263 +1,263 @@ -EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
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-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5CF10AEA
-P 4550 2650
-F 0 "X1" H 4650 2600 60 0000 C CNN
-F 1 "3_and" H 4700 2800 60 0000 C CNN
-F 2 "" H 4550 2650 60 0000 C CNN
-F 3 "" H 4550 2650 60 0000 C CNN
- 1 4550 2650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF10B72
-P 3100 2200
-F 0 "U1" H 3150 2300 30 0000 C CNN
-F 1 "PORT" H 3100 2200 30 0000 C CNN
-F 2 "" H 3100 2200 60 0000 C CNN
-F 3 "" H 3100 2200 60 0000 C CNN
- 1 3100 2200
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF10BC9
-P 3100 2500
-F 0 "U1" H 3150 2600 30 0000 C CNN
-F 1 "PORT" H 3100 2500 30 0000 C CNN
-F 2 "" H 3100 2500 60 0000 C CNN
-F 3 "" H 3100 2500 60 0000 C CNN
- 2 3100 2500
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CF10BEA
-P 3100 2850
-F 0 "U1" H 3150 2950 30 0000 C CNN
-F 1 "PORT" H 3100 2850 30 0000 C CNN
-F 2 "" H 3100 2850 60 0000 C CNN
-F 3 "" H 3100 2850 60 0000 C CNN
- 8 3100 2850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CF10C10
-P 6200 2600
-F 0 "U1" H 6250 2700 30 0000 C CNN
-F 1 "PORT" H 6200 2600 30 0000 C CNN
-F 2 "" H 6200 2600 60 0000 C CNN
-F 3 "" H 6200 2600 60 0000 C CNN
- 9 6200 2600
- -1 0 0 1
-$EndComp
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-$Comp
-L 3_and X3
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-P 4600 4100
-F 0 "X3" H 4700 4050 60 0000 C CNN
-F 1 "3_and" H 4750 4250 60 0000 C CNN
-F 2 "" H 4600 4100 60 0000 C CNN
-F 3 "" H 4600 4100 60 0000 C CNN
- 1 4600 4100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF10DEB
-P 3150 3650
-F 0 "U1" H 3200 3750 30 0000 C CNN
-F 1 "PORT" H 3150 3650 30 0000 C CNN
-F 2 "" H 3150 3650 60 0000 C CNN
-F 3 "" H 3150 3650 60 0000 C CNN
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- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF10DF1
-P 3150 3950
-F 0 "U1" H 3200 4050 30 0000 C CNN
-F 1 "PORT" H 3150 3950 30 0000 C CNN
-F 2 "" H 3150 3950 60 0000 C CNN
-F 3 "" H 3150 3950 60 0000 C CNN
- 4 3150 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CF10DF7
-P 3150 4300
-F 0 "U1" H 3200 4400 30 0000 C CNN
-F 1 "PORT" H 3150 4300 30 0000 C CNN
-F 2 "" H 3150 4300 60 0000 C CNN
-F 3 "" H 3150 4300 60 0000 C CNN
- 5 3150 4300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CF10DFD
-P 6250 4050
-F 0 "U1" H 6300 4150 30 0000 C CNN
-F 1 "PORT" H 6250 4050 30 0000 C CNN
-F 2 "" H 6250 4050 60 0000 C CNN
-F 3 "" H 6250 4050 60 0000 C CNN
- 6 6250 4050
- -1 0 0 1
-$EndComp
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
- 3900 3950 3900 4050
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-$Comp
-L 3_and X2
-U 1 1 5CF10E9C
-P 4550 5450
-F 0 "X2" H 4650 5400 60 0000 C CNN
-F 1 "3_and" H 4700 5600 60 0000 C CNN
-F 2 "" H 4550 5450 60 0000 C CNN
-F 3 "" H 4550 5450 60 0000 C CNN
- 1 4550 5450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF10EA2
-P 3100 5000
-F 0 "U1" H 3150 5100 30 0000 C CNN
-F 1 "PORT" H 3100 5000 30 0000 C CNN
-F 2 "" H 3100 5000 60 0000 C CNN
-F 3 "" H 3100 5000 60 0000 C CNN
- 11 3100 5000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CF10EA8
-P 3100 5300
-F 0 "U1" H 3150 5400 30 0000 C CNN
-F 1 "PORT" H 3100 5300 30 0000 C CNN
-F 2 "" H 3100 5300 60 0000 C CNN
-F 3 "" H 3100 5300 60 0000 C CNN
- 12 3100 5300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF10EAE
-P 3100 5650
-F 0 "U1" H 3150 5750 30 0000 C CNN
-F 1 "PORT" H 3100 5650 30 0000 C CNN
-F 2 "" H 3100 5650 60 0000 C CNN
-F 3 "" H 3100 5650 60 0000 C CNN
- 13 3100 5650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF10EB4
-P 6200 5400
-F 0 "U1" H 6250 5500 30 0000 C CNN
-F 1 "PORT" H 6200 5400 30 0000 C CNN
-F 2 "" H 6200 5400 60 0000 C CNN
-F 3 "" H 6200 5400 60 0000 C CNN
- 10 6200 5400
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 5950 5400 5050 5400
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
- 3850 5400 4200 5400
-Wire Wire Line
- 4200 5500 4200 5650
-Wire Wire Line
- 4200 5650 3350 5650
-$Comp
-L PORT U1
-U 7 1 5CF11A2A
-P 7500 4100
-F 0 "U1" H 7550 4200 30 0000 C CNN
-F 1 "PORT" H 7500 4100 30 0000 C CNN
-F 2 "" H 7500 4100 60 0000 C CNN
-F 3 "" H 7500 4100 60 0000 C CNN
- 7 7500 4100
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF11A8A
-P 7550 4600
-F 0 "U1" H 7600 4700 30 0000 C CNN
-F 1 "PORT" H 7550 4600 30 0000 C CNN
-F 2 "" H 7550 4600 60 0000 C CNN
-F 3 "" H 7550 4600 60 0000 C CNN
- 14 7550 4600
- -1 0 0 1
-$EndComp
-NoConn ~ 7250 4100
-NoConn ~ 7300 4600
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5CF10AEA +P 4550 2650 +F 0 "X1" H 4650 2600 60 0000 C CNN +F 1 "3_and" H 4700 2800 60 0000 C CNN +F 2 "" H 4550 2650 60 0000 C CNN +F 3 "" H 4550 2650 60 0000 C CNN + 1 4550 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF10B72 +P 3100 2200 +F 0 "U1" H 3150 2300 30 0000 C CNN +F 1 "PORT" H 3100 2200 30 0000 C CNN +F 2 "" H 3100 2200 60 0000 C CNN +F 3 "" H 3100 2200 60 0000 C CNN + 1 3100 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF10BC9 +P 3100 2500 +F 0 "U1" H 3150 2600 30 0000 C CNN +F 1 "PORT" H 3100 2500 30 0000 C CNN +F 2 "" H 3100 2500 60 0000 C CNN +F 3 "" H 3100 2500 60 0000 C CNN + 2 3100 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF10BEA +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 8 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF10C10 +P 6200 2600 +F 0 "U1" H 6250 2700 30 0000 C CNN +F 1 "PORT" H 6200 2600 30 0000 C CNN +F 2 "" H 6200 2600 60 0000 C CNN +F 3 "" H 6200 2600 60 0000 C CNN + 9 6200 2600 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2600 5050 2600 +Wire Wire Line + 4200 2500 4200 2200 +Wire Wire Line + 4200 2200 3350 2200 +Wire Wire Line + 3350 2500 3850 2500 +Wire Wire Line + 3850 2500 3850 2600 +Wire Wire Line + 3850 2600 4200 2600 +Wire Wire Line + 4200 2700 4200 2850 +Wire Wire Line + 4200 2850 3350 2850 +$Comp +L 3_and X3 +U 1 1 5CF10DE5 +P 4600 4100 +F 0 "X3" H 4700 4050 60 0000 C CNN +F 1 "3_and" H 4750 4250 60 0000 C CNN +F 2 "" H 4600 4100 60 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4600 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF10DEB +P 3150 3650 +F 0 "U1" H 3200 3750 30 0000 C CNN +F 1 "PORT" H 3150 3650 30 0000 C CNN +F 2 "" H 3150 3650 60 0000 C CNN +F 3 "" H 3150 3650 60 0000 C CNN + 3 3150 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF10DF1 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 4 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF10DF7 +P 3150 4300 +F 0 "U1" H 3200 4400 30 0000 C CNN +F 1 "PORT" H 3150 4300 30 0000 C CNN +F 2 "" H 3150 4300 60 0000 C CNN +F 3 "" H 3150 4300 60 0000 C CNN + 5 3150 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF10DFD +P 6250 4050 +F 0 "U1" H 6300 4150 30 0000 C CNN +F 1 "PORT" H 6250 4050 30 0000 C CNN +F 2 "" H 6250 4050 60 0000 C CNN +F 3 "" H 6250 4050 60 0000 C CNN + 6 6250 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6000 4050 5100 4050 +Wire Wire Line + 4250 3950 4250 3650 +Wire Wire Line + 4250 3650 3400 3650 +Wire Wire Line + 3400 3950 3900 3950 +Wire Wire Line + 3900 3950 3900 4050 +Wire Wire Line + 3900 4050 4250 4050 +Wire Wire Line + 4250 4150 4250 4300 +Wire Wire Line + 4250 4300 3400 4300 +$Comp +L 3_and X2 +U 1 1 5CF10E9C +P 4550 5450 +F 0 "X2" H 4650 5400 60 0000 C CNN +F 1 "3_and" H 4700 5600 60 0000 C CNN +F 2 "" H 4550 5450 60 0000 C CNN +F 3 "" H 4550 5450 60 0000 C CNN + 1 4550 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF10EA2 +P 3100 5000 +F 0 "U1" H 3150 5100 30 0000 C CNN +F 1 "PORT" H 3100 5000 30 0000 C CNN +F 2 "" H 3100 5000 60 0000 C CNN +F 3 "" H 3100 5000 60 0000 C CNN + 11 3100 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF10EA8 +P 3100 5300 +F 0 "U1" H 3150 5400 30 0000 C CNN +F 1 "PORT" H 3100 5300 30 0000 C CNN +F 2 "" H 3100 5300 60 0000 C CNN +F 3 "" H 3100 5300 60 0000 C CNN + 12 3100 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF10EAE +P 3100 5650 +F 0 "U1" H 3150 5750 30 0000 C CNN +F 1 "PORT" H 3100 5650 30 0000 C CNN +F 2 "" H 3100 5650 60 0000 C CNN +F 3 "" H 3100 5650 60 0000 C CNN + 13 3100 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF10EB4 +P 6200 5400 +F 0 "U1" H 6250 5500 30 0000 C CNN +F 1 "PORT" H 6200 5400 30 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 10 6200 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 5400 5050 5400 +Wire Wire Line + 4200 5300 4200 5000 +Wire Wire Line + 4200 5000 3350 5000 +Wire Wire Line + 3350 5300 3850 5300 +Wire Wire Line + 3850 5300 3850 5400 +Wire Wire Line + 3850 5400 4200 5400 +Wire Wire Line + 4200 5500 4200 5650 +Wire Wire Line + 4200 5650 3350 5650 +$Comp +L PORT U1 +U 7 1 5CF11A2A +P 7500 4100 +F 0 "U1" H 7550 4200 30 0000 C CNN +F 1 "PORT" H 7500 4100 30 0000 C CNN +F 2 "" H 7500 4100 60 0000 C CNN +F 3 "" H 7500 4100 60 0000 C CNN + 7 7500 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11A8A +P 7550 4600 +F 0 "U1" H 7600 4700 30 0000 C CNN +F 1 "PORT" H 7550 4600 30 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 14 7550 4600 + -1 0 0 1 +$EndComp +NoConn ~ 7250 4100 +NoConn ~ 7300 4600 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/4073.sub b/src/SubcircuitLibrary/4073/4073.sub index b10679cc..15208169 100644 --- a/src/SubcircuitLibrary/4073/4073.sub +++ b/src/SubcircuitLibrary/4073/4073.sub @@ -1,10 +1,10 @@ -* Subcircuit 4073
-.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
-* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
-x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
-x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
-* Control Statements
-
+* Subcircuit 4073 +.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +* Control Statements + .ends 4073
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib index a3c1c972..155f5e60 100644 --- a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib +++ b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib @@ -1,63 +1,63 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir index 7adbf177..b338b7b5 100644 --- a/src/SubcircuitLibrary/4_OR/4_OR.cir +++ b/src/SubcircuitLibrary/4_OR/4_OR.cir @@ -1,14 +1,14 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
-U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
-U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out index 4388b975..adb6b01b 100644 --- a/src/SubcircuitLibrary/4_OR/4_OR.cir.out +++ b/src/SubcircuitLibrary/4_OR/4_OR.cir.out @@ -1,24 +1,24 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro index 1e19b3a7..9daf26bc 100644 --- a/src/SubcircuitLibrary/4_OR/4_OR.pro +++ b/src/SubcircuitLibrary/4_OR/4_OR.pro @@ -1,45 +1,45 @@ -update=06/01/19 12:36:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
+update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch index 2f28896c..11896865 100644 --- a/src/SubcircuitLibrary/4_OR/4_OR.sch +++ b/src/SubcircuitLibrary/4_OR/4_OR.sch @@ -1,150 +1,150 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C9D00E1
-P 4300 2950
-F 0 "U2" H 4300 2950 60 0000 C CNN
-F 1 "d_or" H 4300 3050 60 0000 C CNN
-F 2 "" H 4300 2950 60 0000 C CNN
-F 3 "" H 4300 2950 60 0000 C CNN
- 1 4300 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60 0000 C CNN
-F 1 "d_or" H 4300 3450 60 0000 C CNN
-F 2 "" H 4300 3350 60 0000 C CNN
-F 3 "" H 4300 3350 60 0000 C CNN
- 1 4300 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60 0000 C CNN
-F 1 "d_or" H 5250 3250 60 0000 C CNN
-F 2 "" H 5250 3150 60 0000 C CNN
-F 3 "" H 5250 3150 60 0000 C CNN
- 1 5250 3150
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4800 3050 4800 2900
-Wire Wire Line
- 4800 2900 4750 2900
-Wire Wire Line
- 4800 3150 4800 3300
-Wire Wire Line
- 4800 3300 4750 3300
-Wire Wire Line
- 3350 2850 3850 2850
-Wire Wire Line
- 3850 2950 3600 2950
-Wire Wire Line
- 3850 3250 3350 3250
-Wire Wire Line
- 3600 2950 3600 3000
-Wire Wire Line
- 3600 3000 3350 3000
-Wire Wire Line
- 3850 3350 3850 3400
-Wire Wire Line
- 3850 3400 3350 3400
-Wire Wire Line
- 5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30 0000 C CNN
-F 1 "PORT" H 3100 2850 30 0000 C CNN
-F 2 "" H 3100 2850 60 0000 C CNN
-F 3 "" H 3100 2850 60 0000 C CNN
- 1 3100 2850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
-P 3100 3000
-F 0 "U1" H 3150 3100 30 0000 C CNN
-F 1 "PORT" H 3100 3000 30 0000 C CNN
-F 2 "" H 3100 3000 60 0000 C CNN
-F 3 "" H 3100 3000 60 0000 C CNN
- 2 3100 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
-P 3100 3250
-F 0 "U1" H 3150 3350 30 0000 C CNN
-F 1 "PORT" H 3100 3250 30 0000 C CNN
-F 2 "" H 3100 3250 60 0000 C CNN
-F 3 "" H 3100 3250 60 0000 C CNN
- 3 3100 3250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30 0000 C CNN
-F 1 "PORT" H 3100 3400 30 0000 C CNN
-F 2 "" H 3100 3400 60 0000 C CNN
-F 3 "" H 3100 3400 60 0000 C CNN
- 4 3100 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30 0000 C CNN
-F 1 "PORT" H 6450 3100 30 0000 C CNN
-F 2 "" H 6450 3100 60 0000 C CNN
-F 3 "" H 6450 3100 60 0000 C CNN
- 5 6450 3100
- -1 0 0 1
-$EndComp
-Text Notes 3450 2850 0 60 ~ 12
-in1
-Text Notes 3450 3000 0 60 ~ 12
-in2
-Text Notes 3450 3250 0 60 ~ 12
-in3
-Text Notes 3450 3400 0 60 ~ 12
-in4
-Text Notes 5800 3100 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub index 53fc8b33..d1fd3a24 100644 --- a/src/SubcircuitLibrary/4_OR/4_OR.sub +++ b/src/SubcircuitLibrary/4_OR/4_OR.sub @@ -1,18 +1,18 @@ -* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/4_and/3_and-cache.lib +++ b/src/SubcircuitLibrary/4_and/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/4_and/3_and.cir +++ b/src/SubcircuitLibrary/4_and/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/4_and/3_and.cir.out +++ b/src/SubcircuitLibrary/4_and/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro index 0fdf4d25..76df4655 100644 --- a/src/SubcircuitLibrary/4_and/3_and.pro +++ b/src/SubcircuitLibrary/4_and/3_and.pro @@ -1,44 +1,44 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch index c853bf49..d6ac89f9 100644 --- a/src/SubcircuitLibrary/4_and/3_and.sch +++ b/src/SubcircuitLibrary/4_and/3_and.sch @@ -1,130 +1,130 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/4_and/3_and.sub +++ b/src/SubcircuitLibrary/4_and/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib index cb84d8f2..60f1a83d 100644 --- a/src/SubcircuitLibrary/4_and/4_and-cache.lib +++ b/src/SubcircuitLibrary/4_and/4_and-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib index 6b2c17f7..e3833051 100644 --- a/src/SubcircuitLibrary/4_and/4_and-rescue.lib +++ b/src/SubcircuitLibrary/4_and/4_and-rescue.lib @@ -1,22 +1,22 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir index 35e46097..fdf2e107 100644 --- a/src/SubcircuitLibrary/4_and/4_and.cir +++ b/src/SubcircuitLibrary/4_and/4_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
-U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out index 6e35b18a..f40e5bc6 100644 --- a/src/SubcircuitLibrary/4_and/4_and.cir.out +++ b/src/SubcircuitLibrary/4_and/4_and.cir.out @@ -1,18 +1,18 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro index 814ad76a..9c0be79e 100644 --- a/src/SubcircuitLibrary/4_and/4_and.pro +++ b/src/SubcircuitLibrary/4_and/4_and.pro @@ -1,58 +1,58 @@ -update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
+update=06/01/19 15:08:42 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch index 2d8296d4..f5e8febd 100644 --- a/src/SubcircuitLibrary/4_and/4_and.sch +++ b/src/SubcircuitLibrary/4_and/4_and.sch @@ -1,151 +1,151 @@ -EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
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-$EndDescr
-$Comp
-L 3_and-RESCUE-4_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60 0000 C CNN
-F 1 "3_and" H 4650 4000 60 0000 C CNN
-F 2 "" H 3700 3500 60 0000 C CNN
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-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60 0000 C CNN
-F 1 "d_and" H 5500 3500 60 0000 C CNN
-F 2 "" H 5450 3400 60 0000 C CNN
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-$EndComp
-Wire Wire Line
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-Wire Wire Line
- 5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30 0000 C CNN
-F 1 "PORT" H 2950 2700 30 0000 C CNN
-F 2 "" H 2950 2700 60 0000 C CNN
-F 3 "" H 2950 2700 60 0000 C CNN
- 1 2950 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30 0000 C CNN
-F 1 "PORT" H 2950 3000 30 0000 C CNN
-F 2 "" H 2950 3000 60 0000 C CNN
-F 3 "" H 2950 3000 60 0000 C CNN
- 2 2950 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30 0000 C CNN
-F 1 "PORT" H 3000 3300 30 0000 C CNN
-F 2 "" H 3000 3300 60 0000 C CNN
-F 3 "" H 3000 3300 60 0000 C CNN
- 3 3000 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30 0000 C CNN
-F 1 "PORT" H 3000 3550 30 0000 C CNN
-F 2 "" H 3000 3550 60 0000 C CNN
-F 3 "" H 3000 3550 60 0000 C CNN
- 4 3000 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30 0000 C CNN
-F 1 "PORT" H 6750 3350 30 0000 C CNN
-F 2 "" H 6750 3350 60 0000 C CNN
-F 3 "" H 6750 3350 60 0000 C CNN
- 5 6750 3350
- -1 0 0 1
-$EndComp
-Text Notes 3450 2650 0 60 ~ 12
-in1
-Text Notes 3450 2950 0 60 ~ 12
-in2
-Text Notes 3500 3300 0 60 ~ 12
-in3
-Text Notes 3500 3550 0 60 ~ 12
-in4
-Text Notes 6150 3350 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub index bf20b628..8663f37e 100644 --- a/src/SubcircuitLibrary/4_and/4_and.sub +++ b/src/SubcircuitLibrary/4_and/4_and.sub @@ -1,12 +1,12 @@ -* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib +++ b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir b/src/SubcircuitLibrary/4to16_demux/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/4to16_demux/3_and.cir +++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out +++ b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.pro b/src/SubcircuitLibrary/4to16_demux/3_and.pro index 0fdf4d25..76df4655 100644 --- a/src/SubcircuitLibrary/4to16_demux/3_and.pro +++ b/src/SubcircuitLibrary/4to16_demux/3_and.pro @@ -1,44 +1,44 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sch b/src/SubcircuitLibrary/4to16_demux/3_and.sch index c853bf49..d6ac89f9 100644 --- a/src/SubcircuitLibrary/4to16_demux/3_and.sch +++ b/src/SubcircuitLibrary/4to16_demux/3_and.sch @@ -1,130 +1,130 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
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-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
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-Wire Wire Line
- 3300 2700 3300 2800
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- 3300 3100 4700 3100
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- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sub b/src/SubcircuitLibrary/4to16_demux/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/4to16_demux/3_and.sub +++ b/src/SubcircuitLibrary/4to16_demux/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib index 4cf915be..ac396288 100644 --- a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib +++ b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir b/src/SubcircuitLibrary/4to16_demux/5_and.cir index ca1199bd..6a05b9b5 100644 --- a/src/SubcircuitLibrary/4to16_demux/5_and.cir +++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir @@ -1,14 +1,14 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
-U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
-U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out index 20d3f8a5..6a6b126a 100644 --- a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out +++ b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out @@ -1,22 +1,22 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.pro b/src/SubcircuitLibrary/4to16_demux/5_and.pro index a9d6304f..7a2f090e 100644 --- a/src/SubcircuitLibrary/4to16_demux/5_and.pro +++ b/src/SubcircuitLibrary/4to16_demux/5_and.pro @@ -1,50 +1,50 @@ -update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
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-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
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-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
+update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sch b/src/SubcircuitLibrary/4to16_demux/5_and.sch index 0d86cdec..e9eb58ee 100644 --- a/src/SubcircuitLibrary/4to16_demux/5_and.sch +++ b/src/SubcircuitLibrary/4to16_demux/5_and.sch @@ -1,171 +1,171 @@ -EESchema Schematic File Version 2
-LIBS:cypress
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-LIBS:opto
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-LIBS:contrib
-LIBS:valves
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-LIBS:eSim_Digital
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-LIBS:eSim_Miscellaneous
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-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
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-$Comp
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-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sub b/src/SubcircuitLibrary/4to16_demux/5_and.sub index 9d929fcb..35b10e17 100644 --- a/src/SubcircuitLibrary/4to16_demux/5_and.sub +++ b/src/SubcircuitLibrary/4to16_demux/5_and.sub @@ -1,16 +1,16 @@ -* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/556/556-cache.lib b/src/SubcircuitLibrary/556/556-cache.lib new file mode 100644 index 00000000..75d610da --- /dev/null +++ b/src/SubcircuitLibrary/556/556-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/556/556.cir b/src/SubcircuitLibrary/556/556.cir new file mode 100644 index 00000000..48baa73e --- /dev/null +++ b/src/SubcircuitLibrary/556/556.cir @@ -0,0 +1,13 @@ +* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N +X2 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/src/SubcircuitLibrary/556/556.cir.out b/src/SubcircuitLibrary/556/556.cir.out new file mode 100644 index 00000000..c74aab7c --- /dev/null +++ b/src/SubcircuitLibrary/556/556.cir.out @@ -0,0 +1,15 @@ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir + +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/556/556.pro b/src/SubcircuitLibrary/556/556.pro new file mode 100644 index 00000000..a165313d --- /dev/null +++ b/src/SubcircuitLibrary/556/556.pro @@ -0,0 +1,72 @@ +update=03/18/19 18:13:51 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=microcontrollers +LibName12=dsp +LibName13=microchip +LibName14=analog_switches +LibName15=motorola +LibName16=texas +LibName17=intel +LibName18=audio +LibName19=interface +LibName20=digital-audio +LibName21=philips +LibName22=display +LibName23=cypress +LibName24=siliconi +LibName25=opto +LibName26=atmel +LibName27=contrib +LibName28=valves +LibName29=eSim_User +LibName30=eSim_Subckt +LibName31=eSim_Sources +LibName32=eSim_PSpice +LibName33=eSim_Power +LibName34=eSim_Plot +LibName35=eSim_Miscellaneous +LibName36=eSim_Hybrid +LibName37=eSim_Digital +LibName38=eSim_Devices +LibName39=eSim_Analog diff --git a/src/SubcircuitLibrary/556/556.sch b/src/SubcircuitLibrary/556/556.sch new file mode 100644 index 00000000..af4e1bc9 --- /dev/null +++ b/src/SubcircuitLibrary/556/556.sch @@ -0,0 +1,275 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LM555N X1 +U 1 1 5C8F9298 +P 4150 3850 +F 0 "X1" H 4150 3800 60 0000 C CNN +F 1 "LM555N" H 4150 3950 60 0000 C CNN +F 2 "" H 4100 3850 60 0000 C CNN +F 3 "" H 4100 3850 60 0000 C CNN + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L LM555N X2 +U 1 1 5C8F92E5 +P 7100 3850 +F 0 "X2" H 7100 3800 60 0000 C CNN +F 1 "LM555N" H 7100 3950 60 0000 C CNN +F 2 "" H 7050 3850 60 0000 C CNN +F 3 "" H 7050 3850 60 0000 C CNN + 1 7100 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 3250 4150 3000 +Wire Wire Line + 4150 3000 7100 3000 +Wire Wire Line + 4150 4450 4150 4650 +Wire Wire Line + 4150 4650 7100 4650 +$Comp +L PORT U1 +U 14 1 5C8F93E6 +P 4650 2600 +F 0 "U1" H 4700 2700 30 0000 C CNN +F 1 "PORT" H 4650 2600 30 0000 C CNN +F 2 "" H 4650 2600 60 0000 C CNN +F 3 "" H 4650 2600 60 0000 C CNN + 14 4650 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4900 2600 5000 2600 +Wire Wire Line + 5000 2600 5000 3000 +Connection ~ 5000 3000 +$Comp +L PORT U1 +U 6 1 5C8F94B6 +P 3050 3600 +F 0 "U1" H 3100 3700 30 0000 C CNN +F 1 "PORT" H 3050 3600 30 0000 C CNN +F 2 "" H 3050 3600 60 0000 C CNN +F 3 "" H 3050 3600 60 0000 C CNN + 6 3050 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C8F95C0 +P 3050 3850 +F 0 "U1" H 3100 3950 30 0000 C CNN +F 1 "PORT" H 3050 3850 30 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 3 3050 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C8F95E7 +P 3050 4100 +F 0 "U1" H 3100 4200 30 0000 C CNN +F 1 "PORT" H 3050 4100 30 0000 C CNN +F 2 "" H 3050 4100 60 0000 C CNN +F 3 "" H 3050 4100 60 0000 C CNN + 4 3050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 3000 7100 3250 +Wire Wire Line + 7100 4650 7100 4450 +$Comp +L PORT U1 +U 8 1 5C8F9C35 +P 6000 3600 +F 0 "U1" H 6050 3700 30 0000 C CNN +F 1 "PORT" H 6000 3600 30 0000 C CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 8 6000 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C8F9C3B +P 6000 3850 +F 0 "U1" H 6050 3950 30 0000 C CNN +F 1 "PORT" H 6000 3850 30 0000 C CNN +F 2 "" H 6000 3850 60 0000 C CNN +F 3 "" H 6000 3850 60 0000 C CNN + 11 6000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C8F9C41 +P 6000 4100 +F 0 "U1" H 6050 4200 30 0000 C CNN +F 1 "PORT" H 6000 4100 30 0000 C CNN +F 2 "" H 6000 4100 60 0000 C CNN +F 3 "" H 6000 4100 60 0000 C CNN + 10 6000 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C8F9D22 +P 5200 4100 +F 0 "U1" H 5250 4200 30 0000 C CNN +F 1 "PORT" H 5200 4100 30 0000 C CNN +F 2 "" H 5200 4100 60 0000 C CNN +F 3 "" H 5200 4100 60 0000 C CNN + 2 5200 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C8F9D28 +P 5200 3850 +F 0 "U1" H 5250 3950 30 0000 C CNN +F 1 "PORT" H 5200 3850 30 0000 C CNN +F 2 "" H 5200 3850 60 0000 C CNN +F 3 "" H 5200 3850 60 0000 C CNN + 1 5200 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C8F9D2E +P 5200 3600 +F 0 "U1" H 5250 3700 30 0000 C CNN +F 1 "PORT" H 5200 3600 30 0000 C CNN +F 2 "" H 5200 3600 60 0000 C CNN +F 3 "" H 5200 3600 60 0000 C CNN + 5 5200 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C8FA0FA +P 8250 4100 +F 0 "U1" H 8300 4200 30 0000 C CNN +F 1 "PORT" H 8250 4100 30 0000 C CNN +F 2 "" H 8250 4100 60 0000 C CNN +F 3 "" H 8250 4100 60 0000 C CNN + 12 8250 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C8FA100 +P 8250 3850 +F 0 "U1" H 8300 3950 30 0000 C CNN +F 1 "PORT" H 8250 3850 30 0000 C CNN +F 2 "" H 8250 3850 60 0000 C CNN +F 3 "" H 8250 3850 60 0000 C CNN + 13 8250 3850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C8FA106 +P 8250 3600 +F 0 "U1" H 8300 3700 30 0000 C CNN +F 1 "PORT" H 8250 3600 30 0000 C CNN +F 2 "" H 8250 3600 60 0000 C CNN +F 3 "" H 8250 3600 60 0000 C CNN + 9 8250 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C8FA319 +P 4950 5050 +F 0 "U1" H 5000 5150 30 0000 C CNN +F 1 "PORT" H 4950 5050 30 0000 C CNN +F 2 "" H 4950 5050 60 0000 C CNN +F 3 "" H 4950 5050 60 0000 C CNN + 7 4950 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5200 5050 5200 4650 +Connection ~ 5200 4650 +Wire Wire Line + 3300 3600 3600 3600 +Wire Wire Line + 3300 3850 3600 3850 +Wire Wire Line + 3300 4100 3600 4100 +Wire Wire Line + 4700 3600 4950 3600 +Wire Wire Line + 4700 3850 4950 3850 +Wire Wire Line + 4700 4100 4950 4100 +Wire Wire Line + 6250 3600 6550 3600 +Wire Wire Line + 6250 3850 6550 3850 +Wire Wire Line + 6250 4100 6550 4100 +Wire Wire Line + 8000 3600 7650 3600 +Wire Wire Line + 8000 3850 7650 3850 +Wire Wire Line + 8000 4100 7650 4100 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/556/556.sub b/src/SubcircuitLibrary/556/556.sub new file mode 100644 index 00000000..a370b703 --- /dev/null +++ b/src/SubcircuitLibrary/556/556.sub @@ -0,0 +1,9 @@ +* Subcircuit 556 +.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\esim\esim\src\subcircuitlibrary\556\556.cir +.include lm555n.sub +x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n +x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n +* Control Statements + +.ends 556
\ No newline at end of file diff --git a/src/SubcircuitLibrary/556/556_Previous_Values.xml b/src/SubcircuitLibrary/556/556_Previous_Values.xml new file mode 100644 index 00000000..c025c2d1 --- /dev/null +++ b/src/SubcircuitLibrary/556/556_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/5_and/3_and-cache.lib +++ b/src/SubcircuitLibrary/5_and/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/5_and/3_and.cir +++ b/src/SubcircuitLibrary/5_and/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/5_and/3_and.cir.out +++ b/src/SubcircuitLibrary/5_and/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro index 0fdf4d25..76df4655 100644 --- a/src/SubcircuitLibrary/5_and/3_and.pro +++ b/src/SubcircuitLibrary/5_and/3_and.pro @@ -1,44 +1,44 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch index c853bf49..d6ac89f9 100644 --- a/src/SubcircuitLibrary/5_and/3_and.sch +++ b/src/SubcircuitLibrary/5_and/3_and.sch @@ -1,130 +1,130 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
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-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
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-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
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-F 0 "U1" H 3100 3200 30 0000 C CNN
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-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
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-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
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-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/5_and/3_and.sub +++ b/src/SubcircuitLibrary/5_and/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib index 4cf915be..ac396288 100644 --- a/src/SubcircuitLibrary/5_and/5_and-cache.lib +++ b/src/SubcircuitLibrary/5_and/5_and-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir index ca1199bd..6a05b9b5 100644 --- a/src/SubcircuitLibrary/5_and/5_and.cir +++ b/src/SubcircuitLibrary/5_and/5_and.cir @@ -1,14 +1,14 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
-U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
-U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out index 20d3f8a5..6a6b126a 100644 --- a/src/SubcircuitLibrary/5_and/5_and.cir.out +++ b/src/SubcircuitLibrary/5_and/5_and.cir.out @@ -1,22 +1,22 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro index a9d6304f..7a2f090e 100644 --- a/src/SubcircuitLibrary/5_and/5_and.pro +++ b/src/SubcircuitLibrary/5_and/5_and.pro @@ -1,50 +1,50 @@ -update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
+update=06/01/19 11:31:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch index 0d86cdec..e9eb58ee 100644 --- a/src/SubcircuitLibrary/5_and/5_and.sch +++ b/src/SubcircuitLibrary/5_and/5_and.sch @@ -1,171 +1,171 @@ -EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60 0000 C CNN
-F 1 "3_and" H 4750 3850 60 0000 C CNN
-F 2 "" H 3800 3350 60 0000 C CNN
-F 3 "" H 3800 3350 60 0000 C CNN
- 1 3800 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2764
-P 4650 3400
-F 0 "U2" H 4650 3400 60 0000 C CNN
-F 1 "d_and" H 4700 3500 60 0000 C CNN
-F 2 "" H 4650 3400 60 0000 C CNN
-F 3 "" H 4650 3400 60 0000 C CNN
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-$Comp
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-$Comp
-L PORT U1
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-F 0 "U1" H 3400 2800 30 0000 C CNN
-F 1 "PORT" H 3350 2700 30 0000 C CNN
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-$EndComp
-$Comp
-L PORT U1
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-F 0 "U1" H 3400 3000 30 0000 C CNN
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-F 2 "" H 3350 2900 60 0000 C CNN
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- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A28D9
-P 3350 3100
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-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A28FF
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-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
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-F 3 "" H 3350 3500 60 0000 C CNN
- 5 3350 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
-P 6750 3150
-F 0 "U1" H 6800 3250 30 0000 C CNN
-F 1 "PORT" H 6750 3150 30 0000 C CNN
-F 2 "" H 6750 3150 60 0000 C CNN
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-$EndComp
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-in4
-Text Notes 3800 3500 0 60 ~ 12
-in5
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-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub index 9d929fcb..35b10e17 100644 --- a/src/SubcircuitLibrary/5_and/5_and.sub +++ b/src/SubcircuitLibrary/5_and/5_and.sub @@ -1,16 +1,16 @@ -* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and-cache.lib b/src/SubcircuitLibrary/74153/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/74153/3_and-cache.lib +++ b/src/SubcircuitLibrary/74153/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/3_and.cir b/src/SubcircuitLibrary/74153/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/74153/3_and.cir +++ b/src/SubcircuitLibrary/74153/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/3_and.cir.out b/src/SubcircuitLibrary/74153/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/74153/3_and.cir.out +++ b/src/SubcircuitLibrary/74153/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/3_and.pro b/src/SubcircuitLibrary/74153/3_and.pro index 0fdf4d25..2c9ac554 100644 --- a/src/SubcircuitLibrary/74153/3_and.pro +++ b/src/SubcircuitLibrary/74153/3_and.pro @@ -1,44 +1,58 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74153/3_and.sch b/src/SubcircuitLibrary/74153/3_and.sch index c853bf49..86be0215 100644 --- a/src/SubcircuitLibrary/74153/3_and.sch +++ b/src/SubcircuitLibrary/74153/3_and.sch @@ -1,130 +1,121 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
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-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/3_and.sub b/src/SubcircuitLibrary/74153/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/74153/3_and.sub +++ b/src/SubcircuitLibrary/74153/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR-cache.lib b/src/SubcircuitLibrary/74153/4_OR-cache.lib index a3c1c972..155f5e60 100644 --- a/src/SubcircuitLibrary/74153/4_OR-cache.lib +++ b/src/SubcircuitLibrary/74153/4_OR-cache.lib @@ -1,63 +1,63 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_OR.cir b/src/SubcircuitLibrary/74153/4_OR.cir index 7adbf177..b338b7b5 100644 --- a/src/SubcircuitLibrary/74153/4_OR.cir +++ b/src/SubcircuitLibrary/74153/4_OR.cir @@ -1,14 +1,14 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
-U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
-U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/4_OR.cir.out b/src/SubcircuitLibrary/74153/4_OR.cir.out index 4388b975..adb6b01b 100644 --- a/src/SubcircuitLibrary/74153/4_OR.cir.out +++ b/src/SubcircuitLibrary/74153/4_OR.cir.out @@ -1,24 +1,24 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/4_OR.pro b/src/SubcircuitLibrary/74153/4_OR.pro index 1e19b3a7..2c258cec 100644 --- a/src/SubcircuitLibrary/74153/4_OR.pro +++ b/src/SubcircuitLibrary/74153/4_OR.pro @@ -1,45 +1,45 @@ -update=06/01/19 12:36:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
+update=03/28/19 22:43:48 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_OR.sch b/src/SubcircuitLibrary/74153/4_OR.sch index 2f28896c..11896865 100644 --- a/src/SubcircuitLibrary/74153/4_OR.sch +++ b/src/SubcircuitLibrary/74153/4_OR.sch @@ -1,150 +1,150 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C9D00E1
-P 4300 2950
-F 0 "U2" H 4300 2950 60 0000 C CNN
-F 1 "d_or" H 4300 3050 60 0000 C CNN
-F 2 "" H 4300 2950 60 0000 C CNN
-F 3 "" H 4300 2950 60 0000 C CNN
- 1 4300 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60 0000 C CNN
-F 1 "d_or" H 4300 3450 60 0000 C CNN
-F 2 "" H 4300 3350 60 0000 C CNN
-F 3 "" H 4300 3350 60 0000 C CNN
- 1 4300 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60 0000 C CNN
-F 1 "d_or" H 5250 3250 60 0000 C CNN
-F 2 "" H 5250 3150 60 0000 C CNN
-F 3 "" H 5250 3150 60 0000 C CNN
- 1 5250 3150
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4800 3050 4800 2900
-Wire Wire Line
- 4800 2900 4750 2900
-Wire Wire Line
- 4800 3150 4800 3300
-Wire Wire Line
- 4800 3300 4750 3300
-Wire Wire Line
- 3350 2850 3850 2850
-Wire Wire Line
- 3850 2950 3600 2950
-Wire Wire Line
- 3850 3250 3350 3250
-Wire Wire Line
- 3600 2950 3600 3000
-Wire Wire Line
- 3600 3000 3350 3000
-Wire Wire Line
- 3850 3350 3850 3400
-Wire Wire Line
- 3850 3400 3350 3400
-Wire Wire Line
- 5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30 0000 C CNN
-F 1 "PORT" H 3100 2850 30 0000 C CNN
-F 2 "" H 3100 2850 60 0000 C CNN
-F 3 "" H 3100 2850 60 0000 C CNN
- 1 3100 2850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
-P 3100 3000
-F 0 "U1" H 3150 3100 30 0000 C CNN
-F 1 "PORT" H 3100 3000 30 0000 C CNN
-F 2 "" H 3100 3000 60 0000 C CNN
-F 3 "" H 3100 3000 60 0000 C CNN
- 2 3100 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
-P 3100 3250
-F 0 "U1" H 3150 3350 30 0000 C CNN
-F 1 "PORT" H 3100 3250 30 0000 C CNN
-F 2 "" H 3100 3250 60 0000 C CNN
-F 3 "" H 3100 3250 60 0000 C CNN
- 3 3100 3250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30 0000 C CNN
-F 1 "PORT" H 3100 3400 30 0000 C CNN
-F 2 "" H 3100 3400 60 0000 C CNN
-F 3 "" H 3100 3400 60 0000 C CNN
- 4 3100 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30 0000 C CNN
-F 1 "PORT" H 6450 3100 30 0000 C CNN
-F 2 "" H 6450 3100 60 0000 C CNN
-F 3 "" H 6450 3100 60 0000 C CNN
- 5 6450 3100
- -1 0 0 1
-$EndComp
-Text Notes 3450 2850 0 60 ~ 12
-in1
-Text Notes 3450 3000 0 60 ~ 12
-in2
-Text Notes 3450 3250 0 60 ~ 12
-in3
-Text Notes 3450 3400 0 60 ~ 12
-in4
-Text Notes 5800 3100 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub index 53fc8b33..d1fd3a24 100644 --- a/src/SubcircuitLibrary/74153/4_OR.sub +++ b/src/SubcircuitLibrary/74153/4_OR.sub @@ -1,18 +1,18 @@ -* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml index 0683d9eb..23698d37 100644 --- a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml +++ b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and-cache.lib b/src/SubcircuitLibrary/74153/4_and-cache.lib index cb84d8f2..ac396288 100644 --- a/src/SubcircuitLibrary/74153/4_and-cache.lib +++ b/src/SubcircuitLibrary/74153/4_and-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/4_and.cir b/src/SubcircuitLibrary/74153/4_and.cir index 35e46097..50d490fa 100644 --- a/src/SubcircuitLibrary/74153/4_and.cir +++ b/src/SubcircuitLibrary/74153/4_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
-U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/74153/4_and.cir.out b/src/SubcircuitLibrary/74153/4_and.cir.out index 6e35b18a..f40e5bc6 100644 --- a/src/SubcircuitLibrary/74153/4_and.cir.out +++ b/src/SubcircuitLibrary/74153/4_and.cir.out @@ -1,18 +1,18 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74153/4_and.pro b/src/SubcircuitLibrary/74153/4_and.pro index 814ad76a..6eb77fff 100644 --- a/src/SubcircuitLibrary/74153/4_and.pro +++ b/src/SubcircuitLibrary/74153/4_and.pro @@ -1,58 +1,57 @@ -update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
+update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_and.sch b/src/SubcircuitLibrary/74153/4_and.sch index 2d8296d4..883458e1 100644 --- a/src/SubcircuitLibrary/74153/4_and.sch +++ b/src/SubcircuitLibrary/74153/4_and.sch @@ -1,151 +1,139 @@ -EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and-RESCUE-4_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60 0000 C CNN
-F 1 "3_and" H 4650 4000 60 0000 C CNN
-F 2 "" H 3700 3500 60 0000 C CNN
-F 3 "" H 3700 3500 60 0000 C CNN
- 1 3700 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60 0000 C CNN
-F 1 "d_and" H 5500 3500 60 0000 C CNN
-F 2 "" H 5450 3400 60 0000 C CNN
-F 3 "" H 5450 3400 60 0000 C CNN
- 1 5450 3400
- 1 0 0 -1
-$EndComp
-Wire Wire Line
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-Wire Wire Line
- 4150 3000 4150 2700
-Wire Wire Line
- 4150 2700 3200 2700
-Wire Wire Line
- 4150 3100 4000 3100
-Wire Wire Line
- 4000 3100 4000 3000
-Wire Wire Line
- 4000 3000 3200 3000
-Wire Wire Line
- 4150 3200 4150 3300
-Wire Wire Line
- 4150 3300 3250 3300
-Wire Wire Line
- 5000 3400 5000 3550
-Wire Wire Line
- 5000 3550 3250 3550
-Wire Wire Line
- 5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30 0000 C CNN
-F 1 "PORT" H 2950 2700 30 0000 C CNN
-F 2 "" H 2950 2700 60 0000 C CNN
-F 3 "" H 2950 2700 60 0000 C CNN
- 1 2950 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30 0000 C CNN
-F 1 "PORT" H 2950 3000 30 0000 C CNN
-F 2 "" H 2950 3000 60 0000 C CNN
-F 3 "" H 2950 3000 60 0000 C CNN
- 2 2950 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30 0000 C CNN
-F 1 "PORT" H 3000 3300 30 0000 C CNN
-F 2 "" H 3000 3300 60 0000 C CNN
-F 3 "" H 3000 3300 60 0000 C CNN
- 3 3000 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30 0000 C CNN
-F 1 "PORT" H 3000 3550 30 0000 C CNN
-F 2 "" H 3000 3550 60 0000 C CNN
-F 3 "" H 3000 3550 60 0000 C CNN
- 4 3000 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30 0000 C CNN
-F 1 "PORT" H 6750 3350 30 0000 C CNN
-F 2 "" H 6750 3350 60 0000 C CNN
-F 3 "" H 6750 3350 60 0000 C CNN
- 5 6750 3350
- -1 0 0 1
-$EndComp
-Text Notes 3450 2650 0 60 ~ 12
-in1
-Text Notes 3450 2950 0 60 ~ 12
-in2
-Text Notes 3500 3300 0 60 ~ 12
-in3
-Text Notes 3500 3550 0 60 ~ 12
-in4
-Text Notes 6150 3350 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_and.sub b/src/SubcircuitLibrary/74153/4_and.sub index bf20b628..8663f37e 100644 --- a/src/SubcircuitLibrary/74153/4_and.sub +++ b/src/SubcircuitLibrary/74153/4_and.sub @@ -1,12 +1,12 @@ -* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153-cache.lib b/src/SubcircuitLibrary/74153/74153-cache.lib index 4f81c933..1e85854e 100644 --- a/src/SubcircuitLibrary/74153/74153-cache.lib +++ b/src/SubcircuitLibrary/74153/74153-cache.lib @@ -4,40 +4,40 @@ EESchema-LIBRARY Version 2.3 # 4_OR # DEF 4_OR X 0 40 Y Y 1 F N -F0 "X" 150 -100 60 H V C CNN -F1 "4_OR" 150 100 60 H V C CNN +F0 "X" 3900 3050 60 H V C CNN +F1 "4_OR" 3900 3250 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 -A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 -A -30 -99 393 627 146 0 1 0 N 150 250 350 0 -P 2 0 1 0 -200 -250 150 -250 N -P 2 0 1 0 -200 250 150 250 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X in4 4 -350 -150 200 R 50 50 1 1 I -X out 5 550 0 200 L 50 50 1 1 O +A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 +A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 +A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 +P 2 0 1 0 3550 2900 3900 2900 N +P 2 0 1 0 3550 3400 3900 3400 N +X in1 1 3400 3300 200 R 50 50 1 1 I +X in2 2 3400 3200 200 R 50 50 1 1 I +X in3 3 3400 3100 200 R 50 50 1 1 I +X in4 4 3400 3000 200 R 50 50 1 1 I +X out 5 4300 3150 200 L 50 50 1 1 O ENDDRAW ENDDEF # # 4_and # DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "4_and" 100 100 60 H V C CNN +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 -P 2 0 1 0 -200 200 150 200 N -P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N -X in1 1 -400 150 200 R 50 50 1 1 I -X in2 2 -400 50 200 R 50 50 1 1 I -X in3 3 -400 -50 200 R 50 50 1 1 I -X in4 4 -400 -150 200 R 50 50 1 1 I -X out 5 500 0 200 L 50 50 1 1 O +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O ENDDRAW ENDDEF # @@ -89,7 +89,7 @@ F1 "d_inverter" 0 150 60 H V C CNN F2 "" 50 -50 60 H V C CNN F3 "" 50 -50 60 H V C CNN DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N X ~ 1 -300 0 200 R 50 50 1 1 I X ~ 2 300 0 200 L 50 50 1 1 O I ENDDRAW diff --git a/src/SubcircuitLibrary/74153/74153.cir b/src/SubcircuitLibrary/74153/74153.cir index 955b30b1..b20e6858 100644 --- a/src/SubcircuitLibrary/74153/74153.cir +++ b/src/SubcircuitLibrary/74153/74153.cir @@ -1,25 +1,25 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74153/74153.cir +* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 26 15:19:41 2019 +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 * Sheet Name: / -U2 Net-_U1-Pad14_ Net-_U2-Pad2_ d_inverter -U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT -U35 Net-_U1-Pad1_ Net-_U35-Pad2_ d_inverter -U34 Net-_U1-Pad15_ Net-_U34-Pad2_ d_inverter -X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and -X9 Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and -X4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and -X10 Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and -X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad10_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and -X6 Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U1-Pad11_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and -X3 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad12_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and -X7 Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad13_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and -X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad9_ 4_OR -X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad7_ 4_OR +U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U35 Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter +U34 Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter +X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and +X9 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and +X4 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and +X10 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and +X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and +X6 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and +X3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and +X7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR +X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR .end diff --git a/src/SubcircuitLibrary/74153/74153.cir.out b/src/SubcircuitLibrary/74153/74153.cir.out index 93b8fdd1..c95e5ad9 100644 --- a/src/SubcircuitLibrary/74153/74153.cir.out +++ b/src/SubcircuitLibrary/74153/74153.cir.out @@ -1,26 +1,26 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74153/74153.cir +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir .include 4_and.sub .include 4_OR.sub -* u2 net-_u1-pad14_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port -* u35 net-_u1-pad1_ net-_u35-pad2_ d_inverter -* u34 net-_u1-pad15_ net-_u34-pad2_ d_inverter -x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u35-pad2_ net-_x2-pad1_ 4_and -x9 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad5_ net-_u35-pad2_ net-_x2-pad2_ 4_and -x4 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u35-pad2_ net-_x2-pad3_ 4_and -x10 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u35-pad2_ net-_x10-pad5_ 4_and -x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad10_ net-_u34-pad2_ net-_x1-pad1_ 4_and -x6 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad11_ net-_u34-pad2_ net-_x1-pad2_ 4_and -x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad12_ net-_u34-pad2_ net-_x1-pad3_ 4_and -x7 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad13_ net-_u34-pad2_ net-_x1-pad4_ 4_and -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad9_ 4_OR -x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad7_ 4_OR -a1 net-_u1-pad14_ net-_u2-pad2_ u2 -a2 net-_u1-pad2_ net-_u3-pad2_ u3 -a3 net-_u1-pad1_ net-_u35-pad2_ u35 -a4 net-_u1-pad15_ net-_u34-pad2_ u34 +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter @@ -29,7 +29,7 @@ a4 net-_u1-pad15_ net-_u34-pad2_ u34 .model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-03 0e-00 0e-03 +.tran 0e-00 0e-00 0e-00 * Control Statements .control diff --git a/src/SubcircuitLibrary/74153/74153.pro b/src/SubcircuitLibrary/74153/74153.pro index 78440d11..ed8b8bf2 100644 --- a/src/SubcircuitLibrary/74153/74153.pro +++ b/src/SubcircuitLibrary/74153/74153.pro @@ -1,4 +1,4 @@ -update=Tue Jun 25 16:51:16 2019 +update=03/28/19 23:27:36 version=1 last_client=eeschema [general] @@ -29,15 +29,31 @@ version=1 NetIExt=net [eeschema] version=1 -LibDir=../../../kicadSchematicLibrary +LibDir= [eeschema/libraries] -LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName1=power +LibName2=device +LibName3=texas +LibName4=intel +LibName5=audio +LibName6=interface +LibName7=digital-audio +LibName8=philips +LibName9=display +LibName10=cypress +LibName11=siliconi +LibName12=opto +LibName13=atmel +LibName14=contrib +LibName15=valves +LibName16=eSim_Analog +LibName17=eSim_Devices +LibName18=eSim_Digital +LibName19=eSim_Hybrid +LibName20=eSim_Miscellaneous +LibName21=eSim_Plot +LibName22=eSim_Power +LibName23=eSim_PSpice +LibName24=eSim_Sources +LibName25=eSim_User +LibName26=eSim_Subckt diff --git a/src/SubcircuitLibrary/74153/74153.sch b/src/SubcircuitLibrary/74153/74153.sch index fc9b4516..e0bcf950 100644 --- a/src/SubcircuitLibrary/74153/74153.sch +++ b/src/SubcircuitLibrary/74153/74153.sch @@ -1,4 +1,19 @@ EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves LIBS:eSim_Analog LIBS:eSim_Devices LIBS:eSim_Digital @@ -6,9 +21,10 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power +LIBS:eSim_PSpice LIBS:eSim_Sources -LIBS:eSim_Subckt LIBS:eSim_User +LIBS:eSim_Subckt LIBS:74153-cache EELAYER 25 0 EELAYER END @@ -48,156 +64,156 @@ F 3 "" H 2750 900 60 0000 C CNN $EndComp $Comp L PORT U1 -U 6 1 5C93A0F9 +U 1 1 5C93A0F9 P 1350 2050 F 0 "U1" H 1400 2150 30 0000 C CNN F 1 "PORT" H 1350 2050 30 0000 C CNN F 2 "" H 1350 2050 60 0000 C CNN F 3 "" H 1350 2050 60 0000 C CNN - 6 1350 2050 + 1 1350 2050 1 0 0 -1 $EndComp $Comp L PORT U1 -U 10 1 5C93A174 +U 6 1 5C93A174 P 1350 4700 F 0 "U1" H 1400 4800 30 0000 C CNN F 1 "PORT" H 1350 4700 30 0000 C CNN F 2 "" H 1350 4700 60 0000 C CNN F 3 "" H 1350 4700 60 0000 C CNN - 10 1350 4700 + 6 1350 4700 1 0 0 -1 $EndComp $Comp L PORT U1 -U 5 1 5C93AA3C +U 2 1 5C93AA3C P 1350 2600 F 0 "U1" H 1400 2700 30 0000 C CNN F 1 "PORT" H 1350 2600 30 0000 C CNN F 2 "" H 1350 2600 60 0000 C CNN F 3 "" H 1350 2600 60 0000 C CNN - 5 1350 2600 + 2 1350 2600 1 0 0 -1 $EndComp $Comp L PORT U1 -U 4 1 5C93AACB +U 3 1 5C93AACB P 1350 3200 F 0 "U1" H 1400 3300 30 0000 C CNN F 1 "PORT" H 1350 3200 30 0000 C CNN F 2 "" H 1350 3200 60 0000 C CNN F 3 "" H 1350 3200 60 0000 C CNN - 4 1350 3200 + 3 1350 3200 1 0 0 -1 $EndComp $Comp L PORT U1 -U 3 1 5C93AB5F +U 4 1 5C93AB5F P 1350 3700 F 0 "U1" H 1400 3800 30 0000 C CNN F 1 "PORT" H 1350 3700 30 0000 C CNN F 2 "" H 1350 3700 60 0000 C CNN F 3 "" H 1350 3700 60 0000 C CNN - 3 1350 3700 + 4 1350 3700 1 0 0 -1 $EndComp $Comp L PORT U1 -U 11 1 5C93AD97 +U 7 1 5C93AD97 P 1350 5250 F 0 "U1" H 1400 5350 30 0000 C CNN F 1 "PORT" H 1350 5250 30 0000 C CNN F 2 "" H 1350 5250 60 0000 C CNN F 3 "" H 1350 5250 60 0000 C CNN - 11 1350 5250 + 7 1350 5250 1 0 0 -1 $EndComp $Comp L PORT U1 -U 12 1 5C93ADFC +U 8 1 5C93ADFC P 1350 5850 F 0 "U1" H 1400 5950 30 0000 C CNN F 1 "PORT" H 1350 5850 30 0000 C CNN F 2 "" H 1350 5850 60 0000 C CNN F 3 "" H 1350 5850 60 0000 C CNN - 12 1350 5850 + 8 1350 5850 1 0 0 -1 $EndComp $Comp L PORT U1 -U 13 1 5C93AE63 +U 9 1 5C93AE63 P 1350 6350 F 0 "U1" H 1400 6450 30 0000 C CNN F 1 "PORT" H 1350 6350 30 0000 C CNN F 2 "" H 1350 6350 60 0000 C CNN F 3 "" H 1350 6350 60 0000 C CNN - 13 1350 6350 + 9 1350 6350 1 0 0 -1 $EndComp $Comp L PORT U1 -U 1 1 5C93AECA +U 5 1 5C93AECA P 1350 3950 F 0 "U1" H 1400 4050 30 0000 C CNN F 1 "PORT" H 1350 3950 30 0000 C CNN F 2 "" H 1350 3950 60 0000 C CNN F 3 "" H 1350 3950 60 0000 C CNN - 1 1350 3950 + 5 1350 3950 1 0 0 -1 $EndComp $Comp L PORT U1 -U 15 1 5C93AF79 +U 10 1 5C93AF79 P 1350 6600 F 0 "U1" H 1400 6700 30 0000 C CNN F 1 "PORT" H 1350 6600 30 0000 C CNN F 2 "" H 1350 6600 60 0000 C CNN F 3 "" H 1350 6600 60 0000 C CNN - 15 1350 6600 + 10 1350 6600 1 0 0 -1 $EndComp $Comp L PORT U1 -U 2 1 5C93B10A +U 11 1 5C93B10A P 1550 950 F 0 "U1" H 1600 1050 30 0000 C CNN F 1 "PORT" H 1550 950 30 0000 C CNN F 2 "" H 1550 950 60 0000 C CNN F 3 "" H 1550 950 60 0000 C CNN - 2 1550 950 + 11 1550 950 1 0 0 -1 $EndComp $Comp L PORT U1 -U 14 1 5C93B179 +U 12 1 5C93B179 P 1550 1350 F 0 "U1" H 1600 1450 30 0000 C CNN F 1 "PORT" H 1550 1350 30 0000 C CNN F 2 "" H 1550 1350 60 0000 C CNN F 3 "" H 1550 1350 60 0000 C CNN - 14 1550 1350 + 12 1550 1350 1 0 0 -1 $EndComp $Comp L PORT U1 -U 7 1 5C93B567 +U 13 1 5C93B567 P 7850 2600 F 0 "U1" H 7900 2700 30 0000 C CNN F 1 "PORT" H 7850 2600 30 0000 C CNN F 2 "" H 7850 2600 60 0000 C CNN F 3 "" H 7850 2600 60 0000 C CNN - 7 7850 2600 + 13 7850 2600 -1 0 0 1 $EndComp $Comp L PORT U1 -U 9 1 5C93B5DA +U 14 1 5C93B5DA P 7900 5250 F 0 "U1" H 7950 5350 30 0000 C CNN F 1 "PORT" H 7900 5250 30 0000 C CNN F 2 "" H 7900 5250 60 0000 C CNN F 3 "" H 7900 5250 60 0000 C CNN - 9 7900 5250 + 14 7900 5250 -1 0 0 1 $EndComp $Comp @@ -253,89 +269,89 @@ YB $Comp L 4_and X8 U 1 1 5C9D0C22 -P 4200 1950 -F 0 "X8" H 4250 1950 60 0000 C CNN -F 1 "4_and" H 4300 2050 60 0000 C CNN -F 2 "" H 4200 1950 60 0000 C CNN -F 3 "" H 4200 1950 60 0000 C CNN - 1 4200 1950 +P 2750 3050 +F 0 "X8" H 4250 4100 60 0000 C CNN +F 1 "4_and" H 4300 4250 60 0000 C CNN +F 2 "" H 2750 3050 60 0000 C CNN +F 3 "" H 2750 3050 60 0000 C CNN + 1 2750 3050 1 0 0 -1 $EndComp $Comp L 4_and X9 U 1 1 5C9D0CA2 -P 4200 2500 -F 0 "X9" H 4250 2500 60 0000 C CNN -F 1 "4_and" H 4300 2600 60 0000 C CNN -F 2 "" H 4200 2500 60 0000 C CNN -F 3 "" H 4200 2500 60 0000 C CNN - 1 4200 2500 +P 2750 3600 +F 0 "X9" H 4250 4650 60 0000 C CNN +F 1 "4_and" H 4300 4800 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 1 0 0 -1 $EndComp $Comp L 4_and X4 U 1 1 5C9D0D16 -P 4150 3100 -F 0 "X4" H 4200 3100 60 0000 C CNN -F 1 "4_and" H 4250 3200 60 0000 C CNN -F 2 "" H 4150 3100 60 0000 C CNN -F 3 "" H 4150 3100 60 0000 C CNN - 1 4150 3100 +P 2700 4200 +F 0 "X4" H 4200 5250 60 0000 C CNN +F 1 "4_and" H 4250 5400 60 0000 C CNN +F 2 "" H 2700 4200 60 0000 C CNN +F 3 "" H 2700 4200 60 0000 C CNN + 1 2700 4200 1 0 0 -1 $EndComp $Comp L 4_and X10 U 1 1 5C9D0D93 -P 4200 3600 -F 0 "X10" H 4250 3600 60 0000 C CNN -F 1 "4_and" H 4300 3700 60 0000 C CNN -F 2 "" H 4200 3600 60 0000 C CNN -F 3 "" H 4200 3600 60 0000 C CNN - 1 4200 3600 +P 2750 4700 +F 0 "X10" H 4250 5750 60 0000 C CNN +F 1 "4_and" H 4300 5900 60 0000 C CNN +F 2 "" H 2750 4700 60 0000 C CNN +F 3 "" H 2750 4700 60 0000 C CNN + 1 2750 4700 1 0 0 -1 $EndComp $Comp L 4_and X5 U 1 1 5C9D182A -P 4150 4600 -F 0 "X5" H 4200 4600 60 0000 C CNN -F 1 "4_and" H 4250 4700 60 0000 C CNN -F 2 "" H 4150 4600 60 0000 C CNN -F 3 "" H 4150 4600 60 0000 C CNN - 1 4150 4600 +P 2700 5700 +F 0 "X5" H 4200 6750 60 0000 C CNN +F 1 "4_and" H 4250 6900 60 0000 C CNN +F 2 "" H 2700 5700 60 0000 C CNN +F 3 "" H 2700 5700 60 0000 C CNN + 1 2700 5700 1 0 0 -1 $EndComp $Comp L 4_and X6 U 1 1 5C9D1830 -P 4150 5150 -F 0 "X6" H 4200 5150 60 0000 C CNN -F 1 "4_and" H 4250 5250 60 0000 C CNN -F 2 "" H 4150 5150 60 0000 C CNN -F 3 "" H 4150 5150 60 0000 C CNN - 1 4150 5150 +P 2700 6250 +F 0 "X6" H 4200 7300 60 0000 C CNN +F 1 "4_and" H 4250 7450 60 0000 C CNN +F 2 "" H 2700 6250 60 0000 C CNN +F 3 "" H 2700 6250 60 0000 C CNN + 1 2700 6250 1 0 0 -1 $EndComp $Comp L 4_and X3 U 1 1 5C9D1836 -P 4100 5750 -F 0 "X3" H 4150 5750 60 0000 C CNN -F 1 "4_and" H 4200 5850 60 0000 C CNN -F 2 "" H 4100 5750 60 0000 C CNN -F 3 "" H 4100 5750 60 0000 C CNN - 1 4100 5750 +P 2650 6850 +F 0 "X3" H 4150 7900 60 0000 C CNN +F 1 "4_and" H 4200 8050 60 0000 C CNN +F 2 "" H 2650 6850 60 0000 C CNN +F 3 "" H 2650 6850 60 0000 C CNN + 1 2650 6850 1 0 0 -1 $EndComp $Comp L 4_and X7 U 1 1 5C9D183C -P 4150 6250 -F 0 "X7" H 4200 6250 60 0000 C CNN -F 1 "4_and" H 4250 6350 60 0000 C CNN -F 2 "" H 4150 6250 60 0000 C CNN -F 3 "" H 4150 6250 60 0000 C CNN - 1 4150 6250 +P 2700 7350 +F 0 "X7" H 4200 8400 60 0000 C CNN +F 1 "4_and" H 4250 8550 60 0000 C CNN +F 2 "" H 2700 7350 60 0000 C CNN +F 3 "" H 2700 7350 60 0000 C CNN + 1 2700 7350 1 0 0 -1 $EndComp Wire Wire Line @@ -498,12 +514,12 @@ Wire Wire Line $Comp L 4_OR X1 U 1 1 5C9D22F7 -P 5900 5250 -F 0 "X1" H 6000 5250 60 0000 C CNN -F 1 "4_OR" H 6050 5350 60 0000 C CNN -F 2 "" H 5900 5250 60 0000 C CNN -F 3 "" H 5900 5250 60 0000 C CNN - 1 5900 5250 +P 2150 8400 +F 0 "X1" H 6050 11450 60 0000 C CNN +F 1 "4_OR" H 6050 11650 60 0000 C CNN +F 2 "" H 2150 8400 60 0000 C CNN +F 3 "" H 2150 8400 60 0000 C CNN + 1 2150 8400 1 0 0 -1 $EndComp Wire Wire Line @@ -525,12 +541,12 @@ Wire Wire Line $Comp L 4_OR X2 U 1 1 5C9D28DE -P 6000 2600 -F 0 "X2" H 6100 2600 60 0000 C CNN -F 1 "4_OR" H 6150 2700 60 0000 C CNN -F 2 "" H 6000 2600 60 0000 C CNN -F 3 "" H 6000 2600 60 0000 C CNN - 1 6000 2600 +P 2250 5750 +F 0 "X2" H 6150 8800 60 0000 C CNN +F 1 "4_OR" H 6150 9000 60 0000 C CNN +F 2 "" H 2250 5750 60 0000 C CNN +F 3 "" H 2250 5750 60 0000 C CNN + 1 2250 5750 1 0 0 -1 $EndComp Wire Wire Line @@ -549,28 +565,4 @@ Wire Wire Line 4700 3600 4700 2750 Wire Wire Line 4700 2750 5650 2750 -$Comp -L PORT U1 -U 16 1 5D11F8AE -P 7450 1200 -F 0 "U1" H 7500 1300 30 0000 C CNN -F 1 "PORT" H 7450 1200 30 0000 C CNN -F 2 "" H 7450 1200 60 0000 C CNN -F 3 "" H 7450 1200 60 0000 C CNN - 16 7450 1200 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 8 1 5D11F97A -P 7400 1550 -F 0 "U1" H 7450 1650 30 0000 C CNN -F 1 "PORT" H 7400 1550 30 0000 C CNN -F 2 "" H 7400 1550 60 0000 C CNN -F 3 "" H 7400 1550 60 0000 C CNN - 8 7400 1550 - -1 0 0 1 -$EndComp -NoConn ~ 7200 1200 -NoConn ~ 7150 1550 $EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/74153.sub b/src/SubcircuitLibrary/74153/74153.sub index 0bbdea00..6e00261f 100644 --- a/src/SubcircuitLibrary/74153/74153.sub +++ b/src/SubcircuitLibrary/74153/74153.sub @@ -1,26 +1,26 @@ * Subcircuit 74153 -.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74153/74153.cir +.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir .include 4_and.sub .include 4_OR.sub -* u2 net-_u1-pad14_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u35 net-_u1-pad1_ net-_u35-pad2_ d_inverter -* u34 net-_u1-pad15_ net-_u34-pad2_ d_inverter -x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u35-pad2_ net-_x2-pad1_ 4_and -x9 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad5_ net-_u35-pad2_ net-_x2-pad2_ 4_and -x4 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u35-pad2_ net-_x2-pad3_ 4_and -x10 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u35-pad2_ net-_x10-pad5_ 4_and -x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad10_ net-_u34-pad2_ net-_x1-pad1_ 4_and -x6 net-_u1-pad14_ net-_u3-pad2_ net-_u1-pad11_ net-_u34-pad2_ net-_x1-pad2_ 4_and -x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad12_ net-_u34-pad2_ net-_x1-pad3_ 4_and -x7 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad13_ net-_u34-pad2_ net-_x1-pad4_ 4_and -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad9_ 4_OR -x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad7_ 4_OR -a1 net-_u1-pad14_ net-_u2-pad2_ u2 -a2 net-_u1-pad2_ net-_u3-pad2_ u3 -a3 net-_u1-pad1_ net-_u35-pad2_ u35 -a4 net-_u1-pad15_ net-_u34-pad2_ u34 +* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter +* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter +x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and +x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and +x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and +x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and +x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and +x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and +x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR +x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR +a1 net-_u1-pad12_ net-_u2-pad2_ u2 +a2 net-_u1-pad11_ net-_u3-pad2_ u3 +a3 net-_u1-pad5_ net-_u35-pad2_ u35 +a4 net-_u1-pad10_ net-_u34-pad2_ u34 * Schematic Name: d_inverter, NgSpice Name: d_inverter .model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_inverter, NgSpice Name: d_inverter diff --git a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml index 028f2d75..ea70e6f3 100644 --- a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml +++ b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_OR</field></x2><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x9><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x10><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_OR</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib index 32c8b38f..10496d63 100644 --- a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib @@ -1,94 +1,94 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir index 5dddad23..583c4a00 100644 --- a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir @@ -1,45 +1,45 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and
-U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and
-U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and
-U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and
-U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and
-U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and
-U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and
-U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and
-U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or
-U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or
-U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or
-U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter
-U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter
-U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and
-U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and
-U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and
-U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and
-U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and
-U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and
-U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and
-U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and
-U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and
-U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and
-U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and
-U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and
-U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or
-U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or
-U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or
-U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and
-U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
-U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and
-U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
-U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter
-U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and +U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and +U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or +U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or +U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or +U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and +U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and +U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and +U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and +U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and +U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and +U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and +U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or +U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and +U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter +U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter + +.end diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch index bb19bb7d..340b1a31 100644 --- a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch +++ b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch @@ -1,814 +1,814 @@ -EESchema Schematic File Version 2
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-LIBS:device
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:74153-cache
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-F 0 "U3" H 2700 850 60 0000 C CNN
-F 1 "d_inverter" H 2700 1100 60 0000 C CNN
-F 2 "" H 2750 900 60 0000 C CNN
-F 3 "" H 2750 900 60 0000 C CNN
- 1 2700 950
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3500 1800 3100 1800
-Wire Wire Line
- 3100 1350 3100 5600
-Wire Wire Line
- 3500 1900 3200 1900
-Wire Wire Line
- 3200 950 3200 5100
-Wire Wire Line
- 2950 1350 3100 1350
-Connection ~ 3100 1800
-Wire Wire Line
- 3000 950 3200 950
-Connection ~ 3200 1900
-Wire Wire Line
- 1800 950 2400 950
-Wire Wire Line
- 1800 1350 2350 1350
-Wire Wire Line
- 2200 950 2200 6200
-Connection ~ 2200 950
-Wire Wire Line
- 2300 1350 2300 6100
-$Comp
-L d_and U15
-U 1 1 5C937C96
-P 3850 2700
-F 0 "U15" H 3850 2700 60 0000 C CNN
-F 1 "d_and" H 3900 2800 60 0000 C CNN
-F 2 "" H 3850 2700 60 0000 C CNN
-F 3 "" H 3850 2700 60 0000 C CNN
- 1 3850 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U6
-U 1 1 5C937CEE
-P 3800 3300
-F 0 "U6" H 3800 3300 60 0000 C CNN
-F 1 "d_and" H 3850 3400 60 0000 C CNN
-F 2 "" H 3800 3300 60 0000 C CNN
-F 3 "" H 3800 3300 60 0000 C CNN
- 1 3800 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U8
-U 1 1 5C937D35
-P 3800 3800
-F 0 "U8" H 3800 3800 60 0000 C CNN
-F 1 "d_and" H 3850 3900 60 0000 C CNN
-F 2 "" H 3800 3800 60 0000 C CNN
-F 3 "" H 3800 3800 60 0000 C CNN
- 1 3800 3800
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5C937DC5
-P 3800 2150
-F 0 "U4" H 3800 2150 60 0000 C CNN
-F 1 "d_and" H 3850 2250 60 0000 C CNN
-F 2 "" H 3800 2150 60 0000 C CNN
-F 3 "" H 3800 2150 60 0000 C CNN
- 1 3800 2150
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3350 2150 3300 2150
-Wire Wire Line
- 3300 2150 3300 3800
-Wire Wire Line
- 3300 2700 3400 2700
-Wire Wire Line
- 3300 3300 3350 3300
-Connection ~ 3300 2700
-Wire Wire Line
- 3000 3800 3350 3800
-Connection ~ 3300 3300
-Wire Wire Line
- 4350 3200 4350 3250
-Wire Wire Line
- 4350 3250 4250 3250
-Wire Wire Line
- 4400 2600 4400 2650
-Wire Wire Line
- 4400 2650 4300 2650
-Wire Wire Line
- 4400 2150 4300 2150
-Wire Wire Line
- 4300 2150 4300 2100
-Wire Wire Line
- 4300 2100 4250 2100
-Wire Wire Line
- 4350 3700 4250 3700
-Wire Wire Line
- 4250 3700 4250 3750
-Wire Wire Line
- 3350 3700 1600 3700
-Wire Wire Line
- 3350 3200 1600 3200
-Wire Wire Line
- 3400 2600 1600 2600
-Wire Wire Line
- 3350 2050 1600 2050
-Wire Wire Line
- 3000 3950 3000 3800
-Wire Wire Line
- 2950 3950 3000 3950
-Wire Wire Line
- 1600 3950 2350 3950
-Connection ~ 3300 3800
-$Comp
-L d_and U16
-U 1 1 5C9388D0
-P 3850 5100
-F 0 "U16" H 3850 5100 60 0000 C CNN
-F 1 "d_and" H 3900 5200 60 0000 C CNN
-F 2 "" H 3850 5100 60 0000 C CNN
-F 3 "" H 3850 5100 60 0000 C CNN
- 1 3850 5100
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U27
-U 1 1 5C9388D6
-P 4850 5250
-F 0 "U27" H 4850 5250 60 0000 C CNN
-F 1 "d_and" H 4900 5350 60 0000 C CNN
-F 2 "" H 4850 5250 60 0000 C CNN
-F 3 "" H 4850 5250 60 0000 C CNN
- 1 4850 5250
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U10
-U 1 1 5C9388DC
-P 3800 5700
-F 0 "U10" H 3800 5700 60 0000 C CNN
-F 1 "d_and" H 3850 5800 60 0000 C CNN
-F 2 "" H 3800 5700 60 0000 C CNN
-F 3 "" H 3800 5700 60 0000 C CNN
- 1 3800 5700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U22
-U 1 1 5C9388E2
-P 4800 5850
-F 0 "U22" H 4800 5850 60 0000 C CNN
-F 1 "d_and" H 4850 5950 60 0000 C CNN
-F 2 "" H 4800 5850 60 0000 C CNN
-F 3 "" H 4800 5850 60 0000 C CNN
- 1 4800 5850
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U12
-U 1 1 5C9388E8
-P 3800 6200
-F 0 "U12" H 3800 6200 60 0000 C CNN
-F 1 "d_and" H 3850 6300 60 0000 C CNN
-F 2 "" H 3800 6200 60 0000 C CNN
-F 3 "" H 3800 6200 60 0000 C CNN
- 1 3800 6200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U23
-U 1 1 5C9388EE
-P 4800 6350
-F 0 "U23" H 4800 6350 60 0000 C CNN
-F 1 "d_and" H 4850 6450 60 0000 C CNN
-F 2 "" H 4800 6350 60 0000 C CNN
-F 3 "" H 4800 6350 60 0000 C CNN
- 1 4800 6350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U19
-U 1 1 5C9388F4
-P 3950 4550
-F 0 "U19" H 3950 4550 60 0000 C CNN
-F 1 "d_and" H 4000 4650 60 0000 C CNN
-F 2 "" H 3950 4550 60 0000 C CNN
-F 3 "" H 3950 4550 60 0000 C CNN
- 1 3950 4550
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U26
-U 1 1 5C9388FA
-P 4850 4800
-F 0 "U26" H 4850 4800 60 0000 C CNN
-F 1 "d_and" H 4900 4900 60 0000 C CNN
-F 2 "" H 4850 4800 60 0000 C CNN
-F 3 "" H 4850 4800 60 0000 C CNN
- 1 4850 4800
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U30
-U 1 1 5C938900
-P 5900 5200
-F 0 "U30" H 5900 5200 60 0000 C CNN
-F 1 "d_or" H 5900 5300 60 0000 C CNN
-F 2 "" H 5900 5200 60 0000 C CNN
-F 3 "" H 5900 5200 60 0000 C CNN
- 1 5900 5200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U31
-U 1 1 5C938906
-P 5900 5450
-F 0 "U31" H 5900 5450 60 0000 C CNN
-F 1 "d_or" H 5900 5550 60 0000 C CNN
-F 2 "" H 5900 5450 60 0000 C CNN
-F 3 "" H 5900 5450 60 0000 C CNN
- 1 5900 5450
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U33
-U 1 1 5C93890C
-P 6850 5300
-F 0 "U33" H 6850 5300 60 0000 C CNN
-F 1 "d_or" H 6850 5400 60 0000 C CNN
-F 2 "" H 6850 5300 60 0000 C CNN
-F 3 "" H 6850 5300 60 0000 C CNN
- 1 6850 5300
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4400 4500 4400 4700
-Wire Wire Line
- 4400 5150 4400 5050
-Wire Wire Line
- 4400 5050 4300 5050
-Wire Wire Line
- 4350 5750 4350 5650
-Wire Wire Line
- 4350 5650 4250 5650
-Wire Wire Line
- 4350 6250 4350 6150
-Wire Wire Line
- 4350 6150 4250 6150
-Wire Wire Line
- 6400 5200 6400 5150
-Wire Wire Line
- 6400 5150 6350 5150
-Wire Wire Line
- 6400 5300 6400 5400
-Wire Wire Line
- 6400 5400 6350 5400
-Wire Wire Line
- 5450 5100 5350 5100
-Wire Wire Line
- 5350 5100 5350 4750
-Wire Wire Line
- 5350 4750 5300 4750
-Wire Wire Line
- 5300 5200 5450 5200
-Wire Wire Line
- 5450 5350 5300 5350
-Wire Wire Line
- 5300 5350 5300 5800
-Wire Wire Line
- 5300 5800 5250 5800
-Wire Wire Line
- 5250 6300 5400 6300
-Wire Wire Line
- 5400 6300 5400 5450
-Wire Wire Line
- 5400 5450 5450 5450
-Wire Wire Line
- 3100 4450 3500 4450
-Wire Wire Line
- 3200 4550 3500 4550
-$Comp
-L d_and U17
-U 1 1 5C938937
-P 3850 5350
-F 0 "U17" H 3850 5350 60 0000 C CNN
-F 1 "d_and" H 3900 5450 60 0000 C CNN
-F 2 "" H 3850 5350 60 0000 C CNN
-F 3 "" H 3850 5350 60 0000 C CNN
- 1 3850 5350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U11
-U 1 1 5C93893D
-P 3800 5950
-F 0 "U11" H 3800 5950 60 0000 C CNN
-F 1 "d_and" H 3850 6050 60 0000 C CNN
-F 2 "" H 3800 5950 60 0000 C CNN
-F 3 "" H 3800 5950 60 0000 C CNN
- 1 3800 5950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U13
-U 1 1 5C938943
-P 3800 6450
-F 0 "U13" H 3800 6450 60 0000 C CNN
-F 1 "d_and" H 3850 6550 60 0000 C CNN
-F 2 "" H 3800 6450 60 0000 C CNN
-F 3 "" H 3800 6450 60 0000 C CNN
- 1 3800 6450
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U9
-U 1 1 5C938949
-P 3800 4800
-F 0 "U9" H 3800 4800 60 0000 C CNN
-F 1 "d_and" H 3850 4900 60 0000 C CNN
-F 2 "" H 3800 4800 60 0000 C CNN
-F 3 "" H 3800 4800 60 0000 C CNN
- 1 3800 4800
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3350 4800 3300 4800
-Wire Wire Line
- 3300 4800 3300 6450
-Wire Wire Line
- 3300 5350 3400 5350
-Wire Wire Line
- 3300 5950 3350 5950
-Connection ~ 3300 5350
-Wire Wire Line
- 3200 6450 3350 6450
-Connection ~ 3300 5950
-Wire Wire Line
- 4350 5850 4350 5900
-Wire Wire Line
- 4350 5900 4250 5900
-Wire Wire Line
- 4400 5250 4400 5300
-Wire Wire Line
- 4400 5300 4300 5300
-Wire Wire Line
- 4400 4800 4300 4800
-Wire Wire Line
- 4300 4800 4300 4750
-Wire Wire Line
- 4300 4750 4250 4750
-Wire Wire Line
- 4350 6350 4250 6350
-Wire Wire Line
- 4250 6350 4250 6400
-Wire Wire Line
- 3350 6350 1600 6350
-Wire Wire Line
- 3350 5850 1600 5850
-Wire Wire Line
- 3400 5250 1600 5250
-Wire Wire Line
- 3350 4700 1600 4700
-Wire Wire Line
- 3200 6600 3200 6450
-Wire Wire Line
- 3000 6600 3200 6600
-Wire Wire Line
- 1600 6600 2400 6600
-Connection ~ 3300 6450
-Connection ~ 2300 1350
-Connection ~ 3100 4450
-Connection ~ 3200 4550
-$Comp
-L PORT U1
-U 1 1 5C93A0F9
-P 1350 2050
-F 0 "U1" H 1400 2150 30 0000 C CNN
-F 1 "PORT" H 1350 2050 30 0000 C CNN
-F 2 "" H 1350 2050 60 0000 C CNN
-F 3 "" H 1350 2050 60 0000 C CNN
- 1 1350 2050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C93A174
-P 1350 4700
-F 0 "U1" H 1400 4800 30 0000 C CNN
-F 1 "PORT" H 1350 4700 30 0000 C CNN
-F 2 "" H 1350 4700 60 0000 C CNN
-F 3 "" H 1350 4700 60 0000 C CNN
- 6 1350 4700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C93AA3C
-P 1350 2600
-F 0 "U1" H 1400 2700 30 0000 C CNN
-F 1 "PORT" H 1350 2600 30 0000 C CNN
-F 2 "" H 1350 2600 60 0000 C CNN
-F 3 "" H 1350 2600 60 0000 C CNN
- 2 1350 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C93AACB
-P 1350 3200
-F 0 "U1" H 1400 3300 30 0000 C CNN
-F 1 "PORT" H 1350 3200 30 0000 C CNN
-F 2 "" H 1350 3200 60 0000 C CNN
-F 3 "" H 1350 3200 60 0000 C CNN
- 3 1350 3200
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C93AB5F
-P 1350 3700
-F 0 "U1" H 1400 3800 30 0000 C CNN
-F 1 "PORT" H 1350 3700 30 0000 C CNN
-F 2 "" H 1350 3700 60 0000 C CNN
-F 3 "" H 1350 3700 60 0000 C CNN
- 4 1350 3700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C93AD97
-P 1350 5250
-F 0 "U1" H 1400 5350 30 0000 C CNN
-F 1 "PORT" H 1350 5250 30 0000 C CNN
-F 2 "" H 1350 5250 60 0000 C CNN
-F 3 "" H 1350 5250 60 0000 C CNN
- 7 1350 5250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C93ADFC
-P 1350 5850
-F 0 "U1" H 1400 5950 30 0000 C CNN
-F 1 "PORT" H 1350 5850 30 0000 C CNN
-F 2 "" H 1350 5850 60 0000 C CNN
-F 3 "" H 1350 5850 60 0000 C CNN
- 8 1350 5850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C93AE63
-P 1350 6350
-F 0 "U1" H 1400 6450 30 0000 C CNN
-F 1 "PORT" H 1350 6350 30 0000 C CNN
-F 2 "" H 1350 6350 60 0000 C CNN
-F 3 "" H 1350 6350 60 0000 C CNN
- 9 1350 6350
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C93AECA
-P 1350 3950
-F 0 "U1" H 1400 4050 30 0000 C CNN
-F 1 "PORT" H 1350 3950 30 0000 C CNN
-F 2 "" H 1350 3950 60 0000 C CNN
-F 3 "" H 1350 3950 60 0000 C CNN
- 5 1350 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C93AF79
-P 1350 6600
-F 0 "U1" H 1400 6700 30 0000 C CNN
-F 1 "PORT" H 1350 6600 30 0000 C CNN
-F 2 "" H 1350 6600 60 0000 C CNN
-F 3 "" H 1350 6600 60 0000 C CNN
- 10 1350 6600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C93B10A
-P 1550 950
-F 0 "U1" H 1600 1050 30 0000 C CNN
-F 1 "PORT" H 1550 950 30 0000 C CNN
-F 2 "" H 1550 950 60 0000 C CNN
-F 3 "" H 1550 950 60 0000 C CNN
- 11 1550 950
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5C93B179
-P 1550 1350
-F 0 "U1" H 1600 1450 30 0000 C CNN
-F 1 "PORT" H 1550 1350 30 0000 C CNN
-F 2 "" H 1550 1350 60 0000 C CNN
-F 3 "" H 1550 1350 60 0000 C CNN
- 12 1550 1350
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7300 2600 7600 2600
-Wire Wire Line
- 7300 5250 7650 5250
-$Comp
-L PORT U1
-U 13 1 5C93B567
-P 7850 2600
-F 0 "U1" H 7900 2700 30 0000 C CNN
-F 1 "PORT" H 7850 2600 30 0000 C CNN
-F 2 "" H 7850 2600 60 0000 C CNN
-F 3 "" H 7850 2600 60 0000 C CNN
- 13 7850 2600
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C93B5DA
-P 7900 5250
-F 0 "U1" H 7950 5350 30 0000 C CNN
-F 1 "PORT" H 7900 5250 30 0000 C CNN
-F 2 "" H 7900 5250 60 0000 C CNN
-F 3 "" H 7900 5250 60 0000 C CNN
- 14 7900 5250
- -1 0 0 1
-$EndComp
-Connection ~ 2200 3450
-Wire Wire Line
- 3200 5100 3400 5100
-Wire Wire Line
- 3400 5000 2300 5000
-Connection ~ 2300 5000
-Wire Wire Line
- 3100 5600 3350 5600
-Wire Wire Line
- 2200 5700 3350 5700
-Wire Wire Line
- 2200 6200 3350 6200
-Connection ~ 2200 5700
-Wire Wire Line
- 2300 6100 3350 6100
-Wire Wire Line
- 3400 2450 3200 2450
-Connection ~ 3200 2450
-Wire Wire Line
- 3400 2350 2300 2350
-Connection ~ 2300 2350
-Wire Wire Line
- 3350 3050 2200 3050
-Connection ~ 2200 3050
-Wire Wire Line
- 3350 2950 3100 2950
-Connection ~ 3100 2950
-Wire Wire Line
- 3350 3450 2300 3450
-Wire Wire Line
- 2300 3450 2300 3400
-Connection ~ 2300 3400
-Wire Wire Line
- 3350 3550 2200 3550
-Connection ~ 2200 3550
-$Comp
-L d_inverter U34
-U 1 1 5C95C9D0
-P 2650 3950
-F 0 "U34" H 2650 3850 60 0000 C CNN
-F 1 "d_inverter" H 2650 4100 60 0000 C CNN
-F 2 "" H 2700 3900 60 0000 C CNN
-F 3 "" H 2700 3900 60 0000 C CNN
- 1 2650 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U35
-U 1 1 5C95CD17
-P 2700 6600
-F 0 "U35" H 2700 6500 60 0000 C CNN
-F 1 "d_inverter" H 2700 6750 60 0000 C CNN
-F 2 "" H 2750 6550 60 0000 C CNN
-F 3 "" H 2750 6550 60 0000 C CNN
- 1 2700 6600
- 1 0 0 -1
-$EndComp
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:74153-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U14 +U 1 1 5C936BFE +P 3850 2450 +F 0 "U14" H 3850 2450 60 0000 C CNN +F 1 "d_and" H 3900 2550 60 0000 C CNN +F 2 "" H 3850 2450 60 0000 C CNN +F 3 "" H 3850 2450 60 0000 C CNN + 1 3850 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 5C936C8A +P 4850 2600 +F 0 "U25" H 4850 2600 60 0000 C CNN +F 1 "d_and" H 4900 2700 60 0000 C CNN +F 2 "" H 4850 2600 60 0000 C CNN +F 3 "" H 4850 2600 60 0000 C CNN + 1 4850 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 5C936E84 +P 3800 3050 +F 0 "U5" H 3800 3050 60 0000 C CNN +F 1 "d_and" H 3850 3150 60 0000 C CNN +F 2 "" H 3800 3050 60 0000 C CNN +F 3 "" H 3800 3050 60 0000 C CNN + 1 3800 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 5C936E8A +P 4800 3200 +F 0 "U20" H 4800 3200 60 0000 C CNN +F 1 "d_and" H 4850 3300 60 0000 C CNN +F 2 "" H 4800 3200 60 0000 C CNN +F 3 "" H 4800 3200 60 0000 C CNN + 1 4800 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C936EF6 +P 3800 3550 +F 0 "U7" H 3800 3550 60 0000 C CNN +F 1 "d_and" H 3850 3650 60 0000 C CNN +F 2 "" H 3800 3550 60 0000 C CNN +F 3 "" H 3800 3550 60 0000 C CNN + 1 3800 3550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 5C936EFC +P 4800 3700 +F 0 "U21" H 4800 3700 60 0000 C CNN +F 1 "d_and" H 4850 3800 60 0000 C CNN +F 2 "" H 4800 3700 60 0000 C CNN +F 3 "" H 4800 3700 60 0000 C CNN + 1 4800 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C936F88 +P 3950 1900 +F 0 "U18" H 3950 1900 60 0000 C CNN +F 1 "d_and" H 4000 2000 60 0000 C CNN +F 2 "" H 3950 1900 60 0000 C CNN +F 3 "" H 3950 1900 60 0000 C CNN + 1 3950 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 5C936F8E +P 4850 2150 +F 0 "U24" H 4850 2150 60 0000 C CNN +F 1 "d_and" H 4900 2250 60 0000 C CNN +F 2 "" H 4850 2150 60 0000 C CNN +F 3 "" H 4850 2150 60 0000 C CNN + 1 4850 2150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 5C937316 +P 5900 2550 +F 0 "U28" H 5900 2550 60 0000 C CNN +F 1 "d_or" H 5900 2650 60 0000 C CNN +F 2 "" H 5900 2550 60 0000 C CNN +F 3 "" H 5900 2550 60 0000 C CNN + 1 5900 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_or U29 +U 1 1 5C9373A8 +P 5900 2800 +F 0 "U29" H 5900 2800 60 0000 C CNN +F 1 "d_or" H 5900 2900 60 0000 C CNN +F 2 "" H 5900 2800 60 0000 C CNN +F 3 "" H 5900 2800 60 0000 C CNN + 1 5900 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 5C9373FC +P 6850 2650 +F 0 "U32" H 6850 2650 60 0000 C CNN +F 1 "d_or" H 6850 2750 60 0000 C CNN +F 2 "" H 6850 2650 60 0000 C CNN +F 3 "" H 6850 2650 60 0000 C CNN + 1 6850 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 1850 4400 2050 +Wire Wire Line + 4400 2500 4400 2400 +Wire Wire Line + 4400 2400 4300 2400 +Wire Wire Line + 4350 3100 4350 3000 +Wire Wire Line + 4350 3000 4250 3000 +Wire Wire Line + 4350 3600 4350 3500 +Wire Wire Line + 4350 3500 4250 3500 +Wire Wire Line + 6400 2550 6400 2500 +Wire Wire Line + 6400 2500 6350 2500 +Wire Wire Line + 6400 2650 6400 2750 +Wire Wire Line + 6400 2750 6350 2750 +Wire Wire Line + 5450 2450 5350 2450 +Wire Wire Line + 5350 2450 5350 2100 +Wire Wire Line + 5350 2100 5300 2100 +Wire Wire Line + 5300 2550 5450 2550 +Wire Wire Line + 5450 2700 5300 2700 +Wire Wire Line + 5300 2700 5300 3150 +Wire Wire Line + 5300 3150 5250 3150 +Wire Wire Line + 5250 3650 5400 3650 +Wire Wire Line + 5400 3650 5400 2800 +Wire Wire Line + 5400 2800 5450 2800 +$Comp +L d_inverter U2 +U 1 1 5C9378F6 +P 2650 1350 +F 0 "U2" H 2650 1250 60 0000 C CNN +F 1 "d_inverter" H 2650 1500 60 0000 C CNN +F 2 "" H 2700 1300 60 0000 C CNN +F 3 "" H 2700 1300 60 0000 C CNN + 1 2650 1350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C93798D +P 2700 950 +F 0 "U3" H 2700 850 60 0000 C CNN +F 1 "d_inverter" H 2700 1100 60 0000 C CNN +F 2 "" H 2750 900 60 0000 C CNN +F 3 "" H 2750 900 60 0000 C CNN + 1 2700 950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 1800 3100 1800 +Wire Wire Line + 3100 1350 3100 5600 +Wire Wire Line + 3500 1900 3200 1900 +Wire Wire Line + 3200 950 3200 5100 +Wire Wire Line + 2950 1350 3100 1350 +Connection ~ 3100 1800 +Wire Wire Line + 3000 950 3200 950 +Connection ~ 3200 1900 +Wire Wire Line + 1800 950 2400 950 +Wire Wire Line + 1800 1350 2350 1350 +Wire Wire Line + 2200 950 2200 6200 +Connection ~ 2200 950 +Wire Wire Line + 2300 1350 2300 6100 +$Comp +L d_and U15 +U 1 1 5C937C96 +P 3850 2700 +F 0 "U15" H 3850 2700 60 0000 C CNN +F 1 "d_and" H 3900 2800 60 0000 C CNN +F 2 "" H 3850 2700 60 0000 C CNN +F 3 "" H 3850 2700 60 0000 C CNN + 1 3850 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 5C937CEE +P 3800 3300 +F 0 "U6" H 3800 3300 60 0000 C CNN +F 1 "d_and" H 3850 3400 60 0000 C CNN +F 2 "" H 3800 3300 60 0000 C CNN +F 3 "" H 3800 3300 60 0000 C CNN + 1 3800 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C937D35 +P 3800 3800 +F 0 "U8" H 3800 3800 60 0000 C CNN +F 1 "d_and" H 3850 3900 60 0000 C CNN +F 2 "" H 3800 3800 60 0000 C CNN +F 3 "" H 3800 3800 60 0000 C CNN + 1 3800 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 5C937DC5 +P 3800 2150 +F 0 "U4" H 3800 2150 60 0000 C CNN +F 1 "d_and" H 3850 2250 60 0000 C CNN +F 2 "" H 3800 2150 60 0000 C CNN +F 3 "" H 3800 2150 60 0000 C CNN + 1 3800 2150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 2150 3300 2150 +Wire Wire Line + 3300 2150 3300 3800 +Wire Wire Line + 3300 2700 3400 2700 +Wire Wire Line + 3300 3300 3350 3300 +Connection ~ 3300 2700 +Wire Wire Line + 3000 3800 3350 3800 +Connection ~ 3300 3300 +Wire Wire Line + 4350 3200 4350 3250 +Wire Wire Line + 4350 3250 4250 3250 +Wire Wire Line + 4400 2600 4400 2650 +Wire Wire Line + 4400 2650 4300 2650 +Wire Wire Line + 4400 2150 4300 2150 +Wire Wire Line + 4300 2150 4300 2100 +Wire Wire Line + 4300 2100 4250 2100 +Wire Wire Line + 4350 3700 4250 3700 +Wire Wire Line + 4250 3700 4250 3750 +Wire Wire Line + 3350 3700 1600 3700 +Wire Wire Line + 3350 3200 1600 3200 +Wire Wire Line + 3400 2600 1600 2600 +Wire Wire Line + 3350 2050 1600 2050 +Wire Wire Line + 3000 3950 3000 3800 +Wire Wire Line + 2950 3950 3000 3950 +Wire Wire Line + 1600 3950 2350 3950 +Connection ~ 3300 3800 +$Comp +L d_and U16 +U 1 1 5C9388D0 +P 3850 5100 +F 0 "U16" H 3850 5100 60 0000 C CNN +F 1 "d_and" H 3900 5200 60 0000 C CNN +F 2 "" H 3850 5100 60 0000 C CNN +F 3 "" H 3850 5100 60 0000 C CNN + 1 3850 5100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 5C9388D6 +P 4850 5250 +F 0 "U27" H 4850 5250 60 0000 C CNN +F 1 "d_and" H 4900 5350 60 0000 C CNN +F 2 "" H 4850 5250 60 0000 C CNN +F 3 "" H 4850 5250 60 0000 C CNN + 1 4850 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9388DC +P 3800 5700 +F 0 "U10" H 3800 5700 60 0000 C CNN +F 1 "d_and" H 3850 5800 60 0000 C CNN +F 2 "" H 3800 5700 60 0000 C CNN +F 3 "" H 3800 5700 60 0000 C CNN + 1 3800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 5C9388E2 +P 4800 5850 +F 0 "U22" H 4800 5850 60 0000 C CNN +F 1 "d_and" H 4850 5950 60 0000 C CNN +F 2 "" H 4800 5850 60 0000 C CNN +F 3 "" H 4800 5850 60 0000 C CNN + 1 4800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 5C9388E8 +P 3800 6200 +F 0 "U12" H 3800 6200 60 0000 C CNN +F 1 "d_and" H 3850 6300 60 0000 C CNN +F 2 "" H 3800 6200 60 0000 C CNN +F 3 "" H 3800 6200 60 0000 C CNN + 1 3800 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 5C9388EE +P 4800 6350 +F 0 "U23" H 4800 6350 60 0000 C CNN +F 1 "d_and" H 4850 6450 60 0000 C CNN +F 2 "" H 4800 6350 60 0000 C CNN +F 3 "" H 4800 6350 60 0000 C CNN + 1 4800 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9388F4 +P 3950 4550 +F 0 "U19" H 3950 4550 60 0000 C CNN +F 1 "d_and" H 4000 4650 60 0000 C CNN +F 2 "" H 3950 4550 60 0000 C CNN +F 3 "" H 3950 4550 60 0000 C CNN + 1 3950 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 5C9388FA +P 4850 4800 +F 0 "U26" H 4850 4800 60 0000 C CNN +F 1 "d_and" H 4900 4900 60 0000 C CNN +F 2 "" H 4850 4800 60 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4850 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U30 +U 1 1 5C938900 +P 5900 5200 +F 0 "U30" H 5900 5200 60 0000 C CNN +F 1 "d_or" H 5900 5300 60 0000 C CNN +F 2 "" H 5900 5200 60 0000 C CNN +F 3 "" H 5900 5200 60 0000 C CNN + 1 5900 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U31 +U 1 1 5C938906 +P 5900 5450 +F 0 "U31" H 5900 5450 60 0000 C CNN +F 1 "d_or" H 5900 5550 60 0000 C CNN +F 2 "" H 5900 5450 60 0000 C CNN +F 3 "" H 5900 5450 60 0000 C CNN + 1 5900 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 5C93890C +P 6850 5300 +F 0 "U33" H 6850 5300 60 0000 C CNN +F 1 "d_or" H 6850 5400 60 0000 C CNN +F 2 "" H 6850 5300 60 0000 C CNN +F 3 "" H 6850 5300 60 0000 C CNN + 1 6850 5300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4400 4500 4400 4700 +Wire Wire Line + 4400 5150 4400 5050 +Wire Wire Line + 4400 5050 4300 5050 +Wire Wire Line + 4350 5750 4350 5650 +Wire Wire Line + 4350 5650 4250 5650 +Wire Wire Line + 4350 6250 4350 6150 +Wire Wire Line + 4350 6150 4250 6150 +Wire Wire Line + 6400 5200 6400 5150 +Wire Wire Line + 6400 5150 6350 5150 +Wire Wire Line + 6400 5300 6400 5400 +Wire Wire Line + 6400 5400 6350 5400 +Wire Wire Line + 5450 5100 5350 5100 +Wire Wire Line + 5350 5100 5350 4750 +Wire Wire Line + 5350 4750 5300 4750 +Wire Wire Line + 5300 5200 5450 5200 +Wire Wire Line + 5450 5350 5300 5350 +Wire Wire Line + 5300 5350 5300 5800 +Wire Wire Line + 5300 5800 5250 5800 +Wire Wire Line + 5250 6300 5400 6300 +Wire Wire Line + 5400 6300 5400 5450 +Wire Wire Line + 5400 5450 5450 5450 +Wire Wire Line + 3100 4450 3500 4450 +Wire Wire Line + 3200 4550 3500 4550 +$Comp +L d_and U17 +U 1 1 5C938937 +P 3850 5350 +F 0 "U17" H 3850 5350 60 0000 C CNN +F 1 "d_and" H 3900 5450 60 0000 C CNN +F 2 "" H 3850 5350 60 0000 C CNN +F 3 "" H 3850 5350 60 0000 C CNN + 1 3850 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 5C93893D +P 3800 5950 +F 0 "U11" H 3800 5950 60 0000 C CNN +F 1 "d_and" H 3850 6050 60 0000 C CNN +F 2 "" H 3800 5950 60 0000 C CNN +F 3 "" H 3800 5950 60 0000 C CNN + 1 3800 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5C938943 +P 3800 6450 +F 0 "U13" H 3800 6450 60 0000 C CNN +F 1 "d_and" H 3850 6550 60 0000 C CNN +F 2 "" H 3800 6450 60 0000 C CNN +F 3 "" H 3800 6450 60 0000 C CNN + 1 3800 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C938949 +P 3800 4800 +F 0 "U9" H 3800 4800 60 0000 C CNN +F 1 "d_and" H 3850 4900 60 0000 C CNN +F 2 "" H 3800 4800 60 0000 C CNN +F 3 "" H 3800 4800 60 0000 C CNN + 1 3800 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 4800 3300 4800 +Wire Wire Line + 3300 4800 3300 6450 +Wire Wire Line + 3300 5350 3400 5350 +Wire Wire Line + 3300 5950 3350 5950 +Connection ~ 3300 5350 +Wire Wire Line + 3200 6450 3350 6450 +Connection ~ 3300 5950 +Wire Wire Line + 4350 5850 4350 5900 +Wire Wire Line + 4350 5900 4250 5900 +Wire Wire Line + 4400 5250 4400 5300 +Wire Wire Line + 4400 5300 4300 5300 +Wire Wire Line + 4400 4800 4300 4800 +Wire Wire Line + 4300 4800 4300 4750 +Wire Wire Line + 4300 4750 4250 4750 +Wire Wire Line + 4350 6350 4250 6350 +Wire Wire Line + 4250 6350 4250 6400 +Wire Wire Line + 3350 6350 1600 6350 +Wire Wire Line + 3350 5850 1600 5850 +Wire Wire Line + 3400 5250 1600 5250 +Wire Wire Line + 3350 4700 1600 4700 +Wire Wire Line + 3200 6600 3200 6450 +Wire Wire Line + 3000 6600 3200 6600 +Wire Wire Line + 1600 6600 2400 6600 +Connection ~ 3300 6450 +Connection ~ 2300 1350 +Connection ~ 3100 4450 +Connection ~ 3200 4550 +$Comp +L PORT U1 +U 1 1 5C93A0F9 +P 1350 2050 +F 0 "U1" H 1400 2150 30 0000 C CNN +F 1 "PORT" H 1350 2050 30 0000 C CNN +F 2 "" H 1350 2050 60 0000 C CNN +F 3 "" H 1350 2050 60 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C93A174 +P 1350 4700 +F 0 "U1" H 1400 4800 30 0000 C CNN +F 1 "PORT" H 1350 4700 30 0000 C CNN +F 2 "" H 1350 4700 60 0000 C CNN +F 3 "" H 1350 4700 60 0000 C CNN + 6 1350 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C93AA3C +P 1350 2600 +F 0 "U1" H 1400 2700 30 0000 C CNN +F 1 "PORT" H 1350 2600 30 0000 C CNN +F 2 "" H 1350 2600 60 0000 C CNN +F 3 "" H 1350 2600 60 0000 C CNN + 2 1350 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C93AACB +P 1350 3200 +F 0 "U1" H 1400 3300 30 0000 C CNN +F 1 "PORT" H 1350 3200 30 0000 C CNN +F 2 "" H 1350 3200 60 0000 C CNN +F 3 "" H 1350 3200 60 0000 C CNN + 3 1350 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C93AB5F +P 1350 3700 +F 0 "U1" H 1400 3800 30 0000 C CNN +F 1 "PORT" H 1350 3700 30 0000 C CNN +F 2 "" H 1350 3700 60 0000 C CNN +F 3 "" H 1350 3700 60 0000 C CNN + 4 1350 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C93AD97 +P 1350 5250 +F 0 "U1" H 1400 5350 30 0000 C CNN +F 1 "PORT" H 1350 5250 30 0000 C CNN +F 2 "" H 1350 5250 60 0000 C CNN +F 3 "" H 1350 5250 60 0000 C CNN + 7 1350 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C93ADFC +P 1350 5850 +F 0 "U1" H 1400 5950 30 0000 C CNN +F 1 "PORT" H 1350 5850 30 0000 C CNN +F 2 "" H 1350 5850 60 0000 C CNN +F 3 "" H 1350 5850 60 0000 C CNN + 8 1350 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C93AE63 +P 1350 6350 +F 0 "U1" H 1400 6450 30 0000 C CNN +F 1 "PORT" H 1350 6350 30 0000 C CNN +F 2 "" H 1350 6350 60 0000 C CNN +F 3 "" H 1350 6350 60 0000 C CNN + 9 1350 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C93AECA +P 1350 3950 +F 0 "U1" H 1400 4050 30 0000 C CNN +F 1 "PORT" H 1350 3950 30 0000 C CNN +F 2 "" H 1350 3950 60 0000 C CNN +F 3 "" H 1350 3950 60 0000 C CNN + 5 1350 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C93AF79 +P 1350 6600 +F 0 "U1" H 1400 6700 30 0000 C CNN +F 1 "PORT" H 1350 6600 30 0000 C CNN +F 2 "" H 1350 6600 60 0000 C CNN +F 3 "" H 1350 6600 60 0000 C CNN + 10 1350 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C93B10A +P 1550 950 +F 0 "U1" H 1600 1050 30 0000 C CNN +F 1 "PORT" H 1550 950 30 0000 C CNN +F 2 "" H 1550 950 60 0000 C CNN +F 3 "" H 1550 950 60 0000 C CNN + 11 1550 950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5C93B179 +P 1550 1350 +F 0 "U1" H 1600 1450 30 0000 C CNN +F 1 "PORT" H 1550 1350 30 0000 C CNN +F 2 "" H 1550 1350 60 0000 C CNN +F 3 "" H 1550 1350 60 0000 C CNN + 12 1550 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 2600 7600 2600 +Wire Wire Line + 7300 5250 7650 5250 +$Comp +L PORT U1 +U 13 1 5C93B567 +P 7850 2600 +F 0 "U1" H 7900 2700 30 0000 C CNN +F 1 "PORT" H 7850 2600 30 0000 C CNN +F 2 "" H 7850 2600 60 0000 C CNN +F 3 "" H 7850 2600 60 0000 C CNN + 13 7850 2600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C93B5DA +P 7900 5250 +F 0 "U1" H 7950 5350 30 0000 C CNN +F 1 "PORT" H 7900 5250 30 0000 C CNN +F 2 "" H 7900 5250 60 0000 C CNN +F 3 "" H 7900 5250 60 0000 C CNN + 14 7900 5250 + -1 0 0 1 +$EndComp +Connection ~ 2200 3450 +Wire Wire Line + 3200 5100 3400 5100 +Wire Wire Line + 3400 5000 2300 5000 +Connection ~ 2300 5000 +Wire Wire Line + 3100 5600 3350 5600 +Wire Wire Line + 2200 5700 3350 5700 +Wire Wire Line + 2200 6200 3350 6200 +Connection ~ 2200 5700 +Wire Wire Line + 2300 6100 3350 6100 +Wire Wire Line + 3400 2450 3200 2450 +Connection ~ 3200 2450 +Wire Wire Line + 3400 2350 2300 2350 +Connection ~ 2300 2350 +Wire Wire Line + 3350 3050 2200 3050 +Connection ~ 2200 3050 +Wire Wire Line + 3350 2950 3100 2950 +Connection ~ 3100 2950 +Wire Wire Line + 3350 3450 2300 3450 +Wire Wire Line + 2300 3450 2300 3400 +Connection ~ 2300 3400 +Wire Wire Line + 3350 3550 2200 3550 +Connection ~ 2200 3550 +$Comp +L d_inverter U34 +U 1 1 5C95C9D0 +P 2650 3950 +F 0 "U34" H 2650 3850 60 0000 C CNN +F 1 "d_inverter" H 2650 4100 60 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 1 2650 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 5C95CD17 +P 2700 6600 +F 0 "U35" H 2700 6500 60 0000 C CNN +F 1 "d_inverter" H 2700 6750 60 0000 C CNN +F 2 "" H 2750 6550 60 0000 C CNN +F 3 "" H 2750 6550 60 0000 C CNN + 1 2700 6600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/analysis b/src/SubcircuitLibrary/74153/analysis index 655d30ed..ebd5c0a9 100644 --- a/src/SubcircuitLibrary/74153/analysis +++ b/src/SubcircuitLibrary/74153/analysis @@ -1 +1 @@ -.tran 0e-03 0e-00 0e-03
\ No newline at end of file +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/74157/3_and-cache.lib +++ b/src/SubcircuitLibrary/74157/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/74157/3_and.cir +++ b/src/SubcircuitLibrary/74157/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/74157/3_and.cir.out +++ b/src/SubcircuitLibrary/74157/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro index 0fdf4d25..2c9ac554 100644 --- a/src/SubcircuitLibrary/74157/3_and.pro +++ b/src/SubcircuitLibrary/74157/3_and.pro @@ -1,44 +1,58 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch index c853bf49..86be0215 100644 --- a/src/SubcircuitLibrary/74157/3_and.sch +++ b/src/SubcircuitLibrary/74157/3_and.sch @@ -1,130 +1,121 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/74157/3_and.sub +++ b/src/SubcircuitLibrary/74157/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib index d72d1628..de171255 100644 --- a/src/SubcircuitLibrary/74157/74157-cache.lib +++ b/src/SubcircuitLibrary/74157/74157-cache.lib @@ -1,17 +1,17 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # -# 3_and-RESCUE-74157 +# 3_and # -DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N +DEF 3_and X 0 40 Y Y 1 F N F0 "X" 900 300 60 H V C CNN -F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N X in1 1 450 500 200 R 50 50 1 1 I X in2 2 450 400 200 R 50 50 1 1 I X in3 3 450 300 200 R 50 50 1 1 I @@ -67,7 +67,7 @@ F1 "d_inverter" 0 150 60 H V C CNN F2 "" 50 -50 60 H V C CNN F3 "" 50 -50 60 H V C CNN DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N X ~ 1 -300 0 200 R 50 50 1 1 I X ~ 2 300 0 200 L 50 50 1 1 O I ENDDRAW @@ -84,8 +84,8 @@ DRAW A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 A -25 -124 325 574 323 0 1 0 N 150 150 250 50 A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N X IN1 1 -450 100 215 R 50 50 1 1 I X IN2 2 -450 0 215 R 50 50 1 1 I X OUT 3 450 50 200 L 50 50 1 1 O diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir index cfd1c0e9..6920161c 100644 --- a/src/SubcircuitLibrary/74157/74157.cir +++ b/src/SubcircuitLibrary/74157/74157.cir @@ -1,25 +1,25 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/74157/74157.cir +* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 20:50:36 2019 +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 * Sheet Name: / -U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad4_ d_or -U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad7_ d_or -U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad9_ d_or -U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad12_ d_or -U3 Net-_U1-Pad1_ Net-_U3-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT -U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_inverter -X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad1_ 3_and -X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U21-Pad1_ 3_and -X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U22-Pad1_ 3_and -X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U23-Pad1_ 3_and -X6 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U20-Pad2_ 3_and -X7 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U21-Pad2_ 3_and -X1 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad10_ Net-_U22-Pad2_ 3_and -X8 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad13_ Net-_U23-Pad2_ 3_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or +U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter +X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and +X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and +X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and +X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and +X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and +X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and +X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and +X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and .end diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out index b9a19223..3a11a42d 100644 --- a/src/SubcircuitLibrary/74157/74157.cir.out +++ b/src/SubcircuitLibrary/74157/74157.cir.out @@ -1,27 +1,27 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir .include 3_and.sub -* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or -* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or -* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or -* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or -* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port -* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter -x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and -x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and -x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and -x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and -x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and -x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and -x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and -x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and -a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20 -a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21 -a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22 -a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23 -a5 net-_u1-pad1_ net-_u3-pad2_ u3 -a6 net-_u1-pad15_ net-_u2-pad2_ u2 +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 * Schematic Name: d_or, NgSpice Name: d_or .model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro index 4042e1e9..fcbb1fc8 100644 --- a/src/SubcircuitLibrary/74157/74157.pro +++ b/src/SubcircuitLibrary/74157/74157.pro @@ -1,4 +1,4 @@ -update=Tue Jun 25 20:59:09 2019 +update=03/28/19 22:30:06 version=1 last_client=eeschema [general] @@ -29,16 +29,29 @@ version=1 NetIExt=net [eeschema] version=1 -LibDir=../../../kicadSchematicLibrary +LibDir= [eeschema/libraries] -LibName1=74157-rescue -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User +LibName1=power +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_User +LibName24=eSim_Subckt diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch index c7c64ece..7fd3609e 100644 --- a/src/SubcircuitLibrary/74157/74157.sch +++ b/src/SubcircuitLibrary/74157/74157.sch @@ -1,5 +1,17 @@ EESchema Schematic File Version 2 -LIBS:74157-rescue +LIBS:power +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves LIBS:eSim_Analog LIBS:eSim_Devices LIBS:eSim_Digital @@ -7,9 +19,10 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power +LIBS:eSim_PSpice LIBS:eSim_Sources -LIBS:eSim_Subckt LIBS:eSim_User +LIBS:eSim_Subckt LIBS:74157-cache EELAYER 25 0 EELAYER END @@ -25,6 +38,34 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 1650 1850 2750 1850 +Wire Wire Line + 2750 3350 1650 3350 +Wire Wire Line + 2750 3050 2750 3350 +Wire Wire Line + 2800 4050 1650 4050 +Wire Wire Line + 2800 3550 2800 4050 +Wire Wire Line + 2200 2150 2200 4350 +Wire Wire Line + 2200 2150 1650 2150 +Wire Wire Line + 2150 2900 2150 4850 +Wire Wire Line + 2150 2900 1650 2900 +Wire Wire Line + 2100 3600 2100 5300 +Wire Wire Line + 2100 3600 1650 3600 +Wire Wire Line + 2050 4300 2050 5800 +Wire Wire Line + 1650 4300 2050 4300 +Wire Wire Line + 2200 5500 2200 6250 $Comp L d_or U20 U 1 1 5C95E06C @@ -69,6 +110,62 @@ F 3 "" H 6650 4750 60 0000 C CNN 1 6650 4750 1 0 0 -1 $EndComp +Wire Wire Line + 6200 3200 5950 3200 +Wire Wire Line + 5950 3200 5950 2000 +Wire Wire Line + 5950 2000 4750 2000 +Wire Wire Line + 6200 3700 5850 3700 +Wire Wire Line + 5850 3700 5850 2500 +Wire Wire Line + 5850 2500 4750 2500 +Wire Wire Line + 6200 4150 5750 4150 +Wire Wire Line + 5750 4150 5750 2950 +Wire Wire Line + 5750 2950 4750 2950 +Wire Wire Line + 6200 4650 5650 4650 +Wire Wire Line + 5650 4650 5650 3450 +Wire Wire Line + 5650 3450 4750 3450 +Wire Wire Line + 4750 4250 5450 4250 +Wire Wire Line + 5450 4250 5450 3300 +Wire Wire Line + 5450 3300 6200 3300 +Wire Wire Line + 4750 4750 5550 4750 +Wire Wire Line + 5550 4750 5550 3800 +Wire Wire Line + 5550 3800 6200 3800 +Wire Wire Line + 4700 5200 5600 5200 +Wire Wire Line + 5600 5200 5600 4250 +Wire Wire Line + 5600 4250 6200 4250 +Wire Wire Line + 4750 5700 5700 5700 +Wire Wire Line + 5700 5700 5700 4750 +Wire Wire Line + 5700 4750 6200 4750 +Wire Wire Line + 7100 3250 8300 3250 +Wire Wire Line + 7100 3750 8300 3750 +Wire Wire Line + 7100 4200 8300 4200 +Wire Wire Line + 7100 4700 8250 4700 $Comp L d_inverter U3 U 1 1 5C95E74D @@ -80,154 +177,168 @@ F 3 "" H 2800 6200 60 0000 C CNN 1 2750 6250 1 0 0 -1 $EndComp +Wire Wire Line + 1700 6250 2450 6250 +Connection ~ 2200 6250 $Comp L PORT U1 -U 2 1 5C95E920 +U 1 1 5C95E920 P 1400 1850 F 0 "U1" H 1450 1950 30 0000 C CNN F 1 "PORT" H 1400 1850 30 0000 C CNN F 2 "" H 1400 1850 60 0000 C CNN F 3 "" H 1400 1850 60 0000 C CNN - 2 1400 1850 + 1 1400 1850 1 0 0 -1 $EndComp $Comp L PORT U1 -U 3 1 5C95E9CF +U 2 1 5C95E9CF P 1400 2150 F 0 "U1" H 1450 2250 30 0000 C CNN F 1 "PORT" H 1400 2150 30 0000 C CNN F 2 "" H 1400 2150 60 0000 C CNN F 3 "" H 1400 2150 60 0000 C CNN - 3 1400 2150 + 2 1400 2150 1 0 0 -1 $EndComp $Comp L PORT U1 -U 11 1 5C95EA28 +U 3 1 5C95EA28 +P 1400 2700 +F 0 "U1" H 1450 2800 30 0000 C CNN +F 1 "PORT" H 1400 2700 30 0000 C CNN +F 2 "" H 1400 2700 60 0000 C CNN +F 3 "" H 1400 2700 60 0000 C CNN + 3 1400 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C95EA9C +P 1400 2900 +F 0 "U1" H 1450 3000 30 0000 C CNN +F 1 "PORT" H 1400 2900 30 0000 C CNN +F 2 "" H 1400 2900 60 0000 C CNN +F 3 "" H 1400 2900 60 0000 C CNN + 4 1400 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C95EAFD P 1400 3350 F 0 "U1" H 1450 3450 30 0000 C CNN F 1 "PORT" H 1400 3350 30 0000 C CNN F 2 "" H 1400 3350 60 0000 C CNN F 3 "" H 1400 3350 60 0000 C CNN - 11 1400 3350 + 5 1400 3350 1 0 0 -1 $EndComp $Comp L PORT U1 -U 10 1 5C95EA9C +U 6 1 5C95EB63 P 1400 3600 F 0 "U1" H 1450 3700 30 0000 C CNN F 1 "PORT" H 1400 3600 30 0000 C CNN F 2 "" H 1400 3600 60 0000 C CNN F 3 "" H 1400 3600 60 0000 C CNN - 10 1400 3600 + 6 1400 3600 1 0 0 -1 $EndComp $Comp L PORT U1 -U 5 1 5C95EAFD -P 1400 2650 -F 0 "U1" H 1450 2750 30 0000 C CNN -F 1 "PORT" H 1400 2650 30 0000 C CNN -F 2 "" H 1400 2650 60 0000 C CNN -F 3 "" H 1400 2650 60 0000 C CNN - 5 1400 2650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C95EB63 -P 1400 2900 -F 0 "U1" H 1450 3000 30 0000 C CNN -F 1 "PORT" H 1400 2900 30 0000 C CNN -F 2 "" H 1400 2900 60 0000 C CNN -F 3 "" H 1400 2900 60 0000 C CNN - 6 1400 2900 +U 7 1 5C95EBC8 +P 1400 4050 +F 0 "U1" H 1450 4150 30 0000 C CNN +F 1 "PORT" H 1400 4050 30 0000 C CNN +F 2 "" H 1400 4050 60 0000 C CNN +F 3 "" H 1400 4050 60 0000 C CNN + 7 1400 4050 1 0 0 -1 $EndComp $Comp L PORT U1 -U 13 1 5C95EC38 +U 8 1 5C95EC38 P 1400 4300 F 0 "U1" H 1450 4400 30 0000 C CNN F 1 "PORT" H 1400 4300 30 0000 C CNN F 2 "" H 1400 4300 60 0000 C CNN F 3 "" H 1400 4300 60 0000 C CNN - 13 1400 4300 + 8 1400 4300 1 0 0 -1 $EndComp $Comp L PORT U1 -U 1 1 5C95ECA1 +U 10 1 5C95ECA1 P 1450 6250 F 0 "U1" H 1500 6350 30 0000 C CNN F 1 "PORT" H 1450 6250 30 0000 C CNN F 2 "" H 1450 6250 60 0000 C CNN F 3 "" H 1450 6250 60 0000 C CNN - 1 1450 6250 + 10 1450 6250 1 0 0 -1 $EndComp $Comp L PORT U1 -U 15 1 5C95ED51 +U 9 1 5C95ED51 P 1400 6650 F 0 "U1" H 1450 6750 30 0000 C CNN F 1 "PORT" H 1400 6650 30 0000 C CNN F 2 "" H 1400 6650 60 0000 C CNN F 3 "" H 1400 6650 60 0000 C CNN - 15 1400 6650 + 9 1400 6650 1 0 0 -1 $EndComp $Comp L PORT U1 -U 4 1 5C95EDCC +U 12 1 5C95EDCC P 8550 3250 F 0 "U1" H 8600 3350 30 0000 C CNN F 1 "PORT" H 8550 3250 30 0000 C CNN F 2 "" H 8550 3250 60 0000 C CNN F 3 "" H 8550 3250 60 0000 C CNN - 4 8550 3250 + 12 8550 3250 -1 0 0 1 $EndComp $Comp L PORT U1 -U 7 1 5C95EEA6 +U 13 1 5C95EEA6 P 8550 3750 F 0 "U1" H 8600 3850 30 0000 C CNN F 1 "PORT" H 8550 3750 30 0000 C CNN F 2 "" H 8550 3750 60 0000 C CNN F 3 "" H 8550 3750 60 0000 C CNN - 7 8550 3750 + 13 8550 3750 -1 0 0 1 $EndComp $Comp L PORT U1 -U 9 1 5C95EF2D +U 14 1 5C95EF2D P 8550 4200 F 0 "U1" H 8600 4300 30 0000 C CNN F 1 "PORT" H 8550 4200 30 0000 C CNN F 2 "" H 8550 4200 60 0000 C CNN F 3 "" H 8550 4200 60 0000 C CNN - 9 8550 4200 + 14 8550 4200 -1 0 0 1 $EndComp $Comp L PORT U1 -U 12 1 5C95EFB5 +U 11 1 5C95EFB5 P 8500 4700 F 0 "U1" H 8550 4800 30 0000 C CNN F 1 "PORT" H 8500 4700 30 0000 C CNN F 2 "" H 8500 4700 60 0000 C CNN F 3 "" H 8500 4700 60 0000 C CNN - 12 8500 4700 + 11 8500 4700 -1 0 0 1 $EndComp Text Notes 1950 1800 0 60 ~ 12 A0\n Text Notes 1950 2100 0 60 ~ 12 A1 -Text Notes 1900 2600 0 60 ~ 12 +Text Notes 1900 2650 0 60 ~ 12 B0 Text Notes 1900 2900 0 60 ~ 12 B1\n @@ -254,6 +365,10 @@ F 3 "" H 2700 6600 60 0000 C CNN 1 2650 6650 1 0 0 -1 $EndComp +Wire Wire Line + 3400 6650 2950 6650 +Wire Wire Line + 1650 6650 2350 6650 Text Notes 7850 3200 0 60 ~ 12 YA Text Notes 7850 3700 0 60 ~ 12 @@ -262,8 +377,69 @@ Text Notes 7850 4200 2 60 ~ 12 YC Text Notes 7800 4700 0 60 ~ 12 YD +Wire Wire Line + 3450 2000 3900 2000 +Wire Wire Line + 3450 2000 3450 5700 +Wire Wire Line + 3450 2500 3900 2500 +Wire Wire Line + 3450 2950 3900 2950 +Connection ~ 3450 2500 +Wire Wire Line + 3450 3450 3900 3450 +Connection ~ 3450 2950 +Wire Wire Line + 3450 4250 3900 4250 +Connection ~ 3450 3450 +Wire Wire Line + 3450 4750 3900 4750 +Connection ~ 3450 4250 +Wire Wire Line + 3450 5200 3850 5200 +Connection ~ 3450 4750 +Wire Wire Line + 3400 5700 3900 5700 +Connection ~ 3450 5200 +Wire Wire Line + 3300 5600 3900 5600 +Wire Wire Line + 3300 4150 3300 5600 +Wire Wire Line + 3300 5100 3850 5100 +Wire Wire Line + 3300 4650 3900 4650 +Connection ~ 3300 5100 +Wire Wire Line + 3300 4150 3900 4150 +Connection ~ 3300 4650 +Wire Wire Line + 3250 3350 3900 3350 +Wire Wire Line + 3250 1900 3250 3350 +Wire Wire Line + 3250 2850 3900 2850 +Wire Wire Line + 3250 2400 3900 2400 +Connection ~ 3250 2850 +Wire Wire Line + 3250 1900 3900 1900 +Connection ~ 3250 2400 +Wire Wire Line + 3250 3000 3100 3000 +Wire Wire Line + 3100 3000 3100 6250 +Wire Wire Line + 3100 6250 3050 6250 +Connection ~ 3250 3000 +Wire Wire Line + 3300 5500 2200 5500 +Connection ~ 3300 5500 +Wire Wire Line + 3400 6650 3400 5700 +Connection ~ 3450 5700 $Comp -L 3_and-RESCUE-74157 X2 +L 3_and X2 U 1 1 5C9D0110 P 3450 2400 F 0 "X2" H 4350 2700 60 0000 C CNN @@ -274,7 +450,7 @@ F 3 "" H 3450 2400 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X3 +L 3_and X3 U 1 1 5C9D01B8 P 3450 2900 F 0 "X3" H 4350 3200 60 0000 C CNN @@ -285,7 +461,7 @@ F 3 "" H 3450 2900 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X4 +L 3_and X4 U 1 1 5C9D0222 P 3450 3350 F 0 "X4" H 4350 3650 60 0000 C CNN @@ -296,7 +472,7 @@ F 3 "" H 3450 3350 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X5 +L 3_and X5 U 1 1 5C9D0289 P 3450 3850 F 0 "X5" H 4350 4150 60 0000 C CNN @@ -307,7 +483,7 @@ F 3 "" H 3450 3850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X6 +L 3_and X6 U 1 1 5C9D0361 P 3450 4650 F 0 "X6" H 4350 4950 60 0000 C CNN @@ -318,7 +494,7 @@ F 3 "" H 3450 4650 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X7 +L 3_and X7 U 1 1 5C9D0367 P 3450 5150 F 0 "X7" H 4350 5450 60 0000 C CNN @@ -329,7 +505,7 @@ F 3 "" H 3450 5150 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X1 +L 3_and X1 U 1 1 5C9D036D P 3400 5600 F 0 "X1" H 4300 5900 60 0000 C CNN @@ -340,7 +516,7 @@ F 3 "" H 3400 5600 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L 3_and-RESCUE-74157 X8 +L 3_and X8 U 1 1 5C9D0373 P 3450 6100 F 0 "X8" H 4350 6400 60 0000 C CNN @@ -350,180 +526,6 @@ F 3 "" H 3450 6100 60 0000 C CNN 1 3450 6100 1 0 0 -1 $EndComp -$Comp -L PORT U1 -U 8 1 5D123D14 -P 8450 1500 -F 0 "U1" H 8500 1600 30 0000 C CNN -F 1 "PORT" H 8450 1500 30 0000 C CNN -F 2 "" H 8450 1500 60 0000 C CNN -F 3 "" H 8450 1500 60 0000 C CNN - 8 8450 1500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 16 1 5D123E38 -P 8450 1850 -F 0 "U1" H 8500 1950 30 0000 C CNN -F 1 "PORT" H 8450 1850 30 0000 C CNN -F 2 "" H 8450 1850 60 0000 C CNN -F 3 "" H 8450 1850 60 0000 C CNN - 16 8450 1850 - -1 0 0 1 -$EndComp -Wire Wire Line - 1650 1850 2750 1850 -Wire Wire Line - 2750 3350 1650 3350 -Wire Wire Line - 2750 3050 2750 3350 -Wire Wire Line - 2800 4050 1650 4050 -Wire Wire Line - 2800 3550 2800 4050 -Wire Wire Line - 2200 2150 2200 4350 -Wire Wire Line - 2200 2150 1650 2150 -Wire Wire Line - 2150 2900 2150 4850 -Wire Wire Line - 2150 2900 1650 2900 -Wire Wire Line - 2100 3600 2100 5300 -Wire Wire Line - 2100 3600 1650 3600 -Wire Wire Line - 2050 4300 2050 5800 -Wire Wire Line - 1650 4300 2050 4300 -Wire Wire Line - 2200 5500 2200 6250 -Wire Wire Line - 6200 3200 5950 3200 -Wire Wire Line - 5950 3200 5950 2000 -Wire Wire Line - 5950 2000 4750 2000 -Wire Wire Line - 6200 3700 5850 3700 -Wire Wire Line - 5850 3700 5850 2500 -Wire Wire Line - 5850 2500 4750 2500 -Wire Wire Line - 6200 4150 5750 4150 -Wire Wire Line - 5750 4150 5750 2950 -Wire Wire Line - 5750 2950 4750 2950 -Wire Wire Line - 6200 4650 5650 4650 -Wire Wire Line - 5650 4650 5650 3450 -Wire Wire Line - 5650 3450 4750 3450 -Wire Wire Line - 4750 4250 5450 4250 -Wire Wire Line - 5450 4250 5450 3300 -Wire Wire Line - 5450 3300 6200 3300 -Wire Wire Line - 4750 4750 5550 4750 -Wire Wire Line - 5550 4750 5550 3800 -Wire Wire Line - 5550 3800 6200 3800 -Wire Wire Line - 4700 5200 5600 5200 -Wire Wire Line - 5600 5200 5600 4250 -Wire Wire Line - 5600 4250 6200 4250 -Wire Wire Line - 4750 5700 5700 5700 -Wire Wire Line - 5700 5700 5700 4750 -Wire Wire Line - 5700 4750 6200 4750 -Wire Wire Line - 7100 3250 8300 3250 -Wire Wire Line - 7100 3750 8300 3750 -Wire Wire Line - 7100 4200 8300 4200 -Wire Wire Line - 7100 4700 8250 4700 -Wire Wire Line - 1700 6250 2450 6250 -Connection ~ 2200 6250 -Wire Wire Line - 3400 6650 2950 6650 -Wire Wire Line - 1650 6650 2350 6650 -Wire Wire Line - 3450 2000 3900 2000 -Wire Wire Line - 3450 2000 3450 5700 -Wire Wire Line - 3450 2500 3900 2500 -Wire Wire Line - 3450 2950 3900 2950 -Connection ~ 3450 2500 -Wire Wire Line - 3450 3450 3900 3450 -Connection ~ 3450 2950 -Wire Wire Line - 3450 4250 3900 4250 -Connection ~ 3450 3450 -Wire Wire Line - 3450 4750 3900 4750 -Connection ~ 3450 4250 -Wire Wire Line - 3450 5200 3850 5200 -Connection ~ 3450 4750 -Wire Wire Line - 3400 5700 3900 5700 -Connection ~ 3450 5200 -Wire Wire Line - 3300 5600 3900 5600 -Wire Wire Line - 3300 4150 3300 5600 -Wire Wire Line - 3300 5100 3850 5100 -Wire Wire Line - 3300 4650 3900 4650 -Connection ~ 3300 5100 -Wire Wire Line - 3300 4150 3900 4150 -Connection ~ 3300 4650 -Wire Wire Line - 3250 3350 3900 3350 -Wire Wire Line - 3250 1900 3250 3350 -Wire Wire Line - 3250 2850 3900 2850 -Wire Wire Line - 3250 2400 3900 2400 -Connection ~ 3250 2850 -Wire Wire Line - 3250 1900 3900 1900 -Connection ~ 3250 2400 -Wire Wire Line - 3250 3000 3100 3000 -Wire Wire Line - 3100 3000 3100 6250 -Wire Wire Line - 3100 6250 3050 6250 -Connection ~ 3250 3000 -Wire Wire Line - 3300 5500 2200 5500 -Connection ~ 3300 5500 -Wire Wire Line - 3400 6650 3400 5700 -Connection ~ 3450 5700 Wire Wire Line 3900 2100 2750 2100 Wire Wire Line @@ -531,7 +533,7 @@ Wire Wire Line Wire Wire Line 3900 2600 1650 2600 Wire Wire Line - 1650 2600 1650 2650 + 1650 2600 1650 2700 Wire Wire Line 3900 3050 2750 3050 Wire Wire Line @@ -544,17 +546,4 @@ Wire Wire Line 2100 5300 3850 5300 Wire Wire Line 2050 5800 3900 5800 -$Comp -L PORT U1 -U 14 1 5C95EBC8 -P 1400 4050 -F 0 "U1" H 1450 4150 30 0000 C CNN -F 1 "PORT" H 1400 4050 30 0000 C CNN -F 2 "" H 1400 4050 60 0000 C CNN -F 3 "" H 1400 4050 60 0000 C CNN - 14 1400 4050 - 1 0 0 -1 -$EndComp -NoConn ~ 8200 1500 -NoConn ~ 8200 1850 $EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub index 54897c26..545741f5 100644 --- a/src/SubcircuitLibrary/74157/74157.sub +++ b/src/SubcircuitLibrary/74157/74157.sub @@ -1,27 +1,27 @@ * Subcircuit 74157 -.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/74157/74157.cir +.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir .include 3_and.sub -* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad4_ d_or -* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad7_ d_or -* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad9_ d_or -* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad12_ d_or -* u3 net-_u1-pad1_ net-_u3-pad2_ d_inverter -* u2 net-_u1-pad15_ net-_u2-pad2_ d_inverter -x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad1_ 3_and -x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u21-pad1_ 3_and -x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad11_ net-_u22-pad1_ 3_and -x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u23-pad1_ 3_and -x6 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad3_ net-_u20-pad2_ 3_and -x7 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad6_ net-_u21-pad2_ 3_and -x1 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad10_ net-_u22-pad2_ 3_and -x8 net-_u1-pad1_ net-_u2-pad2_ net-_u1-pad13_ net-_u23-pad2_ 3_and -a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad4_ u20 -a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad7_ u21 -a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad9_ u22 -a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad12_ u23 -a5 net-_u1-pad1_ net-_u3-pad2_ u3 -a6 net-_u1-pad15_ net-_u2-pad2_ u2 +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or +* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter +x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and +x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and +x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and +x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and +x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and +x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and +x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and +x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and +a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 +a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 +a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 +a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 +a5 net-_u1-pad10_ net-_u3-pad2_ u3 +a6 net-_u1-pad9_ net-_u2-pad2_ u2 * Schematic Name: d_or, NgSpice Name: d_or .model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) * Schematic Name: d_or, NgSpice Name: d_or diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml index 6fa26ea2..85f14960 100644 --- a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml +++ b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x8><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib index 0a3ccf7f..af058641 100644 --- a/src/SubcircuitLibrary/7485/3_and-cache.lib +++ b/src/SubcircuitLibrary/7485/3_and-cache.lib @@ -1,61 +1,61 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir index 15f8954d..ba296cf0 100644 --- a/src/SubcircuitLibrary/7485/3_and.cir +++ b/src/SubcircuitLibrary/7485/3_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out index e3c96645..d7cf79a0 100644 --- a/src/SubcircuitLibrary/7485/3_and.cir.out +++ b/src/SubcircuitLibrary/7485/3_and.cir.out @@ -1,20 +1,20 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro index 0fdf4d25..2c9ac554 100644 --- a/src/SubcircuitLibrary/7485/3_and.pro +++ b/src/SubcircuitLibrary/7485/3_and.pro @@ -1,44 +1,58 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
+update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch index c853bf49..86be0215 100644 --- a/src/SubcircuitLibrary/7485/3_and.sch +++ b/src/SubcircuitLibrary/7485/3_and.sch @@ -1,130 +1,121 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub index b949ae4f..3d9120bb 100644 --- a/src/SubcircuitLibrary/7485/3_and.sub +++ b/src/SubcircuitLibrary/7485/3_and.sub @@ -1,14 +1,14 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib index cb84d8f2..ac396288 100644 --- a/src/SubcircuitLibrary/7485/4_and-cache.lib +++ b/src/SubcircuitLibrary/7485/4_and-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir index 35e46097..50d490fa 100644 --- a/src/SubcircuitLibrary/7485/4_and.cir +++ b/src/SubcircuitLibrary/7485/4_and.cir @@ -1,13 +1,13 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
-U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out index 6e35b18a..f40e5bc6 100644 --- a/src/SubcircuitLibrary/7485/4_and.cir.out +++ b/src/SubcircuitLibrary/7485/4_and.cir.out @@ -1,18 +1,18 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro index 814ad76a..6eb77fff 100644 --- a/src/SubcircuitLibrary/7485/4_and.pro +++ b/src/SubcircuitLibrary/7485/4_and.pro @@ -1,58 +1,57 @@ -update=06/01/19 15:08:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=4_and-rescue
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
+update=03/26/19 18:58:33 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch index 2d8296d4..883458e1 100644 --- a/src/SubcircuitLibrary/7485/4_and.sch +++ b/src/SubcircuitLibrary/7485/4_and.sch @@ -1,151 +1,139 @@ -EESchema Schematic File Version 2
-LIBS:4_and-rescue
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and-RESCUE-4_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60 0000 C CNN
-F 1 "3_and" H 4650 4000 60 0000 C CNN
-F 2 "" H 3700 3500 60 0000 C CNN
-F 3 "" H 3700 3500 60 0000 C CNN
- 1 3700 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60 0000 C CNN
-F 1 "d_and" H 5500 3500 60 0000 C CNN
-F 2 "" H 5450 3400 60 0000 C CNN
-F 3 "" H 5450 3400 60 0000 C CNN
- 1 5450 3400
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5000 3100 5000 3300
-Wire Wire Line
- 4150 3000 4150 2700
-Wire Wire Line
- 4150 2700 3200 2700
-Wire Wire Line
- 4150 3100 4000 3100
-Wire Wire Line
- 4000 3100 4000 3000
-Wire Wire Line
- 4000 3000 3200 3000
-Wire Wire Line
- 4150 3200 4150 3300
-Wire Wire Line
- 4150 3300 3250 3300
-Wire Wire Line
- 5000 3400 5000 3550
-Wire Wire Line
- 5000 3550 3250 3550
-Wire Wire Line
- 5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30 0000 C CNN
-F 1 "PORT" H 2950 2700 30 0000 C CNN
-F 2 "" H 2950 2700 60 0000 C CNN
-F 3 "" H 2950 2700 60 0000 C CNN
- 1 2950 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30 0000 C CNN
-F 1 "PORT" H 2950 3000 30 0000 C CNN
-F 2 "" H 2950 3000 60 0000 C CNN
-F 3 "" H 2950 3000 60 0000 C CNN
- 2 2950 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30 0000 C CNN
-F 1 "PORT" H 3000 3300 30 0000 C CNN
-F 2 "" H 3000 3300 60 0000 C CNN
-F 3 "" H 3000 3300 60 0000 C CNN
- 3 3000 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30 0000 C CNN
-F 1 "PORT" H 3000 3550 30 0000 C CNN
-F 2 "" H 3000 3550 60 0000 C CNN
-F 3 "" H 3000 3550 60 0000 C CNN
- 4 3000 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30 0000 C CNN
-F 1 "PORT" H 6750 3350 30 0000 C CNN
-F 2 "" H 6750 3350 60 0000 C CNN
-F 3 "" H 6750 3350 60 0000 C CNN
- 5 6750 3350
- -1 0 0 1
-$EndComp
-Text Notes 3450 2650 0 60 ~ 12
-in1
-Text Notes 3450 2950 0 60 ~ 12
-in2
-Text Notes 3500 3300 0 60 ~ 12
-in3
-Text Notes 3500 3550 0 60 ~ 12
-in4
-Text Notes 6150 3350 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub index bf20b628..8663f37e 100644 --- a/src/SubcircuitLibrary/7485/4_and.sub +++ b/src/SubcircuitLibrary/7485/4_and.sub @@ -1,12 +1,12 @@ -* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib index 4cf915be..ac396288 100644 --- a/src/SubcircuitLibrary/7485/5_and-cache.lib +++ b/src/SubcircuitLibrary/7485/5_and-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir index ca1199bd..6a05b9b5 100644 --- a/src/SubcircuitLibrary/7485/5_and.cir +++ b/src/SubcircuitLibrary/7485/5_and.cir @@ -1,14 +1,14 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
-U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
-U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out index 20d3f8a5..6a6b126a 100644 --- a/src/SubcircuitLibrary/7485/5_and.cir.out +++ b/src/SubcircuitLibrary/7485/5_and.cir.out @@ -1,22 +1,22 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro index a9d6304f..c82e4e6d 100644 --- a/src/SubcircuitLibrary/7485/5_and.pro +++ b/src/SubcircuitLibrary/7485/5_and.pro @@ -1,50 +1,50 @@ -update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
+update=03/26/19 18:50:27 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_PSpice +LibName15=eSim_Sources +LibName16=eSim_Subckt +LibName17=eSim_User diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch index 0d86cdec..da927b09 100644 --- a/src/SubcircuitLibrary/7485/5_and.sch +++ b/src/SubcircuitLibrary/7485/5_and.sch @@ -1,171 +1,158 @@ -EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60 0000 C CNN
-F 1 "3_and" H 4750 3850 60 0000 C CNN
-F 2 "" H 3800 3350 60 0000 C CNN
-F 3 "" H 3800 3350 60 0000 C CNN
- 1 3800 3350
- 1 0 0 -1
-$EndComp
-$Comp
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-U 1 1 5C9A2764
-P 4650 3400
-F 0 "U2" H 4650 3400 60 0000 C CNN
-F 1 "d_and" H 4700 3500 60 0000 C CNN
-F 2 "" H 4650 3400 60 0000 C CNN
-F 3 "" H 4650 3400 60 0000 C CNN
- 1 4650 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2791
-P 5550 3200
-F 0 "U3" H 5550 3200 60 0000 C CNN
-F 1 "d_and" H 5600 3300 60 0000 C CNN
-F 2 "" H 5550 3200 60 0000 C CNN
-F 3 "" H 5550 3200 60 0000 C CNN
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-$EndComp
-Wire Wire Line
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- 4250 2950 4150 2950
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- 4200 3500 3600 3500
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- 6000 3150 6500 3150
-$Comp
-L PORT U1
-U 1 1 5C9A2865
-P 3350 2700
-F 0 "U1" H 3400 2800 30 0000 C CNN
-F 1 "PORT" H 3350 2700 30 0000 C CNN
-F 2 "" H 3350 2700 60 0000 C CNN
-F 3 "" H 3350 2700 60 0000 C CNN
- 1 3350 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A28B6
-P 3350 2900
-F 0 "U1" H 3400 3000 30 0000 C CNN
-F 1 "PORT" H 3350 2900 30 0000 C CNN
-F 2 "" H 3350 2900 60 0000 C CNN
-F 3 "" H 3350 2900 60 0000 C CNN
- 2 3350 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A28D9
-P 3350 3100
-F 0 "U1" H 3400 3200 30 0000 C CNN
-F 1 "PORT" H 3350 3100 30 0000 C CNN
-F 2 "" H 3350 3100 60 0000 C CNN
-F 3 "" H 3350 3100 60 0000 C CNN
- 3 3350 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A28FF
-P 3350 3300
-F 0 "U1" H 3400 3400 30 0000 C CNN
-F 1 "PORT" H 3350 3300 30 0000 C CNN
-F 2 "" H 3350 3300 60 0000 C CNN
-F 3 "" H 3350 3300 60 0000 C CNN
- 4 3350 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
-P 3350 3500
-F 0 "U1" H 3400 3600 30 0000 C CNN
-F 1 "PORT" H 3350 3500 30 0000 C CNN
-F 2 "" H 3350 3500 60 0000 C CNN
-F 3 "" H 3350 3500 60 0000 C CNN
- 5 3350 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
-P 6750 3150
-F 0 "U1" H 6800 3250 30 0000 C CNN
-F 1 "PORT" H 6750 3150 30 0000 C CNN
-F 2 "" H 6750 3150 60 0000 C CNN
-F 3 "" H 6750 3150 60 0000 C CNN
- 6 6750 3150
- -1 0 0 1
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-Text Notes 3800 2700 0 60 ~ 12
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-Text Notes 3800 3500 0 60 ~ 12
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-Text Notes 6150 3150 0 60 ~ 12
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-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub index 9d929fcb..35b10e17 100644 --- a/src/SubcircuitLibrary/7485/5_and.sub +++ b/src/SubcircuitLibrary/7485/5_and.sub @@ -1,16 +1,16 @@ -* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib index eb9a059e..6edb5033 100644 --- a/src/SubcircuitLibrary/7485/7485-cache.lib +++ b/src/SubcircuitLibrary/7485/7485-cache.lib @@ -4,80 +4,57 @@ EESchema-LIBRARY Version 2.3 # 3_and # DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN +F0 "X" 900 300 60 H V C CNN +F1 "3_and" 950 500 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O ENDDRAW ENDDEF # # 4_and # DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 50 -50 60 H V C CNN -F1 "4_and" 100 100 60 H V C CNN +F0 "X" 1500 1050 60 H V C CNN +F1 "4_and" 1550 1200 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 -P 2 0 1 0 -200 200 150 200 N -P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N -X in1 1 -400 150 200 R 50 50 1 1 I -X in2 2 -400 50 200 R 50 50 1 1 I -X in3 3 -400 -50 200 R 50 50 1 1 I -X in4 4 -400 -150 200 R 50 50 1 1 I -X out 5 500 0 200 L 50 50 1 1 O +A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 +P 2 0 1 0 1250 1300 1600 1300 N +P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N +X in1 1 1050 1250 200 R 50 50 1 1 I +X in2 2 1050 1150 200 R 50 50 1 1 I +X in3 3 1050 1050 200 R 50 50 1 1 I +X in4 4 1050 950 200 R 50 50 1 1 I +X out 5 1950 1100 200 L 50 50 1 1 O ENDDRAW ENDDEF # # 5_and # DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 5_nor -# -DEF 5_nor X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_nor" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -T 0 50 400 60 0 0 0 name~is~c_gate Normal 0 C C -T 0 50 450 60 0 0 0 subcircuit~file Normal 0 C C -A 150 0 316 716 -716 0 1 0 N 250 300 250 -300 -P 2 0 1 0 -300 300 250 300 N -P 4 0 1 0 -300 300 -300 -300 200 -300 250 -300 N -X in1 1 -500 250 200 R 50 50 1 1 I I -X in2 2 -500 150 200 R 50 50 1 1 I I -X in3 3 -500 50 200 R 50 50 1 1 I I -X in4 4 -500 -50 200 R 50 50 1 1 I I -X in5 5 -500 -150 200 R 50 50 1 1 I I -X in6 6 -500 -250 200 R 50 50 1 1 I I -X out 7 650 0 200 L 50 50 1 1 O +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O ENDDRAW ENDDEF # @@ -121,6 +98,27 @@ X ~ 26 250 0 100 L 30 30 26 1 B ENDDRAW ENDDEF # +# c_gate +# +DEF c_gate X 0 40 Y Y 1 F N +F0 "X" 5900 4450 60 H V C CNN +F1 "c_gate" 5950 4700 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 +P 2 0 1 0 5550 4850 6100 4850 N +P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N +X in1 1 5350 4800 200 R 50 50 1 1 I I +X in2 2 5350 4700 200 R 50 50 1 1 I I +X in3 3 5350 4600 200 R 50 50 1 1 I I +X in4 4 5350 4500 200 R 50 50 1 1 I I +X in5 5 5350 4400 200 R 50 50 1 1 I I +X in6 6 5350 4300 200 R 50 50 1 1 I I +X out 7 6500 4550 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# # d_and # DEF d_and U 0 40 Y Y 1 F N @@ -131,7 +129,7 @@ F3 "" 0 0 60 H V C CNN DRAW A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N X IN1 1 -450 100 200 R 50 50 1 1 I X IN2 2 -450 0 200 R 50 50 1 1 I X OUT 3 450 50 200 L 50 50 1 1 O @@ -148,7 +146,7 @@ F3 "" 0 0 60 H V C CNN DRAW A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N X IN1 1 -450 100 200 R 50 50 1 1 I X IN2 2 -450 0 200 R 50 50 1 1 I X OUT 3 450 50 200 L 50 50 1 1 O I @@ -166,8 +164,8 @@ DRAW A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 A -25 -124 325 574 323 0 1 0 N 150 150 250 50 A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N X IN1 1 -450 100 215 R 50 50 1 1 I X IN2 2 -450 0 215 R 50 50 1 1 I X OUT 3 450 50 200 L 50 50 1 1 O I diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir index 87188910..e15a357f 100644 --- a/src/SubcircuitLibrary/7485/7485.cir +++ b/src/SubcircuitLibrary/7485/7485.cir @@ -1,42 +1,42 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/7485/7485.cir +* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:22:51 2019 +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 * Sheet Name: / -U6 Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and -U2 Net-_U1-Pad15_ Net-_U1-Pad1_ Net-_U18-Pad2_ d_nand -U7 Net-_U18-Pad2_ Net-_U1-Pad1_ Net-_U14-Pad2_ d_and +U6 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand +U7 Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor -U19 Net-_U1-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and -U18 Net-_U1-Pad15_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and -U8 Net-_U1-Pad13_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and -U3 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U3-Pad3_ d_nand -U9 Net-_U3-Pad3_ Net-_U1-Pad14_ Net-_U15-Pad2_ d_and +U19 Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +X12 Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and +X7 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and +X9 Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and +X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and +X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and +X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and +U18 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +X8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and +X3 Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and +X6 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and +X5 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and +X4 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and +U8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and +U3 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand +U9 Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and -U5 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U12-Pad2_ d_nand -U13 Net-_U12-Pad2_ Net-_U1-Pad9_ Net-_U13-Pad3_ d_and +U5 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand +U13 Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor -U10 Net-_U1-Pad12_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and -U4 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U10-Pad2_ d_nand -U11 Net-_U10-Pad2_ Net-_U1-Pad11_ Net-_U11-Pad3_ d_and +U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U4 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand +U11 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT -X7 Net-_U1-Pad14_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad2_ 3_and -X8 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X12-Pad3_ 4_and -X3 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U1-Pad12_ Net-_X1-Pad4_ 4_and -X2 Net-_U14-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad13_ Net-_X1-Pad5_ 3_and -X6 Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad10_ Net-_X1-Pad3_ 5_and -X5 Net-_U1-Pad4_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad2_ 5_and -X4 Net-_U1-Pad3_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad1_ 5_and -X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X11-Pad6_ 5_and -X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X10-Pad6_ 5_and -X9 Net-_U1-Pad9_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X12-Pad4_ 5_and -X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad6_ 5_and -X12 Net-_U19-Pad3_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_X12-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad5_ 5_nor -X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad7_ 5_nor +X2 Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate +X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT .end diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out index 76e4fe6d..afc7b865 100644 --- a/src/SubcircuitLibrary/7485/7485.cir.out +++ b/src/SubcircuitLibrary/7485/7485.cir.out @@ -1,58 +1,58 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir -.include 5_nor.sub .include 4_and.sub .include 3_and.sub .include 5_and.sub -* u6 net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and -* u2 net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand -* u7 net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and * u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor -* u19 net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and -* u18 net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and -* u8 net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and -* u3 net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand -* u9 net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and * u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor * u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and -* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand -* u13 net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and * u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor -* u10 net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and -* u4 net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand -* u11 net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and * u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port -x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and -x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and -x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and -x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and -x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and -x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and -x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and -x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and -x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and -x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and -x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and -x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor -a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6 -a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2 -a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7 +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 -a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 -a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18 -a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8 -a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3 -a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 -a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5 -a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 -a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10 -a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4 -a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 * Schematic Name: d_and, NgSpice Name: d_and .model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro index fee23d1f..8fb4abb4 100644 --- a/src/SubcircuitLibrary/7485/7485.pro +++ b/src/SubcircuitLibrary/7485/7485.pro @@ -1,4 +1,4 @@ -update=Tue Jun 25 23:21:38 2019 +update=03/26/19 19:27:48 version=1 last_client=eeschema [general] @@ -29,15 +29,30 @@ version=1 NetIExt=net [eeschema] version=1 -LibDir=../../../kicadSchematicLibrary +LibDir= [eeschema/libraries] -LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User -LibName10=eSim_Subckt +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_User +LibName25=eSim_Subckt diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch index 32175173..0db5f0d6 100644 --- a/src/SubcircuitLibrary/7485/7485.sch +++ b/src/SubcircuitLibrary/7485/7485.sch @@ -1,4 +1,18 @@ EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves LIBS:eSim_Analog LIBS:eSim_Devices LIBS:eSim_Digital @@ -6,6 +20,7 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power +LIBS:eSim_PSpice LIBS:eSim_Sources LIBS:eSim_User LIBS:eSim_Subckt @@ -80,6 +95,72 @@ F 3 "" H 6900 1000 60 0000 C CNN 1 0 0 -1 $EndComp $Comp +L 3_and X12 +U 1 1 5C9A2DC4 +P 6050 1650 +F 0 "X12" H 6950 1950 60 0000 C CNN +F 1 "3_and" H 7000 2150 60 0000 C CNN +F 2 "" H 6050 1650 60 0000 C CNN +F 3 "" H 6050 1650 60 0000 C CNN + 1 6050 1650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9A2EB7 +P 5450 2750 +F 0 "X7" H 6950 3800 60 0000 C CNN +F 1 "4_and" H 7000 3950 60 0000 C CNN +F 2 "" H 5450 2750 60 0000 C CNN +F 3 "" H 5450 2750 60 0000 C CNN + 1 5450 2750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 5C9A2F2E +P 5650 3050 +F 0 "X9" H 7000 3850 60 0000 C CNN +F 1 "5_and" H 7050 4100 60 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 5C9A2F95 +P 5650 3600 +F 0 "X10" H 7000 4400 60 0000 C CNN +F 1 "5_and" H 7050 4650 60 0000 C CNN +F 2 "" H 5650 3600 60 0000 C CNN +F 3 "" H 5650 3600 60 0000 C CNN + 1 5650 3600 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 5C9A3164 +P 5650 4150 +F 0 "X11" H 7000 4950 60 0000 C CNN +F 1 "5_and" H 7050 5200 60 0000 C CNN +F 2 "" H 5650 4150 60 0000 C CNN +F 3 "" H 5650 4150 60 0000 C CNN + 1 5650 4150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 5C9A31B3 +P 7550 4850 +F 0 "X13" H 8900 5650 60 0000 C CNN +F 1 "5_and" H 8950 5900 60 0000 C CNN +F 2 "" H 7550 4850 60 0000 C CNN +F 3 "" H 7550 4850 60 0000 C CNN + 1 7550 4850 + 1 0 0 -1 +$EndComp +$Comp L d_and U18 U 1 1 5C9A32FD P 6350 6900 @@ -91,6 +172,61 @@ F 3 "" H 6350 6900 60 0000 C CNN 1 0 0 1 $EndComp $Comp +L 3_and X8 +U 1 1 5C9A3303 +P 5500 6250 +F 0 "X8" H 6400 6550 60 0000 C CNN +F 1 "3_and" H 6450 6750 60 0000 C CNN +F 2 "" H 5500 6250 60 0000 C CNN +F 3 "" H 5500 6250 60 0000 C CNN + 1 5500 6250 + 1 0 0 1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5C9A3309 +P 4900 5150 +F 0 "X3" H 6400 6200 60 0000 C CNN +F 1 "4_and" H 6450 6350 60 0000 C CNN +F 2 "" H 4900 5150 60 0000 C CNN +F 3 "" H 4900 5150 60 0000 C CNN + 1 4900 5150 + 1 0 0 1 +$EndComp +$Comp +L 5_and X6 +U 1 1 5C9A330F +P 5100 4850 +F 0 "X6" H 6450 5650 60 0000 C CNN +F 1 "5_and" H 6500 5900 60 0000 C CNN +F 2 "" H 5100 4850 60 0000 C CNN +F 3 "" H 5100 4850 60 0000 C CNN + 1 5100 4850 + 1 0 0 1 +$EndComp +$Comp +L 5_and X5 +U 1 1 5C9A3315 +P 5100 4300 +F 0 "X5" H 6450 5100 60 0000 C CNN +F 1 "5_and" H 6500 5350 60 0000 C CNN +F 2 "" H 5100 4300 60 0000 C CNN +F 3 "" H 5100 4300 60 0000 C CNN + 1 5100 4300 + 1 0 0 1 +$EndComp +$Comp +L 5_and X4 +U 1 1 5C9A331B +P 5100 3750 +F 0 "X4" H 6450 4550 60 0000 C CNN +F 1 "5_and" H 6500 4800 60 0000 C CNN +F 2 "" H 5100 3750 60 0000 C CNN +F 3 "" H 5100 3750 60 0000 C CNN + 1 5100 3750 + 1 0 0 1 +$EndComp +$Comp L d_and U8 U 1 1 5C9A39D8 P 3250 2600 @@ -222,20 +358,56 @@ F 3 "" H 4300 3950 60 0000 C CNN 1 4300 3950 1 0 0 -1 $EndComp +$Comp +L c_gate X2 +U 1 1 5C9A4498 +P 3050 6600 +F 0 "X2" H 3100 6650 60 0000 C CNN +F 1 "c_gate" H 9000 11300 60 0000 C CNN +F 2 "" H 3050 6600 60 0000 C CNN +F 3 "" H 3050 6600 60 0000 C CNN + 1 3050 6600 + 1 0 0 -1 +$EndComp +$Comp +L c_gate X1 +U 1 1 5C9A465F +P 2850 10000 +F 0 "X1" H 2900 10050 60 0000 C CNN +F 1 "c_gate" H 8800 14700 60 0000 C CNN +F 2 "" H 2850 10000 60 0000 C CNN +F 3 "" H 2850 10000 60 0000 C CNN + 1 2850 10000 + 1 0 0 -1 +$EndComp Wire Wire Line 3600 1300 3600 1150 Wire Wire Line 3600 1400 3600 1550 Wire Wire Line - 2700 1000 2700 4700 + 2700 1000 2700 1200 +Wire Wire Line + 2700 1200 2700 1400 +Wire Wire Line + 2700 1400 2700 1500 +Wire Wire Line + 2700 1500 2700 4700 Wire Wire Line 2700 1600 1550 1600 Wire Wire Line 1550 1600 1550 1450 Wire Wire Line - 1100 1450 1650 1450 + 1100 1450 1500 1450 +Wire Wire Line + 1500 1450 1550 1450 +Wire Wire Line + 1550 1450 1650 1450 +Wire Wire Line + 1100 1350 1400 1350 +Wire Wire Line + 1400 1350 1550 1350 Wire Wire Line - 1100 1350 1650 1350 + 1550 1350 1650 1350 Wire Wire Line 1550 1350 1550 1100 Wire Wire Line @@ -250,15 +422,29 @@ Wire Wire Line Wire Wire Line 3700 2800 3700 2950 Wire Wire Line - 2800 2000 2800 4600 + 2800 2000 2800 2600 +Wire Wire Line + 2800 2600 2800 2800 +Wire Wire Line + 2800 2800 2800 2900 +Wire Wire Line + 2800 2900 2800 4600 Wire Wire Line 2800 3000 1650 3000 Wire Wire Line 1650 3000 1650 2850 Wire Wire Line - 1200 2850 1750 2850 + 1200 2850 1600 2850 +Wire Wire Line + 1600 2850 1650 2850 +Wire Wire Line + 1650 2850 1750 2850 Wire Wire Line - 1200 2750 1750 2750 + 1200 2750 1450 2750 +Wire Wire Line + 1450 2750 1650 2750 +Wire Wire Line + 1650 2750 1750 2750 Wire Wire Line 1650 2750 1650 2500 Wire Wire Line @@ -273,15 +459,29 @@ Wire Wire Line Wire Wire Line 4050 5150 4050 5300 Wire Wire Line - 3150 4950 3150 5850 + 3150 4950 3150 5000 +Wire Wire Line + 3150 5000 3150 5150 +Wire Wire Line + 3150 5150 3150 5250 +Wire Wire Line + 3150 5250 3150 5850 Wire Wire Line 3150 5350 2000 5350 Wire Wire Line 2000 5350 2000 5200 Wire Wire Line - 1250 5200 2100 5200 + 1250 5200 1500 5200 +Wire Wire Line + 1500 5200 2000 5200 Wire Wire Line - 1250 5100 2100 5100 + 2000 5200 2100 5200 +Wire Wire Line + 1250 5100 1800 5100 +Wire Wire Line + 1800 5100 2000 5100 +Wire Wire Line + 2000 5100 2100 5100 Wire Wire Line 2000 5100 2000 4850 Wire Wire Line @@ -296,15 +496,29 @@ Wire Wire Line Wire Wire Line 3850 3950 3850 4100 Wire Wire Line - 2950 3200 2950 4350 + 2950 3200 2950 3750 +Wire Wire Line + 2950 3750 2950 3950 +Wire Wire Line + 2950 3950 2950 4050 +Wire Wire Line + 2950 4050 2950 4350 Wire Wire Line 2950 4150 1800 4150 Wire Wire Line 1800 4150 1800 4000 Wire Wire Line - 1350 4000 1900 4000 + 1350 4000 1750 4000 +Wire Wire Line + 1750 4000 1800 4000 +Wire Wire Line + 1800 4000 1900 4000 Wire Wire Line - 1200 3900 1900 3900 + 1200 3900 1600 3900 +Wire Wire Line + 1600 3900 1800 3900 +Wire Wire Line + 1800 3900 1900 3900 Wire Wire Line 1800 3900 1800 3650 Wire Wire Line @@ -343,9 +557,29 @@ Connection ~ 2800 2900 Wire Wire Line 5100 6550 5950 6550 Wire Wire Line - 5100 1350 5100 6550 + 5100 1350 5100 1700 +Wire Wire Line + 5100 1700 5100 2150 +Wire Wire Line + 5100 2150 5100 2500 +Wire Wire Line + 5100 2500 5100 3050 +Wire Wire Line + 5100 3050 5100 3750 +Wire Wire Line + 5100 3750 5100 4850 +Wire Wire Line + 5100 4850 5100 5400 Wire Wire Line - 4500 1350 6500 1350 + 5100 5400 5100 5750 +Wire Wire Line + 5100 5750 5100 6300 +Wire Wire Line + 5100 6300 5100 6550 +Wire Wire Line + 4500 1350 5100 1350 +Wire Wire Line + 5100 1350 6500 1350 Wire Wire Line 1500 1450 1500 900 Wire Wire Line @@ -393,7 +627,23 @@ Connection ~ 5100 1700 Wire Wire Line 6500 1800 5250 1800 Wire Wire Line - 5250 1800 5250 6100 + 5250 1800 5250 2250 +Wire Wire Line + 5250 2250 5250 2600 +Wire Wire Line + 5250 2600 5250 2750 +Wire Wire Line + 5250 2750 5250 3150 +Wire Wire Line + 5250 3150 5250 3850 +Wire Wire Line + 5250 3850 5250 4750 +Wire Wire Line + 5250 4750 5250 5300 +Wire Wire Line + 5250 5300 5250 5650 +Wire Wire Line + 5250 5650 5250 6100 Wire Wire Line 5250 2750 4600 2750 Wire Wire Line @@ -419,7 +669,19 @@ Connection ~ 5250 2250 Wire Wire Line 6500 2350 5350 2350 Wire Wire Line - 5350 2350 5350 5550 + 5350 2350 5350 2700 +Wire Wire Line + 5350 2700 5350 3200 +Wire Wire Line + 5350 3200 5350 3900 +Wire Wire Line + 5350 3900 5350 4050 +Wire Wire Line + 5350 4050 5350 4650 +Wire Wire Line + 5350 4650 5350 5200 +Wire Wire Line + 5350 5200 5350 5550 Wire Wire Line 5350 3900 4750 3900 Wire Wire Line @@ -434,9 +696,17 @@ Connection ~ 5350 2700 Wire Wire Line 6500 2800 5450 2800 Wire Wire Line - 5450 2800 5450 5100 + 5450 2800 5450 3350 Wire Wire Line - 4950 5100 5950 5100 + 5450 3350 5450 4150 +Wire Wire Line + 5450 4150 5450 4550 +Wire Wire Line + 5450 4550 5450 5100 +Wire Wire Line + 4950 5100 5450 5100 +Wire Wire Line + 5450 5100 5950 5100 Wire Wire Line 6500 2900 5550 2900 Wire Wire Line @@ -460,13 +730,19 @@ Wire Wire Line 6500 3350 5450 3350 Connection ~ 5450 3350 Wire Wire Line - 4800 3450 6500 3450 + 4800 3450 5950 3450 +Wire Wire Line + 5950 3450 6500 3450 Wire Wire Line - 4800 3400 4800 3450 + 4800 3450 4800 3400 Wire Wire Line - 1050 3400 4800 3400 + 4800 3400 2600 3400 Wire Wire Line - 5950 3450 5950 4450 + 2050 3400 1050 3400 +Wire Wire Line + 5950 3450 5950 3950 +Wire Wire Line + 5950 3950 5950 4450 Connection ~ 5950 3450 Wire Wire Line 5950 4550 5450 4550 @@ -616,72 +892,72 @@ Wire Wire Line 7950 5700 8200 5700 $Comp L PORT U1 -U 15 1 5C9A8539 +U 4 1 5C9A8539 P 850 1350 F 0 "U1" H 900 1450 30 0000 C CNN F 1 "PORT" H 850 1350 30 0000 C CNN F 2 "" H 850 1350 60 0000 C CNN F 3 "" H 850 1350 60 0000 C CNN - 15 850 1350 + 4 850 1350 1 0 0 -1 $EndComp $Comp L PORT U1 -U 1 1 5C9A8668 +U 5 1 5C9A8668 P 850 1550 F 0 "U1" H 900 1650 30 0000 C CNN F 1 "PORT" H 850 1550 30 0000 C CNN F 2 "" H 850 1550 60 0000 C CNN F 3 "" H 850 1550 60 0000 C CNN - 1 850 1550 + 5 850 1550 1 0 0 -1 $EndComp Wire Wire Line 1100 1550 1100 1450 $Comp L PORT U1 -U 13 1 5C9A8815 +U 6 1 5C9A8815 P 950 2650 F 0 "U1" H 1000 2750 30 0000 C CNN F 1 "PORT" H 950 2650 30 0000 C CNN F 2 "" H 950 2650 60 0000 C CNN F 3 "" H 950 2650 60 0000 C CNN - 13 950 2650 + 6 950 2650 1 0 0 -1 $EndComp Wire Wire Line 1200 2650 1200 2750 $Comp L PORT U1 -U 14 1 5C9A8B82 +U 7 1 5C9A8B82 P 950 2850 F 0 "U1" H 1000 2950 30 0000 C CNN F 1 "PORT" H 950 2850 30 0000 C CNN F 2 "" H 950 2850 60 0000 C CNN F 3 "" H 950 2850 60 0000 C CNN - 14 950 2850 + 7 950 2850 1 0 0 -1 $EndComp $Comp L PORT U1 -U 12 1 5C9A8C46 +U 8 1 5C9A8C46 P 950 3900 F 0 "U1" H 1000 4000 30 0000 C CNN F 1 "PORT" H 950 3900 30 0000 C CNN F 2 "" H 950 3900 60 0000 C CNN F 3 "" H 950 3900 60 0000 C CNN - 12 950 3900 + 8 950 3900 1 0 0 -1 $EndComp $Comp L PORT U1 -U 11 1 5C9A8D2C +U 9 1 5C9A8D2C P 950 4100 F 0 "U1" H 1000 4200 30 0000 C CNN F 1 "PORT" H 950 4100 30 0000 C CNN F 2 "" H 950 4100 60 0000 C CNN F 3 "" H 950 4100 60 0000 C CNN - 11 950 4100 + 9 950 4100 1 0 0 -1 $EndComp $Comp @@ -697,46 +973,46 @@ F 3 "" H 1000 5100 60 0000 C CNN $EndComp $Comp L PORT U1 -U 9 1 5C9A8E65 +U 11 1 5C9A8E65 P 1000 5300 F 0 "U1" H 1050 5400 30 0000 C CNN F 1 "PORT" H 1000 5300 30 0000 C CNN F 2 "" H 1000 5300 60 0000 C CNN F 3 "" H 1000 5300 60 0000 C CNN - 9 1000 5300 + 11 1000 5300 1 0 0 -1 $EndComp $Comp L PORT U1 -U 2 1 5C9A8EEE +U 1 1 5C9A8EEE P 800 3150 F 0 "U1" H 850 3250 30 0000 C CNN F 1 "PORT" H 800 3150 30 0000 C CNN F 2 "" H 800 3150 60 0000 C CNN F 3 "" H 800 3150 60 0000 C CNN - 2 800 3150 + 1 800 3150 1 0 0 -1 $EndComp $Comp L PORT U1 -U 3 1 5C9A8F9C +U 2 1 5C9A8F9C P 800 3400 F 0 "U1" H 850 3500 30 0000 C CNN F 1 "PORT" H 800 3400 30 0000 C CNN F 2 "" H 800 3400 60 0000 C CNN F 3 "" H 800 3400 60 0000 C CNN - 3 800 3400 + 2 800 3400 1 0 0 -1 $EndComp $Comp L PORT U1 -U 4 1 5C9A9031 +U 3 1 5C9A9031 P 800 3600 F 0 "U1" H 850 3700 30 0000 C CNN F 1 "PORT" H 800 3600 30 0000 C CNN F 2 "" H 800 3600 60 0000 C CNN F 3 "" H 800 3600 60 0000 C CNN - 4 800 3600 + 3 800 3600 1 0 0 -1 $EndComp Wire Wire Line @@ -755,35 +1031,35 @@ Wire Wire Line 9350 5450 9900 5450 $Comp L PORT U1 -U 5 1 5C9A9B26 +U 12 1 5C9A9B26 P 10100 2050 F 0 "U1" H 10150 2150 30 0000 C CNN F 1 "PORT" H 10100 2050 30 0000 C CNN F 2 "" H 10100 2050 60 0000 C CNN F 3 "" H 10100 2050 60 0000 C CNN - 5 10100 2050 + 12 10100 2050 -1 0 0 1 $EndComp $Comp L PORT U1 -U 6 1 5C9A9BCA +U 13 1 5C9A9BCA P 10100 3950 F 0 "U1" H 10150 4050 30 0000 C CNN F 1 "PORT" H 10100 3950 30 0000 C CNN F 2 "" H 10100 3950 60 0000 C CNN F 3 "" H 10100 3950 60 0000 C CNN - 6 10100 3950 + 13 10100 3950 -1 0 0 1 $EndComp $Comp L PORT U1 -U 7 1 5C9A9CA0 +U 14 1 5C9A9CA0 P 10150 5450 F 0 "U1" H 10200 5550 30 0000 C CNN F 1 "PORT" H 10150 5450 30 0000 C CNN F 2 "" H 10150 5450 60 0000 C CNN F 3 "" H 10150 5450 60 0000 C CNN - 7 10150 5450 + 14 10150 5450 -1 0 0 1 $EndComp Text Notes 9650 2000 0 60 ~ 12 @@ -846,172 +1122,6 @@ Wire Notes Line 10550 1550 9500 1550 Text Notes 9900 3400 0 60 ~ 12 Outputs -$Comp -L 3_and X7 -U 1 1 5D1262A3 -P 6850 1300 -F 0 "X7" H 6950 1250 60 0000 C CNN -F 1 "3_and" H 7000 1450 60 0000 C CNN -F 2 "" H 6850 1300 60 0000 C CNN -F 3 "" H 6850 1300 60 0000 C CNN - 1 6850 1300 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X8 -U 1 1 5D126302 -P 6900 1650 -F 0 "X8" H 6950 1600 60 0000 C CNN -F 1 "4_and" H 7000 1750 60 0000 C CNN -F 2 "" H 6900 1650 60 0000 C CNN -F 3 "" H 6900 1650 60 0000 C CNN - 1 6900 1650 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X3 -U 1 1 5D12638A -P 6350 6250 -F 0 "X3" H 6400 6200 60 0000 C CNN -F 1 "4_and" H 6450 6350 60 0000 C CNN -F 2 "" H 6350 6250 60 0000 C CNN -F 3 "" H 6350 6250 60 0000 C CNN - 1 6350 6250 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X2 -U 1 1 5D126462 -P 6300 6700 -F 0 "X2" H 6400 6650 60 0000 C CNN -F 1 "3_and" H 6450 6850 60 0000 C CNN -F 2 "" H 6300 6700 60 0000 C CNN -F 3 "" H 6300 6700 60 0000 C CNN - 1 6300 6700 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X6 -U 1 1 5D126552 -P 6400 5750 -F 0 "X6" H 6450 5650 60 0000 C CNN -F 1 "5_and" H 6500 5900 60 0000 C CNN -F 2 "" H 6400 5750 60 0000 C CNN -F 3 "" H 6400 5750 60 0000 C CNN - 1 6400 5750 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X5 -U 1 1 5D1265DF -P 6400 5200 -F 0 "X5" H 6450 5100 60 0000 C CNN -F 1 "5_and" H 6500 5350 60 0000 C CNN -F 2 "" H 6400 5200 60 0000 C CNN -F 3 "" H 6400 5200 60 0000 C CNN - 1 6400 5200 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X4 -U 1 1 5D12666C -P 6400 4650 -F 0 "X4" H 6450 4550 60 0000 C CNN -F 1 "5_and" H 6500 4800 60 0000 C CNN -F 2 "" H 6400 4650 60 0000 C CNN -F 3 "" H 6400 4650 60 0000 C CNN - 1 6400 4650 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X11 -U 1 1 5D126706 -P 6950 3250 -F 0 "X11" H 7000 3150 60 0000 C CNN -F 1 "5_and" H 7050 3400 60 0000 C CNN -F 2 "" H 6950 3250 60 0000 C CNN -F 3 "" H 6950 3250 60 0000 C CNN - 1 6950 3250 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X10 -U 1 1 5D1267CB -P 6950 2700 -F 0 "X10" H 7000 2600 60 0000 C CNN -F 1 "5_and" H 7050 2850 60 0000 C CNN -F 2 "" H 6950 2700 60 0000 C CNN -F 3 "" H 6950 2700 60 0000 C CNN - 1 6950 2700 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X9 -U 1 1 5D12686F -P 6950 2150 -F 0 "X9" H 7000 2050 60 0000 C CNN -F 1 "5_and" H 7050 2300 60 0000 C CNN -F 2 "" H 6950 2150 60 0000 C CNN -F 3 "" H 6950 2150 60 0000 C CNN - 1 6950 2150 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X13 -U 1 1 5D126AC3 -P 8850 3950 -F 0 "X13" H 8900 3850 60 0000 C CNN -F 1 "5_and" H 8950 4100 60 0000 C CNN -F 2 "" H 8850 3950 60 0000 C CNN -F 3 "" H 8850 3950 60 0000 C CNN - 1 8850 3950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5D127AEB -P 10550 650 -F 0 "U1" H 10600 750 30 0000 C CNN -F 1 "PORT" H 10550 650 30 0000 C CNN -F 2 "" H 10550 650 60 0000 C CNN -F 3 "" H 10550 650 60 0000 C CNN - 8 10550 650 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 16 1 5D127BBA -P 10550 900 -F 0 "U1" H 10600 1000 30 0000 C CNN -F 1 "PORT" H 10550 900 30 0000 C CNN -F 2 "" H 10550 900 60 0000 C CNN -F 3 "" H 10550 900 60 0000 C CNN - 16 10550 900 - -1 0 0 1 -$EndComp -NoConn ~ 10300 650 -NoConn ~ 10300 900 -NoConn ~ 2950 10200 -$Comp -L 5_nor X12 -U 1 1 5D12919D -P 8900 2050 -F 0 "X12" H 8950 1950 60 0000 C CNN -F 1 "5_nor" H 9000 2200 60 0000 C CNN -F 2 "" H 8900 2050 60 0000 C CNN -F 3 "" H 8900 2050 60 0000 C CNN - 1 8900 2050 - 1 0 0 -1 -$EndComp -$Comp -L 5_nor X1 -U 1 1 5D12935A -P 8700 5450 -F 0 "X1" H 8750 5350 60 0000 C CNN -F 1 "5_nor" H 8800 5600 60 0000 C CNN -F 2 "" H 8700 5450 60 0000 C CNN -F 3 "" H 8700 5450 60 0000 C CNN - 1 8700 5450 - 1 0 0 -1 -$EndComp +Wire Wire Line + 2600 3400 2050 3400 $EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub index 63ea7f3b..5a45c57c 100644 --- a/src/SubcircuitLibrary/7485/7485.sub +++ b/src/SubcircuitLibrary/7485/7485.sub @@ -1,58 +1,58 @@ * Subcircuit 7485 -.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/7485/7485.cir -.include 5_nor.sub +.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir .include 4_and.sub .include 3_and.sub .include 5_and.sub -* u6 net-_u1-pad15_ net-_u18-pad2_ net-_u14-pad1_ d_and -* u2 net-_u1-pad15_ net-_u1-pad1_ net-_u18-pad2_ d_nand -* u7 net-_u18-pad2_ net-_u1-pad1_ net-_u14-pad2_ d_and +.include c_gate.sub +* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand +* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and * u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor -* u19 net-_u1-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and -* u18 net-_u1-pad15_ net-_u18-pad2_ net-_u18-pad3_ d_and -* u8 net-_u1-pad13_ net-_u3-pad3_ net-_u15-pad1_ d_and -* u3 net-_u1-pad13_ net-_u1-pad14_ net-_u3-pad3_ d_nand -* u9 net-_u3-pad3_ net-_u1-pad14_ net-_u15-pad2_ d_and +* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and +x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and +x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and +x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and +x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and +x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and +x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and +x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and +x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and +x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and +x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and +* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand +* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and * u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor * u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and -* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u12-pad2_ d_nand -* u13 net-_u12-pad2_ net-_u1-pad9_ net-_u13-pad3_ d_and +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and * u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor -* u10 net-_u1-pad12_ net-_u10-pad2_ net-_u10-pad3_ d_and -* u4 net-_u1-pad12_ net-_u1-pad11_ net-_u10-pad2_ d_nand -* u11 net-_u10-pad2_ net-_u1-pad11_ net-_u11-pad3_ d_and +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and * u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor -x7 net-_u1-pad14_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad2_ 3_and -x8 net-_u1-pad11_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x12-pad3_ 4_and -x3 net-_u15-pad3_ net-_u10-pad2_ net-_u14-pad3_ net-_u1-pad12_ net-_x1-pad4_ 4_and -x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad13_ net-_x1-pad5_ 3_and -x6 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_x1-pad3_ 5_and -x5 net-_u1-pad4_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad2_ 5_and -x4 net-_u1-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_x1-pad1_ 5_and -x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x11-pad6_ 5_and -x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x10-pad6_ 5_and -x9 net-_u1-pad9_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x12-pad4_ 5_and -x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ 5_and -x12 net-_u19-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad5_ 5_nor -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad7_ 5_nor -a1 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u14-pad1_ u6 -a2 [net-_u1-pad15_ net-_u1-pad1_ ] net-_u18-pad2_ u2 -a3 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u14-pad2_ u7 +x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate +x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate +a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 +a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 -a5 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 -a6 [net-_u1-pad15_ net-_u18-pad2_ ] net-_u18-pad3_ u18 -a7 [net-_u1-pad13_ net-_u3-pad3_ ] net-_u15-pad1_ u8 -a8 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u3-pad3_ u3 -a9 [net-_u3-pad3_ net-_u1-pad14_ ] net-_u15-pad2_ u9 +a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 +a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 -a12 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u12-pad2_ u5 -a13 [net-_u12-pad2_ net-_u1-pad9_ ] net-_u13-pad3_ u13 +a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 -a15 [net-_u1-pad12_ net-_u10-pad2_ ] net-_u10-pad3_ u10 -a16 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u10-pad2_ u4 -a17 [net-_u10-pad2_ net-_u1-pad11_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 * Schematic Name: d_and, NgSpice Name: d_and .model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml index 124a0047..6d8f93b6 100644 --- a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml +++ b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor</field></x1><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x9><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4_and</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor</field></x12><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x13><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/3_and</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib index f1f7990e..6edb5033 100644 --- a/src/SubcircuitLibrary/7485/7485mod-cache.lib +++ b/src/SubcircuitLibrary/7485/7485mod-cache.lib @@ -1,175 +1,175 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0 1250 1300 1600 1300 N
-P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0 1050 1150 1450 1150 N
-P 3 0 1 0 1050 1150 1050 650 1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# c_gate
-#
-DEF c_gate X 0 40 Y Y 1 F N
-F0 "X" 5900 4450 60 H V C CNN
-F1 "c_gate" 5950 4700 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250
-P 2 0 1 0 5550 4850 6100 4850 N
-P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N
-X in1 1 5350 4800 200 R 50 50 1 1 I I
-X in2 2 5350 4700 200 R 50 50 1 1 I I
-X in3 3 5350 4600 200 R 50 50 1 1 I I
-X in4 4 5350 4500 200 R 50 50 1 1 I I
-X in5 5 5350 4400 200 R 50 50 1 1 I I
-X in6 6 5350 4300 200 R 50 50 1 1 I I
-X out 7 6500 4550 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_nand
-#
-DEF d_nand U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nand" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
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-LIBS:texas
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-LIBS:digital-audio
-LIBS:philips
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-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
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-LIBS:eSim_Devices
-LIBS:eSim_Digital
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-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:7485-cache
-EELAYER 25 0
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-Wire Wire Line
- 5950 4850 5100 4850
-Connection ~ 5100 4850
-Wire Wire Line
- 5950 5400 5100 5400
-Connection ~ 5100 5400
-Wire Wire Line
- 5950 5750 5100 5750
-Connection ~ 5100 5750
-Wire Wire Line
- 5950 5000 4800 5000
-Wire Wire Line
- 4800 5000 4800 3550
-Wire Wire Line
- 4800 3550 1050 3550
-Connection ~ 5450 5100
-Wire Wire Line
- 5350 5200 5950 5200
-Connection ~ 5350 4650
-Wire Wire Line
- 5250 5300 5950 5300
-Connection ~ 5250 4750
-Wire Wire Line
- 5950 5950 1800 5950
-Wire Wire Line
- 1800 5950 1800 5100
-Connection ~ 1800 5100
-Wire Wire Line
- 5950 6400 1600 6400
-Wire Wire Line
- 1600 6400 1600 3900
-Connection ~ 1600 3900
-Wire Wire Line
- 5950 6300 5100 6300
-Connection ~ 5100 6300
-Wire Wire Line
- 5350 5550 5950 5550
-Connection ~ 5350 5200
-Wire Wire Line
- 5250 5650 5950 5650
-Connection ~ 5250 5300
-Wire Wire Line
- 3150 5850 5950 5850
-Connection ~ 3150 5250
-Wire Wire Line
- 5250 6100 5950 6100
-Connection ~ 5250 5650
-Wire Wire Line
- 5950 6200 3000 6200
-Wire Wire Line
- 3000 6200 3000 4350
-Wire Wire Line
- 3000 4350 2950 4350
-Connection ~ 2950 4050
-Wire Wire Line
- 8400 3950 5950 3950
-Connection ~ 5950 3950
-Wire Wire Line
- 8400 3750 5100 3750
-Connection ~ 5100 3750
-Wire Wire Line
- 8400 3850 5250 3850
-Connection ~ 5250 3850
-Wire Wire Line
- 8400 4050 5350 4050
-Connection ~ 5350 4050
-Wire Wire Line
- 8400 4150 5450 4150
-Connection ~ 5450 4150
-Wire Wire Line
- 8400 1800 8400 950
-Wire Wire Line
- 8400 950 7350 950
-Wire Wire Line
- 8400 1900 8200 1900
-Wire Wire Line
- 8200 1900 8200 1250
-Wire Wire Line
- 8200 1250 7350 1250
-Wire Wire Line
- 8400 2000 8050 2000
-Wire Wire Line
- 8050 2000 8050 1650
-Wire Wire Line
- 8050 1650 7400 1650
-Wire Wire Line
- 7500 2150 7800 2150
-Wire Wire Line
- 7800 2150 7800 2100
-Wire Wire Line
- 7800 2100 8400 2100
-Wire Wire Line
- 8400 2200 7900 2200
-Wire Wire Line
- 7900 2200 7900 2700
-Wire Wire Line
- 7900 2700 7500 2700
-Wire Wire Line
- 7500 3250 8050 3250
-Wire Wire Line
- 8050 3250 8050 2300
-Wire Wire Line
- 8050 2300 8400 2300
-Wire Wire Line
- 8200 5200 8200 4650
-Wire Wire Line
- 8200 4650 6950 4650
-Wire Wire Line
- 8200 5300 8050 5300
-Wire Wire Line
- 8050 5300 8050 5200
-Wire Wire Line
- 8050 5200 6950 5200
-Wire Wire Line
- 8200 5400 7250 5400
-Wire Wire Line
- 7250 5400 7250 5750
-Wire Wire Line
- 7250 5750 6950 5750
-Wire Wire Line
- 6850 6250 6850 5850
-Wire Wire Line
- 6850 5850 7350 5850
-Wire Wire Line
- 7350 5850 7350 5500
-Wire Wire Line
- 7350 5500 8200 5500
-Wire Wire Line
- 6800 6950 6950 6950
-Wire Wire Line
- 6950 6950 6950 6200
-Wire Wire Line
- 6950 6200 7950 6200
-Wire Wire Line
- 7950 6200 7950 5700
-Wire Wire Line
- 7950 5700 8200 5700
-$Comp
-L PORT U1
-U 4 1 5C9A8539
-P 850 1350
-F 0 "U1" H 900 1450 30 0000 C CNN
-F 1 "PORT" H 850 1350 30 0000 C CNN
-F 2 "" H 850 1350 60 0000 C CNN
-F 3 "" H 850 1350 60 0000 C CNN
- 4 850 1350
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A8668
-P 850 1550
-F 0 "U1" H 900 1650 30 0000 C CNN
-F 1 "PORT" H 850 1550 30 0000 C CNN
-F 2 "" H 850 1550 60 0000 C CNN
-F 3 "" H 850 1550 60 0000 C CNN
- 5 850 1550
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 1100 1550 1100 1450
-$Comp
-L PORT U1
-U 6 1 5C9A8815
-P 950 2650
-F 0 "U1" H 1000 2750 30 0000 C CNN
-F 1 "PORT" H 950 2650 30 0000 C CNN
-F 2 "" H 950 2650 60 0000 C CNN
-F 3 "" H 950 2650 60 0000 C CNN
- 6 950 2650
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 1200 2650 1200 2750
-$Comp
-L PORT U1
-U 7 1 5C9A8B82
-P 950 2850
-F 0 "U1" H 1000 2950 30 0000 C CNN
-F 1 "PORT" H 950 2850 30 0000 C CNN
-F 2 "" H 950 2850 60 0000 C CNN
-F 3 "" H 950 2850 60 0000 C CNN
- 7 950 2850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9A8C46
-P 950 3900
-F 0 "U1" H 1000 4000 30 0000 C CNN
-F 1 "PORT" H 950 3900 30 0000 C CNN
-F 2 "" H 950 3900 60 0000 C CNN
-F 3 "" H 950 3900 60 0000 C CNN
- 8 950 3900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C9A8D2C
-P 950 4100
-F 0 "U1" H 1000 4200 30 0000 C CNN
-F 1 "PORT" H 950 4100 30 0000 C CNN
-F 2 "" H 950 4100 60 0000 C CNN
-F 3 "" H 950 4100 60 0000 C CNN
- 9 950 4100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C9A8DBD
-P 1000 5100
-F 0 "U1" H 1050 5200 30 0000 C CNN
-F 1 "PORT" H 1000 5100 30 0000 C CNN
-F 2 "" H 1000 5100 60 0000 C CNN
-F 3 "" H 1000 5100 60 0000 C CNN
- 10 1000 5100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C9A8E65
-P 1000 5300
-F 0 "U1" H 1050 5400 30 0000 C CNN
-F 1 "PORT" H 1000 5300 30 0000 C CNN
-F 2 "" H 1000 5300 60 0000 C CNN
-F 3 "" H 1000 5300 60 0000 C CNN
- 11 1000 5300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A8EEE
-P 800 3150
-F 0 "U1" H 850 3250 30 0000 C CNN
-F 1 "PORT" H 800 3150 30 0000 C CNN
-F 2 "" H 800 3150 60 0000 C CNN
-F 3 "" H 800 3150 60 0000 C CNN
- 1 800 3150
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A8F9C
-P 800 3400
-F 0 "U1" H 850 3500 30 0000 C CNN
-F 1 "PORT" H 800 3400 30 0000 C CNN
-F 2 "" H 800 3400 60 0000 C CNN
-F 3 "" H 800 3400 60 0000 C CNN
- 2 800 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A9031
-P 800 3600
-F 0 "U1" H 850 3700 30 0000 C CNN
-F 1 "PORT" H 800 3600 30 0000 C CNN
-F 2 "" H 800 3600 60 0000 C CNN
-F 3 "" H 800 3600 60 0000 C CNN
- 3 800 3600
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 1050 3250 1050 3150
-Wire Wire Line
- 1050 3550 1050 3600
-Wire Wire Line
- 1350 4000 1350 4100
-Wire Wire Line
- 1350 4100 1200 4100
-Wire Wire Line
- 9550 2050 9850 2050
-Wire Wire Line
- 9400 3950 9850 3950
-Wire Wire Line
- 9350 5450 9900 5450
-$Comp
-L PORT U1
-U 12 1 5C9A9B26
-P 10100 2050
-F 0 "U1" H 10150 2150 30 0000 C CNN
-F 1 "PORT" H 10100 2050 30 0000 C CNN
-F 2 "" H 10100 2050 60 0000 C CNN
-F 3 "" H 10100 2050 60 0000 C CNN
- 12 10100 2050
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5C9A9BCA
-P 10100 3950
-F 0 "U1" H 10150 4050 30 0000 C CNN
-F 1 "PORT" H 10100 3950 30 0000 C CNN
-F 2 "" H 10100 3950 60 0000 C CNN
-F 3 "" H 10100 3950 60 0000 C CNN
- 13 10100 3950
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C9A9CA0
-P 10150 5450
-F 0 "U1" H 10200 5550 30 0000 C CNN
-F 1 "PORT" H 10150 5450 30 0000 C CNN
-F 2 "" H 10150 5450 60 0000 C CNN
-F 3 "" H 10150 5450 60 0000 C CNN
- 14 10150 5450
- -1 0 0 1
-$EndComp
-Text Notes 9650 2000 0 60 ~ 12
-A>B
-Text Notes 9600 3900 0 60 ~ 12
-A=B\n
-Text Notes 9600 5400 0 60 ~ 12
-A<B\n
-Text Notes 1250 5100 0 60 ~ 12
-A0
-Text Notes 1200 5400 0 60 ~ 12
-B0
-Text Notes 1300 3900 2 60 ~ 12
-A1
-Text Notes 1300 4200 2 60 ~ 12
-B1
-Text Notes 1250 3250 2 60 ~ 12
-A<B
-Text Notes 1250 3400 2 60 ~ 12
-A=B
-Text Notes 1250 3550 2 60 ~ 12
-A>B
-Text Notes 1350 2750 2 60 ~ 12
-A2
-Text Notes 1350 2950 2 60 ~ 12
-B2
-Text Notes 1300 1350 2 60 ~ 12
-A3
-Text Notes 1300 1550 2 60 ~ 12
-B3
-Wire Wire Line
- 8200 5600 7450 5600
-Wire Wire Line
- 7450 5600 7450 6050
-Wire Wire Line
- 7450 6050 6900 6050
-Wire Wire Line
- 6800 6650 6800 6300
-Wire Wire Line
- 6800 6300 6900 6300
-Wire Wire Line
- 6900 6300 6900 6050
-Wire Notes Line
- 500 3000 1350 3000
-Wire Notes Line
- 1350 3000 1350 3750
-Wire Notes Line
- 1350 3750 500 3750
-Wire Notes Line
- 500 3750 500 3000
-Text Notes 600 3000 3 60 ~ 12
-Cascading Inputs
-Wire Notes Line
- 9500 1550 9500 6050
-Wire Notes Line
- 9500 6050 10550 6050
-Wire Notes Line
- 10550 6050 10550 1550
-Wire Notes Line
- 10550 1550 9500 1550
-Text Notes 9900 3400 0 60 ~ 12
-Outputs
-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:7485-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U6 +U 1 1 5C9A2432 +P 3150 1200 +F 0 "U6" H 3150 1200 60 0000 C CNN +F 1 "d_and" H 3200 1300 60 0000 C CNN +F 2 "" H 3150 1200 60 0000 C CNN +F 3 "" H 3150 1200 60 0000 C CNN + 1 3150 1200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U2 +U 1 1 5C9A246F +P 2100 1450 +F 0 "U2" H 2100 1450 60 0000 C CNN +F 1 "d_nand" H 2150 1550 60 0000 C CNN +F 2 "" H 2100 1450 60 0000 C CNN +F 3 "" H 2100 1450 60 0000 C CNN + 1 2100 1450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 5C9A24BA +P 3150 1600 +F 0 "U7" H 3150 1600 60 0000 C CNN +F 1 "d_and" H 3200 1700 60 0000 C CNN +F 2 "" H 3150 1600 60 0000 C CNN +F 3 "" H 3150 1600 60 0000 C CNN + 1 3150 1600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 5C9A252F +P 4050 1400 +F 0 "U14" H 4050 1400 60 0000 C CNN +F 1 "d_nor" H 4100 1500 60 0000 C CNN +F 2 "" H 4050 1400 60 0000 C CNN +F 3 "" H 4050 1400 60 0000 C CNN + 1 4050 1400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 5C9A2580 +P 6900 1000 +F 0 "U19" H 6900 1000 60 0000 C CNN +F 1 "d_and" H 6950 1100 60 0000 C CNN +F 2 "" H 6900 1000 60 0000 C CNN +F 3 "" H 6900 1000 60 0000 C CNN + 1 6900 1000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X12 +U 1 1 5C9A2DC4 +P 6050 1650 +F 0 "X12" H 6950 1950 60 0000 C CNN +F 1 "3_and" H 7000 2150 60 0000 C CNN +F 2 "" H 6050 1650 60 0000 C CNN +F 3 "" H 6050 1650 60 0000 C CNN + 1 6050 1650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 5C9A2EB7 +P 5450 2750 +F 0 "X7" H 6950 3800 60 0000 C CNN +F 1 "4_and" H 7000 3950 60 0000 C CNN +F 2 "" H 5450 2750 60 0000 C CNN +F 3 "" H 5450 2750 60 0000 C CNN + 1 5450 2750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 5C9A2F2E +P 5650 3050 +F 0 "X9" H 7000 3850 60 0000 C CNN +F 1 "5_and" H 7050 4100 60 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 5C9A2F95 +P 5650 3600 +F 0 "X10" H 7000 4400 60 0000 C CNN +F 1 "5_and" H 7050 4650 60 0000 C CNN +F 2 "" H 5650 3600 60 0000 C CNN +F 3 "" H 5650 3600 60 0000 C CNN + 1 5650 3600 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 5C9A3164 +P 5650 4150 +F 0 "X11" H 7000 4950 60 0000 C CNN +F 1 "5_and" H 7050 5200 60 0000 C CNN +F 2 "" H 5650 4150 60 0000 C CNN +F 3 "" H 5650 4150 60 0000 C CNN + 1 5650 4150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 5C9A31B3 +P 7550 4850 +F 0 "X13" H 8900 5650 60 0000 C CNN +F 1 "5_and" H 8950 5900 60 0000 C CNN +F 2 "" H 7550 4850 60 0000 C CNN +F 3 "" H 7550 4850 60 0000 C CNN + 1 7550 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 5C9A32FD +P 6350 6900 +F 0 "U18" H 6350 6900 60 0000 C CNN +F 1 "d_and" H 6400 7000 60 0000 C CNN +F 2 "" H 6350 6900 60 0000 C CNN +F 3 "" H 6350 6900 60 0000 C CNN + 1 6350 6900 + 1 0 0 1 +$EndComp +$Comp +L 3_and X8 +U 1 1 5C9A3303 +P 5500 6250 +F 0 "X8" H 6400 6550 60 0000 C CNN +F 1 "3_and" H 6450 6750 60 0000 C CNN +F 2 "" H 5500 6250 60 0000 C CNN +F 3 "" H 5500 6250 60 0000 C CNN + 1 5500 6250 + 1 0 0 1 +$EndComp +$Comp +L 4_and X3 +U 1 1 5C9A3309 +P 4900 5150 +F 0 "X3" H 6400 6200 60 0000 C CNN +F 1 "4_and" H 6450 6350 60 0000 C CNN +F 2 "" H 4900 5150 60 0000 C CNN +F 3 "" H 4900 5150 60 0000 C CNN + 1 4900 5150 + 1 0 0 1 +$EndComp +$Comp +L 5_and X6 +U 1 1 5C9A330F +P 5100 4850 +F 0 "X6" H 6450 5650 60 0000 C CNN +F 1 "5_and" H 6500 5900 60 0000 C CNN +F 2 "" H 5100 4850 60 0000 C CNN +F 3 "" H 5100 4850 60 0000 C CNN + 1 5100 4850 + 1 0 0 1 +$EndComp +$Comp +L 5_and X5 +U 1 1 5C9A3315 +P 5100 4300 +F 0 "X5" H 6450 5100 60 0000 C CNN +F 1 "5_and" H 6500 5350 60 0000 C CNN +F 2 "" H 5100 4300 60 0000 C CNN +F 3 "" H 5100 4300 60 0000 C CNN + 1 5100 4300 + 1 0 0 1 +$EndComp +$Comp +L 5_and X4 +U 1 1 5C9A331B +P 5100 3750 +F 0 "X4" H 6450 4550 60 0000 C CNN +F 1 "5_and" H 6500 4800 60 0000 C CNN +F 2 "" H 5100 3750 60 0000 C CNN +F 3 "" H 5100 3750 60 0000 C CNN + 1 5100 3750 + 1 0 0 1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A39D8 +P 3250 2600 +F 0 "U8" H 3250 2600 60 0000 C CNN +F 1 "d_and" H 3300 2700 60 0000 C CNN +F 2 "" H 3250 2600 60 0000 C CNN +F 3 "" H 3250 2600 60 0000 C CNN + 1 3250 2600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U3 +U 1 1 5C9A39DE +P 2200 2850 +F 0 "U3" H 2200 2850 60 0000 C CNN +F 1 "d_nand" H 2250 2950 60 0000 C CNN +F 2 "" H 2200 2850 60 0000 C CNN +F 3 "" H 2200 2850 60 0000 C CNN + 1 2200 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 5C9A39E4 +P 3250 3000 +F 0 "U9" H 3250 3000 60 0000 C CNN +F 1 "d_and" H 3300 3100 60 0000 C CNN +F 2 "" H 3250 3000 60 0000 C CNN +F 3 "" H 3250 3000 60 0000 C CNN + 1 3250 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 5C9A39EA +P 4150 2800 +F 0 "U15" H 4150 2800 60 0000 C CNN +F 1 "d_nor" H 4200 2900 60 0000 C CNN +F 2 "" H 4150 2800 60 0000 C CNN +F 3 "" H 4150 2800 60 0000 C CNN + 1 4150 2800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 5C9A3B56 +P 3600 4950 +F 0 "U12" H 3600 4950 60 0000 C CNN +F 1 "d_and" H 3650 5050 60 0000 C CNN +F 2 "" H 3600 4950 60 0000 C CNN +F 3 "" H 3600 4950 60 0000 C CNN + 1 3600 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U5 +U 1 1 5C9A3B5C +P 2550 5200 +F 0 "U5" H 2550 5200 60 0000 C CNN +F 1 "d_nand" H 2600 5300 60 0000 C CNN +F 2 "" H 2550 5200 60 0000 C CNN +F 3 "" H 2550 5200 60 0000 C CNN + 1 2550 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 5C9A3B62 +P 3600 5350 +F 0 "U13" H 3600 5350 60 0000 C CNN +F 1 "d_and" H 3650 5450 60 0000 C CNN +F 2 "" H 3600 5350 60 0000 C CNN +F 3 "" H 3600 5350 60 0000 C CNN + 1 3600 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U17 +U 1 1 5C9A3B68 +P 4500 5150 +F 0 "U17" H 4500 5150 60 0000 C CNN +F 1 "d_nor" H 4550 5250 60 0000 C CNN +F 2 "" H 4500 5150 60 0000 C CNN +F 3 "" H 4500 5150 60 0000 C CNN + 1 4500 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 5C9A3C6D +P 3400 3750 +F 0 "U10" H 3400 3750 60 0000 C CNN +F 1 "d_and" H 3450 3850 60 0000 C CNN +F 2 "" H 3400 3750 60 0000 C CNN +F 3 "" H 3400 3750 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 5C9A3C73 +P 2350 4000 +F 0 "U4" H 2350 4000 60 0000 C CNN +F 1 "d_nand" H 2400 4100 60 0000 C CNN +F 2 "" H 2350 4000 60 0000 C CNN +F 3 "" H 2350 4000 60 0000 C CNN + 1 2350 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 5C9A3C79 +P 3400 4150 +F 0 "U11" H 3400 4150 60 0000 C CNN +F 1 "d_and" H 3450 4250 60 0000 C CNN +F 2 "" H 3400 4150 60 0000 C CNN +F 3 "" H 3400 4150 60 0000 C CNN + 1 3400 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U16 +U 1 1 5C9A3C7F +P 4300 3950 +F 0 "U16" H 4300 3950 60 0000 C CNN +F 1 "d_nor" H 4350 4050 60 0000 C CNN +F 2 "" H 4300 3950 60 0000 C CNN +F 3 "" H 4300 3950 60 0000 C CNN + 1 4300 3950 + 1 0 0 -1 +$EndComp +$Comp +L c_gate X2 +U 1 1 5C9A4498 +P 3050 6600 +F 0 "X2" H 3100 6650 60 0000 C CNN +F 1 "c_gate" H 9000 11300 60 0000 C CNN +F 2 "" H 3050 6600 60 0000 C CNN +F 3 "" H 3050 6600 60 0000 C CNN + 1 3050 6600 + 1 0 0 -1 +$EndComp +$Comp +L c_gate X1 +U 1 1 5C9A465F +P 2850 10000 +F 0 "X1" H 2900 10050 60 0000 C CNN +F 1 "c_gate" H 8800 14700 60 0000 C CNN +F 2 "" H 2850 10000 60 0000 C CNN +F 3 "" H 2850 10000 60 0000 C CNN + 1 2850 10000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 1300 3600 1150 +Wire Wire Line + 3600 1400 3600 1550 +Wire Wire Line + 2700 1000 2700 4700 +Wire Wire Line + 2700 1600 1550 1600 +Wire Wire Line + 1550 1600 1550 1450 +Wire Wire Line + 1100 1450 1650 1450 +Wire Wire Line + 1100 1350 1650 1350 +Wire Wire Line + 1550 1350 1550 1100 +Wire Wire Line + 1550 1100 2700 1100 +Wire Wire Line + 2550 1400 2700 1400 +Connection ~ 2700 1400 +Connection ~ 1550 1350 +Connection ~ 1550 1450 +Wire Wire Line + 3700 2700 3700 2550 +Wire Wire Line + 3700 2800 3700 2950 +Wire Wire Line + 2800 2000 2800 4600 +Wire Wire Line + 2800 3000 1650 3000 +Wire Wire Line + 1650 3000 1650 2850 +Wire Wire Line + 1200 2850 1750 2850 +Wire Wire Line + 1200 2750 1750 2750 +Wire Wire Line + 1650 2750 1650 2500 +Wire Wire Line + 1650 2500 2800 2500 +Wire Wire Line + 2650 2800 2800 2800 +Connection ~ 2800 2800 +Connection ~ 1650 2750 +Connection ~ 1650 2850 +Wire Wire Line + 4050 5050 4050 4900 +Wire Wire Line + 4050 5150 4050 5300 +Wire Wire Line + 3150 4950 3150 5850 +Wire Wire Line + 3150 5350 2000 5350 +Wire Wire Line + 2000 5350 2000 5200 +Wire Wire Line + 1250 5200 2100 5200 +Wire Wire Line + 1250 5100 2100 5100 +Wire Wire Line + 2000 5100 2000 4850 +Wire Wire Line + 2000 4850 3150 4850 +Wire Wire Line + 3000 5150 3150 5150 +Connection ~ 3150 5150 +Connection ~ 2000 5100 +Connection ~ 2000 5200 +Wire Wire Line + 3850 3850 3850 3700 +Wire Wire Line + 3850 3950 3850 4100 +Wire Wire Line + 2950 3200 2950 4350 +Wire Wire Line + 2950 4150 1800 4150 +Wire Wire Line + 1800 4150 1800 4000 +Wire Wire Line + 1350 4000 1900 4000 +Wire Wire Line + 1200 3900 1900 3900 +Wire Wire Line + 1800 3900 1800 3650 +Wire Wire Line + 1800 3650 2950 3650 +Wire Wire Line + 2800 3950 2950 3950 +Connection ~ 2950 3950 +Connection ~ 1800 3900 +Connection ~ 1800 4000 +Wire Wire Line + 1400 1350 1400 7000 +Wire Wire Line + 1400 7000 5900 7000 +Connection ~ 1400 1350 +Wire Wire Line + 1250 5200 1250 5300 +Wire Wire Line + 5900 6900 2900 6900 +Wire Wire Line + 2900 6900 2900 4700 +Wire Wire Line + 2900 4700 2700 4700 +Connection ~ 2700 1500 +Wire Wire Line + 5950 6750 1450 6750 +Wire Wire Line + 1450 6750 1450 2750 +Connection ~ 1450 2750 +Wire Wire Line + 5950 6650 2950 6650 +Wire Wire Line + 2950 6650 2950 4600 +Wire Wire Line + 2950 4600 2800 4600 +Connection ~ 2800 2900 +Wire Wire Line + 5100 6550 5950 6550 +Wire Wire Line + 5100 1350 5100 6550 +Wire Wire Line + 4500 1350 6500 1350 +Wire Wire Line + 1500 1450 1500 900 +Wire Wire Line + 1500 900 6450 900 +Connection ~ 1500 1450 +Wire Wire Line + 2700 1000 6450 1000 +Connection ~ 2700 1200 +Wire Wire Line + 6500 1150 4500 1150 +Wire Wire Line + 4500 1150 4500 1900 +Wire Wire Line + 4500 1900 1600 1900 +Wire Wire Line + 1600 1900 1600 2850 +Connection ~ 1600 2850 +Wire Wire Line + 6500 1250 4550 1250 +Wire Wire Line + 4550 1250 4550 2000 +Wire Wire Line + 4550 2000 2800 2000 +Connection ~ 2800 2600 +Connection ~ 5100 1350 +Wire Wire Line + 6500 1500 4600 1500 +Wire Wire Line + 4600 1500 4600 2100 +Wire Wire Line + 4600 2100 1750 2100 +Wire Wire Line + 1750 2100 1750 4000 +Connection ~ 1750 4000 +Wire Wire Line + 6500 1600 4650 1600 +Wire Wire Line + 4650 1600 4650 3200 +Wire Wire Line + 4650 3200 2950 3200 +Connection ~ 2950 3750 +Wire Wire Line + 6500 1700 5100 1700 +Connection ~ 5100 1700 +Wire Wire Line + 6500 1800 5250 1800 +Wire Wire Line + 5250 1800 5250 6100 +Wire Wire Line + 5250 2750 4600 2750 +Wire Wire Line + 6500 1950 1500 1950 +Wire Wire Line + 1500 1950 1500 5200 +Connection ~ 1500 5200 +Wire Wire Line + 6500 2050 4950 2050 +Wire Wire Line + 4950 2050 4950 4300 +Wire Wire Line + 4950 4300 3150 4300 +Wire Wire Line + 3150 4300 3150 5000 +Connection ~ 3150 5000 +Wire Wire Line + 6500 2150 5100 2150 +Connection ~ 5100 2150 +Wire Wire Line + 6500 2250 5250 2250 +Connection ~ 5250 2250 +Wire Wire Line + 6500 2350 5350 2350 +Wire Wire Line + 5350 2350 5350 5550 +Wire Wire Line + 5350 3900 4750 3900 +Wire Wire Line + 6500 2500 5100 2500 +Connection ~ 5100 2500 +Wire Wire Line + 6500 2600 5250 2600 +Connection ~ 5250 2600 +Wire Wire Line + 6500 2700 5350 2700 +Connection ~ 5350 2700 +Wire Wire Line + 6500 2800 5450 2800 +Wire Wire Line + 5450 2800 5450 5100 +Wire Wire Line + 4950 5100 5950 5100 +Wire Wire Line + 6500 2900 5550 2900 +Wire Wire Line + 5550 2900 5550 3250 +Wire Wire Line + 5550 3250 1050 3250 +Wire Wire Line + 6500 3050 5100 3050 +Connection ~ 5100 3050 +Wire Wire Line + 5250 3150 6500 3150 +Connection ~ 5250 2750 +Wire Wire Line + 6500 3250 5700 3250 +Wire Wire Line + 5700 3250 5700 3200 +Wire Wire Line + 5700 3200 5350 3200 +Connection ~ 5350 3200 +Wire Wire Line + 6500 3350 5450 3350 +Connection ~ 5450 3350 +Wire Wire Line + 4800 3450 6500 3450 +Wire Wire Line + 4800 3450 4800 3400 +Wire Wire Line + 4800 3400 1050 3400 +Wire Wire Line + 5950 3450 5950 4450 +Connection ~ 5950 3450 +Wire Wire Line + 5950 4550 5450 4550 +Connection ~ 5450 4550 +Wire Wire Line + 5350 4650 5950 4650 +Connection ~ 5350 3900 +Wire Wire Line + 5250 4750 5950 4750 +Connection ~ 5250 3150 +Wire Wire Line + 5950 4850 5100 4850 +Connection ~ 5100 4850 +Wire Wire Line + 5950 5400 5100 5400 +Connection ~ 5100 5400 +Wire Wire Line + 5950 5750 5100 5750 +Connection ~ 5100 5750 +Wire Wire Line + 5950 5000 4800 5000 +Wire Wire Line + 4800 5000 4800 3550 +Wire Wire Line + 4800 3550 1050 3550 +Connection ~ 5450 5100 +Wire Wire Line + 5350 5200 5950 5200 +Connection ~ 5350 4650 +Wire Wire Line + 5250 5300 5950 5300 +Connection ~ 5250 4750 +Wire Wire Line + 5950 5950 1800 5950 +Wire Wire Line + 1800 5950 1800 5100 +Connection ~ 1800 5100 +Wire Wire Line + 5950 6400 1600 6400 +Wire Wire Line + 1600 6400 1600 3900 +Connection ~ 1600 3900 +Wire Wire Line + 5950 6300 5100 6300 +Connection ~ 5100 6300 +Wire Wire Line + 5350 5550 5950 5550 +Connection ~ 5350 5200 +Wire Wire Line + 5250 5650 5950 5650 +Connection ~ 5250 5300 +Wire Wire Line + 3150 5850 5950 5850 +Connection ~ 3150 5250 +Wire Wire Line + 5250 6100 5950 6100 +Connection ~ 5250 5650 +Wire Wire Line + 5950 6200 3000 6200 +Wire Wire Line + 3000 6200 3000 4350 +Wire Wire Line + 3000 4350 2950 4350 +Connection ~ 2950 4050 +Wire Wire Line + 8400 3950 5950 3950 +Connection ~ 5950 3950 +Wire Wire Line + 8400 3750 5100 3750 +Connection ~ 5100 3750 +Wire Wire Line + 8400 3850 5250 3850 +Connection ~ 5250 3850 +Wire Wire Line + 8400 4050 5350 4050 +Connection ~ 5350 4050 +Wire Wire Line + 8400 4150 5450 4150 +Connection ~ 5450 4150 +Wire Wire Line + 8400 1800 8400 950 +Wire Wire Line + 8400 950 7350 950 +Wire Wire Line + 8400 1900 8200 1900 +Wire Wire Line + 8200 1900 8200 1250 +Wire Wire Line + 8200 1250 7350 1250 +Wire Wire Line + 8400 2000 8050 2000 +Wire Wire Line + 8050 2000 8050 1650 +Wire Wire Line + 8050 1650 7400 1650 +Wire Wire Line + 7500 2150 7800 2150 +Wire Wire Line + 7800 2150 7800 2100 +Wire Wire Line + 7800 2100 8400 2100 +Wire Wire Line + 8400 2200 7900 2200 +Wire Wire Line + 7900 2200 7900 2700 +Wire Wire Line + 7900 2700 7500 2700 +Wire Wire Line + 7500 3250 8050 3250 +Wire Wire Line + 8050 3250 8050 2300 +Wire Wire Line + 8050 2300 8400 2300 +Wire Wire Line + 8200 5200 8200 4650 +Wire Wire Line + 8200 4650 6950 4650 +Wire Wire Line + 8200 5300 8050 5300 +Wire Wire Line + 8050 5300 8050 5200 +Wire Wire Line + 8050 5200 6950 5200 +Wire Wire Line + 8200 5400 7250 5400 +Wire Wire Line + 7250 5400 7250 5750 +Wire Wire Line + 7250 5750 6950 5750 +Wire Wire Line + 6850 6250 6850 5850 +Wire Wire Line + 6850 5850 7350 5850 +Wire Wire Line + 7350 5850 7350 5500 +Wire Wire Line + 7350 5500 8200 5500 +Wire Wire Line + 6800 6950 6950 6950 +Wire Wire Line + 6950 6950 6950 6200 +Wire Wire Line + 6950 6200 7950 6200 +Wire Wire Line + 7950 6200 7950 5700 +Wire Wire Line + 7950 5700 8200 5700 +$Comp +L PORT U1 +U 4 1 5C9A8539 +P 850 1350 +F 0 "U1" H 900 1450 30 0000 C CNN +F 1 "PORT" H 850 1350 30 0000 C CNN +F 2 "" H 850 1350 60 0000 C CNN +F 3 "" H 850 1350 60 0000 C CNN + 4 850 1350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A8668 +P 850 1550 +F 0 "U1" H 900 1650 30 0000 C CNN +F 1 "PORT" H 850 1550 30 0000 C CNN +F 2 "" H 850 1550 60 0000 C CNN +F 3 "" H 850 1550 60 0000 C CNN + 5 850 1550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 1550 1100 1450 +$Comp +L PORT U1 +U 6 1 5C9A8815 +P 950 2650 +F 0 "U1" H 1000 2750 30 0000 C CNN +F 1 "PORT" H 950 2650 30 0000 C CNN +F 2 "" H 950 2650 60 0000 C CNN +F 3 "" H 950 2650 60 0000 C CNN + 6 950 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 2650 1200 2750 +$Comp +L PORT U1 +U 7 1 5C9A8B82 +P 950 2850 +F 0 "U1" H 1000 2950 30 0000 C CNN +F 1 "PORT" H 950 2850 30 0000 C CNN +F 2 "" H 950 2850 60 0000 C CNN +F 3 "" H 950 2850 60 0000 C CNN + 7 950 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5C9A8C46 +P 950 3900 +F 0 "U1" H 1000 4000 30 0000 C CNN +F 1 "PORT" H 950 3900 30 0000 C CNN +F 2 "" H 950 3900 60 0000 C CNN +F 3 "" H 950 3900 60 0000 C CNN + 8 950 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5C9A8D2C +P 950 4100 +F 0 "U1" H 1000 4200 30 0000 C CNN +F 1 "PORT" H 950 4100 30 0000 C CNN +F 2 "" H 950 4100 60 0000 C CNN +F 3 "" H 950 4100 60 0000 C CNN + 9 950 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5C9A8DBD +P 1000 5100 +F 0 "U1" H 1050 5200 30 0000 C CNN +F 1 "PORT" H 1000 5100 30 0000 C CNN +F 2 "" H 1000 5100 60 0000 C CNN +F 3 "" H 1000 5100 60 0000 C CNN + 10 1000 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5C9A8E65 +P 1000 5300 +F 0 "U1" H 1050 5400 30 0000 C CNN +F 1 "PORT" H 1000 5300 30 0000 C CNN +F 2 "" H 1000 5300 60 0000 C CNN +F 3 "" H 1000 5300 60 0000 C CNN + 11 1000 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A8EEE +P 800 3150 +F 0 "U1" H 850 3250 30 0000 C CNN +F 1 "PORT" H 800 3150 30 0000 C CNN +F 2 "" H 800 3150 60 0000 C CNN +F 3 "" H 800 3150 60 0000 C CNN + 1 800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A8F9C +P 800 3400 +F 0 "U1" H 850 3500 30 0000 C CNN +F 1 "PORT" H 800 3400 30 0000 C CNN +F 2 "" H 800 3400 60 0000 C CNN +F 3 "" H 800 3400 60 0000 C CNN + 2 800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A9031 +P 800 3600 +F 0 "U1" H 850 3700 30 0000 C CNN +F 1 "PORT" H 800 3600 30 0000 C CNN +F 2 "" H 800 3600 60 0000 C CNN +F 3 "" H 800 3600 60 0000 C CNN + 3 800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 3250 1050 3150 +Wire Wire Line + 1050 3550 1050 3600 +Wire Wire Line + 1350 4000 1350 4100 +Wire Wire Line + 1350 4100 1200 4100 +Wire Wire Line + 9550 2050 9850 2050 +Wire Wire Line + 9400 3950 9850 3950 +Wire Wire Line + 9350 5450 9900 5450 +$Comp +L PORT U1 +U 12 1 5C9A9B26 +P 10100 2050 +F 0 "U1" H 10150 2150 30 0000 C CNN +F 1 "PORT" H 10100 2050 30 0000 C CNN +F 2 "" H 10100 2050 60 0000 C CNN +F 3 "" H 10100 2050 60 0000 C CNN + 12 10100 2050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 5C9A9BCA +P 10100 3950 +F 0 "U1" H 10150 4050 30 0000 C CNN +F 1 "PORT" H 10100 3950 30 0000 C CNN +F 2 "" H 10100 3950 60 0000 C CNN +F 3 "" H 10100 3950 60 0000 C CNN + 13 10100 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5C9A9CA0 +P 10150 5450 +F 0 "U1" H 10200 5550 30 0000 C CNN +F 1 "PORT" H 10150 5450 30 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 14 10150 5450 + -1 0 0 1 +$EndComp +Text Notes 9650 2000 0 60 ~ 12 +A>B +Text Notes 9600 3900 0 60 ~ 12 +A=B\n +Text Notes 9600 5400 0 60 ~ 12 +A<B\n +Text Notes 1250 5100 0 60 ~ 12 +A0 +Text Notes 1200 5400 0 60 ~ 12 +B0 +Text Notes 1300 3900 2 60 ~ 12 +A1 +Text Notes 1300 4200 2 60 ~ 12 +B1 +Text Notes 1250 3250 2 60 ~ 12 +A<B +Text Notes 1250 3400 2 60 ~ 12 +A=B +Text Notes 1250 3550 2 60 ~ 12 +A>B +Text Notes 1350 2750 2 60 ~ 12 +A2 +Text Notes 1350 2950 2 60 ~ 12 +B2 +Text Notes 1300 1350 2 60 ~ 12 +A3 +Text Notes 1300 1550 2 60 ~ 12 +B3 +Wire Wire Line + 8200 5600 7450 5600 +Wire Wire Line + 7450 5600 7450 6050 +Wire Wire Line + 7450 6050 6900 6050 +Wire Wire Line + 6800 6650 6800 6300 +Wire Wire Line + 6800 6300 6900 6300 +Wire Wire Line + 6900 6300 6900 6050 +Wire Notes Line + 500 3000 1350 3000 +Wire Notes Line + 1350 3000 1350 3750 +Wire Notes Line + 1350 3750 500 3750 +Wire Notes Line + 500 3750 500 3000 +Text Notes 600 3000 3 60 ~ 12 +Cascading Inputs +Wire Notes Line + 9500 1550 9500 6050 +Wire Notes Line + 9500 6050 10550 6050 +Wire Notes Line + 10550 6050 10550 1550 +Wire Notes Line + 10550 1550 9500 1550 +Text Notes 9900 3400 0 60 ~ 12 +Outputs +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib index e83bf18b..05fb44d7 100644 --- a/src/SubcircuitLibrary/7485/c_gate-cache.lib +++ b/src/SubcircuitLibrary/7485/c_gate-cache.lib @@ -1,95 +1,95 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 1350 800 60 H V C CNN
-F1 "5_and" 1400 1050 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650
-P 2 0 1 0 1050 1150 1450 1150 N
-P 3 0 1 0 1050 1150 1050 650 1450 650 N
-X in1 1 850 1100 200 R 50 50 1 1 I
-X in2 2 850 1000 200 R 50 50 1 1 I
-X in3 3 850 900 200 R 50 50 1 1 I
-X in4 4 850 800 200 R 50 50 1 1 I
-X in5 5 850 700 200 R 50 50 1 1 I
-X out 6 1850 900 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 1350 800 60 H V C CNN +F1 "5_and" 1400 1050 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 +P 2 0 1 0 1050 1150 1450 1150 N +P 3 0 1 0 1050 1150 1050 650 1450 650 N +X in1 1 850 1100 200 R 50 50 1 1 I +X in2 2 850 1000 200 R 50 50 1 1 I +X in3 3 850 900 200 R 50 50 1 1 I +X in4 4 850 800 200 R 50 50 1 1 I +X in5 5 850 700 200 R 50 50 1 1 I +X out 6 1850 900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir index 865e4229..1ac12515 100644 --- a/src/SubcircuitLibrary/7485/c_gate.cir +++ b/src/SubcircuitLibrary/7485/c_gate.cir @@ -1,19 +1,19 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and
-U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and
-U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
-U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter
-U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter
-U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter
-U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter
-U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and +U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT + +.end diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out index 249e9b8f..db7bb2f8 100644 --- a/src/SubcircuitLibrary/7485/c_gate.cir.out +++ b/src/SubcircuitLibrary/7485/c_gate.cir.out @@ -1,42 +1,42 @@ -* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
-
-.include 5_and.sub
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir + +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro index 0ac5f7d7..f0743529 100644 --- a/src/SubcircuitLibrary/7485/c_gate.pro +++ b/src/SubcircuitLibrary/7485/c_gate.pro @@ -1,57 +1,57 @@ -update=03/26/19 19:06:59
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=texas
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
+update=03/26/19 19:06:59 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=texas +LibName2=intel +LibName3=audio +LibName4=interface +LibName5=digital-audio +LibName6=philips +LibName7=display +LibName8=cypress +LibName9=siliconi +LibName10=opto +LibName11=atmel +LibName12=contrib +LibName13=valves +LibName14=eSim_Analog +LibName15=eSim_Devices +LibName16=eSim_Digital +LibName17=eSim_Hybrid +LibName18=eSim_Miscellaneous +LibName19=eSim_Plot +LibName20=eSim_Power +LibName21=eSim_PSpice +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch index 8205ff7f..5d960c8d 100644 --- a/src/SubcircuitLibrary/7485/c_gate.sch +++ b/src/SubcircuitLibrary/7485/c_gate.sch @@ -1,246 +1,246 @@ -EESchema Schematic File Version 2
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:c_gate-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
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-L PORT U1
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-U 3 1 5C9A2FDD
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-U 4 1 5C9A301A
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-L PORT U1
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-U 7 1 5C9A30DD
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-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:c_gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 5C9A2B0B +P 3300 3750 +F 0 "X1" H 4650 4550 60 0000 C CNN +F 1 "5_and" H 4700 4800 60 0000 C CNN +F 2 "" H 3300 3750 60 0000 C CNN +F 3 "" H 3300 3750 60 0000 C CNN + 1 3300 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 5C9A2B3E +P 5600 3300 +F 0 "U8" H 5600 3300 60 0000 C CNN +F 1 "d_and" H 5650 3400 60 0000 C CNN +F 2 "" H 5600 3300 60 0000 C CNN +F 3 "" H 5600 3300 60 0000 C CNN + 1 5600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 3200 5150 2850 +Wire Wire Line + 4150 2650 4150 2350 +Wire Wire Line + 4150 2350 3600 2350 +Wire Wire Line + 4150 2750 4050 2750 +Wire Wire Line + 4050 2750 4050 2550 +Wire Wire Line + 4050 2550 3600 2550 +Wire Wire Line + 4150 2850 3700 2850 +Wire Wire Line + 3700 2850 3700 2750 +Wire Wire Line + 3700 2750 3600 2750 +Wire Wire Line + 4150 2950 3600 2950 +Wire Wire Line + 4150 3050 4150 3150 +Wire Wire Line + 4150 3150 3600 3150 +Wire Wire Line + 5150 3300 3600 3300 +$Comp +L d_inverter U2 +U 1 1 5C9A2CDC +P 3300 2350 +F 0 "U2" H 3300 2250 60 0000 C CNN +F 1 "d_inverter" H 3300 2500 60 0000 C CNN +F 2 "" H 3350 2300 60 0000 C CNN +F 3 "" H 3350 2300 60 0000 C CNN + 1 3300 2350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 5C9A2D06 +P 3300 2550 +F 0 "U3" H 3300 2450 60 0000 C CNN +F 1 "d_inverter" H 3300 2700 60 0000 C CNN +F 2 "" H 3350 2500 60 0000 C CNN +F 3 "" H 3350 2500 60 0000 C CNN + 1 3300 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 5C9A2D26 +P 3300 2750 +F 0 "U4" H 3300 2650 60 0000 C CNN +F 1 "d_inverter" H 3300 2900 60 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3300 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 5C9A2D49 +P 3300 2950 +F 0 "U5" H 3300 2850 60 0000 C CNN +F 1 "d_inverter" H 3300 3100 60 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 1 3300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 5C9A2D73 +P 3300 3150 +F 0 "U6" H 3300 3050 60 0000 C CNN +F 1 "d_inverter" H 3300 3300 60 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 1 3300 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5C9A2D9E +P 3300 3300 +F 0 "U7" H 3300 3200 60 0000 C CNN +F 1 "d_inverter" H 3300 3450 60 0000 C CNN +F 2 "" H 3350 3250 60 0000 C CNN +F 3 "" H 3350 3250 60 0000 C CNN + 1 3300 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3000 2350 2000 2350 +Wire Wire Line + 3000 2550 2000 2550 +Wire Wire Line + 3000 2750 2050 2750 +Wire Wire Line + 3000 2950 2050 2950 +Wire Wire Line + 3000 3150 2050 3150 +Wire Wire Line + 3000 3300 2050 3300 +Wire Wire Line + 6050 3250 6950 3250 +$Comp +L PORT U1 +U 1 1 5C9A2F6F +P 1750 2350 +F 0 "U1" H 1800 2450 30 0000 C CNN +F 1 "PORT" H 1750 2350 30 0000 C CNN +F 2 "" H 1750 2350 60 0000 C CNN +F 3 "" H 1750 2350 60 0000 C CNN + 1 1750 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A2FAB +P 1750 2550 +F 0 "U1" H 1800 2650 30 0000 C CNN +F 1 "PORT" H 1750 2550 30 0000 C CNN +F 2 "" H 1750 2550 60 0000 C CNN +F 3 "" H 1750 2550 60 0000 C CNN + 2 1750 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2FDD +P 1800 2750 +F 0 "U1" H 1850 2850 30 0000 C CNN +F 1 "PORT" H 1800 2750 30 0000 C CNN +F 2 "" H 1800 2750 60 0000 C CNN +F 3 "" H 1800 2750 60 0000 C CNN + 3 1800 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A301A +P 1800 2950 +F 0 "U1" H 1850 3050 30 0000 C CNN +F 1 "PORT" H 1800 2950 30 0000 C CNN +F 2 "" H 1800 2950 60 0000 C CNN +F 3 "" H 1800 2950 60 0000 C CNN + 4 1800 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A3052 +P 1800 3150 +F 0 "U1" H 1850 3250 30 0000 C CNN +F 1 "PORT" H 1800 3150 30 0000 C CNN +F 2 "" H 1800 3150 60 0000 C CNN +F 3 "" H 1800 3150 60 0000 C CNN + 5 1800 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A308D +P 1800 3300 +F 0 "U1" H 1850 3400 30 0000 C CNN +F 1 "PORT" H 1800 3300 30 0000 C CNN +F 2 "" H 1800 3300 60 0000 C CNN +F 3 "" H 1800 3300 60 0000 C CNN + 6 1800 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5C9A30DD +P 7200 3250 +F 0 "U1" H 7250 3350 30 0000 C CNN +F 1 "PORT" H 7200 3250 30 0000 C CNN +F 2 "" H 7200 3250 60 0000 C CNN +F 3 "" H 7200 3250 60 0000 C CNN + 7 7200 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub index e7138794..c6eaa478 100644 --- a/src/SubcircuitLibrary/7485/c_gate.sub +++ b/src/SubcircuitLibrary/7485/c_gate.sub @@ -1,36 +1,36 @@ -* Subcircuit c_gate
-.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
-* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir
-.include 5_and.sub
-x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and
-* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
-* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter
-* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter
-* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter
-* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter
-a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 net-_u1-pad2_ net-_u3-pad2_ u3
-a4 net-_u1-pad3_ net-_u4-pad2_ u4
-a5 net-_u1-pad4_ net-_u5-pad2_ u5
-a6 net-_u1-pad5_ net-_u6-pad2_ u6
-a7 net-_u1-pad6_ net-_u7-pad2_ u7
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit c_gate +.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ +* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir +.include 5_and.sub +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and +* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter +a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u4-pad2_ u4 +a5 net-_u1-pad4_ net-_u5-pad2_ u5 +a6 net-_u1-pad5_ net-_u6-pad2_ u6 +a7 net-_u1-pad6_ net-_u7-pad2_ u7 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends c_gate
\ No newline at end of file diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib b/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro b/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro new file mode 100644 index 00000000..b3f410b6 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro @@ -0,0 +1,73 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml b/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/src/SubcircuitLibrary/INVCMOS/analysis b/src/SubcircuitLibrary/INVCMOS/analysis new file mode 100644 index 00000000..334c5333 --- /dev/null +++ b/src/SubcircuitLibrary/INVCMOS/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib new file mode 100644 index 00000000..c02b3211 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib @@ -0,0 +1,135 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib new file mode 100644 index 00000000..e6cfa7d6 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-LM7812 +# +DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-LM7812 +# +DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir b/src/SubcircuitLibrary/LM7812/LM7812.cir new file mode 100644 index 00000000..3f0d3adf --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.cir @@ -0,0 +1,51 @@ +* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir.out b/src/SubcircuitLibrary/LM7812/LM7812.cir.out new file mode 100644 index 00000000..73404965 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.cir.out @@ -0,0 +1,60 @@ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/LM7812/LM7812.pro b/src/SubcircuitLibrary/LM7812/LM7812.pro new file mode 100644 index 00000000..12d08139 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.pro @@ -0,0 +1,46 @@ +update=Mon Aug 26 14:09:03 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=LM7812-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User + diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sch b/src/SubcircuitLibrary/LM7812/LM7812.sch new file mode 100644 index 00000000..ca95c2ca --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.sch @@ -0,0 +1,758 @@ +EESchema Schematic File Version 2 +LIBS:LM7812-rescue +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:LM7812-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN-RESCUE-LM7812 Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP-RESCUE-LM7812 Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP-RESCUE-LM7812 Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN-RESCUE-LM7812 Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP-RESCUE-LM7812 Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN-RESCUE-LM7812 Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "10.38k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN-RESCUE-LM7812 Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN-RESCUE-LM7812 Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sub b/src/SubcircuitLibrary/LM7812/LM7812.sub new file mode 100644 index 00000000..0dd95154 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812.sub @@ -0,0 +1,54 @@ +* Subcircuit LM7812 +.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends LM7812
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml new file mode 100644 index 00000000..263f360c --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/NPN.lib b/src/SubcircuitLibrary/LM7812/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/PNP.lib b/src/SubcircuitLibrary/LM7812/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/Q_PNP.lib b/src/SubcircuitLibrary/LM7812/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/analysis b/src/SubcircuitLibrary/LM7812/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/LM7812/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_adder/full_adder.pro b/src/SubcircuitLibrary/full_adder/full_adder.pro index 0bd0d5af..c0db0775 100644 --- a/src/SubcircuitLibrary/full_adder/full_adder.pro +++ b/src/SubcircuitLibrary/full_adder/full_adder.pro @@ -61,9 +61,9 @@ LibName27=opto LibName28=atmel LibName29=contrib LibName30=valves -LibName31=eSim_Analog -LibName32=eSim_Devices -LibName33=eSim_Digital -LibName34=eSim_Hybrid -LibName35=eSim_Sources -LibName36=eSim_Subckt +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_adder/half_adder.pro b/src/SubcircuitLibrary/full_adder/half_adder.pro index 30094fb9..695ae0f6 100644 --- a/src/SubcircuitLibrary/full_adder/half_adder.pro +++ b/src/SubcircuitLibrary/full_adder/half_adder.pro @@ -61,9 +61,9 @@ LibName27=opto LibName28=atmel LibName29=contrib LibName30=valves -LibName31=eSim_Analog -LibName32=eSim_Devices -LibName33=eSim_Digital -LibName34=eSim_Hybrid -LibName35=eSim_Sources -LibName36=eSim_Subckt +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib index f874f5e2..6949ac1a 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib +++ b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib @@ -1,79 +1,79 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# half_sub
-#
-DEF half_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -300 300 300 -300 0 1 0 N
-X A 1 -500 200 200 R 50 50 1 1 I
-X B 2 -500 -100 200 R 50 50 1 1 I
-X D 3 500 150 200 L 50 50 1 1 O
-X BORROW 4 500 -100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib index 416747ef..803b5ece 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib +++ b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib @@ -1,20 +1,20 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# half_sub-RESCUE-full_sub
-#
-DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -1450 850 1550 -1050 0 1 0 N
-X A 1 -1100 850 200 R 50 50 1 1 I
-X B 2 -350 850 200 R 50 50 1 1 I
-X D 3 -800 -1050 200 L 50 50 1 1 O
-X BORROW 4 0 -1050 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# half_sub-RESCUE-full_sub +# +DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1450 850 1550 -1050 0 1 0 N +X A 1 -1100 850 200 R 50 50 1 1 I +X B 2 -350 850 200 R 50 50 1 1 I +X D 3 -800 -1050 200 L 50 50 1 1 O +X BORROW 4 0 -1050 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir index 7d6f198f..67359421 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub.cir +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir @@ -1,14 +1,14 @@ -* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or
-U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT
-X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub
-X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub
-
-.end
+* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT +X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub +X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub + +.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out index e310dcd0..5e58cc0a 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub.cir.out +++ b/src/SubcircuitLibrary/full_sub/full_sub.cir.out @@ -1,19 +1,19 @@ -* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-
-.include half_sub.sub
-* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir + +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro index 3336e88e..1a0c3543 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub.pro +++ b/src/SubcircuitLibrary/full_sub/full_sub.pro @@ -1,74 +1,74 @@ -update=03/07/19 10:55:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=full_sub-rescue
-LibName2=adc-dac
-LibName3=memory
-LibName4=xilinx
-LibName5=microcontrollers
-LibName6=dsp
-LibName7=microchip
-LibName8=analog_switches
-LibName9=motorola
-LibName10=texas
-LibName11=intel
-LibName12=audio
-LibName13=interface
-LibName14=digital-audio
-LibName15=philips
-LibName16=display
-LibName17=cypress
-LibName18=siliconi
-LibName19=opto
-LibName20=atmel
-LibName21=contrib
-LibName22=power
-LibName23=device
-LibName24=transistors
-LibName25=conn
-LibName26=linear
-LibName27=regul
-LibName28=74xx
-LibName29=cmos4000
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Power
-LibName36=eSim_Sources
-LibName37=eSim_Subckt
-LibName38=eSim_User
-LibName39=eSim_Plot
-LibName40=eSim_PSpice
-
+update=03/07/19 10:55:03 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=full_sub-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=device +LibName24=transistors +LibName25=conn +LibName26=linear +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_User +LibName39=eSim_Plot +LibName40=eSim_PSpice + diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch index ed8ac50d..99ca85e5 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub.sch +++ b/src/SubcircuitLibrary/full_sub/full_sub.sch @@ -1,211 +1,211 @@ -EESchema Schematic File Version 2
-LIBS:full_sub-rescue
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:eSim_Plot
-LIBS:eSim_PSpice
-LIBS:full_sub-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
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-$EndComp
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- 2 1200 3650
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-L PORT U5
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-Wire Wire Line
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-L half_sub X2
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-$EndSCHEMATC
+EESchema Schematic File Version 2 +LIBS:full_sub-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:full_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U3 +U 1 1 5C80734A +P 9350 4050 +F 0 "U3" H 9350 4050 60 0000 C CNN +F 1 "d_or" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4050 60 0000 C CNN +F 3 "" H 9350 4050 60 0000 C CNN + 1 9350 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 3600 5800 3600 +Wire Wire Line + 4650 2800 8600 2800 +Wire Wire Line + 8600 2800 8600 3950 +Wire Wire Line + 8600 3950 8900 3950 +Wire Wire Line + 8100 4450 8650 4450 +Wire Wire Line + 8650 4450 8650 4050 +Wire Wire Line + 8650 4050 8900 4050 +Wire Wire Line + 2800 3450 2800 3250 +Wire Wire Line + 2800 3250 3300 3250 +Wire Wire Line + 1450 3550 3300 3550 +Wire Wire Line + 4050 5100 5200 5100 +Wire Wire Line + 5800 3600 5800 5250 +Wire Wire Line + 8250 5250 9350 5250 +Wire Wire Line + 9350 5250 9350 4900 +Wire Wire Line + 9350 4900 10750 4900 +Wire Wire Line + 9800 4000 9800 4600 +Wire Wire Line + 9800 4600 9550 4600 +Wire Wire Line + 9550 4600 9550 4800 +Wire Wire Line + 9550 4800 10750 4800 +$Comp +L PORT U5 +U 1 1 5C80A4E8 +P 1200 3450 +F 0 "U5" H 1250 3550 30 0000 C CNN +F 1 "PORT" H 1200 3450 30 0000 C CNN +F 2 "" H 1200 3450 60 0000 C CNN +F 3 "" H 1200 3450 60 0000 C CNN + 1 1200 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 2 1 5C80A51E +P 1200 3650 +F 0 "U5" H 1250 3750 30 0000 C CNN +F 1 "PORT" H 1200 3650 30 0000 C CNN +F 2 "" H 1200 3650 60 0000 C CNN +F 3 "" H 1200 3650 60 0000 C CNN + 2 1200 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 3 1 5C80A54E +P 3800 5100 +F 0 "U5" H 3850 5200 30 0000 C CNN +F 1 "PORT" H 3800 5100 30 0000 C CNN +F 2 "" H 3800 5100 60 0000 C CNN +F 3 "" H 3800 5100 60 0000 C CNN + 3 3800 5100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U5 +U 5 1 5C80A828 +P 11000 4800 +F 0 "U5" H 11050 4900 30 0000 C CNN +F 1 "PORT" H 11000 4800 30 0000 C CNN +F 2 "" H 11000 4800 60 0000 C CNN +F 3 "" H 11000 4800 60 0000 C CNN + 5 11000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 4 1 5C80AB2A +P 11000 4950 +F 0 "U5" H 11050 5050 30 0000 C CNN +F 1 "PORT" H 11000 4950 30 0000 C CNN +F 2 "" H 11000 4950 60 0000 C CNN +F 3 "" H 11000 4950 60 0000 C CNN + 4 11000 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 3450 2800 3450 +Wire Wire Line + 1450 3650 1450 3550 +Wire Wire Line + 10750 4900 10750 4950 +$Comp +L half_sub X1 +U 1 1 5C80AC4D +P 3800 3450 +F 0 "X1" H 3800 3450 60 0000 C CNN +F 1 "half_sub" H 3800 3450 60 0000 C CNN +F 2 "" H 3800 3450 60 0001 C CNN +F 3 "" H 3800 3450 60 0001 C CNN + 1 3800 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3550 4650 3550 +Wire Wire Line + 4650 3550 4650 2800 +Wire Wire Line + 4300 3300 4850 3300 +Wire Wire Line + 4850 3300 4850 3600 +$Comp +L half_sub X2 +U 1 1 5C80AD72 +P 7300 5150 +F 0 "X2" H 7300 5150 60 0000 C CNN +F 1 "half_sub" H 7300 5150 60 0000 C CNN +F 2 "" H 7300 5150 60 0001 C CNN +F 3 "" H 7300 5150 60 0001 C CNN + 1 7300 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 5250 6800 5250 +Wire Wire Line + 5200 5100 5200 4950 +Wire Wire Line + 5200 4950 6800 4950 +Wire Wire Line + 7800 5000 8250 5000 +Wire Wire Line + 8250 5000 8250 5250 +Wire Wire Line + 7800 5250 8100 5250 +Wire Wire Line + 8100 5250 8100 4450 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub index ec5698b5..9c9dcc5a 100644 --- a/src/SubcircuitLibrary/full_sub/full_sub.sub +++ b/src/SubcircuitLibrary/full_sub/full_sub.sub @@ -1,13 +1,13 @@ -* Subcircuit full_sub
-.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_
-* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir
-.include half_sub.sub
-* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or
-x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub
-x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub
-a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit full_sub +.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ +* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir +.include half_sub.sub +* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or +x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub +x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub +a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends full_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out index 95e6e2bd..91816956 100644 --- a/src/SubcircuitLibrary/full_sub/half_sub.cir.out +++ b/src/SubcircuitLibrary/full_sub/half_sub.cir.out @@ -1,24 +1,24 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub index 1931f76e..a61a3409 100644 --- a/src/SubcircuitLibrary/full_sub/half_sub.sub +++ b/src/SubcircuitLibrary/full_sub/half_sub.sub @@ -1,18 +1,18 @@ -* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends half_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/half_adder/half_adder.pro b/src/SubcircuitLibrary/half_adder/half_adder.pro index 30094fb9..695ae0f6 100644 --- a/src/SubcircuitLibrary/half_adder/half_adder.pro +++ b/src/SubcircuitLibrary/half_adder/half_adder.pro @@ -61,9 +61,9 @@ LibName27=opto LibName28=atmel LibName29=contrib LibName30=valves -LibName31=eSim_Analog -LibName32=eSim_Devices -LibName33=eSim_Digital -LibName34=eSim_Hybrid -LibName35=eSim_Sources -LibName36=eSim_Subckt +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir.out b/src/SubcircuitLibrary/half_sub/half_sub.cir.out index 95e6e2bd..91816956 100644 --- a/src/SubcircuitLibrary/half_sub/half_sub.cir.out +++ b/src/SubcircuitLibrary/half_sub/half_sub.cir.out @@ -1,24 +1,24 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir + +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sub b/src/SubcircuitLibrary/half_sub/half_sub.sub index 1931f76e..a61a3409 100644 --- a/src/SubcircuitLibrary/half_sub/half_sub.sub +++ b/src/SubcircuitLibrary/half_sub/half_sub.sub @@ -1,18 +1,18 @@ -* Subcircuit half_sub
-.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3
-a2 net-_u1-pad1_ net-_u2-pad2_ u2
-a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit half_sub +.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir +* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + .ends half_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/NPN.lib b/src/SubcircuitLibrary/lm555n/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis index 31bc5ccd..a0953567 100644 --- a/src/SubcircuitLibrary/lm555n/analysis +++ b/src/SubcircuitLibrary/lm555n/analysis @@ -1 +1 @@ -.ac oct 897897 kjadsfhHz jhdsakjHz
\ No newline at end of file +.tran 10e-03 100e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib index 421c1147..824af11e 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib +++ b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib @@ -1,147 +1,26 @@ -EESchema-LIBRARY Version 2.3 Date: Monday 17 December 2012 11:00:43 AM IST +EESchema-LIBRARY Version 2.3 #encoding utf-8 # -# ADC8 +# GND-RESCUE-lm555n # -DEF ADC8 U 0 10 Y Y 8 L N -F0 "U" -100 100 40 H V C CNN -F1 "ADC8" 0 0 40 H V C CNN -DRAW -S -150 50 150 -50 0 1 0 N -X in1 1 -300 0 150 R 25 25 1 1 I -X out1 9 300 0 150 L 25 25 1 1 O -X in2 2 -300 0 150 R 25 25 2 1 I -X out2 10 300 0 150 L 25 25 2 1 O -X in3 3 -300 0 150 R 25 25 3 1 I -X out3 11 300 0 150 L 25 25 3 1 O -X in4 4 -300 0 150 R 25 25 4 1 I -X out4 12 300 0 150 L 25 25 4 1 O -X in5 5 -300 0 150 R 25 25 5 1 I -X out5 13 300 0 150 L 25 25 5 1 O -X in6 6 -300 0 150 R 25 25 6 1 I -X out6 14 300 0 150 L 25 25 6 1 O -X in7 7 -300 0 150 R 25 25 7 1 I -X out7 15 300 0 150 L 25 25 7 1 O -X in8 8 -300 0 150 R 25 25 8 1 I -X out8 16 300 0 150 L 25 25 8 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" -150 100 40 H V C CNN -F1 "d_inverter" 100 100 40 H V C CNN -DRAW -P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N -X in 1 -250 0 150 R 25 25 1 1 I -X out 2 250 0 150 L 25 25 1 1 O I -ENDDRAW -ENDDEF -# -# D_SRLatch -# -DEF D_SRLatch U 0 40 Y Y 1 F N -F0 "U" -200 250 60 H V C CNN -F1 "D_SRLatch" 0 100 60 H V C CNN -DRAW -S -300 200 300 -200 0 1 0 N -X S 1 -600 150 300 R 50 50 1 1 I -X R 2 -600 -150 300 R 50 50 1 1 I -X Enable 3 -600 0 300 R 50 50 1 1 I -X Set 4 150 -500 300 U 50 50 1 1 I -X Reset 5 -150 -500 300 U 50 50 1 1 I -X Q 6 600 150 300 L 50 50 1 1 O -X ~Q 7 600 -150 300 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# DAC8 -# -DEF DAC8 U 0 10 Y Y 8 L N -F0 "U" -100 100 40 H V C CNN -F1 "DAC8" 0 0 40 H V C CNN -DRAW -S -150 50 150 -50 0 1 0 N -X in1 1 -300 0 150 R 25 25 1 1 I -X out1 9 300 0 150 L 25 25 1 1 O -X in2 2 -300 0 150 R 25 25 2 1 I -X out2 10 300 0 150 L 25 25 2 1 O -X in3 3 -300 0 150 R 25 25 3 1 I -X out3 11 300 0 150 L 25 25 3 1 O -X in4 4 -300 0 150 R 25 25 4 1 I -X out4 12 300 0 150 L 25 25 4 1 O -X in5 5 -300 0 150 R 25 25 5 1 I -X out5 13 300 0 150 L 25 25 5 1 O -X in6 6 -300 0 150 R 25 25 6 1 I -X out6 14 300 0 150 L 25 25 6 1 O -X in7 7 -300 0 150 R 25 25 7 1 I -X out7 15 300 0 150 L 25 25 7 1 O -X in8 8 -300 0 150 R 25 25 8 1 I -X out8 16 300 0 150 L 25 25 8 1 O -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N X GND 1 0 0 0 U 30 30 1 1 W N ENDDRAW ENDDEF # -# LIMIT8 -# -DEF LIMIT8 U 0 40 Y Y 8 F N -F0 "U" 0 100 30 H V C CNN -F1 "LIMIT8" 0 0 30 H V C CNN -DRAW -S -150 50 150 -50 0 1 0 N -X in 1 -300 0 150 R 25 25 1 1 I -X out 9 300 0 150 L 25 25 1 1 O -X in 2 -300 0 150 R 25 25 2 1 I -X out 10 300 0 150 L 25 25 2 1 O -X in 3 -300 0 150 R 25 25 3 1 I -X out 11 300 0 150 L 25 25 3 1 O -X in 4 -300 0 150 R 25 25 4 1 I -X out 12 300 0 150 L 25 25 4 1 O -X in 5 -300 0 150 R 25 25 5 1 I -X out 13 300 0 150 L 25 25 5 1 O -X in 6 -300 0 150 R 25 25 6 1 I -X out 14 300 0 150 L 25 25 6 1 O -X in 7 -300 0 150 R 25 25 7 1 I -X out 15 300 0 150 L 25 25 7 1 O -X in 8 -300 0 150 R 25 25 8 1 I -X out 16 300 0 150 L 25 25 8 1 O -ENDDRAW -ENDDEF -# -# NPN -# -DEF NPN Q 0 0 Y Y 1 F N -F0 "Q" 0 -150 50 H V R CNN -F1 "NPN" 0 150 50 H V R CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 0 0 100 100 N -P 3 0 1 10 0 75 0 -75 0 -75 N -P 3 0 1 0 50 -50 0 0 0 0 N -P 3 0 1 0 90 -90 100 -100 100 -100 N -P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F -X E 1 100 -200 100 U 40 40 1 1 P -X B 2 -200 0 200 R 40 40 1 1 I -X C 3 100 200 100 D 40 40 1 1 P -ENDDRAW -ENDDEF -# # PORT # -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 0 -50 30 H V C CNN +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN DRAW A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 @@ -154,26 +33,47 @@ X ~ 5 250 0 100 L 30 30 5 1 B X ~ 6 250 0 100 L 30 30 6 1 B X ~ 7 250 0 100 L 30 30 7 1 B X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B ENDDRAW ENDDEF # # PWR_FLAG # DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N ENDDRAW ENDDEF # -# R +# R-RESCUE-lm555n # -DEF R R 0 0 N Y 1 F N +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN $FPLIST R? SM0603 @@ -190,8 +90,10 @@ ENDDEF # VCVS # DEF VCVS E 0 40 Y Y 1 F N -F0 "E" -200 100 50 H V C CNN +F0 "E" 0 150 50 H V C CNN F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN $FPLIST 1_pin $ENDFPLIST @@ -204,4 +106,100 @@ X -c 4 50 -200 100 U 35 35 1 1 P ENDDRAW ENDDEF # +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# #End Library diff --git a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib index 2ed63bd8..fffeca36 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib +++ b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib @@ -1,36 +1,17 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # -# GND-RESCUE-lm555n +# d_inverter-RESCUE-lm555n # -DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# R-RESCUE-lm555n -# -DEF R-RESCUE-lm555n R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I ENDDRAW ENDDEF # diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir index 144b7152..682d4945 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.cir +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir @@ -1,25 +1,31 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:00:36 AM IST +* /home/ash98/Downloads/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 -*Sheet Name:/ -U5 5 21 D_INVERTER -U6 1 4 5 21 21 8 10 D_SRLATCH -E2 18 0 23 14 10000 -U4 19 20 11 12 LIMIT8 -U3 8 10 7 9 DAC8 -U2 11 12 6 4 1 5 ADC8 -U1 22 14 7 6 15 16 3 13 PORT -R8 9 2 1500 -Q1 22 2 3 QNOM -R7 18 20 25 -R6 17 19 25 -E1 17 0 16 15 10000 -R4 16 15 2E6 -R5 23 14 2E6 -R3 23 22 5000 -R2 15 23 5000 -R1 13 15 5000 +* Sheet Name: / +E2 Net-_E2-Pad1_ GND /c /d 10000 +U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad3_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 +U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit +U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit +U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN .end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out index f45920fd..a81070a1 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -1,5 +1,5 @@ * eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist - +.include npn_1.lib * Inverter d_inverter * SR Latch d_srlatch e2 18 0 23 14 10000 @@ -8,7 +8,7 @@ e2 18 0 23 14 10000 * Analog to Digital converter adc8 u1 22 14 7 6 15 16 3 13 port r8 9 2 1500 -q1 3 2 22 qnom +q1 3 2 22 npn_1 r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -33,3 +33,10 @@ a7 [11] [4] u2 a8 [12] [1] u2 a9 [6] [5] u2 .model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro index 1a966cc5..0a5408b6 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.pro +++ b/src/SubcircuitLibrary/lm555n/lm555n.pro @@ -1,8 +1,8 @@ -update=Thu May 19 16:58:03 2016 +update=Tue Apr 2 17:35:59 2019 last_client=eeschema [eeschema] version=1 -LibDir= +LibDir=/home/yogesh/FreeEDA/library [eeschema/libraries] LibName1=lm555n-rescue LibName2=power @@ -44,3 +44,14 @@ LibName37=measurementSpice LibName38=portSpice LibName39=sourcesSpice LibName40=digitalXSpice +LibName41=eSim_User +LibName42=eSim_Subckt +LibName43=eSim_Sources +LibName44=eSim_PSpice +LibName45=eSim_Power +LibName46=eSim_Plot +LibName47=eSim_Miscellaneous +LibName48=eSim_Hybrid +LibName49=eSim_Digital +LibName50=eSim_Devices +LibName51=eSim_Analog diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch index 417063b1..28110b13 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.sch +++ b/src/SubcircuitLibrary/lm555n/lm555n.sch @@ -1,4 +1,5 @@ -EESchema Schematic File Version 2 date Monday 17 December 2012 11:00:43 AM IST +EESchema Schematic File Version 2 +LIBS:lm555n-rescue LIBS:power LIBS:device LIBS:transistors @@ -10,7 +11,6 @@ LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx -LIBS:special LIBS:microcontrollers LIBS:dsp LIBS:microchip @@ -29,19 +29,21 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves -LIBS:analogSpice -LIBS:analogXSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:digitalXSpice +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog LIBS:lm555n-cache -EELAYER 25 0 +EELAYER 25 0 EELAYER END -$Descr A4 11700 8267 +$Descr A4 11693 8268 encoding utf-8 Sheet 1 1 Title "" @@ -53,383 +55,464 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -$Comp -L D_INVERTER U5 -U 1 1 50CEA9C5 -P 6700 4050 -F 0 "U5" H 6550 4150 40 0000 C CNN -F 1 "D_INVERTER" H 6800 4150 40 0000 C CNN - 1 6700 4050 - 1 0 0 -1 -$EndComp -$Comp -L D_SRLATCH U6 -U 1 1 50CEA9AE -P 7100 3400 -F 0 "U6" H 6900 3650 60 0000 C CNN -F 1 "D_SRLATCH" H 7100 3500 60 0000 C CNN - 1 7100 3400 - 1 0 0 -1 -$EndComp -Text Notes 5750 3050 0 60 ~ 0 +Text Notes 3700 3050 0 60 ~ 0 IC 555 Wire Wire Line - 4700 3000 4900 3000 -Wire Wire Line - 4700 4750 4700 4650 -Connection ~ 4400 3550 -Connection ~ 4400 4900 -Wire Wire Line - 4300 4900 7700 4900 -Wire Wire Line - 4400 4200 4400 4100 -Wire Wire Line - 7700 4900 7700 4800 -Wire Wire Line - 7700 3250 7850 3250 -Wire Wire Line - 7400 4600 7100 4600 -Wire Wire Line - 7100 4600 7100 4250 + 2650 3000 2850 3000 Wire Wire Line - 7700 3650 7700 3550 + 2650 4750 2650 4650 +Connection ~ 2350 3550 +Connection ~ 2350 4900 Wire Wire Line - 6350 4050 6450 4050 + 2350 4100 2350 4200 Wire Wire Line - 6950 3900 6950 4000 + 9100 4900 9100 4800 Wire Wire Line - 7150 4000 7150 4050 + 8500 4600 8500 4250 Wire Wire Line - 7150 4050 6950 4050 + 3350 3250 3050 3250 Wire Wire Line - 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1 7350 4250 +P 8750 4250 +F 0 "R8" V 8830 4250 50 0000 C CNN +F 1 "1500" V 8750 4250 50 0000 C CNN +F 2 "" H 8750 4250 60 0001 C CNN +F 3 "" H 8750 4250 60 0001 C CNN + 1 8750 4250 0 1 1 0 $EndComp $Comp -L NPN Q1 -U 1 1 50AA2050 -P 7600 4600 -F 0 "Q1" H 7600 4450 50 0000 R CNN -F 1 "QNOM" H 7600 4750 50 0000 R CNN - 1 7600 4600 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR02 +L GND-RESCUE-lm555n #PWR02 U 1 1 50AA140C -P 5550 4500 -F 0 "#PWR02" H 5550 4500 30 0001 C CNN -F 1 "GND" H 5550 4430 30 0001 C CNN - 1 5550 4500 +P 3500 4500 +F 0 "#PWR02" H 3500 4500 30 0001 C CNN +F 1 "GND" H 3500 4430 30 0001 C CNN +F 2 "" H 3500 4500 60 0001 C CNN +F 3 "" H 3500 4500 60 0001 C CNN + 1 3500 4500 1 0 0 -1 $EndComp -Text Label 4850 4000 0 60 ~ 0 +Text Label 2800 4000 0 60 ~ 0 c -Text Label 4700 4650 0 60 ~ 0 +Text Label 2650 4650 0 60 ~ 0 d -Text Label 4700 4150 0 60 ~ 0 +Text Label 2650 4150 0 60 ~ 0 c $Comp -L R R7 +L R-RESCUE-lm555n R7 U 1 1 50AA12F7 -P 5650 3250 -F 0 "R7" V 5730 3250 50 0000 C CNN -F 1 "25" V 5650 3250 50 0000 C CNN - 1 5650 3250 +P 3600 3250 +F 0 "R7" V 3680 3250 50 0000 C CNN +F 1 "25" V 3600 3250 50 0000 C CNN +F 2 "" H 3600 3250 60 0001 C CNN +F 3 "" H 3600 3250 60 0001 C CNN + 1 3600 3250 0 -1 -1 0 $EndComp $Comp -L R R6 +L R-RESCUE-lm555n R6 U 1 1 50AA12B0 -P 5450 3550 -F 0 "R6" V 5530 3550 50 0000 C CNN -F 1 "25" V 5450 3550 50 0000 C CNN - 1 5450 3550 +P 3400 3550 +F 0 "R6" V 3480 3550 50 0000 C CNN +F 1 "25" V 3400 3550 50 0000 C CNN +F 2 "" H 3400 3550 60 0001 C CNN +F 3 "" H 3400 3550 60 0001 C CNN + 1 3400 3550 0 -1 -1 0 $EndComp -Text Label 5300 4000 0 60 ~ 0 +Text Label 3250 4000 0 60 ~ 0 b -Text Label 5300 4100 0 60 ~ 0 +Text Label 3250 4100 0 60 ~ 0 a -Text Label 4700 3000 0 60 ~ 0 +Text Label 2650 3000 0 60 ~ 0 b -Text Label 4700 3500 0 60 ~ 0 +Text Label 2650 3500 0 60 ~ 0 a $Comp L VCVS E1 U 1 1 50AA11B6 -P 5500 4050 -F 0 "E1" H 5300 4150 50 0000 C CNN -F 1 "10000" H 5300 4000 50 0000 C CNN - 1 5500 4050 +P 3450 4050 +F 0 "E1" H 3250 4150 50 0000 C CNN +F 1 "10000" H 3250 4000 50 0000 C CNN +F 2 "" H 3450 4050 60 0001 C CNN +F 3 "" H 3450 4050 60 0001 C CNN + 1 3450 4050 0 1 1 0 $EndComp $Comp -L R R4 +L R-RESCUE-lm555n R4 U 1 1 50A9E00B -P 4700 3250 -F 0 "R4" V 4780 3250 50 0000 C CNN -F 1 "2E6" V 4700 3250 50 0000 C CNN - 1 4700 3250 +P 2650 3250 +F 0 "R4" V 2730 3250 50 0000 C CNN +F 1 "2E6" V 2650 3250 50 0000 C CNN +F 2 "" H 2650 3250 60 0001 C CNN +F 3 "" H 2650 3250 60 0001 C CNN + 1 2650 3250 1 0 0 -1 $EndComp $Comp -L R R5 +L R-RESCUE-lm555n R5 U 1 1 50A9E001 -P 4700 4400 -F 0 "R5" V 4780 4400 50 0000 C CNN -F 1 "2E6" V 4700 4400 50 0000 C CNN - 1 4700 4400 +P 2650 4400 +F 0 "R5" V 2730 4400 50 0000 C CNN +F 1 "2E6" V 2650 4400 50 0000 C CNN +F 2 "" H 2650 4400 60 0001 C CNN +F 3 "" H 2650 4400 60 0001 C CNN + 1 2650 4400 1 0 0 -1 $EndComp $Comp -L R R3 +L R-RESCUE-lm555n R3 U 1 1 50A9DF09 -P 4400 4450 -F 0 "R3" V 4480 4450 50 0000 C CNN -F 1 "5000" V 4400 4450 50 0000 C CNN - 1 4400 4450 +P 2350 4450 +F 0 "R3" V 2430 4450 50 0000 C CNN +F 1 "5000" V 2350 4450 50 0000 C CNN +F 2 "" H 2350 4450 60 0001 C CNN +F 3 "" H 2350 4450 60 0001 C CNN + 1 2350 4450 1 0 0 -1 $EndComp $Comp -L R R2 +L R-RESCUE-lm555n R2 U 1 1 50A9DF03 -P 4400 3850 -F 0 "R2" V 4480 3850 50 0000 C CNN -F 1 "5000" V 4400 3850 50 0000 C CNN - 1 4400 3850 +P 2350 3850 +F 0 "R2" V 2430 3850 50 0000 C CNN +F 1 "5000" V 2350 3850 50 0000 C CNN +F 2 "" H 2350 3850 60 0001 C CNN +F 3 "" H 2350 3850 60 0001 C CNN + 1 2350 3850 1 0 0 -1 $EndComp $Comp -L R R1 +L R-RESCUE-lm555n R1 U 1 1 50A9DEFE -P 4400 3250 -F 0 "R1" V 4480 3250 50 0000 C CNN -F 1 "5000" V 4400 3250 50 0000 C CNN - 1 4400 3250 +P 2350 3250 +F 0 "R1" V 2430 3250 50 0000 C CNN +F 1 "5000" V 2350 3250 50 0000 C CNN +F 2 "" H 2350 3250 60 0001 C CNN +F 3 "" H 2350 3250 60 0001 C CNN + 1 2350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_srlatch U8 +U 1 1 5E01E563 +P 8000 3350 +F 0 "U8" H 8000 3350 60 0000 C CNN +F 1 "d_srlatch" H 8050 3500 60 0000 C CNN +F 2 "" H 8000 3350 60 0000 C CNN +F 3 "" H 8000 3350 60 0000 C CNN + 1 8000 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5E01F10F +P 7450 4400 +F 0 "U7" H 7450 4300 60 0000 C CNN +F 1 "d_inverter" H 7450 4550 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 4400 8150 4400 +Wire Wire Line + 8000 4400 8000 4150 +$Comp +L adc_bridge_1 U5 +U 1 1 5E01F2C7 +P 6350 3400 +F 0 "U5" H 6350 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 1 6350 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3350 7200 3350 +Wire Wire Line + 4300 4650 5600 4650 +Wire Wire Line + 5600 4650 5600 3350 +Wire Wire Line + 5600 3350 5750 3350 +$Comp +L adc_bridge_1 U4 +U 1 1 5E01F3F2 +P 6350 3000 +F 0 "U4" H 6350 3000 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN +F 2 "" H 6350 3000 60 0000 C CNN +F 3 "" H 6350 3000 60 0000 C CNN + 1 6350 3000 1 0 0 -1 $EndComp +$Comp +L adc_bridge_1 U6 +U 1 1 5E01F469 +P 6350 3850 +F 0 "U6" H 6350 3850 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN +F 2 "" H 6350 3850 60 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3800 7200 3800 +Wire Wire Line + 7200 2950 6900 2950 +$Comp +L limit U3 +U 1 1 5E01F5DC +P 4900 2950 +F 0 "U3" H 4950 2900 60 0000 C CNN +F 1 "limit" H 4950 3000 60 0000 C CNN +F 2 "" H 4900 3000 60 0000 C CNN +F 3 "" H 4900 3000 60 0000 C CNN + 1 4900 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2950 5750 2950 +Wire Wire Line + 4200 3250 4200 2950 +Wire Wire Line + 4200 2950 4500 2950 +$Comp +L limit U2 +U 1 1 5E01F79D +P 4800 3800 +F 0 "U2" H 4850 3750 60 0000 C CNN +F 1 "limit" H 4850 3850 60 0000 C CNN +F 2 "" H 4800 3850 60 0000 C CNN +F 3 "" H 4800 3850 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3800 5750 3800 +Wire Wire Line + 4200 3550 4200 3800 +Wire Wire Line + 4200 3800 4400 3800 +Wire Wire Line + 7050 3350 7050 4400 +Wire Wire Line + 7050 4400 7150 4400 +Connection ~ 7050 3350 +Wire Wire Line + 8000 2600 8150 2600 +Wire Wire Line + 8150 2600 8150 4400 +Connection ~ 8000 4400 +$Comp +L dac_bridge_1 U9 +U 1 1 5E01FCD2 +P 9550 3000 +F 0 "U9" H 9550 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN +F 2 "" H 9550 3000 60 0000 C CNN +F 3 "" H 9550 3000 60 0000 C CNN + 1 9550 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2950 8950 2950 +$Comp +L dac_bridge_1 U10 +U 1 1 5E01FE8E +P 9600 3850 +F 0 "U10" H 9600 3850 60 0000 C CNN +F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN +F 2 "" H 9600 3850 60 0000 C CNN +F 3 "" H 9600 3850 60 0000 C CNN + 1 9600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3800 8800 3800 +Wire Wire Line + 9100 4000 9100 4250 +Wire Wire Line + 9100 4000 10300 4000 +Wire Wire Line + 10300 4000 10300 3800 +Wire Wire Line + 10300 3800 10150 3800 +$Comp +L eSim_NPN Q1 +U 1 1 5E01E782 +P 9000 4600 +F 0 "Q1" H 8900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN +F 2 "" H 9200 4700 29 0000 C CNN +F 3 "" H 9000 4600 60 0000 C CNN + 1 9000 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 4600 8500 4600 +Wire Wire Line + 2250 4900 9100 4900 $EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub index beeefc43..b524f5c6 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.sub +++ b/src/SubcircuitLibrary/lm555n/lm555n.sub @@ -1,5 +1,6 @@ * Subcircuit lm555n -.subckt lm555n 22 14 7 6 15 16 3 13 +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib * eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist * Inverter d_inverter * SR Latch d_srlatch @@ -8,7 +9,7 @@ e2 18 0 23 14 10000 * Digital to Analog converter dac8 * Analog to Digital converter adc8 r8 9 2 1500 -q1 3 2 22 qnom +q1 3 2 22 npn_1 r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -33,5 +34,6 @@ a7 [11] [4] u2 a8 [12] [1] u2 a9 [6] [5] u2 .model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements -.ends lm555n
\ No newline at end of file +.ends lm555n diff --git a/src/SubcircuitLibrary/lm555n/npn_1.lib b/src/SubcircuitLibrary/lm555n/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/src/SubcircuitLibrary/lm555n/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/NPN.lib b/src/SubcircuitLibrary/lm7805/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm7805/PNP.lib b/src/SubcircuitLibrary/lm7805/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/lm7805/Q_PNP.lib b/src/SubcircuitLibrary/lm7805/Q_PNP.lib new file mode 100644 index 00000000..154ed2d8 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/Q_PNP.lib @@ -0,0 +1 @@ +.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/analysis b/src/SubcircuitLibrary/lm7805/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib new file mode 100644 index 00000000..aaf8454e --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir b/src/SubcircuitLibrary/lm7805/lm7805.cir new file mode 100644 index 00000000..081b4920 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.cir @@ -0,0 +1,51 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k +R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 +R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k +R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k +U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN +R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k +Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k +Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k +R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k +Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP +R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 +R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k +Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN +R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k +R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k +R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k +U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener +Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN +R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 +R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 +R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 +U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT + +.end diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir.out b/src/SubcircuitLibrary/lm7805/lm7805.cir.out new file mode 100644 index 00000000..f122fba6 --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.cir.out @@ -0,0 +1,60 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm7805/lm7805.pro b/src/SubcircuitLibrary/lm7805/lm7805.pro new file mode 100644 index 00000000..d410e2fa --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.pro @@ -0,0 +1,45 @@ +update=Mon Aug 26 14:34:23 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_PSpice +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User + diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sch b/src/SubcircuitLibrary/lm7805/lm7805.sch new file mode 100644 index 00000000..701d163d --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.sch @@ -0,0 +1,757 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm7805-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 5CE41429 +P 1250 1600 +F 0 "R1" V 1330 1600 50 0000 C CNN +F 1 "100k" V 1250 1600 50 0000 C CNN +F 2 "" V 1180 1600 50 0001 C CNN +F 3 "" H 1250 1600 50 0001 C CNN + 1 1250 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5CE4148B +P 1950 1600 +F 0 "R2" V 2030 1600 50 0000 C CNN +F 1 "500" V 1950 1600 50 0000 C CNN +F 2 "" V 1880 1600 50 0001 C CNN +F 3 "" H 1950 1600 50 0001 C CNN + 1 1950 1600 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5CE414A5 +P 1950 3050 +F 0 "R3" V 2030 3050 50 0000 C CNN +F 1 "3.3k" V 1950 3050 50 0000 C CNN +F 2 "" V 1880 3050 50 0001 C CNN +F 3 "" H 1950 3050 50 0001 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 5CE414CA +P 1950 3750 +F 0 "R4" V 2030 3750 50 0000 C CNN +F 1 "2.7k" V 1950 3750 50 0000 C CNN +F 2 "" V 1880 3750 50 0001 C CNN +F 3 "" H 1950 3750 50 0001 C CNN + 1 1950 3750 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 5CE414FA +P 1250 3350 +F 0 "U1" H 1200 3250 60 0000 C CNN +F 1 "zener" H 1250 3450 60 0000 C CNN +F 2 "" H 1300 3350 60 0000 C CNN +F 3 "" H 1300 3350 60 0000 C CNN + 1 1250 3350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 5CE41586 +P 1850 2350 +F 0 "Q1" H 1750 2400 50 0000 R CNN +F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN +F 2 "" H 2050 2450 29 0000 C CNN +F 3 "" H 1850 2350 60 0000 C CNN + 1 1850 2350 + 1 0 0 -1 +$EndComp +$Comp +L R R5 +U 1 1 5CE418C5 +P 1950 4600 +F 0 "R5" V 2030 4600 50 0000 C CNN +F 1 "500" V 1950 4600 50 0000 C CNN +F 2 "" V 1880 4600 50 0001 C CNN +F 3 "" H 1950 4600 50 0001 C CNN + 1 1950 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1750 1250 3050 +Wire Wire Line + 1250 1450 1250 1300 +Wire Wire Line + 1250 1300 1950 1300 +Wire Wire Line + 1950 1300 1950 1450 +Wire Wire Line + 1950 2150 1950 1750 +Wire Wire Line + 1950 2550 1950 2900 +Wire Wire Line + 1950 3200 1950 3600 +Wire Wire Line + 1950 3900 1950 4450 +Wire Wire Line + 1250 3550 1250 5200 +Wire Wire Line + 1250 5200 3200 5200 +Wire Wire Line + 1950 5200 1950 4750 +Wire Wire Line + 1650 2350 1250 2350 +Connection ~ 1250 2350 +$Comp +L eSim_NPN Q2 +U 1 1 5CE41D6C +P 2650 3350 +F 0 "Q2" H 2550 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN +F 2 "" H 2850 3450 29 0000 C CNN +F 3 "" H 2650 3350 60 0000 C CNN + 1 2650 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 5CE41E26 +P 3100 4100 +F 0 "Q4" H 3000 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN +F 2 "" H 3300 4200 29 0000 C CNN +F 3 "" H 3100 4100 60 0000 C CNN + 1 3100 4100 + 1 0 0 -1 +$EndComp +$Comp +L R R6 +U 1 1 5CE41EA8 +P 2750 3850 +F 0 "R6" V 2830 3850 50 0000 C CNN +F 1 "1k" V 2750 3850 50 0000 C CNN +F 2 "" V 2680 3850 50 0001 C CNN +F 3 "" H 2750 3850 50 0001 C CNN + 1 2750 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE41EFE +P 2850 4650 +F 0 "Q3" H 2750 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN +F 2 "" H 3050 4750 29 0000 C CNN +F 3 "" H 2850 4650 60 0000 C CNN + 1 2850 4650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2750 3550 2750 3700 +Wire Wire Line + 2750 4000 2750 4450 +Wire Wire Line + 2900 4100 2750 4100 +Connection ~ 2750 4100 +Wire Wire Line + 3200 4300 3200 4750 +Wire Wire Line + 3050 4650 3450 4650 +Wire Wire Line + 2450 3350 1950 3350 +Connection ~ 1950 3350 +Wire Wire Line + 2750 3600 3600 3600 +Wire Wire Line + 3200 3600 3200 3900 +Connection ~ 2750 3600 +$Comp +L R R7 +U 1 1 5CE42281 +P 3200 4900 +F 0 "R7" V 3280 4900 50 0000 C CNN +F 1 "6k" V 3200 4900 50 0000 C CNN +F 2 "" V 3130 4900 50 0001 C CNN +F 3 "" H 3200 4900 50 0001 C CNN + 1 3200 4900 + 1 0 0 -1 +$EndComp +Connection ~ 3200 4650 +Wire Wire Line + 3200 5050 3200 5250 +Connection ~ 1950 5200 +Wire Wire Line + 2750 4850 2750 5200 +Connection ~ 2750 5200 +$Comp +L eSim_NPN Q6 +U 1 1 5CE424FB +P 3650 4650 +F 0 "Q6" H 3550 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN +F 2 "" H 3850 4750 29 0000 C CNN +F 3 "" H 3650 4650 60 0000 C CNN + 1 3650 4650 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 5CE42584 +P 3750 5100 +F 0 "R10" V 3830 5100 50 0000 C CNN +F 1 "1k" V 3750 5100 50 0000 C CNN +F 2 "" V 3680 5100 50 0001 C CNN +F 3 "" H 3750 5100 50 0001 C CNN + 1 3750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4850 3750 4950 +Wire Wire Line + 3200 5250 3750 5250 +Connection ~ 3200 5200 +$Comp +L eSim_NPN Q7 +U 1 1 5CE427DA +P 3700 2750 +F 0 "Q7" H 3600 2800 50 0000 R CNN +F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN +F 2 "" H 3900 2850 29 0000 C CNN +F 3 "" H 3700 2750 60 0000 C CNN + 1 3700 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE428D0 +P 3700 3400 +F 0 "Q8" H 3600 3450 50 0000 R CNN +F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN +F 2 "" H 3900 3500 29 0000 C CNN +F 3 "" H 3700 3400 60 0000 C CNN + 1 3700 3400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE4293A +P 4350 3000 +F 0 "Q12" H 4250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN +F 2 "" H 4550 3100 29 0000 C CNN +F 3 "" H 4350 3000 60 0000 C CNN + 1 4350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2950 3600 3200 +Wire Wire Line + 4250 3200 4250 3400 +Wire Wire Line + 4250 3400 3900 3400 +Wire Wire Line + 4250 2750 4250 2800 +Wire Wire Line + 3900 2750 4250 2750 +Connection ~ 3200 3600 +$Comp +L R R12 +U 1 1 5CE42C4F +P 4350 3450 +F 0 "R12" V 4430 3450 50 0000 C CNN +F 1 "6k" V 4350 3450 50 0000 C CNN +F 2 "" V 4280 3450 50 0001 C CNN +F 3 "" H 4350 3450 50 0001 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 3300 4250 3300 +Connection ~ 4250 3300 +Wire Wire Line + 3700 3600 4350 3600 +Wire Wire Line + 3700 3600 3700 3650 +Wire Wire Line + 3700 3650 3550 3650 +Wire Wire Line + 3550 3650 3550 3600 +Connection ~ 3550 3600 +$Comp +L R R9 +U 1 1 5CE42EA3 +P 3750 3950 +F 0 "R9" V 3830 3950 50 0000 C CNN +F 1 "20k" V 3750 3950 50 0000 C CNN +F 2 "" V 3680 3950 50 0001 C CNN +F 3 "" H 3750 3950 50 0001 C CNN + 1 3750 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4100 3750 4450 +Wire Wire Line + 3750 3800 3750 3600 +Connection ~ 3750 3600 +Wire Wire Line + 2750 3150 2750 2450 +Wire Wire Line + 2750 2450 3600 2450 +Wire Wire Line + 3600 2450 3600 2550 +$Comp +L eSim_PNP Q5 +U 1 1 5CE43397 +P 3450 1700 +F 0 "Q5" H 3350 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN +F 2 "" H 3650 1800 29 0000 C CNN +F 3 "" H 3450 1700 60 0000 C CNN + 1 3450 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE4353C +P 4100 1700 +F 0 "Q9" H 4000 1750 50 0000 R CNN +F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN +F 2 "" H 4300 1800 29 0000 C CNN +F 3 "" H 4100 1700 60 0000 C CNN + 1 4100 1700 + 1 0 0 1 +$EndComp +$Comp +L R R8 +U 1 1 5CE435B8 +P 3350 1250 +F 0 "R8" V 3430 1250 50 0000 C CNN +F 1 "100" V 3350 1250 50 0000 C CNN +F 2 "" V 3280 1250 50 0001 C CNN +F 3 "" H 3350 1250 50 0001 C CNN + 1 3350 1250 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 5CE4368E +P 4200 1250 +F 0 "R11" V 4280 1250 50 0000 C CNN +F 1 "50" V 4200 1250 50 0000 C CNN +F 2 "" V 4130 1250 50 0001 C CNN +F 3 "" H 4200 1250 50 0001 C CNN + 1 4200 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 5CE43705 +P 4100 2200 +F 0 "Q10" H 4000 2250 50 0000 R CNN +F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN +F 2 "" H 4300 2300 29 0000 C CNN +F 3 "" H 4100 2200 60 0000 C CNN + 1 4100 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3350 1400 3350 1500 +Wire Wire Line + 3650 1700 3900 1700 +Wire Wire Line + 4200 1400 4200 1500 +Wire Wire Line + 3350 1100 3350 1050 +Wire Wire Line + 1650 1050 7800 1050 +Wire Wire Line + 4200 1050 4200 1100 +Wire Wire Line + 4200 1900 4200 2000 +Wire Wire Line + 3750 1700 3750 2000 +Wire Wire Line + 3750 2000 3350 2000 +Wire Wire Line + 3350 1900 3350 2450 +Connection ~ 3750 1700 +Connection ~ 3350 2450 +Connection ~ 3350 2000 +Wire Wire Line + 2300 2200 3900 2200 +Wire Wire Line + 2300 2200 2300 4200 +Wire Wire Line + 2300 4200 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 2200 2400 4200 2400 +Wire Wire Line + 2200 2400 2200 5200 +Connection ~ 2200 5200 +$Comp +L eSim_NPN Q11 +U 1 1 5CE4439E +P 4300 4400 +F 0 "Q11" H 4200 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN +F 2 "" H 4500 4500 29 0000 C CNN +F 3 "" H 4300 4400 60 0000 C CNN + 1 4300 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE44419 +P 4600 4800 +F 0 "Q13" H 4500 4850 50 0000 R CNN +F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN +F 2 "" H 4800 4900 29 0000 C CNN +F 3 "" H 4600 4800 60 0000 C CNN + 1 4600 4800 + 1 0 0 -1 +$EndComp +$Comp +L R R13 +U 1 1 5CE444B9 +P 4400 5050 +F 0 "R13" V 4480 5050 50 0000 C CNN +F 1 "6k" V 4400 5050 50 0000 C CNN +F 2 "" V 4330 5050 50 0001 C CNN +F 3 "" H 4400 5050 50 0001 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE4451D +P 4050 4150 +F 0 "C1" H 4075 4250 50 0000 L CNN +F 1 "30p" H 4075 4050 50 0000 L CNN +F 2 "" H 4088 4000 30 0000 C CNN +F 3 "" H 4050 4150 60 0000 C CNN + 1 4050 4150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4100 4400 3750 4400 +Connection ~ 3750 4400 +Wire Wire Line + 3900 4150 3750 4150 +Connection ~ 3750 4150 +Wire Wire Line + 4700 4150 4200 4150 +Wire Wire Line + 4400 4150 4400 4200 +Wire Wire Line + 4400 4600 4400 4900 +Connection ~ 4400 4800 +Wire Wire Line + 4400 5200 4400 5300 +Wire Wire Line + 3650 5300 6400 5300 +Wire Wire Line + 3650 5300 3650 5250 +Connection ~ 3650 5250 +Wire Wire Line + 4700 5300 4700 5000 +Connection ~ 4400 5300 +Wire Wire Line + 4700 3800 4700 4600 +Connection ~ 4400 4150 +$Comp +L R R14 +U 1 1 5CE44FFF +P 4700 3650 +F 0 "R14" V 4780 3650 50 0000 C CNN +F 1 "6k" V 4700 3650 50 0000 C CNN +F 2 "" V 4630 3650 50 0001 C CNN +F 3 "" H 4700 3650 50 0001 C CNN + 1 4700 3650 + 1 0 0 -1 +$EndComp +Connection ~ 4700 4150 +$Comp +L eSim_PNP Q14 +U 1 1 5CE45652 +P 5050 3950 +F 0 "Q14" H 4950 4000 50 0000 R CNN +F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN +F 2 "" H 5250 4050 29 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5050 3950 + 1 0 0 1 +$EndComp +Wire Wire Line + 4850 3950 4700 3950 +Connection ~ 4700 3950 +Wire Wire Line + 4700 3500 4700 3450 +Wire Wire Line + 4700 3450 5150 3450 +Wire Wire Line + 5150 3450 5150 3750 +Wire Wire Line + 5150 5300 5150 4150 +Connection ~ 4700 5300 +Wire Wire Line + 4750 3450 4750 1950 +Wire Wire Line + 4200 1950 5300 1950 +Connection ~ 4200 1950 +Connection ~ 4750 3450 +$Comp +L eSim_NPN Q15 +U 1 1 5CE463AD +P 5400 2150 +F 0 "Q15" H 5300 2200 50 0000 R CNN +F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN +F 2 "" H 5600 2250 29 0000 C CNN +F 3 "" H 5400 2150 60 0000 C CNN + 1 5400 2150 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1950 +Wire Wire Line + 4150 2750 4150 2600 +Wire Wire Line + 4150 2600 6100 2600 +Wire Wire Line + 5300 2600 5300 2350 +Connection ~ 4150 2750 +$Comp +L R R17 +U 1 1 5CE46DDE +P 6050 4250 +F 0 "R17" V 6130 4250 50 0000 C CNN +F 1 "5k" V 6050 4250 50 0000 C CNN +F 2 "" V 5980 4250 50 0001 C CNN +F 3 "" H 6050 4250 50 0001 C CNN + 1 6050 4250 + 1 0 0 -1 +$EndComp +$Comp +L R R16 +U 1 1 5CE46F8E +P 6050 3050 +F 0 "R16" V 6130 3050 50 0000 C CNN +F 1 "1.385k" V 6050 3050 50 0000 C CNN +F 2 "" V 5980 3050 50 0001 C CNN +F 3 "" H 6050 3050 50 0001 C CNN + 1 6050 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3200 6050 4100 +Wire Wire Line + 6050 5300 6050 4400 +Connection ~ 5150 5300 +Wire Wire Line + 6050 2600 6050 2900 +Connection ~ 5300 2600 +Wire Wire Line + 4550 3000 5100 3000 +Wire Wire Line + 5100 3000 5100 3250 +Wire Wire Line + 5100 3250 5350 3250 +Wire Wire Line + 5350 3250 5350 3600 +Wire Wire Line + 5350 3600 6050 3600 +Connection ~ 6050 3600 +Wire Wire Line + 1650 1050 1650 1300 +Connection ~ 1650 1300 +Connection ~ 3350 1050 +$Comp +L R R15 +U 1 1 5CE47F7A +P 5850 1300 +F 0 "R15" V 5930 1300 50 0000 C CNN +F 1 "10k" V 5850 1300 50 0000 C CNN +F 2 "" V 5780 1300 50 0001 C CNN +F 3 "" H 5850 1300 50 0001 C CNN + 1 5850 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1050 5850 1150 +Connection ~ 4200 1050 +$Comp +L zener U2 +U 1 1 5CE48686 +P 5850 1900 +F 0 "U2" H 5800 1800 60 0000 C CNN +F 1 "zener" H 5850 2000 60 0000 C CNN +F 2 "" H 5900 1900 60 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5850 1900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5850 1450 5850 1600 +Wire Wire Line + 5850 2100 5850 2250 +Wire Wire Line + 5850 2150 5600 2150 +$Comp +L eSim_NPN Q16 +U 1 1 5CE4907A +P 6550 1600 +F 0 "Q16" H 6450 1650 50 0000 R CNN +F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN +F 2 "" H 6750 1700 29 0000 C CNN +F 3 "" H 6550 1600 60 0000 C CNN + 1 6550 1600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE4942E +P 7300 1950 +F 0 "Q17" H 7200 2000 50 0000 R CNN +F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN +F 2 "" H 7500 2050 29 0000 C CNN +F 3 "" H 7300 1950 60 0000 C CNN + 1 7300 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 1800 6650 2300 +Wire Wire Line + 6650 1950 7100 1950 +Wire Wire Line + 7400 1050 7400 1750 +Connection ~ 5850 1050 +Wire Wire Line + 6650 1400 6650 1050 +Connection ~ 6650 1050 +$Comp +L R R18 +U 1 1 5CE498BA +P 6650 2450 +F 0 "R18" V 6730 2450 50 0000 C CNN +F 1 "200" V 6650 2450 50 0000 C CNN +F 2 "" V 6580 2450 50 0001 C CNN +F 3 "" H 6650 2450 50 0001 C CNN + 1 6650 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R20 +U 1 1 5CE4999A +P 7400 2450 +F 0 "R20" V 7480 2450 50 0000 C CNN +F 1 "0.3" V 7400 2450 50 0000 C CNN +F 2 "" V 7330 2450 50 0001 C CNN +F 3 "" H 7400 2450 50 0001 C CNN + 1 7400 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R19 +U 1 1 5CE49AF5 +P 7000 2250 +F 0 "R19" V 7080 2250 50 0000 C CNN +F 1 "240" V 7000 2250 50 0000 C CNN +F 2 "" V 6930 2250 50 0001 C CNN +F 3 "" H 7000 2250 50 0001 C CNN + 1 7000 2250 + 0 1 1 0 +$EndComp +Connection ~ 6650 1950 +Wire Wire Line + 5850 2250 6850 2250 +Connection ~ 5850 2150 +Wire Wire Line + 7400 2150 7400 2300 +Wire Wire Line + 7150 2250 7400 2250 +Connection ~ 7400 2250 +Wire Wire Line + 6100 2600 6100 2650 +Wire Wire Line + 6100 2650 7400 2650 +Wire Wire Line + 7400 2650 7400 2600 +Connection ~ 6050 2600 +Wire Wire Line + 6650 2600 6650 2650 +Connection ~ 6650 2650 +$Comp +L PORT U3 +U 1 1 5CE4AAF6 +P 8050 1050 +F 0 "U3" H 8100 1150 30 0000 C CNN +F 1 "PORT" H 8050 1050 30 0000 C CNN +F 2 "" H 8050 1050 60 0000 C CNN +F 3 "" H 8050 1050 60 0000 C CNN + 1 8050 1050 + -1 0 0 1 +$EndComp +Connection ~ 7400 1050 +$Comp +L PORT U3 +U 3 1 5CE4B13E +P 7700 3000 +F 0 "U3" H 7750 3100 30 0000 C CNN +F 1 "PORT" H 7700 3000 30 0000 C CNN +F 2 "" H 7700 3000 60 0000 C CNN +F 3 "" H 7700 3000 60 0000 C CNN + 3 7700 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 2 1 5CE4B701 +P 6650 5300 +F 0 "U3" H 6700 5400 30 0000 C CNN +F 1 "PORT" H 6650 5300 30 0000 C CNN +F 2 "" H 6650 5300 60 0000 C CNN +F 3 "" H 6650 5300 60 0000 C CNN + 2 6650 5300 + -1 0 0 1 +$EndComp +Connection ~ 6050 5300 +Wire Wire Line + 6350 1600 5950 1600 +Wire Wire Line + 5950 1600 5950 1550 +Wire Wire Line + 5950 1550 5000 1550 +Wire Wire Line + 5000 1550 5000 1950 +Connection ~ 5000 1950 +Wire Wire Line + 7300 2650 7300 3000 +Wire Wire Line + 7300 3000 7450 3000 +Connection ~ 7300 2650 +Connection ~ 2500 5200 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sub b/src/SubcircuitLibrary/lm7805/lm7805.sub new file mode 100644 index 00000000..7ee1489c --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805.sub @@ -0,0 +1,54 @@ +* Subcircuit lm7805 +.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ +* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir +.include PNP.lib +.include NPN.lib +r1 net-_q16-pad1_ net-_q1-pad2_ 100k +r2 net-_q16-pad1_ net-_q1-pad1_ 500 +r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k +r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k +* u1 net-_q10-pad3_ net-_q1-pad2_ zener +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r5 net-_q10-pad2_ net-_q10-pad3_ 500 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 +r6 net-_q2-pad3_ net-_q3-pad1_ 1k +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q3-pad2_ net-_q10-pad3_ 6k +q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 +r10 net-_q6-pad3_ net-_q10-pad3_ 1k +q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r12 net-_q12-pad3_ net-_q2-pad3_ 6k +r9 net-_q2-pad3_ net-_c1-pad2_ 20k +q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A +r8 net-_q16-pad1_ net-_q5-pad3_ 100 +r11 net-_q16-pad1_ net-_q9-pad3_ 50 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 +r13 net-_q11-pad3_ net-_q10-pad3_ 6k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +r14 net-_q10-pad1_ net-_c1-pad1_ 6k +q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 +r17 net-_q12-pad2_ net-_q10-pad3_ 5k +r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k +r15 net-_q16-pad1_ net-_r15-pad2_ 10k +* u2 net-_q15-pad2_ net-_r15-pad2_ zener +q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 +r18 net-_q16-pad3_ net-_q12-pad1_ 200 +r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 +r19 net-_q17-pad3_ net-_q15-pad2_ 240 +a1 net-_q10-pad3_ net-_q1-pad2_ u1 +a2 net-_q15-pad2_ net-_r15-pad2_ u2 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) +* Control Statements + +.ends lm7805
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml new file mode 100644 index 00000000..7395bd7c --- /dev/null +++ b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/NPN.lib b/src/SubcircuitLibrary/lm_741/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm_741/PNP.lib b/src/SubcircuitLibrary/lm_741/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/lm_741/analysis b/src/SubcircuitLibrary/lm_741/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir b/src/SubcircuitLibrary/lm_741/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir.out b/src/SubcircuitLibrary/lm_741/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/lm_741/lm_741.pro b/src/SubcircuitLibrary/lm_741/lm_741.pro new file mode 100644 index 00000000..cbe83f35 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.pro @@ -0,0 +1,45 @@ +update=Fri Jun 7 21:53:51 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_PSpice +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sch b/src/SubcircuitLibrary/lm_741/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sub b/src/SubcircuitLibrary/lm_741/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/npn_1.lib b/src/SubcircuitLibrary/lm_741/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/pnp_1.lib b/src/SubcircuitLibrary/lm_741/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/src/SubcircuitLibrary/lm_741/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib new file mode 100644 index 00000000..ef18bb50 --- /dev/null +++ b/src/SubcircuitLibrary/scr/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib index d6fb6469..a2f61dce 100644 --- a/src/SubcircuitLibrary/scr/PowerDiode.lib +++ b/src/SubcircuitLibrary/scr/PowerDiode.lib @@ -1 +1,20 @@ -.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m ) +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib index 24105a8a..0a685b80 100644 --- a/src/SubcircuitLibrary/scr/scr-cache.lib +++ b/src/SubcircuitLibrary/scr/scr-cache.lib @@ -6,20 +6,16 @@ EESchema-LIBRARY Version 2.3 DEF C C 0 10 N Y 1 F N F0 "C" 25 100 50 H V L CNN F1 "C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN $FPLIST - C? - C_????_* - C_???? - SMD*_c - Capacitor* + C_* $ENDFPLIST DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P ENDDRAW ENDDEF # @@ -54,8 +50,8 @@ $FPLIST S* $ENDFPLIST DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F X A 1 -200 0 150 R 40 40 1 1 P X K 2 200 0 150 L 40 40 1 1 P ENDDRAW @@ -63,7 +59,7 @@ ENDDEF # # PORT # -DEF PORT U 0 40 Y Y 8 F N +DEF PORT U 0 40 Y Y 26 F N F0 "U" 50 100 30 H V C CNN F1 "PORT" 0 0 30 H V C CNN F2 "" 0 0 60 H V C CNN @@ -80,14 +76,32 @@ X ~ 5 250 0 100 L 30 30 5 1 B X ~ 6 250 0 100 L 30 30 6 1 B X ~ 7 250 0 100 L 30 30 7 1 B X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B ENDDRAW ENDDEF # -# R +# R-RESCUE-scr # -DEF R R 0 0 N Y 1 F N +DEF R-RESCUE-scr R 0 0 N Y 1 F N F0 "R" 50 130 50 H V C CNN -F1 "R" 50 50 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN F2 "" 50 -20 30 H V C CNN F3 "" 50 50 30 V V C CNN $FPLIST @@ -116,11 +130,11 @@ X ~ 1_IN 450 -100 200 U 50 20 1 1 I ENDDRAW ENDDEF # -# dc +# dc-RESCUE-scr # -DEF dc v 0 40 Y Y 1 F N +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN -F1 "dc" -200 -50 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/src/SubcircuitLibrary/scr/scr-rescue.lib b/src/SubcircuitLibrary/scr/scr-rescue.lib new file mode 100644 index 00000000..64237b7d --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr-rescue.lib @@ -0,0 +1,39 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# R-RESCUE-scr +# +DEF R-RESCUE-scr R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R-RESCUE-scr" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# dc-RESCUE-scr +# +DEF dc-RESCUE-scr v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro index fc4ca966..ca0df803 100644 --- a/src/SubcircuitLibrary/scr/scr.pro +++ b/src/SubcircuitLibrary/scr/scr.pro @@ -1,44 +1,45 @@ -update=Tue Dec 8 15:45:12 2015 -last_client=eeschema +update=Wed Jul 31 19:51:09 2019 +last_client=kicad [eeschema] version=1 LibDir= [eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Sources -LibName7=eSim_Subckt -LibName8=eSim_User -LibName9=power -LibName10=device -LibName11=transistors -LibName12=conn -LibName13=linear -LibName14=regul -LibName15=74xx -LibName16=cmos4000 -LibName17=adc-dac -LibName18=memory -LibName19=xilinx -LibName20=special -LibName21=microcontrollers -LibName22=dsp -LibName23=microchip -LibName24=analog_switches -LibName25=motorola -LibName26=texas -LibName27=intel -LibName28=audio -LibName29=interface -LibName30=digital-audio -LibName31=philips -LibName32=display -LibName33=cypress -LibName34=siliconi -LibName35=opto -LibName36=atmel -LibName37=contrib -LibName38=valves +LibName1=scr-rescue +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Sources +LibName8=eSim_Subckt +LibName9=eSim_User +LibName10=power +LibName11=device +LibName12=transistors +LibName13=conn +LibName14=linear +LibName15=regul +LibName16=74xx +LibName17=cmos4000 +LibName18=adc-dac +LibName19=memory +LibName20=xilinx +LibName21=special +LibName22=microcontrollers +LibName23=dsp +LibName24=microchip +LibName25=analog_switches +LibName26=motorola +LibName27=texas +LibName28=intel +LibName29=audio +LibName30=interface +LibName31=digital-audio +LibName32=philips +LibName33=display +LibName34=cypress +LibName35=siliconi +LibName36=opto +LibName37=atmel +LibName38=contrib +LibName39=valves diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch index 1f23ec65..69244f56 100644 --- a/src/SubcircuitLibrary/scr/scr.sch +++ b/src/SubcircuitLibrary/scr/scr.sch @@ -1,4 +1,5 @@ EESchema Schematic File Version 2 +LIBS:scr-rescue LIBS:eSim_Analog LIBS:eSim_Devices LIBS:eSim_Digital @@ -182,7 +183,7 @@ F 3 "" H 3800 4350 60 0001 C CNN 0 1 1 0 $EndComp $Comp -L dc v1 +L dc-RESCUE-scr v1 U 1 1 565DBF58 P 3600 3700 F 0 "v1" H 3400 3800 60 0000 C CNN @@ -193,7 +194,7 @@ F 3 "" H 3600 3700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L dc v2 +L dc-RESCUE-scr v2 U 1 1 565DC066 P 5550 3000 F 0 "v2" H 5350 3100 60 0000 C CNN @@ -217,7 +218,7 @@ $EndComp Wire Wire Line 5950 2000 6650 2000 $Comp -L R R1 +L R-RESCUE-scr R1 U 1 1 5666B019 P 3550 2950 F 0 "R1" H 3600 3080 50 0000 C CNN @@ -228,7 +229,7 @@ F 3 "" V 3600 3000 30 0000 C CNN 0 1 1 0 $EndComp $Comp -L R R2 +L R-RESCUE-scr R2 U 1 1 5666B17A P 4200 5300 F 0 "R2" H 4250 5430 50 0000 C CNN diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro index be9bc92c..5dbb81a5 100644 --- a/src/SubcircuitLibrary/ua741/ua741.pro +++ b/src/SubcircuitLibrary/ua741/ua741.pro @@ -2,7 +2,7 @@ update=Monday 17 December 2012 06:14:06 PM IST last_client=eeschema [eeschema] version=1 -LibDir= +LibDir=/home/yogesh/FreeEDA/library NetFmt=1 HPGLSpd=20 HPGLDm=15 diff --git a/src/SubcircuitLibrary/ujt/analysis b/src/SubcircuitLibrary/ujt/analysis index 21dc4b94..ffc57a6b 100644 --- a/src/SubcircuitLibrary/ujt/analysis +++ b/src/SubcircuitLibrary/ujt/analysis @@ -1 +1 @@ -.tran 5e-06 100e-03 0e-03
\ No newline at end of file +.tran 5e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/emitter.lib b/src/SubcircuitLibrary/ujt/emitter.lib index 3af759f4..3e78b1ee 100644 --- a/src/SubcircuitLibrary/ujt/emitter.lib +++ b/src/SubcircuitLibrary/ujt/emitter.lib @@ -1,4 +1,11 @@ -.MODEL emitter D( -+ Is=21.3P -+ N=1.8 -)
\ No newline at end of file +.model emitter D( ++ Vj=1 ++ Cjo=1.700E-12 ++ Rs=4.755E-01 ++ Is=21.3P ++ M=1.959E-01 ++ N=1.8 ++ Bv=1.000E+02 ++ tt=3.030E-09 ++ Ibv=1.000E-04 +) diff --git a/src/SubcircuitLibrary/ujt/plot_data_i.txt b/src/SubcircuitLibrary/ujt/plot_data_i.txt index bb08d2c2..e69de29b 100644 --- a/src/SubcircuitLibrary/ujt/plot_data_i.txt +++ b/src/SubcircuitLibrary/ujt/plot_data_i.txt @@ -1,67 +0,0 @@ - * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir - Transient Analysis Sat Jun 15 16:01:36 2019 --------------------------------------------------------------------------------- -Index time h1#branch vh1#branch --------------------------------------------------------------------------------- -0 0.000000e+00 1.936296e-124 -1.93630e-121 -1 1.000000e-05 1.522607e-65 -1.52261e-62 -2 2.000000e-05 1.522589e-65 -1.52259e-62 -3 4.000000e-05 1.522545e-65 -1.52255e-62 -4 8.000000e-05 0.000000e+00 0.000000e+00 -5 1.600000e-04 0.000000e+00 0.000000e+00 -6 3.200000e-04 0.000000e+00 0.000000e+00 -7 6.400000e-04 0.000000e+00 0.000000e+00 -8 1.280000e-03 3.035283e-65 -3.03528e-62 -9 2.560000e-03 1.511759e-65 -1.51176e-62 -10 4.560000e-03 0.000000e+00 0.000000e+00 -11 6.560000e-03 0.000000e+00 0.000000e+00 -12 8.560000e-03 0.000000e+00 0.000000e+00 -13 1.056000e-02 0.000000e+00 0.000000e+00 -14 1.256000e-02 0.000000e+00 0.000000e+00 -15 1.456000e-02 0.000000e+00 0.000000e+00 -16 1.656000e-02 0.000000e+00 0.000000e+00 -17 1.856000e-02 0.000000e+00 0.000000e+00 -18 2.056000e-02 0.000000e+00 0.000000e+00 -19 2.256000e-02 0.000000e+00 0.000000e+00 -20 2.456000e-02 0.000000e+00 0.000000e+00 -21 2.656000e-02 0.000000e+00 0.000000e+00 -22 2.856000e-02 0.000000e+00 0.000000e+00 -23 3.056000e-02 0.000000e+00 0.000000e+00 -24 3.256000e-02 0.000000e+00 0.000000e+00 -25 3.456000e-02 0.000000e+00 0.000000e+00 -26 3.656000e-02 0.000000e+00 0.000000e+00 -27 3.856000e-02 0.000000e+00 0.000000e+00 -28 4.056000e-02 0.000000e+00 0.000000e+00 -29 4.256000e-02 0.000000e+00 0.000000e+00 -30 4.456000e-02 0.000000e+00 0.000000e+00 -31 4.656000e-02 0.000000e+00 0.000000e+00 -32 4.856000e-02 0.000000e+00 0.000000e+00 -33 5.056000e-02 0.000000e+00 0.000000e+00 -34 5.256000e-02 0.000000e+00 0.000000e+00 -35 5.456000e-02 0.000000e+00 0.000000e+00 -36 5.656000e-02 0.000000e+00 0.000000e+00 -37 5.856000e-02 0.000000e+00 0.000000e+00 -38 6.056000e-02 0.000000e+00 0.000000e+00 -39 6.256000e-02 0.000000e+00 0.000000e+00 -40 6.456000e-02 0.000000e+00 0.000000e+00 -41 6.656000e-02 0.000000e+00 0.000000e+00 -42 6.856000e-02 0.000000e+00 0.000000e+00 -43 7.056000e-02 0.000000e+00 0.000000e+00 -44 7.256000e-02 0.000000e+00 0.000000e+00 -45 7.456000e-02 0.000000e+00 0.000000e+00 -46 7.656000e-02 0.000000e+00 0.000000e+00 -47 7.856000e-02 0.000000e+00 0.000000e+00 -48 8.056000e-02 0.000000e+00 0.000000e+00 -49 8.256000e-02 0.000000e+00 0.000000e+00 -50 8.456000e-02 0.000000e+00 0.000000e+00 -51 8.656000e-02 0.000000e+00 0.000000e+00 -52 8.856000e-02 0.000000e+00 0.000000e+00 -53 9.056000e-02 0.000000e+00 0.000000e+00 -54 9.256000e-02 0.000000e+00 0.000000e+00 - -Index time h1#branch vh1#branch --------------------------------------------------------------------------------- -55 9.456000e-02 0.000000e+00 0.000000e+00 -56 9.656000e-02 0.000000e+00 0.000000e+00 -57 9.856000e-02 0.000000e+00 0.000000e+00 -58 1.000000e-01 3.640960e-66 -3.64096e-63 diff --git a/src/SubcircuitLibrary/ujt/plot_data_v.txt b/src/SubcircuitLibrary/ujt/plot_data_v.txt index 207ce5b7..e69de29b 100644 --- a/src/SubcircuitLibrary/ujt/plot_data_v.txt +++ b/src/SubcircuitLibrary/ujt/plot_data_v.txt @@ -1,203 +0,0 @@ - * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir - Transient Analysis Sat Jun 15 16:01:36 2019 --------------------------------------------------------------------------------- -Index time V(1) V(2) V(3) --------------------------------------------------------------------------------- -0 0.000000e+00 6.088894e-52 -2.80622e-43 -2.80622e-43 -1 1.000000e-05 -2.51069e-46 -2.80871e-43 -2.80871e-43 -2 2.000000e-05 -2.51068e-46 -2.80868e-43 -2.80868e-43 -3 4.000000e-05 -2.51147e-46 -2.80860e-43 -2.80860e-43 -4 8.000000e-05 1.691803e-50 -2.80589e-43 -2.80589e-43 -5 1.600000e-04 -1.19543e-50 -2.80543e-43 -2.80543e-43 -6 3.200000e-04 -2.36974e-50 -2.80438e-43 -2.80438e-43 -7 6.400000e-04 4.520590e-52 -2.80203e-43 -2.80203e-43 -8 1.280000e-03 -2.71395e-46 -2.79955e-43 -2.79955e-43 -9 2.560000e-03 -3.13629e-46 -2.78870e-43 -2.78870e-43 -10 4.560000e-03 -5.10465e-52 -2.76667e-43 -2.76667e-43 -11 6.560000e-03 -2.20180e-52 -2.74650e-43 -2.74650e-43 -12 8.560000e-03 2.805351e-52 -2.72507e-43 -2.72507e-43 -13 1.056000e-02 -6.11918e-52 -2.70239e-43 -2.70239e-43 -14 1.256000e-02 -1.35091e-52 -2.67846e-43 -2.67846e-43 -15 1.456000e-02 6.127039e-53 -2.65331e-43 -2.65331e-43 -16 1.656000e-02 -6.60318e-52 -2.62693e-43 -2.62693e-43 -17 1.856000e-02 -2.70241e-52 -2.59936e-43 -2.59936e-43 -18 2.056000e-02 6.713684e-53 -2.57059e-43 -2.57059e-43 -19 2.256000e-02 -1.55773e-52 -2.54064e-43 -2.54064e-43 -20 2.456000e-02 3.929090e-53 -2.50953e-43 -2.50953e-43 -21 2.656000e-02 -5.71836e-52 -2.47727e-43 -2.47727e-43 -22 2.856000e-02 -1.42047e-52 -2.44388e-43 -2.44388e-43 -23 3.056000e-02 -4.85310e-52 -2.40937e-43 -2.40937e-43 -24 3.256000e-02 3.962144e-52 -2.37377e-43 -2.37377e-43 -25 3.456000e-02 -7.13895e-52 -2.33707e-43 -2.33707e-43 -26 3.656000e-02 -3.25981e-52 -2.29932e-43 -2.29932e-43 -27 3.856000e-02 -3.11521e-52 -2.26051e-43 -2.26051e-43 -28 4.056000e-02 2.279041e-52 -2.22068e-43 -2.22068e-43 -29 4.256000e-02 -4.09991e-52 -2.17983e-43 -2.17983e-43 -30 4.456000e-02 6.197036e-53 -2.13800e-43 -2.13800e-43 -31 4.656000e-02 -4.88067e-52 -2.09519e-43 -2.09519e-43 -32 4.856000e-02 -5.64247e-52 -2.05144e-43 -2.05144e-43 -33 5.056000e-02 -4.96151e-52 -2.00675e-43 -2.00675e-43 -34 5.256000e-02 -4.23061e-52 -1.96115e-43 -1.96115e-43 -35 5.456000e-02 2.057927e-52 -1.91467e-43 -1.91467e-43 -36 5.656000e-02 -6.33244e-52 -1.86732e-43 -1.86732e-43 -37 5.856000e-02 -3.34770e-52 -1.81913e-43 -1.81913e-43 -38 6.056000e-02 -2.07109e-52 -1.77011e-43 -1.77011e-43 -39 6.256000e-02 1.985474e-52 -1.72030e-43 -1.72030e-43 -40 6.456000e-02 -2.45836e-52 -1.66972e-43 -1.66972e-43 -41 6.656000e-02 -1.04902e-52 -1.61839e-43 -1.61839e-43 -42 6.856000e-02 -2.43454e-52 -1.56633e-43 -1.56633e-43 -43 7.056000e-02 -9.13597e-53 -1.51357e-43 -1.51357e-43 -44 7.256000e-02 -2.89902e-52 -1.46013e-43 -1.46013e-43 -45 7.456000e-02 -1.08625e-52 -1.40604e-43 -1.40604e-43 -46 7.656000e-02 -1.19143e-52 -1.35132e-43 -1.35132e-43 -47 7.856000e-02 -3.87284e-52 -1.29600e-43 -1.29600e-43 -48 8.056000e-02 -1.76399e-52 -1.24011e-43 -1.24011e-43 -49 8.256000e-02 9.167300e-53 -1.18367e-43 -1.18367e-43 -50 8.456000e-02 -1.40774e-52 -1.12671e-43 -1.12671e-43 -51 8.656000e-02 1.945441e-52 -1.06925e-43 -1.06925e-43 -52 8.856000e-02 -7.42845e-53 -1.01132e-43 -1.01132e-43 -53 9.056000e-02 -3.70259e-52 -9.52954e-44 -9.52954e-44 -54 9.256000e-02 -5.23530e-54 -8.94171e-44 -8.94171e-44 - -Index time V(1) V(2) V(3) --------------------------------------------------------------------------------- -55 9.456000e-02 1.749423e-52 -8.35001e-44 -8.35001e-44 -56 9.656000e-02 -1.18682e-52 -7.75471e-44 -7.75471e-44 -57 9.856000e-02 -3.13438e-53 -7.15610e-44 -7.15610e-44 -58 1.000000e-01 6.326077e-47 -6.71639e-44 -6.71639e-44 - - * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir - Transient Analysis Sat Jun 15 16:01:36 2019 --------------------------------------------------------------------------------- -Index time V(4) V(5) V(6) --------------------------------------------------------------------------------- -0 0.000000e+00 -2.80622e-43 -2.80622e-43 -1.93630e-118 -1 1.000000e-05 -2.80871e-43 -2.80871e-43 -1.52261e-59 -2 2.000000e-05 -2.80868e-43 -2.80868e-43 -1.52259e-59 -3 4.000000e-05 -2.80860e-43 -2.80860e-43 -1.52255e-59 -4 8.000000e-05 -2.80589e-43 -2.80589e-43 0.000000e+00 -5 1.600000e-04 -2.80543e-43 -2.80543e-43 0.000000e+00 -6 3.200000e-04 -2.80438e-43 -2.80438e-43 0.000000e+00 -7 6.400000e-04 -2.80203e-43 -2.80203e-43 0.000000e+00 -8 1.280000e-03 -2.79955e-43 -2.79955e-43 -3.03528e-59 -9 2.560000e-03 -2.78870e-43 -2.78870e-43 -1.51176e-59 -10 4.560000e-03 -2.76667e-43 -2.76667e-43 0.000000e+00 -11 6.560000e-03 -2.74650e-43 -2.74650e-43 0.000000e+00 -12 8.560000e-03 -2.72507e-43 -2.72507e-43 0.000000e+00 -13 1.056000e-02 -2.70239e-43 -2.70239e-43 0.000000e+00 -14 1.256000e-02 -2.67846e-43 -2.67846e-43 0.000000e+00 -15 1.456000e-02 -2.65331e-43 -2.65331e-43 0.000000e+00 -16 1.656000e-02 -2.62693e-43 -2.62693e-43 0.000000e+00 -17 1.856000e-02 -2.59936e-43 -2.59936e-43 0.000000e+00 -18 2.056000e-02 -2.57059e-43 -2.57059e-43 0.000000e+00 -19 2.256000e-02 -2.54064e-43 -2.54064e-43 0.000000e+00 -20 2.456000e-02 -2.50953e-43 -2.50953e-43 0.000000e+00 -21 2.656000e-02 -2.47727e-43 -2.47727e-43 0.000000e+00 -22 2.856000e-02 -2.44388e-43 -2.44388e-43 0.000000e+00 -23 3.056000e-02 -2.40937e-43 -2.40937e-43 0.000000e+00 -24 3.256000e-02 -2.37377e-43 -2.37377e-43 0.000000e+00 -25 3.456000e-02 -2.33707e-43 -2.33707e-43 0.000000e+00 -26 3.656000e-02 -2.29932e-43 -2.29932e-43 0.000000e+00 -27 3.856000e-02 -2.26051e-43 -2.26051e-43 0.000000e+00 -28 4.056000e-02 -2.22068e-43 -2.22068e-43 0.000000e+00 -29 4.256000e-02 -2.17983e-43 -2.17983e-43 0.000000e+00 -30 4.456000e-02 -2.13800e-43 -2.13800e-43 0.000000e+00 -31 4.656000e-02 -2.09519e-43 -2.09519e-43 0.000000e+00 -32 4.856000e-02 -2.05144e-43 -2.05144e-43 0.000000e+00 -33 5.056000e-02 -2.00675e-43 -2.00675e-43 0.000000e+00 -34 5.256000e-02 -1.96115e-43 -1.96115e-43 0.000000e+00 -35 5.456000e-02 -1.91467e-43 -1.91467e-43 0.000000e+00 -36 5.656000e-02 -1.86732e-43 -1.86732e-43 0.000000e+00 -37 5.856000e-02 -1.81913e-43 -1.81913e-43 0.000000e+00 -38 6.056000e-02 -1.77011e-43 -1.77011e-43 0.000000e+00 -39 6.256000e-02 -1.72030e-43 -1.72030e-43 0.000000e+00 -40 6.456000e-02 -1.66972e-43 -1.66972e-43 0.000000e+00 -41 6.656000e-02 -1.61839e-43 -1.61839e-43 0.000000e+00 -42 6.856000e-02 -1.56633e-43 -1.56633e-43 0.000000e+00 -43 7.056000e-02 -1.51357e-43 -1.51357e-43 0.000000e+00 -44 7.256000e-02 -1.46013e-43 -1.46013e-43 0.000000e+00 -45 7.456000e-02 -1.40604e-43 -1.40604e-43 0.000000e+00 -46 7.656000e-02 -1.35132e-43 -1.35132e-43 0.000000e+00 -47 7.856000e-02 -1.29600e-43 -1.29600e-43 0.000000e+00 -48 8.056000e-02 -1.24011e-43 -1.24011e-43 0.000000e+00 -49 8.256000e-02 -1.18367e-43 -1.18367e-43 0.000000e+00 -50 8.456000e-02 -1.12671e-43 -1.12671e-43 0.000000e+00 -51 8.656000e-02 -1.06925e-43 -1.06925e-43 0.000000e+00 -52 8.856000e-02 -1.01132e-43 -1.01132e-43 0.000000e+00 -53 9.056000e-02 -9.52954e-44 -9.52954e-44 0.000000e+00 -54 9.256000e-02 -8.94171e-44 -8.94171e-44 0.000000e+00 - -Index time V(4) V(5) V(6) --------------------------------------------------------------------------------- -55 9.456000e-02 -8.35001e-44 -8.35001e-44 0.000000e+00 -56 9.656000e-02 -7.75471e-44 -7.75471e-44 0.000000e+00 -57 9.856000e-02 -7.15610e-44 -7.15610e-44 0.000000e+00 -58 1.000000e-01 -6.71639e-44 -6.71639e-44 -3.64096e-60 - - * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir - Transient Analysis Sat Jun 15 16:01:36 2019 --------------------------------------------------------------------------------- -Index time V(7) --------------------------------------------------------------------------------- -0 0.000000e+00 -2.80622e-43 -1 1.000000e-05 -2.80871e-43 -2 2.000000e-05 -2.80868e-43 -3 4.000000e-05 -2.80860e-43 -4 8.000000e-05 -2.80589e-43 -5 1.600000e-04 -2.80543e-43 -6 3.200000e-04 -2.80438e-43 -7 6.400000e-04 -2.80203e-43 -8 1.280000e-03 -2.79955e-43 -9 2.560000e-03 -2.78870e-43 -10 4.560000e-03 -2.76667e-43 -11 6.560000e-03 -2.74650e-43 -12 8.560000e-03 -2.72507e-43 -13 1.056000e-02 -2.70239e-43 -14 1.256000e-02 -2.67846e-43 -15 1.456000e-02 -2.65331e-43 -16 1.656000e-02 -2.62693e-43 -17 1.856000e-02 -2.59936e-43 -18 2.056000e-02 -2.57059e-43 -19 2.256000e-02 -2.54064e-43 -20 2.456000e-02 -2.50953e-43 -21 2.656000e-02 -2.47727e-43 -22 2.856000e-02 -2.44388e-43 -23 3.056000e-02 -2.40937e-43 -24 3.256000e-02 -2.37377e-43 -25 3.456000e-02 -2.33707e-43 -26 3.656000e-02 -2.29932e-43 -27 3.856000e-02 -2.26051e-43 -28 4.056000e-02 -2.22068e-43 -29 4.256000e-02 -2.17983e-43 -30 4.456000e-02 -2.13800e-43 -31 4.656000e-02 -2.09519e-43 -32 4.856000e-02 -2.05144e-43 -33 5.056000e-02 -2.00675e-43 -34 5.256000e-02 -1.96115e-43 -35 5.456000e-02 -1.91467e-43 -36 5.656000e-02 -1.86732e-43 -37 5.856000e-02 -1.81913e-43 -38 6.056000e-02 -1.77011e-43 -39 6.256000e-02 -1.72030e-43 -40 6.456000e-02 -1.66972e-43 -41 6.656000e-02 -1.61839e-43 -42 6.856000e-02 -1.56633e-43 -43 7.056000e-02 -1.51357e-43 -44 7.256000e-02 -1.46013e-43 -45 7.456000e-02 -1.40604e-43 -46 7.656000e-02 -1.35132e-43 -47 7.856000e-02 -1.29600e-43 -48 8.056000e-02 -1.24011e-43 -49 8.256000e-02 -1.18367e-43 -50 8.456000e-02 -1.12671e-43 -51 8.656000e-02 -1.06925e-43 -52 8.856000e-02 -1.01132e-43 -53 9.056000e-02 -9.52954e-44 -54 9.256000e-02 -8.94171e-44 - -Index time V(7) --------------------------------------------------------------------------------- -55 9.456000e-02 -8.35001e-44 -56 9.656000e-02 -7.75471e-44 -57 9.856000e-02 -7.15610e-44 -58 1.000000e-01 -6.71639e-44 diff --git a/src/SubcircuitLibrary/ujt/ujt-cache.lib b/src/SubcircuitLibrary/ujt/ujt-cache.lib index e6fcb32b..ff75f664 100644 --- a/src/SubcircuitLibrary/ujt/ujt-cache.lib +++ b/src/SubcircuitLibrary/ujt/ujt-cache.lib @@ -20,23 +20,10 @@ X -c 4 50 -200 100 U 35 35 1 1 P ENDDRAW ENDDEF # -# GND -# -DEF GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# # NLDS # -DEF NLDS B 0 40 Y Y 1 F N -F0 "B" 0 0 60 H V C CNN +DEF NLDS BB 0 40 Y Y 1 F N +F0 "BB" 0 0 60 H V C CNN F1 "NLDS" 0 0 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN diff --git a/src/SubcircuitLibrary/ujt/ujt.cir b/src/SubcircuitLibrary/ujt/ujt.cir index 017c4845..e0e911d7 100644 --- a/src/SubcircuitLibrary/ujt/ujt.cir +++ b/src/SubcircuitLibrary/ujt/ujt.cir @@ -1,18 +1,18 @@ * /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir -* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jun 16 10:51:40 2019 +* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 * Sheet Name: / -R3 GND 6 1000k -C1 5 7 35p -R1 7 2 38.15 -R2 3 5 2.518k -U1 1 2 3 PORT -B1 5 7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) -D1 1 4 eSim_Diode -H1 6 GND 4 5 1k +R3 /0 /6 1000k +H1 /6 /0 /4 /5 1k +C1 /5 /7 35p +R1 /7 /2 38.15k +R2 /3 /5 2.518k +U1 /1 /2 /3 PORT +B1 /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) +D1 /1 /4 eSim_Diode .end diff --git a/src/SubcircuitLibrary/ujt/ujt.cir.out b/src/SubcircuitLibrary/ujt/ujt.cir.out index c3186f1c..2045c539 100644 --- a/src/SubcircuitLibrary/ujt/ujt.cir.out +++ b/src/SubcircuitLibrary/ujt/ujt.cir.out @@ -1,17 +1,17 @@ * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir .include emitter.lib -r3 gnd 6 1000k -c1 5 7 35p -r1 7 2 38.15 -r2 3 5 2.518k -* u1 1 2 3 port -b1 5 7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) -d1 1 4 emitter +r3 /0 /6 1000k * h1 -Vh1 4 5 0 -h1 6 gnd Vh1 1k -.tran 5e-06 100e-03 0e-03 +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +* u1 /1 /2 /3 port +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k +.tran 5e-03 100e-03 0e-03 * Control Statements .control diff --git a/src/SubcircuitLibrary/ujt/ujt.sch b/src/SubcircuitLibrary/ujt/ujt.sch index c1eb98f1..a82bddf7 100644 --- a/src/SubcircuitLibrary/ujt/ujt.sch +++ b/src/SubcircuitLibrary/ujt/ujt.sch @@ -28,15 +28,26 @@ $EndDescr $Comp L eSim_R R3 U 1 1 5CF5F733 -P 7400 2850 -F 0 "R3" H 7450 2980 50 0000 C CNN -F 1 "1000k" H 7450 2900 50 0000 C CNN -F 2 "" H 7450 2830 30 0000 C CNN -F 3 "" V 7450 2900 30 0000 C CNN - 1 7400 2850 +P 6650 3400 +F 0 "R3" H 6700 3530 50 0000 C CNN +F 1 "1000k" H 6700 3450 50 0000 C CNN +F 2 "" H 6700 3380 30 0000 C CNN +F 3 "" V 6700 3450 30 0000 C CNN + 1 6650 3400 0 1 -1 0 $EndComp $Comp +L CCVS H1 +U 1 1 5CF5F77B +P 6150 3350 +F 0 "H1" H 6150 3500 50 0000 C CNN +F 1 "1k" H 5950 3300 50 0000 C CNN +F 2 "" H 6150 3350 60 0000 C CNN +F 3 "" H 6150 3350 60 0000 C CNN + 1 6150 3350 + 0 1 1 0 +$EndComp +$Comp L eSim_C C1 U 1 1 5CF61B3A P 5150 4700 @@ -52,7 +63,7 @@ L eSim_R R1 U 1 1 5CF6211F P 4300 4850 F 0 "R1" H 4350 4980 50 0000 C CNN -F 1 "38.15" H 4350 4900 50 0000 C CNN +F 1 "38.15k" H 4350 4900 50 0000 C CNN F 2 "" H 4350 4830 30 0000 C CNN F 3 "" V 4350 4900 30 0000 C CNN 1 4300 4850 @@ -83,12 +94,12 @@ $EndComp $Comp L PORT U1 U 1 1 5CF689AD -P 5950 1200 -F 0 "U1" H 6000 1300 30 0000 C CNN -F 1 "PORT" H 5950 1200 30 0000 C CNN -F 2 "" H 5950 1200 60 0000 C CNN -F 3 "" H 5950 1200 60 0000 C CNN - 1 5950 1200 +P 5950 2200 +F 0 "U1" H 6000 2300 30 0000 C CNN +F 1 "PORT" H 5950 2200 30 0000 C CNN +F 2 "" H 5950 2200 60 0000 C CNN +F 3 "" H 5950 2200 60 0000 C CNN + 1 5950 2200 0 1 1 0 $EndComp $Comp @@ -102,6 +113,16 @@ F 3 "" H 4600 3000 60 0000 C CNN 3 4600 3000 0 1 1 0 $EndComp +Text Label 5600 4100 0 60 ~ 0 +5 +Text Label 5950 3150 0 60 ~ 0 +4 +Text Label 5950 2600 0 60 ~ 0 +1 +Text Label 6450 3050 0 60 ~ 0 +6 +Text Label 6450 3650 0 60 ~ 0 +0 $Comp L NLDS B1 U 1 1 5CFD2C88 @@ -113,37 +134,54 @@ F 3 "" H 5950 4800 60 0000 C CNN 1 5950 4800 1 0 0 -1 $EndComp +Text Label 5350 5250 0 60 ~ 0 +7 +Text Label 4600 3450 0 60 ~ 0 +3 +Text Label 4250 4500 0 60 ~ 0 +2 $Comp L eSim_Diode D1 U 1 1 5CFF8BB7 -P 5950 1850 -F 0 "D1" H 5950 1950 50 0000 C CNN -F 1 "eSim_Diode" H 5950 1750 50 0000 C CNN -F 2 "" H 5950 1850 60 0000 C CNN -F 3 "" H 5950 1850 60 0000 C CNN - 1 5950 1850 +P 5950 2850 +F 0 "D1" H 5950 2950 50 0000 C CNN +F 1 "eSim_Diode" H 5950 2750 50 0000 C CNN +F 2 "" H 5950 2850 60 0000 C CNN +F 3 "" H 5950 2850 60 0000 C CNN + 1 5950 2850 0 1 1 0 $EndComp Wire Wire Line - 6950 2500 7450 2500 + 6200 3050 6700 3050 +Wire Wire Line + 6700 3050 6700 3200 +Wire Wire Line + 6200 3650 6300 3650 +Wire Wire Line + 6300 3650 6700 3650 Wire Wire Line - 7450 2500 7450 2650 + 5950 2450 5950 2700 Wire Wire Line - 6950 3100 7450 3100 + 5950 3000 5950 3300 Wire Wire Line - 5950 1450 5950 1700 + 5950 3400 5950 3850 Wire Wire Line - 5950 2000 5950 2750 + 5950 3850 5950 4100 Wire Wire Line - 5950 2850 5950 4450 + 5950 4100 5950 4450 Wire Wire Line 5150 4100 5150 4550 Wire Wire Line - 4600 4100 5950 4100 + 4600 4100 5150 4100 +Wire Wire Line + 5150 4100 5950 4100 +Connection ~ 5950 4100 Wire Wire Line 5150 4850 5150 5250 Wire Wire Line - 4250 5250 5950 5250 + 4250 5250 5150 5250 +Wire Wire Line + 5150 5250 5950 5250 Wire Wire Line 4250 5250 4250 4950 Wire Wire Line @@ -157,49 +195,5 @@ Wire Wire Line 5950 5250 5950 5150 Connection ~ 5150 5250 Wire Wire Line - 7450 3100 7450 2950 -Connection ~ 5950 4100 -$Comp -L CCVS H1 -U 1 1 5D04A7ED -P 6900 2800 -F 0 "H1" H 6900 2950 50 0000 C CNN -F 1 "1k" H 6700 2750 50 0000 C CNN -F 2 "" H 6900 2800 60 0000 C CNN -F 3 "" H 6900 2800 60 0000 C CNN - 1 6900 2800 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR01 -U 1 1 5D04C560 -P 7150 3150 -F 0 "#PWR01" H 7150 2900 50 0001 C CNN -F 1 "GND" H 7150 3000 50 0000 C CNN -F 2 "" H 7150 3150 50 0001 C CNN -F 3 "" H 7150 3150 50 0001 C CNN - 1 7150 3150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7150 3150 7150 3100 -Connection ~ 7150 3100 -Wire Wire Line - 5950 2750 6700 2750 -Wire Wire Line - 6700 2850 5950 2850 -Text GLabel 5950 1550 0 60 Input ~ 0 -1 -Text GLabel 5950 2200 0 60 Input ~ 0 -4 -Text GLabel 5950 3500 0 60 Input ~ 0 -5 -Text GLabel 5700 5250 3 60 Input ~ 0 -7 -Text GLabel 4250 4550 0 60 Input ~ 0 -2 -Text GLabel 4600 3350 0 60 Input ~ 0 -3 -Text GLabel 7200 2500 1 60 Input ~ 0 -6 + 6700 3650 6700 3500 $EndSCHEMATC diff --git a/src/SubcircuitLibrary/ujt/ujt.sub b/src/SubcircuitLibrary/ujt/ujt.sub index e86745b5..2fb1db35 100644 --- a/src/SubcircuitLibrary/ujt/ujt.sub +++ b/src/SubcircuitLibrary/ujt/ujt.sub @@ -1,16 +1,16 @@ * Subcircuit ujt -.subckt ujt 1 2 3 +.subckt ujt /1 /2 /3 * /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir .include emitter.lib -r3 gnd 6 1000k -c1 5 7 35p -r1 7 2 38.15 -r2 3 5 2.518k -b1 5 7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) -d1 1 4 emitter +r3 /0 /6 1000k * h1 -Vh1 4 5 0 -h1 6 gnd Vh1 1k +c1 /5 /7 35p +r1 /7 /2 38.15k +r2 /3 /5 2.518k +b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) +d1 /1 /4 emitter +Vh1 /4 /5 0 +h1 /6 /0 Vh1 1k * Control Statements .ends ujt
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml index 993933d5..4468b395 100644 --- a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml +++ b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml @@ -1 +1 @@ -<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file +<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/browser/Welcome.py b/src/browser/Welcome.py index f9f273df..2d91bcc9 100644 --- a/src/browser/Welcome.py +++ b/src/browser/Welcome.py @@ -2,7 +2,10 @@ from PyQt4 import QtGui, QtCore class Welcome(QtGui.QWidget): - """This class contains content of dock area part of initial esim Window.""" + """ + This class contains content of dock area part of initial esim Window. + It creates Welcome page of eSim. + """ def __init__(self): QtGui.QWidget.__init__(self) diff --git a/src/browser/pages/welcome.html b/src/browser/pages/welcome.html index 3c48a85a..6c4a6d11 100644 --- a/src/browser/pages/welcome.html +++ b/src/browser/pages/welcome.html @@ -39,7 +39,7 @@ pre{ <center><img src="../../../images/logo.png" alt="eSim logo" height="100" width="100"></center> <br/> <p> -<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>) and Ngspice(<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>). eSim source is released under <b>GNU General Public License.</b> +<b>eSim</b> is an open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad (<a href=http://www.kicad-pcb.org>http://www.kicad-pcb.org</a>), Ngspice (<a href=http://ngspice.sourceforge.net>http://ngspice.sourceforge.net</a>) and GHDL (<a href=http://ghdl.free.fr/>http://ghdl.free.fr/</a>). eSim source is released under <b>GNU General Public License.</b> </p> <br/> <p> diff --git a/src/configuration/Appconfig.py b/src/configuration/Appconfig.py index 2ab8743e..8a29ad72 100644 --- a/src/configuration/Appconfig.py +++ b/src/configuration/Appconfig.py @@ -12,11 +12,10 @@ # AUTHOR: Fahim Khan, fahim.elex@gmail.com # MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. -# CREATED: Tuesday 24 Feb 2015 -# REVISION: Wednesday 18 Dec 2019 +# CREATED: Tuesday 24 February 2015 +# REVISION: Friday 14 February 2020 # ========================================================================= - from PyQt4 import QtGui import os import json @@ -31,7 +30,7 @@ class Appconfig(QtGui.QWidget): This class also contains function for - Printing error. - Showing warnings. - - Dispalying information. + - Displaying information. """ # Home directory @@ -42,9 +41,9 @@ class Appconfig(QtGui.QWidget): # Current Subcircuit detail current_subcircuit = {"SubcircuitName": None} # Workspace detail - workspace_text = '''eSim stores your project in a folder called a \ - eSim-Workspace. You can choose a different workspace folder to use\ - for this session.''' + workspace_text = "eSim stores your project in a folder called " + workspace_text += "eSim-Workspace. You can choose a different " + workspace_text += "workspace folder to use for this session." procThread_list = [] proc_dict = {} # holds the pids of all external windows corresponds to the current project @@ -63,8 +62,23 @@ class Appconfig(QtGui.QWidget): # Try catch added, since eSim cannot be accessed under parser for Win10 try: modelica_map_json = parser_esim.get('eSim', 'MODELICA_MAP_JSON') - except BaseException: - print("Cannot access Modelica's map_json path --- .esim folder") + except BaseException as e: + print("===============================================") + print("Cannot access Modelica map file --- .esim folder") + print(str(e)) + print("===============================================") + + # Open file and read KiCad config path + try: + file = open('../supportFiles/kicad_config_path.txt', 'r') + kicad_path = file.read().rstrip() + file.close() + except BaseException as e: + kicad_path = None + print("===============================================") + print("Cannot access kicad path file --- supportFiles") + print(str(e)) + print("===============================================") try: project_explorer = json.load(open(dictPath)) @@ -76,8 +90,8 @@ class Appconfig(QtGui.QWidget): super(Appconfig, self).__init__() # Application Details self._APPLICATION = 'eSim' - self._VERSION = 'v1.1' - self._AUTHOR = 'Fahim' + self._VERSION = 'v2.0.0' + self._AUTHOR = 'Fahim, Rahul' # Application geometry setting self._app_xpos = 100 diff --git a/src/configuration/browser/UserManual.py b/src/configuration/browser/UserManual.py deleted file mode 100644 index 3bcfbace..00000000 --- a/src/configuration/browser/UserManual.py +++ /dev/null @@ -1,20 +0,0 @@ -from PyQt4 import QtGui -import webbrowser - - -class UserManual(QtGui.QWidget): - """ - This class creates Welcome page of eSim. - """ - - def __init__(self): - QtGui.QWidget.__init__(self) - - self.vlayout = QtGui.QVBoxLayout() - - self.url = "../browser/pages/User-Manual/eSim.html" - self.test = webbrowser.open( - "../browser/pages/User-Manual/eSim.html", new=2) - - self.setLayout(self.vlayout) - self.show() diff --git a/src/deviceModelLibrary/Diode/D.lib b/src/deviceModelLibrary/Diode/D.lib index 974dd402..8a7fb4da 100644 --- a/src/deviceModelLibrary/Diode/D.lib +++ b/src/deviceModelLibrary/Diode/D.lib @@ -1 +1,2 @@ -.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 ) +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/deviceModelLibrary/Diode/LED.lib b/src/deviceModelLibrary/Diode/LED.lib new file mode 100644 index 00000000..000831b2 --- /dev/null +++ b/src/deviceModelLibrary/Diode/LED.lib @@ -0,0 +1,2 @@ +.model LED D(is=4.36625E-25 rs=3.00014 n=1.38167 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/deviceModelLibrary/Diode/LED.xml b/src/deviceModelLibrary/Diode/LED.xml new file mode 100644 index 00000000..91eb9169 --- /dev/null +++ b/src/deviceModelLibrary/Diode/LED.xml @@ -0,0 +1 @@ +<library><model_name>D</model_name><ref_model>LED</ref_model><param><cjo>1.700E-12</cjo><rs>4.755E-01</rs><is>2.495E-09</is><m>1.959E-01</m><n>1.679E00</n><bv>1.000E02</bv><ibv>1.000E-04</ibv><tt>3.030E-09</tt><vj>1</vj></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Diode/PowerDiode.lib b/src/deviceModelLibrary/Diode/PowerDiode.lib index d6fb6469..a2f61dce 100644 --- a/src/deviceModelLibrary/Diode/PowerDiode.lib +++ b/src/deviceModelLibrary/Diode/PowerDiode.lib @@ -1 +1,20 @@ -.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m ) +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/Diode/ZenerD1N750.lib b/src/deviceModelLibrary/Diode/ZenerD1N750.lib index ec968783..890c37fe 100644 --- a/src/deviceModelLibrary/Diode/ZenerD1N750.lib +++ b/src/deviceModelLibrary/Diode/ZenerD1N750.lib @@ -1 +1,3 @@ -.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m Nbvl=14.976 Tbv1=-21.277u ) +.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516 ++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m ++ Nbvl=14.976 Tbv1=-21.277u) diff --git a/src/deviceModelLibrary/IGBT/NIGBT.lib b/src/deviceModelLibrary/IGBT/NIGBT.lib index 67cdd9ca..86cd1b4e 100644 --- a/src/deviceModelLibrary/IGBT/NIGBT.lib +++ b/src/deviceModelLibrary/IGBT/NIGBT.lib @@ -1 +1,11 @@ -.MODEL IXGH40N60 NIGBT( TAU=287.56E-9 KF=.36047 AREA=37.500E-6 AGD=18.750E-6 KP=50.034 VT=4.1822 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 ) +.MODEL IXGH40N60 NIGBT( ++ TAU=287.56E-9 ++ KF=.36047 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ KP=50.034 ++ VT=4.1822 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570 +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/IGBT/PIGBT.lib b/src/deviceModelLibrary/IGBT/PIGBT.lib index ddf3c779..d4f9e814 100644 --- a/src/deviceModelLibrary/IGBT/PIGBT.lib +++ b/src/deviceModelLibrary/IGBT/PIGBT.lib @@ -1 +1,10 @@ -.MODEL IXGH40N60 PIGBT( TAU=287.56E-9 KP=50.034 AREA=37.500E-6 AGD=18.750E-6 VT=4.1822 KF=.36047 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 ) +.MODEL IXGH40N60 PIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/src/deviceModelLibrary/JFET/NJF.lib b/src/deviceModelLibrary/JFET/NJF.lib index a9ea544f..dbb2cbae 100644 --- a/src/deviceModelLibrary/JFET/NJF.lib +++ b/src/deviceModelLibrary/JFET/NJF.lib @@ -1 +1,4 @@ -.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 ) +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/src/deviceModelLibrary/JFET/PJF.lib b/src/deviceModelLibrary/JFET/PJF.lib index 95297dea..5589571d 100644 --- a/src/deviceModelLibrary/JFET/PJF.lib +++ b/src/deviceModelLibrary/JFET/PJF.lib @@ -1 +1,5 @@ -.model J2N3820 PJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 ) +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib index a38a9673..2e6f4635 100644 --- a/src/deviceModelLibrary/MOS/NMOS-0.5um.lib +++ b/src/deviceModelLibrary/MOS/NMOS-0.5um.lib @@ -1 +1,6 @@ -.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 NSUB=1.40E17 ) +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/MOS/NMOS-180nm.lib b/src/deviceModelLibrary/MOS/NMOS-180nm.lib index bb481014..51e9b119 100644 --- a/src/deviceModelLibrary/MOS/NMOS-180nm.lib +++ b/src/deviceModelLibrary/MOS/NMOS-180nm.lib @@ -1 +1,13 @@ -.model CMOSN NMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3 ) +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/src/deviceModelLibrary/MOS/NMOS-5um.lib b/src/deviceModelLibrary/MOS/NMOS-5um.lib index 5260b17a..a237e1fe 100644 --- a/src/deviceModelLibrary/MOS/NMOS-5um.lib +++ b/src/deviceModelLibrary/MOS/NMOS-5um.lib @@ -1,3 +1,5 @@ * 5um technology -.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 Level=1 Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib index 12ae53b8..848e8b05 100644 --- a/src/deviceModelLibrary/MOS/PMOS-0.5um.lib +++ b/src/deviceModelLibrary/MOS/PMOS-0.5um.lib @@ -1 +1,6 @@ -.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 NSUB=1.0E17 ) +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/MOS/PMOS-180nm.lib b/src/deviceModelLibrary/MOS/PMOS-180nm.lib index 998d1885..032b5b95 100644 --- a/src/deviceModelLibrary/MOS/PMOS-180nm.lib +++ b/src/deviceModelLibrary/MOS/PMOS-180nm.lib @@ -1 +1,11 @@ -.model CMOSP PMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3 ) +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/src/deviceModelLibrary/MOS/PMOS-5um.lib b/src/deviceModelLibrary/MOS/PMOS-5um.lib index 1d808f0b..9c3ed976 100644 --- a/src/deviceModelLibrary/MOS/PMOS-5um.lib +++ b/src/deviceModelLibrary/MOS/PMOS-5um.lib @@ -1,3 +1,5 @@ *5um technology -.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 Level=1 Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/Misc/CORE.lib b/src/deviceModelLibrary/Misc/CORE.lib index df7539a5..a7581029 100644 --- a/src/deviceModelLibrary/Misc/CORE.lib +++ b/src/deviceModelLibrary/Misc/CORE.lib @@ -1 +1,9 @@ -.MODEL K3019PL_3C8 Core( A=44.82 C=.4112 abc=123 Area=1.38 K=25.74 MS=415.2K Path=4.52 ) +.MODEL K3019PL_3C8 Core( ++ A=44.82 ++ C=.4112 ++ abc=123 ++ Area=1.38 ++ K=25.74 ++ MS=415.2K ++ Path=4.52 +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/CORE.lib b/src/deviceModelLibrary/Templates/CORE.lib index df7539a5..a7581029 100644 --- a/src/deviceModelLibrary/Templates/CORE.lib +++ b/src/deviceModelLibrary/Templates/CORE.lib @@ -1 +1,9 @@ -.MODEL K3019PL_3C8 Core( A=44.82 C=.4112 abc=123 Area=1.38 K=25.74 MS=415.2K Path=4.52 ) +.MODEL K3019PL_3C8 Core( ++ A=44.82 ++ C=.4112 ++ abc=123 ++ Area=1.38 ++ K=25.74 ++ MS=415.2K ++ Path=4.52 +)
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/D.lib b/src/deviceModelLibrary/Templates/D.lib index 974dd402..8a7fb4da 100644 --- a/src/deviceModelLibrary/Templates/D.lib +++ b/src/deviceModelLibrary/Templates/D.lib @@ -1 +1,2 @@ -.model 1n4148 D( is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04 ) +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/src/deviceModelLibrary/Templates/NIGBT.lib b/src/deviceModelLibrary/Templates/NIGBT.lib index 67cdd9ca..8c09dcbc 100644 --- a/src/deviceModelLibrary/Templates/NIGBT.lib +++ b/src/deviceModelLibrary/Templates/NIGBT.lib @@ -1 +1,10 @@ -.MODEL IXGH40N60 NIGBT( TAU=287.56E-9 KF=.36047 AREA=37.500E-6 AGD=18.750E-6 KP=50.034 VT=4.1822 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 ) +.MODEL IXGH40N60 NIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/src/deviceModelLibrary/Templates/NJF.lib b/src/deviceModelLibrary/Templates/NJF.lib index a9ea544f..dbb2cbae 100644 --- a/src/deviceModelLibrary/Templates/NJF.lib +++ b/src/deviceModelLibrary/Templates/NJF.lib @@ -1 +1,4 @@ -.model J2N3819 NJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 ) +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib index a38a9673..2e6f4635 100644 --- a/src/deviceModelLibrary/Templates/NMOS-0.5um.lib +++ b/src/deviceModelLibrary/Templates/NMOS-0.5um.lib @@ -1 +1,6 @@ -.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 NSUB=1.40E17 ) +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/NMOS-180nm.lib b/src/deviceModelLibrary/Templates/NMOS-180nm.lib index bb481014..51e9b119 100644 --- a/src/deviceModelLibrary/Templates/NMOS-180nm.lib +++ b/src/deviceModelLibrary/Templates/NMOS-180nm.lib @@ -1 +1,13 @@ -.model CMOSN NMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3 ) +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/src/deviceModelLibrary/Templates/NMOS-5um.lib b/src/deviceModelLibrary/Templates/NMOS-5um.lib index 5260b17a..a237e1fe 100644 --- a/src/deviceModelLibrary/Templates/NMOS-5um.lib +++ b/src/deviceModelLibrary/Templates/NMOS-5um.lib @@ -1,3 +1,5 @@ * 5um technology -.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 Level=1 Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/Templates/NPN.lib b/src/deviceModelLibrary/Templates/NPN.lib index 382b5380..6509fe7a 100644 --- a/src/deviceModelLibrary/Templates/NPN.lib +++ b/src/deviceModelLibrary/Templates/NPN.lib @@ -1 +1,4 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 ) +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/deviceModelLibrary/Templates/PIGBT.lib b/src/deviceModelLibrary/Templates/PIGBT.lib index ddf3c779..d4f9e814 100644 --- a/src/deviceModelLibrary/Templates/PIGBT.lib +++ b/src/deviceModelLibrary/Templates/PIGBT.lib @@ -1 +1,10 @@ -.MODEL IXGH40N60 PIGBT( TAU=287.56E-9 KP=50.034 AREA=37.500E-6 AGD=18.750E-6 VT=4.1822 KF=.36047 CGS=31.942E-9 COXD=53.188E-9 VTD=2.6570 ) +.MODEL IXGH40N60 PIGBT ( ++ TAU=287.56E-9 ++ KP=50.034 ++ AREA=37.500E-6 ++ AGD=18.750E-6 ++ VT=4.1822 ++ KF=.36047 ++ CGS=31.942E-9 ++ COXD=53.188E-9 ++ VTD=2.6570) diff --git a/src/deviceModelLibrary/Templates/PJF.lib b/src/deviceModelLibrary/Templates/PJF.lib index 95297dea..5589571d 100644 --- a/src/deviceModelLibrary/Templates/PJF.lib +++ b/src/deviceModelLibrary/Templates/PJF.lib @@ -1 +1,5 @@ -.model J2N3820 PJF( Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 Af=1 ) +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib index 12ae53b8..848e8b05 100644 --- a/src/deviceModelLibrary/Templates/PMOS-0.5um.lib +++ b/src/deviceModelLibrary/Templates/PMOS-0.5um.lib @@ -1 +1,6 @@ -.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 NSUB=1.0E17 ) +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/src/deviceModelLibrary/Templates/PMOS-180nm.lib b/src/deviceModelLibrary/Templates/PMOS-180nm.lib index 998d1885..032b5b95 100644 --- a/src/deviceModelLibrary/Templates/PMOS-180nm.lib +++ b/src/deviceModelLibrary/Templates/PMOS-180nm.lib @@ -1 +1,11 @@ -.model CMOSP PMOS( LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3 ) +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/src/deviceModelLibrary/Templates/PMOS-5um.lib b/src/deviceModelLibrary/Templates/PMOS-5um.lib index 1d808f0b..9c3ed976 100644 --- a/src/deviceModelLibrary/Templates/PMOS-5um.lib +++ b/src/deviceModelLibrary/Templates/PMOS-5um.lib @@ -1,3 +1,5 @@ *5um technology -.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 Level=1 Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/src/deviceModelLibrary/Templates/PNP.lib b/src/deviceModelLibrary/Templates/PNP.lib index 23fe9d0f..7edda0ea 100644 --- a/src/deviceModelLibrary/Templates/PNP.lib +++ b/src/deviceModelLibrary/Templates/PNP.lib @@ -1 +1,4 @@ -.model Q2N2907A PNP( Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10 ) +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/deviceModelLibrary/Transistor/BC547B.lib b/src/deviceModelLibrary/Transistor/BC547B.lib new file mode 100644 index 00000000..723537a7 --- /dev/null +++ b/src/deviceModelLibrary/Transistor/BC547B.lib @@ -0,0 +1 @@ +.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8) diff --git a/src/deviceModelLibrary/Transistor/BC547B.xml b/src/deviceModelLibrary/Transistor/BC547B.xml new file mode 100644 index 00000000..da06e5c4 --- /dev/null +++ b/src/deviceModelLibrary/Transistor/BC547B.xml @@ -0,0 +1 @@ +<library><model_name>NPN</model_name><ref_model>BC547B</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Isc>0 </Isc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400 </Bf><Fc>.5 </Fc><Ise>14.34f </Ise><Br>6.092 </Br><Ikf>.2847 </Ikf><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Vjc>.75 </Vjc><Vje>.75 </Vje><Xtf>3 </Xtf><Itf>.6 </Itf><Is>14.34f </Is><Eg>1.11 </Eg></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Transistor/NPN.lib b/src/deviceModelLibrary/Transistor/NPN.lib index 382b5380..6509fe7a 100644 --- a/src/deviceModelLibrary/Transistor/NPN.lib +++ b/src/deviceModelLibrary/Transistor/NPN.lib @@ -1 +1,4 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 Rb=10 ) +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/deviceModelLibrary/Transistor/NPN.xml b/src/deviceModelLibrary/Transistor/NPN.xml index b2698bb1..ee2abcbc 100644 --- a/src/deviceModelLibrary/Transistor/NPN.xml +++ b/src/deviceModelLibrary/Transistor/NPN.xml @@ -1,33 +1 @@ -<library> -<model_name>NPN</model_name> -<ref_model>Q2N2222</ref_model> -<param> -<Is>14.34f </Is> -<Xti>3 </Xti> -<Eg>1.11 </Eg> -<Vaf>74.03 </Vaf> -<Bf>400 </Bf> -<Ne>1.307 </Ne> -<Ise>14.34f </Ise> -<Ikf>.2847 </Ikf> -<Xtb>1.5 </Xtb> -<Br>6.092 </Br> -<Nc>2 </Nc> -<Isc>0 </Isc> -<Ikr>0 </Ikr> -<Rc>1 </Rc> -<Cjc>7.306p </Cjc> -<Mjc>.3416 </Mjc> -<Vjc>.75 </Vjc> -<Fc>.5 </Fc> -<Cje>22.01p </Cje> -<Mje>.377 </Mje> -<Vje>.75 </Vje> -<Tr>46.91n </Tr> -<Tf>411.1p </Tf> -<Itf>.6 </Itf> -<Vtf>1.7 </Vtf> -<Xtf>3 </Xtf> -<Rb>10 </Rb> -</param> -</library> +<library><model_name>NPN</model_name><ref_model>Q2N2222</ref_model><param><Vtf>1.7 </Vtf><Cjc>7.306p </Cjc><Nc>2 </Nc><Tr>46.91n </Tr><Ne>1.307 </Ne><Cje>22.01p </Cje><Vjc>.75 </Vjc><Xtb>1.5 </Xtb><Rb>10 </Rb><Rc>1 </Rc><Tf>411.1p </Tf><Xti>3 </Xti><Ikr>0 </Ikr><Bf>400</Bf><Fc>.5 </Fc><Ikf>.2847 </Ikf><Br>6.092 </Br><Mje>.377 </Mje><Mjc>.3416 </Mjc><Vaf>74.03 </Vaf><Isc>0 </Isc><Ise>14.34f </Ise><Xtf>3 </Xtf><Vje>.75 </Vje><Is>14.34f </Is><Itf>.6 </Itf><Eg>1.11 </Eg></param></library>
\ No newline at end of file diff --git a/src/deviceModelLibrary/Transistor/PNP.lib b/src/deviceModelLibrary/Transistor/PNP.lib index 23fe9d0f..7edda0ea 100644 --- a/src/deviceModelLibrary/Transistor/PNP.lib +++ b/src/deviceModelLibrary/Transistor/PNP.lib @@ -1 +1,4 @@ -.model Q2N2907A PNP( Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10 ) +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/deviceModelLibrary/User Libraries/userDiode.lib b/src/deviceModelLibrary/User Libraries/userDiode.lib index 89b96f4a..ef18bb50 100644 --- a/src/deviceModelLibrary/User Libraries/userDiode.lib +++ b/src/deviceModelLibrary/User Libraries/userDiode.lib @@ -1 +1,20 @@ -.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m ) +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/frontEnd/Application.py b/src/frontEnd/Application.py index 8973501d..6cb25e80 100644 --- a/src/frontEnd/Application.py +++ b/src/frontEnd/Application.py @@ -12,11 +12,10 @@ # AUTHOR: Fahim Khan, fahim.elex@gmail.com # MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. -# CREATED: Tuesday 24 Feb 2015 -# REVISION: Wednesday 18 Dec 2019 +# CREATED: Tuesday 24 February 2015 +# REVISION: Friday 14 February 2020 # ========================================================================= - import pathmagic # noqa from PyQt4 import QtGui, QtCore from configuration.Appconfig import Appconfig @@ -32,11 +31,12 @@ import time from PyQt4.Qt import QSize import sys import os +import shutil # Its our main window of application. class Application(QtGui.QMainWindow): - """This class initializes all objects used in this file(Application.py).""" + """This class initializes all objects used in this file.""" global project_name def __init__(self, *args): @@ -45,6 +45,9 @@ class Application(QtGui.QMainWindow): # Calling __init__ of super class QtGui.QMainWindow.__init__(self, *args) + #Flag for mode of operation. Default is set to offline mode. + self.online_flag = False + # Creating require Object self.obj_workspace = Workspace.Workspace() self.obj_Mainview = MainView() @@ -62,57 +65,64 @@ class Application(QtGui.QMainWindow): self.setWindowTitle(self.obj_appconfig._APPLICATION) self.showMaximized() self.setWindowIcon(QtGui.QIcon('../../images/logo.png')) - # self.show() + self.systemTrayIcon = QtGui.QSystemTrayIcon(self) self.systemTrayIcon.setIcon(QtGui.QIcon('../../images/logo.png')) self.systemTrayIcon.setVisible(True) - # This function initializes Tool Bars def initToolBar(self): """ - In this function we are setting icons, short-cuts,and - defining functonality for: - - - Top-tool-bar (New project, Open project, Close project,\ - Help option ) - - Left-tool-bar (Open Schematic, Convert KiCad to NgSpice,\ - Simuation, Model Editor, Subcircuit, NGHDL, Modelica\ - Converter, OM Optimisation ) + This function initializes Tool Bars. + It setups the icons, short-cuts and defining functonality for: + + - Top-tool-bar (New project, Open project, Close project, \ + Mode switch, Help option) + - Left-tool-bar (Open Schematic, Convert KiCad to NgSpice, \ + Simuation, Model Editor, Subcircuit, NGHDL, Modelica \ + Converter, OM Optimisation) """ # Top Tool bar self.newproj = QtGui.QAction( QtGui.QIcon('../../images/newProject.png'), - '<b>New Project</b>', - self) + '<b>New Project</b>', self + ) self.newproj.setShortcut('Ctrl+N') self.newproj.triggered.connect(self.new_project) - # self.newproj.connect(self.newproj, QtCore.SIGNAL('triggered()'), - # self, QtCore.SLOT(self.new_project())) self.openproj = QtGui.QAction( QtGui.QIcon('../../images/openProject.png'), - '<b>Open Project</b>', - self) + '<b>Open Project</b>', self + ) self.openproj.setShortcut('Ctrl+O') self.openproj.triggered.connect(self.open_project) self.closeproj = QtGui.QAction( QtGui.QIcon('../../images/closeProject.png'), - '<b>Close Project</b>', - self) + '<b>Close Project</b>', self + ) self.closeproj.setShortcut('Ctrl+X') self.closeproj.triggered.connect(self.close_project) + self.switchmode = QtGui.QAction( + QtGui.QIcon('../../images/disable.png'), + '<b>Mode switching has been disabled. Relaunch ' + + 'eSim to fix any config issues</b>', self + ) + self.validate_mode() + self.switchmode.setShortcut('Ctrl+G') + self.switchmode.triggered.connect(self.change_mode) + self.helpfile = QtGui.QAction( - QtGui.QIcon('../../images/helpProject.png'), '<b>Help</b>', self) + QtGui.QIcon('../../images/helpProject.png'), '<b>Help</b>', self + ) self.helpfile.setShortcut('Ctrl+H') self.helpfile.triggered.connect(self.help_project) self.topToolbar = self.addToolBar('Top Tool Bar') self.topToolbar.addAction(self.newproj) self.topToolbar.addAction(self.openproj) - self.topToolbar.addAction(self.closeproj) + self.topToolbar.addAction(self.switchmode) self.topToolbar.addAction(self.helpfile) # This part is setting fossee logo to the right @@ -125,9 +135,8 @@ class Application(QtGui.QMainWindow): self.logo = QtGui.QLabel() self.logopic = QtGui.QPixmap( os.path.join( - os.path.abspath('../..'), - 'images', - 'fosseeLogo.png')) + os.path.abspath('../..'), 'images', 'fosseeLogo.png' + )) self.logopic = self.logopic.scaled( QSize(150, 150), QtCore.Qt.KeepAspectRatio) self.logo.setPixmap(self.logopic) @@ -137,50 +146,48 @@ class Application(QtGui.QMainWindow): # Left Tool bar Action Widget self.kicad = QtGui.QAction( QtGui.QIcon('../../images/kicad.png'), - '<b>Open Schematic</b>', - self) + '<b>Open Schematic</b>', self + ) self.kicad.triggered.connect(self.obj_kicad.openSchematic) self.conversion = QtGui.QAction( QtGui.QIcon('../../images/ki-ng.png'), - '<b>Convert Kicad to Ngspice</b>', - self) + '<b>Convert Kicad to Ngspice</b>', self + ) self.conversion.triggered.connect(self.obj_kicad.openKicadToNgspice) self.ngspice = QtGui.QAction( - QtGui.QIcon('../../images/ngspice.png'), - '<b>Simulation</b>', - self) + QtGui.QIcon('../../images/ngspice.png'), '<b>Simulation</b>', self + ) self.ngspice.triggered.connect(self.open_ngspice) self.model = QtGui.QAction( QtGui.QIcon('../../images/model.png'), - '<b>Model Editor</b>', - self) + '<b>Model Editor</b>', self + ) self.model.triggered.connect(self.open_modelEditor) self.subcircuit = QtGui.QAction( QtGui.QIcon('../../images/subckt.png'), - '<b>Subcircuit</b>', - self) + '<b>Subcircuit</b>', self + ) self.subcircuit.triggered.connect(self.open_subcircuit) self.nghdl = QtGui.QAction( - QtGui.QIcon('../../images/nghdl.png'), - '<b>Nghdl</b>', - self) + QtGui.QIcon('../../images/nghdl.png'), '<b>Nghdl</b>', self + ) self.nghdl.triggered.connect(self.open_nghdl) self.omedit = QtGui.QAction( QtGui.QIcon('../../images/omedit.png'), - '<b>Modelica Converter</b>', - self) + '<b>Modelica Converter</b>', self + ) self.omedit.triggered.connect(self.open_OMedit) self.omoptim = QtGui.QAction( QtGui.QIcon('../../images/omoptim.png'), - '<b>OM Optimisation</b>', - self) + '<b>OM Optimisation</b>', self + ) self.omoptim.triggered.connect(self.open_OMoptim) # Adding Action Widget to tool bar @@ -197,30 +204,30 @@ class Application(QtGui.QMainWindow): self.lefttoolbar.setOrientation(QtCore.Qt.Vertical) self.lefttoolbar.setIconSize(QSize(40, 40)) - # This function closes the ongoing program(process). def closeEvent(self, event): ''' - When exit button is pressed a Message box pops out with + This function closes the ongoing program (process). + When exit button is pressed a Message box pops out with \ exit message and buttons 'Yes', 'No'. 1. If 'Yes' is pressed: - - it checks that program(process) in procThread_list\ - (list made in Appconfig.py): + - check that program (process) in procThread_list \ + (a list made in Appconfig.py): - - if available it terminates that program - - if the program(process) is not available,\ - it checks for it - in process_obj (list made in Appconfig.py) if found it - closes the program. + - if available it terminates that program. + - if the program (process) is not available, \ + then check it in process_obj (a list made in \ + Appconfig.py) and if found, it closes the program. 2. If 'No' is pressed: - the program just continues as it was doing earlier. ''' - exit_msg = "Are you sure you want to exit the program?" \ - " All unsaved data will be lost." + exit_msg = "Are you sure you want to exit the program?" + exit_msg += " All unsaved data will be lost." reply = QtGui.QMessageBox.question( self, 'Message', exit_msg, QtGui.QMessageBox.Yes, - QtGui.QMessageBox.No) + QtGui.QMessageBox.No + ) if reply == QtGui.QMessageBox.Yes: for proc in self.obj_appconfig.procThread_list: @@ -236,8 +243,9 @@ class Application(QtGui.QMainWindow): pass except BaseException: pass - # Just checking if open project and New project window is open. If - # yes just close it when application is closed + + # Check if "Open project" and "New project" window is open. + # If yes, just close it when application is closed. try: self.project.close() except BaseException: @@ -248,15 +256,48 @@ class Application(QtGui.QMainWindow): elif reply == QtGui.QMessageBox.No: event.ignore() - # This function closes the saved project. + def new_project(self): + """This function call New Project Info class.""" + text, ok = QtGui.QInputDialog.getText( + self, 'New Project Info', 'Enter Project Name:' + ) + if ok: + self.projname = (str(text)) + self.project = NewProjectInfo() + directory, filelist = self.project.createProject(self.projname) + self.obj_Mainview.obj_projectExplorer.addTreeNode( + directory, filelist) + else: + print("No new project created") + self.obj_appconfig.print_info('No new project created') + try: + self.obj_appconfig.print_info( + 'Current project is : ' + + self.obj_appconfig.current_project["ProjectName"] + ) + except BaseException: + pass + + def open_project(self): + """This project call Open Project Info class.""" + print("Function : Open Project") + self.project = OpenProjectInfo() + try: + directory, filelist = self.project.body() + self.obj_Mainview.obj_projectExplorer.addTreeNode( + directory, filelist) + except BaseException: + pass + def close_project(self): """ - This function first checks whether project(file) is present in list. + This function closes the saved project. + It first checks whether project (file) is present in list. - If present: - it first kills that process-id. - closes that file. - - Shows message "Current project <path of file> is closed" + - Shows message "Current project <path_to_file> is closed" - If not present: pass """ @@ -274,60 +315,155 @@ class Application(QtGui.QMainWindow): self.obj_Mainview.obj_dockarea.closeDock() self.obj_appconfig.current_project['ProjectName'] = None self.systemTrayIcon.showMessage( - 'Close', - 'Current project ' + - os.path.basename(current_project) + - ' is Closed.') - - # This function call New Project Info class. - def new_project(self): - text, ok = QtGui.QInputDialog.getText( - self, 'New Project Info', 'Enter Project Name:') - if ok: - self.projname = (str(text)) - self.project = NewProjectInfo() - directory, filelist = self.project.createProject(self.projname) + 'Close', 'Current project ' + + os.path.basename(current_project) + ' is Closed.' + ) - self.obj_Mainview.obj_projectExplorer.addTreeNode( - directory, filelist) + def validate_mode(self): + """ + This function is used for checking fp-lib-tables file. + If not than copy from supportFiles folder. + First it will check path for kicad folder is present or not. if present + 1) it will check fp-lib-table file is present or not. + - If not present + - Than copy form SourceFile folder + 2) it will check for both file, + i.e online and offline file is present or not. + - If both are present + -Than remove offline. + 3) it will check wich file is present + - If fp-lib-table-offline is present + - Than online mode will set and used + - If fp-lib-table-online is present + - Than offline mode wiil set and used + - If both file are not present + -Than copy fp-lib-table from source file + Otherwise the disable icon is set and feature is disabled. + """ + if self.obj_appconfig.kicad_path is not None: + # ----------------------------------------------------- + # fp-lib-table is not there than copy from supportFiles/ + if not os.path.exists( + self.obj_appconfig.kicad_path + "/fp-lib-table"): + shutil.copy('../supportFiles/fp-lib-table' , + self.obj_appconfig.kicad_path + "/") + # ----------------------------------------------------- + """checking online and offline both file's are avaliable. + if yes than remove offline file.""" + if os.path.exists(self.obj_appconfig.kicad_path + + "/fp-lib-table-offline") and os.path.exists( + self.obj_appconfig.kicad_path + + "/fp-lib-table-online"): + os.remove(self.obj_appconfig.kicad_path + + "/fp-lib-table-offline") + # ----------------------------------------------------- + # This ladder is used for checking which file is present. + if os.path.exists(self.obj_appconfig.kicad_path + + "/fp-lib-table-offline"): + self.switchmode = QtGui.QAction( + QtGui.QIcon('../../images/online.png'), + '<b>Go Offline</b>',self) + self.online_flag = True + + elif os.path.exists(self.obj_appconfig.kicad_path + + "/fp-lib-table-online"): + self.switchmode = QtGui.QAction( + QtGui.QIcon('../../images/offline.png'), + '<b>Go Online</b>',self) + self.online_flag = False + else: + # if online and offline is not avaliable + shutil.copy('../supportFiles/fp-lib-table-online' , + self.obj_appconfig.kicad_path + "/") + if os.path.exists(self.obj_appconfig.kicad_path + + "/fp-lib-table-online"): + self.switchmode = QtGui.QAction( + QtGui.QIcon('../../images/offline.png'), + '<b>Go Online</b>',self) + self.online_flag = False + #---------------------------------------------------- else: - print("No new project created") - self.obj_appconfig.print_info('No new project created') - try: - self.obj_appconfig.print_info( - 'Current project is : ' + - self.obj_appconfig.current_project["ProjectName"]) - except BaseException: - pass + # if path is not found + self.switchmode = QtGui.QAction(QtGui.QIcon( + '../../images/disable.png'), + '<b>Mode switching has been disabled. Relaunch ' + + 'eSim to fix any config issues</b>', self) - # This project call Open Project Info class - def open_project(self): - print("Function : Open Project") - self.project = OpenProjectInfo() - - try: - directory, filelist = self.project.body() - self.obj_Mainview.obj_projectExplorer.addTreeNode( - directory, filelist) - except BaseException: - pass + def change_mode(self): + """ + This function is used for changing mode of operation for KiCad. \ + There are three modes of operation : + - online + - offline + - disable + + It will check whether kicad config path is present or not. + - If path is available and none of the KiCad tools \ + (associated with eSim) are open, then depending on \ + online_flag, it will swap appropriate fp-lib-table files. + - If any of the KiCad tools (associated with eSim) is open, \ + then ask user to close all these tools. + - And if path is not found, then disable this feature. + + @paramas + + @return + None + """ + if self.obj_appconfig.kicad_path is not None: + try: + if not self.obj_kicad.check_open_schematic(): + if self.online_flag: + os.rename( + self.obj_appconfig.kicad_path + "/fp-lib-table", + self.obj_appconfig.kicad_path + "/fp-lib-table-online" + ) + os.rename( + self.obj_appconfig.kicad_path + "/fp-lib-table-offline", + self.obj_appconfig.kicad_path + "/fp-lib-table" + ) + self.switchmode.setIcon(QtGui.QIcon('../../images/offline.png')) + self.switchmode.setText('<b>Go Online</b>') + self.online_flag = False + else: + os.rename( + self.obj_appconfig.kicad_path + "/fp-lib-table", + self.obj_appconfig.kicad_path + "/fp-lib-table-offline") + os.rename( + self.obj_appconfig.kicad_path + "/fp-lib-table-online", + self.obj_appconfig.kicad_path + "/fp-lib-table") + self.switchmode.setIcon(QtGui.QIcon('../../images/online.png')) + self.switchmode.setText('<b>Go Offline</b>') + self.online_flag = True + else: + self.msg = QtGui.QErrorMessage() + self.msg.showMessage('Please save and close all the Kicad' + 'Windows first, and then change the online-offline mode') + self.msg.setWindowTitle("Error Message") + except: + self.validate_mode() + else: + self.info_msg = QtGui.QMessageBox.critical(self, + 'Message', + "Please make sure kicad_folder_file is " + + "present in supportFiles folder.") - # This page opens usermanual in dockarea. def help_project(self): """ - - It prints the message ""Function : Help"" - - Uses print_info() method of class Appconfig - from Configuration/Appconfig.py file. - - Call method usermanual() from ./DockArea.py. + This function opens usermanual in dockarea. + - It prints the message ""Function : Help"" + - Uses print_info() method of class Appconfig + from Configuration/Appconfig.py file. + - Call method usermanual() from ./DockArea.py. """ print("Function : Help") self.obj_appconfig.print_info('Help is called') print("Current Project is : ", self.obj_appconfig.current_project) self.obj_Mainview.obj_dockarea.usermanual() - # This Function execute ngspice on current project. def open_ngspice(self): + """This Function execute ngspice on current project.""" self.projDir = self.obj_appconfig.current_project["ProjectName"] if self.projDir is not None: @@ -342,37 +478,39 @@ class Application(QtGui.QMainWindow): break except Exception: pass - time.sleep(0.2) + time.sleep(0.5) # Fail Safe ===> count += 1 if count >= 100: raise Exception( - "ngspice taking too long, check netlist file") + "Ngspice taking too long for simulation. " + "Check netlist file to change simulation parameters." + ) # Calling Python Plotting - try: self.obj_Mainview.obj_dockarea.plottingEditor() except Exception as e: self.msg = QtGui.QErrorMessage(None) self.msg.showMessage( 'Error while opening python plotting Editor.' - ' Please look at console for more details') + ' Please look at console for more details.' + ) print("Exception Message:", str(e)) self.obj_appconfig.print_error('Exception Message : ' + str(e)) self.msg.setWindowTitle("Error Message") - else: self.msg = QtGui.QErrorMessage() self.msg.showMessage( 'Please select the project first.' - ' You can either create new project or open existing project') + ' You can either create new project or open existing project' + ) self.msg.setWindowTitle("Error Message") - # This function opens 'subcircuit' option in left-tool-bar. def open_subcircuit(self): """ + This function opens 'subcircuit' option in left-tool-bar. When 'subcircuit' icon is clicked wich is present in left-tool-bar of main page: @@ -384,36 +522,34 @@ class Application(QtGui.QMainWindow): self.obj_appconfig.print_info('Subcircuit editor is called') self.obj_Mainview.obj_dockarea.subcircuiteditor() - # This function calls NGHDl option in left-tool-bar. def open_nghdl(self): """ - This function uses validateTool() method from - Validation.py: + This function calls NGHDL option in left-tool-bar. + It uses validateTool() method from Validation.py: - If 'nghdl' is present in executables list then - it adds passes command 'nghdl -e' to WorkerThread class of + it passes command 'nghdl -e' to WorkerThread class of Worker.py. - - If 'nghdl' not present then it shows error message. + - If 'nghdl' is not present, then it shows error message. """ - print("Function : Nghdl") - self.obj_appconfig.print_info('Nghdl is called') + print("Function : NGHDL") + self.obj_appconfig.print_info('NGHDL is called') if self.obj_validation.validateTool('nghdl'): self.cmd = 'nghdl -e' self.obj_workThread = Worker.WorkerThread(self.cmd) self.obj_workThread.start() - else: self.msg = QtGui.QErrorMessage(None) - self.msg.showMessage('Error while opening nghdl.\ - Please make sure nghdl is installed') - self.obj_appconfig.print_error('Error while opening nghdl.\ - Please make sure nghdl is installed') - self.msg.setWindowTitle('nghdl Error Message') + self.msg.showMessage('Error while opening NGHDL. ' + + 'Please make sure it is installed') + self.obj_appconfig.print_error('Error while opening NGHDL. ' + + 'Please make sure it is installed') + self.msg.setWindowTitle('NGHDL Error') - # This function opens model editor option in left-tool-bar. def open_modelEditor(self): """ + This function opens model editor option in left-tool-bar. When model editor icon is clicked which is present in left-tool-bar of main page: @@ -425,19 +561,22 @@ class Application(QtGui.QMainWindow): self.obj_appconfig.print_info('Model editor is called') self.obj_Mainview.obj_dockarea.modelEditor() - # This function call ngspice to OM edit converter - # and then launch OM edit. def open_OMedit(self): - self.obj_appconfig.print_info('OM edit is called') + """ + This function calls ngspice to OMEdit converter and then launch OMEdit. + """ + self.obj_appconfig.print_info('OMEdit is called') self.projDir = self.obj_appconfig.current_project["ProjectName"] if self.projDir is not None: if self.obj_validation.validateCirOut(self.projDir): self.projName = os.path.basename(self.projDir) self.ngspiceNetlist = os.path.join( - self.projDir, self.projName + ".cir.out") + self.projDir, self.projName + ".cir.out" + ) self.modelicaNetlist = os.path.join( - self.projDir, self.projName + ".mo") + self.projDir, self.projName + ".mo" + ) """ try: @@ -487,31 +626,29 @@ class Application(QtGui.QMainWindow): else: self.msg = QtGui.QErrorMessage() self.msg.showMessage( - 'Current project does not contain any ngspice file.\ - Please create ngspice file with extension .cir.out') + 'Current project does not contain any Ngspice file. ' + + 'Please create Ngspice file with extension .cir.out' + ) self.msg.setWindowTitle("Missing Ngspice netlist") else: self.msg = QtGui.QErrorMessage() self.msg.showMessage( - 'Please select the project first.\ - You can either create new project\ - or open existing project') + 'Please select the project first. ' + + 'You can either create a new project or open existing project' + ) self.msg.setWindowTitle("Error Message") - # sdf def open_OMoptim(self): """ - This function uses validateTool() method from - Validation.py: + This function uses validateTool() method from Validation.py: - If 'OMOptim' is present in executables list then - it adds passes command 'OMOptim' to WorkerThread class of - Worker.py. - - If 'OMOptim' not present then it shows error message with + it passes command 'OMOptim' to WorkerThread class of Worker.py + - If 'OMOptim' is not present, then it shows error message with link to download it on Linux and Windows. """ - print("Function : OM Optim") - self.obj_appconfig.print_info('OM Optim is called') + print("Function : OMOptim") + self.obj_appconfig.print_info('OMOptim is called') # Check if OMOptim is installed if self.obj_validation.validateTool("OMOptim"): # Creating a command to run @@ -531,7 +668,7 @@ class Application(QtGui.QMainWindow): "To install it on Windows : Go to <a href=" "https://www.openmodelica.org/download/download-windows" ">OpenModelica Windows</a> and install latest version.<br/>" - ) + ) self.msg.setTextFormat(QtCore.Qt.RichText) self.msg.setText(self.msgContent) self.msg.setWindowTitle("Error Message") @@ -545,14 +682,11 @@ class MainView(QtGui.QWidget): This class defines whole view and style of main page: - Position of tool bars: - - - Top tool bar. - - Left tool bar. - + - Top tool bar. + - Left tool bar. - Project explorer Area. - Dock area. - Console area. - """ def __init__(self, *args): @@ -606,7 +740,7 @@ class MainView(QtGui.QWidget): self.setLayout(self.mainLayout) -# It is main function of the module.It starts the application +# It is main function of the module and starts the application def main(args): """ The splash screen opened at the starting of screen is performed @@ -628,8 +762,6 @@ def main(args): # Call main function - - if __name__ == '__main__': # Create and display the splash screen main(sys.argv) diff --git a/src/frontEnd/DockArea.py b/src/frontEnd/DockArea.py index db706fa7..9824a307 100644 --- a/src/frontEnd/DockArea.py +++ b/src/frontEnd/DockArea.py @@ -14,6 +14,7 @@ dockList = ['Welcome'] count = 1 dock = {} + class DockArea(QtGui.QMainWindow): """ This class contains function for designing UI of all the editors @@ -22,8 +23,8 @@ class DockArea(QtGui.QMainWindow): - Test Editor. - Model Editor. - Python Plotting. - - NgSpice Editor. - - Kicad to NgSpice Editor. + - Ngspice Editor. + - Kicad to Ngspice Editor. - Subcircuit Editor. - Modelica editor. """ @@ -53,8 +54,9 @@ class DockArea(QtGui.QMainWindow): self.show() def createTestEditor(self): - """This function create widget for Library Editor.""" + """This function create widget for Library Editor""" global count + self.testWidget = QtGui.QWidget() self.testArea = QtGui.QTextEdit() self.testLayout = QtGui.QVBoxLayout() @@ -74,16 +76,18 @@ class DockArea(QtGui.QMainWindow): dock['Tips-' + str(count)].raise_() - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['Tips-' + str(count)]) + temp = self.obj_appconfig.current_project['ProjectName'] + if temp: + self.obj_appconfig.dock_dict[temp].append( + dock['Tips-' + str(count)] + ) count = count + 1 def plottingEditor(self): - """This function create widget for interactive PythonPlotting""" + """This function create widget for interactive PythonPlotting.""" self.projDir = self.obj_appconfig.current_project["ProjectName"] self.projName = os.path.basename(self.projDir) - # self.project = os.path.join(self.projDir,self.projName) + # self.project = os.path.join(self.projDir, self.projName) global count self.plottingWidget = QtGui.QWidget() @@ -104,13 +108,15 @@ class DockArea(QtGui.QMainWindow): dock['Plotting-' + str(count)].setFocus() dock['Plotting-' + str(count)].raise_() - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['Plotting-' + str(count)]) + temp = self.obj_appconfig.current_project['ProjectName'] + if temp: + self.obj_appconfig.dock_dict[temp].append( + dock['Plotting-' + str(count)] + ) count = count + 1 def ngspiceEditor(self, projDir): - """Sdf.""" + """ This function creates widget for Ngspice window.""" self.projDir = projDir self.projName = os.path.basename(self.projDir) self.ngspiceNetlist = os.path.join( @@ -121,9 +127,8 @@ class DockArea(QtGui.QMainWindow): self.ngspiceLayout = QtGui.QVBoxLayout() self.ngspiceLayout.addWidget( - NgspiceWidget( - self.ngspiceNetlist, - self.projDir)) + NgspiceWidget(self.ngspiceNetlist, self.projDir) + ) # Adding to main Layout self.ngspiceWidget.setLayout(self.ngspiceLayout) @@ -143,9 +148,12 @@ class DockArea(QtGui.QMainWindow): dock['NgSpice-' + str(count)].setVisible(True) dock['NgSpice-' + str(count)].setFocus() dock['NgSpice-' + str(count)].raise_() - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['NgSpice-' + str(count)]) + + temp = self.obj_appconfig.current_project['ProjectName'] + if temp: + self.obj_appconfig.dock_dict[temp].append( + dock['NgSpice-' + str(count)] + ) count = count + 1 def modelEditor(self): @@ -178,15 +186,11 @@ class DockArea(QtGui.QMainWindow): dock['Model Editor-' + str(count)].setFocus() dock['Model Editor-' + str(count)].raise_() - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['Model Editor-' + str(count)]) count = count + 1 def kicadToNgspiceEditor(self, clarg1, clarg2=None): """ - This function is creating Editor UI for- - Kicad to Ngspice conversion. + This function is creating Editor UI for Kicad to Ngspice conversion. """ global count self.kicadToNgspiceWidget = QtGui.QWidget() @@ -212,10 +216,13 @@ class DockArea(QtGui.QMainWindow): dock['kicadToNgspice-' + str(count)].setVisible(True) dock['kicadToNgspice-' + str(count)].setFocus() dock['kicadToNgspice-' + str(count)].raise_() + dock['kicadToNgspice-' + str(count)].activateWindow() - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['kicadToNgspice-' + str(count)]) + temp = self.obj_appconfig.current_project['ProjectName'] + if temp: + self.obj_appconfig.dock_dict[temp].append( + dock['kicadToNgspice-' + str(count)] + ) count = count + 1 def subcircuiteditor(self): @@ -244,12 +251,10 @@ class DockArea(QtGui.QMainWindow): dock['Subcircuit-' + str(count)].setFocus() dock['Subcircuit-' + str(count)].raise_() - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['Subcircuit-' + str(count)]) count = count + 1 def usermanual(self): + """This function creates a widget for user manual.""" global count self.usermanualWidget = QtGui.QWidget() self.usermanualLayout = QtGui.QVBoxLayout() @@ -277,7 +282,7 @@ class DockArea(QtGui.QMainWindow): count = count + 1 def modelicaEditor(self, projDir): - """Dfg.""" + """This function sets up the UI for ngspice to modelica conversion.""" global count self.modelicaWidget = QtGui.QWidget() self.modelicaLayout = QtGui.QVBoxLayout() @@ -300,9 +305,11 @@ class DockArea(QtGui.QMainWindow): .QWidget { border-radius: 15px; border: 1px solid gray;\ padding: 5px; width: 200px; height: 150px; } \ ") - # temp = self.obj_appconfig.current_project['ProjectName'] - # self.obj_appconfig.dock_dict[temp].append( - # dock['Modelica-' + str(count)]) + temp = self.obj_appconfig.current_project['ProjectName'] + if temp: + self.obj_appconfig.dock_dict[temp].append( + dock['Modelica-' + str(count)] + ) count = count + 1 diff --git a/src/frontEnd/ProjectExplorer.py b/src/frontEnd/ProjectExplorer.py index 09e756af..1557d450 100644 --- a/src/frontEnd/ProjectExplorer.py +++ b/src/frontEnd/ProjectExplorer.py @@ -35,6 +35,8 @@ class ProjectExplorer(QtGui.QWidget): # CSS self.treewidget.setStyleSheet(" \ + QTreeView { border-radius: 15px; border: 1px \ + solid gray; padding: 5px; width: 200px; height: 150px; }\ QTreeView::branch:has-siblings:!adjoins-item { \ border-image: url(../../images/vline.png) 0;} \ QTreeView::branch:has-siblings:adjoins-item { \ @@ -61,7 +63,8 @@ class ProjectExplorer(QtGui.QWidget): ) for files in children: QtGui.QTreeWidgetItem( - parentnode, [files, os.path.join(parents, files)]) + parentnode, [files, os.path.join(parents, files)] + ) self.window.addWidget(self.treewidget) self.treewidget.doubleClicked.connect(self.openProject) @@ -74,7 +77,8 @@ class ProjectExplorer(QtGui.QWidget): os.path.join(parents) pathlist = parents.split(os.sep) parentnode = QtGui.QTreeWidgetItem( - self.treewidget, [pathlist[-1], parents]) + self.treewidget, [pathlist[-1], parents] + ) for files in children: QtGui.QTreeWidgetItem( parentnode, [files, os.path.join(parents, files)] @@ -90,7 +94,6 @@ class ProjectExplorer(QtGui.QWidget): ) = [] def openMenu(self, position): - indexes = self.treewidget.selectedIndexes() if len(indexes) > 0: level = 0 @@ -117,9 +120,8 @@ class ProjectExplorer(QtGui.QWidget): self.indexItem = self.treewidget.currentIndex() filename = str(self.indexItem.data()) self.filePath = str( - self.indexItem.sibling( - self.indexItem.row(), - 1).data()) + self.indexItem.sibling(self.indexItem.row(), 1).data() + ) self.obj_appconfig.print_info( 'The current project is ' + self.filePath) @@ -132,16 +134,15 @@ class ProjectExplorer(QtGui.QWidget): self.save = QtGui.QPushButton('Save and Exit') self.save.setDisabled(True) self.windowgrid = QtGui.QGridLayout() - # if (os.path.isfile(str(self.filePath))) == True: + if (os.path.isfile(str(self.filePath))): self.fopen = open(str(self.filePath), 'r') lines = self.fopen.read() self.text.setText(lines) QtCore.QObject.connect( - self.text, - QtCore.SIGNAL("textChanged()"), - self.enable_save) + self.text, QtCore.SIGNAL("textChanged()"), self.enable_save + ) vbox_main = QtGui.QVBoxLayout(self.textwindow) vbox_main.addWidget(self.text) @@ -167,29 +168,30 @@ class ProjectExplorer(QtGui.QWidget): self.obj_appconfig.current_project['ProjectName']] ) = [] - # This function is enabling save button option. def enable_save(self): + """This function enables save button option.""" self.save.setEnabled(True) - # This function is saving data before it closes the given file. def save_data(self): """ - This function first opens file in write-mode, when write - operation is performed it closes that file and then it closes window. + This function saves data before it closes the given file. + It first opens file in write-mode, write operation is performed, \ + closes that file and then it closes window. """ self.fopen = open(self.filePath, 'w') self.fopen.write(self.text.toPlainText()) self.fopen.close() self.textwindow.close() - # This function removes the project in explorer area by right - # clicking on project and selecting remove option. def removeProject(self): + """ + This function removes the project in explorer area by right \ + clicking on project and selecting remove option. + """ self.indexItem = self.treewidget.currentIndex() self.filePath = str( - self.indexItem.sibling( - self.indexItem.row(), - 1).data()) + self.indexItem.sibling(self.indexItem.row(), 1).data() + ) self.int = self.indexItem.row() self.treewidget.takeTopLevelItem(self.int) @@ -200,14 +202,15 @@ class ProjectExplorer(QtGui.QWidget): json.dump(self.obj_appconfig.project_explorer, open(self.obj_appconfig.dictPath, 'w')) - # This function refresh the project in explorer area by right - # clicking on project and selecting refresh option. def refreshProject(self): + """ + This function refresh the project in explorer area by right \ + clicking on project and selecting refresh option. + """ self.indexItem = self.treewidget.currentIndex() self.filePath = str( - self.indexItem.sibling( - self.indexItem.row(), - 1).data()) + self.indexItem.sibling(self.indexItem.row(), 1).data() + ) filelistnew = os.listdir(os.path.join(self.filePath)) parentnode = self.treewidget.currentItem() count = parentnode.childCount() @@ -216,9 +219,8 @@ class ProjectExplorer(QtGui.QWidget): items.removeChild(items.child(0)) for files in filelistnew: QtGui.QTreeWidgetItem( - parentnode, [ - files, os.path.join( - self.filePath, files)]) + parentnode, [files, os.path.join(self.filePath, files)] + ) self.obj_appconfig.project_explorer[self.filePath] = filelistnew json.dump(self.obj_appconfig.project_explorer, @@ -226,23 +228,22 @@ class ProjectExplorer(QtGui.QWidget): def renameProject(self): """ - This function renames the project present in project explorer area - it validates first: + This function renames the project present in project explorer area. + It validates first: - If project names is not empty. - Project name does not contain spaces between them. - Project name is different between what it was earlier. - Project name should not exist. - And after project name is changed it recreates - the project explorer tree. + After project name is changed, it recreates the project explorer tree. """ self.indexItem = self.treewidget.currentIndex() self.baseFileName = str(self.indexItem.data()) newBaseFileName, ok = QtGui.QInputDialog.getText( - self, 'Rename Project', 'Project Name:', QtGui.QLineEdit.Normal, - self.baseFileName - ) + self, 'Rename Project', 'Project Name:', + QtGui.QLineEdit.Normal, self.baseFileName + ) if ok and newBaseFileName: print(newBaseFileName) print("=================") @@ -284,8 +285,8 @@ class ProjectExplorer(QtGui.QWidget): # rename project folder updatedProjectPath = newBaseFileName.join( projectPath.rsplit(self.baseFileName, 1)) - print("Renaming " + projectPath + " to " - + updatedProjectPath) + print("Renaming " + projectPath + " to " + + updatedProjectPath) os.rename(projectPath, updatedProjectPath) # rename files matching project name @@ -297,8 +298,8 @@ class ProjectExplorer(QtGui.QWidget): self.baseFileName, newBaseFileName, 1) newFilePath = os.path.join( updatedProjectPath, projectFile) - print("Renaming " + oldFilePath + " to" - + newFilePath) + print("Renaming " + oldFilePath + " to" + + newFilePath) os.rename(oldFilePath, newFilePath) updatedProjectFiles.append(projectFile) @@ -323,10 +324,10 @@ class ProjectExplorer(QtGui.QWidget): print("==========================") msg = QtGui.QErrorMessage(self) msg.showMessage( - 'The project "' - + newBaseFileName - + '" already exist.Please select the different name or' - + ' delete existing project') + 'The project "' + newBaseFileName + + '" already exist. Please select a different name or' + + ' delete existing project' + ) msg.setWindowTitle("Error Message") elif reply == "CHECKNAME": @@ -334,6 +335,7 @@ class ProjectExplorer(QtGui.QWidget): print("===========================") msg = QtGui.QErrorMessage(self) msg.showMessage( - 'The project name should not' - + 'contain space between them') + 'The project name should not ' + + 'contain space between them' + ) msg.setWindowTitle("Error Message") diff --git a/src/frontEnd/Workspace.py b/src/frontEnd/Workspace.py index 55a8c95e..29be09fc 100644 --- a/src/frontEnd/Workspace.py +++ b/src/frontEnd/Workspace.py @@ -1,5 +1,4 @@ # ========================================================================= -# # FILE: Workspace.py # # USAGE: --- @@ -11,27 +10,26 @@ # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. # CREATED: Wednesday 05 February 2015 -# REVISION: --- +# REVISION: Friday 14 February 2020 # ========================================================================= + from PyQt4 import QtCore, QtGui from configuration.Appconfig import Appconfig import time import os -# This class creates Workspace GUI. class Workspace(QtGui.QWidget): """ This class creates UI for WorkSpace selection window. - This window contains text area to select location of your choice - or browse location for workspace area. - - By default workspace is set in ~/eSim-Workspace. - - This workspace area contains all the projects made by user. + - This window contains text area to select location of your choice \ + or browse location for workspace area. + - By default workspace is set in ~/eSim-Workspace. + - This workspace area contains all the projects made by user. """ @@ -43,7 +41,6 @@ class Workspace(QtGui.QWidget): self.initWorkspace() def initWorkspace(self): - # print "Calling workspace" self.mainwindow = QtGui.QVBoxLayout() self.split = QtGui.QSplitter() diff --git a/src/frontEnd/pathmagic.py b/src/frontEnd/pathmagic.py index 49c4932d..5f0d712c 100644 --- a/src/frontEnd/pathmagic.py +++ b/src/frontEnd/pathmagic.py @@ -1,5 +1,6 @@ import os import sys + # Setting PYTHONPATH cwd = os.getcwd() (setPath, fronEnd) = os.path.split(cwd) diff --git a/src/kicadtoNgspice/Analysis.py b/src/kicadtoNgspice/Analysis.py index b24f24c7..e5c05ebe 100644 --- a/src/kicadtoNgspice/Analysis.py +++ b/src/kicadtoNgspice/Analysis.py @@ -1,29 +1,27 @@ - -from PyQt4 import QtGui +from PyQt4 import QtGui, QtCore from . import TrackWidget import os -# from xml.etree import ElementTree as ET import json class Analysis(QtGui.QWidget): """ - This class create Analysis Tab in KicadtoNgspice Window. 4 sections - - - - Select Analysis Type - - - AC Analysis - - - DC Analysis - - - Transient Analysis - - Set various track widget options here, for tracking purposes across\ - different functions and modules - - - - AC_entry_var - - - AC_Parameter - - - DC_entry_var - - - DC_Parameter - - - TRAN_entry_var - - - TRAN_Parameter - - - set_Checkbox - - - AC_type - - - op_check + - Select Analysis Type + - AC Analysis + - DC Analysis + - Transient Analysis + - Set various track widget options here, for tracking purposes across \ + different functions and modules - + - AC_entry_var + - AC_Parameter + - DC_entry_var + - DC_Parameter + - TRAN_entry_var + - TRAN_Parameter + - set_Checkbox + - AC_type + - op_check """ def __init__(self, clarg1): @@ -42,19 +40,21 @@ class Analysis(QtGui.QWidget): def createAnalysisWidget(self): """ - - Create the main anaylsis widget overwiew - - - Checkbox for analysis type - - - Place, `AC`, `DC` and `TRANSIENT` analysis tab - - - `self.acbox`, `self.dcbox`,`self.trbox`... + - Create the main anaylsis widget overwiew: + - Checkbox for analysis type + - Place, `AC`, `DC` and `TRANSIENT` analysis tab + - `self.acbox`, `self.dcbox`, `self.trbox`... - Check for `analysis` file, if any in projDir, extract data from it - Else set the default checkbox to `TRAN` - Accordingly set state for track widget options, as `TRAN`, `AC` ... """ self.grid = QtGui.QGridLayout() - self.grid.addWidget(self.createCheckBox(), 0, 0) - self.grid.addWidget(self.createACgroup(), 1, 0) - self.grid.addWidget(self.createDCgroup(), 2, 0) - self.grid.addWidget(self.createTRANgroup(), 3, 0) + self.setLayout(self.grid) + + self.grid.addWidget(self.createCheckBox(), 0, 0, QtCore.Qt.AlignTop) + self.grid.addWidget(self.createACgroup(), 1, 0, 5, 0) + self.grid.addWidget(self.createDCgroup(), 1, 0, 5, 0) + self.grid.addWidget(self.createTRANgroup(), 1, 0, 5, 0) try: kicadFile = self.clarg1 @@ -74,6 +74,10 @@ class Analysis(QtGui.QWidget): self.acbox.setDisabled(False) self.dcbox.setDisabled(True) self.trbox.setDisabled(True) + + self.acbox.setVisible(True) + self.dcbox.setVisible(False) + self.trbox.setVisible(False) self.track_obj.set_CheckBox["ITEMS"] = "AC" if contentlist[1] == 'lin': self.Lin.setChecked(True) @@ -90,6 +94,10 @@ class Analysis(QtGui.QWidget): self.dcbox.setDisabled(False) self.acbox.setDisabled(True) self.trbox.setDisabled(True) + + self.dcbox.setVisible(True) + self.acbox.setVisible(False) + self.trbox.setVisible(False) self.track_obj.set_CheckBox["ITEMS"] = "DC" elif contentlist[0] == '.tran': @@ -97,6 +105,10 @@ class Analysis(QtGui.QWidget): self.trbox.setDisabled(False) self.acbox.setDisabled(True) self.dcbox.setDisabled(True) + + self.trbox.setVisible(True) + self.dcbox.setVisible(False) + self.acbox.setVisible(False) self.track_obj.set_CheckBox["ITEMS"] = "TRAN" elif contentlist[0] == '.op': @@ -104,6 +116,10 @@ class Analysis(QtGui.QWidget): self.dcbox.setDisabled(False) self.acbox.setDisabled(True) self.trbox.setDisabled(True) + + self.dcbox.setVisible(True) + self.acbox.setVisible(False) + self.trbox.setVisible(False) self.check.setChecked(True) self.track_obj.set_CheckBox["ITEMS"] = "DC" @@ -111,7 +127,6 @@ class Analysis(QtGui.QWidget): self.checkTRAN.setChecked(True) self.track_obj.set_CheckBox["ITEMS"] = "TRAN" - self.setLayout(self.grid) self.show() def createCheckBox(self): @@ -151,25 +166,37 @@ class Analysis(QtGui.QWidget): self.acbox.setDisabled(False) self.dcbox.setDisabled(True) self.trbox.setDisabled(True) + + self.acbox.setVisible(True) + self.dcbox.setVisible(False) + self.trbox.setVisible(False) self.track_obj.set_CheckBox["ITEMS"] = "AC" elif self.checkDC.isChecked(): self.dcbox.setDisabled(False) self.acbox.setDisabled(True) self.trbox.setDisabled(True) + + self.dcbox.setVisible(True) + self.acbox.setVisible(False) + self.trbox.setVisible(False) self.track_obj.set_CheckBox["ITEMS"] = "DC" elif self.checkTRAN.isChecked(): self.trbox.setDisabled(False) self.acbox.setDisabled(True) self.dcbox.setDisabled(True) + + self.trbox.setVisible(True) + self.acbox.setVisible(False) + self.dcbox.setVisible(False) self.track_obj.set_CheckBox["ITEMS"] = "TRAN" def createACgroup(self): """ - Designing of AC group in analysis tab - 3 radio buttons - Lin | Dec | Oct - - 3 input boxes, with top 2 combos\ + - 3 input boxes, with top 2 combos - If previous values exist then fill default values from previous value json file """ @@ -194,6 +221,7 @@ class Analysis(QtGui.QWidget): self.acbox = QtGui.QGroupBox() self.acbox.setTitle("AC Analysis") self.acbox.setDisabled(True) + self.acbox.setVisible(False) self.acgrid = QtGui.QGridLayout() self.radiobuttongroup = QtGui.QButtonGroup() self.Lin = QtGui.QRadioButton("Lin") @@ -320,11 +348,10 @@ class Analysis(QtGui.QWidget): ''' - Below 2 functions handle combo value event listeners for - - - start frequency for ac - - - stop frequency for ac + - start frequency for ac + - stop frequency for ac - And accordingly set the ac_parameters ''' - def start_combovalue(self, text): """ - Handle start_fre_combo box event @@ -343,7 +370,7 @@ class Analysis(QtGui.QWidget): def set_ac_type(self): """ - - Set track object for AC, according to the type of radio box selected + Sets track object for AC, according to the type of radio box selected. """ self.parameter_cnt = 0 @@ -353,17 +380,15 @@ class Analysis(QtGui.QWidget): self.track_obj.AC_type["ITEMS"] = "dec" elif self.Oct.isChecked(): self.track_obj.AC_type["ITEMS"] = "oct" - else: - pass def createDCgroup(self): """ - Create DC area under analysis tab - Source 1 and 2, each having 4 input boxes as follows - - - Source - - - Start - - - Increment - - - Stop + - Source + - Start + - Increment + - Stop - The last 3 have combo box pertaining to their unit as well - Also in the end a checkbox, for operating system point analysis """ @@ -388,6 +413,7 @@ class Analysis(QtGui.QWidget): self.dcbox = QtGui.QGroupBox() self.dcbox.setTitle("DC Analysis") self.dcbox.setDisabled(True) + self.dcbox.setVisible(False) self.dcgrid = QtGui.QGridLayout() self.dcbox.setLayout(self.dcgrid) @@ -811,10 +837,10 @@ class Analysis(QtGui.QWidget): print("Transient Analysis JSON Parse Error") return self.trbox + ''' - Below 3 functions handle event for the combo box in transient group ''' - def start_combo_change(self, text): """Handle start combo box, ie. units, as second, ms""" self.tran_parameter[0] = str(text) diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py index 883ba534..99f8768a 100644 --- a/src/kicadtoNgspice/Convert.py +++ b/src/kicadtoNgspice/Convert.py @@ -1,5 +1,4 @@ from PyQt4 import QtGui - import os import shutil from . import TrackWidget @@ -9,15 +8,15 @@ from xml.etree import ElementTree as ET class Convert: """ - This class has all the necessary function required to convert \ - kicad netlist to ngspice netlist. + kicad netlist to ngspice netlist. - Method List - - - addDeviceLibrary - - - addModelParameter - - - addSourceParameter - - - addSubcircuit - - - analysisInsertor - - - converttosciform - - - defaultvalue + - addDeviceLibrary + - addModelParameter + - addSourceParameter + - addSubcircuit + - analysisInsertor + - converttosciform + - defaultvalue """ def __init__(self, sourcelisttrack, source_entry_var, @@ -32,12 +31,12 @@ class Convert: """ - This function extracts the source details to schematicInfo - keywords recognised and parsed - - - - sine - - - pulse - - - pwl - - - ac - - - dc - - - exp + - sine + - pulse + - pwl + - ac + - dc + - exp - Return updated schematic """ @@ -355,7 +354,7 @@ class Convert: def addModelParameter(self, schematicInfo): """ - This function add the Ngspice Model details to schematicInfo + This function adds the Ngspice Model details to schematicInfo """ # Create object of TrackWidget @@ -446,8 +445,6 @@ class Convert: # end = line[8] addmodelLine = ".model " + line[3] + " " + line[2] + "(" for key, value in line[9].items(): - # print "Tags: ",key - # print "Value: ",value # Checking for default value and accordingly assign # param and default. if ':' in key: @@ -457,7 +454,7 @@ class Convert: else: param = key default = 0 - # Cheking if value is iterable.its for vector + # Checking if value is iterable.its for vector if ( not isinstance(value, str) and hasattr(value, '__iter__') @@ -516,17 +513,16 @@ class Convert: includeLine = [] # All .include line list if not deviceLibList: - print("No Library Added in the schematic") - pass + print("No library added in the schematic") else: for eachline in schematicInfo: words = eachline.split() if words[0] in deviceLibList: - print("Found Library line") + # print("Found Library line") index = schematicInfo.index(eachline) completeLibPath = deviceLibList[words[0]] (libpath, libname) = os.path.split(completeLibPath) - print("Library Path :", libpath) + # print("Library Path :", libpath) # Copying library from devicemodelLibrary to Project Path # Special case for MOSFET if eachline[0] == 'm': @@ -562,9 +558,6 @@ class Convert: dst = projpath shutil.copy2(src, dst) - else: - pass - # Adding device line to schematicInfo for index, value in deviceLine.items(): # Update the device line @@ -582,7 +575,6 @@ class Convert: """ This function add the subcircuit to schematicInfo """ - (projpath, filename) = os.path.split(kicadFile) subList = self.obj_track.subcircuitTrack @@ -600,7 +592,6 @@ class Convert: raise Exception('All subcircuit directories need to be specified.') elif not subList: print("No Subcircuit Added in the schematic") - pass else: for eachline in schematicInfo: words = eachline.split() @@ -624,8 +615,6 @@ class Convert: if os.path.isfile(os.path.join(src, files)): if files != "analysis": shutil.copy2(os.path.join(src, files), dst) - else: - pass # Adding subcircuit line to schematicInfo for index, value in subLine.items(): @@ -649,6 +638,5 @@ class Convert: for child in libtree.iter(): if child.tag == 'ref_model': retVal = child.text - else: - pass + return retVal diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py index 7f63a43b..41faa6f0 100644 --- a/src/kicadtoNgspice/DeviceModel.py +++ b/src/kicadtoNgspice/DeviceModel.py @@ -1,6 +1,5 @@ from PyQt4 import QtGui import os -# from xml.etree import ElementTree as ET import json from . import TrackWidget @@ -12,13 +11,13 @@ class DeviceModel(QtGui.QWidget): transistor and jfet. - Same function as the subCircuit file, except for this takes different parameters in the if block - - - q TRANSISTOR - - - d DIODE - - - j JFET - - - m MOSFET + - q TRANSISTOR + - d DIODE + - j JFET + - m MOSFET - Other 2 functions same as the ones in subCircuit - - - trackLibrary - - - trackLibraryWithoutButton + - trackLibrary + - trackLibraryWithoutButton """ def __init__(self, schematicInfo, clarg1): @@ -62,14 +61,14 @@ class DeviceModel(QtGui.QWidget): # Set Layout self.grid = QtGui.QGridLayout() self.setLayout(self.grid) - print("Reading Device model details from Schematic") + # print("Reading Device model details from Schematic") for eachline in schematicInfo: print("=========================================") print(eachline) words = eachline.split() if eachline[0] == 'q': - print("Device Model Transistor: ", words[0]) + # print("Device Model Transistor: ", words[0]) self.devicemodel_dict_beg[words[0]] = self.count transbox = QtGui.QGroupBox() transgrid = QtGui.QGridLayout() @@ -85,8 +84,6 @@ class DeviceModel(QtGui.QWidget): try: for key in json_data["deviceModel"]: if key == words[0]: - # print "DEVICE MODEL MATCHING---",child.tag[0],\ - # child.tag[1],eachline[0],eachline[1] try: if os.path.exists( json_data["deviceModel"][key][0]): @@ -128,7 +125,7 @@ class DeviceModel(QtGui.QWidget): self.grid.addWidget(transbox) - # Adding Device Details + # Adding Device Details # # Increment row and widget count self.row = self.row + 1 @@ -136,7 +133,7 @@ class DeviceModel(QtGui.QWidget): self.count = self.count + 1 elif eachline[0] == 'd': - print("Device Model Diode:", words[0]) + # print("Device Model Diode:", words[0]) self.devicemodel_dict_beg[words[0]] = self.count diodebox = QtGui.QGroupBox() diodegrid = QtGui.QGridLayout() @@ -151,8 +148,6 @@ class DeviceModel(QtGui.QWidget): try: for key in json_data["deviceModel"]: if key == words[0]: - # print "DEVICE MODEL MATCHING---",child.tag[0],\ - # child.tag[1],eachline[0],eachline[1] try: if os.path.exists( json_data["deviceModel"][key][0]): @@ -193,7 +188,7 @@ class DeviceModel(QtGui.QWidget): self.grid.addWidget(diodebox) - # Adding Device Details + # Adding Device Details # # Increment row and widget count self.row = self.row + 1 @@ -201,7 +196,7 @@ class DeviceModel(QtGui.QWidget): self.count = self.count + 1 elif eachline[0] == 'j': - print("Device Model JFET:", words[0]) + # print("Device Model JFET:", words[0]) self.devicemodel_dict_beg[words[0]] = self.count jfetbox = QtGui.QGroupBox() jfetgrid = QtGui.QGridLayout() @@ -216,8 +211,6 @@ class DeviceModel(QtGui.QWidget): try: for key in json_data["deviceModel"]: if key == words[0]: - # print "DEVICE MODEL MATCHING---",child.tag[0],\ - # child.tag[1],eachline[0],eachline[1] try: if os.path.exists( json_data["deviceModel"][key][0]): @@ -258,7 +251,8 @@ class DeviceModel(QtGui.QWidget): self.grid.addWidget(jfetbox) - # Adding Device Details + # Adding Device Details # + # Increment row and widget count self.row = self.row + 1 self.devicemodel_dict_end[words[0]] = self.count @@ -329,8 +323,6 @@ class DeviceModel(QtGui.QWidget): try: for key in json_data["deviceModel"]: if key == words[0]: - # print "DEVICE MODEL MATCHING---",child.tag[0],\ - # child.tag[1],eachline[0],eachline[1] while i <= end: self.entry_var[i].setText( json_data["deviceModel"][key][i - beg]) @@ -367,7 +359,6 @@ class DeviceModel(QtGui.QWidget): """ print("Calling Track Device Model Library funtion") sending_btn = self.sender() - # print "Object Called is ",sending_btn.objectName() self.widgetObjCount = int(sending_btn.objectName()) self.libfile = str( @@ -376,14 +367,12 @@ class DeviceModel(QtGui.QWidget): "Open Library Directory", "../deviceModelLibrary", "*.lib")) - # print "Selected Library File :",self.libfile # Setting Library to Text Edit Line self.entry_var[self.widgetObjCount].setText(self.libfile) self.deviceName = self.deviceDetail[self.widgetObjCount] # Storing to track it during conversion - if self.deviceName[0] == 'm': width = str(self.entry_var[self.widgetObjCount + 1].text()) length = str(self.entry_var[self.widgetObjCount + 2].text()) @@ -406,19 +395,16 @@ class DeviceModel(QtGui.QWidget): This function is use to keep track of all Device Model widget """ print("Calling Track Library function Without Button") - # print "Object Called is ",sending_btn.objectName() self.widgetObjCount = iter_value print("self.widgetObjCount-----", self.widgetObjCount) self.libfile = path_value print("PATH VALUE", path_value) - # print "Selected Library File :",self.libfile # Setting Library to Text Edit Line self.entry_var[self.widgetObjCount].setText(self.libfile) self.deviceName = self.deviceDetail[self.widgetObjCount] # Storing to track it during conversion - if self.deviceName[0] == 'm': width = str(self.entry_var[self.widgetObjCount + 1].text()) length = str(self.entry_var[self.widgetObjCount + 2].text()) diff --git a/src/kicadtoNgspice/KicadtoNgspice.py b/src/kicadtoNgspice/KicadtoNgspice.py index ef9201cb..ab2e55e8 100644 --- a/src/kicadtoNgspice/KicadtoNgspice.py +++ b/src/kicadtoNgspice/KicadtoNgspice.py @@ -1,5 +1,4 @@ # ========================================================================= -# # FILE: kicadtoNgspice.py # # USAGE: --- @@ -11,10 +10,12 @@ # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. # CREATED: Wednesday 04 March 2015 -# REVISION: --- +# REVISION: Friday 14 February 2020 # ========================================================================= + import sys import os from PyQt4 import QtGui @@ -28,8 +29,6 @@ from . import Convert from . import TrackWidget import json -# from xml.etree import ElementTree as ET - class MainWindow(QtGui.QWidget): """ @@ -37,7 +36,7 @@ class MainWindow(QtGui.QWidget): - And Call Convert function if convert button is pressed. - The convert function takes all the value entered by user and create a final netlist "*.cir.out". - - This final netlist is compatible with NgSpice. + - This final netlist is compatible with Ngspice. - clarg1 is the path to the .cir file - clarg2 is either None or "sub" depending on the analysis type """ @@ -54,10 +53,10 @@ class MainWindow(QtGui.QWidget): self.clarg2 = clarg2 # Create object of track widget - # Track the dynamically created widget of KicadtoNgSpice Window + # Track the dynamically created widget of KicadtoNgspice Window self.obj_track = TrackWidget.TrackWidget() - # Clear Dictionary/List item of sub circuit and ngspice model + # Clear Dictionary/List item of sub circuit and Ngspice model # Dictionary self.obj_track.subcircuitList.clear() self.obj_track.subcircuitTrack.clear() @@ -70,22 +69,21 @@ class MainWindow(QtGui.QWidget): # Read the netlist, ie the .cir file kicadNetlist = obj_proc.readNetlist(self.kicadFile) - print("=============================================================") - print("Given Kicad Schematic Netlist Info :", kicadNetlist) + # print("=============================================================") + # print("Given Kicad Schematic Netlist Info :", kicadNetlist) # Construct parameter information param = obj_proc.readParamInfo(kicadNetlist) # Replace parameter with values netlist, infoline = obj_proc.preprocessNetlist(kicadNetlist, param) - print("=============================================================") - print("Schematic Info after processing Kicad Netlist: ", netlist) - # print "INFOLINE",infoline + # print("=============================================================") + # print("Schematic Info after processing Kicad Netlist: ", netlist) # Separate option and schematic information optionInfo, schematicInfo = obj_proc.separateNetlistInfo(netlist) - print("=============================================================") - print("OPTIONINFO in the Netlist", optionInfo) + # print("=============================================================") + # print("OPTIONINFO in the Netlist", optionInfo) # List for storing source and its value global sourcelist, sourcelisttrack @@ -111,8 +109,8 @@ class MainWindow(QtGui.QWidget): ) = obj_proc.convertICintoBasicBlocks( schematicInfo, outputOption, modelList, plotText ) - print("=======================================") - print("Model available in the Schematic :", modelList) + # print("=======================================") + # print("Model available in the Schematic :", modelList) """ - Checking if any unknown model is used in schematic which is not @@ -141,13 +139,13 @@ class MainWindow(QtGui.QWidget): def createMainWindow(self): """ - - This function create main window of Kicad to Ngspice converter + - This function create main window of KiCad to Ngspice converter - Two components - - - createcreateConvertWidget - - - Convert button => callConvert + - createcreateConvertWidget + - Convert button => callConvert """ - self.vbox = QtGui.QVBoxLayout(self) - self.hbox = QtGui.QHBoxLayout(self) + self.vbox = QtGui.QVBoxLayout() + self.hbox = QtGui.QHBoxLayout() self.hbox.addStretch(1) self.convertbtn = QtGui.QPushButton("Convert") self.convertbtn.clicked.connect(self.callConvert) @@ -162,23 +160,23 @@ class MainWindow(QtGui.QWidget): def createcreateConvertWidget(self): """ - Contains the tabs for various convertor elements - - - Analysis => obj_analysis + - Analysis => obj_analysis => Analysis.Analysis(`path_to_projFile`) - - - Source Details => obj_source + - Source Details => obj_source => Source.Source(`sourcelist`,`sourcelisttrack`,`path_to_projFile`) - - - NgSpice Model => obj_model + - NgSpice Model => obj_model => Model.Model(`schematicInfo`,`modelList`,`path_to_projFile`) - - - Device Modelling => obj_devicemodel + - Device Modelling => obj_devicemodel => DeviceModel.DeviceModel(`schematicInfo`,`path_to_projFile`) - - - Subcircuits => obj_subcircuitTab + - Subcircuits => obj_subcircuitTab => SubcircuitTab.SubcircuitTab(`schematicInfo`,`path_to_projFile`) - Finally pass each of these objects, to widgets - - convertWindow > mainLayout > tabWidgets > AnalysisTab, SourceTab .... + - convertWindow > mainLayout > tabWidgets > AnalysisTab, SourceTab ... """ global obj_analysis self.convertWindow = QtGui.QWidget() @@ -268,8 +266,6 @@ class MainWindow(QtGui.QWidget): json_data["analysis"]["ac"]["Lin"] = "false" json_data["analysis"]["ac"]["Dec"] = "false" json_data["analysis"]["ac"]["Oct"] = "true" - else: - pass json_data["analysis"]["ac"]["Start Frequency"] = str( obj_analysis.ac_entry_var[0].text()) @@ -594,11 +590,11 @@ class MainWindow(QtGui.QWidget): print("=========================================================") self.createNetlistFile(store_schematicInfo, plotText) - self.msg = "The Kicad to Ngspice Conversion completed\ - successfully!" + self.msg = "The Kicad to Ngspice Conversion completed " + self.msg += "successfully!" QtGui.QMessageBox.information( - self, "Information", self.msg, QtGui.QMessageBox.Ok) - + self, "Information", self.msg, QtGui.QMessageBox.Ok + ) except Exception as e: print("Exception Message: ", e) print("There was error while converting kicad to ngspice") @@ -615,31 +611,26 @@ class MainWindow(QtGui.QWidget): """ - Creating .cir.out file - If analysis file present uses that and extract - - - Simulator - - - Initial - - - Analysis + - Simulator + - Initial + - Analysis - Finally add the following components to .cir.out file - - - SimulatorOption - - - InitialCondOption - - - Store_SchematicInfo - - - AnalysisOption + - SimulatorOption + - InitialCondOption + - Store_SchematicInfo + - AnalysisOption - In the end add control statements and allv, alli, end statements """ print("=============================================================") print("Creating Final netlist") - # print "INFOLINE",infoline - # print "OPTIONINFO",optionInfo - # print "Device MODEL LIST ",devicemodelList - # print "SUBCKT ",subcktList - # print "OUTPUTOPTION",outputOption - # print "KicadfIle",kicadFile + # To avoid writing optionInfo twice in final netlist store_optionInfo = list(optionInfo) # checking if analysis files is present (projpath, filename) = os.path.split(self.kicadFile) analysisFileLoc = os.path.join(projpath, "analysis") - # print "Analysis File Location",analysisFileLoc + if os.path.exists(analysisFileLoc): try: f = open(analysisFileLoc) @@ -653,7 +644,7 @@ class MainWindow(QtGui.QWidget): Please check it") sys.exit() else: - print("========================================================") + # print("========================================================") print(analysisFileLoc + " does not exist") sys.exit() @@ -664,10 +655,7 @@ class MainWindow(QtGui.QWidget): if len(eachline) > 1: if eachline[0] == '.': store_optionInfo.append(eachline) - else: - pass - # print "Option Info",optionInfo analysisOption = [] initialCondOption = [] simulatorOption = [] @@ -743,7 +731,7 @@ class MainWindow(QtGui.QWidget): except BaseException: print("Error in opening .cir.out file.") else: - print("=========================================================") + # print("=========================================================") print( self.projName + ".cir.out does not exist. Please create a spice netlist.") @@ -751,8 +739,8 @@ class MainWindow(QtGui.QWidget): # Read the data from file data = f.read() # Close the file - f.close() + newNetlist = [] netlist = iter(data.splitlines()) for eachline in netlist: @@ -803,5 +791,5 @@ class MainWindow(QtGui.QWidget): out.writelines('\n') out.writelines('.ends ' + self.projName) - print("=============================================================") + # print("=============================================================") print("The subcircuit has been written in " + self.projName + ".sub") diff --git a/src/kicadtoNgspice/Model.py b/src/kicadtoNgspice/Model.py index a182dd4e..3cc3a0cb 100644 --- a/src/kicadtoNgspice/Model.py +++ b/src/kicadtoNgspice/Model.py @@ -1,7 +1,6 @@ from PyQt4 import QtGui import json from . import TrackWidget -# from xml.etree import ElementTree as ET import os @@ -59,8 +58,6 @@ class Model(QtGui.QWidget): # line[7] is parameter dictionary holding parameter tags. i = 0 for key, value in line[7].items(): - # print "Key : ",key - # print "Value : ",value # Check if value is iterable if not isinstance(value, str) and hasattr(value, '__iter__'): # For tag having vector value @@ -127,7 +124,6 @@ class Model(QtGui.QWidget): self.nextrow = self.nextrow + 1 self.end = self.nextcount - 1 - # print "End",self.end modelbox.setLayout(modelgrid) # CSS @@ -173,6 +169,4 @@ class Model(QtGui.QWidget): if check == 0: self.obj_trac.modelTrack.append(lst) - # print "The tag dictionary : ",tag_dict - self.show() diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py index a0f2c79f..1e58daac 100644 --- a/src/kicadtoNgspice/Processing.py +++ b/src/kicadtoNgspice/Processing.py @@ -13,30 +13,28 @@ class PrcocessNetlist: def __init__(self): pass - """ - - Read the circuit file and return splitted lines - """ - def readNetlist(self, filename): + """ + - Read the circuit file and return splitted lines + """ f = open(filename) data = f.read() f.close() - print("=============================================================") - print("readNetList called, from Processing") - print("=============================================================") - print("NETLIST", data.splitlines()) - print("=============================================================") + # print("=============================================================") + # print("readNetList called, from Processing") + # print("=============================================================") + # print("NETLIST", data.splitlines()) + # print("=============================================================") return data.splitlines() - """ - - Read Parameter information and store it into dictionary - - kicadNetlis is the .cir file content - """ - - def readParamInfo(self, kicadNetlis): + def readParamInfo(self, kicadNetlist): + """ + - Read Parameter information and store it into dictionary + - kicadNetlist is the .cir file content + """ param = {} - print("=========================KICADNETLIST========================") - for eachline in kicadNetlis: + # print("=========================KICADNETLIST========================") + for eachline in kicadNetlist: print(eachline) eachline = eachline.strip() if len(eachline) > 1: @@ -46,21 +44,20 @@ class PrcocessNetlist: for i in range(1, len(words), 1): paramList = words[i].split('=') param[paramList[0]] = paramList[1] - print("=============================================================") - print("readParamInfo called, from Processing") - print("=============================================================") - print("PARAM", param) - print("=============================================================") + # print("=============================================================") + # print("readParamInfo called, from Processing") + # print("=============================================================") + # print("PARAM", param) + # print("=============================================================") return param - """ - - Preprocess netlist (replace parameters) - - Separate infoline (first line) from the rest of netlist - """ - - def preprocessNetlist(self, kicadNetlis, param): + def preprocessNetlist(self, kicadNetlist, param): + """ + - Preprocess netlist (replace parameters) + - Separate infoline (first line) from the rest of netlist + """ netlist = [] - for eachline in kicadNetlis: + for eachline in kicadNetlist: # Remove leading and trailing blanks spaces from line eachline = eachline.strip() # Remove special character $ @@ -89,12 +86,12 @@ class PrcocessNetlist: # Copy information line infoline = netlist[0] netlist.remove(netlist[0]) - print("=============================================================") + """print("=============================================================") print("preprocessNetList called, from Processing") print("=============================================================") print("NETLIST", netlist) print("INFOLINE", infoline) - print("=============================================================") + print("=============================================================")""" return netlist, infoline def separateNetlistInfo(self, netlist): @@ -114,26 +111,25 @@ class PrcocessNetlist: optionInfo.append(eachline) else: schematicInfo.append(eachline) - print("=============================================================") + """print("=============================================================") print("separateNetlistInfo called, from Processing") print("=============================================================") print("OPTIONINFO", optionInfo) print("SCHEMATICINFO", schematicInfo) - print("=============================================================") + print("=============================================================")""" return optionInfo, schematicInfo - """ - - Insert Special source parameter - - As per the parameters passed create source list, start with v or i - - Then check for type whether ac, dc, sine, etc... - - Handle starting with h and f as well - """ - def insertSpecialSourceParam(self, schematicInfo, sourcelist): + """ + - Insert Special source parameter + - As per the parameters passed create source list, start with v or i + - Then check for type whether ac, dc, sine, etc... + - Handle starting with h and f as well + """ schematicInfo1 = [] - print("=============================================================") - print("Reading schematic info for source details") - print("=============================================================") + # print("=============================================================") + # print("Reading schematic info for source details") + # print("=============================================================") for compline in schematicInfo: words = compline.split() compName = words[0] @@ -217,14 +213,14 @@ class PrcocessNetlist: words[5]) schematicInfo = schematicInfo + schematicInfo1 - print("Source List : ", sourcelist) - # print schematicInfo - print("=============================================================") + # print("Source List : ", sourcelist) + + """print("=============================================================") print("insertSpecialSourceParam called, from Processing") print("=============================================================") print("SCHEMATICINFO", schematicInfo) print("SOURCELIST", sourcelist) - print("=============================================================") + print("=============================================================")""" return schematicInfo, sourcelist def convertICintoBasicBlocks( @@ -239,8 +235,8 @@ class PrcocessNetlist: - - Plot text - Parsing info is provided below """ - print("=============================================================") - print("Reading Schematic info for Model") + # print("=============================================================") + # print("Reading Schematic info for Model") # Insert details of Ngspice model unknownModelList = [] multipleModelList = [] @@ -293,8 +289,8 @@ class PrcocessNetlist: unknownModelList.append(compType) elif count == 1: try: - print("==========================================\ - ===========================") + # print("==========================================\ + # ===========================") print( "Start Parsing Previous Values XML\ for ngspice model :", modelPath) @@ -355,9 +351,9 @@ class PrcocessNetlist: modelLine += compName else: - print("=====================================\ - ================================") - print("Split Details :", splitDetail) + # print("=====================================\ + # ================================") + # print("Split Details :", splitDetail) modelLine = "a" + str(k) + " " vectorDetail = splitDetail.split(':') # print "Vector Details",vectorDetail @@ -507,7 +503,7 @@ class PrcocessNetlist: else: schematicInfo.insert(index, "* " + compline) - print("=====================================================") + # print("=====================================================") print( "UnknownModelList Used in the Schematic", unknownModelList) @@ -516,7 +512,7 @@ class PrcocessNetlist: "Multiple Model XML file with same name ", multipleModelList) print("=====================================================") - print("Model List Details : ", modelList) + # print("Model List Details : ", modelList) print("=============================================================") print("convertICIntoBasicBlocks called, from Processing") print("=============================================================") diff --git a/src/kicadtoNgspice/Source.py b/src/kicadtoNgspice/Source.py index 26555197..6c5ae637 100644 --- a/src/kicadtoNgspice/Source.py +++ b/src/kicadtoNgspice/Source.py @@ -1,7 +1,6 @@ import os from PyQt4 import QtGui from . import TrackWidget -# from xml.etree import ElementTree as ET import json @@ -13,7 +12,7 @@ class Source(QtGui.QWidget): def __init__(self, sourcelist, sourcelisttrack, clarg1): QtGui.QWidget.__init__(self) self.obj_track = TrackWidget.TrackWidget() - # Variable + # Variables self.count = 1 self.clarg1 = clarg1 self.start = 0 @@ -45,10 +44,10 @@ class Source(QtGui.QWidget): - Each line in sourcelist corresponds to a source - According to the source type modify the source and add it to the tab """ - print("============================================================") + """print("============================================================") print("SOURCE LIST TRACK", sourcelisttrack) print("SOURCE LIST", sourcelist) - print("============================================================") + print("============================================================")""" kicadFile = self.clarg1 (projpath, filename) = os.path.split(kicadFile) project_name = os.path.basename(projpath) @@ -71,10 +70,8 @@ class Source(QtGui.QWidget): if sourcelist: for line in sourcelist: - # print "Voltage source line index: ",line[0] print("SourceList line: ", line) track_id = line[0] - # print "track_id is ",track_id if line[2] == 'ac': acbox = QtGui.QGroupBox() acbox.setTitle(line[3]) @@ -372,7 +369,7 @@ class Source(QtGui.QWidget): else: print("No source is present in your circuit") - print("============================================================") + # print("============================================================") # This is used to keep the track of dynamically created widget self.obj_track.sourcelisttrack["ITEMS"] = sourcelisttrack self.obj_track.source_entry_var["ITEMS"] = self.entry_var diff --git a/src/kicadtoNgspice/SubcircuitTab.py b/src/kicadtoNgspice/SubcircuitTab.py index d15407f7..116b70b1 100644 --- a/src/kicadtoNgspice/SubcircuitTab.py +++ b/src/kicadtoNgspice/SubcircuitTab.py @@ -3,7 +3,6 @@ import json from . import TrackWidget from projManagement import Validation import os -# from xml.etree import ElementTree as ET class SubcircuitTab(QtGui.QWidget): @@ -61,7 +60,7 @@ class SubcircuitTab(QtGui.QWidget): for eachline in schematicInfo: words = eachline.split() if eachline[0] == 'x': - print("Subcircuit : Words", words[0]) + # print("Subcircuit : Words", words[0]) self.obj_trac.subcircuitList[project_name + words[0]] = words self.subcircuit_dict_beg[words[0]] = self.count subbox = QtGui.QGroupBox() @@ -74,8 +73,6 @@ class SubcircuitTab(QtGui.QWidget): try: for key in json_data["subcircuit"]: if key == words[0]: - # print "Subcircuit MATCHING---",child.tag[0], \ - # child.tag[1], eachline[0], eachline[1] try: if os.path.exists( json_data["subcircuit"][key][0]): @@ -97,7 +94,7 @@ class SubcircuitTab(QtGui.QWidget): # eg. If the line is 'x1 4 0 3 ua741', there are 3 ports(4, 0 # and 3). self.numPorts.append(len(words) - 2) - print("Number of ports of sub circuit : ", self.numPorts) + # print("Number of ports of sub circuit : ", self.numPorts) self.addbtn.clicked.connect(self.trackSubcircuit) subgrid.addWidget(self.addbtn, self.row, 2) subbox.setLayout(subgrid) @@ -166,8 +163,8 @@ class SubcircuitTab(QtGui.QWidget): elif self.reply == "DIREC": self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - "Please select a valid Subcircuit directory \ - (Containing '.sub' file).") + "Please select a valid Subcircuit directory " + "(Containing '.sub' file).") self.msg.setWindowTitle("Error Message") self.msg.show() @@ -189,7 +186,6 @@ class SubcircuitTab(QtGui.QWidget): self.subName = self.subDetail[self.widgetObjCount] # Storing to track it during conversion - self.obj_trac.subcircuitTrack[self.subName] = self.subfile elif self.reply == "PORT": self.msg = QtGui.QErrorMessage(self) @@ -200,7 +196,7 @@ class SubcircuitTab(QtGui.QWidget): elif self.reply == "DIREC": self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - "Please select a valid Subcircuit directory \ - (Containing '.sub' file).") + "Please select a valid Subcircuit directory " + "(Containing '.sub' file).") self.msg.setWindowTitle("Error Message") self.msg.show() diff --git a/src/kicadtoNgspice/TrackWidget.py b/src/kicadtoNgspice/TrackWidget.py index ec5c2c81..3a8b0dac 100644 --- a/src/kicadtoNgspice/TrackWidget.py +++ b/src/kicadtoNgspice/TrackWidget.py @@ -2,11 +2,11 @@ class TrackWidget: """ - This Class track the dynamically created widget of KicadtoNgSpice Window. - Tracks using dictionary and lists ==> - - - Sources - - - Parameters - - - References - - - Model Details - - - ... etc + - Sources + - Parameters + - References + - Model Details + - ... etc """ # Track widget list for Source details sourcelisttrack = {"ITEMS": "None"} diff --git a/src/modelEditor/ModelEditor.py b/src/modelEditor/ModelEditor.py index 634c1fe3..3f616808 100644 --- a/src/modelEditor/ModelEditor.py +++ b/src/modelEditor/ModelEditor.py @@ -12,20 +12,20 @@ class ModelEditorclass(QtGui.QWidget): - Initalise directory to save new models, savepathtest = '../deviceModelLibrary' - Initialise buttons and options ====> - - - Name Function Called + - Name Function Called ======================================== - - - New opennew - - - Edit openedit - - - Save savemodelfile - - - Upload converttoxml - - - Add addparameters - - - Remove removeparameter - - - Diode diode_click - - - BJT bjt_click - - - MOS mos_click - - - JFET jfet_click - - - IGBT igbt_click - - - Magnetic Core magnetic_click + - New opennew + - Edit openedit + - Save savemodelfile + - Upload converttoxml + - Add addparameters + - Remove removeparameter + - Diode diode_click + - BJT bjt_click + - MOS mos_click + - JFET jfet_click + - IGBT igbt_click + - Magnetic Core magnetic_click ''' def __init__(self): @@ -301,8 +301,6 @@ class ModelEditorclass(QtGui.QWidget): if filetype == 'Magnetic Core': path = os.path.join(self.path, 'CORE.xml') self.createtable(path) - else: - pass def openedit(self): ''' diff --git a/src/modelParamXML/Analog/gain.xml b/src/modelParamXML/Analog/gain.xml index ff71d46a..a8656072 100644 --- a/src/modelParamXML/Analog/gain.xml +++ b/src/modelParamXML/Analog/gain.xml @@ -6,7 +6,7 @@ <split>None</split> <param> <in_offset default="0.0">Enter offset for input (default=0.0)</in_offset> - <gain vector="2" default="1.0">Enter gain (default=1.0)</gain> + <gain vector="1" default="1.0">Enter gain (default=1.0)</gain> <out_offset default="0.0">Enter offset for output (default=0.0)</out_offset> </param> </model>
\ No newline at end of file diff --git a/src/modelParamXML/Nghdl/.gitignore b/src/modelParamXML/Nghdl/.gitignore new file mode 100644 index 00000000..86d0cb27 --- /dev/null +++ b/src/modelParamXML/Nghdl/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore
\ No newline at end of file diff --git a/src/modelParamXML/Nghdl/inverter.xml b/src/modelParamXML/Nghdl/inverter.xml deleted file mode 100644 index 894389e0..00000000 --- a/src/modelParamXML/Nghdl/inverter.xml +++ /dev/null @@ -1 +0,0 @@ -<model><name>inverter</name><type>Nghdl</type><node_number>2</node_number><title>Add parameters for inverter</title><split>2-V:2-V</split><param><rise_delay default="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay><fall_delay default="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay><input_load default="1.0e-12">Enter Input Load (default=1.0e-12)</input_load><instance_id default="1">Enter Instance ID (Between 0-99)</instance_id></param></model>
\ No newline at end of file diff --git a/src/modelParamXML/Nghdl/myxor.xml b/src/modelParamXML/Nghdl/myxor.xml deleted file mode 100644 index c245879e..00000000 --- a/src/modelParamXML/Nghdl/myxor.xml +++ /dev/null @@ -1 +0,0 @@ -<model><name>myxor</name><type>Nghdl</type><node_number>3</node_number><title>Add parameters for myxor</title><split>1-V:1-V:1-V</split><param><rise_delay default="1.0e-9">Enter Rise Delay (default=1.0e-9)</rise_delay><fall_delay default="1.0e-9">Enter Fall Delay (default=1.0e-9)</fall_delay><input_load default="1.0e-12">Enter Input Load (default=1.0e-12)</input_load><instance_id default="1">Enter Instance ID (Between 0-99)</instance_id></param></model>
\ No newline at end of file diff --git a/src/ngspiceSimulation/pythonPlotting.py b/src/ngspiceSimulation/pythonPlotting.py index bbcc981f..e19b49de 100644 --- a/src/ngspiceSimulation/pythonPlotting.py +++ b/src/ngspiceSimulation/pythonPlotting.py @@ -1,5 +1,5 @@ -from __future__ import division # Used for decimal division eg -# 2/3=0.66 and not '0' 6/2=3.0 and 6//2=3 +from __future__ import division # Used for decimal division +# eg: 2/3=0.66 and not '0' 6/2=3.0 and 6//2=3 import os from PyQt4 import QtGui, QtCore from decimal import Decimal, getcontext @@ -264,20 +264,17 @@ class plotWindow(QtGui.QMainWindow): # p = 0 for i in range(len(self.parts)): - # print "I",i if i % 2 == 0: - # print "I'm in:" for j in range(len(self.obj_dataext.NBList)): if self.parts[i] == self.obj_dataext.NBList[j]: - # print "I got you:",self.parts[i] a.append(j) if len(a) != len(self.parts) // 2 + 1: QtGui.QMessageBox.about( self, "Warning!!", - "One of the operands doesn't belong to\ - the above list of Nodes!!") + "One of the operands doesn't belong to " + "the above list of Nodes!!") for i in a: self.comboAll.append(self.obj_dataext.y[i]) @@ -286,11 +283,11 @@ class plotWindow(QtGui.QMainWindow): if a[i] == len(self.obj_dataext.NBList): QtGui.QMessageBox.about( - self, "Warning!!", "One of the operands doesn't belong\ - to the above list!!") + self, "Warning!!", "One of the operands doesn't belong " + "to the above list!!") self.warnning.setText( - "<font color='red'>To Err Is Human!<br>One of the operands\ - doesn't belong to the above list!!</font>") + "<font color='red'>To Err Is Human!<br>One of the " + + "operands doesn't belong to the above list!!</font>") if self.parts[1] == 'vs': if len(self.parts) > 3: @@ -391,7 +388,6 @@ class plotWindow(QtGui.QMainWindow): # definition of functions onPush_decade, onPush_ac, onPush_trans,\ # onPush_dc, color and multimeter and getRMSValue. def onPush_decade(self): - # print "Calling on push Decade" boxCheck = 0 self.axes.cla() @@ -591,7 +587,6 @@ class DataExtraction: # 'inumber' gives total number of current p = npv = vnumber = inumber = 0 - # print "VoltsData : ",self.voltData # Finding totla number of voltage node for i in self.voltData[3:]: @@ -599,22 +594,16 @@ class DataExtraction: if "Index" in i: # "V(" in i or "x1" in i or "u3" in i: vnumber += 1 - # print "Voltage Number :",vnumber - # Reading Current Source Data with open(os.path.join(fpath, "plot_data_i.txt")) as f1: self.currentData = f1.read() self.currentData = self.currentData.split("\n") - # print "CurrentData : ",self.currentData - # Finding Number of Branch for i in self.currentData[3:]: if "#branch" in i: inumber += 1 - # print "Current Number :",inumber - self.dec = 0 # For AC @@ -655,14 +644,9 @@ class DataExtraction: if "DC" in i: # DC for dc files and AC for ac ones break - # print "VoltNumber",vnumber - # print "CurrentNumber",inumber vnumber = vnumber // npv # vnumber gives the no of voltage nodes inumber = inumber // npv # inumber gives the no of branches - # print "VoltNumber",vnumber - # print "CurrentNumber",inumber - p = [p, vnumber, self.analysisType, self.dec, inumber] return p @@ -691,7 +675,6 @@ class DataExtraction: self.NBIList.append(l) self.NBIList = self.NBIList[2:] len_NBIList = len(self.NBIList) - # print "NBILIST : ",self.NBIList except Exception as e: print("Exception Message : ", str(e)) self.obj_appconfig.print_error('Exception Message :' + str(e)) @@ -706,7 +689,6 @@ class DataExtraction: d4 = d[4] dec = [d3, d[3]] - # print "No. of Nodes:", d2 self.NBList = [] allv = allv.split("\n") for l in allv[3].split(" "): @@ -747,13 +729,11 @@ class DataExtraction: for i in alli[5:d1 - 1]: if len(i.split("\t")) == inum_i: j2 = i.split("\t") - # print j2 j2.pop(0) j2.pop(0) j2.pop() if d3 == 0: # not in trans j2.pop() - # print j2 for l in range(1, d4): j3 = alli[5 + l * d1 + k].split("\t") @@ -763,14 +743,11 @@ class DataExtraction: j3.pop() # not required for dc j3.pop() j2 = j2 + j3 - # print j2 full_data.append(j2) k += 1 - # print "FULL DATA :",full_data - for i in allv[5:d1 - 1]: if len(i.split("\t")) == inum: j = i.split("\t") @@ -790,9 +767,8 @@ class DataExtraction: j1.pop() j = j + j1 j = j + full_data[m] - # print j m += 1 - # print j[:20] + j = "\t".join(j[1:]) j = j.replace(",", "") ivals.append(j) @@ -801,7 +777,6 @@ class DataExtraction: self.data = ivals - # print "volts:",self.butnames self.volts_length = len(self.NBList) self.NBList = self.NBList + self.NBIList @@ -811,12 +786,10 @@ class DataExtraction: def numVals(self): a = self.volts_length # No of voltage nodes b = len(self.data[0].split("\t")) - # print "numvals:",b return [b, a] def computeAxes(self): nums = len(self.data[0].split("\t")) - # print "i'm nums:",nums self.y = [] var = self.data[0].split("\t") for i in range(1, nums): diff --git a/src/ngspicetoModelica/ModelicaUI.py b/src/ngspicetoModelica/ModelicaUI.py index eca03534..d5daf9ad 100644 --- a/src/ngspicetoModelica/ModelicaUI.py +++ b/src/ngspicetoModelica/ModelicaUI.py @@ -44,13 +44,11 @@ class OpenModelicaEditor(QtGui.QWidget): self.show() def browseFile(self): - self.ngspiceNetlist = QtGui.QFileDialog.getOpenFileName( self, 'Open Ngspice file', BROWSE_LOCATION) self.FileEdit.setText(self.ngspiceNetlist) def callConverter(self): - try: self.cmd1 = ( "python3 ../ngspicetoModelica/NgspicetoModelica.py " + @@ -67,17 +65,18 @@ class OpenModelicaEditor(QtGui.QWidget): stderr=STDOUT, close_fds=True) error_code = convert_process.stdout.read() + if not error_code: self.msg = QtGui.QMessageBox() self.msg.setText( "Ngspice netlist successfully converted to OpenModelica" + - "netlist") + "netlist" + ) self.obj_appconfig.print_info( "Ngspice netlist successfully converted to OpenModelica" + "netlist" ) self.msg.exec_() - else: self.err_msg = QtGui.QErrorMessage() self.err_msg.showMessage( diff --git a/src/projManagement/Kicad.py b/src/projManagement/Kicad.py index 0b34015f..02695ef4 100644 --- a/src/projManagement/Kicad.py +++ b/src/projManagement/Kicad.py @@ -1,19 +1,19 @@ # ========================================================================= -# -# FILE: openKicad.py +# FILE: Kicad.py # # USAGE: --- # -# DESCRIPTION: It call kicad schematic +# DESCRIPTION: It calls kicad schematic # # OPTIONS: --- # REQUIREMENTS: --- # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. -# CREATED: Tuesday 17 Feb 2015 -# REVISION: --- +# CREATED: Tuesday 17 February 2015 +# REVISION: Friday 14 February 2020 # ========================================================================= import os @@ -24,7 +24,6 @@ from PyQt4 import QtGui class Kicad: - """ This class called the Kicad Schematic,KicadtoNgspice Converter,Layout editor and Footprint Editor @@ -41,6 +40,28 @@ class Kicad: self.obj_validation = Validation.Validation() self.obj_appconfig = Appconfig() self.obj_dockarea = dockarea + self.obj_workThread = Worker.WorkerThread(None) + + def check_open_schematic(self): + """ + This function checks if any of the project's schematic is open or not + + @params + + @return + True => If the project's schematic is not open + False => If the project's schematic is open + """ + if self.obj_workThread: + procList = self.obj_workThread.get_proc_threads()[:] + if procList: + for proc in procList: + if proc.poll() is None: + return True + else: + self.obj_workThread.get_proc_threads().remove(proc) + + return False def openSchematic(self): """ @@ -61,27 +82,26 @@ class Kicad: # Validating if current project is available or not if self.obj_validation.validateKicad(self.projDir): - # print "calling Kicad schematic ",self.projDir self.projName = os.path.basename(self.projDir) self.project = os.path.join(self.projDir, self.projName) # Creating a command to run self.cmd = "eeschema " + self.project + ".sch " - self.obj_workThread = Worker.WorkerThread(self.cmd) + self.obj_workThread.args = self.cmd self.obj_workThread.start() else: self.msg = QtGui.QErrorMessage(None) self.msg.showMessage( - 'Please select the project first. You can either create' - + 'new project or open existing project') + 'Please select the project first. You can either ' + + 'create new project or open existing project') self.obj_appconfig.print_warning( - 'Please select the project first. You can either create' - + 'new project or open existing project') + 'Please select the project first. You can either ' + + 'create new project or open existing project') self.msg.setWindowTitle("Error Message") ''' - # Commenting as it is no longer needed as PBC and Layout will open from + # Commenting as it is no longer needed as PCB and Layout will open from # eeschema def openFootprint(self): """ @@ -168,7 +188,7 @@ class Kicad: pass # Validating if current project is available or not if self.obj_validation.validateKicad(self.projDir): - # Cheking if project has .cir file or not + # Checking if project has .cir file or not if self.obj_validation.validateCir(self.projDir): self.projName = os.path.basename(self.projDir) self.project = os.path.join(self.projDir, self.projName) @@ -186,19 +206,19 @@ class Kicad: else: self.msg = QtGui.QErrorMessage(None) self.msg.showMessage( - 'The project does not contain any Kicad netlist file for' - + 'conversion.') + 'The project does not contain any Kicad netlist file ' + + 'for conversion.') self.obj_appconfig.print_error( - 'The project does not contain any Kicad netlist file for' - + 'conversion.') + 'The project does not contain any Kicad netlist file ' + + 'for conversion.') self.msg.setWindowTitle("Error Message") else: self.msg = QtGui.QErrorMessage(None) self.msg.showMessage( - 'Please select the project first. You can either create' - + 'new project or open existing project') + 'Please select the project first. You can either ' + + 'create new project or open existing project') self.obj_appconfig.print_warning( - 'Please select the project first. You can either create' - + 'new project or open existing project') + 'Please select the project first. You can either ' + + 'create new project or open existing project') self.msg.setWindowTitle("Error Message") diff --git a/src/projManagement/Validation.py b/src/projManagement/Validation.py index 451fe831..b2d568e4 100644 --- a/src/projManagement/Validation.py +++ b/src/projManagement/Validation.py @@ -1,5 +1,4 @@ # ========================================================================= -# # FILE: Validation.py # # USAGE: --- @@ -12,33 +11,22 @@ # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. # CREATED: Wednesday 12 February 2015 -# REVISION: --- +# REVISION: Friday 14 February 2020 # ========================================================================= + import os import re import distutils.spawn -""" -This is Validation class use for validating Project. -e.g if .proj is present in project directory -or if new project name is already exist in workspace etc -""" - class Validation: """ - Takes as input the path of the project and checks if - projName.proj file exists - projName is same as the folder selected - - @params - :projDir => contains the path of the project folder selected to open - - @return - True => If the folder contains the projName.proj file - False => If the folder doesn't contain projName.proj file + This is Validation class use for validating Project. + e.g if .proj is present in project directory + or if new project name is already exist in workspace etc """ def __init__(self): @@ -46,7 +34,15 @@ class Validation: def validateOpenproj(self, projDir): """ - This function validate Open Project Information. + Takes as input the path of the project and checks if + projName.proj file exists or not + + @params + :projDir => contains the path of the project folder selected to open + + @return + True => If the folder contains the projName.proj file + False => If the folder doesn't contain projName.proj file """ print("Function: Validating Open Project Information") projName = os.path.basename(str(projDir)) @@ -57,21 +53,17 @@ class Validation: else: return False - """ - Validate new project created - - @params - :projDir => Contains path of the new projDir created - - @return - :"CHECKEXIST" => If smae project name folder exists - :"CHECKNAME" => If space is there in name - :"VALID" => If valid project name given - """ - def validateNewproj(self, projDir): """ - This Project Validate New Project Information + Validate new project created + + @params + :projDir => Contains path of the new projDir created + + @return + :"CHECKEXIST" => If smae project name folder exists + :"CHECKNAME" => If space is there in name + :"VALID" => If valid project name given """ print("Function: Validating New Project Information") @@ -85,44 +77,36 @@ class Validation: else: return "VALID" - """ - Validate if projDir is set appropriately in the function calling file - and if Kicad components are present - - @params - :projDir => the path of the project directory, passed from - the calling function - - @return - True - False - """ - def validateKicad(self, projDir): """ - This function validate if Kicad components are present + Validate if projDir is set appropriately in the function calling file + and if Kicad components are present + + @params + :projDir => the path of the project directory, passed from + the calling function + + @return + True + False """ - print("FUnction : Validating for Kicad components") + print("Function : Validating for Kicad components") if projDir is None: return False else: return True - """ - Validate if cir file present in the directory with the appropriate .cir - file name, same as the project directory base - - @params - :projDir => the path to the project diretory - - @return - True - False - """ - def validateCir(self, projDir): """ - This function checks if ".cir" file is present. + Validate if cir file present in the directory with the appropriate .cir + file name, same as the project directory base + + @params + :projDir => the path to the project diretory + + @return + True + False """ projName = os.path.basename(str(projDir)) lookCir = os.path.join(str(projDir), projName + ".cir") diff --git a/src/projManagement/Worker.py b/src/projManagement/Worker.py index 9b9f57e4..e523b533 100644 --- a/src/projManagement/Worker.py +++ b/src/projManagement/Worker.py @@ -1,5 +1,4 @@ # ========================================================================= -# # FILE: WorkerThread.py # # USAGE: --- @@ -11,10 +10,12 @@ # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. -# CREATED: Tuesday 24 Feb 2015 -# REVISION: --- +# CREATED: Tuesday 24 February 2015 +# REVISION: Friday 14 February 2020 # ========================================================================= + from PyQt4 import QtCore import subprocess from configuration.Appconfig import Appconfig @@ -27,7 +28,6 @@ class WorkerThread(QtCore.QThread): other PyQT windows This is a helper functions, used to create threads for various commands - @params :args => takes a space separated string of comamnds to be execute in different child processes (see subproces.Popen()) @@ -39,6 +39,7 @@ class WorkerThread(QtCore.QThread): def __init__(self, args): QtCore.QThread.__init__(self) self.args = args + self.my_workers = [] def __del__(self): """ @@ -53,6 +54,18 @@ class WorkerThread(QtCore.QThread): """ self.wait() + def get_proc_threads(self): + """ + This function is a getter for the list of project's workers, + and is called to check if project's schematic is open or not. + + @params + + @return + :self.my_workers + """ + return self.my_workers + def run(self): """ run is the function that is called, when we start the thread as @@ -82,6 +95,7 @@ class WorkerThread(QtCore.QThread): procThread = Appconfig() proc = subprocess.Popen(command.split()) + self.my_workers.append(proc) procThread.procThread_list.append(proc) procThread.proc_dict[procThread.current_project['ProjectName']].append( proc.pid) diff --git a/src/projManagement/newProject.py b/src/projManagement/newProject.py index 6f8de2b9..b7cce397 100644 --- a/src/projManagement/newProject.py +++ b/src/projManagement/newProject.py @@ -1,5 +1,4 @@ # ========================================================================= -# # FILE: newProject.py # # USAGE: --- @@ -11,10 +10,12 @@ # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. # CREATED: Wednesday 12 February 2015 -# REVISION: --- +# REVISION: Friday 14 February 2020 # ========================================================================= + from PyQt4 import QtGui from .Validation import Validation from configuration.Appconfig import Appconfig @@ -59,7 +60,6 @@ class NewProjectInfo(QtGui.QWidget): :filelist => The files inside the project folder """ - # print "Create Project Called" self.projName = projName self.workspace = self.obj_appconfig.default_workspace['workspace'] # self.projName = self.projEdit.text() @@ -84,12 +84,11 @@ class NewProjectInfo(QtGui.QWidget): self.projDir, self.projName + ".proj") f = open(self.projFile, "w") except BaseException: - # print "Some Thing Went Wrong" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - 'Unable to create project. Please make sure you have' - + ' write permission on ' - + self.workspace) + 'Unable to create project. Please make sure you have ' + + 'write permission on ' + self.workspace + ) self.msg.setWindowTitle("Error Message") f.write("schematicFile " + self.projName + ".sch\n") f.close() @@ -112,24 +111,21 @@ class NewProjectInfo(QtGui.QWidget): return self.projDir, newprojlist elif self.reply == "CHECKEXIST": - # print "Project already exist" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - 'The project "' - + self.projName - + '" already exist.Please select the different name or delete' - + ' existing project') + 'The project "' + self.projName + + '" already exist.Please select the different name or delete' + + ' existing project' + ) self.msg.setWindowTitle("Error Message") elif self.reply == "CHECKNAME": - # print "Name is not proper" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( 'The project name should not contain space between them') self.msg.setWindowTitle("Error Message") elif self.reply == "NONE": - # print "Empty Project Name" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage('The project name cannot be empty') self.msg.setWindowTitle("Error Message") diff --git a/src/projManagement/openProject.py b/src/projManagement/openProject.py index 23e2c361..504bb473 100644 --- a/src/projManagement/openProject.py +++ b/src/projManagement/openProject.py @@ -1,5 +1,4 @@ # ========================================================================= -# # FILE: openProject.py # # USAGE: --- @@ -11,9 +10,10 @@ # BUGS: --- # NOTES: --- # AUTHOR: Fahim Khan, fahim.elex@gmail.com +# MODIFIED: Rahul Paknikar, rahulp@iitb.ac.in # ORGANIZATION: eSim team at FOSSEE, IIT Bombay. # CREATED: Wednesday 12 February 2015 -# REVISION: --- +# REVISION: Friday 14 February 2020 # ========================================================================= from PyQt4 import QtGui @@ -52,7 +52,7 @@ class OpenProjectInfo(QtGui.QWidget): self.obj_Appconfig.current_project['ProjectName'] = str( self.projDir) if os.path.isdir(self.projDir): - print("true") + print("True") for dirs, subdirs, filelist in os.walk( self.obj_Appconfig.current_project["ProjectName"]): @@ -70,15 +70,17 @@ class OpenProjectInfo(QtGui.QWidget): else: self.obj_Appconfig.print_error( - "The project doesn't contain .proj file. Please select the" - + "proper directory else you won't be able to perform any" - + "operation") + "The project doesn't contain .proj file. Please select the " + + "proper directory else you won't be able to perform any " + + "operation" + ) reply = QtGui.QMessageBox.critical( None, "Error Message", "<b>Error: The project doesn't contain .proj file.</b><br/>" "<b>Please select the proper project directory else you won't" " be able to perform any operation</b>", - QtGui.QMessageBox.Ok | QtGui.QMessageBox.Cancel) + QtGui.QMessageBox.Ok | QtGui.QMessageBox.Cancel + ) if reply == QtGui.QMessageBox.Ok: self.body() @@ -87,5 +89,3 @@ class OpenProjectInfo(QtGui.QWidget): 'Current Project is ' + self.projDir) elif reply == QtGui.QMessageBox.Cancel: self.obj_Appconfig.print_info('No Project opened') - else: - pass diff --git a/src/subcircuit/convertSub.py b/src/subcircuit/convertSub.py index 7bdccfb2..1439f140 100644 --- a/src/subcircuit/convertSub.py +++ b/src/subcircuit/convertSub.py @@ -4,8 +4,7 @@ from configuration.Appconfig import Appconfig import os -# This class is called when User create new Project and contains \ -# functions to convert kicad to Ngspice. +# This class is called when user creates new Project class convertSub(QtGui.QWidget): """ Contains functions that checks project present for conversion and @@ -34,7 +33,6 @@ class convertSub(QtGui.QWidget): if self.obj_validation.validateKicad(self.projDir): # Checking if project has .cir file or not if self.obj_validation.validateCir(self.projDir): - # print "CIR file present" self.projName = os.path.basename(self.projDir) self.project = os.path.join(self.projDir, self.projName) @@ -44,12 +42,14 @@ class convertSub(QtGui.QWidget): else: self.msg = QtGui.QErrorMessage(None) self.msg.showMessage( - 'The subcircuit does not contain any Kicad netlist file' - + ' for conversion.') + 'The subcircuit does not contain any Kicad netlist file' + + ' for conversion.' + ) self.msg.setWindowTitle("Error Message") else: self.msg = QtGui.QErrorMessage(None) self.msg.showMessage( - 'Please select the subcircuit first. You can either create' - + ' new subcircuit or open existing subcircuit') + 'Please select the subcircuit first. You can either create ' + + 'new subcircuit or open existing subcircuit' + ) self.msg.setWindowTitle("Error Message") diff --git a/src/subcircuit/newSub.py b/src/subcircuit/newSub.py index bd88064a..90f60319 100644 --- a/src/subcircuit/newSub.py +++ b/src/subcircuit/newSub.py @@ -5,7 +5,7 @@ from projManagement import Worker import os -# This class is called when User create new Project. +# This class is called when User creates new Project. class NewSub(QtGui.QWidget): """ Contains functions to check : @@ -54,32 +54,30 @@ class NewSub(QtGui.QWidget): self.obj_workThread.start() self.close() except BaseException: - # print "Some Thing Went Wrong" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - 'Unable to create subcircuit. Please make sure\ - you have write permission on ' + - self.schematic_path) + 'Unable to create subcircuit. Please make sure ' + + 'you have write permission on ' + self.schematic_path + ) self.msg.setWindowTitle("Error Message") self.obj_appconfig.current_subcircuit['SubcircuitName'] \ = self.schematic_path elif self.reply == "CHECKEXIST": - # print "Project already exist" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - 'The subcircuit "' + - self.create_schematic + - '" already exist.Please select the different name or delete' - + 'existing subcircuit') + 'The subcircuit "' + self.create_schematic + + '" already exist.Please select the different name or delete' + + 'existing subcircuit' + ) self.msg.setWindowTitle("Error Message") elif self.reply == "CHECKNAME": - # print "Name is not proper" self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - 'The subcircuit name should not contain space between them') + 'The subcircuit name should not contain space between them' + ) self.msg.setWindowTitle("Error Message") elif self.reply == "NONE": diff --git a/src/subcircuit/uploadSub.py b/src/subcircuit/uploadSub.py index 00cc9df0..34ec8c33 100644 --- a/src/subcircuit/uploadSub.py +++ b/src/subcircuit/uploadSub.py @@ -50,10 +50,11 @@ class UploadSub(QtGui.QWidget): if not valid: self.msg = QtGui.QErrorMessage(self) self.msg.showMessage( - "Content of file does not meet the required format.\ - Please ensure that file starts with **.subckt \ - " + create_subcircuit + "** and ends with **.ends \ - " + create_subcircuit + "**") + "Content of file does not meet the required format. " + + "Please ensure that file starts with **.subckt " + + create_subcircuit + " ** and ends with **.ends " + + create_subcircuit + " **" + ) self.msg.setWindowTitle("Error Message") print("Invalid file format") return @@ -80,8 +81,8 @@ class UploadSub(QtGui.QWidget): print("==========================") msg = QtGui.QErrorMessage(self) msg.showMessage( - "The project already exist. Please select \ - the different name or delete existing project") + "The project already exist. Please select " + "a different name or delete existing project") msg.setWindowTitle("Error Message") elif reply == "CHECKNAME": diff --git a/src/supportFiles/fp-lib-table b/src/supportFiles/fp-lib-table new file mode 100644 index 00000000..ff605eaf --- /dev/null +++ b/src/supportFiles/fp-lib-table @@ -0,0 +1,92 @@ +(fp_lib_table + (lib (name Battery_Holders)(type KiCad)(uri ${KISYSMOD}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders")) + (lib (name Buttons_Switches_SMD)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount")) + (lib (name Buttons_Switches_THT)(type KiCad)(uri ${KISYSMOD}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole")) + (lib (name Buzzers_Beepers)(type KiCad)(uri ${KISYSMOD}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices")) + (lib (name Capacitors_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount")) + (lib (name Capacitors_Tantalum_SMD)(type KiCad)(uri ${KISYSMOD}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount")) + (lib (name Capacitors_THT)(type KiCad)(uri ${KISYSMOD}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole")) + (lib (name Connectors_Card)(type KiCad)(uri ${KISYSMOD}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders")) + (lib (name Connectors_Harwin)(type KiCad)(uri ${KISYSMOD}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com")) + (lib (name Connectors_HDMI)(type KiCad)(uri ${KISYSMOD}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints")) + (lib (name Connectors_Hirose)(type KiCad)(uri ${KISYSMOD}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com")) + (lib (name Connectors_IEC_DIN)(type KiCad)(uri ${KISYSMOD}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints")) + (lib (name Connectors_JAE)(type KiCad)(uri ${KISYSMOD}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors")) + (lib (name Connectors_JST)(type KiCad)(uri ${KISYSMOD}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com")) + (lib (name Connectors_Mini-Universal)(type KiCad)(uri ${KISYSMOD}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok)) + (lib (name Connectors_Molex)(type KiCad)(uri ${KISYSMOD}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com")) + (lib (name Connectors_Multicomp)(type KiCad)(uri ${KISYSMOD}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints")) + (lib (name Connectors_Phoenix)(type KiCad)(uri ${KISYSMOD}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints")) + (lib (name Connectors_Samtec)(type KiCad)(uri ${KISYSMOD}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints")) + (lib (name Connectors_TE-Connectivity)(type KiCad)(uri ${KISYSMOD}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com")) + (lib (name Connectors_Terminal_Blocks)(type KiCad)(uri ${KISYSMOD}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors")) + (lib (name Connectors_WAGO)(type KiCad)(uri ${KISYSMOD}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com")) + (lib (name Connectors_USB)(type KiCad)(uri ${KISYSMOD}/Connectors_USB.pretty)(options "")(descr "USB connector footprints")) + (lib (name Connectors)(type KiCad)(uri ${KISYSMOD}/Connectors.pretty)(options "")(descr "Assorted connector footprints")) + (lib (name Converters_DCDC_ACDC)(type KiCad)(uri ${KISYSMOD}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules")) + (lib (name Crystals)(type KiCad)(uri ${KISYSMOD}/Crystals.pretty)(options "")(descr "Crystals and oscillators")) + (lib (name Diodes_SMD)(type KiCad)(uri ${KISYSMOD}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount")) + (lib (name Diodes_THT)(type KiCad)(uri ${KISYSMOD}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole")) + (lib (name Displays_7-Segment)(type KiCad)(uri ${KISYSMOD}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays")) + (lib (name Displays)(type KiCad)(uri ${KISYSMOD}/Displays.pretty)(options "")(descr "Display modules")) + (lib (name Enclosures)(type KiCad)(uri ${KISYSMOD}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings")) + (lib (name EuroBoard_Outline)(type KiCad)(uri ${KISYSMOD}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed")) + (lib (name Fiducials)(type KiCad)(uri ${KISYSMOD}/Fiducials.pretty)(options "")(descr "Fiducial markings")) + (lib (name Fuse_Holders_and_Fuses)(type KiCad)(uri ${KISYSMOD}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders")) + (lib (name Hall-Effect_Transducers_LEM)(type KiCad)(uri ${KISYSMOD}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers")) + (lib (name Heatsinks)(type KiCad)(uri ${KISYSMOD}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products")) + (lib (name Housings_BGA)(type KiCad)(uri ${KISYSMOD}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)")) + (lib (name Housings_CSP)(type KiCad)(uri ${KISYSMOD}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)")) + (lib (name Housings_DFN_QFN)(type KiCad)(uri ${KISYSMOD}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN")) + (lib (name Housings_DIP)(type KiCad)(uri ${KISYSMOD}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP")) + (lib (name Housings_LCC)(type KiCad)(uri ${KISYSMOD}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)")) + (lib (name Housings_LGA)(type KiCad)(uri ${KISYSMOD}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)")) + (lib (name Housings_PGA)(type KiCad)(uri ${KISYSMOD}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)")) + (lib (name Housings_QFP)(type KiCad)(uri ${KISYSMOD}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)")) + (lib (name Housings_SIP)(type KiCad)(uri ${KISYSMOD}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)")) + (lib (name Housings_SOIC)(type KiCad)(uri ${KISYSMOD}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)")) + (lib (name Housings_SON)(type KiCad)(uri ${KISYSMOD}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)")) + (lib (name Housings_SSOP)(type KiCad)(uri ${KISYSMOD}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages")) + (lib (name Inductors_SMD)(type KiCad)(uri ${KISYSMOD}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount")) + (lib (name Inductors_THT)(type KiCad)(uri ${KISYSMOD}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole")) + (lib (name IR-DirectFETs)(type KiCad)(uri ${KISYSMOD}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier")) + (lib (name LEDs)(type KiCad)(uri ${KISYSMOD}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)")) + (lib (name Measurement_Points)(type KiCad)(uri ${KISYSMOD}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment")) + (lib (name Measurement_Scales)(type KiCad)(uri ${KISYSMOD}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges")) + (lib (name Microwave)(type KiCad)(uri ${KISYSMOD}/Microwave.pretty)(options "")(descr Microwave)) + (lib (name Modules)(type KiCad)(uri ${KISYSMOD}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module")) + (lib (name Mounting_Holes)(type KiCad)(uri ${KISYSMOD}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners")) + (lib (name Opto-Devices)(type KiCad)(uri ${KISYSMOD}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices")) + (lib (name Oscillators)(type KiCad)(uri ${KISYSMOD}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules")) + (lib (name PFF_PSF_PSS_Leadforms)(type KiCad)(uri ${KISYSMOD}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages")) + (lib (name Pin_Headers)(type KiCad)(uri ${KISYSMOD}/Pin_Headers.pretty)(options "")(descr "Male pin headers")) + (lib (name Potentiometers)(type KiCad)(uri ${KISYSMOD}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors")) + (lib (name Power_Integrations)(type KiCad)(uri ${KISYSMOD}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints")) + (lib (name Relays_SMD)(type KiCad)(uri ${KISYSMOD}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages")) + (lib (name Relays_THT)(type KiCad)(uri ${KISYSMOD}/Relays_THT.pretty)(options "")(descr "Through hole relay packages")) + (lib (name Resistors_SMD)(type KiCad)(uri ${KISYSMOD}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount")) + (lib (name Resistors_THT)(type KiCad)(uri ${KISYSMOD}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole")) + (lib (name Resistors_Universal)(type KiCad)(uri ${KISYSMOD}/Resistors_Universal.pretty)(options "")(descr Experimental)) + (lib (name RF_Antennas)(type KiCad)(uri ${KISYSMOD}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints")) + (lib (name RF_Modules)(type KiCad)(uri ${KISYSMOD}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules")) + (lib (name Shielding_Cabinets)(type KiCad)(uri ${KISYSMOD}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields")) + (lib (name SMD_Packages)(type KiCad)(uri ${KISYSMOD}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries")) + (lib (name Socket_Strips)(type KiCad)(uri ${KISYSMOD}/Socket_Strips.pretty)(options "")(descr "Female socket strips")) + (lib (name Sockets)(type KiCad)(uri ${KISYSMOD}/Sockets.pretty)(options "")(descr "IC sockets")) + (lib (name Symbols)(type KiCad)(uri ${KISYSMOD}/Symbols.pretty)(options "")(descr "PCB symbols")) + (lib (name TerminalBlocks_Phoenix)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks")) + (lib (name TerminalBlocks_WAGO)(type KiCad)(uri ${KISYSMOD}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks")) + (lib (name TO_SOT_Packages_SMD)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages")) + (lib (name TO_SOT_Packages_THT)(type KiCad)(uri ${KISYSMOD}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages")) + (lib (name Transformers_SMD)(type KiCad)(uri ${KISYSMOD}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers")) + (lib (name Transformers_THT)(type KiCad)(uri ${KISYSMOD}/Transformers_THT.pretty)(options "")(descr "Through hole transformers")) + (lib (name Transistors_OldSowjetAera)(type KiCad)(uri ${KISYSMOD}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors")) + (lib (name Valves)(type KiCad)(uri ${KISYSMOD}/Valves.pretty)(options "")(descr Valves)) + (lib (name Varistors)(type KiCad)(uri ${KISYSMOD}/Varistors.pretty)(options "")(descr Varistors)) + (lib (name Wire_Connections_Bridges)(type KiCad)(uri ${KISYSMOD}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points")) + (lib (name Wire_Pads)(type KiCad)(uri ${KISYSMOD}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points")) + (lib (name Choke_Common-Mode_Wurth)(type KiCad)(uri "$(KISYSMOD)Choke_Common-Mode_Wurth.pretty")(options "")(descr "")) + (lib (name Choke_Radial_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Radial_ThroughHole.pretty")(options "")(descr "")) + (lib (name Choke_SMD)(type KiCad)(uri "$(KISYSMOD)Choke_SMD.pretty")(options "")(descr "")) + (lib (name Choke_Toroid_ThroughHole)(type KiCad)(uri "$(KISYSMOD)Choke_Toroid_ThroughHole.pretty")(options "")(descr "")) +) diff --git a/src/supportFiles/fp-lib-table-online b/src/supportFiles/fp-lib-table-online new file mode 100644 index 00000000..5b4081ff --- /dev/null +++ b/src/supportFiles/fp-lib-table-online @@ -0,0 +1,88 @@ +(fp_lib_table + (lib (name Battery_Holders)(type Github)(uri ${KIGITHUB}/Battery_Holders.pretty)(options "")(descr "Batteries and battery holders")) + (lib (name Buttons_Switches_SMD)(type Github)(uri ${KIGITHUB}/Buttons_Switches_SMD.pretty)(options "")(descr "Buttons and switches, surface mount")) + (lib (name Buttons_Switches_THT)(type Github)(uri ${KIGITHUB}/Buttons_Switches_THT.pretty)(options "")(descr "Buttons and switches, through hole")) + (lib (name Buzzers_Beepers)(type Github)(uri ${KIGITHUB}/Buzzers_Beepers.pretty)(options "")(descr "Audio signalling devices")) + (lib (name Capacitors_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_SMD.pretty)(options "")(descr "Capacitors, surface mount")) + (lib (name Capacitors_Tantalum_SMD)(type Github)(uri ${KIGITHUB}/Capacitors_Tantalum_SMD.pretty)(options "")(descr "Tantalum capacitors, surface mount")) + (lib (name Capacitors_THT)(type Github)(uri ${KIGITHUB}/Capacitors_THT.pretty)(options "")(descr "Capacitors, through hole")) + (lib (name Connectors_Card)(type Github)(uri ${KIGITHUB}/Connectors_Card.pretty)(options "")(descr "Footprints for cards and card holders")) + (lib (name Connectors_Harwin)(type Github)(uri ${KIGITHUB}/Connectors_Harwin.pretty)(options "")(descr "Harwin connector footprints www.harwin.com")) + (lib (name Connectors_HDMI)(type Github)(uri ${KIGITHUB}/Connectors_HDMI.pretty)(options "")(descr "HDMI connector footprints")) + (lib (name Connectors_Hirose)(type Github)(uri ${KIGITHUB}/Connectors_Hirose.pretty)(options "")(descr "Hirose connector footprints www.hirose.com")) + (lib (name Connectors_IEC_DIN)(type Github)(uri ${KIGITHUB}/Connectors_IEC_DIN.pretty)(options "")(descr "DIN connector footprints")) + (lib (name Connectors_JAE)(type Github)(uri ${KIGITHUB}/Connectors_JAE.pretty)(options "")(descr "JAE connector footprints http://www.jae.com/jccom/en/connectors")) + (lib (name Connectors_JST)(type Github)(uri ${KIGITHUB}/Connectors_JST.pretty)(options "")(descr "JST connector footprints www.jst.com")) + (lib (name Connectors_Mini-Universal)(type Github)(uri ${KIGITHUB}/Connectors_Mini-Universal.pretty)(options "")(descr Mate-N-Lok)) + (lib (name Connectors_Molex)(type Github)(uri ${KIGITHUB}/Connectors_Molex.pretty)(options "")(descr "Molex connector foottprints www.molex.com")) + (lib (name Connectors_Multicomp)(type Github)(uri ${KIGITHUB}/Connectors_Multicomp.pretty)(options "")(descr "Multicomp connector footprints")) + (lib (name Connectors_Phoenix)(type Github)(uri ${KIGITHUB}/Connectors_Phoenix.pretty)(options "")(descr "Phoenix connector footprints")) + (lib (name Connectors_Samtec)(type Github)(uri ${KIGITHUB}/Connectors_Samtec.pretty)(options "")(descr "Samtec connector footprints")) + (lib (name Connectors_TE-Connectivity)(type Github)(uri ${KIGITHUB}/Connectors_TE-Connectivity.pretty)(options "")(descr "TE Connectivity connector footprints www.te.com")) + (lib (name Connectors_Terminal_Blocks)(type Github)(uri ${KIGITHUB}/Connectors_Terminal_Blocks.pretty)(options "")(descr "Terminal block connectors")) + (lib (name Connectors_WAGO)(type Github)(uri ${KIGITHUB}/Connectors_WAGO.pretty)(options "")(descr "WAGO connector footprints www.wago.com")) + (lib (name Connectors_USB)(type Github)(uri ${KIGITHUB}/Connectors_USB.pretty)(options "")(descr "USB connector footprints")) + (lib (name Connectors)(type Github)(uri ${KIGITHUB}/Connectors.pretty)(options "")(descr "Assorted connector footprints")) + (lib (name Converters_DCDC_ACDC)(type Github)(uri ${KIGITHUB}/Converters_DCDC_ACDC.pretty)(options "")(descr "DC-DC and AC-DC convertor modules")) + (lib (name Crystals)(type Github)(uri ${KIGITHUB}/Crystals.pretty)(options "")(descr "Crystals and oscillators")) + (lib (name Diodes_SMD)(type Github)(uri ${KIGITHUB}/Diodes_SMD.pretty)(options "")(descr "Diodes, surface mount")) + (lib (name Diodes_THT)(type Github)(uri ${KIGITHUB}/Diodes_THT.pretty)(options "")(descr "Diodes, through hole")) + (lib (name Displays_7-Segment)(type Github)(uri ${KIGITHUB}/Displays_7-Segment.pretty)(options "")(descr "Seven segment displays")) + (lib (name Displays)(type Github)(uri ${KIGITHUB}/Displays.pretty)(options "")(descr "Display modules")) + (lib (name Enclosures)(type Github)(uri ${KIGITHUB}/Enclosures.pretty)(options "")(descr "Electronics enclosures and housings")) + (lib (name EuroBoard_Outline)(type Github)(uri ${KIGITHUB}/EuroBoard_Outline.pretty)(options "")(descr "Deprecated - will be removed")) + (lib (name Fiducials)(type Github)(uri ${KIGITHUB}/Fiducials.pretty)(options "")(descr "Fiducial markings")) + (lib (name Fuse_Holders_and_Fuses)(type Github)(uri ${KIGITHUB}/Fuse_Holders_and_Fuses.pretty)(options "")(descr "Fuses and fuse holders")) + (lib (name Hall-Effect_Transducers_LEM)(type Github)(uri ${KIGITHUB}/Hall-Effect_Transducers_LEM.pretty)(options "")(descr "LEM hall effect transducers")) + (lib (name Heatsinks)(type Github)(uri ${KIGITHUB}/Heatsinks.pretty)(options "")(descr "Heatsinks and thermal products")) + (lib (name Housings_BGA)(type Github)(uri ${KIGITHUB}/Housings_BGA.pretty)(options "")(descr "Ball Grid Array (BGA)")) + (lib (name Housings_CSP)(type Github)(uri ${KIGITHUB}/Housings_CSP.pretty)(options "")(descr "Chip Scale Packages (CSP)")) + (lib (name Housings_DFN_QFN)(type Github)(uri ${KIGITHUB}/Housings_DFN_QFN.pretty)(options "")(descr "Surface mount IC packages, DFN / LGA / QFN")) + (lib (name Housings_DIP)(type Github)(uri ${KIGITHUB}/Housings_DIP.pretty)(options "")(descr "Through hole IC packages, DIP")) + (lib (name Housings_LCC)(type Github)(uri ${KIGITHUB}/Housings_LCC.pretty)(options "")(descr "Leaded Chip Carriers (LCC)")) + (lib (name Housings_LGA)(type Github)(uri ${KIGITHUB}/Housings_LGA.pretty)(options "")(descr "Land Grid Array (LGA)")) + (lib (name Housings_PGA)(type Github)(uri ${KIGITHUB}/Housings_PGA.pretty)(options "")(descr "Pin Grid Array (PGA)")) + (lib (name Housings_QFP)(type Github)(uri ${KIGITHUB}/Housings_QFP.pretty)(options "")(descr "Quad Flat Package (QFP)")) + (lib (name Housings_SIP)(type Github)(uri ${KIGITHUB}/Housings_SIP.pretty)(options "")(descr "Single Inline Package (SIP)")) + (lib (name Housings_SOIC)(type Github)(uri ${KIGITHUB}/Housings_SOIC.pretty)(options "")(descr "Small Outline Integrated Circuits (SOIC)")) + (lib (name Housings_SON)(type Github)(uri ${KIGITHUB}/Housings_SON.pretty)(options "")(descr "Small Outline No-Lead (SON)")) + (lib (name Housings_SSOP)(type Github)(uri ${KIGITHUB}/Housings_SSOP.pretty)(options "")(descr "SSOP, TSSOP, MSOP, QSOP, VSO packages")) + (lib (name Inductors_SMD)(type Github)(uri ${KIGITHUB}/Inductors_SMD.pretty)(options "")(descr "Inductors, surface mount")) + (lib (name Inductors_THT)(type Github)(uri ${KIGITHUB}/Inductors_THT.pretty)(options "")(descr "Inductors, through hole")) + (lib (name IR-DirectFETs)(type Github)(uri ${KIGITHUB}/IR-DirectFETs.pretty)(options "")(descr "DirectFet packets from International Rectifier")) + (lib (name LEDs)(type Github)(uri ${KIGITHUB}/LEDs.pretty)(options "")(descr "Light emitting diodes (LEDs)")) + (lib (name Measurement_Points)(type Github)(uri ${KIGITHUB}/Measurement_Points.pretty)(options "")(descr "Terminals for test equipment")) + (lib (name Measurement_Scales)(type Github)(uri ${KIGITHUB}/Measurement_Scales.pretty)(options "")(descr "Measurement scales and gauges")) + (lib (name Microwave)(type Github)(uri ${KIGITHUB}/Microwave.pretty)(options "")(descr "Microwave")) + (lib (name Modules)(type Github)(uri ${KIGITHUB}/Modules.pretty)(options "")(descr "Board-level devices integrating system functionality into a single module")) + (lib (name Mounting_Holes)(type Github)(uri ${KIGITHUB}/Mounting_Holes.pretty)(options "")(descr "Mechanical fasteners")) + (lib (name Opto-Devices)(type Github)(uri ${KIGITHUB}/Opto-Devices.pretty)(options "")(descr "Optocouplers, light sensors, and other optical devices")) + (lib (name Oscillators)(type Github)(uri ${KIGITHUB}/Oscillators.pretty)(options "")(descr "Precicision oscillator modules")) + (lib (name PFF_PSF_PSS_Leadforms)(type Github)(uri ${KIGITHUB}/PFF_PSF_PSS_Leadforms.pretty)(options "")(descr "Allegro leadform packages")) + (lib (name Pin_Headers)(type Github)(uri ${KIGITHUB}/Pin_Headers.pretty)(options "")(descr "Male pin headers")) + (lib (name Potentiometers)(type Github)(uri ${KIGITHUB}/Potentiometers.pretty)(options "")(descr "Potentiometers / variable resistors")) + (lib (name Power_Integrations)(type Github)(uri ${KIGITHUB}/Power_Integrations.pretty)(options "")(descr "Power Integrations footprints")) + (lib (name Relays_SMD)(type Github)(uri ${KIGITHUB}/Relays_SMD.pretty)(options "")(descr "Surface mount relay packages")) + (lib (name Relays_THT)(type Github)(uri ${KIGITHUB}/Relays_THT.pretty)(options "")(descr "Through hole relay packages")) + (lib (name Resistors_SMD)(type Github)(uri ${KIGITHUB}/Resistors_SMD.pretty)(options "")(descr "Resistors, surface mount")) + (lib (name Resistors_THT)(type Github)(uri ${KIGITHUB}/Resistors_THT.pretty)(options "")(descr "Resistors, through hole")) + (lib (name Resistors_Universal)(type Github)(uri ${KIGITHUB}/Resistors_Universal.pretty)(options "")(descr Experimental)) + (lib (name RF_Antennas)(type Github)(uri ${KIGITHUB}/RF_Antennas.pretty)(options "")(descr "Radio-frequency / wireless antenna footprints")) + (lib (name RF_Modules)(type Github)(uri ${KIGITHUB}/RF_Modules.pretty)(options "")(descr "Radio-frequency / wireless modules")) + (lib (name Shielding_Cabinets)(type Github)(uri ${KIGITHUB}/Shielding_Cabinets.pretty)(options "")(descr "RF / EMI shields")) + (lib (name SMD_Packages)(type Github)(uri ${KIGITHUB}/SMD_Packages.pretty)(options "")(descr "Various SMD packages. Read only - footprints will be moved to other libraries")) + (lib (name Socket_Strips)(type Github)(uri ${KIGITHUB}/Socket_Strips.pretty)(options "")(descr "Female socket strips")) + (lib (name Sockets)(type Github)(uri ${KIGITHUB}/Sockets.pretty)(options "")(descr "IC sockets")) + (lib (name Symbols)(type Github)(uri ${KIGITHUB}/Symbols.pretty)(options "")(descr "PCB symbols")) + (lib (name TerminalBlocks_Phoenix)(type Github)(uri ${KIGITHUB}/TerminalBlocks_Phoenix.pretty)(options "")(descr "Phoenix Contact terminal blocks")) + (lib (name TerminalBlocks_WAGO)(type Github)(uri ${KIGITHUB}/TerminalBlocks_WAGO.pretty)(options "")(descr "WAGO terminal blocks")) + (lib (name TO_SOT_Packages_SMD)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_SMD.pretty)(options "")(descr "Surface mount transistor packages")) + (lib (name TO_SOT_Packages_THT)(type Github)(uri ${KIGITHUB}/TO_SOT_Packages_THT.pretty)(options "")(descr "Through hole transistor packages")) + (lib (name Transformers_SMD)(type Github)(uri ${KIGITHUB}/Transformers_SMD.pretty)(options "")(descr "Surface mount transformers")) + (lib (name Transformers_THT)(type Github)(uri ${KIGITHUB}/Transformers_THT.pretty)(options "")(descr "Through hole transformers")) + (lib (name Transistors_OldSowjetAera)(type Github)(uri ${KIGITHUB}/Transistors_OldSowjetAera.pretty)(options "")(descr "Sowjet transistors")) + (lib (name Valves)(type Github)(uri ${KIGITHUB}/Valves.pretty)(options "")(descr "Valves")) + (lib (name Varistors)(type Github)(uri ${KIGITHUB}/Varistors.pretty)(options "")(descr "Varistors")) + (lib (name Wire_Connections_Bridges)(type Github)(uri ${KIGITHUB}/Wire_Connections_Bridges.pretty)(options "")(descr "PCB bridging points")) + (lib (name Wire_Pads)(type Github)(uri ${KIGITHUB}/Wire_Pads.pretty)(options "")(descr "Direct wire-to-board connection points")) +) |