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| author | fahim-oscad | 2016-05-06 12:53:50 +0530 |
|---|---|---|
| committer | fahim-oscad | 2016-05-06 12:53:50 +0530 |
| commit | c5a108d361ea264cbe33b8486e8ad0b6b32d252b (patch) | |
| tree | c3509316d2bc7015046d73c5b88de4aeb9daa353 /src/ngspicetoModelica/Mapping.json | |
| parent | e53b087fbe87c1857b3b04b0dbd4030e774f404d (diff) | |
| download | eSim-c5a108d361ea264cbe33b8486e8ad0b6b32d252b.tar.gz eSim-c5a108d361ea264cbe33b8486e8ad0b6b32d252b.tar.bz2 eSim-c5a108d361ea264cbe33b8486e8ad0b6b32d252b.zip | |
Added JFET model
Diffstat (limited to 'src/ngspicetoModelica/Mapping.json')
| -rw-r--r-- | src/ngspicetoModelica/Mapping.json | 41 |
1 files changed, 37 insertions, 4 deletions
diff --git a/src/ngspicetoModelica/Mapping.json b/src/ngspicetoModelica/Mapping.json index 5d5d84d1..2600d65a 100644 --- a/src/ngspicetoModelica/Mapping.json +++ b/src/ngspicetoModelica/Mapping.json @@ -120,10 +120,43 @@ } }, - "a" : "Analog.Semiconductors.Diode", - "b" : "Analog.Semiconductors.Diode", - "M" :"BondLib.Electrical.Analog.Spice" - + + "j":{ + "import":"Analog.Semiconductors", + "mapping":{ + "bf":"Bf", + "br":"Br", + "is":"Is", + "vak":"Vak", + "tf":"Tauf", + "tr":"Taur", + "cjs":"Ccs", + "cje":"Cje", + "cjc":"Cjc", + "vje":"Phie", + "mje":"Me", + "vjc":"Phic", + "mjc":"Mc" + }, + "default":{ + "Bf":"50", + "Br":"0.1", + "Is":"1e-16", + "Tauf":"1.2e-10", + "Taur":"5e-9", + "Vak":"0.02", + "Ccs":"1e-12", + "Cje":"4e-12", + "Cjc":"5e-13", + "Phie":"0.8", + "Me":"0.4", + "Phic":"0.8", + "Mc":"0.333" + + } + + } + }, |