diff options
author | rahulp13 | 2022-02-22 02:31:30 +0530 |
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committer | rahulp13 | 2022-02-22 02:31:30 +0530 |
commit | 87bc2c82192c948ddb88c52dfcd5213920920c2f (patch) | |
tree | e19ba25793ab0de04e9b337d653589c74aac2da1 /src/maker | |
parent | 272bf20219595c3c541797b1045ce9c400ab02d6 (diff) | |
download | eSim-87bc2c82192c948ddb88c52dfcd5213920920c2f.tar.gz eSim-87bc2c82192c948ddb88c52dfcd5213920920c2f.tar.bz2 eSim-87bc2c82192c948ddb88c52dfcd5213920920c2f.zip |
Fixed typos and resolved flake8 issues
Diffstat (limited to 'src/maker')
-rwxr-xr-x | src/maker/Maker.py | 44 | ||||
-rwxr-xr-x | src/maker/ModelGeneration.py | 55 | ||||
-rwxr-xr-x | src/maker/NgVeri.py | 81 | ||||
-rw-r--r--[-rwxr-xr-x] | src/maker/createkicad.py | 15 | ||||
-rwxr-xr-x | src/maker/makerchip.py | 10 |
5 files changed, 95 insertions, 110 deletions
diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 9f4263c2..c7a66204 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -27,17 +27,11 @@ # ========================================================================= # importing the files and libraries -from xml.etree import ElementTree as ET # noqa:F401 import hdlparse.verilog_parser as vlog -import time # noqa:F401 from PyQt5 import QtCore, QtWidgets -from PyQt5.QtCore import QThread, Qt # noqa:F401 -from PyQt5.QtWidgets \ - import QApplication, \ - QWidget, QLabel, QVBoxLayout # noqa:F401 +from PyQt5.QtCore import QThread from configuration.Appconfig import Appconfig import os -import subprocess # noqa:F401 import watchdog.events import watchdog.observers from os.path import expanduser @@ -101,7 +95,7 @@ class Maker(QtWidgets.QWidget): # self.grid.addWidget(self.creategroup(), 1, 0, 5, 0) self.show() - # This function is to Add new verilog file + # This function is to Add new verilog file def addverilog(self): init_path = '../../' @@ -109,7 +103,7 @@ class Maker(QtWidgets.QWidget): init_path = '' self.verilogfile = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getOpenFileName( - self, "Open verilog Directory", + self, "Open Verilog Directory", init_path + "home", "*v" )[0] ) @@ -120,9 +114,10 @@ class Maker(QtWidgets.QWidget): reply = QtWidgets.QMessageBox.critical( None, "Error Message", - "<b>Error: No Verilog File Chosen.\ - Please chose a Verilog file</b>", + "<b>No Verilog File Chosen. \ + Please choose a verilog file.</b>", QtWidgets.QMessageBox.Ok | QtWidgets.QMessageBox.Cancel) + if reply == QtWidgets.QMessageBox.Ok: self.addverilog() @@ -211,12 +206,12 @@ class Maker(QtWidgets.QWidget): def runmakerchip(self): init_path = '../../' if os.name == 'nt': - init_path = '' # noqa:F841 + init_path = '' try: if not makerchipTOSAccepted(True): return - print("Running Makerchip..............................") + print("Running Makerchip IDE...........................") # self.file = open(self.verilogfile,"w") # self.file.write(self.entry_var[1].toPlainText()) # self.file.close() @@ -246,13 +241,13 @@ class Maker(QtWidgets.QWidget): file = os.path.basename('.'.join( self.verilogfile.split('.')[:-1])) f = open(filename, 'w') - flag = 1 # noqa F841 - ports = "" # noqa F841 code = code.replace(" wire ", " ") code = code.replace(" reg ", " ") vlog_ex = vlog.VerilogExtractor() vlog_mods = vlog_ex.extract_objects_from_source(code) - lint_off = open(init_path + "library/tlv/lint_off.txt").readlines() + lint_off = open( + init_path + "library/tlv/lint_off.txt" + ).readlines() string = '''\\TLV_version 1d: tl-x.org\n\\SV\n''' for item in lint_off: string += "/* verilator lint_off " + \ @@ -281,11 +276,11 @@ output logic passed, output logic failed);\n''' "Error Message", "<b>Error: File name and module \ name are not same. Please \ - ensure that they are same</b>", + ensure that they are same.</b>", QtWidgets.QMessageBox.Ok) self.obj_Appconfig.print_info( - 'NgVeri Stopped due to File \ + 'NgVeri stopped due to file \ name and module name not matching error') return string += "//The $random() can be replaced \ @@ -325,7 +320,7 @@ Add \\TLV here if desired\ print("File: " + filename) self.process.start(cmd) print( - "Makerchip command process pid ---------- >", + "Makerchip IDE command process pid ---------->", self.process.pid()) except BaseException as e: print(e) @@ -333,11 +328,11 @@ Add \\TLV here if desired\ self.msg.setModal(True) self.msg.setWindowTitle("Error Message") self.msg.showMessage( - "Error in running Makerchip. \ -Please check if Verilog File Chosen.") + "Error in running Makerchip IDE. \ +Please check if verilog file is chosen.") self.msg.exec_() - print("Error in running Makerchip. \ -Please check if Verilog File Chosen.") + print("Error in running Makerchip IDE. \ +Please check if verilog file is chosen.") # initial = self.read_file() # while True: @@ -402,7 +397,6 @@ Please check if Verilog File Chosen.") # This function adds the other parts of widget like text box def creategroup(self): - self.trbox = QtWidgets.QGroupBox() self.trbox.setTitle(".tlv file") # self.trbox.setDisabled(True) @@ -413,7 +407,7 @@ Please check if Verilog File Chosen.") self.start = QtWidgets.QLabel("Path to .tlv file") self.trgrid.addWidget(self.start, 1, 0) self.count = 0 - self.entry_var[self.count] = QtWidgets.QLabel(" - ") + self.entry_var[self.count] = QtWidgets.QLabel() self.trgrid.addWidget(self.entry_var[self.count], 1, 1) self.entry_var[self.count].setMaximumWidth(1000) self.count += 1 diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index cbb268af..49d5da0b 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -30,19 +30,14 @@ # importing the files and libraries import re import os -import sys # noqa:F401 -import shutil # noqa:F401 -import subprocess # noqa:F401 -from PyQt5 import QtGui, QtCore, QtWidgets # noqa:F401 -from PyQt5.QtGui import * # noqa:F401 F403 +from PyQt5 import QtCore, QtWidgets from configparser import ConfigParser from configuration import Appconfig from . import createkicad import hdlparse.verilog_parser as vlog -# Class is used to generate the Ngspice Model - +# Class is used to generate the Ngspice Model class ModelGeneration(QtWidgets.QWidget): # initialising the variables @@ -75,11 +70,12 @@ class ModelGeneration(QtWidgets.QWidget): self.release_dir = self.parser.get('NGHDL', 'RELEASE') self.src_home = self.parser.get('SRC', 'SRC_HOME') self.licensefile = self.parser.get('SRC', 'LICENSE') - self.digital_home = self.parser.get('NGHDL', 'DIGITAL_MODEL') + "/Ngveri" + self.digital_home = self.parser.get( + 'NGHDL', 'DIGITAL_MODEL') + "/Ngveri" # # #### Creating connection_info.txt file from verilog file #### # - # Readinf the file and performing operations and copying it in the Ngspice - # folder + # Reading the file and performing operations and + # copying it in the Ngspice folder def verilogfile(self): Text = "<span style=\" font-size:25pt;\ font-weight:1000; color:#008000;\" >" @@ -111,17 +107,21 @@ class ModelGeneration(QtWidgets.QWidget): f.write("\n") f.close() - # This function is call the sandpiper to convert .tlv file to .sv file + # This function calls the sandpiper to convert .tlv file to .sv file def sandpiper(self): init_path = '../../' if os.name == 'nt': init_path = '' # Text="Running Sandpiper............" print("Running Sandpiper-Saas for TLV to SV Conversion") - self.cmd = "cp " + init_path + "library/tlv/clk_gate.v " + init_path + "library/tlv/pseudo_rand.sv "\ - + init_path + "library/tlv/sandpiper.vh " + init_path + "library/tlv/sandpiper_gen.vh "\ - + init_path + "library/tlv/sp_default.vh " + init_path + "library/tlv/pseudo_rand_gen.sv "\ - + init_path + "library/tlv/pseudo_rand.m4out.tlv " + self.file + " " + self.modelpath + self.cmd = "cp " + init_path + "library/tlv/clk_gate.v " + \ + init_path + "library/tlv/pseudo_rand.sv " + \ + init_path + "library/tlv/sandpiper.vh " + \ + init_path + "library/tlv/sandpiper_gen.vh " + \ + init_path + "library/tlv/sp_default.vh " + \ + init_path + "library/tlv/pseudo_rand_gen.sv " + \ + init_path + "library/tlv/pseudo_rand.m4out.tlv " + \ + self.file + " " + self.modelpath self.process = QtCore.QProcess(self) self.args = ['-c', self.cmd] @@ -207,7 +207,7 @@ class ModelGeneration(QtWidgets.QWidget): QtWidgets.QMessageBox.Ok) self.obj_Appconfig.print_info( - 'NgVeri Stopped due to File \ + 'NgVeri stopped due to file \ name and module name not matching error') return "Error" modelname = str(m.name) @@ -897,7 +897,9 @@ and set the load for input ports */ self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o"): - os.remove(self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o") + os.remove( + self.release_home + "src/xspice/icm/Ngveri/" + "verilated.o" + ) if os.path.exists( path_icm + "V" + @@ -948,7 +950,6 @@ and set the load for input ports */ self.cmd = "make" print("Running Make command in " + path_icm) - path = os.getcwd() # noqa self.process = QtCore.QProcess(self) self.process.start('sh', ['-c', self.cmd]) print("make command process pid ---------- >", self.process.pid()) @@ -977,11 +978,11 @@ and set the load for input ports */ try: if os.name == 'nt': self.msys_home = self.parser.get('COMPILER', 'MSYS_HOME') - self.cmd = self.msys_home + "/mingw64/bin/mingw32-make.exe install" + self.cmd = self.msys_home + \ + "/mingw64/bin/mingw32-make.exe install" else: self.cmd = "make install" print("Running Make Install") - path = os.getcwd() # noqa try: self.process.close() except BaseException: @@ -1056,17 +1057,14 @@ and set the load for input ports */ print("Added the File:" + filename) self.termtitle("Added the File:" + filename) - - # This function is used to add additional folder required by the verilog - # top module def addfolder(self): + ''' + This function is used to add additional folder required + by the verilog top module + ''' # self.cur_dir = os.getcwd() print("Adding the folder required by the top level module file") - init_path = '../../' - if os.name == 'nt': - init_path = '' # noqa:F841 - includefolder = QtCore.QDir.toNativeSeparators( QtWidgets.QFileDialog.getExistingDirectory( self, "open", "home" @@ -1089,7 +1087,7 @@ and set the load for input ports */ self.obj_Appconfig.print_info('Add Folder Called') elif reply == QtWidgets.QMessageBox.Cancel: - self.obj_Appconfig.print_info('No File Chosen') + self.obj_Appconfig.print_info('No Folder Chosen') return self.modelpath = self.digital_home + \ @@ -1123,7 +1121,6 @@ and set the load for input ports */ # os.chdir(self.cur_dir) # This function is used to print the titles in the terminal of Ngveri tab - def termtitle(self, textin): Text = "<span style=\" font-size:20pt; \ diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py index c1fbcb4e..cb553a31 100755 --- a/src/maker/NgVeri.py +++ b/src/maker/NgVeri.py @@ -28,12 +28,11 @@ # importing the files and libraries -from PyQt5 import QtCore, QtWidgets, QtGui +from PyQt5 import QtCore, QtWidgets from . import Maker from . import ModelGeneration import os import shutil -import subprocess from configuration.Appconfig import Appconfig from configparser import ConfigParser @@ -83,9 +82,6 @@ class NgVeri(QtWidgets.QWidget): # Adding the verilog file in Maker tab to Ngveri Tab automatically def addverilog(self): - init_path = '../../' - if os.name == 'nt': - init_path = '' # b=Maker.Maker(self) print(Maker.verilogFile) if Maker.verilogFile[self.filecount] == "": @@ -93,11 +89,13 @@ class NgVeri(QtWidgets.QWidget): None, "Error Message", "<b>Error: No Verilog File Chosen. \ - Please chose a Verilog file in Makerchip Tab</b>", + Please choose a verilog file in Makerchip Tab</b>", QtWidgets.QMessageBox.Ok) if reply == QtWidgets.QMessageBox.Ok: self.obj_Appconfig.print_error( - 'No VerilogFile. Please add a File in Makerchip Tab') + 'No Verilog File Chosen. ' + 'Please choose a verilog file in Makerchip Tab' + ) return self.fname = Maker.verilogFile[self.filecount] @@ -136,7 +134,8 @@ class NgVeri(QtWidgets.QWidget): else: try: shutil.copy( - self.release_dir + "/src/xspice/icm/Ngveri/Ngveri.cm", + self.release_dir + + "/src/xspice/icm/Ngveri/Ngveri.cm", self.nghdl_home + "/lib/ngspice/" ) except FileNotFoundError as err: @@ -147,8 +146,8 @@ class NgVeri(QtWidgets.QWidget): terminalLog = self.entry_var[0].toPlainText() if "error" not in terminalLog.lower(): self.entry_var[0].append(''' - <p style=\" font-size:16pt; font-weight:1000; color:#00FF00;\" > - Model Created Successfully! + <p style=\" font-size:16pt; font-weight:1000; + color:#00FF00;\"> Model Created Successfully! </p> ''') @@ -156,35 +155,37 @@ class NgVeri(QtWidgets.QWidget): except BaseException as err: self.entry_var[0].append( - "Error in Ngspice code model generation from Verilog: " + str(err) + "Error in Ngspice code model generation " + + "from Verilog: " + str(err) ) terminalLog = self.entry_var[0].toPlainText() if "error" in terminalLog.lower(): self.entry_var[0].append(''' - <p style=\" font-size:16pt; font-weight:1000; color:#FF0000;\" > - There was an error during model creation, - <br/> - Please rectify the error and try again ! + <p style=\" font-size:16pt; font-weight:1000; + color:#FF0000;\">There was an error during model creation, + <br/>Please rectify the error and try again! </p> - ''') - - # This function is used to add additional files required by the verilog - # top module + ''') def addfile(self): + ''' + This function is used to add additional files required + by the verilog top module + ''' if len(Maker.verilogFile) < (self.filecount + 1): reply = QtWidgets.QMessageBox.critical( None, "Error Message", "<b>Error: No Verilog File Chosen. \ - Please chose a Verilog file in Makerchip Tab</b>", + Please choose a verilog file in Makerchip Tab</b>", QtWidgets.QMessageBox.Ok) if reply == QtWidgets.QMessageBox.Ok: self.obj_Appconfig.print_error( - 'No VerilogFile. Please chose\ - a Verilog File in Makerchip Tab') + 'No Verilog File Chosen. Please choose \ + a verilog file in Makerchip Tab') return + self.fname = Maker.verilogFile[self.filecount] model = ModelGeneration.ModelGeneration(self.fname, self.entry_var[0]) # model.verilogfile() @@ -198,12 +199,12 @@ class NgVeri(QtWidgets.QWidget): None, "Error Message", "<b>Error: No Verilog File Chosen. \ - Please chose a Verilog file in Makerchip Tab</b>", + Please choose a verilog file in Makerchip Tab</b>", QtWidgets.QMessageBox.Ok) if reply == QtWidgets.QMessageBox.Ok: self.obj_Appconfig.print_error( - 'No VerilogFile. Please chose \ - a Verilog File in Makerchip Tab') + 'No Verilog File Chosen. Please choose \ + a verilog file in Makerchip Tab') return self.fname = Maker.verilogFile[self.filecount] model = ModelGeneration.ModelGeneration(self.fname, self.entry_var[0]) @@ -260,7 +261,7 @@ class NgVeri(QtWidgets.QWidget): return self.optionsbox # This function is used to remove models in modlst of Ngspice folder if - # the user wants to remove a model.Note: files do not get removed + # the user wants to remove a model. Note: files do not get removed def edit_modlst(self, text): if text == "Edit modlst": return @@ -268,7 +269,7 @@ class NgVeri(QtWidgets.QWidget): self.entry_var[1].removeItem(index) self.entry_var[1].setCurrentIndex(0) ret = QtWidgets.QMessageBox.warning( - None, "Warning", '''<b>Do you want to remove model:''' + + None, "Warning", '''<b>Do you want to remove the model: ''' + text, QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel ) @@ -297,15 +298,17 @@ class NgVeri(QtWidgets.QWidget): ) except BaseException as err: QtWidgets.QMessageBox.critical( - None, "Error Message", - "The verilog model '" + str(text) + - "' could not be removed: " + str(err), - QtWidgets.QMessageBox.Ok) - + None, "Error Message", + "The verilog model '" + str(text) + + "' could not be removed: " + str(err), + QtWidgets.QMessageBox.Ok + ) - # This is to remove lint_off comments needed by the verilator warnings - # This function writes to the lint_off.txt here in the same folder def lint_off_edit(self, text): + ''' + This is to remove lint_off comments needed by the verilator warnings. + This function writes to the lint_off.txt in the library/tlv folder. + ''' init_path = '../../' if os.name == 'nt': init_path = '' @@ -332,14 +335,12 @@ class NgVeri(QtWidgets.QWidget): file = open(init_path + "library/tlv/lint_off.txt", 'w') for item in data: file.write(item) - return - - # else: - # return - # This is to add lint_off comments needed by the verilator warnings - # This function writes to the lint_off.txt here in the same folder def add_lint_off(self): + ''' + This is to add lint_off comments needed by the verilator warnings. + This function writes to the lint_off.txt in the library/tlv folder. + ''' init_path = '../../' if os.name == 'nt': init_path = '' diff --git a/src/maker/createkicad.py b/src/maker/createkicad.py index c8b14b6e..af30cee0 100755..100644 --- a/src/maker/createkicad.py +++ b/src/maker/createkicad.py @@ -30,7 +30,6 @@ from . import Appconfig import re import os -import sys # noqa F401 import xml.etree.cElementTree as ET from PyQt5 import QtWidgets @@ -68,40 +67,43 @@ class AutoSchematic: if (str(self.modelname) + '.xml') in files: xmlFound = root print(xmlFound) + break + if xmlFound is None: self.getPortInformation() self.createXML() self.createLib() + elif (xmlFound == os.path.join(self.xml_loc, 'Ngveri')): print('Library already exists...') ret = QtWidgets.QMessageBox.warning( None, "Warning", '''<b>Library files for this model''' + ''' already exist. Do you want to overwrite it?</b><br/> If yes press ok, else cancel it and ''' + - '''change the name of your vhdl file.''', + '''change the name of your verilog model.''', QtWidgets.QMessageBox.Ok, QtWidgets.QMessageBox.Cancel ) + if ret == QtWidgets.QMessageBox.Ok: print("Overwriting existing libraries") self.getPortInformation() self.createXML() - self.removeOldLibrary() # Removes the exisitng library + self.removeOldLibrary() # Removes the existng library self.createLib() else: print("Library Creation Cancelled") return "Error" else: - print('Pre existing library...') + print('Pre-existing library...') ret = QtWidgets.QMessageBox.critical( self.parent, "Error", '''<b>A standard library already ''' + '''exists with this name.</b><br/><b>Please change the ''' + - '''name of your vhdl file and upload it again</b>''', + '''name of your verilog model and add it again.</b>''', QtWidgets.QMessageBox.Ok ) # getting the port information here - def getPortInformation(self): portInformation = PortInfo(self, self.modelpath) portInformation.getPortInfo() @@ -267,7 +269,6 @@ class AutoSchematic: port_list = [] j = 0 - k = 0 # noqa F841 for i in range(total): if (i < inputs): input_port[1] = inputName[i] diff --git a/src/maker/makerchip.py b/src/maker/makerchip.py index 29e1421d..152c6cbb 100755 --- a/src/maker/makerchip.py +++ b/src/maker/makerchip.py @@ -27,23 +27,15 @@ # ========================================================================= # importing the files and libraries -import sys -import os from PyQt5 import QtWidgets -from configuration.Appconfig import Appconfig -from projManagement.Validation import Validation -# from .Processing import PrcocessNetlist from . import Maker from . import NgVeri -from xml.etree import ElementTree as ET - # filecount is used to count thenumber of objects created filecount = 0 -# this class creates objects for creating the Maker and the Ngveri tabs - +# This class creates objects for creating the Maker and the Ngveri tabs class makerchip(QtWidgets.QWidget): # initialising the variables |