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| author | Charaan | 2022-02-01 13:26:16 +0530 |
|---|---|---|
| committer | GitHub | 2022-02-01 13:26:16 +0530 |
| commit | 1d5cdb7e19c6efca598a6e7529b2969dfc18a450 (patch) | |
| tree | 9c95ff97c4cfed0c6ee815b02b9b6d94cea1aa35 /src/maker | |
| parent | 17fda9de4d1f011778b1c82e9cdfe1423b4ba775 (diff) | |
| download | eSim-1d5cdb7e19c6efca598a6e7529b2969dfc18a450.tar.gz eSim-1d5cdb7e19c6efca598a6e7529b2969dfc18a450.tar.bz2 eSim-1d5cdb7e19c6efca598a6e7529b2969dfc18a450.zip | |
Update ModelGeneration.py
Diffstat (limited to 'src/maker')
| -rwxr-xr-x | src/maker/ModelGeneration.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 71edad85..bc79e443 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -792,7 +792,7 @@ and set the load for input ports */ # print(self.modelpath) self.cmd = "verilator -Wall " + wno + "\ - --cc --exe --Mdir . -CFLAGS -fPIC sim_main_" + \ + --cc --exe --no-MMD --Mdir . -CFLAGS -fPIC sim_main_" + \ self.fname.split('.')[0] + ".cpp " + self.fname self.process = QtCore.QProcess(self) self.process.readyReadStandardOutput.connect(self.readAllStandard) |