Merge pull request #178 from Eyantra698Sumanto/makerchip

Added the Makerchip Files and icon

1 files changed, 40 insertions, 0 deletions

diff --git a/src/maker/tlv/clk_gate.v b/src/maker/tlv/clk_gate.v
new file mode 100755
index 00000000..77e9186d
--- /dev/null
+++ b/src/maker/tlv/clk_gate.v
@@ -0,0 +1,40 @@
+/*
+Copyright (c) 2015, Steven F. Hoover
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * The name of Steven F. Hoover
+      may not be used to endorse or promote products derived from this software
+      without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+`include "sp_default.vh"
+/* verilator lint_off LATCH */
+
+// Clock gate module used by SandPiper default project.
+
+module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);
+   wire clk_en;
+   reg latched_clk_en  /*verilator clock_enable*/;
+   assign clk_en = func_en & (pwr_en | gating_override);
+   `TLV_BLATCH(latched_clk_en, clk_en, free_clk)
+   assign gated_clk = latched_clk_en & free_clk;
+endmodule
+