summaryrefslogtreecommitdiff
path: root/src/maker/NgVeri.py
diff options
context:
space:
mode:
authorrahulp132022-02-22 01:50:56 +0530
committerrahulp132022-02-22 01:50:56 +0530
commit272bf20219595c3c541797b1045ce9c400ab02d6 (patch)
treea0deeb42b8bfa9af1294b28f4849f92be76ee076 /src/maker/NgVeri.py
parentab7dd7ed89899e2a17f70262e83437f50f2a924f (diff)
downloadeSim-272bf20219595c3c541797b1045ce9c400ab02d6.tar.gz
eSim-272bf20219595c3c541797b1045ce9c400ab02d6.tar.bz2
eSim-272bf20219595c3c541797b1045ce9c400ab02d6.zip
Added a note and tooltip for Makerchip requirements
Diffstat (limited to 'src/maker/NgVeri.py')
-rwxr-xr-xsrc/maker/NgVeri.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/maker/NgVeri.py b/src/maker/NgVeri.py
index c3c4d07c..c1fbcb4e 100755
--- a/src/maker/NgVeri.py
+++ b/src/maker/NgVeri.py
@@ -226,6 +226,10 @@ class NgVeri(QtWidgets.QWidget):
self.addverilogbutton = QtWidgets.QPushButton(
"Run Verilog to NgSpice Converter")
+ self.addverilogbutton.setToolTip(
+ "Requires internet connection for converting TL-Verilog models"
+ )
+ self.addverilogbutton.setToolTipDuration(5000)
self.optionsgroupbtn.addButton(self.addverilogbutton)
self.addverilogbutton.clicked.connect(self.addverilog)
self.optionsgrid.addWidget(self.addverilogbutton, 0, 1)