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author | rahulp13 | 2022-02-22 00:59:17 +0530 |
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committer | rahulp13 | 2022-02-22 00:59:17 +0530 |
commit | faadcb72916d269aeabbaa23f799962b6b99c45c (patch) | |
tree | d9c996c20bcb9703d95d7ea5ae54436387089d4f /src/maker/ModelGeneration.py | |
parent | ac1244c8275f5a43ea513b1c9af8c66044811ccc (diff) | |
download | eSim-faadcb72916d269aeabbaa23f799962b6b99c45c.tar.gz eSim-faadcb72916d269aeabbaa23f799962b6b99c45c.tar.bz2 eSim-faadcb72916d269aeabbaa23f799962b6b99c45c.zip |
Replaced SafeConfigParser alias with ConfigParser
Diffstat (limited to 'src/maker/ModelGeneration.py')
-rwxr-xr-x | src/maker/ModelGeneration.py | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 208664f8..54b91d50 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -35,11 +35,10 @@ import shutil # noqa:F401 import subprocess # noqa:F401 from PyQt5 import QtGui, QtCore, QtWidgets # noqa:F401 from PyQt5.QtGui import * # noqa:F401 F403 -from configparser import ConfigParser # noqa:F401 +from configparser import ConfigParser from configuration import Appconfig from . import createkicad import hdlparse.verilog_parser as vlog -from configparser import SafeConfigParser # noqa:F401 # Class is used to generate the Ngspice Model @@ -59,7 +58,7 @@ class ModelGeneration(QtWidgets.QWidget): self.fname = self.fname.lower() print("Verilog/SystemVerilog/TL Verilog filename is : ", self.fname) self.home = os.path.expanduser("~") - self.parser = SafeConfigParser() + self.parser = ConfigParser() self.parser.read(os.path.join( self.home, os.path.join('.nghdl', 'config.ini'))) self.ngspice_home = self.parser.get('NGSPICE', 'NGSPICE_HOME') |