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| author | Sunil Shetye | 2019-06-25 15:24:11 +0530 |
|---|---|---|
| committer | Sunil Shetye | 2019-06-25 15:55:41 +0530 |
| commit | 713e764817b7bf8c3bb4911c238f07780f3a0532 (patch) | |
| tree | e7e236553cd964c2b83dc61ac2df69cafba0ca2f /src/kicadtoNgspice/Processing.py | |
| parent | 32acf14bfbfa5d5874ebfdbf88ef64777f05e3f8 (diff) | |
| download | eSim-713e764817b7bf8c3bb4911c238f07780f3a0532.tar.gz eSim-713e764817b7bf8c3bb4911c238f07780f3a0532.tar.bz2 eSim-713e764817b7bf8c3bb4911c238f07780f3a0532.zip | |
pep8: break long lines
Diffstat (limited to 'src/kicadtoNgspice/Processing.py')
| -rw-r--r-- | src/kicadtoNgspice/Processing.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py index 216383e6..a0f2c79f 100644 --- a/src/kicadtoNgspice/Processing.py +++ b/src/kicadtoNgspice/Processing.py @@ -471,9 +471,9 @@ class PrcocessNetlist: schematicInfo.append(modelLine) k = k + 1 # For iron core - modelLine = "a" + str(k) + " (" + words[4] + " " + words[2] + ") \ - (interNode_" + str( - interMediateNodeCount + 1) + " " + words[3] + ") " + modelLine = "a" + str(k) + " (" + words[4] + " " + \ + words[2] + ") (interNode_" + \ + str(interMediateNodeCount + 1) + " " + words[3] + ") " modelLine += compName + "_secondary" schematicInfo.append(modelLine) k = k + 1 |