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authorunknown2019-06-03 14:56:53 +0530
committernilshah982019-06-17 22:34:34 +0530
commit89249e5003eccb07917d21788f6ce37e1de6d572 (patch)
tree3cf30e5211f8f5cbfafe7400b7b92670de00929a /src/kicadtoNgspice/Processing.py
parent1d4ee6b6c1254657c497673838922e746f339eca (diff)
downloadeSim-89249e5003eccb07917d21788f6ce37e1de6d572.tar.gz
eSim-89249e5003eccb07917d21788f6ce37e1de6d572.tar.bz2
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sphinx documentation init
Diffstat (limited to 'src/kicadtoNgspice/Processing.py')
-rw-r--r--src/kicadtoNgspice/Processing.py6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py
index 216383e6..ebbd3429 100644
--- a/src/kicadtoNgspice/Processing.py
+++ b/src/kicadtoNgspice/Processing.py
@@ -16,7 +16,6 @@ class PrcocessNetlist:
"""
- Read the circuit file and return splitted lines
"""
-
def readNetlist(self, filename):
f = open(filename)
data = f.read()
@@ -32,7 +31,6 @@ class PrcocessNetlist:
- Read Parameter information and store it into dictionary
- kicadNetlis is the .cir file content
"""
-
def readParamInfo(self, kicadNetlis):
param = {}
print("=========================KICADNETLIST========================")
@@ -57,7 +55,6 @@ class PrcocessNetlist:
- Preprocess netlist (replace parameters)
- Separate infoline (first line) from the rest of netlist
"""
-
def preprocessNetlist(self, kicadNetlis, param):
netlist = []
for eachline in kicadNetlis:
@@ -128,7 +125,6 @@ class PrcocessNetlist:
- Then check for type whether ac, dc, sine, etc...
- Handle starting with h and f as well
"""
-
def insertSpecialSourceParam(self, schematicInfo, sourcelist):
schematicInfo1 = []
print("=============================================================")
@@ -466,7 +462,7 @@ class PrcocessNetlist:
"a" + str(k) + " (" + words[1] + " " +
words[2] + ") (interNode_" +
str(interMediateNodeCount) + " " + words[3] + ") "
- )
+ )
modelLine += compName + "_primary"
schematicInfo.append(modelLine)
k = k + 1