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authorSunil Shetye2019-06-24 15:39:01 +0530
committerGitHub2019-06-24 15:39:01 +0530
commitca27e1ab9d418bfece063a38629da4dc09281e45 (patch)
treedb4048b7d093d7827b663b2cac98c5c49e37358e /src/kicadtoNgspice/Processing.py
parenta5effc6fcfb55751cd60a08f9774391ed34ba711 (diff)
parente75167f3e98add3912ff5db300f6f4d2535c5325 (diff)
downloadeSim-ca27e1ab9d418bfece063a38629da4dc09281e45.tar.gz
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Merge pull request #92 from nilshah98/sphinx
Resolves #90
Diffstat (limited to 'src/kicadtoNgspice/Processing.py')
-rw-r--r--src/kicadtoNgspice/Processing.py6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py
index 216383e6..ebbd3429 100644
--- a/src/kicadtoNgspice/Processing.py
+++ b/src/kicadtoNgspice/Processing.py
@@ -16,7 +16,6 @@ class PrcocessNetlist:
"""
- Read the circuit file and return splitted lines
"""
-
def readNetlist(self, filename):
f = open(filename)
data = f.read()
@@ -32,7 +31,6 @@ class PrcocessNetlist:
- Read Parameter information and store it into dictionary
- kicadNetlis is the .cir file content
"""
-
def readParamInfo(self, kicadNetlis):
param = {}
print("=========================KICADNETLIST========================")
@@ -57,7 +55,6 @@ class PrcocessNetlist:
- Preprocess netlist (replace parameters)
- Separate infoline (first line) from the rest of netlist
"""
-
def preprocessNetlist(self, kicadNetlis, param):
netlist = []
for eachline in kicadNetlis:
@@ -128,7 +125,6 @@ class PrcocessNetlist:
- Then check for type whether ac, dc, sine, etc...
- Handle starting with h and f as well
"""
-
def insertSpecialSourceParam(self, schematicInfo, sourcelist):
schematicInfo1 = []
print("=============================================================")
@@ -466,7 +462,7 @@ class PrcocessNetlist:
"a" + str(k) + " (" + words[1] + " " +
words[2] + ") (interNode_" +
str(interMediateNodeCount) + " " + words[3] + ") "
- )
+ )
modelLine += compName + "_primary"
schematicInfo.append(modelLine)
k = k + 1