diff options
| author | Fahim | 2016-02-17 17:00:35 +0530 |
|---|---|---|
| committer | Fahim | 2016-02-17 17:00:35 +0530 |
| commit | d634304de8022c499b1a4a23c85aa5f124539d93 (patch) | |
| tree | 9ec07da28a569b4ebc54c69eba778809457f451d /src/kicadtoNgspice/Processing.py | |
| parent | 9b6b022edb89e14fa83c3c1d6ebf0a9f96500b1a (diff) | |
| parent | 8a6f29decb7793e678aa8492f4f8d899087f2f68 (diff) | |
| download | eSim-d634304de8022c499b1a4a23c85aa5f124539d93.tar.gz eSim-d634304de8022c499b1a4a23c85aa5f124539d93.tar.bz2 eSim-d634304de8022c499b1a4a23c85aa5f124539d93.zip | |
Merge branch 'develop'
Conflicts:
kicadSchematicLibrary/kicad.pro
src/ngspicetoModelica/__init__.py
Diffstat (limited to 'src/kicadtoNgspice/Processing.py')
| -rw-r--r-- | src/kicadtoNgspice/Processing.py | 37 |
1 files changed, 33 insertions, 4 deletions
diff --git a/src/kicadtoNgspice/Processing.py b/src/kicadtoNgspice/Processing.py index b0f60826..0eaf6d2f 100644 --- a/src/kicadtoNgspice/Processing.py +++ b/src/kicadtoNgspice/Processing.py @@ -152,10 +152,12 @@ class PrcocessNetlist: return schematicInfo,sourcelist - def convertICintoBasicBlocks(self,schematicInfo,outputOption,modelList): + def convertICintoBasicBlocks(self,schematicInfo,outputOption,modelList,plotText): #Insert details of Ngspice model unknownModelList = [] multipleModelList = [] + plotList = ['plot_v1','plot_v2','plot_i2','plot_log','plot_db','plot_phase'] + k = 1 for compline in schematicInfo: words = compline.split() @@ -177,7 +179,7 @@ class PrcocessNetlist: print "Words",words print "compName",compName #Looking if model file is present - if compType != "port" and compType != "ic": + if compType != "port" and compType != "ic" and compType not in plotList: xmlfile = compType+".xml" #XML Model File count = 0 #Check if model of same name is present modelPath = [] @@ -304,14 +306,41 @@ class PrcocessNetlist: text = "Enter initial voltage at node for "+compline paramDict[title] = text modelList.append([index,compline,modelname,compName,comment,title,type,paramDict]) + + elif compType in plotList: + print "Plot Data---------->" + schematicInfo.insert(index,"* "+compline) + if compType == 'plot_v1': + words = compline.split() + plotText.append("plot v("+words[1]+")") + elif compType == 'plot_v2': + words = compline.split() + plotText.append("plot v("+words[1]+","+words[2]+")") + elif compType == 'plot_i2': + words = compline.split() + #Adding zero voltage source to netlist + schematicInfo.append("v_"+words[0]+" "+words[1]+" "+words[2]+" "+"0") + plotText.append("plot i(v_"+words[0]+")") + elif compType == 'plot_log': + words = compline.split() + plotText.append("plot log("+words[1]+")") + elif compType == 'plot_db': + words = compline.split() + plotText.append("plot db("+words[1]+")") + elif compType == 'plot_phase': + words = compline.split() + plotText.append("plot phase("+words[1]+")") + else: schematicInfo.insert(index,"* "+compline) + + #print "Count",count #print "UnknownModelList",unknownModelList #print "MultipleModelList",multipleModelList - return schematicInfo,outputOption,modelList,unknownModelList,multipleModelList + return schematicInfo,outputOption,modelList,unknownModelList,multipleModelList,plotText -
\ No newline at end of file + |