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author | Fahim | 2015-08-11 14:21:15 +0530 |
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committer | Fahim | 2015-08-11 14:21:15 +0530 |
commit | 4c4e4e0882a6e5ed7c78339794073bac1ec3db04 (patch) | |
tree | 944d1c4fdcb897747db4995b8c239c3943bb1152 /src/kicadtoNgspice/Convert.py | |
parent | 4768fe565e83e8c8f4f4607f4cf4b199bf0bdc46 (diff) | |
download | eSim-4c4e4e0882a6e5ed7c78339794073bac1ec3db04.tar.gz eSim-4c4e4e0882a6e5ed7c78339794073bac1ec3db04.tar.bz2 eSim-4c4e4e0882a6e5ed7c78339794073bac1ec3db04.zip |
Subject: Bug Fixing : Remove multiple analysis,.model,.include line from
final schematic file.
Description: Remove multiple analysis,.model,.include line from
final schematic file.
Diffstat (limited to 'src/kicadtoNgspice/Convert.py')
-rw-r--r-- | src/kicadtoNgspice/Convert.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/kicadtoNgspice/Convert.py b/src/kicadtoNgspice/Convert.py index ae426470..2b10f83d 100644 --- a/src/kicadtoNgspice/Convert.py +++ b/src/kicadtoNgspice/Convert.py @@ -374,7 +374,8 @@ class Convert: #Adding .include line to Schematic Info at the start of line for item in list(set(includeLine)): schematicInfo.insert(0,item) - + + return schematicInfo def addSubcircuit(self,schematicInfo,kicadFile): |