Added subcircuit functionality

22 files changed, 1871 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis
new file mode 100644
index 00000000..52ccc5ec
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/analysis
@@ -0,0 +1 @@
+.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.bak b/src/SubcircuitLibrary/lm555n/lm555n.bak
new file mode 100644
index 00000000..92d1f7a7
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.bak
@@ -0,0 +1,435 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 10:48:46 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:digitalXSpice
+LIBS:lm555n-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
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+Title ""
+Date "17 dec 2012"
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diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir
new file mode 100644
index 00000000..8f6f81c6
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir
@@ -0,0 +1,25 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U5  5 21 D_INVERTER		
+U6  1 4 5 21 21 8 10 D_SRLATCH		
+E2  18 0 23 14 10000		
+*U4  19 20 11 12 LIMIT8		
+*U3  8 10 7 9 DAC8		
+*U2  11 12 6 4 1 5 ADC8		
+U1  22 14 7 6 15 16 3 13 PORT		
+R8  9 2 1500		
+Q1  22 2 3 QNOM		
+R7  18 20 25		
+R6  17 19 25		
+E1  17 0 16 15 10000		
+R4  16 15 2E6		
+R5  23 14 2E6		
+R3  23 22 5000		
+R2  15 23 5000		
+R1  13 15 5000		
+
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt
new file mode 100644
index 00000000..90f04a32
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt
@@ -0,0 +1,35 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+
+* Inverter d_inverter
+* SR Latch d_srlatch
+e2  18 0 23 14 10000
+* Limiter limit8
+* Digital to Analog converter dac8
+* Analog to Digital converter adc8
+u1  22 14 7 6 15 16 3 13 port
+r8  9 2 1500
+q1 3 2 22 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
+a2 1 4 5 21 21 8 10 u6
+.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
+a3 19 11 u4
+a4 20 12 u4
+.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0)
+a5 [8] [7] u3
+a6 [10] [9] u3
+.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
+a7 [11] [4] u2
+a8 [12] [1] u2
+a9 [6] [5] u2
+.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
new file mode 100644
index 00000000..f25b1e46
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
@@ -0,0 +1,31 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+
+* u5  5 21 d_inverter
+* u6  1 4 5 21 21 8 10 d_srlatch
+e2  18 0 23 14 10000
+* u1  22 14 7 6 15 16 3 13 port
+r8  9 2 1500
+q1  22 2 3 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+a2 1 4 5 21 21 8 10 u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
+.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out~ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~
new file mode 100644
index 00000000..bc50c640
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~
@@ -0,0 +1,30 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+
+* u5  5 21 d_inverter
+* u6  1 4 5 21 21 8 10 d_srlatch
+e2  18 0 23 14 10000
+r8  9 2 1500
+q1  22 2 3 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+a2 1 4 5 21 21 8 10 u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
+.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir~ b/src/SubcircuitLibrary/lm555n/lm555n.cir~
new file mode 100644
index 00000000..7ef9e6a5
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir~
@@ -0,0 +1,25 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U5  5 21 D_INVERTER		
+U6  1 4 5 21 21 8 10 D_SRLATCH		
+E2  18 0 23 14 10000		
+*U4  19 20 11 12 LIMIT8		
+*U3  8 10 7 9 DAC8		
+*U2  11 12 6 4 1 5 ADC8		
+*U1  22 14 7 6 15 16 3 13 PORT		
+R8  9 2 1500		
+Q1  22 2 3 QNOM		
+R7  18 20 25		
+R6  17 19 25		
+E1  17 0 16 15 10000		
+R4  16 15 2E6		
+R5  23 14 2E6		
+R3  23 22 5000		
+R2  15 23 5000		
+R1  13 15 5000		
+
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro
new file mode 100644
index 00000000..c8e151fb
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.pro
@@ -0,0 +1,73 @@
+update=Monday 19 November 2012 04:56:38 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/FreeEDA/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=analogXSpice
+LibName33=converterSpice
+LibName34=digitalSpice
+LibName35=linearSpice
+LibName36=measurementSpice
+LibName37=portSpice
+LibName38=sourcesSpice
+LibName39=digitalXSpice
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch
new file mode 100644
index 00000000..fabbb666
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sch
@@ -0,0 +1,435 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 10:57:52 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:digitalXSpice
+LIBS:lm555n-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "17 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+U 1 1 50CEA9C5
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+F 0 "U5" H 6550 4150 40  0000 C CNN
+F 1 "D_INVERTER" H 6800 4150 40  0000 C CNN
+	1    6700 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L D_SRLATCH U6
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+P 7100 3400
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+F 1 "D_SRLATCH" H 7100 3500 60  0000 C CNN
+	1    7100 3400
+	1    0    0    -1  
+$EndComp
+Text Notes 5750 3050 0    60   ~ 0
+IC 555
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+	4700 3000 4900 3000
+Wire Wire Line
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+Connection ~ 4400 3550
+Connection ~ 4400 4900
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 5550 4450
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+Wire Wire Line
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+Wire Wire Line
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+Text Label 4850 4100 0    60   ~ 0
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+$EndComp
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+$EndComp
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+$EndComp
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+F 1 "PORT" H 4050 3000 30  0000 C CNN
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+$EndComp
+$Comp
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+F 1 "1500" V 7350 4250 50  0000 C CNN
+	1    7350 4250
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+$EndComp
+$Comp
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+	1    7600 4600
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+$EndComp
+$Comp
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+	1    5550 4500
+	1    0    0    -1  
+$EndComp
+Text Label 4850 4000 0    60   ~ 0
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+$Comp
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+$EndComp
+$Comp
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+$EndComp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
+L R R5
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
+L R R1
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+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub
new file mode 100644
index 00000000..862626ea
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sub
@@ -0,0 +1,25 @@
+* Subcircuit lm555n
+.subckt lm555n 22 14 7 6 15 16 3 13 
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+* u5  5 21 d_inverter
+* u6  1 4 5 21 21 8 10 d_srlatch
+e2  18 0 23 14 10000
+r8  9 2 1500
+q1  22 2 3 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+a2 1 4 5 21 21 8 10 u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
+.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 )
+* Control Statements
+
+.ends lm555n
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml
new file mode 100644
index 00000000..7d81146a
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ua741/analysis b/src/SubcircuitLibrary/ua741/analysis
new file mode 100644
index 00000000..52ccc5ec
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/analysis
@@ -0,0 +1 @@
+.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.bak b/src/SubcircuitLibrary/ua741/ua741-cache.bak
new file mode 100644
index 00000000..eaad34ad
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741-cache.bak
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3  Date: Sunday 21 October 2012 01:22:10 AM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 0 -50 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 I
+X ~ 2 250 0 100 L 30 30 2 1 I
+X ~ 3 250 0 100 L 30 30 3 1 I
+X ~ 4 250 0 100 L 30 30 4 1 I
+X ~ 5 250 0 100 L 30 30 5 1 I
+X ~ 6 250 0 100 L 30 30 6 1 I
+X ~ 7 250 0 100 L 30 30 7 1 I
+X ~ 8 250 0 100 L 30 30 8 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.lib b/src/SubcircuitLibrary/ua741/ua741-cache.lib
new file mode 100644
index 00000000..9114d342
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3  Date: Saturday 17 November 2012 08:10:48 AM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 0 -50 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 I
+X ~ 2 250 0 100 L 30 30 2 1 I
+X ~ 3 250 0 100 L 30 30 3 1 I
+X ~ 4 250 0 100 L 30 30 4 1 I
+X ~ 5 250 0 100 L 30 30 5 1 I
+X ~ 6 250 0 100 L 30 30 6 1 I
+X ~ 7 250 0 100 L 30 30 7 1 I
+X ~ 8 250 0 100 L 30 30 8 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/ua741/ua741.bak b/src/SubcircuitLibrary/ua741/ua741.bak
new file mode 100644
index 00000000..6be92803
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.bak
@@ -0,0 +1,208 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:17:01 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:ua741-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "20 oct 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L PORT U1
+U 3 1 5082C027
+P 6250 2500
+F 0 "U1" H 6250 2450 30  0000 C CNN
+F 1 "PORT" H 6250 2500 30  0000 C CNN
+	3    6250 2500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5082C011
+P 2300 3100
+F 0 "U1" H 2300 3050 30  0000 C CNN
+F 1 "PORT" H 2300 3100 30  0000 C CNN
+	1    2300 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5082C00B
+P 2250 2600
+F 0 "U1" H 2250 2550 30  0000 C CNN
+F 1 "PORT" H 2250 2600 30  0000 C CNN
+	2    2250 2600
+	1    0    0    -1  
+$EndComp
+Connection ~ 3700 3200
+Wire Wire Line
+	3450 3200 3700 3200
+Connection ~ 5000 3300
+Wire Wire Line
+	3700 3300 5250 3300
+Wire Wire Line
+	5250 3300 5250 3200
+Connection ~ 4550 3300
+Wire Wire Line
+	5000 3300 5000 2950
+Connection ~ 3700 3300
+Wire Wire Line
+	4550 3300 4550 3100
+Wire Wire Line
+	3900 2500 3700 2500
+Wire Wire Line
+	3700 2500 3700 2550
+Wire Wire Line
+	3450 2900 3300 2900
+Wire Wire Line
+	3300 2900 3300 3200
+Wire Wire Line
+	3300 3200 2950 3200
+Connection ~ 2950 3100
+Wire Wire Line
+	2950 3200 2950 3100
+Wire Wire Line
+	3000 2600 2500 2600
+Wire Wire Line
+	2550 3100 3000 3100
+Wire Wire Line
+	2950 2600 2950 2500
+Connection ~ 2950 2600
+Wire Wire Line
+	2950 2500 3300 2500
+Wire Wire Line
+	3300 2500 3300 2800
+Wire Wire Line
+	3300 2800 3450 2800
+Wire Wire Line
+	3700 3150 3700 3400
+Wire Wire Line
+	4550 2500 4550 2700
+Wire Wire Line
+	4400 2500 5000 2500
+Wire Wire Line
+	5000 2500 5000 2850
+Connection ~ 4550 2500
+Wire Wire Line
+	5250 2600 5250 2500
+Wire Wire Line
+	5250 2500 5350 2500
+Wire Wire Line
+	5850 2500 6000 2500
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 508152A0
+P 3450 3200
+F 0 "#FLG01" H 3450 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 3450 3430 30  0000 C CNN
+	1    3450 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rout1
+U 1 1 50813F5B
+P 5600 2500
+F 0 "Rout1" V 5680 2500 50  0000 C CNN
+F 1 "75" V 5600 2500 50  0000 C CNN
+	1    5600 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L VCVS Eout1
+U 1 1 50813F0F
+P 5200 2900
+F 0 "Eout1" H 5000 3000 50  0000 C CNN
+F 1 "1" H 5000 2850 50  0000 C CNN
+	1    5200 2900
+	0    1    1    0   
+$EndComp
+$Comp
+L C Cbw1
+U 1 1 50813EE0
+P 4550 2900
+F 0 "Cbw1" H 4600 3000 50  0000 L CNN
+F 1 "31.85e-9" H 4600 2800 50  0000 L CNN
+	1    4550 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rbw1
+U 1 1 50813EAB
+P 4150 2500
+F 0 "Rbw1" V 4230 2500 50  0000 C CNN
+F 1 "0.5e6" V 4150 2500 50  0000 C CNN
+	1    4150 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 50813E0D
+P 3700 3400
+F 0 "#PWR02" H 3700 3400 30  0001 C CNN
+F 1 "GND" H 3700 3330 30  0001 C CNN
+	1    3700 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L VCVS Ein1
+U 1 1 50813D7C
+P 3650 2850
+F 0 "Ein1" H 3450 2950 50  0000 C CNN
+F 1 "100e3" H 3450 2800 50  0000 C CNN
+	1    3650 2850
+	0    1    1    0   
+$EndComp
+$Comp
+L R Rin1
+U 1 1 50813C57
+P 3000 2850
+F 0 "Rin1" V 3080 2850 50  0000 C CNN
+F 1 "2e6" V 3000 2850 50  0000 C CNN
+	1    3000 2850
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/ua741/ua741.cir b/src/SubcircuitLibrary/ua741/ua741.cir
new file mode 100644
index 00000000..de797429
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.cir
@@ -0,0 +1,15 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  6 7 3 PORT		
+Rout1  3 2 75		
+Eout1  2 0 1 0 1		
+Cbw1  1 0 31.85e-9		
+Rbw1  1 4 0.5e6		
+Ein1  4 0 7 6 100e3		
+Rin1  7 6 2e6		
+
+.end
diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.ckt b/src/SubcircuitLibrary/ua741/ua741.cir.ckt
new file mode 100644
index 00000000..3661a9a2
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.cir.ckt
@@ -0,0 +1,9 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+
+u1  6 7 3 port
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.out b/src/SubcircuitLibrary/ua741/ua741.cir.out
new file mode 100644
index 00000000..72e68514
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.cir.out
@@ -0,0 +1,18 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+
+* u1  6 7 3 port
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro
new file mode 100644
index 00000000..5dbb81a5
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.pro
@@ -0,0 +1,72 @@
+update=Monday 17 December 2012 06:14:06 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/FreeEDA/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=converterSpice
+LibName33=digitalSpice
+LibName34=linearSpice
+LibName35=measurementSpice
+LibName36=portSpice
+LibName37=sourcesSpice
+LibName38=analogXSpice
diff --git a/src/SubcircuitLibrary/ua741/ua741.sch b/src/SubcircuitLibrary/ua741/ua741.sch
new file mode 100644
index 00000000..7dfc5e1a
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.sch
@@ -0,0 +1,219 @@
+EESchema Schematic File Version 2  date Wednesday 19 December 2012 10:15:16 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:analogXSpice
+LIBS:ua741-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "19 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Notes 3800 2400 0    60   ~ 0
+Op-Amp
+Text Notes 3750 2850 0    60   ~ 0
+VCCS
+Text Notes 5800 2500 0    60   ~ 0
+out
+Text Notes 2750 3100 0    60   ~ 0
+-
+Text Notes 2700 2600 0    60   ~ 0
++
+$Comp
+L PORT U1
+U 6 1 5082C027
+P 6250 2500
+F 0 "U1" H 6250 2450 30  0000 C CNN
+F 1 "PORT" H 6250 2500 30  0000 C CNN
+	6    6250 2500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5082C011
+P 2300 3100
+F 0 "U1" H 2300 3050 30  0000 C CNN
+F 1 "PORT" H 2300 3100 30  0000 C CNN
+	2    2300 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5082C00B
+P 2250 2600
+F 0 "U1" H 2250 2550 30  0000 C CNN
+F 1 "PORT" H 2250 2600 30  0000 C CNN
+	3    2250 2600
+	1    0    0    -1  
+$EndComp
+Connection ~ 3700 3200
+Wire Wire Line
+	3450 3200 3700 3200
+Connection ~ 5000 3300
+Wire Wire Line
+	3700 3300 5250 3300
+Wire Wire Line
+	5250 3300 5250 3200
+Connection ~ 4550 3300
+Wire Wire Line
+	5000 3300 5000 2950
+Connection ~ 3700 3300
+Wire Wire Line
+	4550 3300 4550 3100
+Wire Wire Line
+	3900 2500 3700 2500
+Wire Wire Line
+	3700 2500 3700 2550
+Wire Wire Line
+	3450 2900 3300 2900
+Wire Wire Line
+	3300 2900 3300 3200
+Wire Wire Line
+	3300 3200 2950 3200
+Connection ~ 2950 3100
+Wire Wire Line
+	2950 3200 2950 3100
+Wire Wire Line
+	3000 2600 2500 2600
+Wire Wire Line
+	2550 3100 3000 3100
+Wire Wire Line
+	2950 2600 2950 2500
+Connection ~ 2950 2600
+Wire Wire Line
+	2950 2500 3300 2500
+Wire Wire Line
+	3300 2500 3300 2800
+Wire Wire Line
+	3300 2800 3450 2800
+Wire Wire Line
+	3700 3150 3700 3400
+Wire Wire Line
+	4550 2500 4550 2700
+Wire Wire Line
+	4400 2500 5000 2500
+Wire Wire Line
+	5000 2500 5000 2850
+Connection ~ 4550 2500
+Wire Wire Line
+	5250 2600 5250 2500
+Wire Wire Line
+	5250 2500 5350 2500
+Wire Wire Line
+	5850 2500 6000 2500
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 508152A0
+P 3450 3200
+F 0 "#FLG01" H 3450 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 3450 3430 30  0000 C CNN
+	1    3450 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rout1
+U 1 1 50813F5B
+P 5600 2500
+F 0 "Rout1" V 5680 2500 50  0000 C CNN
+F 1 "75" V 5600 2500 50  0000 C CNN
+	1    5600 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L VCVS Eout1
+U 1 1 50813F0F
+P 5200 2900
+F 0 "Eout1" H 5000 3000 50  0000 C CNN
+F 1 "1" H 5000 2850 50  0000 C CNN
+	1    5200 2900
+	0    1    1    0   
+$EndComp
+$Comp
+L C Cbw1
+U 1 1 50813EE0
+P 4550 2900
+F 0 "Cbw1" H 4600 3000 50  0000 L CNN
+F 1 "31.85e-9" H 4600 2800 50  0000 L CNN
+	1    4550 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rbw1
+U 1 1 50813EAB
+P 4150 2500
+F 0 "Rbw1" V 4230 2500 50  0000 C CNN
+F 1 "0.5e6" V 4150 2500 50  0000 C CNN
+	1    4150 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 50813E0D
+P 3700 3400
+F 0 "#PWR02" H 3700 3400 30  0001 C CNN
+F 1 "GND" H 3700 3330 30  0001 C CNN
+	1    3700 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L VCVS Ein1
+U 1 1 50813D7C
+P 3650 2850
+F 0 "Ein1" H 3450 2950 50  0000 C CNN
+F 1 "100e3" H 3450 2800 50  0000 C CNN
+	1    3650 2850
+	0    1    1    0   
+$EndComp
+$Comp
+L R Rin1
+U 1 1 50813C57
+P 3000 2850
+F 0 "Rin1" V 3080 2850 50  0000 C CNN
+F 1 "2e6" V 3000 2850 50  0000 C CNN
+	1    3000 2850
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/ua741/ua741.sub b/src/SubcircuitLibrary/ua741/ua741.sub
new file mode 100644
index 00000000..ad26c001
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741.sub
@@ -0,0 +1,12 @@
+* Subcircuit ua741
+.subckt ua741 6 7 3 
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
+* Control Statements
+
+.ends ua741
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml b/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml
new file mode 100644
index 00000000..9c7bb530
--- /dev/null
+++ b/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file