diff options
| author | rahulp13 | 2020-02-21 12:36:46 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-21 12:36:46 +0530 |
| commit | 47d4daff2ab483c4cdfb82117ef0d25d53832214 (patch) | |
| tree | 55aefefe974f151de76c6a2dbe8df3b4c3393bbe /src/SubcircuitLibrary | |
| parent | 453c2dab78f81046fcbd42034a86c4e759a0ff68 (diff) | |
| download | eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.gz eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.tar.bz2 eSim-47d4daff2ab483c4cdfb82117ef0d25d53832214.zip | |
restructured eSim libraries
Diffstat (limited to 'src/SubcircuitLibrary')
642 files changed, 0 insertions, 47502 deletions
diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib deleted file mode 100644 index b3857f54..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter-cache.lib +++ /dev/null @@ -1,62 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_dff -# -DEF d_dff U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_dff" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 350 450 -350 -400 0 1 0 N -X Din 1 -550 350 200 R 50 50 1 1 I -X Clk 2 -550 -300 200 R 50 50 1 1 I C -X Set 3 0 650 200 D 50 50 1 1 I -X Reset 4 0 -600 200 U 50 50 1 1 I -X Dout 5 550 350 200 L 50 50 1 1 O -X Ndout 6 550 -300 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir deleted file mode 100644 index d5d8760a..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir +++ /dev/null @@ -1,13 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:44:38 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U2-Pad1_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ d_dff -U3 Net-_U3-Pad1_ Net-_U2-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U3-Pad1_ d_dff -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out deleted file mode 100644 index 4232f26a..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir - -* u2 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff -* u3 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2 -a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3 -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro deleted file mode 100644 index 7fc2f37d..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=Sat Jun 22 11:40:56 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User - diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch deleted file mode 100644 index 45c6e1de..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sch +++ /dev/null @@ -1,151 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:2bit-Up_counter-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_dff U2 -U 1 1 5D0DC6F1 -P 3900 3400 -F 0 "U2" H 3900 3400 60 0000 C CNN -F 1 "d_dff" H 3900 3550 60 0000 C CNN -F 2 "" H 3900 3400 60 0000 C CNN -F 3 "" H 3900 3400 60 0000 C CNN - 1 3900 3400 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U3 -U 1 1 5D0DC6F2 -P 5750 3400 -F 0 "U3" H 5750 3400 60 0000 C CNN -F 1 "d_dff" H 5750 3550 60 0000 C CNN -F 2 "" H 5750 3400 60 0000 C CNN -F 3 "" H 5750 3400 60 0000 C CNN - 1 5750 3400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3900 2750 3900 2500 -Wire Wire Line - 3900 2500 5750 2500 -Wire Wire Line - 5750 2500 5750 2750 -Wire Wire Line - 3900 4000 3900 4300 -Wire Wire Line - 3900 4300 5750 4300 -Wire Wire Line - 5750 4300 5750 4000 -Wire Wire Line - 4850 2500 4850 4800 -Connection ~ 4850 4300 -Connection ~ 4850 2500 -Wire Wire Line - 4850 4800 5250 4800 -Wire Wire Line - 3350 3700 2600 3700 -Wire Wire Line - 3350 3050 3150 3050 -Wire Wire Line - 3150 3050 3150 2350 -Wire Wire Line - 3150 2350 4600 2350 -Wire Wire Line - 4600 2350 4600 3700 -Wire Wire Line - 4450 3700 5200 3700 -Connection ~ 4600 3700 -Wire Wire Line - 5000 3050 5200 3050 -Wire Wire Line - 5000 3050 5000 2350 -Wire Wire Line - 5000 2350 6450 2350 -Wire Wire Line - 6450 2350 6450 3700 -Wire Wire Line - 6450 3700 6300 3700 -Wire Wire Line - 4450 3050 4500 3050 -Wire Wire Line - 4500 3050 4500 2600 -Wire Wire Line - 4500 2600 6800 2600 -Wire Wire Line - 6300 3050 7050 3050 -$Comp -L PORT U1 -U 1 1 5D0DC6F3 -P 2350 3700 -F 0 "U1" H 2400 3800 30 0000 C CNN -F 1 "PORT" H 2350 3700 30 0000 C CNN -F 2 "" H 2350 3700 60 0000 C CNN -F 3 "" H 2350 3700 60 0000 C CNN - 1 2350 3700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D0DC6F4 -P 5500 4800 -F 0 "U1" H 5550 4900 30 0000 C CNN -F 1 "PORT" H 5500 4800 30 0000 C CNN -F 2 "" H 5500 4800 60 0000 C CNN -F 3 "" H 5500 4800 60 0000 C CNN - 2 5500 4800 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 3 1 5D0DC6F5 -P 7050 2600 -F 0 "U1" H 7100 2700 30 0000 C CNN -F 1 "PORT" H 7050 2600 30 0000 C CNN -F 2 "" H 7050 2600 60 0000 C CNN -F 3 "" H 7050 2600 60 0000 C CNN - 3 7050 2600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 5D0DC6F6 -P 7300 3050 -F 0 "U1" H 7350 3150 30 0000 C CNN -F 1 "PORT" H 7300 3050 30 0000 C CNN -F 2 "" H 7300 3050 60 0000 C CNN -F 3 "" H 7300 3050 60 0000 C CNN - 4 7300 3050 - -1 0 0 1 -$EndComp -Text Notes 2650 3650 0 60 ~ 0 -CLK -Text Notes 6600 2550 0 60 ~ 0 -O0 -Text Notes 6800 3000 0 60 ~ 0 -O1 -Text Notes 5050 4750 0 60 ~ 0 -EN\n -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub deleted file mode 100644 index f888aa71..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 2bit_upcounter -.subckt 2bit_upcounter net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/2bit_upcounter/2bit_upcounter.cir -* u2 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ d_dff -* u3 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ d_dff -a1 net-_u2-pad1_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ u2 -a2 net-_u3-pad1_ net-_u2-pad1_ net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_u3-pad1_ u3 -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Control Statements - -.ends 2bit_upcounter
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml b/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml deleted file mode 100644 index 2daa4f78..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/2bit_upcounter_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bit_upcounter/analysis b/src/SubcircuitLibrary/2bit_upcounter/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/2bit_upcounter/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib b/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib deleted file mode 100644 index e16831e4..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul-cache.lib +++ /dev/null @@ -1,77 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# half_adder -# -DEF half_adder X 0 40 Y Y 1 F N -F0 "X" 900 500 60 H V C CNN -F1 "half_adder" 900 400 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 500 800 1250 0 0 1 0 N -X IN1 1 300 700 200 R 50 50 1 1 I -X IN2 2 300 100 200 R 50 50 1 1 I -X SUM 3 1450 700 200 L 50 50 1 1 O -X COUT 4 1450 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir b/src/SubcircuitLibrary/2bitmul/2bitmul.cir deleted file mode 100644 index 0f4deb6c..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir +++ /dev/null @@ -1,17 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\2bitmul\2bitmul.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 11:42:27 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U5 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad5_ d_and -U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and -U3 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_and -U2 Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_and -X2 Net-_U4-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_X1-Pad1_ half_adder -X1 Net-_X1-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ half_adder -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT - -.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out b/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out deleted file mode 100644 index 71766bd8..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.cir.out +++ /dev/null @@ -1,31 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir - -.include half_adder.sub -* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and -* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and -* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and -* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and -x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder -x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port -a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 -a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 -a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.pro b/src/SubcircuitLibrary/2bitmul/2bitmul.pro deleted file mode 100644 index eafbfb80..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=03/07/19 09:55:40 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary;../../../kicadSchematicLibrary;../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice -LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt - diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sch b/src/SubcircuitLibrary/2bitmul/2bitmul.sch deleted file mode 100644 index 0ba61912..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.sch +++ /dev/null @@ -1,284 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:2bitmul-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U5 -U 1 1 5C7FC048 -P 8150 2950 -F 0 "U5" H 8150 2950 60 0000 C CNN -F 1 "d_and" H 8200 3050 60 0000 C CNN -F 2 "" H 8150 2950 60 0000 C CNN -F 3 "" H 8150 2950 60 0000 C CNN - 1 8150 2950 - 0 1 1 0 -$EndComp -$Comp -L d_and U4 -U 1 1 5C7FC0BC -P 7450 2950 -F 0 "U4" H 7450 2950 60 0000 C CNN -F 1 "d_and" H 7500 3050 60 0000 C CNN -F 2 "" H 7450 2950 60 0000 C CNN -F 3 "" H 7450 2950 60 0000 C CNN - 1 7450 2950 - 0 1 1 0 -$EndComp -$Comp -L d_and U3 -U 1 1 5C7FC0F4 -P 6950 2950 -F 0 "U3" H 6950 2950 60 0000 C CNN -F 1 "d_and" H 7000 3050 60 0000 C CNN -F 2 "" H 6950 2950 60 0000 C CNN -F 3 "" H 6950 2950 60 0000 C CNN - 1 6950 2950 - 0 1 1 0 -$EndComp -$Comp -L d_and U2 -U 1 1 5C7FC11D -P 6400 2950 -F 0 "U2" H 6400 2950 60 0000 C CNN -F 1 "d_and" H 6450 3050 60 0000 C CNN -F 2 "" H 6400 2950 60 0000 C CNN -F 3 "" H 6400 2950 60 0000 C CNN - 1 6400 2950 - 0 1 1 0 -$EndComp -Wire Wire Line - 8150 2500 8150 2350 -Wire Wire Line - 8150 2350 7450 2350 -Wire Wire Line - 7450 2100 7450 2500 -Wire Wire Line - 6950 2500 6950 2350 -Wire Wire Line - 6950 2350 6400 2350 -Wire Wire Line - 6400 2350 6400 2500 -Wire Wire Line - 8250 1100 8250 2500 -Wire Wire Line - 8250 2250 7050 2250 -Wire Wire Line - 7050 2250 7050 2500 -Wire Wire Line - 7550 2150 7550 2500 -Wire Wire Line - 7550 2450 6500 2450 -Wire Wire Line - 6500 2450 6500 2500 -$Comp -L half_adder X2 -U 1 1 5C7FC23A -P 7200 3350 -F 0 "X2" H 8100 3850 60 0000 C CNN -F 1 "half_adder" H 8100 3750 60 0000 C CNN -F 2 "" H 7200 3350 60 0000 C CNN -F 3 "" H 7200 3350 60 0000 C CNN - 1 7200 3350 - 0 1 1 0 -$EndComp -$Comp -L half_adder X1 -U 1 1 5C7FC324 -P 6050 3350 -F 0 "X1" H 6950 3850 60 0000 C CNN -F 1 "half_adder" H 6950 3750 60 0000 C CNN -F 2 "" H 6050 3350 60 0000 C CNN -F 3 "" H 6050 3350 60 0000 C CNN - 1 6050 3350 - 0 1 1 0 -$EndComp -Wire Wire Line - 7500 3400 7900 3400 -Wire Wire Line - 7900 3400 7900 3650 -Wire Wire Line - 7000 3400 7300 3400 -Wire Wire Line - 7300 3400 7300 3650 -Wire Wire Line - 7300 4800 7050 4800 -Wire Wire Line - 7050 4800 7050 3600 -Wire Wire Line - 7050 3600 6750 3600 -Wire Wire Line - 6750 3600 6750 3650 -Wire Wire Line - 6450 3400 6450 3650 -Wire Wire Line - 6450 3650 6150 3650 -$Comp -L PORT U1 -U 5 1 5C7FC4F8 -P 8200 5300 -F 0 "U1" H 8250 5400 30 0000 C CNN -F 1 "PORT" H 8200 5300 30 0000 C CNN -F 2 "" H 8200 5300 60 0000 C CNN -F 3 "" H 8200 5300 60 0000 C CNN - 5 8200 5300 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 6 1 5C7FC5D7 -P 7300 5300 -F 0 "U1" H 7350 5400 30 0000 C CNN -F 1 "PORT" H 7300 5300 30 0000 C CNN -F 2 "" H 7300 5300 60 0000 C CNN -F 3 "" H 7300 5300 60 0000 C CNN - 6 7300 5300 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 7 1 5C7FC641 -P 6750 5150 -F 0 "U1" H 6800 5250 30 0000 C CNN -F 1 "PORT" H 6750 5150 30 0000 C CNN -F 2 "" H 6750 5150 60 0000 C CNN -F 3 "" H 6750 5150 60 0000 C CNN - 7 6750 5150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 8 1 5C7FC698 -P 6150 5250 -F 0 "U1" H 6200 5350 30 0000 C CNN -F 1 "PORT" H 6150 5250 30 0000 C CNN -F 2 "" H 6150 5250 60 0000 C CNN -F 3 "" H 6150 5250 60 0000 C CNN - 8 6150 5250 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 1 1 5C7FC6EC -P 8250 850 -F 0 "U1" H 8300 950 30 0000 C CNN -F 1 "PORT" H 8250 850 30 0000 C CNN -F 2 "" H 8250 850 60 0000 C CNN -F 3 "" H 8250 850 60 0000 C CNN - 1 8250 850 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 2 1 5C7FC815 -P 7900 850 -F 0 "U1" H 7950 950 30 0000 C CNN -F 1 "PORT" H 7900 850 30 0000 C CNN -F 2 "" H 7900 850 60 0000 C CNN -F 3 "" H 7900 850 60 0000 C CNN - 2 7900 850 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 3 1 5C7FC857 -P 7550 850 -F 0 "U1" H 7600 950 30 0000 C CNN -F 1 "PORT" H 7550 850 30 0000 C CNN -F 2 "" H 7550 850 60 0000 C CNN -F 3 "" H 7550 850 60 0000 C CNN - 3 7550 850 - 0 1 1 0 -$EndComp -Connection ~ 8250 2250 -Wire Wire Line - 7900 1100 7900 2150 -Wire Wire Line - 7900 2150 7550 2150 -Connection ~ 7550 2450 -Wire Wire Line - 7550 1100 7550 2100 -Wire Wire Line - 7550 2100 7450 2100 -Connection ~ 7450 2350 -Wire Wire Line - 7200 1050 7200 2100 -Wire Wire Line - 7200 2100 6800 2100 -Wire Wire Line - 6800 2100 6800 2350 -Connection ~ 6800 2350 -Wire Wire Line - 8200 3400 8200 5050 -$Comp -L PORT U1 -U 4 1 5C7FC898 -P 7200 800 -F 0 "U1" H 7250 900 30 0000 C CNN -F 1 "PORT" H 7200 800 30 0000 C CNN -F 2 "" H 7200 800 60 0000 C CNN -F 3 "" H 7200 800 60 0000 C CNN - 4 7200 800 - 0 1 1 0 -$EndComp -Wire Wire Line - 7300 5050 7300 4850 -Wire Wire Line - 7300 4850 7900 4850 -Wire Wire Line - 7900 4850 7900 4800 -Wire Wire Line - 6750 4800 6750 4900 -Wire Wire Line - 6150 4800 6150 5000 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul.sub b/src/SubcircuitLibrary/2bitmul/2bitmul.sub deleted file mode 100644 index e77495a6..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul.sub +++ /dev/null @@ -1,25 +0,0 @@ -* Subcircuit 2bitmul -.subckt 2bitmul net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ -* c:\esim\esim\src\subcircuitlibrary\2bitmul\2bitmul.cir -.include half_adder.sub -* u5 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad5_ d_and -* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad3_ d_and -* u3 net-_u1-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_and -* u2 net-_u1-pad2_ net-_u1-pad4_ net-_u2-pad3_ d_and -x2 net-_u4-pad3_ net-_u3-pad3_ net-_u1-pad6_ net-_x1-pad1_ half_adder -x1 net-_x1-pad1_ net-_u2-pad3_ net-_u1-pad7_ net-_u1-pad8_ half_adder -a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u1-pad5_ u5 -a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad3_ u4 -a3 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a4 [net-_u1-pad2_ net-_u1-pad4_ ] net-_u2-pad3_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 2bitmul
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml deleted file mode 100644 index 8a55af97..00000000 --- a/src/SubcircuitLibrary/2bitmul/2bitmul_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u5 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/analysis b/src/SubcircuitLibrary/2bitmul/analysis deleted file mode 100644 index 660a46cc..00000000 --- a/src/SubcircuitLibrary/2bitmul/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib b/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib deleted file mode 100644 index 68785220..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir b/src/SubcircuitLibrary/2bitmul/half_adder.cir deleted file mode 100644 index 8b2e7e06..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.cir +++ /dev/null @@ -1,11 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 1 4 3 d_xor -U3 1 4 2 d_and -U1 1 4 3 2 PORT - -.end diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out b/src/SubcircuitLibrary/2bitmul/half_adder.cir.out deleted file mode 100644 index b1b6b1e7..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 - -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -* u1 1 4 3 2 port -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.pro b/src/SubcircuitLibrary/2bitmul/half_adder.pro deleted file mode 100644 index 695ae0f6..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.pro +++ /dev/null @@ -1,69 +0,0 @@ -update=Wed Jun 24 11:27:22 2015 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog -LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices -LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital -LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid -LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources -LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sch b/src/SubcircuitLibrary/2bitmul/half_adder.sch deleted file mode 100644 index bf9bcbf0..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.sch +++ /dev/null @@ -1,152 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Sources -LIBS:eSim_Subckt -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_xor U2 -U 1 1 558A946A -P 5650 3050 -F 0 "U2" H 5650 3050 60 0000 C CNN -F 1 "d_xor" H 5700 3150 47 0000 C CNN -F 2 "" H 5650 3050 60 0000 C CNN -F 3 "" H 5650 3050 60 0000 C CNN - 1 5650 3050 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 558A94D5 -P 5700 3800 -F 0 "U3" H 5700 3800 60 0000 C CNN -F 1 "d_and" H 5750 3900 60 0000 C CNN -F 2 "" H 5700 3800 60 0000 C CNN -F 3 "" H 5700 3800 60 0000 C CNN - 1 5700 3800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 558A94F6 -P 4150 3000 -F 0 "U1" H 4200 3100 30 0000 C CNN -F 1 "PORT" H 4150 3000 30 0000 C CNN -F 2 "" H 4150 3000 60 0000 C CNN -F 3 "" H 4150 3000 60 0000 C CNN - 1 4150 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 558A9543 -P 4150 3450 -F 0 "U1" H 4200 3550 30 0000 C CNN -F 1 "PORT" H 4150 3450 30 0000 C CNN -F 2 "" H 4150 3450 60 0000 C CNN -F 3 "" H 4150 3450 60 0000 C CNN - 2 4150 3450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 558A9573 -P 6650 3000 -F 0 "U1" H 6700 3100 30 0000 C CNN -F 1 "PORT" H 6650 3000 30 0000 C CNN -F 2 "" H 6650 3000 60 0000 C CNN -F 3 "" H 6650 3000 60 0000 C CNN - 3 6650 3000 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 558A9606 -P 6700 3750 -F 0 "U1" H 6750 3850 30 0000 C CNN -F 1 "PORT" H 6700 3750 30 0000 C CNN -F 2 "" H 6700 3750 60 0000 C CNN -F 3 "" H 6700 3750 60 0000 C CNN - 4 6700 3750 - -1 0 0 1 -$EndComp -Wire Wire Line - 5200 2950 4450 2950 -Wire Wire Line - 4450 2950 4450 3000 -Wire Wire Line - 4450 3000 4400 3000 -Wire Wire Line - 4400 3450 4550 3450 -Wire Wire Line - 4550 3450 4550 3050 -Wire Wire Line - 4550 3050 5200 3050 -Wire Wire Line - 5250 3700 5000 3700 -Wire Wire Line - 5000 3700 5000 2950 -Connection ~ 5000 2950 -Wire Wire Line - 5250 3800 4850 3800 -Wire Wire Line - 4850 3800 4850 3050 -Connection ~ 4850 3050 -Wire Wire Line - 6100 3000 6400 3000 -Wire Wire Line - 6150 3750 6450 3750 -Text Notes 4550 2950 0 60 ~ 0 -IN1\n\n -Text Notes 4600 3150 0 60 ~ 0 -IN2 -Text Notes 6200 2950 0 60 ~ 0 -SUM\n -Text Notes 6200 3650 0 60 ~ 0 -COUT\n -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/2bitmul/half_adder.sub b/src/SubcircuitLibrary/2bitmul/half_adder.sub deleted file mode 100644 index e9f92223..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit half_adder -.subckt half_adder 1 4 3 2 -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends half_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml deleted file mode 100644 index b915f0da..00000000 --- a/src/SubcircuitLibrary/2bitmul/half_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and-cache.lib b/src/SubcircuitLibrary/3_and/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/3_and/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/3_and/3_and.cir b/src/SubcircuitLibrary/3_and/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/3_and/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/3_and/3_and.cir.out b/src/SubcircuitLibrary/3_and/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/3_and/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/3_and/3_and.pro b/src/SubcircuitLibrary/3_and/3_and.pro deleted file mode 100644 index 76df4655..00000000 --- a/src/SubcircuitLibrary/3_and/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/3_and/3_and.sch b/src/SubcircuitLibrary/3_and/3_and.sch deleted file mode 100644 index d6ac89f9..00000000 --- a/src/SubcircuitLibrary/3_and/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:3_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -Text Notes 3500 2600 0 60 ~ 12 -in1 -Text Notes 3450 2800 0 60 ~ 12 -in2\n -Text Notes 3500 3100 0 60 ~ 12 -in3 -Text Notes 6100 2850 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/3_and/3_and.sub b/src/SubcircuitLibrary/3_and/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/3_and/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/3_and/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/3_and/analysis b/src/SubcircuitLibrary/3_and/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/3_and/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/4002-cache.lib b/src/SubcircuitLibrary/4002/4002-cache.lib deleted file mode 100644 index 677411a9..00000000 --- a/src/SubcircuitLibrary/4002/4002-cache.lib +++ /dev/null @@ -1,82 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_nor -# -DEF d_nor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nor" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4002/4002.cir b/src/SubcircuitLibrary/4002/4002.cir deleted file mode 100644 index 5d5c1ed7..00000000 --- a/src/SubcircuitLibrary/4002/4002.cir +++ /dev/null @@ -1,17 +0,0 @@ -* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or -U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or -U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT -U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or -U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or -U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor - -.end diff --git a/src/SubcircuitLibrary/4002/4002.cir.out b/src/SubcircuitLibrary/4002/4002.cir.out deleted file mode 100644 index e9cc6862..00000000 --- a/src/SubcircuitLibrary/4002/4002.cir.out +++ /dev/null @@ -1,36 +0,0 @@ -* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir - -* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or -* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or -* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or -* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor -a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 -a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 -a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 -a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 -a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4002/4002.pro b/src/SubcircuitLibrary/4002/4002.pro deleted file mode 100644 index 225ef82a..00000000 --- a/src/SubcircuitLibrary/4002/4002.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 09:35:41 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog -LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices -LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital -LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid -LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot -LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power -LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources -LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt -LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User -LibName11=power diff --git a/src/SubcircuitLibrary/4002/4002.sch b/src/SubcircuitLibrary/4002/4002.sch deleted file mode 100644 index 545f46fe..00000000 --- a/src/SubcircuitLibrary/4002/4002.sch +++ /dev/null @@ -1,315 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_or U2 -U 1 1 5CEE059A -P 4750 2900 -F 0 "U2" H 4750 2900 60 0000 C CNN -F 1 "d_or" H 4750 3000 60 0000 C CNN -F 2 "" H 4750 2900 60 0000 C CNN -F 3 "" H 4750 2900 60 0000 C CNN - 1 4750 2900 - 1 0 0 -1 -$EndComp -$Comp -L d_or U3 -U 1 1 5CEE0629 -P 4750 3450 -F 0 "U3" H 4750 3450 60 0000 C CNN -F 1 "d_or" H 4750 3550 60 0000 C CNN -F 2 "" H 4750 3450 60 0000 C CNN -F 3 "" H 4750 3450 60 0000 C CNN - 1 4750 3450 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U6 -U 1 1 5CEE0663 -P 6000 3100 -F 0 "U6" H 6000 3100 60 0000 C CNN -F 1 "d_nor" H 6050 3200 60 0000 C CNN -F 2 "" H 6000 3100 60 0000 C CNN -F 3 "" H 6000 3100 60 0000 C CNN - 1 6000 3100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5200 2850 5400 2850 -Wire Wire Line - 5400 2850 5400 3000 -Wire Wire Line - 5400 3000 5550 3000 -Wire Wire Line - 5200 3400 5400 3400 -Wire Wire Line - 5400 3400 5400 3100 -Wire Wire Line - 5400 3100 5550 3100 -Wire Wire Line - 5650 5350 6050 5350 -Wire Wire Line - 5650 5550 6050 5550 -Wire Wire Line - 5650 5800 6050 5800 -Wire Wire Line - 5650 6000 6050 6000 -NoConn ~ 5650 5350 -NoConn ~ 5650 5550 -NoConn ~ 5650 5800 -NoConn ~ 5650 6000 -$Comp -L PORT U1 -U 2 1 5CEE1C41 -P 3850 2800 -F 0 "U1" H 3900 2900 30 0000 C CNN -F 1 "PORT" H 3850 2800 30 0000 C CNN -F 2 "" H 3850 2800 60 0000 C CNN -F 3 "" H 3850 2800 60 0000 C CNN - 2 3850 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CEE22EE -P 3900 3050 -F 0 "U1" H 3950 3150 30 0000 C CNN -F 1 "PORT" H 3900 3050 30 0000 C CNN -F 2 "" H 3900 3050 60 0000 C CNN -F 3 "" H 3900 3050 60 0000 C CNN - 3 3900 3050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CEE2322 -P 3900 3250 -F 0 "U1" H 3950 3350 30 0000 C CNN -F 1 "PORT" H 3900 3250 30 0000 C CNN -F 2 "" H 3900 3250 60 0000 C CNN -F 3 "" H 3900 3250 60 0000 C CNN - 5 3900 3250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CEE2351 -P 3900 3550 -F 0 "U1" H 3950 3650 30 0000 C CNN -F 1 "PORT" H 3900 3550 30 0000 C CNN -F 2 "" H 3900 3550 60 0000 C CNN -F 3 "" H 3900 3550 60 0000 C CNN - 4 3900 3550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CEE2387 -P 6950 3050 -F 0 "U1" H 7000 3150 30 0000 C CNN -F 1 "PORT" H 6950 3050 30 0000 C CNN -F 2 "" H 6950 3050 60 0000 C CNN -F 3 "" H 6950 3050 60 0000 C CNN - 1 6950 3050 - -1 0 0 1 -$EndComp -Wire Wire Line - 4100 2800 4300 2800 -Wire Wire Line - 4150 3050 4150 2900 -Wire Wire Line - 4150 2900 4300 2900 -Wire Wire Line - 4150 3250 4300 3250 -Wire Wire Line - 4300 3250 4300 3350 -Wire Wire Line - 4150 3550 4150 3450 -Wire Wire Line - 4150 3450 4300 3450 -Wire Wire Line - 6700 3050 6450 3050 -$Comp -L d_or U4 -U 1 1 5CEE4ED7 -P 4900 4100 -F 0 "U4" H 4900 4100 60 0000 C CNN -F 1 "d_or" H 4900 4200 60 0000 C CNN -F 2 "" H 4900 4100 60 0000 C CNN -F 3 "" H 4900 4100 60 0000 C CNN - 1 4900 4100 - 1 0 0 -1 -$EndComp -$Comp -L d_or U5 -U 1 1 5CEE4EDD -P 4900 4650 -F 0 "U5" H 4900 4650 60 0000 C CNN -F 1 "d_or" H 4900 4750 60 0000 C CNN -F 2 "" H 4900 4650 60 0000 C CNN -F 3 "" H 4900 4650 60 0000 C CNN - 1 4900 4650 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U7 -U 1 1 5CEE4EE3 -P 6150 4300 -F 0 "U7" H 6150 4300 60 0000 C CNN -F 1 "d_nor" H 6200 4400 60 0000 C CNN -F 2 "" H 6150 4300 60 0000 C CNN -F 3 "" H 6150 4300 60 0000 C CNN - 1 6150 4300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5350 4050 5550 4050 -Wire Wire Line - 5550 4050 5550 4200 -Wire Wire Line - 5550 4200 5700 4200 -Wire Wire Line - 5350 4600 5550 4600 -Wire Wire Line - 5550 4600 5550 4300 -Wire Wire Line - 5550 4300 5700 4300 -$Comp -L PORT U1 -U 9 1 5CEE4EEF -P 4000 4000 -F 0 "U1" H 4050 4100 30 0000 C CNN -F 1 "PORT" H 4000 4000 30 0000 C CNN -F 2 "" H 4000 4000 60 0000 C CNN -F 3 "" H 4000 4000 60 0000 C CNN - 9 4000 4000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CEE4EF5 -P 4050 4250 -F 0 "U1" H 4100 4350 30 0000 C CNN -F 1 "PORT" H 4050 4250 30 0000 C CNN -F 2 "" H 4050 4250 60 0000 C CNN -F 3 "" H 4050 4250 60 0000 C CNN - 10 4050 4250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CEE4EFB -P 4050 4450 -F 0 "U1" H 4100 4550 30 0000 C CNN -F 1 "PORT" H 4050 4450 30 0000 C CNN -F 2 "" H 4050 4450 60 0000 C CNN -F 3 "" H 4050 4450 60 0000 C CNN - 11 4050 4450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CEE4F01 -P 4050 4750 -F 0 "U1" H 4100 4850 30 0000 C CNN -F 1 "PORT" H 4050 4750 30 0000 C CNN -F 2 "" H 4050 4750 60 0000 C CNN -F 3 "" H 4050 4750 60 0000 C CNN - 12 4050 4750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CEE4F07 -P 7100 4250 -F 0 "U1" H 7150 4350 30 0000 C CNN -F 1 "PORT" H 7100 4250 30 0000 C CNN -F 2 "" H 7100 4250 60 0000 C CNN -F 3 "" H 7100 4250 60 0000 C CNN - 13 7100 4250 - -1 0 0 1 -$EndComp -Wire Wire Line - 4250 4000 4450 4000 -Wire Wire Line - 4300 4250 4300 4100 -Wire Wire Line - 4300 4100 4450 4100 -Wire Wire Line - 4300 4450 4450 4450 -Wire Wire Line - 4450 4450 4450 4550 -Wire Wire Line - 4300 4750 4300 4650 -Wire Wire Line - 4300 4650 4450 4650 -Wire Wire Line - 6850 4250 6600 4250 -$Comp -L PORT U1 -U 6 1 5CEE51A5 -P 6300 5350 -F 0 "U1" H 6350 5450 30 0000 C CNN -F 1 "PORT" H 6300 5350 30 0000 C CNN -F 2 "" H 6300 5350 60 0000 C CNN -F 3 "" H 6300 5350 60 0000 C CNN - 6 6300 5350 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 7 1 5CEE522C -P 6300 5550 -F 0 "U1" H 6350 5650 30 0000 C CNN -F 1 "PORT" H 6300 5550 30 0000 C CNN -F 2 "" H 6300 5550 60 0000 C CNN -F 3 "" H 6300 5550 60 0000 C CNN - 7 6300 5550 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CEE5276 -P 6300 5800 -F 0 "U1" H 6350 5900 30 0000 C CNN -F 1 "PORT" H 6300 5800 30 0000 C CNN -F 2 "" H 6300 5800 60 0000 C CNN -F 3 "" H 6300 5800 60 0000 C CNN - 8 6300 5800 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CEE52C5 -P 6300 6000 -F 0 "U1" H 6350 6100 30 0000 C CNN -F 1 "PORT" H 6300 6000 30 0000 C CNN -F 2 "" H 6300 6000 60 0000 C CNN -F 3 "" H 6300 6000 60 0000 C CNN - 14 6300 6000 - -1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4002/4002.sub b/src/SubcircuitLibrary/4002/4002.sub deleted file mode 100644 index b9726625..00000000 --- a/src/SubcircuitLibrary/4002/4002.sub +++ /dev/null @@ -1,30 +0,0 @@ -* Subcircuit 4002 -.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? -* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir -* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or -* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor -* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or -* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or -* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor -a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 -a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6 -a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 -a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 -a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4002
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml deleted file mode 100644 index 75360e5e..00000000 --- a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4002/analysis b/src/SubcircuitLibrary/4002/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4002/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/4012-cache.lib b/src/SubcircuitLibrary/4012/4012-cache.lib deleted file mode 100644 index ea0d2d70..00000000 --- a/src/SubcircuitLibrary/4012/4012-cache.lib +++ /dev/null @@ -1,75 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4012/4012.cir b/src/SubcircuitLibrary/4012/4012.cir deleted file mode 100644 index a88a9da4..00000000 --- a/src/SubcircuitLibrary/4012/4012.cir +++ /dev/null @@ -1,19 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter -U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT -U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and -U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and -U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and -U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and -U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and -U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and - -.end diff --git a/src/SubcircuitLibrary/4012/4012.cir.out b/src/SubcircuitLibrary/4012/4012.cir.out deleted file mode 100644 index c43dda8c..00000000 --- a/src/SubcircuitLibrary/4012/4012.cir.out +++ /dev/null @@ -1,44 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir - -* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter -* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and -* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and -* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and -* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and -* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and -* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and -a1 net-_u6-pad3_ net-_u1-pad1_ u8 -a2 net-_u7-pad3_ net-_u1-pad13_ u9 -a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 -a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 -a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 -a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 -a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 -a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4012/4012.pro b/src/SubcircuitLibrary/4012/4012.pro deleted file mode 100644 index 0f76f4bb..00000000 --- a/src/SubcircuitLibrary/4012/4012.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=06/01/19 13:10:32 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_Sources -LibName10=eSim_User -LibName11=eSim_Subckt diff --git a/src/SubcircuitLibrary/4012/4012.sch b/src/SubcircuitLibrary/4012/4012.sch deleted file mode 100644 index b3320871..00000000 --- a/src/SubcircuitLibrary/4012/4012.sch +++ /dev/null @@ -1,342 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:4012-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 3350 2600 2550 2600 -Wire Wire Line - 3350 2700 3150 2700 -Wire Wire Line - 3150 2700 3150 2850 -Wire Wire Line - 3150 2850 2550 2850 -Wire Wire Line - 3350 3200 3150 3200 -Wire Wire Line - 3150 3200 3150 3100 -Wire Wire Line - 3150 3100 2550 3100 -Wire Wire Line - 3350 3300 2550 3300 -Wire Wire Line - 5200 2950 5500 2950 -$Comp -L d_inverter U8 -U 1 1 5CEE55AB -P 5800 2950 -F 0 "U8" H 5800 2850 60 0000 C CNN -F 1 "d_inverter" H 5800 3100 60 0000 C CNN -F 2 "" H 5850 2900 60 0000 C CNN -F 3 "" H 5850 2900 60 0000 C CNN - 1 5800 2950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6100 2950 6500 2950 -Wire Wire Line - 3400 3950 2600 3950 -Wire Wire Line - 3400 4050 3200 4050 -Wire Wire Line - 3200 4050 3200 4200 -Wire Wire Line - 3200 4200 2600 4200 -Wire Wire Line - 3400 4550 3200 4550 -Wire Wire Line - 3200 4550 3200 4450 -Wire Wire Line - 3200 4450 2600 4450 -Wire Wire Line - 3400 4650 2600 4650 -Wire Wire Line - 5250 4300 5550 4300 -$Comp -L d_inverter U9 -U 1 1 5CEE5715 -P 5850 4300 -F 0 "U9" H 5850 4200 60 0000 C CNN -F 1 "d_inverter" H 5850 4450 60 0000 C CNN -F 2 "" H 5900 4250 60 0000 C CNN -F 3 "" H 5900 4250 60 0000 C CNN - 1 5850 4300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6150 4300 6550 4300 -$Comp -L PORT U1 -U 2 1 5CEE57D6 -P 2300 2600 -F 0 "U1" H 2350 2700 30 0000 C CNN -F 1 "PORT" H 2300 2600 30 0000 C CNN -F 2 "" H 2300 2600 60 0000 C CNN -F 3 "" H 2300 2600 60 0000 C CNN - 2 2300 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CEE587B -P 2300 2850 -F 0 "U1" H 2350 2950 30 0000 C CNN -F 1 "PORT" H 2300 2850 30 0000 C CNN -F 2 "" H 2300 2850 60 0000 C CNN -F 3 "" H 2300 2850 60 0000 C CNN - 3 2300 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CEE58AF -P 2300 3100 -F 0 "U1" H 2350 3200 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN -F 2 "" H 2300 3100 60 0000 C CNN -F 3 "" H 2300 3100 60 0000 C CNN - 4 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CEE58E6 -P 6800 4300 -F 0 "U1" H 6850 4400 30 0000 C CNN -F 1 "PORT" H 6800 4300 30 0000 C CNN -F 2 "" H 6800 4300 60 0000 C CNN -F 3 "" H 6800 4300 60 0000 C CNN - 13 6800 4300 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CEE5922 -P 2300 3300 -AR Path="/5CEE58E6" Ref="U1" Part="1" -AR Path="/5CEE5922" Ref="U1" Part="5" -F 0 "U1" H 2350 3400 30 0000 C CNN -F 1 "PORT" H 2300 3300 30 0000 C CNN -F 2 "" H 2300 3300 60 0000 C CNN -F 3 "" H 2300 3300 60 0000 C CNN - 5 2300 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5CEE596F -P 2350 3950 -AR Path="/5CEE5922" Ref="U1" Part="5" -AR Path="/5CEE596F" Ref="U1" Part="9" -F 0 "U1" H 2400 4050 30 0000 C CNN -F 1 "PORT" H 2350 3950 30 0000 C CNN -F 2 "" H 2350 3950 60 0000 C CNN -F 3 "" H 2350 3950 60 0000 C CNN - 9 2350 3950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CEE59AF -P 2350 4200 -AR Path="/5CEE596F" Ref="U1" Part="6" -AR Path="/5CEE59AF" Ref="U1" Part="10" -F 0 "U1" H 2400 4300 30 0000 C CNN -F 1 "PORT" H 2350 4200 30 0000 C CNN -F 2 "" H 2350 4200 60 0000 C CNN -F 3 "" H 2350 4200 60 0000 C CNN - 10 2350 4200 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CEE59F6 -P 2350 4450 -AR Path="/5CEE59AF" Ref="U1" Part="7" -AR Path="/5CEE59F6" Ref="U1" Part="11" -F 0 "U1" H 2400 4550 30 0000 C CNN -F 1 "PORT" H 2350 4450 30 0000 C CNN -F 2 "" H 2350 4450 60 0000 C CNN -F 3 "" H 2350 4450 60 0000 C CNN - 11 2350 4450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CEE5A6A -P 2350 4650 -AR Path="/5CEE59F6" Ref="U1" Part="8" -AR Path="/5CEE5A6A" Ref="U1" Part="12" -F 0 "U1" H 2400 4750 30 0000 C CNN -F 1 "PORT" H 2350 4650 30 0000 C CNN -F 2 "" H 2350 4650 60 0000 C CNN -F 3 "" H 2350 4650 60 0000 C CNN - 12 2350 4650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CEE5BF8 -P 6750 2950 -AR Path="/5CEE5A6A" Ref="U1" Part="9" -AR Path="/5CEE5BF8" Ref="U1" Part="1" -F 0 "U1" H 6800 3050 30 0000 C CNN -F 1 "PORT" H 6750 2950 30 0000 C CNN -F 2 "" H 6750 2950 60 0000 C CNN -F 3 "" H 6750 2950 60 0000 C CNN - 1 6750 2950 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CEE5C72 -P 7850 1450 -F 0 "U1" H 7900 1550 30 0000 C CNN -F 1 "PORT" H 7850 1450 30 0000 C CNN -F 2 "" H 7850 1450 60 0000 C CNN -F 3 "" H 7850 1450 60 0000 C CNN - 6 7850 1450 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 7 1 5CEE5D23 -P 7850 1700 -F 0 "U1" H 7900 1800 30 0000 C CNN -F 1 "PORT" H 7850 1700 30 0000 C CNN -F 2 "" H 7850 1700 60 0000 C CNN -F 3 "" H 7850 1700 60 0000 C CNN - 7 7850 1700 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CEE5D75 -P 7850 1950 -F 0 "U1" H 7900 2050 30 0000 C CNN -F 1 "PORT" H 7850 1950 30 0000 C CNN -F 2 "" H 7850 1950 60 0000 C CNN -F 3 "" H 7850 1950 60 0000 C CNN - 14 7850 1950 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CEE5DCA -P 7850 2250 -F 0 "U1" H 7900 2350 30 0000 C CNN -F 1 "PORT" H 7850 2250 30 0000 C CNN -F 2 "" H 7850 2250 60 0000 C CNN -F 3 "" H 7850 2250 60 0000 C CNN - 8 7850 2250 - -1 0 0 1 -$EndComp -NoConn ~ 7600 1450 -NoConn ~ 7600 1700 -NoConn ~ 7600 1950 -NoConn ~ 7600 2250 -$Comp -L d_and U4 -U 1 1 5CEE56F6 -P 3850 4050 -F 0 "U4" H 3850 4050 60 0000 C CNN -F 1 "d_and" H 3900 4150 60 0000 C CNN -F 2 "" H 3850 4050 60 0000 C CNN -F 3 "" H 3850 4050 60 0000 C CNN - 1 3850 4050 - 1 0 0 -1 -$EndComp -$Comp -L d_and U5 -U 1 1 5CEE56FC -P 3850 4650 -F 0 "U5" H 3850 4650 60 0000 C CNN -F 1 "d_and" H 3900 4750 60 0000 C CNN -F 2 "" H 3850 4650 60 0000 C CNN -F 3 "" H 3850 4650 60 0000 C CNN - 1 3850 4650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4350 4600 4300 4600 -Wire Wire Line - 4350 4350 4350 4600 -Wire Wire Line - 4350 4000 4350 4250 -Wire Wire Line - 4300 4000 4350 4000 -$Comp -L d_and U7 -U 1 1 5CEE5702 -P 4800 4350 -F 0 "U7" H 4800 4350 60 0000 C CNN -F 1 "d_and" H 4850 4450 60 0000 C CNN -F 2 "" H 4800 4350 60 0000 C CNN -F 3 "" H 4800 4350 60 0000 C CNN - 1 4800 4350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4250 2650 4300 2650 -Wire Wire Line - 4300 3250 4250 3250 -Wire Wire Line - 4300 2650 4300 2900 -Wire Wire Line - 4300 3000 4300 3250 -$Comp -L d_and U6 -U 1 1 5CEE5432 -P 4750 3000 -F 0 "U6" H 4750 3000 60 0000 C CNN -F 1 "d_and" H 4800 3100 60 0000 C CNN -F 2 "" H 4750 3000 60 0000 C CNN -F 3 "" H 4750 3000 60 0000 C CNN - 1 4750 3000 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5CEE540C -P 3800 3300 -F 0 "U3" H 3800 3300 60 0000 C CNN -F 1 "d_and" H 3850 3400 60 0000 C CNN -F 2 "" H 3800 3300 60 0000 C CNN -F 3 "" H 3800 3300 60 0000 C CNN - 1 3800 3300 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5CEE53DC -P 3800 2700 -F 0 "U2" H 3800 2700 60 0000 C CNN -F 1 "d_and" H 3850 2800 60 0000 C CNN -F 2 "" H 3800 2700 60 0000 C CNN -F 3 "" H 3800 2700 60 0000 C CNN - 1 3800 2700 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4012/4012.sub b/src/SubcircuitLibrary/4012/4012.sub deleted file mode 100644 index 65263f03..00000000 --- a/src/SubcircuitLibrary/4012/4012.sub +++ /dev/null @@ -1,38 +0,0 @@ -* Subcircuit 4012 -.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? -* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir -* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter -* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter -* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and -* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and -* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and -* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and -* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and -* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and -a1 net-_u6-pad3_ net-_u1-pad1_ u8 -a2 net-_u7-pad3_ net-_u1-pad13_ u9 -a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4 -a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5 -a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 -a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 -a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3 -a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4012
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml b/src/SubcircuitLibrary/4012/4012_Previous_Values.xml deleted file mode 100644 index 4e7e73b2..00000000 --- a/src/SubcircuitLibrary/4012/4012_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4012/analysis b/src/SubcircuitLibrary/4012/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4012/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/4017-cache.lib b/src/SubcircuitLibrary/4017/4017-cache.lib deleted file mode 100644 index efa6746f..00000000 --- a/src/SubcircuitLibrary/4017/4017-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_dff -# -DEF d_dff U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_dff" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 350 450 -350 -400 0 1 0 N -X Din 1 -550 350 200 R 50 50 1 1 I -X Clk 2 -550 -300 200 R 50 50 1 1 I C -X Set 3 0 650 200 D 50 50 1 1 I -X Reset 4 0 -600 200 U 50 50 1 1 I -X Dout 5 550 350 200 L 50 50 1 1 O -X Ndout 6 550 -300 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4017/4017.cir b/src/SubcircuitLibrary/4017/4017.cir deleted file mode 100644 index 67ac9971..00000000 --- a/src/SubcircuitLibrary/4017/4017.cir +++ /dev/null @@ -1,26 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\4017\4017.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/14/19 11:20:59 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U7 Net-_U2-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad1_ Net-_U2-Pad2_ d_dff -U11 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U11-Pad5_ Net-_U10-Pad1_ d_dff -U15 Net-_U11-Pad5_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U12-Pad1_ d_dff -U19 Net-_U10-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_dff -U22 Net-_U12-Pad2_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U2-Pad1_ d_dff -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT -U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad1_ d_and -U3 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U1-Pad2_ d_and -U4 Net-_U11-Pad5_ Net-_U12-Pad1_ Net-_U1-Pad3_ d_and -U5 Net-_U10-Pad2_ Net-_U13-Pad1_ Net-_U1-Pad4_ d_and -U6 Net-_U12-Pad2_ Net-_U2-Pad1_ Net-_U1-Pad5_ d_and -U8 Net-_U13-Pad2_ Net-_U11-Pad1_ Net-_U1-Pad6_ d_and -U9 Net-_U2-Pad2_ Net-_U11-Pad5_ Net-_U1-Pad7_ d_and -U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad8_ d_and -U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U1-Pad9_ d_and -U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad10_ d_and - -.end diff --git a/src/SubcircuitLibrary/4017/4017.cir.out b/src/SubcircuitLibrary/4017/4017.cir.out deleted file mode 100644 index e3a384c5..00000000 --- a/src/SubcircuitLibrary/4017/4017.cir.out +++ /dev/null @@ -1,72 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir - -* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff -* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff -* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff -* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff -* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port -* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and -* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and -* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and -* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and -* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and -* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and -* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and -* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and -* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and -* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and -a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 -a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 -a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 -a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 -a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 -a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 -a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 -a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 -a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 -a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 -a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 -a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 -a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 -a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 -a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 5e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4017/4017.pro b/src/SubcircuitLibrary/4017/4017.pro deleted file mode 100644 index 8cdecd6c..00000000 --- a/src/SubcircuitLibrary/4017/4017.pro +++ /dev/null @@ -1,72 +0,0 @@ -update=Fri Jun 14 10:14:54 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot - diff --git a/src/SubcircuitLibrary/4017/4017.sch b/src/SubcircuitLibrary/4017/4017.sch deleted file mode 100644 index 05549a32..00000000 --- a/src/SubcircuitLibrary/4017/4017.sch +++ /dev/null @@ -1,580 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:4017-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_dff U7 -U 1 1 5C7B9B95 -P 2300 4100 -F 0 "U7" H 2300 4100 60 0000 C CNN -F 1 "d_dff" H 2300 4250 60 0000 C CNN -F 2 "" H 2300 4100 60 0000 C CNN -F 3 "" H 2300 4100 60 0000 C CNN - 1 2300 4100 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U11 -U 1 1 5C7B9CEE -P 3700 4100 -F 0 "U11" H 3700 4100 60 0000 C CNN -F 1 "d_dff" H 3700 4250 60 0000 C CNN -F 2 "" H 3700 4100 60 0000 C CNN -F 3 "" H 3700 4100 60 0000 C CNN - 1 3700 4100 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U15 -U 1 1 5C7B9D3E -P 5150 4100 -F 0 "U15" H 5150 4100 60 0000 C CNN -F 1 "d_dff" H 5150 4250 60 0000 C CNN -F 2 "" H 5150 4100 60 0000 C CNN -F 3 "" H 5150 4100 60 0000 C CNN - 1 5150 4100 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U19 -U 1 1 5C7B9D85 -P 6550 4100 -F 0 "U19" H 6550 4100 60 0000 C CNN -F 1 "d_dff" H 6550 4250 60 0000 C CNN -F 2 "" H 6550 4100 60 0000 C CNN -F 3 "" H 6550 4100 60 0000 C CNN - 1 6550 4100 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U22 -U 1 1 5C7B9DD9 -P 8050 4100 -F 0 "U22" H 8050 4100 60 0000 C CNN -F 1 "d_dff" H 8050 4250 60 0000 C CNN -F 2 "" H 8050 4100 60 0000 C CNN -F 3 "" H 8050 4100 60 0000 C CNN - 1 8050 4100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1750 4400 1500 4400 -Wire Wire Line - 1500 4400 1500 5350 -Wire Wire Line - 1500 5350 7500 5350 -Wire Wire Line - 7500 5350 7500 4400 -Wire Wire Line - 2300 4700 2300 6700 -Wire Wire Line - 2300 4900 8050 4900 -Wire Wire Line - 8050 4900 8050 4700 -Wire Wire Line - 3700 4700 3700 4900 -Connection ~ 3700 4900 -Wire Wire Line - 5150 4700 5150 4900 -Connection ~ 5150 4900 -Wire Wire Line - 6550 4700 6550 4900 -Connection ~ 6550 4900 -Wire Wire Line - 6000 4400 6000 5350 -Connection ~ 6000 5350 -Wire Wire Line - 4600 4400 4600 5350 -Connection ~ 4600 5350 -Wire Wire Line - 3150 4400 3150 5350 -Connection ~ 3150 5350 -Wire Wire Line - 2300 3450 2300 3350 -Wire Wire Line - 1550 3350 8050 3350 -Wire Wire Line - 8050 3350 8050 3450 -Wire Wire Line - 6550 3450 6550 3350 -Connection ~ 6550 3350 -Wire Wire Line - 5150 3450 5150 3350 -Connection ~ 5150 3350 -Wire Wire Line - 3700 3350 3700 3450 -Connection ~ 3700 3350 -Wire Wire Line - 7100 3750 7500 3750 -Wire Wire Line - 5700 3750 6000 3750 -Wire Wire Line - 2850 3750 3150 3750 -Wire Wire Line - 4250 3750 4600 3750 -Wire Wire Line - 4250 4400 4400 4400 -Wire Wire Line - 5700 4400 5850 4400 -Wire Wire Line - 2850 4400 3000 4400 -Wire Wire Line - 2100 2300 2100 3300 -Wire Wire Line - 2100 2500 5800 2500 -Wire Wire Line - 5800 2500 5800 2300 -Wire Wire Line - 2750 2300 2750 3200 -Wire Wire Line - 2750 2550 6350 2550 -Wire Wire Line - 6350 2550 6350 2300 -Wire Wire Line - 3450 2300 3450 3150 -Wire Wire Line - 3450 2600 7000 2600 -Wire Wire Line - 7000 2600 7000 2300 -Wire Wire Line - 4000 2300 4000 3050 -Wire Wire Line - 4000 2650 7700 2650 -Wire Wire Line - 7700 2650 7700 2300 -Wire Wire Line - 2650 2300 2650 3250 -Wire Wire Line - 2650 2700 5350 2700 -Wire Wire Line - 5350 2700 5350 2300 -Wire Wire Line - 3350 2300 3350 3250 -Wire Wire Line - 3350 2750 5900 2750 -Wire Wire Line - 5900 2750 5900 2300 -Wire Wire Line - 3900 2300 3900 3100 -Wire Wire Line - 3900 2800 6450 2800 -Wire Wire Line - 6450 2800 6450 2300 -Wire Wire Line - 4550 2300 4550 3000 -Wire Wire Line - 4550 2850 7100 2850 -Wire Wire Line - 7100 2850 7100 2300 -Wire Wire Line - 5250 2300 5250 2950 -Wire Wire Line - 5250 2900 7800 2900 -Wire Wire Line - 7800 2900 7800 2300 -Wire Wire Line - 2000 2300 2000 2450 -Wire Wire Line - 1750 2450 4650 2450 -Wire Wire Line - 4650 2450 4650 2300 -Wire Wire Line - 1750 2450 1750 3750 -Connection ~ 2000 2450 -Wire Wire Line - 8600 4400 8800 4400 -Wire Wire Line - 8800 4400 8800 6350 -Wire Wire Line - 8800 6350 1350 6350 -Wire Wire Line - 1350 6350 1350 3600 -Wire Wire Line - 1350 3600 1750 3600 -Connection ~ 1750 3600 -Wire Wire Line - 2100 3300 3000 3300 -Wire Wire Line - 3000 3300 3000 4400 -Connection ~ 2900 4400 -Connection ~ 2100 2500 -Connection ~ 2650 2700 -Wire Wire Line - 2650 3250 2950 3250 -Wire Wire Line - 2950 3250 2950 3750 -Connection ~ 2950 3750 -Wire Wire Line - 4400 4400 4400 3200 -Wire Wire Line - 4400 3200 2750 3200 -Connection ~ 2750 2550 -Wire Wire Line - 3350 3250 4250 3250 -Wire Wire Line - 4250 3250 4250 3750 -Connection ~ 3350 2750 -Wire Wire Line - 3450 3150 5850 3150 -Wire Wire Line - 5850 3150 5850 4400 -Connection ~ 5750 4400 -Connection ~ 3450 2600 -Wire Wire Line - 3900 3100 5750 3100 -Wire Wire Line - 5750 3100 5750 3750 -Connection ~ 5750 3750 -Connection ~ 3900 2800 -Wire Wire Line - 4000 3050 7350 3050 -Wire Wire Line - 7350 3050 7350 4400 -Wire Wire Line - 7350 4400 7100 4400 -Connection ~ 4000 2650 -Wire Wire Line - 4550 3000 7200 3000 -Wire Wire Line - 7200 3000 7200 3750 -Connection ~ 7200 3750 -Connection ~ 4550 2850 -Wire Wire Line - 5250 2950 8700 2950 -Wire Wire Line - 8700 2950 8700 3750 -Wire Wire Line - 8700 3750 8600 3750 -Connection ~ 5250 2900 -Wire Wire Line - 2300 6700 1100 6700 -Connection ~ 2300 4900 -Wire Wire Line - 1550 3350 1550 5150 -Wire Wire Line - 1550 5150 2300 5150 -Connection ~ 2300 5150 -Connection ~ 2300 3350 -Wire Wire Line - 2550 5350 2550 6650 -Wire Wire Line - 2550 6650 2950 6650 -Wire Wire Line - 2950 6650 2950 7200 -Wire Wire Line - 2950 7200 2700 7200 -Connection ~ 2550 5350 -$Comp -L PORT U1 -U 6 1 5C7C1634 -P 5300 1000 -F 0 "U1" H 5350 1100 30 0000 C CNN -F 1 "PORT" H 5300 1000 30 0000 C CNN -F 2 "" H 5300 1000 60 0000 C CNN -F 3 "" H 5300 1000 60 0000 C CNN - 6 5300 1000 - 0 1 1 0 -$EndComp -Wire Wire Line - 5300 1250 5300 1400 -$Comp -L PORT U1 -U 2 1 5C7BC7B8 -P 2700 1000 -F 0 "U1" H 2750 1100 30 0000 C CNN -F 1 "PORT" H 2700 1000 30 0000 C CNN -F 2 "" H 2700 1000 60 0000 C CNN -F 3 "" H 2700 1000 60 0000 C CNN - 2 2700 1000 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 1 1 5C7BC953 -P 2050 950 -F 0 "U1" H 2100 1050 30 0000 C CNN -F 1 "PORT" H 2050 950 30 0000 C CNN -F 2 "" H 2050 950 60 0000 C CNN -F 3 "" H 2050 950 60 0000 C CNN - 1 2050 950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 3 1 5C7BC9D8 -P 3400 950 -F 0 "U1" H 3450 1050 30 0000 C CNN -F 1 "PORT" H 3400 950 30 0000 C CNN -F 2 "" H 3400 950 60 0000 C CNN -F 3 "" H 3400 950 60 0000 C CNN - 3 3400 950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 7 1 5C7BCAA7 -P 5850 950 -F 0 "U1" H 5900 1050 30 0000 C CNN -F 1 "PORT" H 5850 950 30 0000 C CNN -F 2 "" H 5850 950 60 0000 C CNN -F 3 "" H 5850 950 60 0000 C CNN - 7 5850 950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 8 1 5C7BCB20 -P 6400 1000 -F 0 "U1" H 6450 1100 30 0000 C CNN -F 1 "PORT" H 6400 1000 30 0000 C CNN -F 2 "" H 6400 1000 60 0000 C CNN -F 3 "" H 6400 1000 60 0000 C CNN - 8 6400 1000 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 4 1 5C7BCBB1 -P 3950 950 -F 0 "U1" H 4000 1050 30 0000 C CNN -F 1 "PORT" H 3950 950 30 0000 C CNN -F 2 "" H 3950 950 60 0000 C CNN -F 3 "" H 3950 950 60 0000 C CNN - 4 3950 950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 9 1 5C7BCF23 -P 7050 1000 -F 0 "U1" H 7100 1100 30 0000 C CNN -F 1 "PORT" H 7050 1000 30 0000 C CNN -F 2 "" H 7050 1000 60 0000 C CNN -F 3 "" H 7050 1000 60 0000 C CNN - 9 7050 1000 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 5 1 5C7BCFC0 -P 4600 950 -F 0 "U1" H 4650 1050 30 0000 C CNN -F 1 "PORT" H 4600 950 30 0000 C CNN -F 2 "" H 4600 950 60 0000 C CNN -F 3 "" H 4600 950 60 0000 C CNN - 5 4600 950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 10 1 5C7BD0A5 -P 7750 1000 -F 0 "U1" H 7800 1100 30 0000 C CNN -F 1 "PORT" H 7750 1000 30 0000 C CNN -F 2 "" H 7750 1000 60 0000 C CNN -F 3 "" H 7750 1000 60 0000 C CNN - 10 7750 1000 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 11 1 5C7BD5BB -P 850 6700 -F 0 "U1" H 900 6800 30 0000 C CNN -F 1 "PORT" H 850 6700 30 0000 C CNN -F 2 "" H 850 6700 60 0000 C CNN -F 3 "" H 850 6700 60 0000 C CNN - 11 850 6700 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2050 1200 2050 1400 -Wire Wire Line - 2700 1250 2700 1400 -Wire Wire Line - 3400 1200 3400 1400 -Wire Wire Line - 3950 1200 3950 1400 -Wire Wire Line - 4600 1200 4600 1400 -Wire Wire Line - 5850 1200 5850 1400 -Wire Wire Line - 6400 1250 6400 1400 -Wire Wire Line - 7050 1250 7050 1400 -Wire Wire Line - 7750 1250 7750 1400 -$Comp -L PORT U1 -U 12 1 5C8A0119 -P 2450 7200 -F 0 "U1" H 2500 7300 30 0000 C CNN -F 1 "PORT" H 2450 7200 30 0000 C CNN -F 2 "" H 2450 7200 60 0000 C CNN -F 3 "" H 2450 7200 60 0000 C CNN - 12 2450 7200 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C89F7BC -P 2100 1850 -F 0 "U2" H 2100 1850 60 0000 C CNN -F 1 "d_and" H 2150 1950 60 0000 C CNN -F 2 "" H 2100 1850 60 0000 C CNN -F 3 "" H 2100 1850 60 0000 C CNN - 1 2100 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U3 -U 1 1 5C89FA46 -P 2750 1850 -F 0 "U3" H 2750 1850 60 0000 C CNN -F 1 "d_and" H 2800 1950 60 0000 C CNN -F 2 "" H 2750 1850 60 0000 C CNN -F 3 "" H 2750 1850 60 0000 C CNN - 1 2750 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U4 -U 1 1 5C89FAD5 -P 3450 1850 -F 0 "U4" H 3450 1850 60 0000 C CNN -F 1 "d_and" H 3500 1950 60 0000 C CNN -F 2 "" H 3450 1850 60 0000 C CNN -F 3 "" H 3450 1850 60 0000 C CNN - 1 3450 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U5 -U 1 1 5C89FB62 -P 4000 1850 -F 0 "U5" H 4000 1850 60 0000 C CNN -F 1 "d_and" H 4050 1950 60 0000 C CNN -F 2 "" H 4000 1850 60 0000 C CNN -F 3 "" H 4000 1850 60 0000 C CNN - 1 4000 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U6 -U 1 1 5C89FEBF -P 4650 1850 -F 0 "U6" H 4650 1850 60 0000 C CNN -F 1 "d_and" H 4700 1950 60 0000 C CNN -F 2 "" H 4650 1850 60 0000 C CNN -F 3 "" H 4650 1850 60 0000 C CNN - 1 4650 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U8 -U 1 1 5C89FF2C -P 5350 1850 -F 0 "U8" H 5350 1850 60 0000 C CNN -F 1 "d_and" H 5400 1950 60 0000 C CNN -F 2 "" H 5350 1850 60 0000 C CNN -F 3 "" H 5350 1850 60 0000 C CNN - 1 5350 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U9 -U 1 1 5C89FF96 -P 5900 1850 -F 0 "U9" H 5900 1850 60 0000 C CNN -F 1 "d_and" H 5950 1950 60 0000 C CNN -F 2 "" H 5900 1850 60 0000 C CNN -F 3 "" H 5900 1850 60 0000 C CNN - 1 5900 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U10 -U 1 1 5C8A066D -P 6450 1850 -F 0 "U10" H 6450 1850 60 0000 C CNN -F 1 "d_and" H 6500 1950 60 0000 C CNN -F 2 "" H 6450 1850 60 0000 C CNN -F 3 "" H 6450 1850 60 0000 C CNN - 1 6450 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U12 -U 1 1 5C8A06D8 -P 7100 1850 -F 0 "U12" H 7100 1850 60 0000 C CNN -F 1 "d_and" H 7150 1950 60 0000 C CNN -F 2 "" H 7100 1850 60 0000 C CNN -F 3 "" H 7100 1850 60 0000 C CNN - 1 7100 1850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U13 -U 1 1 5C8A12F5 -P 7800 1850 -F 0 "U13" H 7800 1850 60 0000 C CNN -F 1 "d_and" H 7850 1950 60 0000 C CNN -F 2 "" H 7800 1850 60 0000 C CNN -F 3 "" H 7800 1850 60 0000 C CNN - 1 7800 1850 - 0 -1 -1 0 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4017/4017.sub b/src/SubcircuitLibrary/4017/4017.sub deleted file mode 100644 index 2e27ab61..00000000 --- a/src/SubcircuitLibrary/4017/4017.sub +++ /dev/null @@ -1,66 +0,0 @@ -* Subcircuit 4017 -.subckt 4017 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ -* c:\esim\esim\src\subcircuitlibrary\4017\4017.cir -* u7 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ d_dff -* u11 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ d_dff -* u15 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ d_dff -* u19 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ d_dff -* u22 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ d_dff -* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_and -* u3 net-_u11-pad1_ net-_u10-pad1_ net-_u1-pad2_ d_and -* u4 net-_u11-pad5_ net-_u12-pad1_ net-_u1-pad3_ d_and -* u5 net-_u10-pad2_ net-_u13-pad1_ net-_u1-pad4_ d_and -* u6 net-_u12-pad2_ net-_u2-pad1_ net-_u1-pad5_ d_and -* u8 net-_u13-pad2_ net-_u11-pad1_ net-_u1-pad6_ d_and -* u9 net-_u2-pad2_ net-_u11-pad5_ net-_u1-pad7_ d_and -* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad8_ d_and -* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u1-pad9_ d_and -* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u1-pad10_ d_and -a1 net-_u2-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ net-_u2-pad2_ u7 -a2 net-_u11-pad1_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad5_ net-_u10-pad1_ u11 -a3 net-_u11-pad5_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad2_ net-_u12-pad1_ u15 -a4 net-_u10-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u12-pad2_ net-_u13-pad1_ u19 -a5 net-_u12-pad2_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad2_ net-_u2-pad1_ u22 -a6 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2 -a7 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u1-pad2_ u3 -a8 [net-_u11-pad5_ net-_u12-pad1_ ] net-_u1-pad3_ u4 -a9 [net-_u10-pad2_ net-_u13-pad1_ ] net-_u1-pad4_ u5 -a10 [net-_u12-pad2_ net-_u2-pad1_ ] net-_u1-pad5_ u6 -a11 [net-_u13-pad2_ net-_u11-pad1_ ] net-_u1-pad6_ u8 -a12 [net-_u2-pad2_ net-_u11-pad5_ ] net-_u1-pad7_ u9 -a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad8_ u10 -a14 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u1-pad9_ u12 -a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u1-pad10_ u13 -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u7 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u11 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u19 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_dff, NgSpice Name: d_dff -.model u22 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4017
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml b/src/SubcircuitLibrary/4017/4017_Previous_Values.xml deleted file mode 100644 index 9dfd97a3..00000000 --- a/src/SubcircuitLibrary/4017/4017_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u7 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u7><u11 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u11><u15 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u19 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u22><u9 name="type">d_nand<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u9><u13 name="type">d_nor<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u13><u5 name="type">d_nand<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u5><u8 name="type">d_nand<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_nand<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_nand<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u12><u14 name="type">d_nand<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_nand<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_nand<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_nand<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u18><u20 name="type">d_nand<field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_nand<field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /></u21><u4 name="type">d_inverter<field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /></u6><u23 name="type">d_inverter<field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /></u23><u24 name="type">d_buffer<field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /></u24><u2 name="type">d_and<field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_and<field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_and<field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/D.lib b/src/SubcircuitLibrary/4017/D.lib deleted file mode 100644 index adbdfb35..00000000 --- a/src/SubcircuitLibrary/4017/D.lib +++ /dev/null @@ -1,11 +0,0 @@ -.MODEL 1N4148 D( -+ Vj=1 -+ Cjo=1.700E-12 -+ Rs=4.755E-01 -+ Is=2.495E-09 -+ M=1.959E-01 -+ N=1.679E+00 -+ Bv=1.000E+02 -+ tt=3.030E-09 -+ Ibv=1.000E-04 -)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4017/analysis b/src/SubcircuitLibrary/4017/analysis deleted file mode 100644 index 40bd9d97..00000000 --- a/src/SubcircuitLibrary/4017/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 5e-03 100e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/3_and-cache.lib b/src/SubcircuitLibrary/4023/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/4023/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4023/3_and.cir b/src/SubcircuitLibrary/4023/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/4023/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/4023/3_and.cir.out b/src/SubcircuitLibrary/4023/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/4023/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4023/3_and.pro b/src/SubcircuitLibrary/4023/3_and.pro deleted file mode 100644 index 76df4655..00000000 --- a/src/SubcircuitLibrary/4023/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4023/3_and.sch b/src/SubcircuitLibrary/4023/3_and.sch deleted file mode 100644 index d6ac89f9..00000000 --- a/src/SubcircuitLibrary/4023/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:3_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -Text Notes 3500 2600 0 60 ~ 12 -in1 -Text Notes 3450 2800 0 60 ~ 12 -in2\n -Text Notes 3500 3100 0 60 ~ 12 -in3 -Text Notes 6100 2850 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/3_and.sub b/src/SubcircuitLibrary/4023/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/4023/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/4023/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/4023-cache.lib b/src/SubcircuitLibrary/4023/4023-cache.lib deleted file mode 100644 index c989d8c7..00000000 --- a/src/SubcircuitLibrary/4023/4023-cache.lib +++ /dev/null @@ -1,76 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4023/4023.cir b/src/SubcircuitLibrary/4023/4023.cir deleted file mode 100644 index 6aad9b84..00000000 --- a/src/SubcircuitLibrary/4023/4023.cir +++ /dev/null @@ -1,17 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and -U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT -X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and -U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and -U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter - -.end diff --git a/src/SubcircuitLibrary/4023/4023.cir.out b/src/SubcircuitLibrary/4023/4023.cir.out deleted file mode 100644 index 7f48d16f..00000000 --- a/src/SubcircuitLibrary/4023/4023.cir.out +++ /dev/null @@ -1,28 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir - -.include 3_and.sub -x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and -* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter -a1 net-_u4-pad1_ net-_u1-pad10_ u4 -a2 net-_u3-pad1_ net-_u1-pad6_ u3 -a3 net-_u2-pad1_ net-_u1-pad9_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4023/4023.pro b/src/SubcircuitLibrary/4023/4023.pro deleted file mode 100644 index 5a5ce355..00000000 --- a/src/SubcircuitLibrary/4023/4023.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:32:35 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4023/4023.sch b/src/SubcircuitLibrary/4023/4023.sch deleted file mode 100644 index 57dd7868..00000000 --- a/src/SubcircuitLibrary/4023/4023.sch +++ /dev/null @@ -1,309 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X3 -U 1 1 5CF0FA82 -P 4800 2500 -F 0 "X3" H 4900 2450 60 0000 C CNN -F 1 "3_and" H 4950 2650 60 0000 C CNN -F 2 "" H 4800 2500 60 0000 C CNN -F 3 "" H 4800 2500 60 0000 C CNN - 1 4800 2500 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5CF0FB13 -P 6150 2450 -F 0 "U4" H 6150 2350 60 0000 C CNN -F 1 "d_inverter" H 6150 2600 60 0000 C CNN -F 2 "" H 6200 2400 60 0000 C CNN -F 3 "" H 6200 2400 60 0000 C CNN - 1 6150 2450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CF0FB34 -P 3100 1950 -F 0 "U1" H 3150 2050 30 0000 C CNN -F 1 "PORT" H 3100 1950 30 0000 C CNN -F 2 "" H 3100 1950 60 0000 C CNN -F 3 "" H 3100 1950 60 0000 C CNN - 11 3100 1950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CF0FB90 -P 3100 2350 -F 0 "U1" H 3150 2450 30 0000 C CNN -F 1 "PORT" H 3100 2350 30 0000 C CNN -F 2 "" H 3100 2350 60 0000 C CNN -F 3 "" H 3100 2350 60 0000 C CNN - 12 3100 2350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CF0FBB8 -P 3100 2750 -F 0 "U1" H 3150 2850 30 0000 C CNN -F 1 "PORT" H 3100 2750 30 0000 C CNN -F 2 "" H 3100 2750 60 0000 C CNN -F 3 "" H 3100 2750 60 0000 C CNN - 13 3100 2750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CF0FBED -P 7800 2450 -F 0 "U1" H 7850 2550 30 0000 C CNN -F 1 "PORT" H 7800 2450 30 0000 C CNN -F 2 "" H 7800 2450 60 0000 C CNN -F 3 "" H 7800 2450 60 0000 C CNN - 10 7800 2450 - -1 0 0 1 -$EndComp -Wire Wire Line - 7550 2450 6450 2450 -Wire Wire Line - 5850 2450 5300 2450 -Wire Wire Line - 4450 2350 4450 1950 -Wire Wire Line - 4450 1950 3350 1950 -Wire Wire Line - 4450 2450 4100 2450 -Wire Wire Line - 4100 2450 4100 2350 -Wire Wire Line - 4100 2350 3350 2350 -Wire Wire Line - 3350 2750 3950 2750 -Wire Wire Line - 3950 2750 3950 2550 -Wire Wire Line - 3950 2550 4450 2550 -$Comp -L 3_and X2 -U 1 1 5CF0FF35 -P 4700 3800 -F 0 "X2" H 4800 3750 60 0000 C CNN -F 1 "3_and" H 4850 3950 60 0000 C CNN -F 2 "" H 4700 3800 60 0000 C CNN -F 3 "" H 4700 3800 60 0000 C CNN - 1 4700 3800 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5CF0FF3B -P 6050 3750 -F 0 "U3" H 6050 3650 60 0000 C CNN -F 1 "d_inverter" H 6050 3900 60 0000 C CNN -F 2 "" H 6100 3700 60 0000 C CNN -F 3 "" H 6100 3700 60 0000 C CNN - 1 6050 3750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CF0FF41 -P 3000 3250 -F 0 "U1" H 3050 3350 30 0000 C CNN -F 1 "PORT" H 3000 3250 30 0000 C CNN -F 2 "" H 3000 3250 60 0000 C CNN -F 3 "" H 3000 3250 60 0000 C CNN - 4 3000 3250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CF0FF47 -P 3000 3650 -F 0 "U1" H 3050 3750 30 0000 C CNN -F 1 "PORT" H 3000 3650 30 0000 C CNN -F 2 "" H 3000 3650 60 0000 C CNN -F 3 "" H 3000 3650 60 0000 C CNN - 5 3000 3650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CF0FF4D -P 3000 4050 -F 0 "U1" H 3050 4150 30 0000 C CNN -F 1 "PORT" H 3000 4050 30 0000 C CNN -F 2 "" H 3000 4050 60 0000 C CNN -F 3 "" H 3000 4050 60 0000 C CNN - 3 3000 4050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CF0FF53 -P 7700 3750 -F 0 "U1" H 7750 3850 30 0000 C CNN -F 1 "PORT" H 7700 3750 30 0000 C CNN -F 2 "" H 7700 3750 60 0000 C CNN -F 3 "" H 7700 3750 60 0000 C CNN - 6 7700 3750 - -1 0 0 1 -$EndComp -Wire Wire Line - 7450 3750 6350 3750 -Wire Wire Line - 5750 3750 5200 3750 -Wire Wire Line - 4350 3650 4350 3250 -Wire Wire Line - 4350 3250 3250 3250 -Wire Wire Line - 4350 3750 4000 3750 -Wire Wire Line - 4000 3750 4000 3650 -Wire Wire Line - 4000 3650 3250 3650 -Wire Wire Line - 3250 4050 3850 4050 -Wire Wire Line - 3850 4050 3850 3850 -Wire Wire Line - 3850 3850 4350 3850 -$Comp -L 3_and X1 -U 1 1 5CF100B9 -P 4650 5100 -F 0 "X1" H 4750 5050 60 0000 C CNN -F 1 "3_and" H 4800 5250 60 0000 C CNN -F 2 "" H 4650 5100 60 0000 C CNN -F 3 "" H 4650 5100 60 0000 C CNN - 1 4650 5100 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U2 -U 1 1 5CF100BF -P 6000 5050 -F 0 "U2" H 6000 4950 60 0000 C CNN -F 1 "d_inverter" H 6000 5200 60 0000 C CNN -F 2 "" H 6050 5000 60 0000 C CNN -F 3 "" H 6050 5000 60 0000 C CNN - 1 6000 5050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CF100C5 -P 2950 4550 -F 0 "U1" H 3000 4650 30 0000 C CNN -F 1 "PORT" H 2950 4550 30 0000 C CNN -F 2 "" H 2950 4550 60 0000 C CNN -F 3 "" H 2950 4550 60 0000 C CNN - 1 2950 4550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5CF100CB -P 2950 4950 -F 0 "U1" H 3000 5050 30 0000 C CNN -F 1 "PORT" H 2950 4950 30 0000 C CNN -F 2 "" H 2950 4950 60 0000 C CNN -F 3 "" H 2950 4950 60 0000 C CNN - 2 2950 4950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CF100D1 -P 2950 5350 -F 0 "U1" H 3000 5450 30 0000 C CNN -F 1 "PORT" H 2950 5350 30 0000 C CNN -F 2 "" H 2950 5350 60 0000 C CNN -F 3 "" H 2950 5350 60 0000 C CNN - 8 2950 5350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5CF100D7 -P 7650 5050 -F 0 "U1" H 7700 5150 30 0000 C CNN -F 1 "PORT" H 7650 5050 30 0000 C CNN -F 2 "" H 7650 5050 60 0000 C CNN -F 3 "" H 7650 5050 60 0000 C CNN - 9 7650 5050 - -1 0 0 1 -$EndComp -Wire Wire Line - 7400 5050 6300 5050 -Wire Wire Line - 5700 5050 5150 5050 -Wire Wire Line - 4300 4950 4300 4550 -Wire Wire Line - 4300 4550 3200 4550 -Wire Wire Line - 4300 5050 3950 5050 -Wire Wire Line - 3950 5050 3950 4950 -Wire Wire Line - 3950 4950 3200 4950 -Wire Wire Line - 3200 5350 3800 5350 -Wire Wire Line - 3800 5350 3800 5150 -Wire Wire Line - 3800 5150 4300 5150 -$Comp -L PORT U1 -U 7 1 5CF101BF -P 9950 3350 -F 0 "U1" H 10000 3450 30 0000 C CNN -F 1 "PORT" H 9950 3350 30 0000 C CNN -F 2 "" H 9950 3350 60 0000 C CNN -F 3 "" H 9950 3350 60 0000 C CNN - 7 9950 3350 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CF1025C -P 9950 3900 -F 0 "U1" H 10000 4000 30 0000 C CNN -F 1 "PORT" H 9950 3900 30 0000 C CNN -F 2 "" H 9950 3900 60 0000 C CNN -F 3 "" H 9950 3900 60 0000 C CNN - 14 9950 3900 - -1 0 0 1 -$EndComp -NoConn ~ 9700 3350 -NoConn ~ 9700 3900 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4023/4023.sub b/src/SubcircuitLibrary/4023/4023.sub deleted file mode 100644 index b953da2e..00000000 --- a/src/SubcircuitLibrary/4023/4023.sub +++ /dev/null @@ -1,22 +0,0 @@ -* Subcircuit 4023 -.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? -* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir -.include 3_and.sub -x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and -* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter -x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter -a1 net-_u4-pad1_ net-_u1-pad10_ u4 -a2 net-_u3-pad1_ net-_u1-pad6_ u3 -a3 net-_u2-pad1_ net-_u1-pad9_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4023
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml b/src/SubcircuitLibrary/4023/4023_Previous_Values.xml deleted file mode 100644 index ad900de2..00000000 --- a/src/SubcircuitLibrary/4023/4023_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4023/analysis b/src/SubcircuitLibrary/4023/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4023/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/4025-cache.lib b/src/SubcircuitLibrary/4025/4025-cache.lib deleted file mode 100644 index dd565db9..00000000 --- a/src/SubcircuitLibrary/4025/4025-cache.lib +++ /dev/null @@ -1,82 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4025/4025.cir b/src/SubcircuitLibrary/4025/4025.cir deleted file mode 100644 index a2431c71..00000000 --- a/src/SubcircuitLibrary/4025/4025.cir +++ /dev/null @@ -1,17 +0,0 @@ -* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4025\4025.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:34:19
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
-U6 Net-_U3-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad6_ d_nor
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
-U4 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U4-Pad3_ d_or
-U7 Net-_U4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad10_ d_nor
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
-U5 Net-_U2-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad9_ d_nor
-
-.end
diff --git a/src/SubcircuitLibrary/4025/4025.cir.out b/src/SubcircuitLibrary/4025/4025.cir.out deleted file mode 100644 index b22d91a3..00000000 --- a/src/SubcircuitLibrary/4025/4025.cir.out +++ /dev/null @@ -1,36 +0,0 @@ -* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
-
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
-* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
-a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
-a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
-a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
-a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4025/4025.pro b/src/SubcircuitLibrary/4025/4025.pro deleted file mode 100644 index 3c05588e..00000000 --- a/src/SubcircuitLibrary/4025/4025.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=05/31/19 09:27:16
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
-LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
-LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
-LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
-LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
-LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice
-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
-LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
-LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/4025/4025.sch b/src/SubcircuitLibrary/4025/4025.sch deleted file mode 100644 index 2a0cb4bc..00000000 --- a/src/SubcircuitLibrary/4025/4025.sch +++ /dev/null @@ -1,302 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:4025-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U3
-U 1 1 5CEE0A15
-P 4850 3000
-F 0 "U3" H 4850 3000 60 0000 C CNN
-F 1 "d_or" H 4850 3100 60 0000 C CNN
-F 2 "" H 4850 3000 60 0000 C CNN
-F 3 "" H 4850 3000 60 0000 C CNN
- 1 4850 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L d_nor U6
-U 1 1 5CEE0AE8
-P 6100 3050
-F 0 "U6" H 6100 3050 60 0000 C CNN
-F 1 "d_nor" H 6150 3150 60 0000 C CNN
-F 2 "" H 6100 3050 60 0000 C CNN
-F 3 "" H 6100 3050 60 0000 C CNN
- 1 6100 3050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CEE0B21
-P 3900 2900
-F 0 "U1" H 3950 3000 30 0000 C CNN
-F 1 "PORT" H 3900 2900 30 0000 C CNN
-F 2 "" H 3900 2900 60 0000 C CNN
-F 3 "" H 3900 2900 60 0000 C CNN
- 3 3900 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CEE0B4F
-P 3900 3150
-F 0 "U1" H 3950 3250 30 0000 C CNN
-F 1 "PORT" H 3900 3150 30 0000 C CNN
-F 2 "" H 3900 3150 60 0000 C CNN
-F 3 "" H 3900 3150 60 0000 C CNN
- 4 3900 3150
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CEE0B87
-P 5200 4450
-F 0 "U1" H 5250 4550 30 0000 C CNN
-F 1 "PORT" H 5200 4450 30 0000 C CNN
-F 2 "" H 5200 4450 60 0000 C CNN
-F 3 "" H 5200 4450 60 0000 C CNN
- 8 5200 4450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CEE0BBA
-P 3900 3500
-F 0 "U1" H 3950 3600 30 0000 C CNN
-F 1 "PORT" H 3900 3500 30 0000 C CNN
-F 2 "" H 3900 3500 60 0000 C CNN
-F 3 "" H 3900 3500 60 0000 C CNN
- 11 3900 3500
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4150 2900 4400 2900
-Wire Wire Line
- 4150 3150 4300 3150
-Wire Wire Line
- 4300 3150 4300 3000
-Wire Wire Line
- 4300 3000 4400 3000
-Wire Wire Line
- 5300 2950 5650 2950
-Wire Wire Line
- 5500 3150 5650 3150
-Wire Wire Line
- 5650 3150 5650 3050
-Wire Wire Line
- 6550 3000 6750 3000
-$Comp
-L d_or U4
-U 1 1 5CEE1CD2
-P 4850 3600
-F 0 "U4" H 4850 3600 60 0000 C CNN
-F 1 "d_or" H 4850 3700 60 0000 C CNN
-F 2 "" H 4850 3600 60 0000 C CNN
-F 3 "" H 4850 3600 60 0000 C CNN
- 1 4850 3600
- 1 0 0 -1
-$EndComp
-$Comp
-L d_nor U7
-U 1 1 5CEE1CD8
-P 6100 3650
-F 0 "U7" H 6100 3650 60 0000 C CNN
-F 1 "d_nor" H 6150 3750 60 0000 C CNN
-F 2 "" H 6100 3650 60 0000 C CNN
-F 3 "" H 6100 3650 60 0000 C CNN
- 1 6100 3650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5CEE1CDE
-P 5250 3150
-F 0 "U1" H 5300 3250 30 0000 C CNN
-F 1 "PORT" H 5250 3150 30 0000 C CNN
-F 2 "" H 5250 3150 60 0000 C CNN
-F 3 "" H 5250 3150 60 0000 C CNN
- 5 5250 3150
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CEE1CE4
-P 7000 3000
-F 0 "U1" H 7050 3100 30 0000 C CNN
-F 1 "PORT" H 7000 3000 30 0000 C CNN
-F 2 "" H 7000 3000 60 0000 C CNN
-F 3 "" H 7000 3000 60 0000 C CNN
- 6 7000 3000
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5CEE1CEA
-P 6950 4300
-F 0 "U1" H 7000 4400 30 0000 C CNN
-F 1 "PORT" H 6950 4300 30 0000 C CNN
-F 2 "" H 6950 4300 60 0000 C CNN
-F 3 "" H 6950 4300 60 0000 C CNN
- 9 6950 4300
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CEE1CF0
-P 3900 3750
-F 0 "U1" H 3950 3850 30 0000 C CNN
-F 1 "PORT" H 3900 3750 30 0000 C CNN
-F 2 "" H 3900 3750 60 0000 C CNN
-F 3 "" H 3900 3750 60 0000 C CNN
- 12 3900 3750
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4150 3500 4400 3500
-Wire Wire Line
- 4150 3750 4300 3750
-Wire Wire Line
- 4300 3750 4300 3600
-Wire Wire Line
- 4300 3600 4400 3600
-Wire Wire Line
- 5300 3550 5650 3550
-Wire Wire Line
- 5500 3750 5650 3750
-Wire Wire Line
- 5650 3750 5650 3650
-Wire Wire Line
- 6550 3600 6750 3600
-$Comp
-L d_or U2
-U 1 1 5CEE1F80
-P 4800 4300
-F 0 "U2" H 4800 4300 60 0000 C CNN
-F 1 "d_or" H 4800 4400 60 0000 C CNN
-F 2 "" H 4800 4300 60 0000 C CNN
-F 3 "" H 4800 4300 60 0000 C CNN
- 1 4800 4300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_nor U5
-U 1 1 5CEE1F86
-P 6050 4350
-F 0 "U5" H 6050 4350 60 0000 C CNN
-F 1 "d_nor" H 6100 4450 60 0000 C CNN
-F 2 "" H 6050 4350 60 0000 C CNN
-F 3 "" H 6050 4350 60 0000 C CNN
- 1 6050 4350
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CEE1F8C
-P 3850 4200
-F 0 "U1" H 3900 4300 30 0000 C CNN
-F 1 "PORT" H 3850 4200 30 0000 C CNN
-F 2 "" H 3850 4200 60 0000 C CNN
-F 3 "" H 3850 4200 60 0000 C CNN
- 1 3850 4200
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CEE1F92
-P 3850 4450
-F 0 "U1" H 3900 4550 30 0000 C CNN
-F 1 "PORT" H 3850 4450 30 0000 C CNN
-F 2 "" H 3850 4450 60 0000 C CNN
-F 3 "" H 3850 4450 60 0000 C CNN
- 2 3850 4450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CEE1F98
-P 8450 3500
-F 0 "U1" H 8500 3600 30 0000 C CNN
-F 1 "PORT" H 8450 3500 30 0000 C CNN
-F 2 "" H 8450 3500 60 0000 C CNN
-F 3 "" H 8450 3500 60 0000 C CNN
- 7 8450 3500
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CEE1F9E
-P 7000 3600
-F 0 "U1" H 7050 3700 30 0000 C CNN
-F 1 "PORT" H 7000 3600 30 0000 C CNN
-F 2 "" H 7000 3600 60 0000 C CNN
-F 3 "" H 7000 3600 60 0000 C CNN
- 10 7000 3600
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4100 4200 4350 4200
-Wire Wire Line
- 4100 4450 4250 4450
-Wire Wire Line
- 4250 4450 4250 4300
-Wire Wire Line
- 4250 4300 4350 4300
-Wire Wire Line
- 5250 4250 5600 4250
-Wire Wire Line
- 5450 4450 5600 4450
-Wire Wire Line
- 5600 4450 5600 4350
-Wire Wire Line
- 6500 4300 6700 4300
-Wire Wire Line
- 7800 3500 8200 3500
-NoConn ~ 7800 3500
-$Comp
-L PORT U1
-U 13 1 5CEE2827
-P 5250 3750
-F 0 "U1" H 5300 3850 30 0000 C CNN
-F 1 "PORT" H 5250 3750 30 0000 C CNN
-F 2 "" H 5250 3750 60 0000 C CNN
-F 3 "" H 5250 3750 60 0000 C CNN
- 13 5250 3750
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7800 3850 8200 3850
-NoConn ~ 7800 3850
-$Comp
-L PORT U1
-U 14 1 5CEE289D
-P 8450 3850
-F 0 "U1" H 8500 3950 30 0000 C CNN
-F 1 "PORT" H 8450 3850 30 0000 C CNN
-F 2 "" H 8450 3850 60 0000 C CNN
-F 3 "" H 8450 3850 60 0000 C CNN
- 14 8450 3850
- -1 0 0 1
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4025/4025.sub b/src/SubcircuitLibrary/4025/4025.sub deleted file mode 100644 index 867617fd..00000000 --- a/src/SubcircuitLibrary/4025/4025.sub +++ /dev/null @@ -1,30 +0,0 @@ -* Subcircuit 4025
-.subckt 4025 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
-* c:\users\bhargav\esim\src\subcircuitlibrary\4025\4025.cir
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u6 net-_u3-pad3_ net-_u1-pad5_ net-_u1-pad6_ d_nor
-* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u4-pad3_ d_or
-* u7 net-_u4-pad3_ net-_u1-pad13_ net-_u1-pad10_ d_nor
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u5 net-_u2-pad3_ net-_u1-pad8_ net-_u1-pad9_ d_nor
-a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a2 [net-_u3-pad3_ net-_u1-pad5_ ] net-_u1-pad6_ u6
-a3 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u4-pad3_ u4
-a4 [net-_u4-pad3_ net-_u1-pad13_ ] net-_u1-pad10_ u7
-a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a6 [net-_u2-pad3_ net-_u1-pad8_ ] net-_u1-pad9_ u5
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u5 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4025
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/4025_Previous_Values.xml b/src/SubcircuitLibrary/4025/4025_Previous_Values.xml deleted file mode 100644 index 228a19a0..00000000 --- a/src/SubcircuitLibrary/4025/4025_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u7 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u7><u2 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2><u5 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u5></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4025/analysis b/src/SubcircuitLibrary/4025/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4025/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/4028-cache.lib b/src/SubcircuitLibrary/4028/4028-cache.lib deleted file mode 100644 index 5b7e8ebd..00000000 --- a/src/SubcircuitLibrary/4028/4028-cache.lib +++ /dev/null @@ -1,94 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_nor -# -DEF d_nor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nor" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4028/4028.cir b/src/SubcircuitLibrary/4028/4028.cir deleted file mode 100644 index ff25eb55..00000000 --- a/src/SubcircuitLibrary/4028/4028.cir +++ /dev/null @@ -1,32 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor -U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor -U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor -U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor -U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor -U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor -U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor -U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter -U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter -U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter -U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter -U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and -U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and -U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and -U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and -U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and -U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and -U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and -U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and -U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT -U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and - -.end diff --git a/src/SubcircuitLibrary/4028/4028.cir.out b/src/SubcircuitLibrary/4028/4028.cir.out deleted file mode 100644 index 882115b7..00000000 --- a/src/SubcircuitLibrary/4028/4028.cir.out +++ /dev/null @@ -1,96 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir - -* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor -* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor -* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor -* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor -* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor -* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor -* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor -* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter -* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter -* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter -* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and -* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and -* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and -* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and -* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and -* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and -* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and -* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and -* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port -* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and -a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 -a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 -a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 -a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 -a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 -a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 -a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 -a8 net-_u1-pad10_ net-_u11-pad1_ u2 -a9 net-_u1-pad13_ net-_u10-pad2_ u3 -a10 net-_u1-pad12_ net-_u4-pad2_ u4 -a11 net-_u1-pad11_ net-_u5-pad2_ u5 -a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 -a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 -a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 -a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 -a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 -a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 -a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 -a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 -a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 -a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4028/4028.pro b/src/SubcircuitLibrary/4028/4028.pro deleted file mode 100644 index a63207b3..00000000 --- a/src/SubcircuitLibrary/4028/4028.pro +++ /dev/null @@ -1,43 +0,0 @@ -update=05/31/19 15:43:40 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_Sources -LibName9=eSim_Subckt -LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4028/4028.sch b/src/SubcircuitLibrary/4028/4028.sch deleted file mode 100644 index 373a95e6..00000000 --- a/src/SubcircuitLibrary/4028/4028.sch +++ /dev/null @@ -1,628 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_nor U9 -U 1 1 5CF0FE64 -P 3750 2500 -F 0 "U9" H 3750 2500 60 0000 C CNN -F 1 "d_nor" H 3800 2600 60 0000 C CNN -F 2 "" H 3750 2500 60 0000 C CNN -F 3 "" H 3750 2500 60 0000 C CNN - 1 3750 2500 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U10 -U 1 1 5CF0FEA4 -P 3750 3050 -F 0 "U10" H 3750 3050 60 0000 C CNN -F 1 "d_nor" H 3800 3150 60 0000 C CNN -F 2 "" H 3750 3050 60 0000 C CNN -F 3 "" H 3750 3050 60 0000 C CNN - 1 3750 3050 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U11 -U 1 1 5CF0FECC -P 3750 3550 -F 0 "U11" H 3750 3550 60 0000 C CNN -F 1 "d_nor" H 3800 3650 60 0000 C CNN -F 2 "" H 3750 3550 60 0000 C CNN -F 3 "" H 3750 3550 60 0000 C CNN - 1 3750 3550 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U12 -U 1 1 5CF0FEF5 -P 3750 4150 -F 0 "U12" H 3750 4150 60 0000 C CNN -F 1 "d_nor" H 3800 4250 60 0000 C CNN -F 2 "" H 3750 4150 60 0000 C CNN -F 3 "" H 3750 4150 60 0000 C CNN - 1 3750 4150 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U6 -U 1 1 5CF0FF23 -P 3700 4750 -F 0 "U6" H 3700 4750 60 0000 C CNN -F 1 "d_nor" H 3750 4850 60 0000 C CNN -F 2 "" H 3700 4750 60 0000 C CNN -F 3 "" H 3700 4750 60 0000 C CNN - 1 3700 4750 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U7 -U 1 1 5CF0FF59 -P 3700 5250 -F 0 "U7" H 3700 5250 60 0000 C CNN -F 1 "d_nor" H 3750 5350 60 0000 C CNN -F 2 "" H 3700 5250 60 0000 C CNN -F 3 "" H 3700 5250 60 0000 C CNN - 1 3700 5250 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U8 -U 1 1 5CF0FFA9 -P 3750 2000 -F 0 "U8" H 3750 2000 60 0000 C CNN -F 1 "d_nor" H 3800 2100 60 0000 C CNN -F 2 "" H 3750 2000 60 0000 C CNN -F 3 "" H 3750 2000 60 0000 C CNN - 1 3750 2000 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U2 -U 1 1 5CF1003A -P 2150 2400 -F 0 "U2" H 2150 2300 60 0000 C CNN -F 1 "d_inverter" H 2150 2550 60 0000 C CNN -F 2 "" H 2200 2350 60 0000 C CNN -F 3 "" H 2200 2350 60 0000 C CNN - 1 2150 2400 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5CF1007F -P 2150 3300 -F 0 "U3" H 2150 3200 60 0000 C CNN -F 1 "d_inverter" H 2150 3450 60 0000 C CNN -F 2 "" H 2200 3250 60 0000 C CNN -F 3 "" H 2200 3250 60 0000 C CNN - 1 2150 3300 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5CF100CC -P 2150 4150 -F 0 "U4" H 2150 4050 60 0000 C CNN -F 1 "d_inverter" H 2150 4300 60 0000 C CNN -F 2 "" H 2200 4100 60 0000 C CNN -F 3 "" H 2200 4100 60 0000 C CNN - 1 2150 4150 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U5 -U 1 1 5CF10114 -P 2150 4900 -F 0 "U5" H 2150 4800 60 0000 C CNN -F 1 "d_inverter" H 2150 5050 60 0000 C CNN -F 2 "" H 2200 4850 60 0000 C CNN -F 3 "" H 2200 4850 60 0000 C CNN - 1 2150 4900 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1400 2400 1850 2400 -Wire Wire Line - 1400 3300 1850 3300 -Wire Wire Line - 1450 4150 1850 4150 -Wire Wire Line - 1450 4900 1850 4900 -Wire Wire Line - 2450 4900 2500 4900 -Wire Wire Line - 2500 4900 2500 5250 -Wire Wire Line - 2500 5250 3250 5250 -Wire Wire Line - 2450 4150 2550 4150 -Wire Wire Line - 2550 4150 2550 4650 -Wire Wire Line - 2550 4650 3250 4650 -Wire Wire Line - 2450 3300 2550 3300 -Wire Wire Line - 2550 3300 2550 3550 -Wire Wire Line - 2550 3550 3300 3550 -Wire Wire Line - 2450 2400 2450 2500 -Wire Wire Line - 2450 2500 3300 2500 -Wire Wire Line - 2800 2500 2800 3450 -Wire Wire Line - 2800 3450 3300 3450 -Connection ~ 2800 2500 -Wire Wire Line - 1650 2400 1650 1900 -Wire Wire Line - 1650 1900 3300 1900 -Connection ~ 1650 2400 -Wire Wire Line - 3300 2000 2850 2000 -Wire Wire Line - 2850 2000 2850 3000 -Wire Wire Line - 2850 3000 1650 3000 -Wire Wire Line - 1650 3000 1650 3300 -Connection ~ 1650 3300 -Wire Wire Line - 2850 2400 3300 2400 -Connection ~ 2850 2400 -Wire Wire Line - 2950 1900 2950 2950 -Wire Wire Line - 2950 2950 3300 2950 -Connection ~ 2950 1900 -Wire Wire Line - 3100 3550 3100 3050 -Wire Wire Line - 3100 3050 3300 3050 -Connection ~ 3100 3550 -Wire Wire Line - 1650 3900 1650 4150 -Wire Wire Line - 1650 3900 3050 3900 -Wire Wire Line - 3050 3900 3050 5150 -Wire Wire Line - 3050 4050 3300 4050 -Connection ~ 1650 4150 -Wire Wire Line - 1750 4900 1750 5150 -Wire Wire Line - 1750 5150 2750 5150 -Connection ~ 1750 4900 -Wire Wire Line - 2750 5150 2750 4150 -Wire Wire Line - 2750 4150 3300 4150 -Wire Wire Line - 2750 4750 3250 4750 -Connection ~ 2750 4750 -Wire Wire Line - 3050 5150 3250 5150 -Connection ~ 3050 4050 -$Comp -L d_and U15 -U 1 1 5CF106B1 -P 6600 1850 -F 0 "U15" H 6600 1850 60 0000 C CNN -F 1 "d_and" H 6650 1950 60 0000 C CNN -F 2 "" H 6600 1850 60 0000 C CNN -F 3 "" H 6600 1850 60 0000 C CNN - 1 6600 1850 - 1 0 0 -1 -$EndComp -$Comp -L d_and U16 -U 1 1 5CF10756 -P 6600 2350 -F 0 "U16" H 6600 2350 60 0000 C CNN -F 1 "d_and" H 6650 2450 60 0000 C CNN -F 2 "" H 6600 2350 60 0000 C CNN -F 3 "" H 6600 2350 60 0000 C CNN - 1 6600 2350 - 1 0 0 -1 -$EndComp -$Comp -L d_and U17 -U 1 1 5CF107A1 -P 6600 2800 -F 0 "U17" H 6600 2800 60 0000 C CNN -F 1 "d_and" H 6650 2900 60 0000 C CNN -F 2 "" H 6600 2800 60 0000 C CNN -F 3 "" H 6600 2800 60 0000 C CNN - 1 6600 2800 - 1 0 0 -1 -$EndComp -$Comp -L d_and U18 -U 1 1 5CF107E9 -P 6600 3200 -F 0 "U18" H 6600 3200 60 0000 C CNN -F 1 "d_and" H 6650 3300 60 0000 C CNN -F 2 "" H 6600 3200 60 0000 C CNN -F 3 "" H 6600 3200 60 0000 C CNN - 1 6600 3200 - 1 0 0 -1 -$EndComp -$Comp -L d_and U19 -U 1 1 5CF10834 -P 6600 3650 -F 0 "U19" H 6600 3650 60 0000 C CNN -F 1 "d_and" H 6650 3750 60 0000 C CNN -F 2 "" H 6600 3650 60 0000 C CNN -F 3 "" H 6600 3650 60 0000 C CNN - 1 6600 3650 - 1 0 0 -1 -$EndComp -$Comp -L d_and U20 -U 1 1 5CF1087E -P 6600 4050 -F 0 "U20" H 6600 4050 60 0000 C CNN -F 1 "d_and" H 6650 4150 60 0000 C CNN -F 2 "" H 6600 4050 60 0000 C CNN -F 3 "" H 6600 4050 60 0000 C CNN - 1 6600 4050 - 1 0 0 -1 -$EndComp -$Comp -L d_and U21 -U 1 1 5CF108F9 -P 6600 4450 -F 0 "U21" H 6600 4450 60 0000 C CNN -F 1 "d_and" H 6650 4550 60 0000 C CNN -F 2 "" H 6600 4450 60 0000 C CNN -F 3 "" H 6600 4450 60 0000 C CNN - 1 6600 4450 - 1 0 0 -1 -$EndComp -$Comp -L d_and U13 -U 1 1 5CF1094D -P 6550 4900 -F 0 "U13" H 6550 4900 60 0000 C CNN -F 1 "d_and" H 6600 5000 60 0000 C CNN -F 2 "" H 6550 4900 60 0000 C CNN -F 3 "" H 6550 4900 60 0000 C CNN - 1 6550 4900 - 1 0 0 -1 -$EndComp -$Comp -L d_and U14 -U 1 1 5CF109A6 -P 6550 5350 -F 0 "U14" H 6550 5350 60 0000 C CNN -F 1 "d_and" H 6600 5450 60 0000 C CNN -F 2 "" H 6550 5350 60 0000 C CNN -F 3 "" H 6550 5350 60 0000 C CNN - 1 6550 5350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CF11966 -P 1150 2400 -F 0 "U1" H 1200 2500 30 0000 C CNN -F 1 "PORT" H 1150 2400 30 0000 C CNN -F 2 "" H 1150 2400 60 0000 C CNN -F 3 "" H 1150 2400 60 0000 C CNN - 10 1150 2400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CF119D4 -P 1150 3300 -F 0 "U1" H 1200 3400 30 0000 C CNN -F 1 "PORT" H 1150 3300 30 0000 C CNN -F 2 "" H 1150 3300 60 0000 C CNN -F 3 "" H 1150 3300 60 0000 C CNN - 13 1150 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CF11AFC -P 1200 4150 -F 0 "U1" H 1250 4250 30 0000 C CNN -F 1 "PORT" H 1200 4150 30 0000 C CNN -F 2 "" H 1200 4150 60 0000 C CNN -F 3 "" H 1200 4150 60 0000 C CNN - 12 1200 4150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CF11B6B -P 1200 4900 -F 0 "U1" H 1250 5000 30 0000 C CNN -F 1 "PORT" H 1200 4900 30 0000 C CNN -F 2 "" H 1200 4900 60 0000 C CNN -F 3 "" H 1200 4900 60 0000 C CNN - 11 1200 4900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CF11BDB -P 8000 1800 -F 0 "U1" H 8050 1900 30 0000 C CNN -F 1 "PORT" H 8000 1800 30 0000 C CNN -F 2 "" H 8000 1800 60 0000 C CNN -F 3 "" H 8000 1800 60 0000 C CNN - 3 8000 1800 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CF11F59 -P 8000 2300 -F 0 "U1" H 8050 2400 30 0000 C CNN -F 1 "PORT" H 8000 2300 30 0000 C CNN -F 2 "" H 8000 2300 60 0000 C CNN -F 3 "" H 8000 2300 60 0000 C CNN - 14 8000 2300 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5CF11FC5 -P 8000 2750 -F 0 "U1" H 8050 2850 30 0000 C CNN -F 1 "PORT" H 8000 2750 30 0000 C CNN -F 2 "" H 8000 2750 60 0000 C CNN -F 3 "" H 8000 2750 60 0000 C CNN - 2 8000 2750 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 15 1 5CF1204F -P 8000 3150 -F 0 "U1" H 8050 3250 30 0000 C CNN -F 1 "PORT" H 8000 3150 30 0000 C CNN -F 2 "" H 8000 3150 60 0000 C CNN -F 3 "" H 8000 3150 60 0000 C CNN - 15 8000 3150 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CF120C5 -P 7950 3600 -F 0 "U1" H 8000 3700 30 0000 C CNN -F 1 "PORT" H 7950 3600 30 0000 C CNN -F 2 "" H 7950 3600 60 0000 C CNN -F 3 "" H 7950 3600 60 0000 C CNN - 1 7950 3600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CF1213C -P 7950 4000 -F 0 "U1" H 8000 4100 30 0000 C CNN -F 1 "PORT" H 7950 4000 30 0000 C CNN -F 2 "" H 7950 4000 60 0000 C CNN -F 3 "" H 7950 4000 60 0000 C CNN - 6 7950 4000 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 7 1 5CF121B2 -P 7900 4400 -F 0 "U1" H 7950 4500 30 0000 C CNN -F 1 "PORT" H 7900 4400 30 0000 C CNN -F 2 "" H 7900 4400 60 0000 C CNN -F 3 "" H 7900 4400 60 0000 C CNN - 7 7900 4400 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CF1223D -P 7900 4850 -F 0 "U1" H 7950 4950 30 0000 C CNN -F 1 "PORT" H 7900 4850 30 0000 C CNN -F 2 "" H 7900 4850 60 0000 C CNN -F 3 "" H 7900 4850 60 0000 C CNN - 4 7900 4850 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 9 1 5CF1237B -P 7900 5300 -F 0 "U1" H 7950 5400 30 0000 C CNN -F 1 "PORT" H 7900 5300 30 0000 C CNN -F 2 "" H 7900 5300 60 0000 C CNN -F 3 "" H 7900 5300 60 0000 C CNN - 9 7900 5300 - -1 0 0 1 -$EndComp -Wire Wire Line - 7750 1800 7050 1800 -Wire Wire Line - 7050 2300 7750 2300 -Wire Wire Line - 7750 2750 7050 2750 -Wire Wire Line - 7050 3150 7750 3150 -Wire Wire Line - 7700 3600 7050 3600 -Wire Wire Line - 7050 4000 7700 4000 -Wire Wire Line - 7650 4400 7050 4400 -Wire Wire Line - 7000 4850 7650 4850 -Wire Wire Line - 7650 5300 7000 5300 -$Comp -L d_and U22 -U 1 1 5CF14904 -P 6550 5800 -F 0 "U22" H 6550 5800 60 0000 C CNN -F 1 "d_and" H 6600 5900 60 0000 C CNN -F 2 "" H 6550 5800 60 0000 C CNN -F 3 "" H 6550 5800 60 0000 C CNN - 1 6550 5800 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4200 1950 4600 1950 -Wire Wire Line - 4600 1750 4600 5250 -Wire Wire Line - 4600 1750 6150 1750 -Wire Wire Line - 4600 5250 6100 5250 -Connection ~ 4600 1950 -Wire Wire Line - 6100 5800 5900 5800 -Wire Wire Line - 5900 5800 5900 5350 -Wire Wire Line - 5900 5350 6100 5350 -Wire Wire Line - 5850 4900 6100 4900 -Wire Wire Line - 5850 3650 5850 4900 -Wire Wire Line - 5850 4450 6150 4450 -Wire Wire Line - 5850 4050 6150 4050 -Connection ~ 5850 4450 -Wire Wire Line - 5850 3650 6150 3650 -Connection ~ 5850 4050 -Wire Wire Line - 5050 3200 6150 3200 -Wire Wire Line - 5850 1850 5850 3200 -Wire Wire Line - 5850 2800 6150 2800 -Wire Wire Line - 5850 2350 6150 2350 -Connection ~ 5850 2800 -Wire Wire Line - 5850 1850 6150 1850 -Connection ~ 5850 2350 -Wire Wire Line - 4200 2450 4700 2450 -Wire Wire Line - 4700 2250 4700 5700 -Wire Wire Line - 4700 2250 6150 2250 -Wire Wire Line - 4200 3000 4800 3000 -Wire Wire Line - 4800 2700 4800 4350 -Wire Wire Line - 4800 2700 6150 2700 -Wire Wire Line - 4700 5700 6100 5700 -Connection ~ 4700 2450 -Wire Wire Line - 6150 3550 4600 3550 -Connection ~ 4600 3550 -Wire Wire Line - 6150 3950 4700 3950 -Connection ~ 4700 3950 -Wire Wire Line - 4800 4350 6150 4350 -Connection ~ 4800 3000 -Wire Wire Line - 4200 3500 4900 3500 -Wire Wire Line - 4900 3100 4900 4800 -Wire Wire Line - 4900 3100 6150 3100 -Wire Wire Line - 4900 4800 6100 4800 -Connection ~ 4900 3500 -Wire Wire Line - 4200 4100 5050 4100 -Wire Wire Line - 5050 4100 5050 3200 -Connection ~ 5850 3200 -Wire Wire Line - 4150 4700 5850 4700 -Connection ~ 5850 4700 -Wire Wire Line - 4150 5200 4500 5200 -Wire Wire Line - 4500 5200 4500 5550 -Wire Wire Line - 4500 5550 5900 5550 -Connection ~ 5900 5550 -$Comp -L PORT U1 -U 5 1 5CF1563E -P 7950 5750 -F 0 "U1" H 8000 5850 30 0000 C CNN -F 1 "PORT" H 7950 5750 30 0000 C CNN -F 2 "" H 7950 5750 60 0000 C CNN -F 3 "" H 7950 5750 60 0000 C CNN - 5 7950 5750 - -1 0 0 1 -$EndComp -Wire Wire Line - 7700 5750 7000 5750 -$Comp -L PORT U1 -U 8 1 5CF15953 -P 9550 4800 -F 0 "U1" H 9600 4900 30 0000 C CNN -F 1 "PORT" H 9550 4800 30 0000 C CNN -F 2 "" H 9550 4800 60 0000 C CNN -F 3 "" H 9550 4800 60 0000 C CNN - 8 9550 4800 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 16 1 5CF15A07 -P 9550 5250 -F 0 "U1" H 9600 5350 30 0000 C CNN -F 1 "PORT" H 9550 5250 30 0000 C CNN -F 2 "" H 9550 5250 60 0000 C CNN -F 3 "" H 9550 5250 60 0000 C CNN - 16 9550 5250 - -1 0 0 1 -$EndComp -NoConn ~ 9300 4800 -NoConn ~ 9300 5250 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4028/4028.sub b/src/SubcircuitLibrary/4028/4028.sub deleted file mode 100644 index 828e0b67..00000000 --- a/src/SubcircuitLibrary/4028/4028.sub +++ /dev/null @@ -1,90 +0,0 @@ -* Subcircuit 4028 -.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? -* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir -* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor -* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor -* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor -* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor -* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor -* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor -* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor -* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter -* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter -* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter -* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and -* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and -* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and -* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and -* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and -* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and -* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and -* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and -* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and -* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and -a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9 -a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10 -a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 -a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12 -a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6 -a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7 -a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8 -a8 net-_u1-pad10_ net-_u11-pad1_ u2 -a9 net-_u1-pad13_ net-_u10-pad2_ u3 -a10 net-_u1-pad12_ net-_u4-pad2_ u4 -a11 net-_u1-pad11_ net-_u5-pad2_ u5 -a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15 -a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16 -a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17 -a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18 -a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19 -a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20 -a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21 -a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13 -a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14 -a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22 -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4028
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml b/src/SubcircuitLibrary/4028/4028_Previous_Values.xml deleted file mode 100644 index 189fb200..00000000 --- a/src/SubcircuitLibrary/4028/4028_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4028/analysis b/src/SubcircuitLibrary/4028/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4028/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4072/4072-cache.lib b/src/SubcircuitLibrary/4072/4072-cache.lib deleted file mode 100644 index a3c1c972..00000000 --- a/src/SubcircuitLibrary/4072/4072-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4072/4072.cir b/src/SubcircuitLibrary/4072/4072.cir deleted file mode 100644 index 0f2e56f0..00000000 --- a/src/SubcircuitLibrary/4072/4072.cir +++ /dev/null @@ -1,17 +0,0 @@ -* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4072\4072.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 10:17:30
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
-U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
-U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or
-U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or
-U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_or
-U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_or
-
-.end
diff --git a/src/SubcircuitLibrary/4072/4072.cir.out b/src/SubcircuitLibrary/4072/4072.cir.out deleted file mode 100644 index 61e8e949..00000000 --- a/src/SubcircuitLibrary/4072/4072.cir.out +++ /dev/null @@ -1,36 +0,0 @@ -* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
-
-* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
-* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
-a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4072/4072.pro b/src/SubcircuitLibrary/4072/4072.pro deleted file mode 100644 index 64662931..00000000 --- a/src/SubcircuitLibrary/4072/4072.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=05/31/19 10:11:54
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
-LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
-LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
-LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
-LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
-LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_PSpice
-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
-LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
-LibName12=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/src/SubcircuitLibrary/4072/4072.sch b/src/SubcircuitLibrary/4072/4072.sch deleted file mode 100644 index 782d3e69..00000000 --- a/src/SubcircuitLibrary/4072/4072.sch +++ /dev/null @@ -1,334 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:4002-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5CF0AF1E
-P 4750 2900
-F 0 "U2" H 4750 2900 60 0000 C CNN
-F 1 "d_or" H 4750 3000 60 0000 C CNN
-F 2 "" H 4750 2900 60 0000 C CNN
-F 3 "" H 4750 2900 60 0000 C CNN
- 1 4750 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5CF0AF1F
-P 4750 3450
-F 0 "U3" H 4750 3450 60 0000 C CNN
-F 1 "d_or" H 4750 3550 60 0000 C CNN
-F 2 "" H 4750 3450 60 0000 C CNN
-F 3 "" H 4750 3450 60 0000 C CNN
- 1 4750 3450
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5200 2850 5400 2850
-Wire Wire Line
- 5400 2850 5400 3000
-Wire Wire Line
- 5400 3000 5550 3000
-Wire Wire Line
- 5200 3400 5400 3400
-Wire Wire Line
- 5400 3400 5400 3100
-Wire Wire Line
- 5400 3100 5550 3100
-Wire Wire Line
- 5650 5350 6050 5350
-Wire Wire Line
- 5650 5550 6050 5550
-Wire Wire Line
- 5650 5800 6050 5800
-Wire Wire Line
- 5650 6000 6050 6000
-NoConn ~ 5650 5350
-NoConn ~ 5650 5550
-NoConn ~ 5650 5800
-NoConn ~ 5650 6000
-$Comp
-L PORT U1
-U 5 1 5CF0AF21
-P 3850 2800
-F 0 "U1" H 3900 2900 30 0000 C CNN
-F 1 "PORT" H 3850 2800 30 0000 C CNN
-F 2 "" H 3850 2800 60 0000 C CNN
-F 3 "" H 3850 2800 60 0000 C CNN
- 5 3850 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CF0AF22
-P 3900 3050
-F 0 "U1" H 3950 3150 30 0000 C CNN
-F 1 "PORT" H 3900 3050 30 0000 C CNN
-F 2 "" H 3900 3050 60 0000 C CNN
-F 3 "" H 3900 3050 60 0000 C CNN
- 2 3900 3050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CF0AF23
-P 3900 3250
-F 0 "U1" H 3950 3350 30 0000 C CNN
-F 1 "PORT" H 3900 3250 30 0000 C CNN
-F 2 "" H 3900 3250 60 0000 C CNN
-F 3 "" H 3900 3250 60 0000 C CNN
- 3 3900 3250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CF0AF24
-P 3900 3550
-F 0 "U1" H 3950 3650 30 0000 C CNN
-F 1 "PORT" H 3900 3550 30 0000 C CNN
-F 2 "" H 3900 3550 60 0000 C CNN
-F 3 "" H 3900 3550 60 0000 C CNN
- 4 3900 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CF0AF25
-P 6950 3050
-F 0 "U1" H 7000 3150 30 0000 C CNN
-F 1 "PORT" H 6950 3050 30 0000 C CNN
-F 2 "" H 6950 3050 60 0000 C CNN
-F 3 "" H 6950 3050 60 0000 C CNN
- 1 6950 3050
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4100 2800 4300 2800
-Wire Wire Line
- 4150 3050 4150 2900
-Wire Wire Line
- 4150 2900 4300 2900
-Wire Wire Line
- 4150 3250 4300 3250
-Wire Wire Line
- 4300 3250 4300 3350
-Wire Wire Line
- 4150 3550 4150 3450
-Wire Wire Line
- 4150 3450 4300 3450
-Wire Wire Line
- 6700 3050 6450 3050
-$Comp
-L d_or U4
-U 1 1 5CF0AF26
-P 4900 4100
-F 0 "U4" H 4900 4100 60 0000 C CNN
-F 1 "d_or" H 4900 4200 60 0000 C CNN
-F 2 "" H 4900 4100 60 0000 C CNN
-F 3 "" H 4900 4100 60 0000 C CNN
- 1 4900 4100
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U5
-U 1 1 5CF0AF27
-P 4900 4650
-F 0 "U5" H 4900 4650 60 0000 C CNN
-F 1 "d_or" H 4900 4750 60 0000 C CNN
-F 2 "" H 4900 4650 60 0000 C CNN
-F 3 "" H 4900 4650 60 0000 C CNN
- 1 4900 4650
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5350 4050 5550 4050
-Wire Wire Line
- 5550 4050 5550 4200
-Wire Wire Line
- 5550 4200 5700 4200
-Wire Wire Line
- 5350 4600 5550 4600
-Wire Wire Line
- 5550 4600 5550 4300
-Wire Wire Line
- 5550 4300 5700 4300
-$Comp
-L PORT U1
-U 9 1 5CF0AF29
-P 4000 4000
-F 0 "U1" H 4050 4100 30 0000 C CNN
-F 1 "PORT" H 4000 4000 30 0000 C CNN
-F 2 "" H 4000 4000 60 0000 C CNN
-F 3 "" H 4000 4000 60 0000 C CNN
- 9 4000 4000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5CF0AF2A
-P 4050 4250
-F 0 "U1" H 4100 4350 30 0000 C CNN
-F 1 "PORT" H 4050 4250 30 0000 C CNN
-F 2 "" H 4050 4250 60 0000 C CNN
-F 3 "" H 4050 4250 60 0000 C CNN
- 10 4050 4250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5CF0AF2B
-P 4050 4450
-F 0 "U1" H 4100 4550 30 0000 C CNN
-F 1 "PORT" H 4050 4450 30 0000 C CNN
-F 2 "" H 4050 4450 60 0000 C CNN
-F 3 "" H 4050 4450 60 0000 C CNN
- 11 4050 4450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5CF0AF2C
-P 4050 4750
-F 0 "U1" H 4100 4850 30 0000 C CNN
-F 1 "PORT" H 4050 4750 30 0000 C CNN
-F 2 "" H 4050 4750 60 0000 C CNN
-F 3 "" H 4050 4750 60 0000 C CNN
- 12 4050 4750
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5CF0AF2D
-P 7100 4250
-F 0 "U1" H 7150 4350 30 0000 C CNN
-F 1 "PORT" H 7100 4250 30 0000 C CNN
-F 2 "" H 7100 4250 60 0000 C CNN
-F 3 "" H 7100 4250 60 0000 C CNN
- 13 7100 4250
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4250 4000 4450 4000
-Wire Wire Line
- 4300 4250 4300 4100
-Wire Wire Line
- 4300 4100 4450 4100
-Wire Wire Line
- 4300 4450 4450 4450
-Wire Wire Line
- 4450 4450 4450 4550
-Wire Wire Line
- 4300 4750 4300 4650
-Wire Wire Line
- 4300 4650 4450 4650
-Wire Wire Line
- 6850 4250 6600 4250
-$Comp
-L PORT U1
-U 6 1 5CF0AF2E
-P 6300 5350
-F 0 "U1" H 6350 5450 30 0000 C CNN
-F 1 "PORT" H 6300 5350 30 0000 C CNN
-F 2 "" H 6300 5350 60 0000 C CNN
-F 3 "" H 6300 5350 60 0000 C CNN
- 6 6300 5350
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CF0AF2F
-P 6300 5550
-F 0 "U1" H 6350 5650 30 0000 C CNN
-F 1 "PORT" H 6300 5550 30 0000 C CNN
-F 2 "" H 6300 5550 60 0000 C CNN
-F 3 "" H 6300 5550 60 0000 C CNN
- 7 6300 5550
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5CF0AF30
-P 6300 5800
-F 0 "U1" H 6350 5900 30 0000 C CNN
-F 1 "PORT" H 6300 5800 30 0000 C CNN
-F 2 "" H 6300 5800 60 0000 C CNN
-F 3 "" H 6300 5800 60 0000 C CNN
- 8 6300 5800
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5CF0AF31
-P 6300 6000
-F 0 "U1" H 6350 6100 30 0000 C CNN
-F 1 "PORT" H 6300 6000 30 0000 C CNN
-F 2 "" H 6300 6000 60 0000 C CNN
-F 3 "" H 6300 6000 60 0000 C CNN
- 14 6300 6000
- -1 0 0 1
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5CF0D6D2
-P 6000 3100
-F 0 "U6" H 6000 3100 60 0000 C CNN
-F 1 "d_or" H 6000 3200 60 0000 C CNN
-F 2 "" H 6000 3100 60 0000 C CNN
-F 3 "" H 6000 3100 60 0000 C CNN
- 1 6000 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U7
-U 1 1 5CF0D73F
-P 6150 4300
-F 0 "U7" H 6150 4300 60 0000 C CNN
-F 1 "d_or" H 6150 4400 60 0000 C CNN
-F 2 "" H 6150 4300 60 0000 C CNN
-F 3 "" H 6150 4300 60 0000 C CNN
- 1 6150 4300
- 1 0 0 -1
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4072/4072.sub b/src/SubcircuitLibrary/4072/4072.sub deleted file mode 100644 index 174ea00d..00000000 --- a/src/SubcircuitLibrary/4072/4072.sub +++ /dev/null @@ -1,30 +0,0 @@ -* Subcircuit 4072
-.subckt 4072 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
-* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
-* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
-* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
-a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4072
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4072/4072_Previous_Values.xml b/src/SubcircuitLibrary/4072/4072_Previous_Values.xml deleted file mode 100644 index 0ccd120c..00000000 --- a/src/SubcircuitLibrary/4072/4072_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_or<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4072/analysis b/src/SubcircuitLibrary/4072/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4072/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and-cache.lib b/src/SubcircuitLibrary/4073/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/4073/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4073/3_and.cir b/src/SubcircuitLibrary/4073/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/4073/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/4073/3_and.cir.out b/src/SubcircuitLibrary/4073/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/4073/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4073/3_and.pro b/src/SubcircuitLibrary/4073/3_and.pro deleted file mode 100644 index 76df4655..00000000 --- a/src/SubcircuitLibrary/4073/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4073/3_and.sch b/src/SubcircuitLibrary/4073/3_and.sch deleted file mode 100644 index d6ac89f9..00000000 --- a/src/SubcircuitLibrary/4073/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:3_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -Text Notes 3500 2600 0 60 ~ 12 -in1 -Text Notes 3450 2800 0 60 ~ 12 -in2\n -Text Notes 3500 3100 0 60 ~ 12 -in3 -Text Notes 6100 2850 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/3_and.sub b/src/SubcircuitLibrary/4073/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/4073/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/4073/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073-cache.lib b/src/SubcircuitLibrary/4073/4073-cache.lib deleted file mode 100644 index 4ee605a2..00000000 --- a/src/SubcircuitLibrary/4073/4073-cache.lib +++ /dev/null @@ -1,62 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4073/4073.cir b/src/SubcircuitLibrary/4073/4073.cir deleted file mode 100644 index e159f055..00000000 --- a/src/SubcircuitLibrary/4073/4073.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT -X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and -X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and - -.end diff --git a/src/SubcircuitLibrary/4073/4073.cir.out b/src/SubcircuitLibrary/4073/4073.cir.out deleted file mode 100644 index b25337cd..00000000 --- a/src/SubcircuitLibrary/4073/4073.cir.out +++ /dev/null @@ -1,16 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and -x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4073/4073.pro b/src/SubcircuitLibrary/4073/4073.pro deleted file mode 100644 index 94cd9bd4..00000000 --- a/src/SubcircuitLibrary/4073/4073.pro +++ /dev/null @@ -1,43 +0,0 @@ -update=05/31/19 16:37:06 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_Sources -LibName9=eSim_Subckt -LibName10=eSim_User diff --git a/src/SubcircuitLibrary/4073/4073.sch b/src/SubcircuitLibrary/4073/4073.sch deleted file mode 100644 index 045208e6..00000000 --- a/src/SubcircuitLibrary/4073/4073.sch +++ /dev/null @@ -1,263 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5CF10AEA -P 4550 2650 -F 0 "X1" H 4650 2600 60 0000 C CNN -F 1 "3_and" H 4700 2800 60 0000 C CNN -F 2 "" H 4550 2650 60 0000 C CNN -F 3 "" H 4550 2650 60 0000 C CNN - 1 4550 2650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CF10B72 -P 3100 2200 -F 0 "U1" H 3150 2300 30 0000 C CNN -F 1 "PORT" H 3100 2200 30 0000 C CNN -F 2 "" H 3100 2200 60 0000 C CNN -F 3 "" H 3100 2200 60 0000 C CNN - 1 3100 2200 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5CF10BC9 -P 3100 2500 -F 0 "U1" H 3150 2600 30 0000 C CNN -F 1 "PORT" H 3100 2500 30 0000 C CNN -F 2 "" H 3100 2500 60 0000 C CNN -F 3 "" H 3100 2500 60 0000 C CNN - 2 3100 2500 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CF10BEA -P 3100 2850 -F 0 "U1" H 3150 2950 30 0000 C CNN -F 1 "PORT" H 3100 2850 30 0000 C CNN -F 2 "" H 3100 2850 60 0000 C CNN -F 3 "" H 3100 2850 60 0000 C CNN - 8 3100 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5CF10C10 -P 6200 2600 -F 0 "U1" H 6250 2700 30 0000 C CNN -F 1 "PORT" H 6200 2600 30 0000 C CNN -F 2 "" H 6200 2600 60 0000 C CNN -F 3 "" H 6200 2600 60 0000 C CNN - 9 6200 2600 - -1 0 0 1 -$EndComp -Wire Wire Line - 5950 2600 5050 2600 -Wire Wire Line - 4200 2500 4200 2200 -Wire Wire Line - 4200 2200 3350 2200 -Wire Wire Line - 3350 2500 3850 2500 -Wire Wire Line - 3850 2500 3850 2600 -Wire Wire Line - 3850 2600 4200 2600 -Wire Wire Line - 4200 2700 4200 2850 -Wire Wire Line - 4200 2850 3350 2850 -$Comp -L 3_and X3 -U 1 1 5CF10DE5 -P 4600 4100 -F 0 "X3" H 4700 4050 60 0000 C CNN -F 1 "3_and" H 4750 4250 60 0000 C CNN -F 2 "" H 4600 4100 60 0000 C CNN -F 3 "" H 4600 4100 60 0000 C CNN - 1 4600 4100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CF10DEB -P 3150 3650 -F 0 "U1" H 3200 3750 30 0000 C CNN -F 1 "PORT" H 3150 3650 30 0000 C CNN -F 2 "" H 3150 3650 60 0000 C CNN -F 3 "" H 3150 3650 60 0000 C CNN - 3 3150 3650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CF10DF1 -P 3150 3950 -F 0 "U1" H 3200 4050 30 0000 C CNN -F 1 "PORT" H 3150 3950 30 0000 C CNN -F 2 "" H 3150 3950 60 0000 C CNN -F 3 "" H 3150 3950 60 0000 C CNN - 4 3150 3950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CF10DF7 -P 3150 4300 -F 0 "U1" H 3200 4400 30 0000 C CNN -F 1 "PORT" H 3150 4300 30 0000 C CNN -F 2 "" H 3150 4300 60 0000 C CNN -F 3 "" H 3150 4300 60 0000 C CNN - 5 3150 4300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CF10DFD -P 6250 4050 -F 0 "U1" H 6300 4150 30 0000 C CNN -F 1 "PORT" H 6250 4050 30 0000 C CNN -F 2 "" H 6250 4050 60 0000 C CNN -F 3 "" H 6250 4050 60 0000 C CNN - 6 6250 4050 - -1 0 0 1 -$EndComp -Wire Wire Line - 6000 4050 5100 4050 -Wire Wire Line - 4250 3950 4250 3650 -Wire Wire Line - 4250 3650 3400 3650 -Wire Wire Line - 3400 3950 3900 3950 -Wire Wire Line - 3900 3950 3900 4050 -Wire Wire Line - 3900 4050 4250 4050 -Wire Wire Line - 4250 4150 4250 4300 -Wire Wire Line - 4250 4300 3400 4300 -$Comp -L 3_and X2 -U 1 1 5CF10E9C -P 4550 5450 -F 0 "X2" H 4650 5400 60 0000 C CNN -F 1 "3_and" H 4700 5600 60 0000 C CNN -F 2 "" H 4550 5450 60 0000 C CNN -F 3 "" H 4550 5450 60 0000 C CNN - 1 4550 5450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CF10EA2 -P 3100 5000 -F 0 "U1" H 3150 5100 30 0000 C CNN -F 1 "PORT" H 3100 5000 30 0000 C CNN -F 2 "" H 3100 5000 60 0000 C CNN -F 3 "" H 3100 5000 60 0000 C CNN - 11 3100 5000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CF10EA8 -P 3100 5300 -F 0 "U1" H 3150 5400 30 0000 C CNN -F 1 "PORT" H 3100 5300 30 0000 C CNN -F 2 "" H 3100 5300 60 0000 C CNN -F 3 "" H 3100 5300 60 0000 C CNN - 12 3100 5300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CF10EAE -P 3100 5650 -F 0 "U1" H 3150 5750 30 0000 C CNN -F 1 "PORT" H 3100 5650 30 0000 C CNN -F 2 "" H 3100 5650 60 0000 C CNN -F 3 "" H 3100 5650 60 0000 C CNN - 13 3100 5650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CF10EB4 -P 6200 5400 -F 0 "U1" H 6250 5500 30 0000 C CNN -F 1 "PORT" H 6200 5400 30 0000 C CNN -F 2 "" H 6200 5400 60 0000 C CNN -F 3 "" H 6200 5400 60 0000 C CNN - 10 6200 5400 - -1 0 0 1 -$EndComp -Wire Wire Line - 5950 5400 5050 5400 -Wire Wire Line - 4200 5300 4200 5000 -Wire Wire Line - 4200 5000 3350 5000 -Wire Wire Line - 3350 5300 3850 5300 -Wire Wire Line - 3850 5300 3850 5400 -Wire Wire Line - 3850 5400 4200 5400 -Wire Wire Line - 4200 5500 4200 5650 -Wire Wire Line - 4200 5650 3350 5650 -$Comp -L PORT U1 -U 7 1 5CF11A2A -P 7500 4100 -F 0 "U1" H 7550 4200 30 0000 C CNN -F 1 "PORT" H 7500 4100 30 0000 C CNN -F 2 "" H 7500 4100 60 0000 C CNN -F 3 "" H 7500 4100 60 0000 C CNN - 7 7500 4100 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CF11A8A -P 7550 4600 -F 0 "U1" H 7600 4700 30 0000 C CNN -F 1 "PORT" H 7550 4600 30 0000 C CNN -F 2 "" H 7550 4600 60 0000 C CNN -F 3 "" H 7550 4600 60 0000 C CNN - 14 7550 4600 - -1 0 0 1 -$EndComp -NoConn ~ 7250 4100 -NoConn ~ 7300 4600 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4073/4073.sub b/src/SubcircuitLibrary/4073/4073.sub deleted file mode 100644 index 15208169..00000000 --- a/src/SubcircuitLibrary/4073/4073.sub +++ /dev/null @@ -1,10 +0,0 @@ -* Subcircuit 4073 -.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? -* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and -x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and -x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and -* Control Statements - -.ends 4073
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/4073_Previous_Values.xml b/src/SubcircuitLibrary/4073/4073_Previous_Values.xml deleted file mode 100644 index 5acac768..00000000 --- a/src/SubcircuitLibrary/4073/4073_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4073/analysis b/src/SubcircuitLibrary/4073/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4073/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib deleted file mode 100644 index 155f5e60..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir deleted file mode 100644 index b338b7b5..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or -U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or -U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT - -.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out deleted file mode 100644 index adb6b01b..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or -* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro deleted file mode 100644 index 9daf26bc..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=06/01/19 12:36:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_PSpice -LibName10=eSim_Sources -LibName11=eSim_Subckt -LibName12=eSim_User diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch deleted file mode 100644 index 11896865..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR.sch +++ /dev/null @@ -1,150 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_or U2 -U 1 1 5C9D00E1 -P 4300 2950 -F 0 "U2" H 4300 2950 60 0000 C CNN -F 1 "d_or" H 4300 3050 60 0000 C CNN -F 2 "" H 4300 2950 60 0000 C CNN -F 3 "" H 4300 2950 60 0000 C CNN - 1 4300 2950 - 1 0 0 -1 -$EndComp -$Comp -L d_or U3 -U 1 1 5C9D011F -P 4300 3350 -F 0 "U3" H 4300 3350 60 0000 C CNN -F 1 "d_or" H 4300 3450 60 0000 C CNN -F 2 "" H 4300 3350 60 0000 C CNN -F 3 "" H 4300 3350 60 0000 C CNN - 1 4300 3350 - 1 0 0 -1 -$EndComp -$Comp -L d_or U4 -U 1 1 5C9D0141 -P 5250 3150 -F 0 "U4" H 5250 3150 60 0000 C CNN -F 1 "d_or" H 5250 3250 60 0000 C CNN -F 2 "" H 5250 3150 60 0000 C CNN -F 3 "" H 5250 3150 60 0000 C CNN - 1 5250 3150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4800 3050 4800 2900 -Wire Wire Line - 4800 2900 4750 2900 -Wire Wire Line - 4800 3150 4800 3300 -Wire Wire Line - 4800 3300 4750 3300 -Wire Wire Line - 3350 2850 3850 2850 -Wire Wire Line - 3850 2950 3600 2950 -Wire Wire Line - 3850 3250 3350 3250 -Wire Wire Line - 3600 2950 3600 3000 -Wire Wire Line - 3600 3000 3350 3000 -Wire Wire Line - 3850 3350 3850 3400 -Wire Wire Line - 3850 3400 3350 3400 -Wire Wire Line - 5700 3100 6200 3100 -$Comp -L PORT U1 -U 1 1 5C9D01F4 -P 3100 2850 -F 0 "U1" H 3150 2950 30 0000 C CNN -F 1 "PORT" H 3100 2850 30 0000 C CNN -F 2 "" H 3100 2850 60 0000 C CNN -F 3 "" H 3100 2850 60 0000 C CNN - 1 3100 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9D022F -P 3100 3000 -F 0 "U1" H 3150 3100 30 0000 C CNN -F 1 "PORT" H 3100 3000 30 0000 C CNN -F 2 "" H 3100 3000 60 0000 C CNN -F 3 "" H 3100 3000 60 0000 C CNN - 2 3100 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9D0271 -P 3100 3250 -F 0 "U1" H 3150 3350 30 0000 C CNN -F 1 "PORT" H 3100 3250 30 0000 C CNN -F 2 "" H 3100 3250 60 0000 C CNN -F 3 "" H 3100 3250 60 0000 C CNN - 3 3100 3250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9D0299 -P 3100 3400 -F 0 "U1" H 3150 3500 30 0000 C CNN -F 1 "PORT" H 3100 3400 30 0000 C CNN -F 2 "" H 3100 3400 60 0000 C CNN -F 3 "" H 3100 3400 60 0000 C CNN - 4 3100 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9D02C2 -P 6450 3100 -F 0 "U1" H 6500 3200 30 0000 C CNN -F 1 "PORT" H 6450 3100 30 0000 C CNN -F 2 "" H 6450 3100 60 0000 C CNN -F 3 "" H 6450 3100 60 0000 C CNN - 5 6450 3100 - -1 0 0 1 -$EndComp -Text Notes 3450 2850 0 60 ~ 12 -in1 -Text Notes 3450 3000 0 60 ~ 12 -in2 -Text Notes 3450 3250 0 60 ~ 12 -in3 -Text Notes 3450 3400 0 60 ~ 12 -in4 -Text Notes 5800 3100 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub deleted file mode 100644 index d1fd3a24..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR.sub +++ /dev/null @@ -1,18 +0,0 @@ -* Subcircuit 4_OR -.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or -* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml deleted file mode 100644 index 0683d9eb..00000000 --- a/src/SubcircuitLibrary/4_OR/4_OR_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_OR/analysis b/src/SubcircuitLibrary/4_OR/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4_OR/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and-cache.lib b/src/SubcircuitLibrary/4_and/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/4_and/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4_and/3_and.cir b/src/SubcircuitLibrary/4_and/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/4_and/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/4_and/3_and.cir.out b/src/SubcircuitLibrary/4_and/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/4_and/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4_and/3_and.pro b/src/SubcircuitLibrary/4_and/3_and.pro deleted file mode 100644 index 76df4655..00000000 --- a/src/SubcircuitLibrary/4_and/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4_and/3_and.sch b/src/SubcircuitLibrary/4_and/3_and.sch deleted file mode 100644 index d6ac89f9..00000000 --- a/src/SubcircuitLibrary/4_and/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:3_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -Text Notes 3500 2600 0 60 ~ 12 -in1 -Text Notes 3450 2800 0 60 ~ 12 -in2\n -Text Notes 3500 3100 0 60 ~ 12 -in3 -Text Notes 6100 2850 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/3_and.sub b/src/SubcircuitLibrary/4_and/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/4_and/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/4_and/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and-cache.lib b/src/SubcircuitLibrary/4_and/4_and-cache.lib deleted file mode 100644 index 60f1a83d..00000000 --- a/src/SubcircuitLibrary/4_and/4_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and-RESCUE-4_and -# -DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and-rescue.lib b/src/SubcircuitLibrary/4_and/4_and-rescue.lib deleted file mode 100644 index e3833051..00000000 --- a/src/SubcircuitLibrary/4_and/4_and-rescue.lib +++ /dev/null @@ -1,22 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and-RESCUE-4_and -# -DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4_and/4_and.cir b/src/SubcircuitLibrary/4_and/4_and.cir deleted file mode 100644 index fdf2e107..00000000 --- a/src/SubcircuitLibrary/4_and/4_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and -U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT - -.end diff --git a/src/SubcircuitLibrary/4_and/4_and.cir.out b/src/SubcircuitLibrary/4_and/4_and.cir.out deleted file mode 100644 index f40e5bc6..00000000 --- a/src/SubcircuitLibrary/4_and/4_and.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port -a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4_and/4_and.pro b/src/SubcircuitLibrary/4_and/4_and.pro deleted file mode 100644 index 9c0be79e..00000000 --- a/src/SubcircuitLibrary/4_and/4_and.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=06/01/19 15:08:42 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=4_and-rescue -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/src/SubcircuitLibrary/4_and/4_and.sch b/src/SubcircuitLibrary/4_and/4_and.sch deleted file mode 100644 index f5e8febd..00000000 --- a/src/SubcircuitLibrary/4_and/4_and.sch +++ /dev/null @@ -1,151 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:4_and-rescue -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:4_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and-RESCUE-4_and X1 -U 1 1 5C9A2915 -P 3700 3500 -F 0 "X1" H 4600 3800 60 0000 C CNN -F 1 "3_and" H 4650 4000 60 0000 C CNN -F 2 "" H 3700 3500 60 0000 C CNN -F 3 "" H 3700 3500 60 0000 C CNN - 1 3700 3500 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C9A2940 -P 5450 3400 -F 0 "U2" H 5450 3400 60 0000 C CNN -F 1 "d_and" H 5500 3500 60 0000 C CNN -F 2 "" H 5450 3400 60 0000 C CNN -F 3 "" H 5450 3400 60 0000 C CNN - 1 5450 3400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5000 3100 5000 3300 -Wire Wire Line - 4150 3000 4150 2700 -Wire Wire Line - 4150 2700 3200 2700 -Wire Wire Line - 4150 3100 4000 3100 -Wire Wire Line - 4000 3100 4000 3000 -Wire Wire Line - 4000 3000 3200 3000 -Wire Wire Line - 4150 3200 4150 3300 -Wire Wire Line - 4150 3300 3250 3300 -Wire Wire Line - 5000 3400 5000 3550 -Wire Wire Line - 5000 3550 3250 3550 -Wire Wire Line - 5900 3350 6500 3350 -$Comp -L PORT U1 -U 1 1 5C9A29B1 -P 2950 2700 -F 0 "U1" H 3000 2800 30 0000 C CNN -F 1 "PORT" H 2950 2700 30 0000 C CNN -F 2 "" H 2950 2700 60 0000 C CNN -F 3 "" H 2950 2700 60 0000 C CNN - 1 2950 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A29E9 -P 2950 3000 -F 0 "U1" H 3000 3100 30 0000 C CNN -F 1 "PORT" H 2950 3000 30 0000 C CNN -F 2 "" H 2950 3000 60 0000 C CNN -F 3 "" H 2950 3000 60 0000 C CNN - 2 2950 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A2A0D -P 3000 3300 -F 0 "U1" H 3050 3400 30 0000 C CNN -F 1 "PORT" H 3000 3300 30 0000 C CNN -F 2 "" H 3000 3300 60 0000 C CNN -F 3 "" H 3000 3300 60 0000 C CNN - 3 3000 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2A3C -P 3000 3550 -F 0 "U1" H 3050 3650 30 0000 C CNN -F 1 "PORT" H 3000 3550 30 0000 C CNN -F 2 "" H 3000 3550 60 0000 C CNN -F 3 "" H 3000 3550 60 0000 C CNN - 4 3000 3550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A2A68 -P 6750 3350 -F 0 "U1" H 6800 3450 30 0000 C CNN -F 1 "PORT" H 6750 3350 30 0000 C CNN -F 2 "" H 6750 3350 60 0000 C CNN -F 3 "" H 6750 3350 60 0000 C CNN - 5 6750 3350 - -1 0 0 1 -$EndComp -Text Notes 3450 2650 0 60 ~ 12 -in1 -Text Notes 3450 2950 0 60 ~ 12 -in2 -Text Notes 3500 3300 0 60 ~ 12 -in3 -Text Notes 3500 3550 0 60 ~ 12 -in4 -Text Notes 6150 3350 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4_and/4_and.sub b/src/SubcircuitLibrary/4_and/4_and.sub deleted file mode 100644 index 8663f37e..00000000 --- a/src/SubcircuitLibrary/4_and/4_and.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 4_and -.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and -a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml deleted file mode 100644 index f2ba0130..00000000 --- a/src/SubcircuitLibrary/4_and/4_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_and/analysis b/src/SubcircuitLibrary/4_and/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4_and/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib deleted file mode 100644 index 0a3ccf7f..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir b/src/SubcircuitLibrary/4_bit_FA/3_and.cir deleted file mode 100644 index 15f8954d..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out deleted file mode 100644 index e3c96645..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.pro b/src/SubcircuitLibrary/4_bit_FA/3_and.pro deleted file mode 100644 index 1b535492..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sch b/src/SubcircuitLibrary/4_bit_FA/3_and.sch deleted file mode 100644 index 6c8d3d4a..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and.sch +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and.sub b/src/SubcircuitLibrary/4_bit_FA/3_and.sub deleted file mode 100644 index b949ae4f..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib deleted file mode 100644 index a3c1c972..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir deleted file mode 100644 index 7adbf177..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
-U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
-U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out deleted file mode 100644 index 4388b975..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro b/src/SubcircuitLibrary/4_bit_FA/4_OR.pro deleted file mode 100644 index 8bd4bbf5..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=03/28/19 22:43:48
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch b/src/SubcircuitLibrary/4_bit_FA/4_OR.sch deleted file mode 100644 index 2f28896c..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR.sch +++ /dev/null @@ -1,150 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C9D00E1
-P 4300 2950
-F 0 "U2" H 4300 2950 60 0000 C CNN
-F 1 "d_or" H 4300 3050 60 0000 C CNN
-F 2 "" H 4300 2950 60 0000 C CNN
-F 3 "" H 4300 2950 60 0000 C CNN
- 1 4300 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U3
-U 1 1 5C9D011F
-P 4300 3350
-F 0 "U3" H 4300 3350 60 0000 C CNN
-F 1 "d_or" H 4300 3450 60 0000 C CNN
-F 2 "" H 4300 3350 60 0000 C CNN
-F 3 "" H 4300 3350 60 0000 C CNN
- 1 4300 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C9D0141
-P 5250 3150
-F 0 "U4" H 5250 3150 60 0000 C CNN
-F 1 "d_or" H 5250 3250 60 0000 C CNN
-F 2 "" H 5250 3150 60 0000 C CNN
-F 3 "" H 5250 3150 60 0000 C CNN
- 1 5250 3150
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4800 3050 4800 2900
-Wire Wire Line
- 4800 2900 4750 2900
-Wire Wire Line
- 4800 3150 4800 3300
-Wire Wire Line
- 4800 3300 4750 3300
-Wire Wire Line
- 3350 2850 3850 2850
-Wire Wire Line
- 3850 2950 3600 2950
-Wire Wire Line
- 3850 3250 3350 3250
-Wire Wire Line
- 3600 2950 3600 3000
-Wire Wire Line
- 3600 3000 3350 3000
-Wire Wire Line
- 3850 3350 3850 3400
-Wire Wire Line
- 3850 3400 3350 3400
-Wire Wire Line
- 5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
-P 3100 2850
-F 0 "U1" H 3150 2950 30 0000 C CNN
-F 1 "PORT" H 3100 2850 30 0000 C CNN
-F 2 "" H 3100 2850 60 0000 C CNN
-F 3 "" H 3100 2850 60 0000 C CNN
- 1 3100 2850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9D022F
-P 3100 3000
-F 0 "U1" H 3150 3100 30 0000 C CNN
-F 1 "PORT" H 3100 3000 30 0000 C CNN
-F 2 "" H 3100 3000 60 0000 C CNN
-F 3 "" H 3100 3000 60 0000 C CNN
- 2 3100 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
-P 3100 3250
-F 0 "U1" H 3150 3350 30 0000 C CNN
-F 1 "PORT" H 3100 3250 30 0000 C CNN
-F 2 "" H 3100 3250 60 0000 C CNN
-F 3 "" H 3100 3250 60 0000 C CNN
- 3 3100 3250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
-P 3100 3400
-F 0 "U1" H 3150 3500 30 0000 C CNN
-F 1 "PORT" H 3100 3400 30 0000 C CNN
-F 2 "" H 3100 3400 60 0000 C CNN
-F 3 "" H 3100 3400 60 0000 C CNN
- 4 3100 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30 0000 C CNN
-F 1 "PORT" H 6450 3100 30 0000 C CNN
-F 2 "" H 6450 3100 60 0000 C CNN
-F 3 "" H 6450 3100 60 0000 C CNN
- 5 6450 3100
- -1 0 0 1
-$EndComp
-Text Notes 3450 2850 0 60 ~ 12
-in1
-Text Notes 3450 3000 0 60 ~ 12
-in2
-Text Notes 3450 3250 0 60 ~ 12
-in3
-Text Notes 3450 3400 0 60 ~ 12
-in4
-Text Notes 5800 3100 0 60 ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub b/src/SubcircuitLibrary/4_bit_FA/4_OR.sub deleted file mode 100644 index 53fc8b33..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR.sub +++ /dev/null @@ -1,18 +0,0 @@ -* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml deleted file mode 100644 index 23698d37..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_OR_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib deleted file mode 100644 index 4cf915be..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir b/src/SubcircuitLibrary/4_bit_FA/4_and.cir deleted file mode 100644 index 25e839cd..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
-U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out deleted file mode 100644 index 6e35b18a..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.pro b/src/SubcircuitLibrary/4_bit_FA/4_and.pro deleted file mode 100644 index cc0f1b93..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and.pro +++ /dev/null @@ -1,57 +0,0 @@ -update=03/26/19 18:58:33
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=texas
-LibName2=intel
-LibName3=audio
-LibName4=interface
-LibName5=digital-audio
-LibName6=philips
-LibName7=display
-LibName8=cypress
-LibName9=siliconi
-LibName10=opto
-LibName11=atmel
-LibName12=contrib
-LibName13=valves
-LibName14=eSim_Analog
-LibName15=eSim_Devices
-LibName16=eSim_Digital
-LibName17=eSim_Hybrid
-LibName18=eSim_Miscellaneous
-LibName19=eSim_Plot
-LibName20=eSim_Power
-LibName21=eSim_PSpice
-LibName22=eSim_Sources
-LibName23=eSim_Subckt
-LibName24=eSim_User
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sch b/src/SubcircuitLibrary/4_bit_FA/4_and.sch deleted file mode 100644 index bcc3cecf..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and.sch +++ /dev/null @@ -1,139 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2915
-P 3700 3500
-F 0 "X1" H 4600 3800 60 0000 C CNN
-F 1 "3_and" H 4650 4000 60 0000 C CNN
-F 2 "" H 3700 3500 60 0000 C CNN
-F 3 "" H 3700 3500 60 0000 C CNN
- 1 3700 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2940
-P 5450 3400
-F 0 "U2" H 5450 3400 60 0000 C CNN
-F 1 "d_and" H 5500 3500 60 0000 C CNN
-F 2 "" H 5450 3400 60 0000 C CNN
-F 3 "" H 5450 3400 60 0000 C CNN
- 1 5450 3400
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5000 3100 5000 3300
-Wire Wire Line
- 4150 3000 4150 2700
-Wire Wire Line
- 4150 2700 3200 2700
-Wire Wire Line
- 4150 3100 4000 3100
-Wire Wire Line
- 4000 3100 4000 3000
-Wire Wire Line
- 4000 3000 3200 3000
-Wire Wire Line
- 4150 3200 4150 3300
-Wire Wire Line
- 4150 3300 3250 3300
-Wire Wire Line
- 5000 3400 5000 3550
-Wire Wire Line
- 5000 3550 3250 3550
-Wire Wire Line
- 5900 3350 6500 3350
-$Comp
-L PORT U1
-U 1 1 5C9A29B1
-P 2950 2700
-F 0 "U1" H 3000 2800 30 0000 C CNN
-F 1 "PORT" H 2950 2700 30 0000 C CNN
-F 2 "" H 2950 2700 60 0000 C CNN
-F 3 "" H 2950 2700 60 0000 C CNN
- 1 2950 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A29E9
-P 2950 3000
-F 0 "U1" H 3000 3100 30 0000 C CNN
-F 1 "PORT" H 2950 3000 30 0000 C CNN
-F 2 "" H 2950 3000 60 0000 C CNN
-F 3 "" H 2950 3000 60 0000 C CNN
- 2 2950 3000
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A2A0D
-P 3000 3300
-F 0 "U1" H 3050 3400 30 0000 C CNN
-F 1 "PORT" H 3000 3300 30 0000 C CNN
-F 2 "" H 3000 3300 60 0000 C CNN
-F 3 "" H 3000 3300 60 0000 C CNN
- 3 3000 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2A3C
-P 3000 3550
-F 0 "U1" H 3050 3650 30 0000 C CNN
-F 1 "PORT" H 3000 3550 30 0000 C CNN
-F 2 "" H 3000 3550 60 0000 C CNN
-F 3 "" H 3000 3550 60 0000 C CNN
- 4 3000 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2A68
-P 6750 3350
-F 0 "U1" H 6800 3450 30 0000 C CNN
-F 1 "PORT" H 6750 3350 30 0000 C CNN
-F 2 "" H 6750 3350 60 0000 C CNN
-F 3 "" H 6750 3350 60 0000 C CNN
- 5 6750 3350
- -1 0 0 1
-$EndComp
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and.sub b/src/SubcircuitLibrary/4_bit_FA/4_and.sub deleted file mode 100644 index bf20b628..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 4_and
-.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
-* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
-a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml deleted file mode 100644 index f2ba0130..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib deleted file mode 100644 index f787854a..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA-cache.lib +++ /dev/null @@ -1,172 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_OR
-#
-DEF 4_OR X 0 40 Y Y 1 F N
-F0 "X" 3900 3050 60 H V C CNN
-F1 "4_OR" 3900 3250 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900
-A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150
-A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150
-P 2 0 1 0 3550 2900 3900 2900 N
-P 2 0 1 0 3550 3400 3900 3400 N
-X in1 1 3400 3300 200 R 50 50 1 1 I
-X in2 2 3400 3200 200 R 50 50 1 1 I
-X in3 3 3400 3100 200 R 50 50 1 1 I
-X in4 4 3400 3000 200 R 50 50 1 1 I
-X out 5 4300 3150 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 1500 1050 60 H V C CNN
-F1 "4_and" 1550 1200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900
-P 2 0 1 0 1250 1300 1600 1300 N
-P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N
-X in1 1 1050 1250 200 R 50 50 1 1 I
-X in2 2 1050 1150 200 R 50 50 1 1 I
-X in3 3 1050 1050 200 R 50 50 1 1 I
-X in4 4 1050 950 200 R 50 50 1 1 I
-X out 5 1950 1100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir deleted file mode 100644 index 8fe97f7e..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir +++ /dev/null @@ -1,48 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_bit_FA\4_bit_FA.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:04:20
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U16-Pad2_ d_or
-U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U24-Pad2_ d_and
-U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U17-Pad2_ d_or
-U5 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U26-Pad2_ d_and
-U6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U18-Pad2_ d_or
-U7 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad2_ d_and
-U8 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad1_ d_or
-U9 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U31-Pad2_ d_and
-U16 Net-_U1-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and
-U24 Net-_U16-Pad3_ Net-_U24-Pad2_ Net-_U17-Pad1_ d_or
-U33 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U33-Pad3_ d_or
-U23 Net-_U16-Pad2_ Net-_U23-Pad2_ d_inverter
-U38 Net-_U1-Pad1_ Net-_U33-Pad3_ Net-_U38-Pad3_ d_xor
-U42 Net-_U38-Pad3_ Net-_U1-Pad13_ d_inverter
-U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and
-U26 Net-_U17-Pad3_ Net-_U26-Pad2_ Net-_U18-Pad1_ d_or
-U34 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U34-Pad3_ d_or
-U25 Net-_U17-Pad2_ Net-_U25-Pad2_ d_inverter
-U39 Net-_U17-Pad1_ Net-_U34-Pad3_ Net-_U39-Pad3_ d_xor
-U44 Net-_U39-Pad3_ Net-_U1-Pad10_ d_inverter
-U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and
-U28 Net-_U18-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_or
-U35 Net-_U27-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad3_ d_or
-U27 Net-_U18-Pad2_ Net-_U27-Pad2_ d_inverter
-U40 Net-_U18-Pad1_ Net-_U35-Pad3_ Net-_U40-Pad3_ d_xor
-U45 Net-_U40-Pad3_ Net-_U1-Pad11_ d_inverter
-U31 Net-_U21-Pad2_ Net-_U31-Pad2_ Net-_U31-Pad3_ d_or
-U21 Net-_U10-Pad1_ Net-_U21-Pad2_ d_inverter
-U37 Net-_U28-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_xor
-U43 Net-_U37-Pad3_ Net-_U1-Pad12_ d_inverter
-U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
-U32 Net-_U1-Pad1_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and
-U41 Net-_U32-Pad3_ Net-_U41-Pad2_ Net-_U1-Pad14_ d_or
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
-X1 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U32-Pad2_ 4_and
-X4 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U26-Pad2_ Net-_X3-Pad3_ 3_and
-X2 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_U24-Pad2_ Net-_X2-Pad5_ 4_and
-X3 Net-_U31-Pad2_ Net-_U10-Pad3_ Net-_X3-Pad3_ Net-_X2-Pad5_ Net-_U41-Pad2_ 4_OR
-
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out deleted file mode 100644 index 4d05d64a..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.cir.out +++ /dev/null @@ -1,151 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir
-
-.include 4_and.sub
-.include 3_and.sub
-.include 4_OR.sub
-* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or
-* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and
-* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or
-* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and
-* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or
-* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and
-* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or
-* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and
-* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
-* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or
-* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or
-* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter
-* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor
-* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter
-* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
-* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or
-* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or
-* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
-* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor
-* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter
-* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
-* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or
-* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or
-* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter
-* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor
-* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter
-* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or
-* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter
-* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor
-* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter
-* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and
-x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and
-x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and
-x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR
-a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3
-a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4
-a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5
-a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6
-a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7
-a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8
-a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9
-a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
-a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24
-a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33
-a12 net-_u16-pad2_ net-_u23-pad2_ u23
-a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38
-a14 net-_u38-pad3_ net-_u1-pad13_ u42
-a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
-a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26
-a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34
-a18 net-_u17-pad2_ net-_u25-pad2_ u25
-a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39
-a20 net-_u39-pad3_ net-_u1-pad10_ u44
-a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28
-a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35
-a24 net-_u18-pad2_ net-_u27-pad2_ u27
-a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40
-a26 net-_u40-pad3_ net-_u1-pad11_ u45
-a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31
-a28 net-_u10-pad1_ net-_u21-pad2_ u21
-a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
-a30 net-_u37-pad3_ net-_u1-pad12_ u43
-a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro deleted file mode 100644 index 2d0c38b5..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=03/28/19 23:02:17
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_User
-LibName25=eSim_Subckt
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch deleted file mode 100644 index d3507ac7..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sch +++ /dev/null @@ -1,945 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:4_bit_FA-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_or U2
-U 1 1 5C963B95
-P 3050 3050
-F 0 "U2" H 3050 3050 60 0000 C CNN
-F 1 "d_or" H 3050 3150 60 0000 C CNN
-F 2 "" H 3050 3050 60 0000 C CNN
-F 3 "" H 3050 3050 60 0000 C CNN
- 1 3050 3050
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C963C4C
-P 3050 3450
-F 0 "U3" H 3050 3450 60 0000 C CNN
-F 1 "d_and" H 3100 3550 60 0000 C CNN
-F 2 "" H 3050 3450 60 0000 C CNN
-F 3 "" H 3050 3450 60 0000 C CNN
- 1 3050 3450
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U4
-U 1 1 5C963CD9
-P 3050 4000
-F 0 "U4" H 3050 4000 60 0000 C CNN
-F 1 "d_or" H 3050 4100 60 0000 C CNN
-F 2 "" H 3050 4000 60 0000 C CNN
-F 3 "" H 3050 4000 60 0000 C CNN
- 1 3050 4000
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U5
-U 1 1 5C963CDF
-P 3050 4400
-F 0 "U5" H 3050 4400 60 0000 C CNN
-F 1 "d_and" H 3100 4500 60 0000 C CNN
-F 2 "" H 3050 4400 60 0000 C CNN
-F 3 "" H 3050 4400 60 0000 C CNN
- 1 3050 4400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5C963D79
-P 3050 4850
-F 0 "U6" H 3050 4850 60 0000 C CNN
-F 1 "d_or" H 3050 4950 60 0000 C CNN
-F 2 "" H 3050 4850 60 0000 C CNN
-F 3 "" H 3050 4850 60 0000 C CNN
- 1 3050 4850
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U7
-U 1 1 5C963D7F
-P 3050 5250
-F 0 "U7" H 3050 5250 60 0000 C CNN
-F 1 "d_and" H 3100 5350 60 0000 C CNN
-F 2 "" H 3050 5250 60 0000 C CNN
-F 3 "" H 3050 5250 60 0000 C CNN
- 1 3050 5250
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U8
-U 1 1 5C963D85
-P 3050 5800
-F 0 "U8" H 3050 5800 60 0000 C CNN
-F 1 "d_or" H 3050 5900 60 0000 C CNN
-F 2 "" H 3050 5800 60 0000 C CNN
-F 3 "" H 3050 5800 60 0000 C CNN
- 1 3050 5800
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U9
-U 1 1 5C963D8B
-P 3050 6200
-F 0 "U9" H 3050 6200 60 0000 C CNN
-F 1 "d_and" H 3100 6300 60 0000 C CNN
-F 2 "" H 3050 6200 60 0000 C CNN
-F 3 "" H 3050 6200 60 0000 C CNN
- 1 3050 6200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U16
-U 1 1 5C963D9B
-P 5550 3200
-F 0 "U16" H 5550 3200 60 0000 C CNN
-F 1 "d_and" H 5600 3300 60 0000 C CNN
-F 2 "" H 5550 3200 60 0000 C CNN
-F 3 "" H 5550 3200 60 0000 C CNN
- 1 5550 3200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U24
-U 1 1 5C963DFB
-P 6450 3400
-F 0 "U24" H 6450 3400 60 0000 C CNN
-F 1 "d_or" H 6450 3500 60 0000 C CNN
-F 2 "" H 6450 3400 60 0000 C CNN
-F 3 "" H 6450 3400 60 0000 C CNN
- 1 6450 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U33
-U 1 1 5C963F8F
-P 7800 3450
-F 0 "U33" H 7800 3450 60 0000 C CNN
-F 1 "d_or" H 7800 3550 60 0000 C CNN
-F 2 "" H 7800 3450 60 0000 C CNN
-F 3 "" H 7800 3450 60 0000 C CNN
- 1 7800 3450
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U23
-U 1 1 5C963FFF
-P 6450 2950
-F 0 "U23" H 6450 2850 60 0000 C CNN
-F 1 "d_inverter" H 6450 3100 60 0000 C CNN
-F 2 "" H 6500 2900 60 0000 C CNN
-F 3 "" H 6500 2900 60 0000 C CNN
- 1 6450 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U38
-U 1 1 5C9640A4
-P 8900 3400
-F 0 "U38" H 8900 3400 60 0000 C CNN
-F 1 "d_xor" H 8950 3500 47 0000 C CNN
-F 2 "" H 8900 3400 60 0000 C CNN
-F 3 "" H 8900 3400 60 0000 C CNN
- 1 8900 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U42
-U 1 1 5C96410A
-P 9750 3350
-F 0 "U42" H 9750 3250 60 0000 C CNN
-F 1 "d_inverter" H 9750 3500 60 0000 C CNN
-F 2 "" H 9800 3300 60 0000 C CNN
-F 3 "" H 9800 3300 60 0000 C CNN
- 1 9750 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U17
-U 1 1 5C964222
-P 5550 4150
-F 0 "U17" H 5550 4150 60 0000 C CNN
-F 1 "d_and" H 5600 4250 60 0000 C CNN
-F 2 "" H 5550 4150 60 0000 C CNN
-F 3 "" H 5550 4150 60 0000 C CNN
- 1 5550 4150
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U26
-U 1 1 5C964228
-P 6450 4350
-F 0 "U26" H 6450 4350 60 0000 C CNN
-F 1 "d_or" H 6450 4450 60 0000 C CNN
-F 2 "" H 6450 4350 60 0000 C CNN
-F 3 "" H 6450 4350 60 0000 C CNN
- 1 6450 4350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U34
-U 1 1 5C96422E
-P 7800 4400
-F 0 "U34" H 7800 4400 60 0000 C CNN
-F 1 "d_or" H 7800 4500 60 0000 C CNN
-F 2 "" H 7800 4400 60 0000 C CNN
-F 3 "" H 7800 4400 60 0000 C CNN
- 1 7800 4400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U25
-U 1 1 5C964234
-P 6450 3900
-F 0 "U25" H 6450 3800 60 0000 C CNN
-F 1 "d_inverter" H 6450 4050 60 0000 C CNN
-F 2 "" H 6500 3850 60 0000 C CNN
-F 3 "" H 6500 3850 60 0000 C CNN
- 1 6450 3900
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U39
-U 1 1 5C96423A
-P 8900 4350
-F 0 "U39" H 8900 4350 60 0000 C CNN
-F 1 "d_xor" H 8950 4450 47 0000 C CNN
-F 2 "" H 8900 4350 60 0000 C CNN
-F 3 "" H 8900 4350 60 0000 C CNN
- 1 8900 4350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U44
-U 1 1 5C964240
-P 9800 4300
-F 0 "U44" H 9800 4200 60 0000 C CNN
-F 1 "d_inverter" H 9800 4450 60 0000 C CNN
-F 2 "" H 9850 4250 60 0000 C CNN
-F 3 "" H 9850 4250 60 0000 C CNN
- 1 9800 4300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U18
-U 1 1 5C964304
-P 5600 4950
-F 0 "U18" H 5600 4950 60 0000 C CNN
-F 1 "d_and" H 5650 5050 60 0000 C CNN
-F 2 "" H 5600 4950 60 0000 C CNN
-F 3 "" H 5600 4950 60 0000 C CNN
- 1 5600 4950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U28
-U 1 1 5C96430A
-P 6500 5150
-F 0 "U28" H 6500 5150 60 0000 C CNN
-F 1 "d_or" H 6500 5250 60 0000 C CNN
-F 2 "" H 6500 5150 60 0000 C CNN
-F 3 "" H 6500 5150 60 0000 C CNN
- 1 6500 5150
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U35
-U 1 1 5C964310
-P 7850 5200
-F 0 "U35" H 7850 5200 60 0000 C CNN
-F 1 "d_or" H 7850 5300 60 0000 C CNN
-F 2 "" H 7850 5200 60 0000 C CNN
-F 3 "" H 7850 5200 60 0000 C CNN
- 1 7850 5200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U27
-U 1 1 5C964316
-P 6500 4700
-F 0 "U27" H 6500 4600 60 0000 C CNN
-F 1 "d_inverter" H 6500 4850 60 0000 C CNN
-F 2 "" H 6550 4650 60 0000 C CNN
-F 3 "" H 6550 4650 60 0000 C CNN
- 1 6500 4700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U40
-U 1 1 5C96431C
-P 8950 5150
-F 0 "U40" H 8950 5150 60 0000 C CNN
-F 1 "d_xor" H 9000 5250 47 0000 C CNN
-F 2 "" H 8950 5150 60 0000 C CNN
-F 3 "" H 8950 5150 60 0000 C CNN
- 1 8950 5150
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U45
-U 1 1 5C964322
-P 9850 5100
-F 0 "U45" H 9850 5000 60 0000 C CNN
-F 1 "d_inverter" H 9850 5250 60 0000 C CNN
-F 2 "" H 9900 5050 60 0000 C CNN
-F 3 "" H 9900 5050 60 0000 C CNN
- 1 9850 5100
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U31
-U 1 1 5C964476
-P 7750 6200
-F 0 "U31" H 7750 6200 60 0000 C CNN
-F 1 "d_or" H 7750 6300 60 0000 C CNN
-F 2 "" H 7750 6200 60 0000 C CNN
-F 3 "" H 7750 6200 60 0000 C CNN
- 1 7750 6200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U21
-U 1 1 5C96447C
-P 6400 5700
-F 0 "U21" H 6400 5600 60 0000 C CNN
-F 1 "d_inverter" H 6400 5850 60 0000 C CNN
-F 2 "" H 6450 5650 60 0000 C CNN
-F 3 "" H 6450 5650 60 0000 C CNN
- 1 6400 5700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U37
-U 1 1 5C964482
-P 8850 6150
-F 0 "U37" H 8850 6150 60 0000 C CNN
-F 1 "d_xor" H 8900 6250 47 0000 C CNN
-F 2 "" H 8850 6150 60 0000 C CNN
-F 3 "" H 8850 6150 60 0000 C CNN
- 1 8850 6150
- 1 0 0 -1
-$EndComp
-$Comp
-L d_inverter U43
-U 1 1 5C964488
-P 9750 6100
-F 0 "U43" H 9750 6000 60 0000 C CNN
-F 1 "d_inverter" H 9750 6250 60 0000 C CNN
-F 2 "" H 9800 6050 60 0000 C CNN
-F 3 "" H 9800 6050 60 0000 C CNN
- 1 9750 6100
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U10
-U 1 1 5C966120
-P 5450 1650
-F 0 "U10" H 5450 1650 60 0000 C CNN
-F 1 "d_and" H 5500 1750 60 0000 C CNN
-F 2 "" H 5450 1650 60 0000 C CNN
-F 3 "" H 5450 1650 60 0000 C CNN
- 1 5450 1650
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U32
-U 1 1 5C968A9C
-P 7800 1150
-F 0 "U32" H 7800 1150 60 0000 C CNN
-F 1 "d_and" H 7850 1250 60 0000 C CNN
-F 2 "" H 7800 1150 60 0000 C CNN
-F 3 "" H 7800 1150 60 0000 C CNN
- 1 7800 1150
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U41
-U 1 1 5C968DBD
-P 9400 1500
-F 0 "U41" H 9400 1500 60 0000 C CNN
-F 1 "d_or" H 9400 1600 60 0000 C CNN
-F 2 "" H 9400 1500 60 0000 C CNN
-F 3 "" H 9400 1500 60 0000 C CNN
- 1 9400 1500
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 9450 3350 9350 3350
-Wire Wire Line
- 6750 2950 7350 2950
-Wire Wire Line
- 7350 2950 7350 3350
-Wire Wire Line
- 6000 3150 6000 3300
-Wire Wire Line
- 9500 4300 9350 4300
-Wire Wire Line
- 9550 5100 9400 5100
-Wire Wire Line
- 9450 6100 9300 6100
-Wire Wire Line
- 7350 4300 7350 3900
-Wire Wire Line
- 7350 3900 6750 3900
-Wire Wire Line
- 7400 5100 7400 4700
-Wire Wire Line
- 7400 4700 6800 4700
-Wire Wire Line
- 7300 6100 7300 5700
-Wire Wire Line
- 7300 5700 6700 5700
-Wire Wire Line
- 6050 4900 6050 5050
-Wire Wire Line
- 6000 4100 6000 4250
-Wire Wire Line
- 8250 3400 8450 3400
-Wire Wire Line
- 8250 4350 8450 4350
-Wire Wire Line
- 8200 6150 8400 6150
-Wire Wire Line
- 8500 5150 8300 5150
-Wire Wire Line
- 8450 2700 8450 3300
-Wire Wire Line
- 3400 2700 8450 2700
-Wire Wire Line
- 4950 2700 4950 3100
-Wire Wire Line
- 4950 3100 5100 3100
-Wire Wire Line
- 3500 2950 6150 2950
-Wire Wire Line
- 3500 2950 3500 3000
-Wire Wire Line
- 5100 3200 4850 3200
-Wire Wire Line
- 4850 3200 4850 2950
-Connection ~ 4850 2950
-Wire Wire Line
- 3500 3400 6000 3400
-Wire Wire Line
- 5850 3400 5850 3500
-Wire Wire Line
- 5850 3500 7350 3500
-Wire Wire Line
- 7350 3500 7350 3450
-Connection ~ 5850 3400
-Wire Wire Line
- 5100 4050 5000 4050
-Wire Wire Line
- 5000 4050 5000 3700
-Wire Wire Line
- 5000 3700 8400 3700
-Wire Wire Line
- 8400 3700 8400 4250
-Wire Wire Line
- 8400 4250 8450 4250
-Wire Wire Line
- 6900 3350 6900 3700
-Connection ~ 6900 3700
-Wire Wire Line
- 3500 3900 6150 3900
-Wire Wire Line
- 3500 3900 3500 3950
-Wire Wire Line
- 5100 4150 4950 4150
-Wire Wire Line
- 4950 4150 4950 3900
-Connection ~ 4950 3900
-Wire Wire Line
- 3500 4350 6000 4350
-Wire Wire Line
- 7350 4400 7350 4450
-Wire Wire Line
- 7350 4450 5850 4450
-Wire Wire Line
- 5850 4450 5850 4350
-Connection ~ 5850 4350
-Wire Wire Line
- 8500 5050 8400 5050
-Wire Wire Line
- 8400 5050 8400 4500
-Wire Wire Line
- 8400 4500 5050 4500
-Wire Wire Line
- 5050 4500 5050 4850
-Wire Wire Line
- 5050 4850 5150 4850
-Wire Wire Line
- 6900 4300 7000 4300
-Wire Wire Line
- 7000 4300 7000 4500
-Connection ~ 7000 4500
-Wire Wire Line
- 3500 4700 6200 4700
-Wire Wire Line
- 3500 4700 3500 4800
-Wire Wire Line
- 5150 4950 4950 4950
-Wire Wire Line
- 4950 4950 4950 4700
-Connection ~ 4950 4700
-Wire Wire Line
- 3500 5150 6050 5150
-Wire Wire Line
- 3500 5150 3500 5200
-Wire Wire Line
- 7400 5200 7400 5250
-Wire Wire Line
- 7400 5250 5900 5250
-Wire Wire Line
- 5900 5250 5900 5150
-Connection ~ 5900 5150
-Wire Wire Line
- 3500 5700 6100 5700
-Wire Wire Line
- 3500 5700 3500 5750
-Wire Wire Line
- 3500 6150 7100 6150
-Wire Wire Line
- 8250 5500 8250 6050
-Wire Wire Line
- 8250 6050 8400 6050
-Wire Wire Line
- 7100 6150 7100 6200
-Wire Wire Line
- 7100 6200 7300 6200
-Wire Wire Line
- 8250 5500 7050 5500
-Wire Wire Line
- 7050 5500 7050 5100
-Wire Wire Line
- 7050 5100 6950 5100
-Wire Wire Line
- 2000 2950 2600 2950
-Wire Wire Line
- 2000 3450 2600 3450
-Wire Wire Line
- 2600 3050 2350 3050
-Wire Wire Line
- 2350 3050 2350 3450
-Connection ~ 2350 3450
-Wire Wire Line
- 2600 3350 2500 3350
-Wire Wire Line
- 2500 3350 2500 2950
-Connection ~ 2500 2950
-Wire Wire Line
- 2000 3900 2600 3900
-Wire Wire Line
- 2000 4400 2600 4400
-Wire Wire Line
- 2600 4300 2450 4300
-Wire Wire Line
- 2450 4300 2450 3900
-Connection ~ 2450 3900
-Wire Wire Line
- 2600 4000 2350 4000
-Wire Wire Line
- 2350 4000 2350 4400
-Connection ~ 2350 4400
-Wire Wire Line
- 2000 4750 2600 4750
-Wire Wire Line
- 2000 5250 2600 5250
-Wire Wire Line
- 2600 4850 2350 4850
-Wire Wire Line
- 2350 4850 2350 5250
-Connection ~ 2350 5250
-Wire Wire Line
- 2600 5150 2450 5150
-Wire Wire Line
- 2450 5150 2450 4750
-Connection ~ 2450 4750
-Wire Wire Line
- 2050 5700 2600 5700
-Wire Wire Line
- 2100 6200 2600 6200
-Wire Wire Line
- 2600 6100 2450 6100
-Wire Wire Line
- 2450 6100 2450 5700
-Connection ~ 2450 5700
-Wire Wire Line
- 2600 5800 2500 5800
-Wire Wire Line
- 2500 5800 2500 6200
-Connection ~ 2500 6200
-Wire Wire Line
- 4600 3400 4600 2500
-Wire Wire Line
- 4600 2500 5450 2500
-Connection ~ 4600 3400
-Wire Wire Line
- 4400 2400 5450 2400
-Wire Wire Line
- 4400 1200 4400 3900
-Wire Wire Line
- 4500 2950 4500 1300
-Wire Wire Line
- 4500 1300 5450 1300
-Connection ~ 4500 2950
-Wire Wire Line
- 4100 2300 5450 2300
-Wire Wire Line
- 3800 2200 5450 2200
-Wire Wire Line
- 3800 1000 3800 5700
-Connection ~ 3800 5700
-Wire Wire Line
- 5950 2100 4300 2100
-Wire Wire Line
- 4300 2100 4300 4350
-Connection ~ 4300 4350
-Connection ~ 4400 3900
-Wire Wire Line
- 4100 2300 4100 4700
-Connection ~ 4100 4700
-Wire Wire Line
- 4100 2000 5950 2000
-Wire Wire Line
- 4100 1100 4100 2350
-Connection ~ 4100 2350
-Wire Wire Line
- 3800 1900 5950 1900
-Connection ~ 3800 2200
-Wire Wire Line
- 5000 1550 3800 1550
-Connection ~ 3800 1900
-Wire Wire Line
- 5000 1650 3950 1650
-Wire Wire Line
- 3950 1650 3950 5150
-Connection ~ 3950 5150
-Wire Wire Line
- 4400 1200 5450 1200
-Connection ~ 4400 2400
-Wire Wire Line
- 4100 1100 5450 1100
-Connection ~ 4100 2000
-Wire Wire Line
- 3800 1000 5450 1000
-Connection ~ 3800 1550
-Wire Wire Line
- 5900 1600 7550 1600
-Wire Wire Line
- 7150 900 7150 1500
-Wire Wire Line
- 7150 900 3700 900
-Wire Wire Line
- 3700 900 3700 6150
-Connection ~ 3700 6150
-Wire Wire Line
- 6350 1150 7350 1150
-Wire Wire Line
- 7350 750 7350 1050
-Wire Wire Line
- 2000 750 7350 750
-Wire Wire Line
- 8950 1500 8950 1750
-Wire Wire Line
- 8950 1400 8950 1100
-Wire Wire Line
- 8950 1100 8250 1100
-Wire Wire Line
- 9850 1450 10500 1450
-Wire Wire Line
- 10050 3350 10450 3350
-Wire Wire Line
- 3400 750 3400 2700
-Connection ~ 4950 2700
-Connection ~ 3400 750
-Wire Wire Line
- 10100 4300 10400 4300
-Wire Wire Line
- 10150 5100 10400 5100
-Wire Wire Line
- 10050 6100 10400 6100
-$Comp
-L PORT U1
-U 1 1 5C969A23
-P 1750 750
-F 0 "U1" H 1800 850 30 0000 C CNN
-F 1 "PORT" H 1750 750 30 0000 C CNN
-F 2 "" H 1750 750 60 0000 C CNN
-F 3 "" H 1750 750 60 0000 C CNN
- 1 1750 750
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C969AF9
-P 1750 2950
-F 0 "U1" H 1800 3050 30 0000 C CNN
-F 1 "PORT" H 1750 2950 30 0000 C CNN
-F 2 "" H 1750 2950 60 0000 C CNN
-F 3 "" H 1750 2950 60 0000 C CNN
- 2 1750 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C969BCD
-P 1750 3450
-F 0 "U1" H 1800 3550 30 0000 C CNN
-F 1 "PORT" H 1750 3450 30 0000 C CNN
-F 2 "" H 1750 3450 60 0000 C CNN
-F 3 "" H 1750 3450 60 0000 C CNN
- 3 1750 3450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C969C7A
-P 1750 3900
-F 0 "U1" H 1800 4000 30 0000 C CNN
-F 1 "PORT" H 1750 3900 30 0000 C CNN
-F 2 "" H 1750 3900 60 0000 C CNN
-F 3 "" H 1750 3900 60 0000 C CNN
- 4 1750 3900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C969D28
-P 1750 4400
-F 0 "U1" H 1800 4500 30 0000 C CNN
-F 1 "PORT" H 1750 4400 30 0000 C CNN
-F 2 "" H 1750 4400 60 0000 C CNN
-F 3 "" H 1750 4400 60 0000 C CNN
- 5 1750 4400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C969DDF
-P 1750 4750
-F 0 "U1" H 1800 4850 30 0000 C CNN
-F 1 "PORT" H 1750 4750 30 0000 C CNN
-F 2 "" H 1750 4750 60 0000 C CNN
-F 3 "" H 1750 4750 60 0000 C CNN
- 6 1750 4750
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C969E93
-P 1750 5250
-F 0 "U1" H 1800 5350 30 0000 C CNN
-F 1 "PORT" H 1750 5250 30 0000 C CNN
-F 2 "" H 1750 5250 60 0000 C CNN
-F 3 "" H 1750 5250 60 0000 C CNN
- 7 1750 5250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C969F4E
-P 1800 5700
-F 0 "U1" H 1850 5800 30 0000 C CNN
-F 1 "PORT" H 1800 5700 30 0000 C CNN
-F 2 "" H 1800 5700 60 0000 C CNN
-F 3 "" H 1800 5700 60 0000 C CNN
- 8 1800 5700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C96A00E
-P 1850 6200
-F 0 "U1" H 1900 6300 30 0000 C CNN
-F 1 "PORT" H 1850 6200 30 0000 C CNN
-F 2 "" H 1850 6200 60 0000 C CNN
-F 3 "" H 1850 6200 60 0000 C CNN
- 9 1850 6200
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 14 1 5C96A0CF
-P 10750 1450
-F 0 "U1" H 10800 1550 30 0000 C CNN
-F 1 "PORT" H 10750 1450 30 0000 C CNN
-F 2 "" H 10750 1450 60 0000 C CNN
-F 3 "" H 10750 1450 60 0000 C CNN
- 14 10750 1450
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 13 1 5C96A273
-P 10700 3350
-F 0 "U1" H 10750 3450 30 0000 C CNN
-F 1 "PORT" H 10700 3350 30 0000 C CNN
-F 2 "" H 10700 3350 60 0000 C CNN
-F 3 "" H 10700 3350 60 0000 C CNN
- 13 10700 3350
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C96A464
-P 10650 4300
-F 0 "U1" H 10700 4400 30 0000 C CNN
-F 1 "PORT" H 10650 4300 30 0000 C CNN
-F 2 "" H 10650 4300 60 0000 C CNN
-F 3 "" H 10650 4300 60 0000 C CNN
- 10 10650 4300
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 11 1 5C96A53A
-P 10650 5100
-F 0 "U1" H 10700 5200 30 0000 C CNN
-F 1 "PORT" H 10650 5100 30 0000 C CNN
-F 2 "" H 10650 5100 60 0000 C CNN
-F 3 "" H 10650 5100 60 0000 C CNN
- 11 10650 5100
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 12 1 5C96A619
-P 10650 6100
-F 0 "U1" H 10700 6200 30 0000 C CNN
-F 1 "PORT" H 10650 6100 30 0000 C CNN
-F 2 "" H 10650 6100 60 0000 C CNN
-F 3 "" H 10650 6100 60 0000 C CNN
- 12 10650 6100
- -1 0 0 1
-$EndComp
-Text Notes 10200 3350 0 60 ~ 12
-S0
-Text Notes 10200 4300 0 60 ~ 12
-S1\n
-Text Notes 10200 5100 0 60 ~ 12
-S2
-Text Notes 10150 6100 0 60 ~ 12
-S3
-Text Notes 10050 1450 0 60 ~ 12
-Cout\n
-Text Notes 2250 750 0 60 ~ 12
-Cin\n
-Text Notes 2050 2950 0 60 ~ 12
-A0\n
-Text Notes 2050 3450 0 60 ~ 12
-B0\n
-Text Notes 2050 3900 0 60 ~ 12
-A1
-Text Notes 2050 4400 0 60 ~ 12
-B1
-Text Notes 2050 4750 0 60 ~ 12
-A2
-Text Notes 2050 5250 0 60 ~ 12
-B2
-Text Notes 2100 5700 0 60 ~ 12
-A3
-Text Notes 2150 6200 0 60 ~ 12
-B3
-$Comp
-L 4_and X1
-U 1 1 5C9D037C
-P 4400 2250
-F 0 "X1" H 5900 3300 60 0000 C CNN
-F 1 "4_and" H 5950 3450 60 0000 C CNN
-F 2 "" H 4400 2250 60 0000 C CNN
-F 3 "" H 4400 2250 60 0000 C CNN
- 1 4400 2250
- 1 0 0 -1
-$EndComp
-$Comp
-L 3_and X4
-U 1 1 5C9D0A45
-P 5500 2400
-F 0 "X4" H 6400 2700 60 0000 C CNN
-F 1 "3_and" H 6450 2900 60 0000 C CNN
-F 2 "" H 5500 2400 60 0000 C CNN
-F 3 "" H 5500 2400 60 0000 C CNN
- 1 5500 2400
- 1 0 0 -1
-$EndComp
-$Comp
-L 4_and X2
-U 1 1 5C9D0E20
-P 4400 3450
-F 0 "X2" H 5900 4500 60 0000 C CNN
-F 1 "4_and" H 5950 4650 60 0000 C CNN
-F 2 "" H 4400 3450 60 0000 C CNN
-F 3 "" H 4400 3450 60 0000 C CNN
- 1 4400 3450
- 1 0 0 -1
-$EndComp
-$Comp
-L 4_OR X3
-U 1 1 5C9D1513
-P 4450 4900
-F 0 "X3" H 8350 7950 60 0000 C CNN
-F 1 "4_OR" H 8350 8150 60 0000 C CNN
-F 2 "" H 4450 4900 60 0000 C CNN
-F 3 "" H 4450 4900 60 0000 C CNN
- 1 4450 4900
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 8950 1750 8750 1750
-Wire Wire Line
- 7150 1500 7850 1500
-Wire Wire Line
- 7850 1500 7850 1600
-Wire Wire Line
- 7550 1600 7550 1700
-Wire Wire Line
- 7550 1700 7850 1700
-Wire Wire Line
- 6800 2000 6800 1800
-Wire Wire Line
- 6800 1800 7850 1800
-Wire Wire Line
- 6350 2350 7850 2350
-Wire Wire Line
- 7850 2350 7850 1900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub deleted file mode 100644 index 2f2bc4ef..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA.sub +++ /dev/null @@ -1,145 +0,0 @@ -* Subcircuit 4_bit_FA
-.subckt 4_bit_FA net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
-* c:\users\malli\esim\src\subcircuitlibrary\4_bit_fa\4_bit_fa.cir
-.include 4_and.sub
-.include 3_and.sub
-.include 4_OR.sub
-* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u16-pad2_ d_or
-* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u24-pad2_ d_and
-* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u17-pad2_ d_or
-* u5 net-_u1-pad4_ net-_u1-pad5_ net-_u26-pad2_ d_and
-* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u18-pad2_ d_or
-* u7 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad2_ d_and
-* u8 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad1_ d_or
-* u9 net-_u1-pad8_ net-_u1-pad9_ net-_u31-pad2_ d_and
-* u16 net-_u1-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
-* u24 net-_u16-pad3_ net-_u24-pad2_ net-_u17-pad1_ d_or
-* u33 net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad3_ d_or
-* u23 net-_u16-pad2_ net-_u23-pad2_ d_inverter
-* u38 net-_u1-pad1_ net-_u33-pad3_ net-_u38-pad3_ d_xor
-* u42 net-_u38-pad3_ net-_u1-pad13_ d_inverter
-* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and
-* u26 net-_u17-pad3_ net-_u26-pad2_ net-_u18-pad1_ d_or
-* u34 net-_u25-pad2_ net-_u26-pad2_ net-_u34-pad3_ d_or
-* u25 net-_u17-pad2_ net-_u25-pad2_ d_inverter
-* u39 net-_u17-pad1_ net-_u34-pad3_ net-_u39-pad3_ d_xor
-* u44 net-_u39-pad3_ net-_u1-pad10_ d_inverter
-* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
-* u28 net-_u18-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_or
-* u35 net-_u27-pad2_ net-_u10-pad2_ net-_u35-pad3_ d_or
-* u27 net-_u18-pad2_ net-_u27-pad2_ d_inverter
-* u40 net-_u18-pad1_ net-_u35-pad3_ net-_u40-pad3_ d_xor
-* u45 net-_u40-pad3_ net-_u1-pad11_ d_inverter
-* u31 net-_u21-pad2_ net-_u31-pad2_ net-_u31-pad3_ d_or
-* u21 net-_u10-pad1_ net-_u21-pad2_ d_inverter
-* u37 net-_u28-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_xor
-* u43 net-_u37-pad3_ net-_u1-pad12_ d_inverter
-* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u32 net-_u1-pad1_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u41 net-_u32-pad3_ net-_u41-pad2_ net-_u1-pad14_ d_or
-x1 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u16-pad2_ net-_u32-pad2_ 4_and
-x4 net-_u10-pad1_ net-_u18-pad2_ net-_u26-pad2_ net-_x3-pad3_ 3_and
-x2 net-_u10-pad1_ net-_u18-pad2_ net-_u17-pad2_ net-_u24-pad2_ net-_x2-pad5_ 4_and
-x3 net-_u31-pad2_ net-_u10-pad3_ net-_x3-pad3_ net-_x2-pad5_ net-_u41-pad2_ 4_OR
-a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u16-pad2_ u2
-a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u24-pad2_ u3
-a3 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u17-pad2_ u4
-a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u26-pad2_ u5
-a5 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u18-pad2_ u6
-a6 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad2_ u7
-a7 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad1_ u8
-a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u31-pad2_ u9
-a9 [net-_u1-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
-a10 [net-_u16-pad3_ net-_u24-pad2_ ] net-_u17-pad1_ u24
-a11 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u33-pad3_ u33
-a12 net-_u16-pad2_ net-_u23-pad2_ u23
-a13 [net-_u1-pad1_ net-_u33-pad3_ ] net-_u38-pad3_ u38
-a14 net-_u38-pad3_ net-_u1-pad13_ u42
-a15 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
-a16 [net-_u17-pad3_ net-_u26-pad2_ ] net-_u18-pad1_ u26
-a17 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u34-pad3_ u34
-a18 net-_u17-pad2_ net-_u25-pad2_ u25
-a19 [net-_u17-pad1_ net-_u34-pad3_ ] net-_u39-pad3_ u39
-a20 net-_u39-pad3_ net-_u1-pad10_ u44
-a21 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
-a22 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28
-a23 [net-_u27-pad2_ net-_u10-pad2_ ] net-_u35-pad3_ u35
-a24 net-_u18-pad2_ net-_u27-pad2_ u27
-a25 [net-_u18-pad1_ net-_u35-pad3_ ] net-_u40-pad3_ u40
-a26 net-_u40-pad3_ net-_u1-pad11_ u45
-a27 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u31-pad3_ u31
-a28 net-_u10-pad1_ net-_u21-pad2_ u21
-a29 [net-_u28-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
-a30 net-_u37-pad3_ net-_u1-pad12_ u43
-a31 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a32 [net-_u1-pad1_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a33 [net-_u32-pad3_ net-_u41-pad2_ ] net-_u1-pad14_ u41
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u24 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u38 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u42 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u26 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u34 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u39 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u44 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u28 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u35 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u40 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u45 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u31 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u21 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u37 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u41 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4_bit_FA
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml b/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml deleted file mode 100644 index 49a53e5c..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/4_bit_FA_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u9><u16 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u24 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u24><u33 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u33><u23 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u23><u38 name="type">d_xor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u38><u42 name="type">d_inverter<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u42><u17 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u26 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u26><u34 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u34><u25 name="type">d_inverter<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u25><u39 name="type">d_xor<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u39><u44 name="type">d_inverter<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u44><u18 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u18><u28 name="type">d_or<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u28><u35 name="type">d_or<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u35><u27 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u27><u40 name="type">d_xor<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u40><u45 name="type">d_inverter<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u45><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u21 name="type">d_inverter<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u21><u37 name="type">d_xor<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u37><u43 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u43><u14 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u19><u22 name="type">d_and<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u13><u20 name="type">d_and<field115 name="Enter Fall Delay (default=1.0e-9)" /><field116 name="Enter Input Load (default=1.0e-12)" /><field117 name="Enter Rise Delay (default=1.0e-9)" /></u20><u29 name="type">d_or<field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /></u29><u36 name="type">d_or<field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /><field123 name="Enter Rise Delay (default=1.0e-9)" /></u36><u30 name="type">d_or<field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /><field126 name="Enter Rise Delay (default=1.0e-9)" /></u30><u32 name="type">d_and<field127 name="Enter Fall Delay (default=1.0e-9)" /><field128 name="Enter Input Load (default=1.0e-12)" /><field129 name="Enter Rise Delay (default=1.0e-9)" /></u32><u41 name="type">d_or<field130 name="Enter Fall Delay (default=1.0e-9)" /><field131 name="Enter Input Load (default=1.0e-12)" /><field132 name="Enter Rise Delay (default=1.0e-9)" /></u41></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x1><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4_bit_FA/analysis b/src/SubcircuitLibrary/4_bit_FA/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4_bit_FA/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir b/src/SubcircuitLibrary/4to16_demux/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out b/src/SubcircuitLibrary/4to16_demux/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.pro b/src/SubcircuitLibrary/4to16_demux/3_and.pro deleted file mode 100644 index 76df4655..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sch b/src/SubcircuitLibrary/4to16_demux/3_and.sch deleted file mode 100644 index d6ac89f9..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:3_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -Text Notes 3500 2600 0 60 ~ 12 -in1 -Text Notes 3450 2800 0 60 ~ 12 -in2\n -Text Notes 3500 3100 0 60 ~ 12 -in3 -Text Notes 6100 2850 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/3_and.sub b/src/SubcircuitLibrary/4to16_demux/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/4to16_demux/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib b/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib deleted file mode 100644 index 898ea926..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux-cache.lib +++ /dev/null @@ -1,97 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 5_nand -# -DEF 5_nand X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_nand" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_nor -# -DEF d_nor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nor" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir deleted file mode 100644 index c97c2f8b..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir +++ /dev/null @@ -1,32 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 17:01:07 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U3 Net-_U1-Pad23_ Net-_U3-Pad2_ d_inverter -U4 Net-_U1-Pad22_ Net-_U4-Pad2_ d_inverter -U5 Net-_U1-Pad21_ Net-_U5-Pad2_ d_inverter -U6 Net-_U1-Pad20_ Net-_U6-Pad2_ d_inverter -U2 Net-_U1-Pad19_ Net-_U1-Pad18_ Net-_U2-Pad3_ d_nor -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT -X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad1_ 5_nand -X2 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad2_ 5_nand -X3 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad3_ 5_nand -X4 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad4_ 5_nand -X5 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad5_ 5_nand -X6 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad6_ 5_nand -X7 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad7_ 5_nand -X8 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U6-Pad2_ Net-_U2-Pad3_ Net-_U1-Pad8_ 5_nand -X9 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad9_ 5_nand -X10 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad10_ 5_nand -X11 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad11_ 5_nand -X12 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U5-Pad2_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad13_ 5_nand -X13 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad14_ 5_nand -X14 Net-_U1-Pad23_ Net-_U4-Pad2_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad15_ 5_nand -X15 Net-_U3-Pad2_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad16_ 5_nand -X16 Net-_U1-Pad23_ Net-_U1-Pad22_ Net-_U1-Pad21_ Net-_U1-Pad20_ Net-_U2-Pad3_ Net-_U1-Pad17_ 5_nand - -.end diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out b/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out deleted file mode 100644 index eecdfb06..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.cir.out +++ /dev/null @@ -1,49 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir - -.include 5_nand.sub -* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter -* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port -x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand -x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand -x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand -x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand -x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand -x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand -x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand -x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand -x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand -x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand -x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand -x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand -x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand -x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand -x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand -x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand -a1 net-_u1-pad23_ net-_u3-pad2_ u3 -a2 net-_u1-pad22_ net-_u4-pad2_ u4 -a3 net-_u1-pad21_ net-_u5-pad2_ u5 -a4 net-_u1-pad20_ net-_u6-pad2_ u6 -a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro b/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro deleted file mode 100644 index 5a167cd9..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.pro +++ /dev/null @@ -1,43 +0,0 @@ -update=Fri Jun 21 16:58:10 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_Sources -LibName9=eSim_User -LibName10=eSim_Subckt diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch deleted file mode 100644 index c9142e27..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sch +++ /dev/null @@ -1,889 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:4to16_demux-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_inverter U3 -U 1 1 5CF2315F -P 4700 1900 -F 0 "U3" H 4700 1800 60 0000 C CNN -F 1 "d_inverter" H 4700 2050 60 0000 C CNN -F 2 "" H 4750 1850 60 0000 C CNN -F 3 "" H 4750 1850 60 0000 C CNN - 1 4700 1900 - 0 1 1 0 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5CF231D7 -P 5600 1850 -F 0 "U4" H 5600 1750 60 0000 C CNN -F 1 "d_inverter" H 5600 2000 60 0000 C CNN -F 2 "" H 5650 1800 60 0000 C CNN -F 3 "" H 5650 1800 60 0000 C CNN - 1 5600 1850 - 0 1 1 0 -$EndComp -$Comp -L d_inverter U5 -U 1 1 5CF23245 -P 6550 1850 -F 0 "U5" H 6550 1750 60 0000 C CNN -F 1 "d_inverter" H 6550 2000 60 0000 C CNN -F 2 "" H 6600 1800 60 0000 C CNN -F 3 "" H 6600 1800 60 0000 C CNN - 1 6550 1850 - 0 1 1 0 -$EndComp -$Comp -L d_inverter U6 -U 1 1 5CF232B2 -P 7500 1800 -F 0 "U6" H 7500 1700 60 0000 C CNN -F 1 "d_inverter" H 7500 1950 60 0000 C CNN -F 2 "" H 7550 1750 60 0000 C CNN -F 3 "" H 7550 1750 60 0000 C CNN - 1 7500 1800 - 0 1 1 0 -$EndComp -Text Notes 1300 5450 0 60 ~ 0 -~Y0 -Text Notes 1950 5450 0 60 ~ 0 -~Y1\n -Text Notes 2500 5450 0 60 ~ 0 -~Y2\n -Text Notes 3050 5450 0 60 ~ 0 -~Y3\n -Text Notes 3600 5450 0 60 ~ 0 -~Y4\n -Text Notes 4150 5500 0 60 ~ 0 -~Y5\n -Text Notes 4700 5500 0 60 ~ 0 -~Y6\n -Text Notes 5250 5500 0 60 ~ 0 -~Y7\n -Text Notes 5800 5500 0 60 ~ 0 -~Y8\n -Text Notes 6400 5500 0 60 ~ 0 -~Y9\n -Text Notes 6950 5500 0 60 ~ 0 -~Y10\n -Text Notes 7500 5500 0 60 ~ 0 -~Y11\n -Text Notes 8050 5500 0 60 ~ 0 -~Y12\n -Text Notes 8600 5500 0 60 ~ 0 -~Y13\n -Text Notes 9150 5500 0 60 ~ 0 -~Y14\n -Text Notes 9700 5500 0 60 ~ 0 -~Y15\n -Wire Wire Line - 4700 1250 4700 1600 -Wire Wire Line - 5600 1150 5600 1550 -Wire Wire Line - 6550 1100 6550 1550 -Wire Wire Line - 7500 1050 7500 1500 -Wire Wire Line - 1400 4400 1400 2950 -Wire Wire Line - 1400 2950 9700 2950 -Wire Wire Line - 1950 2950 1950 4400 -Wire Wire Line - 2500 2950 2500 4400 -Connection ~ 1950 2950 -Wire Wire Line - 3050 2950 3050 4400 -Connection ~ 2500 2950 -Wire Wire Line - 3600 2950 3600 4400 -Connection ~ 3050 2950 -Wire Wire Line - 4150 2950 4150 4400 -Connection ~ 3600 2950 -Wire Wire Line - 4700 2950 4700 4400 -Connection ~ 4150 2950 -Wire Wire Line - 5250 2950 5250 4400 -Connection ~ 4700 2950 -Wire Wire Line - 5800 2950 5800 4400 -Connection ~ 5250 2950 -Wire Wire Line - 6400 2950 6400 4400 -Connection ~ 5800 2950 -Wire Wire Line - 6950 2950 6950 4400 -Connection ~ 6400 2950 -Wire Wire Line - 7500 2950 7500 4400 -Connection ~ 6950 2950 -Wire Wire Line - 8050 2950 8050 4400 -Connection ~ 7500 2950 -Wire Wire Line - 8600 2950 8600 4400 -Connection ~ 8050 2950 -Wire Wire Line - 9150 2950 9150 4400 -Connection ~ 8600 2950 -Wire Wire Line - 9700 2950 9700 4400 -Connection ~ 9150 2950 -Wire Wire Line - 7500 2100 7500 2800 -Wire Wire Line - 7500 2800 7400 2800 -Wire Wire Line - 7400 2800 7400 3050 -Wire Wire Line - 7400 3050 1500 3050 -Wire Wire Line - 1500 3050 1500 4400 -Wire Wire Line - 2050 4400 2050 3050 -Connection ~ 2050 3050 -Wire Wire Line - 2600 4400 2600 3050 -Connection ~ 2600 3050 -Wire Wire Line - 3150 4400 3150 3050 -Connection ~ 3150 3050 -Wire Wire Line - 3700 4400 3700 3050 -Connection ~ 3700 3050 -Wire Wire Line - 4250 4400 4250 3050 -Connection ~ 4250 3050 -Wire Wire Line - 4800 4400 4800 3050 -Connection ~ 4800 3050 -Wire Wire Line - 5350 4400 5350 3050 -Connection ~ 5350 3050 -Wire Wire Line - 6550 3150 6550 2150 -Wire Wire Line - 1600 3150 7700 3150 -Wire Wire Line - 1600 3150 1600 4400 -Wire Wire Line - 2150 4400 2150 3150 -Connection ~ 2150 3150 -Wire Wire Line - 2700 4400 2700 3150 -Connection ~ 2700 3150 -Wire Wire Line - 3250 4400 3250 3150 -Connection ~ 3250 3150 -Wire Wire Line - 5600 3250 5600 2150 -Wire Wire Line - 1700 3250 8900 3250 -Wire Wire Line - 1700 3250 1700 4400 -Wire Wire Line - 2250 4400 2250 3250 -Connection ~ 2250 3250 -Wire Wire Line - 3900 4400 3900 3250 -Connection ~ 3900 3250 -Wire Wire Line - 4450 4400 4450 3250 -Connection ~ 4450 3250 -Wire Wire Line - 6100 3250 6100 4400 -Connection ~ 5600 3250 -Wire Wire Line - 6700 3250 6700 4400 -Connection ~ 6100 3250 -Wire Wire Line - 8350 3250 8350 4400 -Connection ~ 6700 3250 -Wire Wire Line - 8900 3250 8900 4400 -Connection ~ 8350 3250 -Wire Wire Line - 4700 2200 4700 2850 -Wire Wire Line - 4700 2850 4600 2850 -Wire Wire Line - 4600 2850 4600 3350 -Wire Wire Line - 1800 3350 1800 4400 -Wire Wire Line - 2900 4400 2900 3350 -Connection ~ 2900 3350 -Connection ~ 4600 3350 -Wire Wire Line - 2350 2650 2350 4400 -Wire Wire Line - 4000 3350 4000 4400 -Connection ~ 4000 3350 -Wire Wire Line - 5100 3350 5100 4400 -Connection ~ 5100 3350 -Wire Wire Line - 6200 3350 6200 4400 -Connection ~ 6200 3350 -Wire Wire Line - 7350 3350 7350 4400 -Connection ~ 7350 3350 -Wire Wire Line - 8450 3350 8450 4400 -Connection ~ 8450 3350 -Wire Wire Line - 1800 3350 9550 3350 -Wire Wire Line - 9550 3350 9550 4400 -Wire Wire Line - 2350 3450 10100 3450 -Wire Wire Line - 3450 3450 3450 4400 -Wire Wire Line - 4550 3450 4550 4400 -Connection ~ 3450 3450 -Wire Wire Line - 5650 3450 5650 4400 -Connection ~ 4550 3450 -Wire Wire Line - 6800 3450 6800 4400 -Connection ~ 5650 3450 -Wire Wire Line - 7900 3450 7900 4400 -Connection ~ 6800 3450 -Wire Wire Line - 9000 3450 9000 4400 -Connection ~ 7900 3450 -Wire Wire Line - 10100 3450 10100 4400 -Connection ~ 9000 3450 -Wire Wire Line - 10000 3550 10000 4400 -Wire Wire Line - 2800 3550 10000 3550 -Wire Wire Line - 9450 3550 9450 4400 -Wire Wire Line - 7800 3550 7800 4400 -Connection ~ 9450 3550 -Wire Wire Line - 7250 3550 7250 4400 -Connection ~ 7800 3550 -Wire Wire Line - 5550 3550 5550 4400 -Connection ~ 7250 3550 -Wire Wire Line - 5000 1400 5000 4400 -Connection ~ 5550 3550 -Wire Wire Line - 3350 3550 3350 4400 -Connection ~ 5000 3550 -Wire Wire Line - 2800 3550 2800 4400 -Connection ~ 3350 3550 -Wire Wire Line - 5000 1400 5600 1400 -Connection ~ 5600 1400 -Wire Wire Line - 9900 3700 9900 4400 -Wire Wire Line - 3800 3700 9900 3700 -Wire Wire Line - 9350 3700 9350 4400 -Wire Wire Line - 8800 3700 8800 4400 -Connection ~ 9350 3700 -Wire Wire Line - 8250 3700 8250 4400 -Connection ~ 8800 3700 -Wire Wire Line - 5450 3700 5450 4400 -Connection ~ 8250 3700 -Wire Wire Line - 4900 3700 4900 4400 -Connection ~ 5450 3700 -Wire Wire Line - 4350 3700 4350 4400 -Connection ~ 4900 3700 -Wire Wire Line - 3800 3700 3800 4400 -Connection ~ 4350 3700 -Wire Wire Line - 5950 3700 5950 1350 -Wire Wire Line - 5950 1350 6550 1350 -Connection ~ 6550 1350 -Connection ~ 5950 3700 -Wire Wire Line - 9800 3850 9800 4400 -Wire Wire Line - 5900 3850 9800 3850 -Wire Wire Line - 9250 3850 9250 4400 -Wire Wire Line - 8700 3850 8700 4400 -Connection ~ 9250 3850 -Wire Wire Line - 8150 3850 8150 4400 -Connection ~ 8700 3850 -Wire Wire Line - 7600 3850 7600 4400 -Connection ~ 8150 3850 -Wire Wire Line - 7050 1350 7050 4400 -Connection ~ 7600 3850 -Wire Wire Line - 6500 3850 6500 4400 -Connection ~ 7050 3850 -Wire Wire Line - 5900 3850 5900 4400 -Connection ~ 6500 3850 -Wire Wire Line - 7050 1350 7500 1350 -Connection ~ 7500 1350 -Wire Wire Line - 7700 3150 7700 4400 -Connection ~ 6550 3150 -Wire Wire Line - 7150 4400 7150 3150 -Connection ~ 7150 3150 -Wire Wire Line - 6600 3150 6600 4400 -Connection ~ 6600 3150 -Wire Wire Line - 6000 4400 6000 3150 -Connection ~ 6000 3150 -Connection ~ 2350 3450 -Connection ~ 4700 1450 -Wire Wire Line - 4000 1450 4700 1450 -Wire Wire Line - 2350 2650 4000 2650 -Wire Wire Line - 4000 2650 4000 1450 -$Comp -L d_nor U2 -U 1 1 5CF2CBDC -P 1600 2050 -F 0 "U2" H 1600 2050 60 0000 C CNN -F 1 "d_nor" H 1650 2150 60 0000 C CNN -F 2 "" H 1600 2050 60 0000 C CNN -F 3 "" H 1600 2050 60 0000 C CNN - 1 1600 2050 - 0 1 1 0 -$EndComp -Wire Wire Line - 1650 2500 1650 2950 -Connection ~ 1650 2950 -Wire Wire Line - 1700 1600 1700 1200 -Wire Wire Line - 1600 1600 1600 1200 -$Comp -L PORT U1 -U 18 1 5CF2D1A2 -P 1600 950 -F 0 "U1" H 1650 1050 30 0000 C CNN -F 1 "PORT" H 1600 950 30 0000 C CNN -F 2 "" H 1600 950 60 0000 C CNN -F 3 "" H 1600 950 60 0000 C CNN - 18 1600 950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 19 1 5CF2D207 -P 1900 900 -F 0 "U1" H 1950 1000 30 0000 C CNN -F 1 "PORT" H 1900 900 30 0000 C CNN -F 2 "" H 1900 900 60 0000 C CNN -F 3 "" H 1900 900 60 0000 C CNN - 19 1900 900 - 0 1 1 0 -$EndComp -Wire Wire Line - 1900 1150 1900 1200 -Wire Wire Line - 1900 1200 1700 1200 -$Comp -L PORT U1 -U 23 1 5CF2D33A -P 4700 1000 -F 0 "U1" H 4750 1100 30 0000 C CNN -F 1 "PORT" H 4700 1000 30 0000 C CNN -F 2 "" H 4700 1000 60 0000 C CNN -F 3 "" H 4700 1000 60 0000 C CNN - 23 4700 1000 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 22 1 5CF2D510 -P 5600 900 -F 0 "U1" H 5650 1000 30 0000 C CNN -F 1 "PORT" H 5600 900 30 0000 C CNN -F 2 "" H 5600 900 60 0000 C CNN -F 3 "" H 5600 900 60 0000 C CNN - 22 5600 900 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 21 1 5CF2D57F -P 6550 850 -F 0 "U1" H 6600 950 30 0000 C CNN -F 1 "PORT" H 6550 850 30 0000 C CNN -F 2 "" H 6550 850 60 0000 C CNN -F 3 "" H 6550 850 60 0000 C CNN - 21 6550 850 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 20 1 5CF2D6A5 -P 7500 800 -F 0 "U1" H 7550 900 30 0000 C CNN -F 1 "PORT" H 7500 800 30 0000 C CNN -F 2 "" H 7500 800 60 0000 C CNN -F 3 "" H 7500 800 60 0000 C CNN - 20 7500 800 - 0 1 1 0 -$EndComp -Text Notes 7700 950 0 60 ~ 0 -A3\n -$Comp -L PORT U1 -U 1 1 5CF2DE5C -P 1600 6200 -F 0 "U1" H 1650 6300 30 0000 C CNN -F 1 "PORT" H 1600 6200 30 0000 C CNN -F 2 "" H 1600 6200 60 0000 C CNN -F 3 "" H 1600 6200 60 0000 C CNN - 1 1600 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 2 1 5CF2E1AE -P 2150 6200 -F 0 "U1" H 2200 6300 30 0000 C CNN -F 1 "PORT" H 2150 6200 30 0000 C CNN -F 2 "" H 2150 6200 60 0000 C CNN -F 3 "" H 2150 6200 60 0000 C CNN - 2 2150 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 3 1 5CF2E23B -P 2700 6200 -F 0 "U1" H 2750 6300 30 0000 C CNN -F 1 "PORT" H 2700 6200 30 0000 C CNN -F 2 "" H 2700 6200 60 0000 C CNN -F 3 "" H 2700 6200 60 0000 C CNN - 3 2700 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 4 1 5CF2E2B3 -P 3250 6200 -F 0 "U1" H 3300 6300 30 0000 C CNN -F 1 "PORT" H 3250 6200 30 0000 C CNN -F 2 "" H 3250 6200 60 0000 C CNN -F 3 "" H 3250 6200 60 0000 C CNN - 4 3250 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 5 1 5CF2E32C -P 3800 6200 -F 0 "U1" H 3850 6300 30 0000 C CNN -F 1 "PORT" H 3800 6200 30 0000 C CNN -F 2 "" H 3800 6200 60 0000 C CNN -F 3 "" H 3800 6200 60 0000 C CNN - 5 3800 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 6 1 5CF2E3CE -P 4350 6200 -F 0 "U1" H 4400 6300 30 0000 C CNN -F 1 "PORT" H 4350 6200 30 0000 C CNN -F 2 "" H 4350 6200 60 0000 C CNN -F 3 "" H 4350 6200 60 0000 C CNN - 6 4350 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 7 1 5CF2E4B6 -P 4900 6200 -F 0 "U1" H 4950 6300 30 0000 C CNN -F 1 "PORT" H 4900 6200 30 0000 C CNN -F 2 "" H 4900 6200 60 0000 C CNN -F 3 "" H 4900 6200 60 0000 C CNN - 7 4900 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 8 1 5CF2E5CA -P 5450 6200 -F 0 "U1" H 5500 6300 30 0000 C CNN -F 1 "PORT" H 5450 6200 30 0000 C CNN -F 2 "" H 5450 6200 60 0000 C CNN -F 3 "" H 5450 6200 60 0000 C CNN - 8 5450 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 9 1 5CF2E651 -P 6000 6200 -F 0 "U1" H 6050 6300 30 0000 C CNN -F 1 "PORT" H 6000 6200 30 0000 C CNN -F 2 "" H 6000 6200 60 0000 C CNN -F 3 "" H 6000 6200 60 0000 C CNN - 9 6000 6200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 10 1 5CF2E6E3 -P 6600 6150 -F 0 "U1" H 6650 6250 30 0000 C CNN -F 1 "PORT" H 6600 6150 30 0000 C CNN -F 2 "" H 6600 6150 60 0000 C CNN -F 3 "" H 6600 6150 60 0000 C CNN - 10 6600 6150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 11 1 5CF2E770 -P 7150 6150 -F 0 "U1" H 7200 6250 30 0000 C CNN -F 1 "PORT" H 7150 6150 30 0000 C CNN -F 2 "" H 7150 6150 60 0000 C CNN -F 3 "" H 7150 6150 60 0000 C CNN - 11 7150 6150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 13 1 5CF2E7F8 -P 7700 6150 -F 0 "U1" H 7750 6250 30 0000 C CNN -F 1 "PORT" H 7700 6150 30 0000 C CNN -F 2 "" H 7700 6150 60 0000 C CNN -F 3 "" H 7700 6150 60 0000 C CNN - 13 7700 6150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 14 1 5CF2E989 -P 8250 6150 -F 0 "U1" H 8300 6250 30 0000 C CNN -F 1 "PORT" H 8250 6150 30 0000 C CNN -F 2 "" H 8250 6150 60 0000 C CNN -F 3 "" H 8250 6150 60 0000 C CNN - 14 8250 6150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 15 1 5CF2EA23 -P 8800 6150 -F 0 "U1" H 8850 6250 30 0000 C CNN -F 1 "PORT" H 8800 6150 30 0000 C CNN -F 2 "" H 8800 6150 60 0000 C CNN -F 3 "" H 8800 6150 60 0000 C CNN - 15 8800 6150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 16 1 5CF2EABA -P 9350 6150 -F 0 "U1" H 9400 6250 30 0000 C CNN -F 1 "PORT" H 9350 6150 30 0000 C CNN -F 2 "" H 9350 6150 60 0000 C CNN -F 3 "" H 9350 6150 60 0000 C CNN - 16 9350 6150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 17 1 5CF2EB7A -P 9900 6100 -F 0 "U1" H 9950 6200 30 0000 C CNN -F 1 "PORT" H 9900 6100 30 0000 C CNN -F 2 "" H 9900 6100 60 0000 C CNN -F 3 "" H 9900 6100 60 0000 C CNN - 17 9900 6100 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 9900 5850 9900 5400 -Wire Wire Line - 9350 5400 9350 5900 -Wire Wire Line - 8800 5400 8800 5900 -Wire Wire Line - 8250 5400 8250 5900 -Wire Wire Line - 7700 5400 7700 5900 -Wire Wire Line - 7150 5400 7150 5900 -Wire Wire Line - 6600 5400 6600 5900 -Wire Wire Line - 6000 5400 6000 5950 -Wire Wire Line - 5450 5400 5450 5950 -Wire Wire Line - 4900 5400 4900 5950 -Wire Wire Line - 4350 5400 4350 5950 -Wire Wire Line - 3800 5400 3800 5950 -Wire Wire Line - 3250 5400 3250 5950 -Wire Wire Line - 2700 5400 2700 5950 -Wire Wire Line - 2150 5400 2150 5950 -Wire Wire Line - 1600 5400 1600 5950 -$Comp -L PORT U1 -U 24 1 5CF327C1 -P 6500 6950 -F 0 "U1" H 6550 7050 30 0000 C CNN -F 1 "PORT" H 6500 6950 30 0000 C CNN -F 2 "" H 6500 6950 60 0000 C CNN -F 3 "" H 6500 6950 60 0000 C CNN - 24 6500 6950 - 0 -1 -1 0 -$EndComp -NoConn ~ 6500 6700 -$Comp -L PORT U1 -U 12 1 5CF33A86 -P 3400 900 -F 0 "U1" H 3450 1000 30 0000 C CNN -F 1 "PORT" H 3400 900 30 0000 C CNN -F 2 "" H 3400 900 60 0000 C CNN -F 3 "" H 3400 900 60 0000 C CNN - 12 3400 900 - 0 1 1 0 -$EndComp -NoConn ~ 3400 1150 -$Comp -L 5_nand X1 -U 1 1 5D0CC4BF -P 1600 4850 -F 0 "X1" H 1650 4750 60 0000 C CNN -F 1 "5_nand" H 1700 5000 60 0000 C CNN -F 2 "" H 1600 4850 60 0000 C CNN -F 3 "" H 1600 4850 60 0000 C CNN - 1 1600 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X2 -U 1 1 5D0CC967 -P 2150 4850 -F 0 "X2" H 2200 4750 60 0000 C CNN -F 1 "5_nand" H 2250 5000 60 0000 C CNN -F 2 "" H 2150 4850 60 0000 C CNN -F 3 "" H 2150 4850 60 0000 C CNN - 1 2150 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X3 -U 1 1 5D0CC9F8 -P 2700 4850 -F 0 "X3" H 2750 4750 60 0000 C CNN -F 1 "5_nand" H 2800 5000 60 0000 C CNN -F 2 "" H 2700 4850 60 0000 C CNN -F 3 "" H 2700 4850 60 0000 C CNN - 1 2700 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X4 -U 1 1 5D0CCA7E -P 3250 4850 -F 0 "X4" H 3300 4750 60 0000 C CNN -F 1 "5_nand" H 3350 5000 60 0000 C CNN -F 2 "" H 3250 4850 60 0000 C CNN -F 3 "" H 3250 4850 60 0000 C CNN - 1 3250 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X5 -U 1 1 5D0CCB6A -P 3800 4850 -F 0 "X5" H 3850 4750 60 0000 C CNN -F 1 "5_nand" H 3900 5000 60 0000 C CNN -F 2 "" H 3800 4850 60 0000 C CNN -F 3 "" H 3800 4850 60 0000 C CNN - 1 3800 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X6 -U 1 1 5D0CCBF6 -P 4350 4850 -F 0 "X6" H 4400 4750 60 0000 C CNN -F 1 "5_nand" H 4450 5000 60 0000 C CNN -F 2 "" H 4350 4850 60 0000 C CNN -F 3 "" H 4350 4850 60 0000 C CNN - 1 4350 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X7 -U 1 1 5D0CCC81 -P 4900 4850 -F 0 "X7" H 4950 4750 60 0000 C CNN -F 1 "5_nand" H 5000 5000 60 0000 C CNN -F 2 "" H 4900 4850 60 0000 C CNN -F 3 "" H 4900 4850 60 0000 C CNN - 1 4900 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X8 -U 1 1 5D0CCD0B -P 5450 4850 -F 0 "X8" H 5500 4750 60 0000 C CNN -F 1 "5_nand" H 5550 5000 60 0000 C CNN -F 2 "" H 5450 4850 60 0000 C CNN -F 3 "" H 5450 4850 60 0000 C CNN - 1 5450 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X9 -U 1 1 5D0CCE34 -P 6000 4850 -F 0 "X9" H 6050 4750 60 0000 C CNN -F 1 "5_nand" H 6100 5000 60 0000 C CNN -F 2 "" H 6000 4850 60 0000 C CNN -F 3 "" H 6000 4850 60 0000 C CNN - 1 6000 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X10 -U 1 1 5D0CCECA -P 6600 4850 -F 0 "X10" H 6650 4750 60 0000 C CNN -F 1 "5_nand" H 6700 5000 60 0000 C CNN -F 2 "" H 6600 4850 60 0000 C CNN -F 3 "" H 6600 4850 60 0000 C CNN - 1 6600 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X11 -U 1 1 5D0CCF63 -P 7150 4850 -F 0 "X11" H 7200 4750 60 0000 C CNN -F 1 "5_nand" H 7250 5000 60 0000 C CNN -F 2 "" H 7150 4850 60 0000 C CNN -F 3 "" H 7150 4850 60 0000 C CNN - 1 7150 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X12 -U 1 1 5D0CD07D -P 7700 4850 -F 0 "X12" H 7750 4750 60 0000 C CNN -F 1 "5_nand" H 7800 5000 60 0000 C CNN -F 2 "" H 7700 4850 60 0000 C CNN -F 3 "" H 7700 4850 60 0000 C CNN - 1 7700 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X13 -U 1 1 5D0CD124 -P 8250 4850 -F 0 "X13" H 8300 4750 60 0000 C CNN -F 1 "5_nand" H 8350 5000 60 0000 C CNN -F 2 "" H 8250 4850 60 0000 C CNN -F 3 "" H 8250 4850 60 0000 C CNN - 1 8250 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X14 -U 1 1 5D0CD1C6 -P 8800 4850 -F 0 "X14" H 8850 4750 60 0000 C CNN -F 1 "5_nand" H 8900 5000 60 0000 C CNN -F 2 "" H 8800 4850 60 0000 C CNN -F 3 "" H 8800 4850 60 0000 C CNN - 1 8800 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X15 -U 1 1 5D0CD348 -P 9350 4850 -F 0 "X15" H 9400 4750 60 0000 C CNN -F 1 "5_nand" H 9450 5000 60 0000 C CNN -F 2 "" H 9350 4850 60 0000 C CNN -F 3 "" H 9350 4850 60 0000 C CNN - 1 9350 4850 - 0 1 1 0 -$EndComp -$Comp -L 5_nand X16 -U 1 1 5D0CD3EE -P 9900 4850 -F 0 "X16" H 9950 4750 60 0000 C CNN -F 1 "5_nand" H 10000 5000 60 0000 C CNN -F 2 "" H 9900 4850 60 0000 C CNN -F 3 "" H 9900 4850 60 0000 C CNN - 1 9900 4850 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub b/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub deleted file mode 100644 index 4f7595da..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux.sub +++ /dev/null @@ -1,43 +0,0 @@ -* Subcircuit 4to16_demux -.subckt 4to16_demux net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/4to16_demux/4to16_demux.cir -.include 5_nand.sub -* u3 net-_u1-pad23_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad22_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad21_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad20_ net-_u6-pad2_ d_inverter -* u2 net-_u1-pad19_ net-_u1-pad18_ net-_u2-pad3_ d_nor -x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad1_ 5_nand -x2 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad2_ 5_nand -x3 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad3_ 5_nand -x4 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad4_ 5_nand -x5 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad5_ 5_nand -x6 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad6_ 5_nand -x7 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad7_ 5_nand -x8 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u6-pad2_ net-_u2-pad3_ net-_u1-pad8_ 5_nand -x9 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad9_ 5_nand -x10 net-_u1-pad23_ net-_u4-pad2_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad10_ 5_nand -x11 net-_u3-pad2_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad11_ 5_nand -x12 net-_u1-pad23_ net-_u1-pad22_ net-_u5-pad2_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad13_ 5_nand -x13 net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad14_ 5_nand -x14 net-_u1-pad23_ net-_u4-pad2_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad15_ 5_nand -x15 net-_u3-pad2_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad16_ 5_nand -x16 net-_u1-pad23_ net-_u1-pad22_ net-_u1-pad21_ net-_u1-pad20_ net-_u2-pad3_ net-_u1-pad17_ 5_nand -a1 net-_u1-pad23_ net-_u3-pad2_ u3 -a2 net-_u1-pad22_ net-_u4-pad2_ u4 -a3 net-_u1-pad21_ net-_u5-pad2_ u5 -a4 net-_u1-pad20_ net-_u6-pad2_ u6 -a5 [net-_u1-pad19_ net-_u1-pad18_ ] net-_u2-pad3_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u2 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4to16_demux
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml deleted file mode 100644 index 93c6f25a..00000000 --- a/src/SubcircuitLibrary/4to16_demux/4to16_demux_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x13><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x13><x14><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x14><x15><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x15><x10><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x10><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x9><x16><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x16><x11><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x11><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x3><x12><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x12><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib deleted file mode 100644 index ac396288..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir b/src/SubcircuitLibrary/4to16_demux/5_and.cir deleted file mode 100644 index 6a05b9b5..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and -U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and -U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT - -.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out b/src/SubcircuitLibrary/4to16_demux/5_and.cir.out deleted file mode 100644 index 6a6b126a..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port -a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.pro b/src/SubcircuitLibrary/4to16_demux/5_and.pro deleted file mode 100644 index 7a2f090e..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and.pro +++ /dev/null @@ -1,50 +0,0 @@ -update=06/01/19 11:31:03 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=cypress -LibName2=siliconi -LibName3=opto -LibName4=atmel -LibName5=contrib -LibName6=valves -LibName7=eSim_Analog -LibName8=eSim_Devices -LibName9=eSim_Digital -LibName10=eSim_Hybrid -LibName11=eSim_Miscellaneous -LibName12=eSim_Plot -LibName13=eSim_Power -LibName14=eSim_PSpice -LibName15=eSim_Sources -LibName16=eSim_Subckt -LibName17=eSim_User diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sch b/src/SubcircuitLibrary/4to16_demux/5_and.sch deleted file mode 100644 index e9eb58ee..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and.sch +++ /dev/null @@ -1,171 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:5_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5C9A2741 -P 3800 3350 -F 0 "X1" H 4700 3650 60 0000 C CNN -F 1 "3_and" H 4750 3850 60 0000 C CNN -F 2 "" H 3800 3350 60 0000 C CNN -F 3 "" H 3800 3350 60 0000 C CNN - 1 3800 3350 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C9A2764 -P 4650 3400 -F 0 "U2" H 4650 3400 60 0000 C CNN -F 1 "d_and" H 4700 3500 60 0000 C CNN -F 2 "" H 4650 3400 60 0000 C CNN -F 3 "" H 4650 3400 60 0000 C CNN - 1 4650 3400 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2791 -P 5550 3200 -F 0 "U3" H 5550 3200 60 0000 C CNN -F 1 "d_and" H 5600 3300 60 0000 C CNN -F 2 "" H 5550 3200 60 0000 C CNN -F 3 "" H 5550 3200 60 0000 C CNN - 1 5550 3200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5100 3100 5100 2950 -Wire Wire Line - 5100 3200 5100 3350 -Wire Wire Line - 4250 2850 4250 2700 -Wire Wire Line - 4250 2700 3600 2700 -Wire Wire Line - 4250 2950 4150 2950 -Wire Wire Line - 4150 2950 4150 2900 -Wire Wire Line - 4150 2900 3600 2900 -Wire Wire Line - 4200 3300 3600 3300 -Wire Wire Line - 4250 3050 4250 3100 -Wire Wire Line - 4250 3100 3600 3100 -Wire Wire Line - 4200 3400 4200 3500 -Wire Wire Line - 4200 3500 3600 3500 -Wire Wire Line - 6000 3150 6500 3150 -$Comp -L PORT U1 -U 1 1 5C9A2865 -P 3350 2700 -F 0 "U1" H 3400 2800 30 0000 C CNN -F 1 "PORT" H 3350 2700 30 0000 C CNN -F 2 "" H 3350 2700 60 0000 C CNN -F 3 "" H 3350 2700 60 0000 C CNN - 1 3350 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A28B6 -P 3350 2900 -F 0 "U1" H 3400 3000 30 0000 C CNN -F 1 "PORT" H 3350 2900 30 0000 C CNN -F 2 "" H 3350 2900 60 0000 C CNN -F 3 "" H 3350 2900 60 0000 C CNN - 2 3350 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A28D9 -P 3350 3100 -F 0 "U1" H 3400 3200 30 0000 C CNN -F 1 "PORT" H 3350 3100 30 0000 C CNN -F 2 "" H 3350 3100 60 0000 C CNN -F 3 "" H 3350 3100 60 0000 C CNN - 3 3350 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A28FF -P 3350 3300 -F 0 "U1" H 3400 3400 30 0000 C CNN -F 1 "PORT" H 3350 3300 30 0000 C CNN -F 2 "" H 3350 3300 60 0000 C CNN -F 3 "" H 3350 3300 60 0000 C CNN - 4 3350 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A2928 -P 3350 3500 -F 0 "U1" H 3400 3600 30 0000 C CNN -F 1 "PORT" H 3350 3500 30 0000 C CNN -F 2 "" H 3350 3500 60 0000 C CNN -F 3 "" H 3350 3500 60 0000 C CNN - 5 3350 3500 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C9A2958 -P 6750 3150 -F 0 "U1" H 6800 3250 30 0000 C CNN -F 1 "PORT" H 6750 3150 30 0000 C CNN -F 2 "" H 6750 3150 60 0000 C CNN -F 3 "" H 6750 3150 60 0000 C CNN - 6 6750 3150 - -1 0 0 1 -$EndComp -Text Notes 3800 2700 0 60 ~ 12 -in1 -Text Notes 3800 2900 0 60 ~ 12 -in2 -Text Notes 3800 3100 0 60 ~ 12 -in3 -Text Notes 3800 3300 0 60 ~ 12 -in4 -Text Notes 3800 3500 0 60 ~ 12 -in5 -Text Notes 6150 3150 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_and.sub b/src/SubcircuitLibrary/4to16_demux/5_and.sub deleted file mode 100644 index 35b10e17..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and.sub +++ /dev/null @@ -1,16 +0,0 @@ -* Subcircuit 5_and -.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and -a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml deleted file mode 100644 index ae2c08a7..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib b/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib deleted file mode 100644 index cb517be1..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand-cache.lib +++ /dev/null @@ -1,78 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir b/src/SubcircuitLibrary/4to16_demux/5_nand.cir deleted file mode 100644 index e833d0f4..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand.cir +++ /dev/null @@ -1,13 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and -U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT - -.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out b/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out deleted file mode 100644 index 164de911..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir - -.include 5_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and -* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port -a1 net-_u2-pad1_ net-_u1-pad6_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.pro b/src/SubcircuitLibrary/4to16_demux/5_nand.pro deleted file mode 100644 index b7d23f44..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand.pro +++ /dev/null @@ -1,83 +0,0 @@ -update=Fri Jun 21 16:46:10 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice -LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User - diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sch b/src/SubcircuitLibrary/4to16_demux/5_nand.sch deleted file mode 100644 index 86379b08..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand.sch +++ /dev/null @@ -1,175 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 5_and X1 -U 1 1 5D0CBD44 -P 4150 3700 -F 0 "X1" H 4200 3600 60 0000 C CNN -F 1 "5_and" H 4250 3850 60 0000 C CNN -F 2 "" H 4150 3700 60 0000 C CNN -F 3 "" H 4150 3700 60 0000 C CNN - 1 4150 3700 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U2 -U 1 1 5D0CBD97 -P 5150 3700 -F 0 "U2" H 5150 3600 60 0000 C CNN -F 1 "d_inverter" H 5150 3850 60 0000 C CNN -F 2 "" H 5200 3650 60 0000 C CNN -F 3 "" H 5200 3650 60 0000 C CNN - 1 5150 3700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5D0CBDBE -P 2900 2900 -F 0 "U1" H 2950 3000 30 0000 C CNN -F 1 "PORT" H 2900 2900 30 0000 C CNN -F 2 "" H 2900 2900 60 0000 C CNN -F 3 "" H 2900 2900 60 0000 C CNN - 1 2900 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D0CBDF4 -P 2900 3150 -F 0 "U1" H 2950 3250 30 0000 C CNN -F 1 "PORT" H 2900 3150 30 0000 C CNN -F 2 "" H 2900 3150 60 0000 C CNN -F 3 "" H 2900 3150 60 0000 C CNN - 2 2900 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5D0CBE16 -P 2900 3400 -F 0 "U1" H 2950 3500 30 0000 C CNN -F 1 "PORT" H 2900 3400 30 0000 C CNN -F 2 "" H 2900 3400 60 0000 C CNN -F 3 "" H 2900 3400 60 0000 C CNN - 3 2900 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5D0CBE3F -P 2900 3750 -F 0 "U1" H 2950 3850 30 0000 C CNN -F 1 "PORT" H 2900 3750 30 0000 C CNN -F 2 "" H 2900 3750 60 0000 C CNN -F 3 "" H 2900 3750 60 0000 C CNN - 4 2900 3750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5D0CBE6B -P 2900 4150 -F 0 "U1" H 2950 4250 30 0000 C CNN -F 1 "PORT" H 2900 4150 30 0000 C CNN -F 2 "" H 2900 4150 60 0000 C CNN -F 3 "" H 2900 4150 60 0000 C CNN - 5 2900 4150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5D0CBE9C -P 6200 3700 -F 0 "U1" H 6250 3800 30 0000 C CNN -F 1 "PORT" H 6200 3700 30 0000 C CNN -F 2 "" H 6200 3700 60 0000 C CNN -F 3 "" H 6200 3700 60 0000 C CNN - 6 6200 3700 - -1 0 0 1 -$EndComp -Wire Wire Line - 3150 2900 3700 2900 -Wire Wire Line - 3700 2900 3700 3500 -Wire Wire Line - 3700 3600 3500 3600 -Wire Wire Line - 3500 3600 3500 3150 -Wire Wire Line - 3500 3150 3150 3150 -Wire Wire Line - 3150 3400 3350 3400 -Wire Wire Line - 3350 3400 3350 3700 -Wire Wire Line - 3350 3700 3700 3700 -Wire Wire Line - 3700 3800 3250 3800 -Wire Wire Line - 3250 3800 3250 3750 -Wire Wire Line - 3250 3750 3150 3750 -Wire Wire Line - 3150 4150 3350 4150 -Wire Wire Line - 3350 4150 3350 3900 -Wire Wire Line - 3350 3900 3700 3900 -Wire Wire Line - 4700 3700 4850 3700 -Wire Wire Line - 5450 3700 5950 3700 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand.sub b/src/SubcircuitLibrary/4to16_demux/5_nand.sub deleted file mode 100644 index c3e041fa..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 5_nand -.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir -.include 5_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and -* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter -a1 net-_u2-pad1_ net-_u1-pad6_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_nand
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml deleted file mode 100644 index c4b4cde2..00000000 --- a/src/SubcircuitLibrary/4to16_demux/5_nand_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/4to16_demux/analysis b/src/SubcircuitLibrary/4to16_demux/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/4to16_demux/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/556/556-cache.lib b/src/SubcircuitLibrary/556/556-cache.lib deleted file mode 100644 index 75d610da..00000000 --- a/src/SubcircuitLibrary/556/556-cache.lib +++ /dev/null @@ -1,64 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# LM555N -# -DEF LM555N X 0 40 Y Y 1 F N -F0 "X" 0 -50 60 H V C CNN -F1 "LM555N" 0 100 60 H V C CNN -F2 "" -50 0 60 H V C CNN -F3 "" -50 0 60 H V C CNN -DRAW -S 350 -400 -350 400 0 1 0 N -X GND 1 0 -600 200 U 50 50 1 1 W -X TR 2 -550 250 200 R 50 50 1 1 I -X Q 3 550 250 200 L 50 50 1 1 O -X R 4 -550 -250 200 R 50 50 1 1 I I -X CV 5 -550 0 200 R 50 50 1 1 I -X THR 6 550 -250 200 L 50 50 1 1 I -X DIS 7 550 0 200 L 50 50 1 1 I -X VCC 8 0 600 200 D 50 50 1 1 W -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/556/556.cir b/src/SubcircuitLibrary/556/556.cir deleted file mode 100644 index 48baa73e..00000000 --- a/src/SubcircuitLibrary/556/556.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\556\556.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/18/19 18:30:44 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad14_ LM555N -X2 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ LM555N -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT - -.end diff --git a/src/SubcircuitLibrary/556/556.cir.out b/src/SubcircuitLibrary/556/556.cir.out deleted file mode 100644 index c74aab7c..00000000 --- a/src/SubcircuitLibrary/556/556.cir.out +++ /dev/null @@ -1,15 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\556\556.cir - -.include lm555n.sub -x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n -x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/556/556.pro b/src/SubcircuitLibrary/556/556.pro deleted file mode 100644 index a165313d..00000000 --- a/src/SubcircuitLibrary/556/556.pro +++ /dev/null @@ -1,72 +0,0 @@ -update=03/18/19 18:13:51 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=regul -LibName6=74xx -LibName7=cmos4000 -LibName8=adc-dac -LibName9=memory -LibName10=xilinx -LibName11=microcontrollers -LibName12=dsp -LibName13=microchip -LibName14=analog_switches -LibName15=motorola -LibName16=texas -LibName17=intel -LibName18=audio -LibName19=interface -LibName20=digital-audio -LibName21=philips -LibName22=display -LibName23=cypress -LibName24=siliconi -LibName25=opto -LibName26=atmel -LibName27=contrib -LibName28=valves -LibName29=eSim_User -LibName30=eSim_Subckt -LibName31=eSim_Sources -LibName32=eSim_PSpice -LibName33=eSim_Power -LibName34=eSim_Plot -LibName35=eSim_Miscellaneous -LibName36=eSim_Hybrid -LibName37=eSim_Digital -LibName38=eSim_Devices -LibName39=eSim_Analog diff --git a/src/SubcircuitLibrary/556/556.sch b/src/SubcircuitLibrary/556/556.sch deleted file mode 100644 index af4e1bc9..00000000 --- a/src/SubcircuitLibrary/556/556.sch +++ /dev/null @@ -1,275 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:eSim_Sources -LIBS:eSim_PSpice -LIBS:eSim_Power -LIBS:eSim_Plot -LIBS:eSim_Miscellaneous -LIBS:eSim_Hybrid -LIBS:eSim_Digital -LIBS:eSim_Devices -LIBS:eSim_Analog -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L LM555N X1 -U 1 1 5C8F9298 -P 4150 3850 -F 0 "X1" H 4150 3800 60 0000 C CNN -F 1 "LM555N" H 4150 3950 60 0000 C CNN -F 2 "" H 4100 3850 60 0000 C CNN -F 3 "" H 4100 3850 60 0000 C CNN - 1 4150 3850 - 1 0 0 -1 -$EndComp -$Comp -L LM555N X2 -U 1 1 5C8F92E5 -P 7100 3850 -F 0 "X2" H 7100 3800 60 0000 C CNN -F 1 "LM555N" H 7100 3950 60 0000 C CNN -F 2 "" H 7050 3850 60 0000 C CNN -F 3 "" H 7050 3850 60 0000 C CNN - 1 7100 3850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4150 3250 4150 3000 -Wire Wire Line - 4150 3000 7100 3000 -Wire Wire Line - 4150 4450 4150 4650 -Wire Wire Line - 4150 4650 7100 4650 -$Comp -L PORT U1 -U 14 1 5C8F93E6 -P 4650 2600 -F 0 "U1" H 4700 2700 30 0000 C CNN -F 1 "PORT" H 4650 2600 30 0000 C CNN -F 2 "" H 4650 2600 60 0000 C CNN -F 3 "" H 4650 2600 60 0000 C CNN - 14 4650 2600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4900 2600 5000 2600 -Wire Wire Line - 5000 2600 5000 3000 -Connection ~ 5000 3000 -$Comp -L PORT U1 -U 6 1 5C8F94B6 -P 3050 3600 -F 0 "U1" H 3100 3700 30 0000 C CNN -F 1 "PORT" H 3050 3600 30 0000 C CNN -F 2 "" H 3050 3600 60 0000 C CNN -F 3 "" H 3050 3600 60 0000 C CNN - 6 3050 3600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C8F95C0 -P 3050 3850 -F 0 "U1" H 3100 3950 30 0000 C CNN -F 1 "PORT" H 3050 3850 30 0000 C CNN -F 2 "" H 3050 3850 60 0000 C CNN -F 3 "" H 3050 3850 60 0000 C CNN - 3 3050 3850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C8F95E7 -P 3050 4100 -F 0 "U1" H 3100 4200 30 0000 C CNN -F 1 "PORT" H 3050 4100 30 0000 C CNN -F 2 "" H 3050 4100 60 0000 C CNN -F 3 "" H 3050 4100 60 0000 C CNN - 4 3050 4100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7100 3000 7100 3250 -Wire Wire Line - 7100 4650 7100 4450 -$Comp -L PORT U1 -U 8 1 5C8F9C35 -P 6000 3600 -F 0 "U1" H 6050 3700 30 0000 C CNN -F 1 "PORT" H 6000 3600 30 0000 C CNN -F 2 "" H 6000 3600 60 0000 C CNN -F 3 "" H 6000 3600 60 0000 C CNN - 8 6000 3600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C8F9C3B -P 6000 3850 -F 0 "U1" H 6050 3950 30 0000 C CNN -F 1 "PORT" H 6000 3850 30 0000 C CNN -F 2 "" H 6000 3850 60 0000 C CNN -F 3 "" H 6000 3850 60 0000 C CNN - 11 6000 3850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C8F9C41 -P 6000 4100 -F 0 "U1" H 6050 4200 30 0000 C CNN -F 1 "PORT" H 6000 4100 30 0000 C CNN -F 2 "" H 6000 4100 60 0000 C CNN -F 3 "" H 6000 4100 60 0000 C CNN - 10 6000 4100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C8F9D22 -P 5200 4100 -F 0 "U1" H 5250 4200 30 0000 C CNN -F 1 "PORT" H 5200 4100 30 0000 C CNN -F 2 "" H 5200 4100 60 0000 C CNN -F 3 "" H 5200 4100 60 0000 C CNN - 2 5200 4100 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C8F9D28 -P 5200 3850 -F 0 "U1" H 5250 3950 30 0000 C CNN -F 1 "PORT" H 5200 3850 30 0000 C CNN -F 2 "" H 5200 3850 60 0000 C CNN -F 3 "" H 5200 3850 60 0000 C CNN - 1 5200 3850 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C8F9D2E -P 5200 3600 -F 0 "U1" H 5250 3700 30 0000 C CNN -F 1 "PORT" H 5200 3600 30 0000 C CNN -F 2 "" H 5200 3600 60 0000 C CNN -F 3 "" H 5200 3600 60 0000 C CNN - 5 5200 3600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 12 1 5C8FA0FA -P 8250 4100 -F 0 "U1" H 8300 4200 30 0000 C CNN -F 1 "PORT" H 8250 4100 30 0000 C CNN -F 2 "" H 8250 4100 60 0000 C CNN -F 3 "" H 8250 4100 60 0000 C CNN - 12 8250 4100 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 13 1 5C8FA100 -P 8250 3850 -F 0 "U1" H 8300 3950 30 0000 C CNN -F 1 "PORT" H 8250 3850 30 0000 C CNN -F 2 "" H 8250 3850 60 0000 C CNN -F 3 "" H 8250 3850 60 0000 C CNN - 13 8250 3850 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C8FA106 -P 8250 3600 -F 0 "U1" H 8300 3700 30 0000 C CNN -F 1 "PORT" H 8250 3600 30 0000 C CNN -F 2 "" H 8250 3600 60 0000 C CNN -F 3 "" H 8250 3600 60 0000 C CNN - 9 8250 3600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 7 1 5C8FA319 -P 4950 5050 -F 0 "U1" H 5000 5150 30 0000 C CNN -F 1 "PORT" H 4950 5050 30 0000 C CNN -F 2 "" H 4950 5050 60 0000 C CNN -F 3 "" H 4950 5050 60 0000 C CNN - 7 4950 5050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5200 5050 5200 4650 -Connection ~ 5200 4650 -Wire Wire Line - 3300 3600 3600 3600 -Wire Wire Line - 3300 3850 3600 3850 -Wire Wire Line - 3300 4100 3600 4100 -Wire Wire Line - 4700 3600 4950 3600 -Wire Wire Line - 4700 3850 4950 3850 -Wire Wire Line - 4700 4100 4950 4100 -Wire Wire Line - 6250 3600 6550 3600 -Wire Wire Line - 6250 3850 6550 3850 -Wire Wire Line - 6250 4100 6550 4100 -Wire Wire Line - 8000 3600 7650 3600 -Wire Wire Line - 8000 3850 7650 3850 -Wire Wire Line - 8000 4100 7650 4100 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/556/556.sub b/src/SubcircuitLibrary/556/556.sub deleted file mode 100644 index a370b703..00000000 --- a/src/SubcircuitLibrary/556/556.sub +++ /dev/null @@ -1,9 +0,0 @@ -* Subcircuit 556 -.subckt 556 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ -* c:\esim\esim\src\subcircuitlibrary\556\556.cir -.include lm555n.sub -x1 net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad14_ lm555n -x2 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ lm555n -* Control Statements - -.ends 556
\ No newline at end of file diff --git a/src/SubcircuitLibrary/556/556_Previous_Values.xml b/src/SubcircuitLibrary/556/556_Previous_Values.xml deleted file mode 100644 index c025c2d1..00000000 --- a/src/SubcircuitLibrary/556/556_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and-cache.lib b/src/SubcircuitLibrary/5_and/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/5_and/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/5_and/3_and.cir b/src/SubcircuitLibrary/5_and/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/5_and/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/5_and/3_and.cir.out b/src/SubcircuitLibrary/5_and/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/5_and/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/5_and/3_and.pro b/src/SubcircuitLibrary/5_and/3_and.pro deleted file mode 100644 index 76df4655..00000000 --- a/src/SubcircuitLibrary/5_and/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5_and/3_and.sch b/src/SubcircuitLibrary/5_and/3_and.sch deleted file mode 100644 index d6ac89f9..00000000 --- a/src/SubcircuitLibrary/5_and/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:3_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -Text Notes 3500 2600 0 60 ~ 12 -in1 -Text Notes 3450 2800 0 60 ~ 12 -in2\n -Text Notes 3500 3100 0 60 ~ 12 -in3 -Text Notes 6100 2850 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/3_and.sub b/src/SubcircuitLibrary/5_and/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/5_and/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/5_and/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and-cache.lib b/src/SubcircuitLibrary/5_and/5_and-cache.lib deleted file mode 100644 index ac396288..00000000 --- a/src/SubcircuitLibrary/5_and/5_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/5_and/5_and.cir b/src/SubcircuitLibrary/5_and/5_and.cir deleted file mode 100644 index 6a05b9b5..00000000 --- a/src/SubcircuitLibrary/5_and/5_and.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and -U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and -U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT - -.end diff --git a/src/SubcircuitLibrary/5_and/5_and.cir.out b/src/SubcircuitLibrary/5_and/5_and.cir.out deleted file mode 100644 index 6a6b126a..00000000 --- a/src/SubcircuitLibrary/5_and/5_and.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port -a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/5_and/5_and.pro b/src/SubcircuitLibrary/5_and/5_and.pro deleted file mode 100644 index 7a2f090e..00000000 --- a/src/SubcircuitLibrary/5_and/5_and.pro +++ /dev/null @@ -1,50 +0,0 @@ -update=06/01/19 11:31:03 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=cypress -LibName2=siliconi -LibName3=opto -LibName4=atmel -LibName5=contrib -LibName6=valves -LibName7=eSim_Analog -LibName8=eSim_Devices -LibName9=eSim_Digital -LibName10=eSim_Hybrid -LibName11=eSim_Miscellaneous -LibName12=eSim_Plot -LibName13=eSim_Power -LibName14=eSim_PSpice -LibName15=eSim_Sources -LibName16=eSim_Subckt -LibName17=eSim_User diff --git a/src/SubcircuitLibrary/5_and/5_and.sch b/src/SubcircuitLibrary/5_and/5_and.sch deleted file mode 100644 index e9eb58ee..00000000 --- a/src/SubcircuitLibrary/5_and/5_and.sch +++ /dev/null @@ -1,171 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:5_and-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5C9A2741 -P 3800 3350 -F 0 "X1" H 4700 3650 60 0000 C CNN -F 1 "3_and" H 4750 3850 60 0000 C CNN -F 2 "" H 3800 3350 60 0000 C CNN -F 3 "" H 3800 3350 60 0000 C CNN - 1 3800 3350 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C9A2764 -P 4650 3400 -F 0 "U2" H 4650 3400 60 0000 C CNN -F 1 "d_and" H 4700 3500 60 0000 C CNN -F 2 "" H 4650 3400 60 0000 C CNN -F 3 "" H 4650 3400 60 0000 C CNN - 1 4650 3400 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2791 -P 5550 3200 -F 0 "U3" H 5550 3200 60 0000 C CNN -F 1 "d_and" H 5600 3300 60 0000 C CNN -F 2 "" H 5550 3200 60 0000 C CNN -F 3 "" H 5550 3200 60 0000 C CNN - 1 5550 3200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5100 3100 5100 2950 -Wire Wire Line - 5100 3200 5100 3350 -Wire Wire Line - 4250 2850 4250 2700 -Wire Wire Line - 4250 2700 3600 2700 -Wire Wire Line - 4250 2950 4150 2950 -Wire Wire Line - 4150 2950 4150 2900 -Wire Wire Line - 4150 2900 3600 2900 -Wire Wire Line - 4200 3300 3600 3300 -Wire Wire Line - 4250 3050 4250 3100 -Wire Wire Line - 4250 3100 3600 3100 -Wire Wire Line - 4200 3400 4200 3500 -Wire Wire Line - 4200 3500 3600 3500 -Wire Wire Line - 6000 3150 6500 3150 -$Comp -L PORT U1 -U 1 1 5C9A2865 -P 3350 2700 -F 0 "U1" H 3400 2800 30 0000 C CNN -F 1 "PORT" H 3350 2700 30 0000 C CNN -F 2 "" H 3350 2700 60 0000 C CNN -F 3 "" H 3350 2700 60 0000 C CNN - 1 3350 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A28B6 -P 3350 2900 -F 0 "U1" H 3400 3000 30 0000 C CNN -F 1 "PORT" H 3350 2900 30 0000 C CNN -F 2 "" H 3350 2900 60 0000 C CNN -F 3 "" H 3350 2900 60 0000 C CNN - 2 3350 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A28D9 -P 3350 3100 -F 0 "U1" H 3400 3200 30 0000 C CNN -F 1 "PORT" H 3350 3100 30 0000 C CNN -F 2 "" H 3350 3100 60 0000 C CNN -F 3 "" H 3350 3100 60 0000 C CNN - 3 3350 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A28FF -P 3350 3300 -F 0 "U1" H 3400 3400 30 0000 C CNN -F 1 "PORT" H 3350 3300 30 0000 C CNN -F 2 "" H 3350 3300 60 0000 C CNN -F 3 "" H 3350 3300 60 0000 C CNN - 4 3350 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A2928 -P 3350 3500 -F 0 "U1" H 3400 3600 30 0000 C CNN -F 1 "PORT" H 3350 3500 30 0000 C CNN -F 2 "" H 3350 3500 60 0000 C CNN -F 3 "" H 3350 3500 60 0000 C CNN - 5 3350 3500 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C9A2958 -P 6750 3150 -F 0 "U1" H 6800 3250 30 0000 C CNN -F 1 "PORT" H 6750 3150 30 0000 C CNN -F 2 "" H 6750 3150 60 0000 C CNN -F 3 "" H 6750 3150 60 0000 C CNN - 6 6750 3150 - -1 0 0 1 -$EndComp -Text Notes 3800 2700 0 60 ~ 12 -in1 -Text Notes 3800 2900 0 60 ~ 12 -in2 -Text Notes 3800 3100 0 60 ~ 12 -in3 -Text Notes 3800 3300 0 60 ~ 12 -in4 -Text Notes 3800 3500 0 60 ~ 12 -in5 -Text Notes 6150 3150 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_and/5_and.sub b/src/SubcircuitLibrary/5_and/5_and.sub deleted file mode 100644 index 35b10e17..00000000 --- a/src/SubcircuitLibrary/5_and/5_and.sub +++ /dev/null @@ -1,16 +0,0 @@ -* Subcircuit 5_and -.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and -a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml deleted file mode 100644 index ae2c08a7..00000000 --- a/src/SubcircuitLibrary/5_and/5_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_and/analysis b/src/SubcircuitLibrary/5_and/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/5_and/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/3_and-cache.lib b/src/SubcircuitLibrary/5_nand/3_and-cache.lib deleted file mode 100644 index 0a3ccf7f..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir b/src/SubcircuitLibrary/5_nand/3_and.cir deleted file mode 100644 index 15f8954d..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/3_and.cir.out b/src/SubcircuitLibrary/5_nand/3_and.cir.out deleted file mode 100644 index e3c96645..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/3_and.pro b/src/SubcircuitLibrary/5_nand/3_and.pro deleted file mode 100644 index 0fdf4d25..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_nand/3_and.sch b/src/SubcircuitLibrary/5_nand/3_and.sch deleted file mode 100644 index c853bf49..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/3_and.sub b/src/SubcircuitLibrary/5_nand/3_and.sub deleted file mode 100644 index b949ae4f..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/5_nand/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_and-cache.lib b/src/SubcircuitLibrary/5_nand/5_and-cache.lib deleted file mode 100644 index 4cf915be..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir b/src/SubcircuitLibrary/5_nand/5_and.cir deleted file mode 100644 index ca1199bd..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
-U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
-U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_and.cir.out b/src/SubcircuitLibrary/5_nand/5_and.cir.out deleted file mode 100644 index 20d3f8a5..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nand/5_and.pro b/src/SubcircuitLibrary/5_nand/5_and.pro deleted file mode 100644 index a9d6304f..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and.pro +++ /dev/null @@ -1,50 +0,0 @@ -update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_nand/5_and.sch b/src/SubcircuitLibrary/5_nand/5_and.sch deleted file mode 100644 index 0d86cdec..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and.sch +++ /dev/null @@ -1,171 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60 0000 C CNN
-F 1 "3_and" H 4750 3850 60 0000 C CNN
-F 2 "" H 3800 3350 60 0000 C CNN
-F 3 "" H 3800 3350 60 0000 C CNN
- 1 3800 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2764
-P 4650 3400
-F 0 "U2" H 4650 3400 60 0000 C CNN
-F 1 "d_and" H 4700 3500 60 0000 C CNN
-F 2 "" H 4650 3400 60 0000 C CNN
-F 3 "" H 4650 3400 60 0000 C CNN
- 1 4650 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2791
-P 5550 3200
-F 0 "U3" H 5550 3200 60 0000 C CNN
-F 1 "d_and" H 5600 3300 60 0000 C CNN
-F 2 "" H 5550 3200 60 0000 C CNN
-F 3 "" H 5550 3200 60 0000 C CNN
- 1 5550 3200
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5100 3100 5100 2950
-Wire Wire Line
- 5100 3200 5100 3350
-Wire Wire Line
- 4250 2850 4250 2700
-Wire Wire Line
- 4250 2700 3600 2700
-Wire Wire Line
- 4250 2950 4150 2950
-Wire Wire Line
- 4150 2950 4150 2900
-Wire Wire Line
- 4150 2900 3600 2900
-Wire Wire Line
- 4200 3300 3600 3300
-Wire Wire Line
- 4250 3050 4250 3100
-Wire Wire Line
- 4250 3100 3600 3100
-Wire Wire Line
- 4200 3400 4200 3500
-Wire Wire Line
- 4200 3500 3600 3500
-Wire Wire Line
- 6000 3150 6500 3150
-$Comp
-L PORT U1
-U 1 1 5C9A2865
-P 3350 2700
-F 0 "U1" H 3400 2800 30 0000 C CNN
-F 1 "PORT" H 3350 2700 30 0000 C CNN
-F 2 "" H 3350 2700 60 0000 C CNN
-F 3 "" H 3350 2700 60 0000 C CNN
- 1 3350 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A28B6
-P 3350 2900
-F 0 "U1" H 3400 3000 30 0000 C CNN
-F 1 "PORT" H 3350 2900 30 0000 C CNN
-F 2 "" H 3350 2900 60 0000 C CNN
-F 3 "" H 3350 2900 60 0000 C CNN
- 2 3350 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A28D9
-P 3350 3100
-F 0 "U1" H 3400 3200 30 0000 C CNN
-F 1 "PORT" H 3350 3100 30 0000 C CNN
-F 2 "" H 3350 3100 60 0000 C CNN
-F 3 "" H 3350 3100 60 0000 C CNN
- 3 3350 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A28FF
-P 3350 3300
-F 0 "U1" H 3400 3400 30 0000 C CNN
-F 1 "PORT" H 3350 3300 30 0000 C CNN
-F 2 "" H 3350 3300 60 0000 C CNN
-F 3 "" H 3350 3300 60 0000 C CNN
- 4 3350 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
-P 3350 3500
-F 0 "U1" H 3400 3600 30 0000 C CNN
-F 1 "PORT" H 3350 3500 30 0000 C CNN
-F 2 "" H 3350 3500 60 0000 C CNN
-F 3 "" H 3350 3500 60 0000 C CNN
- 5 3350 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
-P 6750 3150
-F 0 "U1" H 6800 3250 30 0000 C CNN
-F 1 "PORT" H 6750 3150 30 0000 C CNN
-F 2 "" H 6750 3150 60 0000 C CNN
-F 3 "" H 6750 3150 60 0000 C CNN
- 6 6750 3150
- -1 0 0 1
-$EndComp
-Text Notes 3800 2700 0 60 ~ 12
-in1
-Text Notes 3800 2900 0 60 ~ 12
-in2
-Text Notes 3800 3100 0 60 ~ 12
-in3
-Text Notes 3800 3300 0 60 ~ 12
-in4
-Text Notes 3800 3500 0 60 ~ 12
-in5
-Text Notes 6150 3150 0 60 ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nand/5_and.sub b/src/SubcircuitLibrary/5_nand/5_and.sub deleted file mode 100644 index 9d929fcb..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and.sub +++ /dev/null @@ -1,16 +0,0 @@ -* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml deleted file mode 100644 index ae2c08a7..00000000 --- a/src/SubcircuitLibrary/5_nand/5_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib b/src/SubcircuitLibrary/5_nand/5_nand-cache.lib deleted file mode 100644 index cb517be1..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand-cache.lib +++ /dev/null @@ -1,78 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir b/src/SubcircuitLibrary/5_nand/5_nand.cir deleted file mode 100644 index e833d0f4..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand.cir +++ /dev/null @@ -1,13 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nand/5_nand.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 21 16:57:27 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad1_ 5_and -U2 Net-_U2-Pad1_ Net-_U1-Pad6_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT - -.end diff --git a/src/SubcircuitLibrary/5_nand/5_nand.cir.out b/src/SubcircuitLibrary/5_nand/5_nand.cir.out deleted file mode 100644 index 164de911..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir - -.include 5_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and -* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port -a1 net-_u2-pad1_ net-_u1-pad6_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/5_nand/5_nand.pro b/src/SubcircuitLibrary/5_nand/5_nand.pro deleted file mode 100644 index b7d23f44..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand.pro +++ /dev/null @@ -1,83 +0,0 @@ -update=Fri Jun 21 16:46:10 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice -LibName40=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName41=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName42=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName43=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName44=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName45=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName46=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName47=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName48=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName49=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User - diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sch b/src/SubcircuitLibrary/5_nand/5_nand.sch deleted file mode 100644 index 86379b08..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand.sch +++ /dev/null @@ -1,175 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 5_and X1 -U 1 1 5D0CBD44 -P 4150 3700 -F 0 "X1" H 4200 3600 60 0000 C CNN -F 1 "5_and" H 4250 3850 60 0000 C CNN -F 2 "" H 4150 3700 60 0000 C CNN -F 3 "" H 4150 3700 60 0000 C CNN - 1 4150 3700 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U2 -U 1 1 5D0CBD97 -P 5150 3700 -F 0 "U2" H 5150 3600 60 0000 C CNN -F 1 "d_inverter" H 5150 3850 60 0000 C CNN -F 2 "" H 5200 3650 60 0000 C CNN -F 3 "" H 5200 3650 60 0000 C CNN - 1 5150 3700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5D0CBDBE -P 2900 2900 -F 0 "U1" H 2950 3000 30 0000 C CNN -F 1 "PORT" H 2900 2900 30 0000 C CNN -F 2 "" H 2900 2900 60 0000 C CNN -F 3 "" H 2900 2900 60 0000 C CNN - 1 2900 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D0CBDF4 -P 2900 3150 -F 0 "U1" H 2950 3250 30 0000 C CNN -F 1 "PORT" H 2900 3150 30 0000 C CNN -F 2 "" H 2900 3150 60 0000 C CNN -F 3 "" H 2900 3150 60 0000 C CNN - 2 2900 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5D0CBE16 -P 2900 3400 -F 0 "U1" H 2950 3500 30 0000 C CNN -F 1 "PORT" H 2900 3400 30 0000 C CNN -F 2 "" H 2900 3400 60 0000 C CNN -F 3 "" H 2900 3400 60 0000 C CNN - 3 2900 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5D0CBE3F -P 2900 3750 -F 0 "U1" H 2950 3850 30 0000 C CNN -F 1 "PORT" H 2900 3750 30 0000 C CNN -F 2 "" H 2900 3750 60 0000 C CNN -F 3 "" H 2900 3750 60 0000 C CNN - 4 2900 3750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5D0CBE6B -P 2900 4150 -F 0 "U1" H 2950 4250 30 0000 C CNN -F 1 "PORT" H 2900 4150 30 0000 C CNN -F 2 "" H 2900 4150 60 0000 C CNN -F 3 "" H 2900 4150 60 0000 C CNN - 5 2900 4150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5D0CBE9C -P 6200 3700 -F 0 "U1" H 6250 3800 30 0000 C CNN -F 1 "PORT" H 6200 3700 30 0000 C CNN -F 2 "" H 6200 3700 60 0000 C CNN -F 3 "" H 6200 3700 60 0000 C CNN - 6 6200 3700 - -1 0 0 1 -$EndComp -Wire Wire Line - 3150 2900 3700 2900 -Wire Wire Line - 3700 2900 3700 3500 -Wire Wire Line - 3700 3600 3500 3600 -Wire Wire Line - 3500 3600 3500 3150 -Wire Wire Line - 3500 3150 3150 3150 -Wire Wire Line - 3150 3400 3350 3400 -Wire Wire Line - 3350 3400 3350 3700 -Wire Wire Line - 3350 3700 3700 3700 -Wire Wire Line - 3700 3800 3250 3800 -Wire Wire Line - 3250 3800 3250 3750 -Wire Wire Line - 3250 3750 3150 3750 -Wire Wire Line - 3150 4150 3350 4150 -Wire Wire Line - 3350 4150 3350 3900 -Wire Wire Line - 3350 3900 3700 3900 -Wire Wire Line - 4700 3700 4850 3700 -Wire Wire Line - 5450 3700 5950 3700 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nand/5_nand.sub b/src/SubcircuitLibrary/5_nand/5_nand.sub deleted file mode 100644 index c3e041fa..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 5_nand -.subckt 5_nand net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nand/5_nand.cir -.include 5_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad1_ 5_and -* u2 net-_u2-pad1_ net-_u1-pad6_ d_inverter -a1 net-_u2-pad1_ net-_u1-pad6_ u2 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_nand
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml b/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml deleted file mode 100644 index c4b4cde2..00000000 --- a/src/SubcircuitLibrary/5_nand/5_nand_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nand/analysis b/src/SubcircuitLibrary/5_nand/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/5_nand/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/3_and-cache.lib b/src/SubcircuitLibrary/5_nor/3_and-cache.lib deleted file mode 100644 index 0a3ccf7f..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nor/3_and.cir b/src/SubcircuitLibrary/5_nor/3_and.cir deleted file mode 100644 index 15f8954d..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
-U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nor/3_and.cir.out b/src/SubcircuitLibrary/5_nor/3_and.cir.out deleted file mode 100644 index e3c96645..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nor/3_and.pro b/src/SubcircuitLibrary/5_nor/3_and.pro deleted file mode 100644 index 0fdf4d25..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/src/SubcircuitLibrary/5_nor/3_and.sch b/src/SubcircuitLibrary/5_nor/3_and.sch deleted file mode 100644 index c853bf49..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and.sch +++ /dev/null @@ -1,130 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:3_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60 0000 C CNN
-F 1 "d_and" H 4300 2800 60 0000 C CNN
-F 2 "" H 4250 2700 60 0000 C CNN
-F 3 "" H 4250 2700 60 0000 C CNN
- 1 4250 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60 0000 C CNN
-F 1 "d_and" H 5200 3000 60 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30 0000 C CNN
-F 1 "PORT" H 3050 2600 30 0000 C CNN
-F 2 "" H 3050 2600 60 0000 C CNN
-F 3 "" H 3050 2600 60 0000 C CNN
- 1 3050 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30 0000 C CNN
-F 1 "PORT" H 3050 2800 30 0000 C CNN
-F 2 "" H 3050 2800 60 0000 C CNN
-F 3 "" H 3050 2800 60 0000 C CNN
- 2 3050 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30 0000 C CNN
-F 1 "PORT" H 3050 3100 30 0000 C CNN
-F 2 "" H 3050 3100 60 0000 C CNN
-F 3 "" H 3050 3100 60 0000 C CNN
- 3 3050 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30 0000 C CNN
-F 1 "PORT" H 6900 2850 30 0000 C CNN
-F 2 "" H 6900 2850 60 0000 C CNN
-F 3 "" H 6900 2850 60 0000 C CNN
- 4 6900 2850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4700 2650 4700 2800
-Wire Wire Line
- 5600 2850 6650 2850
-Wire Wire Line
- 3800 2600 3300 2600
-Wire Wire Line
- 3800 2700 3300 2700
-Wire Wire Line
- 3300 2700 3300 2800
-Wire Wire Line
- 3300 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Text Notes 3500 2600 0 60 ~ 12
-in1
-Text Notes 3450 2800 0 60 ~ 12
-in2\n
-Text Notes 3500 3100 0 60 ~ 12
-in3
-Text Notes 6100 2850 0 60 ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nor/3_and.sub b/src/SubcircuitLibrary/5_nor/3_and.sub deleted file mode 100644 index b949ae4f..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/5_nor/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_and-cache.lib b/src/SubcircuitLibrary/5_nor/5_and-cache.lib deleted file mode 100644 index 4cf915be..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5_nor/5_and.cir b/src/SubcircuitLibrary/5_nor/5_and.cir deleted file mode 100644 index ca1199bd..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
-U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
-U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5_nor/5_and.cir.out b/src/SubcircuitLibrary/5_nor/5_and.cir.out deleted file mode 100644 index 20d3f8a5..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5_nor/5_and.pro b/src/SubcircuitLibrary/5_nor/5_and.pro deleted file mode 100644 index a9d6304f..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and.pro +++ /dev/null @@ -1,50 +0,0 @@ -update=06/01/19 11:31:03
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=cypress
-LibName2=siliconi
-LibName3=opto
-LibName4=atmel
-LibName5=contrib
-LibName6=valves
-LibName7=eSim_Analog
-LibName8=eSim_Devices
-LibName9=eSim_Digital
-LibName10=eSim_Hybrid
-LibName11=eSim_Miscellaneous
-LibName12=eSim_Plot
-LibName13=eSim_Power
-LibName14=eSim_PSpice
-LibName15=eSim_Sources
-LibName16=eSim_Subckt
-LibName17=eSim_User
diff --git a/src/SubcircuitLibrary/5_nor/5_and.sch b/src/SubcircuitLibrary/5_nor/5_and.sch deleted file mode 100644 index 0d86cdec..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and.sch +++ /dev/null @@ -1,171 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:5_and-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L 3_and X1
-U 1 1 5C9A2741
-P 3800 3350
-F 0 "X1" H 4700 3650 60 0000 C CNN
-F 1 "3_and" H 4750 3850 60 0000 C CNN
-F 2 "" H 3800 3350 60 0000 C CNN
-F 3 "" H 3800 3350 60 0000 C CNN
- 1 3800 3350
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U2
-U 1 1 5C9A2764
-P 4650 3400
-F 0 "U2" H 4650 3400 60 0000 C CNN
-F 1 "d_and" H 4700 3500 60 0000 C CNN
-F 2 "" H 4650 3400 60 0000 C CNN
-F 3 "" H 4650 3400 60 0000 C CNN
- 1 4650 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2791
-P 5550 3200
-F 0 "U3" H 5550 3200 60 0000 C CNN
-F 1 "d_and" H 5600 3300 60 0000 C CNN
-F 2 "" H 5550 3200 60 0000 C CNN
-F 3 "" H 5550 3200 60 0000 C CNN
- 1 5550 3200
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5100 3100 5100 2950
-Wire Wire Line
- 5100 3200 5100 3350
-Wire Wire Line
- 4250 2850 4250 2700
-Wire Wire Line
- 4250 2700 3600 2700
-Wire Wire Line
- 4250 2950 4150 2950
-Wire Wire Line
- 4150 2950 4150 2900
-Wire Wire Line
- 4150 2900 3600 2900
-Wire Wire Line
- 4200 3300 3600 3300
-Wire Wire Line
- 4250 3050 4250 3100
-Wire Wire Line
- 4250 3100 3600 3100
-Wire Wire Line
- 4200 3400 4200 3500
-Wire Wire Line
- 4200 3500 3600 3500
-Wire Wire Line
- 6000 3150 6500 3150
-$Comp
-L PORT U1
-U 1 1 5C9A2865
-P 3350 2700
-F 0 "U1" H 3400 2800 30 0000 C CNN
-F 1 "PORT" H 3350 2700 30 0000 C CNN
-F 2 "" H 3350 2700 60 0000 C CNN
-F 3 "" H 3350 2700 60 0000 C CNN
- 1 3350 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A28B6
-P 3350 2900
-F 0 "U1" H 3400 3000 30 0000 C CNN
-F 1 "PORT" H 3350 2900 30 0000 C CNN
-F 2 "" H 3350 2900 60 0000 C CNN
-F 3 "" H 3350 2900 60 0000 C CNN
- 2 3350 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A28D9
-P 3350 3100
-F 0 "U1" H 3400 3200 30 0000 C CNN
-F 1 "PORT" H 3350 3100 30 0000 C CNN
-F 2 "" H 3350 3100 60 0000 C CNN
-F 3 "" H 3350 3100 60 0000 C CNN
- 3 3350 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A28FF
-P 3350 3300
-F 0 "U1" H 3400 3400 30 0000 C CNN
-F 1 "PORT" H 3350 3300 30 0000 C CNN
-F 2 "" H 3350 3300 60 0000 C CNN
-F 3 "" H 3350 3300 60 0000 C CNN
- 4 3350 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9A2928
-P 3350 3500
-F 0 "U1" H 3400 3600 30 0000 C CNN
-F 1 "PORT" H 3350 3500 30 0000 C CNN
-F 2 "" H 3350 3500 60 0000 C CNN
-F 3 "" H 3350 3500 60 0000 C CNN
- 5 3350 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9A2958
-P 6750 3150
-F 0 "U1" H 6800 3250 30 0000 C CNN
-F 1 "PORT" H 6750 3150 30 0000 C CNN
-F 2 "" H 6750 3150 60 0000 C CNN
-F 3 "" H 6750 3150 60 0000 C CNN
- 6 6750 3150
- -1 0 0 1
-$EndComp
-Text Notes 3800 2700 0 60 ~ 12
-in1
-Text Notes 3800 2900 0 60 ~ 12
-in2
-Text Notes 3800 3100 0 60 ~ 12
-in3
-Text Notes 3800 3300 0 60 ~ 12
-in4
-Text Notes 3800 3500 0 60 ~ 12
-in5
-Text Notes 6150 3150 0 60 ~ 12
-out
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5_nor/5_and.sub b/src/SubcircuitLibrary/5_nor/5_and.sub deleted file mode 100644 index 9d929fcb..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and.sub +++ /dev/null @@ -1,16 +0,0 @@ -* Subcircuit 5_and
-.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
-* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
-.include 3_and.sub
-x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
-* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
-* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
-a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
-a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml deleted file mode 100644 index ae2c08a7..00000000 --- a/src/SubcircuitLibrary/5_nor/5_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_nor-cache.lib b/src/SubcircuitLibrary/5_nor/5_nor-cache.lib deleted file mode 100644 index 7098010f..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor-cache.lib +++ /dev/null @@ -1,95 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/5_nor/5_nor.cir b/src/SubcircuitLibrary/5_nor/5_nor.cir deleted file mode 100644 index 0e4db1ea..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor.cir +++ /dev/null @@ -1,19 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and -U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter -U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter -U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter -U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter -U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter -U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT -X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and - -.end diff --git a/src/SubcircuitLibrary/5_nor/5_nor.cir.out b/src/SubcircuitLibrary/5_nor/5_nor.cir.out deleted file mode 100644 index bc90e004..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor.cir.out +++ /dev/null @@ -1,42 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir - -.include 5_and.sub -* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter -* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port -x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and -a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 net-_u1-pad2_ net-_u3-pad2_ u3 -a4 net-_u1-pad3_ net-_u4-pad2_ u4 -a5 net-_u1-pad4_ net-_u5-pad2_ u5 -a6 net-_u1-pad5_ net-_u6-pad2_ u6 -a7 net-_u1-pad6_ net-_u7-pad2_ u7 -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/5_nor/5_nor.pro b/src/SubcircuitLibrary/5_nor/5_nor.pro deleted file mode 100644 index 4716d4ae..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor.pro +++ /dev/null @@ -1,73 +0,0 @@ -update=Tue Jun 25 23:32:34 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_User -LibName37=eSim_Plot -LibName38=eSim_PSpice -LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt - diff --git a/src/SubcircuitLibrary/5_nor/5_nor.sch b/src/SubcircuitLibrary/5_nor/5_nor.sch deleted file mode 100644 index 6bb6fcb8..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor.sch +++ /dev/null @@ -1,275 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:eSim_Subckt -LIBS:c_gate-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U8 -U 1 1 5D126275 -P 5600 3300 -F 0 "U8" H 5600 3300 60 0000 C CNN -F 1 "d_and" H 5650 3400 60 0000 C CNN -F 2 "" H 5600 3300 60 0000 C CNN -F 3 "" H 5600 3300 60 0000 C CNN - 1 5600 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5150 3200 5150 2850 -Wire Wire Line - 4150 2650 4150 2350 -Wire Wire Line - 4150 2350 3600 2350 -Wire Wire Line - 4150 2750 4050 2750 -Wire Wire Line - 4050 2750 4050 2550 -Wire Wire Line - 4050 2550 3600 2550 -Wire Wire Line - 4150 2850 3700 2850 -Wire Wire Line - 3700 2850 3700 2750 -Wire Wire Line - 3700 2750 3600 2750 -Wire Wire Line - 4150 2950 3600 2950 -Wire Wire Line - 4150 3050 4150 3150 -Wire Wire Line - 4150 3150 3600 3150 -Wire Wire Line - 5150 3300 3600 3300 -$Comp -L d_inverter U2 -U 1 1 5D126276 -P 3300 2350 -F 0 "U2" H 3300 2250 60 0000 C CNN -F 1 "d_inverter" H 3300 2500 60 0000 C CNN -F 2 "" H 3350 2300 60 0000 C CNN -F 3 "" H 3350 2300 60 0000 C CNN - 1 3300 2350 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5D126277 -P 3300 2550 -F 0 "U3" H 3300 2450 60 0000 C CNN -F 1 "d_inverter" H 3300 2700 60 0000 C CNN -F 2 "" H 3350 2500 60 0000 C CNN -F 3 "" H 3350 2500 60 0000 C CNN - 1 3300 2550 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5D126278 -P 3300 2750 -F 0 "U4" H 3300 2650 60 0000 C CNN -F 1 "d_inverter" H 3300 2900 60 0000 C CNN -F 2 "" H 3350 2700 60 0000 C CNN -F 3 "" H 3350 2700 60 0000 C CNN - 1 3300 2750 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U5 -U 1 1 5D126279 -P 3300 2950 -F 0 "U5" H 3300 2850 60 0000 C CNN -F 1 "d_inverter" H 3300 3100 60 0000 C CNN -F 2 "" H 3350 2900 60 0000 C CNN -F 3 "" H 3350 2900 60 0000 C CNN - 1 3300 2950 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U6 -U 1 1 5D12627A -P 3300 3150 -F 0 "U6" H 3300 3050 60 0000 C CNN -F 1 "d_inverter" H 3300 3300 60 0000 C CNN -F 2 "" H 3350 3100 60 0000 C CNN -F 3 "" H 3350 3100 60 0000 C CNN - 1 3300 3150 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U7 -U 1 1 5D12627B -P 3300 3300 -F 0 "U7" H 3300 3200 60 0000 C CNN -F 1 "d_inverter" H 3300 3450 60 0000 C CNN -F 2 "" H 3350 3250 60 0000 C CNN -F 3 "" H 3350 3250 60 0000 C CNN - 1 3300 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3000 2350 2000 2350 -Wire Wire Line - 3000 2550 2000 2550 -Wire Wire Line - 3000 2750 2050 2750 -Wire Wire Line - 3000 2950 2050 2950 -Wire Wire Line - 3000 3150 2050 3150 -Wire Wire Line - 3000 3300 2050 3300 -Wire Wire Line - 6050 3250 6950 3250 -$Comp -L PORT U1 -U 1 1 5D12627C -P 1750 2350 -F 0 "U1" H 1800 2450 30 0000 C CNN -F 1 "PORT" H 1750 2350 30 0000 C CNN -F 2 "" H 1750 2350 60 0000 C CNN -F 3 "" H 1750 2350 60 0000 C CNN - 1 1750 2350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D12627D -P 1750 2550 -F 0 "U1" H 1800 2650 30 0000 C CNN -F 1 "PORT" H 1750 2550 30 0000 C CNN -F 2 "" H 1750 2550 60 0000 C CNN -F 3 "" H 1750 2550 60 0000 C CNN - 2 1750 2550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5D12627E -P 1800 2750 -F 0 "U1" H 1850 2850 30 0000 C CNN -F 1 "PORT" H 1800 2750 30 0000 C CNN -F 2 "" H 1800 2750 60 0000 C CNN -F 3 "" H 1800 2750 60 0000 C CNN - 3 1800 2750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5D12627F -P 1800 2950 -F 0 "U1" H 1850 3050 30 0000 C CNN -F 1 "PORT" H 1800 2950 30 0000 C CNN -F 2 "" H 1800 2950 60 0000 C CNN -F 3 "" H 1800 2950 60 0000 C CNN - 4 1800 2950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5D126280 -P 1800 3150 -F 0 "U1" H 1850 3250 30 0000 C CNN -F 1 "PORT" H 1800 3150 30 0000 C CNN -F 2 "" H 1800 3150 60 0000 C CNN -F 3 "" H 1800 3150 60 0000 C CNN - 5 1800 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5D126281 -P 1800 3300 -F 0 "U1" H 1850 3400 30 0000 C CNN -F 1 "PORT" H 1800 3300 30 0000 C CNN -F 2 "" H 1800 3300 60 0000 C CNN -F 3 "" H 1800 3300 60 0000 C CNN - 6 1800 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5D126282 -P 7200 3250 -F 0 "U1" H 7250 3350 30 0000 C CNN -F 1 "PORT" H 7200 3250 30 0000 C CNN -F 2 "" H 7200 3250 60 0000 C CNN -F 3 "" H 7200 3250 60 0000 C CNN - 7 7200 3250 - -1 0 0 1 -$EndComp -Text Notes 2400 2350 0 60 ~ 12 -in1 -Text Notes 2400 2550 0 60 ~ 12 -in2 -Text Notes 2400 2750 0 60 ~ 12 -in3 -Text Notes 2400 2950 0 60 ~ 12 -in4 -Text Notes 2400 3150 0 60 ~ 12 -in5 -Text Notes 2400 3300 0 60 ~ 12 -in6 -Text Notes 6350 3250 0 60 ~ 12 -out -$Comp -L 5_and X1 -U 1 1 5D1262D5 -P 4600 2850 -F 0 "X1" H 4650 2750 60 0000 C CNN -F 1 "5_and" H 4700 3000 60 0000 C CNN -F 2 "" H 4600 2850 60 0000 C CNN -F 3 "" H 4600 2850 60 0000 C CNN - 1 4600 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5_nor/5_nor.sub b/src/SubcircuitLibrary/5_nor/5_nor.sub deleted file mode 100644 index dbcdb750..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor.sub +++ /dev/null @@ -1,36 +0,0 @@ -* Subcircuit 5_nor -.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir -.include 5_and.sub -* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter -* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter -x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and -a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 net-_u1-pad2_ net-_u3-pad2_ u3 -a4 net-_u1-pad3_ net-_u4-pad2_ u4 -a5 net-_u1-pad4_ net-_u5-pad2_ u5 -a6 net-_u1-pad5_ net-_u6-pad2_ u6 -a7 net-_u1-pad6_ net-_u7-pad2_ u7 -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_nor
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml deleted file mode 100644 index 75f5258c..00000000 --- a/src/SubcircuitLibrary/5_nor/5_nor_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5_nor/analysis b/src/SubcircuitLibrary/5_nor/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/5_nor/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib deleted file mode 100644 index b75ae867..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# Full-Adder -# -DEF Full-Adder X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "Full-Adder" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 200 300 -200 0 1 0 N -X A 1 -500 150 200 R 50 50 1 1 I -X B 2 -500 0 200 R 50 50 1 1 I -X Cin 3 -500 -150 200 R 50 50 1 1 I -X Out 4 500 100 200 L 50 50 1 1 I -X Cout 5 500 -100 200 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir deleted file mode 100644 index 84b7b723..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir +++ /dev/null @@ -1,16 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\5bit-Ripple_carry_adder\5bit-Ripple_carry_adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 02:16:47
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X4 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X4-Pad3_ Net-_U1-Pad4_ ? Full-Adder
-X5 Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X5-Pad3_ Net-_U1-Pad7_ Net-_X4-Pad3_ Full-Adder
-X6 Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X6-Pad3_ Net-_U1-Pad10_ Net-_X5-Pad3_ Full-Adder
-X7 Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_X7-Pad3_ Net-_U1-Pad13_ Net-_X6-Pad3_ Full-Adder
-X8 Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X7-Pad3_ Full-Adder
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out deleted file mode 100644 index dfda0a3b..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir
-
-.include Full-Adder.sub
-x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder
-x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder
-x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder
-x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder
-x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
-.ac lin 0 0Hz 0Hz
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro deleted file mode 100644 index d3bfc6c4..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=Sat Jun 22 12:25:13 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../eSim-1.1.2/kicadSchematicLibrary -[eeschema/libraries] -LibName1=9bit-BoothMultiplier-cache -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch deleted file mode 100644 index dd2e9165..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sch +++ /dev/null @@ -1,386 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:5bit-Ripple_carry_adder-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L Full-Adder X4 -U 1 1 5C93C7FA -P 3000 3550 -F 0 "X4" H 3000 3550 60 0000 C CNN -F 1 "Full-Adder" H 3000 3550 60 0000 C CNN -F 2 "" H 3000 3550 60 0000 C CNN -F 3 "" H 3000 3550 60 0000 C CNN - 1 3000 3550 - 1 0 0 -1 -$EndComp -$Comp -L Full-Adder X5 -U 1 1 5C93C84A -P 4350 3550 -F 0 "X5" H 4350 3550 60 0000 C CNN -F 1 "Full-Adder" H 4350 3550 60 0000 C CNN -F 2 "" H 4350 3550 60 0000 C CNN -F 3 "" H 4350 3550 60 0000 C CNN - 1 4350 3550 - 1 0 0 -1 -$EndComp -$Comp -L Full-Adder X6 -U 1 1 5C93C897 -P 5700 3550 -F 0 "X6" H 5700 3550 60 0000 C CNN -F 1 "Full-Adder" H 5700 3550 60 0000 C CNN -F 2 "" H 5700 3550 60 0000 C CNN -F 3 "" H 5700 3550 60 0000 C CNN - 1 5700 3550 - 1 0 0 -1 -$EndComp -$Comp -L Full-Adder X7 -U 1 1 5C93C961 -P 7000 3550 -F 0 "X7" H 7000 3550 60 0000 C CNN -F 1 "Full-Adder" H 7000 3550 60 0000 C CNN -F 2 "" H 7000 3550 60 0000 C CNN -F 3 "" H 7000 3550 60 0000 C CNN - 1 7000 3550 - 1 0 0 -1 -$EndComp -$Comp -L Full-Adder X8 -U 1 1 5C93C9A8 -P 8250 3550 -F 0 "X8" H 8250 3550 60 0000 C CNN -F 1 "Full-Adder" H 8250 3550 60 0000 C CNN -F 2 "" H 8250 3550 60 0000 C CNN -F 3 "" H 8250 3550 60 0000 C CNN - 1 8250 3550 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3500 3450 3650 3450 -Wire Wire Line - 3650 3450 3650 4800 -Wire Wire Line - 2500 3700 2500 3850 -Wire Wire Line - 2500 3850 4900 3850 -Wire Wire Line - 4900 3850 4900 3650 -Wire Wire Line - 4900 3650 4850 3650 -Wire Wire Line - 4850 3450 4950 3450 -Wire Wire Line - 4950 3450 4950 4800 -Wire Wire Line - 3850 3700 3850 3900 -Wire Wire Line - 3850 3900 6250 3900 -Wire Wire Line - 6250 3900 6250 3650 -Wire Wire Line - 6250 3650 6200 3650 -Wire Wire Line - 5200 3700 5200 3850 -Wire Wire Line - 5200 3850 7550 3850 -Wire Wire Line - 7550 3850 7550 3650 -Wire Wire Line - 7550 3650 7500 3650 -Wire Wire Line - 6500 3900 8750 3900 -Wire Wire Line - 8750 3900 8750 3650 -Wire Wire Line - 8750 3450 8800 3450 -Wire Wire Line - 8800 3450 8800 4950 -Wire Wire Line - 7500 3450 7600 3450 -Wire Wire Line - 7600 3450 7600 4850 -Wire Wire Line - 6200 3450 6300 3450 -Wire Wire Line - 6300 3450 6300 4800 -Wire Wire Line - 7750 3700 7750 3850 -Wire Wire Line - 7750 3850 8000 3850 -Wire Wire Line - 8000 3850 8000 4900 -Wire Wire Line - 2350 3400 2500 3400 -Wire Wire Line - 2350 2200 2350 3400 -Wire Wire Line - 2450 3550 2500 3550 -Wire Wire Line - 2450 2550 2450 3550 -Wire Wire Line - 3650 3400 3850 3400 -Wire Wire Line - 3650 2200 3650 3400 -Wire Wire Line - 7600 3400 7750 3400 -Wire Wire Line - 7600 2200 7600 3400 -Wire Wire Line - 6300 3400 6500 3400 -Wire Wire Line - 6300 2200 6300 3400 -Wire Wire Line - 6400 3550 6500 3550 -Wire Wire Line - 6400 2550 6400 3550 -Wire Wire Line - 4950 3400 5200 3400 -Wire Wire Line - 4950 2200 4950 3400 -Wire Wire Line - 5050 3550 5200 3550 -Wire Wire Line - 5050 2500 5050 3550 -Text Notes 7550 2750 1 60 ~ 0 -A0 -Text Notes 6200 2750 1 60 ~ 0 -A1 -Text Notes 4900 2750 1 60 ~ 0 -A2 -Text Notes 3600 2750 1 60 ~ 0 -A3 -Text Notes 2300 2750 1 60 ~ 0 -A4 -Text Notes 7800 2900 3 60 ~ 0 -B0 -Text Notes 6500 3050 1 60 ~ 0 -B1 -Text Notes 5150 3050 1 60 ~ 0 -B2 -Text Notes 3850 3050 1 60 ~ 0 -B3 -Text Notes 2550 3050 1 60 ~ 0 -B4 -Text Notes 8750 4700 1 60 ~ 0 -O0 -Text Notes 7550 4700 1 60 ~ 0 -O1 -Text Notes 6250 4650 1 60 ~ 0 -O2 -Text Notes 4900 4650 1 60 ~ 0 -O3 -Text Notes 3600 4650 1 60 ~ 0 -O4 -Wire Wire Line - 7700 2550 7700 3550 -Wire Wire Line - 7700 3550 7750 3550 -Wire Wire Line - 3850 3550 3750 3550 -Wire Wire Line - 3750 3550 3750 2550 -Wire Wire Line - 6500 3900 6500 3700 -$Comp -L PORT U1 -U 12 1 5C95CA38 -P 7600 1950 -F 0 "U1" H 7650 2050 30 0000 C CNN -F 1 "PORT" H 7600 1950 30 0000 C CNN -F 2 "" H 7600 1950 60 0000 C CNN -F 3 "" H 7600 1950 60 0000 C CNN - 12 7600 1950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 9 1 5C95CAA1 -P 6300 1950 -F 0 "U1" H 6350 2050 30 0000 C CNN -F 1 "PORT" H 6300 1950 30 0000 C CNN -F 2 "" H 6300 1950 60 0000 C CNN -F 3 "" H 6300 1950 60 0000 C CNN - 9 6300 1950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 6 1 5C95CAD4 -P 4950 1950 -F 0 "U1" H 5000 2050 30 0000 C CNN -F 1 "PORT" H 4950 1950 30 0000 C CNN -F 2 "" H 4950 1950 60 0000 C CNN -F 3 "" H 4950 1950 60 0000 C CNN - 6 4950 1950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 3 1 5C95CB01 -P 3650 1950 -F 0 "U1" H 3700 2050 30 0000 C CNN -F 1 "PORT" H 3650 1950 30 0000 C CNN -F 2 "" H 3650 1950 60 0000 C CNN -F 3 "" H 3650 1950 60 0000 C CNN - 3 3650 1950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 1 1 5C95CB34 -P 2350 1950 -F 0 "U1" H 2400 2050 30 0000 C CNN -F 1 "PORT" H 2350 1950 30 0000 C CNN -F 2 "" H 2350 1950 60 0000 C CNN -F 3 "" H 2350 1950 60 0000 C CNN - 1 2350 1950 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 14 1 5C95CB65 -P 7700 2300 -F 0 "U1" H 7750 2400 30 0000 C CNN -F 1 "PORT" H 7700 2300 30 0000 C CNN -F 2 "" H 7700 2300 60 0000 C CNN -F 3 "" H 7700 2300 60 0000 C CNN - 14 7700 2300 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 11 1 5C95CBEC -P 6400 2300 -F 0 "U1" H 6450 2400 30 0000 C CNN -F 1 "PORT" H 6400 2300 30 0000 C CNN -F 2 "" H 6400 2300 60 0000 C CNN -F 3 "" H 6400 2300 60 0000 C CNN - 11 6400 2300 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 8 1 5C95CC27 -P 5050 2250 -F 0 "U1" H 5100 2350 30 0000 C CNN -F 1 "PORT" H 5050 2250 30 0000 C CNN -F 2 "" H 5050 2250 60 0000 C CNN -F 3 "" H 5050 2250 60 0000 C CNN - 8 5050 2250 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 5 1 5C95CC5E -P 3750 2300 -F 0 "U1" H 3800 2400 30 0000 C CNN -F 1 "PORT" H 3750 2300 30 0000 C CNN -F 2 "" H 3750 2300 60 0000 C CNN -F 3 "" H 3750 2300 60 0000 C CNN - 5 3750 2300 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 2 1 5C95CC9F -P 2450 2300 -F 0 "U1" H 2500 2400 30 0000 C CNN -F 1 "PORT" H 2450 2300 30 0000 C CNN -F 2 "" H 2450 2300 60 0000 C CNN -F 3 "" H 2450 2300 60 0000 C CNN - 2 2450 2300 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 15 1 5C95D6FB -P 8000 5150 -F 0 "U1" H 8050 5250 30 0000 C CNN -F 1 "PORT" H 8000 5150 30 0000 C CNN -F 2 "" H 8000 5150 60 0000 C CNN -F 3 "" H 8000 5150 60 0000 C CNN - 15 8000 5150 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 16 1 5C95D772 -P 8800 5200 -F 0 "U1" H 8850 5300 30 0000 C CNN -F 1 "PORT" H 8800 5200 30 0000 C CNN -F 2 "" H 8800 5200 60 0000 C CNN -F 3 "" H 8800 5200 60 0000 C CNN - 16 8800 5200 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 13 1 5C95D7ED -P 7600 5100 -F 0 "U1" H 7650 5200 30 0000 C CNN -F 1 "PORT" H 7600 5100 30 0000 C CNN -F 2 "" H 7600 5100 60 0000 C CNN -F 3 "" H 7600 5100 60 0000 C CNN - 13 7600 5100 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 10 1 5C95D844 -P 6300 5050 -F 0 "U1" H 6350 5150 30 0000 C CNN -F 1 "PORT" H 6300 5050 30 0000 C CNN -F 2 "" H 6300 5050 60 0000 C CNN -F 3 "" H 6300 5050 60 0000 C CNN - 10 6300 5050 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 7 1 5C95D899 -P 4950 5050 -F 0 "U1" H 5000 5150 30 0000 C CNN -F 1 "PORT" H 4950 5050 30 0000 C CNN -F 2 "" H 4950 5050 60 0000 C CNN -F 3 "" H 4950 5050 60 0000 C CNN - 7 4950 5050 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 4 1 5C95D8EA -P 3650 5050 -F 0 "U1" H 3700 5150 30 0000 C CNN -F 1 "PORT" H 3650 5050 30 0000 C CNN -F 2 "" H 3650 5050 60 0000 C CNN -F 3 "" H 3650 5050 60 0000 C CNN - 4 3650 5050 - 0 -1 -1 0 -$EndComp -Text Notes 7950 4700 1 60 ~ 0 -Cin -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub deleted file mode 100644 index 675975d9..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 5bit-Ripple_carry_adder
-.subckt 5bit-Ripple_carry_adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_
-* c:\esim\esim\src\subcircuitlibrary\5bit-ripple_carry_adder\5bit-ripple_carry_adder.cir
-.include Full-Adder.sub
-x4 net-_u1-pad1_ net-_u1-pad2_ net-_x4-pad3_ net-_u1-pad4_ ? Full-Adder
-x5 net-_u1-pad3_ net-_u1-pad5_ net-_x5-pad3_ net-_u1-pad7_ net-_x4-pad3_ Full-Adder
-x6 net-_u1-pad6_ net-_u1-pad8_ net-_x6-pad3_ net-_u1-pad10_ net-_x5-pad3_ Full-Adder
-x7 net-_u1-pad9_ net-_u1-pad11_ net-_x7-pad3_ net-_u1-pad13_ net-_x6-pad3_ Full-Adder
-x8 net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x7-pad3_ Full-Adder
-* Control Statements
-
-.ends 5bit-Ripple_carry_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml deleted file mode 100644 index 8fbbb417..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/5bit-Ripple_carry_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x8><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x8><x6><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x6><x7><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x7><x4><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x4><x5><field>C:\esim\eSim\src\SubcircuitLibrary\Full-Adder</field></x5></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib deleted file mode 100644 index cba68b20..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder-cache.lib +++ /dev/null @@ -1,100 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir deleted file mode 100644 index ea7aed36..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir +++ /dev/null @@ -1,16 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\Full-Adder\Full-Adder.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/19 17:15:52
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_xor
-U5 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_xor
-U4 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and
-U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ d_and
-U6 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad5_ d_or
-
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out deleted file mode 100644 index 086d8b71..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.cir.out +++ /dev/null @@ -1,32 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.ac lin 0 0Hz 0Hz
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro deleted file mode 100644 index 7089d69d..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=03/21/19 17:06:42
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
-LibName12=half-adder
-LibName13=power
-LibName14=device
-LibName15=transistors
-LibName16=conn
-LibName17=linear
-LibName18=regul
-LibName19=74xx
-LibName20=cmos4000
-LibName21=adc-dac
-LibName22=memory
-LibName23=xilinx
-LibName24=microcontrollers
-LibName25=dsp
-LibName26=microchip
-LibName27=analog_switches
-LibName28=motorola
-LibName29=texas
-LibName30=intel
-LibName31=audio
-LibName32=interface
-LibName33=digital-audio
-LibName34=philips
-LibName35=display
-LibName36=cypress
-LibName37=siliconi
-LibName38=opto
-LibName39=atmel
-LibName40=contrib
-LibName41=valves
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch deleted file mode 100644 index 981e7cdb..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sch +++ /dev/null @@ -1,226 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:half-adder
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:Full-Adder-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L PORT U1
-U 1 1 5C93775D
-P 4100 2800
-F 0 "U1" H 4150 2900 30 0000 C CNN
-F 1 "PORT" H 4100 2800 30 0000 C CNN
-F 2 "" H 4100 2800 60 0000 C CNN
-F 3 "" H 4100 2800 60 0000 C CNN
- 1 4100 2800
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9377A8
-P 4100 3100
-F 0 "U1" H 4150 3200 30 0000 C CNN
-F 1 "PORT" H 4100 3100 30 0000 C CNN
-F 2 "" H 4100 3100 60 0000 C CNN
-F 3 "" H 4100 3100 60 0000 C CNN
- 2 4100 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9377CD
-P 4100 3400
-F 0 "U1" H 4150 3500 30 0000 C CNN
-F 1 "PORT" H 4100 3400 30 0000 C CNN
-F 2 "" H 4100 3400 60 0000 C CNN
-F 3 "" H 4100 3400 60 0000 C CNN
- 3 4100 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9377F2
-P 8450 2900
-F 0 "U1" H 8500 3000 30 0000 C CNN
-F 1 "PORT" H 8450 2900 30 0000 C CNN
-F 2 "" H 8450 2900 60 0000 C CNN
-F 3 "" H 8450 2900 60 0000 C CNN
- 4 8450 2900
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C937851
-P 8450 3200
-F 0 "U1" H 8500 3300 30 0000 C CNN
-F 1 "PORT" H 8450 3200 30 0000 C CNN
-F 2 "" H 8450 3200 60 0000 C CNN
-F 3 "" H 8450 3200 60 0000 C CNN
- 5 8450 3200
- -1 0 0 1
-$EndComp
-$Comp
-L d_xor U2
-U 1 1 5C93788C
-P 5150 2900
-F 0 "U2" H 5150 2900 60 0000 C CNN
-F 1 "d_xor" H 5200 3000 47 0000 C CNN
-F 2 "" H 5150 2900 60 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U5
-U 1 1 5C9378DF
-P 6400 2950
-F 0 "U5" H 6400 2950 60 0000 C CNN
-F 1 "d_xor" H 6450 3050 47 0000 C CNN
-F 2 "" H 6400 2950 60 0000 C CNN
-F 3 "" H 6400 2950 60 0000 C CNN
- 1 6400 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5C937928
-P 6150 3300
-F 0 "U4" H 6150 3300 60 0000 C CNN
-F 1 "d_and" H 6200 3400 60 0000 C CNN
-F 2 "" H 6150 3300 60 0000 C CNN
-F 3 "" H 6150 3300 60 0000 C CNN
- 1 6150 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9379CF
-P 5200 3500
-F 0 "U3" H 5200 3500 60 0000 C CNN
-F 1 "d_and" H 5250 3600 60 0000 C CNN
-F 2 "" H 5200 3500 60 0000 C CNN
-F 3 "" H 5200 3500 60 0000 C CNN
- 1 5200 3500
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5C937A14
-P 7250 3550
-F 0 "U6" H 7250 3550 60 0000 C CNN
-F 1 "d_or" H 7250 3650 60 0000 C CNN
-F 2 "" H 7250 3550 60 0000 C CNN
-F 3 "" H 7250 3550 60 0000 C CNN
- 1 7250 3550
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4350 2800 4700 2800
-Wire Wire Line
- 4350 3100 4700 3100
-Wire Wire Line
- 4700 3100 4700 2900
-Wire Wire Line
- 5600 2850 5950 2850
-Wire Wire Line
- 4350 3400 4400 3400
-Wire Wire Line
- 4400 3400 4400 3150
-Wire Wire Line
- 4400 3150 5450 3150
-Wire Wire Line
- 5450 3150 5450 2950
-Wire Wire Line
- 5450 2950 5950 2950
-Wire Wire Line
- 6850 2900 8200 2900
-Wire Wire Line
- 4450 2800 4450 3400
-Wire Wire Line
- 4450 3400 4750 3400
-Connection ~ 4450 2800
-Wire Wire Line
- 4600 3100 4600 3500
-Wire Wire Line
- 4600 3500 4750 3500
-Connection ~ 4600 3100
-Wire Wire Line
- 5650 3450 6800 3450
-Wire Wire Line
- 4400 3300 5700 3300
-Connection ~ 4400 3300
-Wire Wire Line
- 5700 3200 5700 2850
-Connection ~ 5700 2850
-Wire Wire Line
- 6600 3250 6650 3250
-Wire Wire Line
- 6650 3250 6650 3550
-Wire Wire Line
- 6650 3550 6800 3550
-Wire Wire Line
- 7700 3500 7700 3200
-Wire Wire Line
- 7700 3200 8200 3200
-Text Notes 4400 2750 0 60 ~ 0
-A
-Text Notes 4400 3050 0 60 ~ 0
-B
-Text Notes 4350 3500 0 60 ~ 0
-Cin
-Text Notes 7950 2850 0 60 ~ 0
-Sum
-Text Notes 7950 3150 0 60 ~ 0
-Cout
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub deleted file mode 100644 index 0ea4496d..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder.sub +++ /dev/null @@ -1,26 +0,0 @@ -* Subcircuit Full-Adder
-.subckt Full-Adder net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\esim\esim\src\subcircuitlibrary\full-adder\full-adder.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_xor
-* u5 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_xor
-* u4 net-_u2-pad3_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ d_and
-* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u5
-a3 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u3-pad3_ u3
-a5 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad5_ u6
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends Full-Adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml deleted file mode 100644 index c7136641..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/Full-Adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u5 name="type">d_xor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u5><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis b/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis deleted file mode 100644 index 52ccc5ec..00000000 --- a/src/SubcircuitLibrary/5bit-Ripple_carry_adder/analysis +++ /dev/null @@ -1 +0,0 @@ -.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and-cache.lib b/src/SubcircuitLibrary/74153/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/74153/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74153/3_and.cir b/src/SubcircuitLibrary/74153/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/74153/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/74153/3_and.cir.out b/src/SubcircuitLibrary/74153/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/74153/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/74153/3_and.pro b/src/SubcircuitLibrary/74153/3_and.pro deleted file mode 100644 index 2c9ac554..00000000 --- a/src/SubcircuitLibrary/74153/3_and.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74153/3_and.sch b/src/SubcircuitLibrary/74153/3_and.sch deleted file mode 100644 index 86be0215..00000000 --- a/src/SubcircuitLibrary/74153/3_and.sch +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/3_and.sub b/src/SubcircuitLibrary/74153/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/74153/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/74153/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR-cache.lib b/src/SubcircuitLibrary/74153/4_OR-cache.lib deleted file mode 100644 index 155f5e60..00000000 --- a/src/SubcircuitLibrary/74153/4_OR-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74153/4_OR.cir b/src/SubcircuitLibrary/74153/4_OR.cir deleted file mode 100644 index b338b7b5..00000000 --- a/src/SubcircuitLibrary/74153/4_OR.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or -U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or -U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT - -.end diff --git a/src/SubcircuitLibrary/74153/4_OR.cir.out b/src/SubcircuitLibrary/74153/4_OR.cir.out deleted file mode 100644 index adb6b01b..00000000 --- a/src/SubcircuitLibrary/74153/4_OR.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or -* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/74153/4_OR.pro b/src/SubcircuitLibrary/74153/4_OR.pro deleted file mode 100644 index 2c258cec..00000000 --- a/src/SubcircuitLibrary/74153/4_OR.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=03/28/19 22:43:48 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_PSpice -LibName10=eSim_Sources -LibName11=eSim_Subckt -LibName12=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_OR.sch b/src/SubcircuitLibrary/74153/4_OR.sch deleted file mode 100644 index 11896865..00000000 --- a/src/SubcircuitLibrary/74153/4_OR.sch +++ /dev/null @@ -1,150 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_or U2 -U 1 1 5C9D00E1 -P 4300 2950 -F 0 "U2" H 4300 2950 60 0000 C CNN -F 1 "d_or" H 4300 3050 60 0000 C CNN -F 2 "" H 4300 2950 60 0000 C CNN -F 3 "" H 4300 2950 60 0000 C CNN - 1 4300 2950 - 1 0 0 -1 -$EndComp -$Comp -L d_or U3 -U 1 1 5C9D011F -P 4300 3350 -F 0 "U3" H 4300 3350 60 0000 C CNN -F 1 "d_or" H 4300 3450 60 0000 C CNN -F 2 "" H 4300 3350 60 0000 C CNN -F 3 "" H 4300 3350 60 0000 C CNN - 1 4300 3350 - 1 0 0 -1 -$EndComp -$Comp -L d_or U4 -U 1 1 5C9D0141 -P 5250 3150 -F 0 "U4" H 5250 3150 60 0000 C CNN -F 1 "d_or" H 5250 3250 60 0000 C CNN -F 2 "" H 5250 3150 60 0000 C CNN -F 3 "" H 5250 3150 60 0000 C CNN - 1 5250 3150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4800 3050 4800 2900 -Wire Wire Line - 4800 2900 4750 2900 -Wire Wire Line - 4800 3150 4800 3300 -Wire Wire Line - 4800 3300 4750 3300 -Wire Wire Line - 3350 2850 3850 2850 -Wire Wire Line - 3850 2950 3600 2950 -Wire Wire Line - 3850 3250 3350 3250 -Wire Wire Line - 3600 2950 3600 3000 -Wire Wire Line - 3600 3000 3350 3000 -Wire Wire Line - 3850 3350 3850 3400 -Wire Wire Line - 3850 3400 3350 3400 -Wire Wire Line - 5700 3100 6200 3100 -$Comp -L PORT U1 -U 1 1 5C9D01F4 -P 3100 2850 -F 0 "U1" H 3150 2950 30 0000 C CNN -F 1 "PORT" H 3100 2850 30 0000 C CNN -F 2 "" H 3100 2850 60 0000 C CNN -F 3 "" H 3100 2850 60 0000 C CNN - 1 3100 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9D022F -P 3100 3000 -F 0 "U1" H 3150 3100 30 0000 C CNN -F 1 "PORT" H 3100 3000 30 0000 C CNN -F 2 "" H 3100 3000 60 0000 C CNN -F 3 "" H 3100 3000 60 0000 C CNN - 2 3100 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9D0271 -P 3100 3250 -F 0 "U1" H 3150 3350 30 0000 C CNN -F 1 "PORT" H 3100 3250 30 0000 C CNN -F 2 "" H 3100 3250 60 0000 C CNN -F 3 "" H 3100 3250 60 0000 C CNN - 3 3100 3250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9D0299 -P 3100 3400 -F 0 "U1" H 3150 3500 30 0000 C CNN -F 1 "PORT" H 3100 3400 30 0000 C CNN -F 2 "" H 3100 3400 60 0000 C CNN -F 3 "" H 3100 3400 60 0000 C CNN - 4 3100 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9D02C2 -P 6450 3100 -F 0 "U1" H 6500 3200 30 0000 C CNN -F 1 "PORT" H 6450 3100 30 0000 C CNN -F 2 "" H 6450 3100 60 0000 C CNN -F 3 "" H 6450 3100 60 0000 C CNN - 5 6450 3100 - -1 0 0 1 -$EndComp -Text Notes 3450 2850 0 60 ~ 12 -in1 -Text Notes 3450 3000 0 60 ~ 12 -in2 -Text Notes 3450 3250 0 60 ~ 12 -in3 -Text Notes 3450 3400 0 60 ~ 12 -in4 -Text Notes 5800 3100 0 60 ~ 12 -out -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_OR.sub b/src/SubcircuitLibrary/74153/4_OR.sub deleted file mode 100644 index d1fd3a24..00000000 --- a/src/SubcircuitLibrary/74153/4_OR.sub +++ /dev/null @@ -1,18 +0,0 @@ -* Subcircuit 4_OR -.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ -* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or -* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or -* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4_OR
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml deleted file mode 100644 index 23698d37..00000000 --- a/src/SubcircuitLibrary/74153/4_OR_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and-cache.lib b/src/SubcircuitLibrary/74153/4_and-cache.lib deleted file mode 100644 index ac396288..00000000 --- a/src/SubcircuitLibrary/74153/4_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74153/4_and-rescue.lib b/src/SubcircuitLibrary/74153/4_and-rescue.lib deleted file mode 100644 index 6b2c17f7..00000000 --- a/src/SubcircuitLibrary/74153/4_and-rescue.lib +++ /dev/null @@ -1,22 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/74153/4_and.cir b/src/SubcircuitLibrary/74153/4_and.cir deleted file mode 100644 index 50d490fa..00000000 --- a/src/SubcircuitLibrary/74153/4_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and -U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT - -.end diff --git a/src/SubcircuitLibrary/74153/4_and.cir.out b/src/SubcircuitLibrary/74153/4_and.cir.out deleted file mode 100644 index f40e5bc6..00000000 --- a/src/SubcircuitLibrary/74153/4_and.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port -a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/74153/4_and.pro b/src/SubcircuitLibrary/74153/4_and.pro deleted file mode 100644 index 6eb77fff..00000000 --- a/src/SubcircuitLibrary/74153/4_and.pro +++ /dev/null @@ -1,57 +0,0 @@ -update=03/26/19 18:58:33 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=texas -LibName2=intel -LibName3=audio -LibName4=interface -LibName5=digital-audio -LibName6=philips -LibName7=display -LibName8=cypress -LibName9=siliconi -LibName10=opto -LibName11=atmel -LibName12=contrib -LibName13=valves -LibName14=eSim_Analog -LibName15=eSim_Devices -LibName16=eSim_Digital -LibName17=eSim_Hybrid -LibName18=eSim_Miscellaneous -LibName19=eSim_Plot -LibName20=eSim_Power -LibName21=eSim_PSpice -LibName22=eSim_Sources -LibName23=eSim_Subckt -LibName24=eSim_User diff --git a/src/SubcircuitLibrary/74153/4_and.sch b/src/SubcircuitLibrary/74153/4_and.sch deleted file mode 100644 index 883458e1..00000000 --- a/src/SubcircuitLibrary/74153/4_and.sch +++ /dev/null @@ -1,139 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5C9A2915 -P 3700 3500 -F 0 "X1" H 4600 3800 60 0000 C CNN -F 1 "3_and" H 4650 4000 60 0000 C CNN -F 2 "" H 3700 3500 60 0000 C CNN -F 3 "" H 3700 3500 60 0000 C CNN - 1 3700 3500 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C9A2940 -P 5450 3400 -F 0 "U2" H 5450 3400 60 0000 C CNN -F 1 "d_and" H 5500 3500 60 0000 C CNN -F 2 "" H 5450 3400 60 0000 C CNN -F 3 "" H 5450 3400 60 0000 C CNN - 1 5450 3400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5000 3100 5000 3300 -Wire Wire Line - 4150 3000 4150 2700 -Wire Wire Line - 4150 2700 3200 2700 -Wire Wire Line - 4150 3100 4000 3100 -Wire Wire Line - 4000 3100 4000 3000 -Wire Wire Line - 4000 3000 3200 3000 -Wire Wire Line - 4150 3200 4150 3300 -Wire Wire Line - 4150 3300 3250 3300 -Wire Wire Line - 5000 3400 5000 3550 -Wire Wire Line - 5000 3550 3250 3550 -Wire Wire Line - 5900 3350 6500 3350 -$Comp -L PORT U1 -U 1 1 5C9A29B1 -P 2950 2700 -F 0 "U1" H 3000 2800 30 0000 C CNN -F 1 "PORT" H 2950 2700 30 0000 C CNN -F 2 "" H 2950 2700 60 0000 C CNN -F 3 "" H 2950 2700 60 0000 C CNN - 1 2950 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A29E9 -P 2950 3000 -F 0 "U1" H 3000 3100 30 0000 C CNN -F 1 "PORT" H 2950 3000 30 0000 C CNN -F 2 "" H 2950 3000 60 0000 C CNN -F 3 "" H 2950 3000 60 0000 C CNN - 2 2950 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A2A0D -P 3000 3300 -F 0 "U1" H 3050 3400 30 0000 C CNN -F 1 "PORT" H 3000 3300 30 0000 C CNN -F 2 "" H 3000 3300 60 0000 C CNN -F 3 "" H 3000 3300 60 0000 C CNN - 3 3000 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2A3C -P 3000 3550 -F 0 "U1" H 3050 3650 30 0000 C CNN -F 1 "PORT" H 3000 3550 30 0000 C CNN -F 2 "" H 3000 3550 60 0000 C CNN -F 3 "" H 3000 3550 60 0000 C CNN - 4 3000 3550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A2A68 -P 6750 3350 -F 0 "U1" H 6800 3450 30 0000 C CNN -F 1 "PORT" H 6750 3350 30 0000 C CNN -F 2 "" H 6750 3350 60 0000 C CNN -F 3 "" H 6750 3350 60 0000 C CNN - 5 6750 3350 - -1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/4_and.sub b/src/SubcircuitLibrary/74153/4_and.sub deleted file mode 100644 index 8663f37e..00000000 --- a/src/SubcircuitLibrary/74153/4_and.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 4_and -.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and -a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml b/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml deleted file mode 100644 index f2ba0130..00000000 --- a/src/SubcircuitLibrary/74153/4_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153-cache.lib b/src/SubcircuitLibrary/74153/74153-cache.lib deleted file mode 100644 index 1e85854e..00000000 --- a/src/SubcircuitLibrary/74153/74153-cache.lib +++ /dev/null @@ -1,98 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 4_OR -# -DEF 4_OR X 0 40 Y Y 1 F N -F0 "X" 3900 3050 60 H V C CNN -F1 "4_OR" 3900 3250 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 2950 3150 650 226 -226 0 1 0 N 3550 3400 3550 2900 -A 3677 3284 444 -599 -176 0 1 0 N 3900 2900 4100 3150 -A 3720 3051 393 627 146 0 1 0 N 3900 3400 4100 3150 -P 2 0 1 0 3550 2900 3900 2900 N -P 2 0 1 0 3550 3400 3900 3400 N -X in1 1 3400 3300 200 R 50 50 1 1 I -X in2 2 3400 3200 200 R 50 50 1 1 I -X in3 3 3400 3100 200 R 50 50 1 1 I -X in4 4 3400 3000 200 R 50 50 1 1 I -X out 5 4300 3150 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_and -# -DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 1500 1050 60 H V C CNN -F1 "4_and" 1550 1200 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 -P 2 0 1 0 1250 1300 1600 1300 N -P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N -X in1 1 1050 1250 200 R 50 50 1 1 I -X in2 2 1050 1150 200 R 50 50 1 1 I -X in3 3 1050 1050 200 R 50 50 1 1 I -X in4 4 1050 950 200 R 50 50 1 1 I -X out 5 1950 1100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74153/74153.cir b/src/SubcircuitLibrary/74153/74153.cir deleted file mode 100644 index b20e6858..00000000 --- a/src/SubcircuitLibrary/74153/74153.cir +++ /dev/null @@ -1,25 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\74153.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 23:33:11 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad12_ Net-_U2-Pad2_ d_inverter -U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT -U35 Net-_U1-Pad5_ Net-_U35-Pad2_ d_inverter -U34 Net-_U1-Pad10_ Net-_U34-Pad2_ d_inverter -X8 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad1_ Net-_U35-Pad2_ Net-_X2-Pad1_ 4_and -X9 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad2_ 4_and -X4 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U35-Pad2_ Net-_X2-Pad3_ 4_and -X10 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad4_ Net-_U35-Pad2_ Net-_X10-Pad5_ 4_and -X5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad6_ Net-_U34-Pad2_ Net-_X1-Pad1_ 4_and -X6 Net-_U1-Pad12_ Net-_U3-Pad2_ Net-_U1-Pad7_ Net-_U34-Pad2_ Net-_X1-Pad2_ 4_and -X3 Net-_U2-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U34-Pad2_ Net-_X1-Pad3_ 4_and -X7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad9_ Net-_U34-Pad2_ Net-_X1-Pad4_ 4_and -X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_U1-Pad14_ 4_OR -X2 Net-_X2-Pad1_ Net-_X2-Pad2_ Net-_X2-Pad3_ Net-_X10-Pad5_ Net-_U1-Pad13_ 4_OR - -.end diff --git a/src/SubcircuitLibrary/74153/74153.cir.out b/src/SubcircuitLibrary/74153/74153.cir.out deleted file mode 100644 index c95e5ad9..00000000 --- a/src/SubcircuitLibrary/74153/74153.cir.out +++ /dev/null @@ -1,40 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir - -.include 4_and.sub -.include 4_OR.sub -* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port -* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter -* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter -x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and -x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and -x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and -x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and -x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and -x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and -x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and -x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR -x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR -a1 net-_u1-pad12_ net-_u2-pad2_ u2 -a2 net-_u1-pad11_ net-_u3-pad2_ u3 -a3 net-_u1-pad5_ net-_u35-pad2_ u35 -a4 net-_u1-pad10_ net-_u34-pad2_ u34 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/74153/74153.pro b/src/SubcircuitLibrary/74153/74153.pro deleted file mode 100644 index ed8b8bf2..00000000 --- a/src/SubcircuitLibrary/74153/74153.pro +++ /dev/null @@ -1,59 +0,0 @@ -update=03/28/19 23:27:36 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=texas -LibName4=intel -LibName5=audio -LibName6=interface -LibName7=digital-audio -LibName8=philips -LibName9=display -LibName10=cypress -LibName11=siliconi -LibName12=opto -LibName13=atmel -LibName14=contrib -LibName15=valves -LibName16=eSim_Analog -LibName17=eSim_Devices -LibName18=eSim_Digital -LibName19=eSim_Hybrid -LibName20=eSim_Miscellaneous -LibName21=eSim_Plot -LibName22=eSim_Power -LibName23=eSim_PSpice -LibName24=eSim_Sources -LibName25=eSim_User -LibName26=eSim_Subckt diff --git a/src/SubcircuitLibrary/74153/74153.sch b/src/SubcircuitLibrary/74153/74153.sch deleted file mode 100644 index e0bcf950..00000000 --- a/src/SubcircuitLibrary/74153/74153.sch +++ /dev/null @@ -1,568 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:74153-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_inverter U2 -U 1 1 5C9378F6 -P 2650 1350 -F 0 "U2" H 2650 1250 60 0000 C CNN -F 1 "d_inverter" H 2650 1500 60 0000 C CNN -F 2 "" H 2700 1300 60 0000 C CNN -F 3 "" H 2700 1300 60 0000 C CNN - 1 2650 1350 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5C93798D -P 2700 950 -F 0 "U3" H 2700 850 60 0000 C CNN -F 1 "d_inverter" H 2700 1100 60 0000 C CNN -F 2 "" H 2750 900 60 0000 C CNN -F 3 "" H 2750 900 60 0000 C CNN - 1 2700 950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C93A0F9 -P 1350 2050 -F 0 "U1" H 1400 2150 30 0000 C CNN -F 1 "PORT" H 1350 2050 30 0000 C CNN -F 2 "" H 1350 2050 60 0000 C CNN -F 3 "" H 1350 2050 60 0000 C CNN - 1 1350 2050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C93A174 -P 1350 4700 -F 0 "U1" H 1400 4800 30 0000 C CNN -F 1 "PORT" H 1350 4700 30 0000 C CNN -F 2 "" H 1350 4700 60 0000 C CNN -F 3 "" H 1350 4700 60 0000 C CNN - 6 1350 4700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C93AA3C -P 1350 2600 -F 0 "U1" H 1400 2700 30 0000 C CNN -F 1 "PORT" H 1350 2600 30 0000 C CNN -F 2 "" H 1350 2600 60 0000 C CNN -F 3 "" H 1350 2600 60 0000 C CNN - 2 1350 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C93AACB -P 1350 3200 -F 0 "U1" H 1400 3300 30 0000 C CNN -F 1 "PORT" H 1350 3200 30 0000 C CNN -F 2 "" H 1350 3200 60 0000 C CNN -F 3 "" H 1350 3200 60 0000 C CNN - 3 1350 3200 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C93AB5F -P 1350 3700 -F 0 "U1" H 1400 3800 30 0000 C CNN -F 1 "PORT" H 1350 3700 30 0000 C CNN -F 2 "" H 1350 3700 60 0000 C CNN -F 3 "" H 1350 3700 60 0000 C CNN - 4 1350 3700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5C93AD97 -P 1350 5250 -F 0 "U1" H 1400 5350 30 0000 C CNN -F 1 "PORT" H 1350 5250 30 0000 C CNN -F 2 "" H 1350 5250 60 0000 C CNN -F 3 "" H 1350 5250 60 0000 C CNN - 7 1350 5250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5C93ADFC -P 1350 5850 -F 0 "U1" H 1400 5950 30 0000 C CNN -F 1 "PORT" H 1350 5850 30 0000 C CNN -F 2 "" H 1350 5850 60 0000 C CNN -F 3 "" H 1350 5850 60 0000 C CNN - 8 1350 5850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C93AE63 -P 1350 6350 -F 0 "U1" H 1400 6450 30 0000 C CNN -F 1 "PORT" H 1350 6350 30 0000 C CNN -F 2 "" H 1350 6350 60 0000 C CNN -F 3 "" H 1350 6350 60 0000 C CNN - 9 1350 6350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C93AECA -P 1350 3950 -F 0 "U1" H 1400 4050 30 0000 C CNN -F 1 "PORT" H 1350 3950 30 0000 C CNN -F 2 "" H 1350 3950 60 0000 C CNN -F 3 "" H 1350 3950 60 0000 C CNN - 5 1350 3950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C93AF79 -P 1350 6600 -F 0 "U1" H 1400 6700 30 0000 C CNN -F 1 "PORT" H 1350 6600 30 0000 C CNN -F 2 "" H 1350 6600 60 0000 C CNN -F 3 "" H 1350 6600 60 0000 C CNN - 10 1350 6600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C93B10A -P 1550 950 -F 0 "U1" H 1600 1050 30 0000 C CNN -F 1 "PORT" H 1550 950 30 0000 C CNN -F 2 "" H 1550 950 60 0000 C CNN -F 3 "" H 1550 950 60 0000 C CNN - 11 1550 950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5C93B179 -P 1550 1350 -F 0 "U1" H 1600 1450 30 0000 C CNN -F 1 "PORT" H 1550 1350 30 0000 C CNN -F 2 "" H 1550 1350 60 0000 C CNN -F 3 "" H 1550 1350 60 0000 C CNN - 12 1550 1350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5C93B567 -P 7850 2600 -F 0 "U1" H 7900 2700 30 0000 C CNN -F 1 "PORT" H 7850 2600 30 0000 C CNN -F 2 "" H 7850 2600 60 0000 C CNN -F 3 "" H 7850 2600 60 0000 C CNN - 13 7850 2600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5C93B5DA -P 7900 5250 -F 0 "U1" H 7950 5350 30 0000 C CNN -F 1 "PORT" H 7900 5250 30 0000 C CNN -F 2 "" H 7900 5250 60 0000 C CNN -F 3 "" H 7900 5250 60 0000 C CNN - 14 7900 5250 - -1 0 0 1 -$EndComp -$Comp -L d_inverter U35 -U 1 1 5C95CBCC -P 2700 3950 -F 0 "U35" H 2700 3850 60 0000 C CNN -F 1 "d_inverter" H 2700 4100 60 0000 C CNN -F 2 "" H 2750 3900 60 0000 C CNN -F 3 "" H 2750 3900 60 0000 C CNN - 1 2700 3950 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U34 -U 1 1 5C95CC99 -P 2650 6600 -F 0 "U34" H 2650 6500 60 0000 C CNN -F 1 "d_inverter" H 2650 6750 60 0000 C CNN -F 2 "" H 2700 6550 60 0000 C CNN -F 3 "" H 2700 6550 60 0000 C CNN - 1 2650 6600 - 1 0 0 -1 -$EndComp -Text Notes 1750 2050 0 60 ~ 12 -A0 -Text Notes 1800 2600 0 60 ~ 12 -A1 -Text Notes 1800 3200 0 60 ~ 12 -A2 -Text Notes 1750 3700 0 60 ~ 12 -A3\n -Text Notes 1750 3950 0 60 ~ 12 -EnA\n -Text Notes 1800 4700 0 60 ~ 12 -B0\n -Text Notes 1800 5250 0 60 ~ 12 -B1 -Text Notes 1800 5850 0 60 ~ 12 -B2 -Text Notes 1750 6350 0 60 ~ 12 -B3 -Text Notes 1800 6600 0 60 ~ 12 -EnB -Text Notes 2000 950 0 60 ~ 12 -S1\n -Text Notes 2000 1350 0 60 ~ 12 -S0 -Text Notes 7350 2600 0 60 ~ 12 -YA -Text Notes 7400 5250 0 60 ~ 12 -YB -$Comp -L 4_and X8 -U 1 1 5C9D0C22 -P 2750 3050 -F 0 "X8" H 4250 4100 60 0000 C CNN -F 1 "4_and" H 4300 4250 60 0000 C CNN -F 2 "" H 2750 3050 60 0000 C CNN -F 3 "" H 2750 3050 60 0000 C CNN - 1 2750 3050 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X9 -U 1 1 5C9D0CA2 -P 2750 3600 -F 0 "X9" H 4250 4650 60 0000 C CNN -F 1 "4_and" H 4300 4800 60 0000 C CNN -F 2 "" H 2750 3600 60 0000 C CNN -F 3 "" H 2750 3600 60 0000 C CNN - 1 2750 3600 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X4 -U 1 1 5C9D0D16 -P 2700 4200 -F 0 "X4" H 4200 5250 60 0000 C CNN -F 1 "4_and" H 4250 5400 60 0000 C CNN -F 2 "" H 2700 4200 60 0000 C CNN -F 3 "" H 2700 4200 60 0000 C CNN - 1 2700 4200 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X10 -U 1 1 5C9D0D93 -P 2750 4700 -F 0 "X10" H 4250 5750 60 0000 C CNN -F 1 "4_and" H 4300 5900 60 0000 C CNN -F 2 "" H 2750 4700 60 0000 C CNN -F 3 "" H 2750 4700 60 0000 C CNN - 1 2750 4700 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X5 -U 1 1 5C9D182A -P 2700 5700 -F 0 "X5" H 4200 6750 60 0000 C CNN -F 1 "4_and" H 4250 6900 60 0000 C CNN -F 2 "" H 2700 5700 60 0000 C CNN -F 3 "" H 2700 5700 60 0000 C CNN - 1 2700 5700 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X6 -U 1 1 5C9D1830 -P 2700 6250 -F 0 "X6" H 4200 7300 60 0000 C CNN -F 1 "4_and" H 4250 7450 60 0000 C CNN -F 2 "" H 2700 6250 60 0000 C CNN -F 3 "" H 2700 6250 60 0000 C CNN - 1 2700 6250 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X3 -U 1 1 5C9D1836 -P 2650 6850 -F 0 "X3" H 4150 7900 60 0000 C CNN -F 1 "4_and" H 4200 8050 60 0000 C CNN -F 2 "" H 2650 6850 60 0000 C CNN -F 3 "" H 2650 6850 60 0000 C CNN - 1 2650 6850 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X7 -U 1 1 5C9D183C -P 2700 7350 -F 0 "X7" H 4200 8400 60 0000 C CNN -F 1 "4_and" H 4250 8550 60 0000 C CNN -F 2 "" H 2700 7350 60 0000 C CNN -F 3 "" H 2700 7350 60 0000 C CNN - 1 2700 7350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3100 1800 3800 1800 -Wire Wire Line - 3100 1350 3100 5600 -Wire Wire Line - 3200 1900 3800 1900 -Wire Wire Line - 3200 950 3200 5100 -Wire Wire Line - 2950 1350 3100 1350 -Connection ~ 3100 1800 -Wire Wire Line - 3000 950 3200 950 -Connection ~ 3200 1900 -Wire Wire Line - 1800 950 2400 950 -Wire Wire Line - 1800 1350 2350 1350 -Wire Wire Line - 2200 950 2200 6200 -Connection ~ 2200 950 -Wire Wire Line - 2300 1350 2300 6100 -Wire Wire Line - 3300 2100 3800 2100 -Wire Wire Line - 3300 2100 3300 3800 -Wire Wire Line - 3300 2700 3800 2700 -Wire Wire Line - 3300 3300 3750 3300 -Connection ~ 3300 2700 -Wire Wire Line - 3000 3800 3800 3800 -Connection ~ 3300 3300 -Wire Wire Line - 1600 3700 3800 3700 -Wire Wire Line - 1600 3200 3750 3200 -Wire Wire Line - 3400 2600 1600 2600 -Wire Wire Line - 1600 2050 3800 2050 -Wire Wire Line - 3000 3800 3000 3950 -Wire Wire Line - 1600 3950 2400 3950 -Connection ~ 3300 3800 -Wire Wire Line - 3100 4450 3750 4450 -Wire Wire Line - 3200 4550 3750 4550 -Wire Wire Line - 3300 4800 3750 4800 -Wire Wire Line - 3300 4800 3300 6450 -Wire Wire Line - 3300 5350 3750 5350 -Wire Wire Line - 3300 5950 3700 5950 -Connection ~ 3300 5350 -Wire Wire Line - 3200 6450 3750 6450 -Connection ~ 3300 5950 -Wire Wire Line - 3350 6350 1600 6350 -Wire Wire Line - 1600 5850 3700 5850 -Wire Wire Line - 1600 5250 3750 5250 -Wire Wire Line - 3350 4700 1600 4700 -Wire Wire Line - 3200 6600 3200 6450 -Wire Wire Line - 2950 6600 3200 6600 -Wire Wire Line - 1600 6600 2350 6600 -Connection ~ 3300 6450 -Connection ~ 2300 1350 -Connection ~ 3100 4450 -Connection ~ 3200 4550 -Wire Wire Line - 6550 2600 7600 2600 -Wire Wire Line - 6450 5250 7650 5250 -Connection ~ 2200 3450 -Wire Wire Line - 3200 5100 3750 5100 -Wire Wire Line - 2300 5000 3750 5000 -Connection ~ 2300 5000 -Wire Wire Line - 3100 5600 3700 5600 -Wire Wire Line - 2200 5700 3700 5700 -Wire Wire Line - 2200 6200 3750 6200 -Connection ~ 2200 5700 -Wire Wire Line - 2300 6100 3750 6100 -Wire Wire Line - 3200 2450 3800 2450 -Connection ~ 3200 2450 -Wire Wire Line - 2300 2350 3800 2350 -Connection ~ 2300 2350 -Wire Wire Line - 2200 3050 3750 3050 -Connection ~ 2200 3050 -Wire Wire Line - 3100 2950 3750 2950 -Connection ~ 3100 2950 -Wire Wire Line - 2300 3450 3800 3450 -Wire Wire Line - 2300 3450 2300 3400 -Connection ~ 2300 3400 -Wire Wire Line - 2200 3550 3800 3550 -Connection ~ 2200 3550 -Wire Wire Line - 3800 2050 3800 2000 -Wire Wire Line - 3400 2600 3400 2550 -Wire Wire Line - 3400 2550 3800 2550 -Wire Wire Line - 3800 2700 3800 2650 -Wire Wire Line - 3750 3200 3750 3150 -Wire Wire Line - 3750 3300 3750 3250 -Wire Wire Line - 3800 3700 3800 3650 -Wire Wire Line - 3800 3800 3800 3750 -Wire Wire Line - 3350 4700 3350 4650 -Wire Wire Line - 3350 4650 3750 4650 -Wire Wire Line - 3750 4800 3750 4750 -Wire Wire Line - 3750 5250 3750 5200 -Wire Wire Line - 3750 5350 3750 5300 -Wire Wire Line - 3700 5850 3700 5800 -Wire Wire Line - 3700 5950 3700 5900 -Wire Wire Line - 3350 6350 3350 6300 -Wire Wire Line - 3350 6300 3750 6300 -Wire Wire Line - 3750 6450 3750 6400 -$Comp -L 4_OR X1 -U 1 1 5C9D22F7 -P 2150 8400 -F 0 "X1" H 6050 11450 60 0000 C CNN -F 1 "4_OR" H 6050 11650 60 0000 C CNN -F 2 "" H 2150 8400 60 0000 C CNN -F 3 "" H 2150 8400 60 0000 C CNN - 1 2150 8400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5550 5100 5550 4600 -Wire Wire Line - 5550 4600 4650 4600 -Wire Wire Line - 5550 5200 4650 5200 -Wire Wire Line - 4650 5200 4650 5150 -Wire Wire Line - 4600 5750 4600 5300 -Wire Wire Line - 4600 5300 5550 5300 -Wire Wire Line - 4650 6250 4650 5400 -Wire Wire Line - 4650 5400 5550 5400 -$Comp -L 4_OR X2 -U 1 1 5C9D28DE -P 2250 5750 -F 0 "X2" H 6150 8800 60 0000 C CNN -F 1 "4_OR" H 6150 9000 60 0000 C CNN -F 2 "" H 2250 5750 60 0000 C CNN -F 3 "" H 2250 5750 60 0000 C CNN - 1 2250 5750 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4700 1950 5650 1950 -Wire Wire Line - 5650 1950 5650 2450 -Wire Wire Line - 5650 2550 4700 2550 -Wire Wire Line - 4700 2550 4700 2500 -Wire Wire Line - 4650 3100 4650 2650 -Wire Wire Line - 4650 2650 5650 2650 -Wire Wire Line - 4700 3600 4700 2750 -Wire Wire Line - 4700 2750 5650 2750 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/74153.sub b/src/SubcircuitLibrary/74153/74153.sub deleted file mode 100644 index 6e00261f..00000000 --- a/src/SubcircuitLibrary/74153/74153.sub +++ /dev/null @@ -1,34 +0,0 @@ -* Subcircuit 74153 -.subckt 74153 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ -* c:\users\malli\esim\src\subcircuitlibrary\74153\74153.cir -.include 4_and.sub -.include 4_OR.sub -* u2 net-_u1-pad12_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter -* u35 net-_u1-pad5_ net-_u35-pad2_ d_inverter -* u34 net-_u1-pad10_ net-_u34-pad2_ d_inverter -x8 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad1_ net-_u35-pad2_ net-_x2-pad1_ 4_and -x9 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad2_ net-_u35-pad2_ net-_x2-pad2_ 4_and -x4 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad3_ net-_u35-pad2_ net-_x2-pad3_ 4_and -x10 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad4_ net-_u35-pad2_ net-_x10-pad5_ 4_and -x5 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_u34-pad2_ net-_x1-pad1_ 4_and -x6 net-_u1-pad12_ net-_u3-pad2_ net-_u1-pad7_ net-_u34-pad2_ net-_x1-pad2_ 4_and -x3 net-_u2-pad2_ net-_u1-pad11_ net-_u1-pad8_ net-_u34-pad2_ net-_x1-pad3_ 4_and -x7 net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad9_ net-_u34-pad2_ net-_x1-pad4_ 4_and -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_u1-pad14_ 4_OR -x2 net-_x2-pad1_ net-_x2-pad2_ net-_x2-pad3_ net-_x10-pad5_ net-_u1-pad13_ 4_OR -a1 net-_u1-pad12_ net-_u2-pad2_ u2 -a2 net-_u1-pad11_ net-_u3-pad2_ u3 -a3 net-_u1-pad5_ net-_u35-pad2_ u35 -a4 net-_u1-pad10_ net-_u34-pad2_ u34 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u34 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 74153
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml b/src/SubcircuitLibrary/74153/74153_Previous_Values.xml deleted file mode 100644 index ea70e6f3..00000000 --- a/src/SubcircuitLibrary/74153/74153_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u14 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u14><u25 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u25><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u20 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u20><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u21 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u21><u18 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u24 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u24><u28 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u29 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u29><u32 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u32><u2 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u15 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u15><u6 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u6><u8 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u4><u16 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16><u27 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u27><u10 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u10><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u12 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u12><u23 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u23><u19 name="type">d_and<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u19><u26 name="type">d_and<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u26><u30 name="type">d_or<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u30><u31 name="type">d_or<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u17 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u17><u11 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u11><u13 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u13><u9 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x9><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x10><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib b/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib deleted file mode 100644 index 10496d63..00000000 --- a/src/SubcircuitLibrary/74153/Dual4to1MUX-cache.lib +++ /dev/null @@ -1,94 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir b/src/SubcircuitLibrary/74153/Dual4to1MUX.cir deleted file mode 100644 index 583c4a00..00000000 --- a/src/SubcircuitLibrary/74153/Dual4to1MUX.cir +++ /dev/null @@ -1,45 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\74153\Dual4to1MUX.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/23/19 11:18:42 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U14 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and -U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_and -U5 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U20-Pad1_ d_and -U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and -U7 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U21-Pad1_ d_and -U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and -U18 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U18-Pad3_ d_and -U24 Net-_U18-Pad3_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and -U28 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U28-Pad3_ d_or -U29 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U29-Pad3_ d_or -U32 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U1-Pad13_ d_or -U2 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter -U3 Net-_U1-Pad11_ Net-_U14-Pad2_ d_inverter -U15 Net-_U1-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and -U6 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U20-Pad2_ d_and -U8 Net-_U1-Pad4_ Net-_U15-Pad2_ Net-_U21-Pad2_ d_and -U4 Net-_U1-Pad1_ Net-_U15-Pad2_ Net-_U24-Pad2_ d_and -U16 Net-_U1-Pad12_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and -U27 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and -U10 Net-_U10-Pad1_ Net-_U1-Pad11_ Net-_U10-Pad3_ d_and -U22 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_and -U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_and -U23 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_and -U19 Net-_U10-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and -U26 Net-_U19-Pad3_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and -U30 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U30-Pad3_ d_or -U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_or -U33 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U1-Pad14_ d_or -U17 Net-_U1-Pad7_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and -U11 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and -U13 Net-_U1-Pad9_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and -U9 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U26-Pad2_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT -U34 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter -U35 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter - -.end diff --git a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch b/src/SubcircuitLibrary/74153/Dual4to1MUX.sch deleted file mode 100644 index 340b1a31..00000000 --- a/src/SubcircuitLibrary/74153/Dual4to1MUX.sch +++ /dev/null @@ -1,814 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:74153-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U14 -U 1 1 5C936BFE -P 3850 2450 -F 0 "U14" H 3850 2450 60 0000 C CNN -F 1 "d_and" H 3900 2550 60 0000 C CNN -F 2 "" H 3850 2450 60 0000 C CNN -F 3 "" H 3850 2450 60 0000 C CNN - 1 3850 2450 - 1 0 0 -1 -$EndComp -$Comp -L d_and U25 -U 1 1 5C936C8A -P 4850 2600 -F 0 "U25" H 4850 2600 60 0000 C CNN -F 1 "d_and" H 4900 2700 60 0000 C CNN -F 2 "" H 4850 2600 60 0000 C CNN -F 3 "" H 4850 2600 60 0000 C CNN - 1 4850 2600 - 1 0 0 -1 -$EndComp -$Comp -L d_and U5 -U 1 1 5C936E84 -P 3800 3050 -F 0 "U5" H 3800 3050 60 0000 C CNN -F 1 "d_and" H 3850 3150 60 0000 C CNN -F 2 "" H 3800 3050 60 0000 C CNN -F 3 "" H 3800 3050 60 0000 C CNN - 1 3800 3050 - 1 0 0 -1 -$EndComp -$Comp -L d_and U20 -U 1 1 5C936E8A -P 4800 3200 -F 0 "U20" H 4800 3200 60 0000 C CNN -F 1 "d_and" H 4850 3300 60 0000 C CNN -F 2 "" H 4800 3200 60 0000 C CNN -F 3 "" H 4800 3200 60 0000 C CNN - 1 4800 3200 - 1 0 0 -1 -$EndComp -$Comp -L d_and U7 -U 1 1 5C936EF6 -P 3800 3550 -F 0 "U7" H 3800 3550 60 0000 C CNN -F 1 "d_and" H 3850 3650 60 0000 C CNN -F 2 "" H 3800 3550 60 0000 C CNN -F 3 "" H 3800 3550 60 0000 C CNN - 1 3800 3550 - 1 0 0 -1 -$EndComp -$Comp -L d_and U21 -U 1 1 5C936EFC -P 4800 3700 -F 0 "U21" H 4800 3700 60 0000 C CNN -F 1 "d_and" H 4850 3800 60 0000 C CNN -F 2 "" H 4800 3700 60 0000 C CNN -F 3 "" H 4800 3700 60 0000 C CNN - 1 4800 3700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U18 -U 1 1 5C936F88 -P 3950 1900 -F 0 "U18" H 3950 1900 60 0000 C CNN -F 1 "d_and" H 4000 2000 60 0000 C CNN -F 2 "" H 3950 1900 60 0000 C CNN -F 3 "" H 3950 1900 60 0000 C CNN - 1 3950 1900 - 1 0 0 -1 -$EndComp -$Comp -L d_and U24 -U 1 1 5C936F8E -P 4850 2150 -F 0 "U24" H 4850 2150 60 0000 C CNN -F 1 "d_and" H 4900 2250 60 0000 C CNN -F 2 "" H 4850 2150 60 0000 C CNN -F 3 "" H 4850 2150 60 0000 C CNN - 1 4850 2150 - 1 0 0 -1 -$EndComp -$Comp -L d_or U28 -U 1 1 5C937316 -P 5900 2550 -F 0 "U28" H 5900 2550 60 0000 C CNN -F 1 "d_or" H 5900 2650 60 0000 C CNN -F 2 "" H 5900 2550 60 0000 C CNN -F 3 "" H 5900 2550 60 0000 C CNN - 1 5900 2550 - 1 0 0 -1 -$EndComp -$Comp -L d_or U29 -U 1 1 5C9373A8 -P 5900 2800 -F 0 "U29" H 5900 2800 60 0000 C CNN -F 1 "d_or" H 5900 2900 60 0000 C CNN -F 2 "" H 5900 2800 60 0000 C CNN -F 3 "" H 5900 2800 60 0000 C CNN - 1 5900 2800 - 1 0 0 -1 -$EndComp -$Comp -L d_or U32 -U 1 1 5C9373FC -P 6850 2650 -F 0 "U32" H 6850 2650 60 0000 C CNN -F 1 "d_or" H 6850 2750 60 0000 C CNN -F 2 "" H 6850 2650 60 0000 C CNN -F 3 "" H 6850 2650 60 0000 C CNN - 1 6850 2650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4400 1850 4400 2050 -Wire Wire Line - 4400 2500 4400 2400 -Wire Wire Line - 4400 2400 4300 2400 -Wire Wire Line - 4350 3100 4350 3000 -Wire Wire Line - 4350 3000 4250 3000 -Wire Wire Line - 4350 3600 4350 3500 -Wire Wire Line - 4350 3500 4250 3500 -Wire Wire Line - 6400 2550 6400 2500 -Wire Wire Line - 6400 2500 6350 2500 -Wire Wire Line - 6400 2650 6400 2750 -Wire Wire Line - 6400 2750 6350 2750 -Wire Wire Line - 5450 2450 5350 2450 -Wire Wire Line - 5350 2450 5350 2100 -Wire Wire Line - 5350 2100 5300 2100 -Wire Wire Line - 5300 2550 5450 2550 -Wire Wire Line - 5450 2700 5300 2700 -Wire Wire Line - 5300 2700 5300 3150 -Wire Wire Line - 5300 3150 5250 3150 -Wire Wire Line - 5250 3650 5400 3650 -Wire Wire Line - 5400 3650 5400 2800 -Wire Wire Line - 5400 2800 5450 2800 -$Comp -L d_inverter U2 -U 1 1 5C9378F6 -P 2650 1350 -F 0 "U2" H 2650 1250 60 0000 C CNN -F 1 "d_inverter" H 2650 1500 60 0000 C CNN -F 2 "" H 2700 1300 60 0000 C CNN -F 3 "" H 2700 1300 60 0000 C CNN - 1 2650 1350 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5C93798D -P 2700 950 -F 0 "U3" H 2700 850 60 0000 C CNN -F 1 "d_inverter" H 2700 1100 60 0000 C CNN -F 2 "" H 2750 900 60 0000 C CNN -F 3 "" H 2750 900 60 0000 C CNN - 1 2700 950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3500 1800 3100 1800 -Wire Wire Line - 3100 1350 3100 5600 -Wire Wire Line - 3500 1900 3200 1900 -Wire Wire Line - 3200 950 3200 5100 -Wire Wire Line - 2950 1350 3100 1350 -Connection ~ 3100 1800 -Wire Wire Line - 3000 950 3200 950 -Connection ~ 3200 1900 -Wire Wire Line - 1800 950 2400 950 -Wire Wire Line - 1800 1350 2350 1350 -Wire Wire Line - 2200 950 2200 6200 -Connection ~ 2200 950 -Wire Wire Line - 2300 1350 2300 6100 -$Comp -L d_and U15 -U 1 1 5C937C96 -P 3850 2700 -F 0 "U15" H 3850 2700 60 0000 C CNN -F 1 "d_and" H 3900 2800 60 0000 C CNN -F 2 "" H 3850 2700 60 0000 C CNN -F 3 "" H 3850 2700 60 0000 C CNN - 1 3850 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U6 -U 1 1 5C937CEE -P 3800 3300 -F 0 "U6" H 3800 3300 60 0000 C CNN -F 1 "d_and" H 3850 3400 60 0000 C CNN -F 2 "" H 3800 3300 60 0000 C CNN -F 3 "" H 3800 3300 60 0000 C CNN - 1 3800 3300 - 1 0 0 -1 -$EndComp -$Comp -L d_and U8 -U 1 1 5C937D35 -P 3800 3800 -F 0 "U8" H 3800 3800 60 0000 C CNN -F 1 "d_and" H 3850 3900 60 0000 C CNN -F 2 "" H 3800 3800 60 0000 C CNN -F 3 "" H 3800 3800 60 0000 C CNN - 1 3800 3800 - 1 0 0 -1 -$EndComp -$Comp -L d_and U4 -U 1 1 5C937DC5 -P 3800 2150 -F 0 "U4" H 3800 2150 60 0000 C CNN -F 1 "d_and" H 3850 2250 60 0000 C CNN -F 2 "" H 3800 2150 60 0000 C CNN -F 3 "" H 3800 2150 60 0000 C CNN - 1 3800 2150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3350 2150 3300 2150 -Wire Wire Line - 3300 2150 3300 3800 -Wire Wire Line - 3300 2700 3400 2700 -Wire Wire Line - 3300 3300 3350 3300 -Connection ~ 3300 2700 -Wire Wire Line - 3000 3800 3350 3800 -Connection ~ 3300 3300 -Wire Wire Line - 4350 3200 4350 3250 -Wire Wire Line - 4350 3250 4250 3250 -Wire Wire Line - 4400 2600 4400 2650 -Wire Wire Line - 4400 2650 4300 2650 -Wire Wire Line - 4400 2150 4300 2150 -Wire Wire Line - 4300 2150 4300 2100 -Wire Wire Line - 4300 2100 4250 2100 -Wire Wire Line - 4350 3700 4250 3700 -Wire Wire Line - 4250 3700 4250 3750 -Wire Wire Line - 3350 3700 1600 3700 -Wire Wire Line - 3350 3200 1600 3200 -Wire Wire Line - 3400 2600 1600 2600 -Wire Wire Line - 3350 2050 1600 2050 -Wire Wire Line - 3000 3950 3000 3800 -Wire Wire Line - 2950 3950 3000 3950 -Wire Wire Line - 1600 3950 2350 3950 -Connection ~ 3300 3800 -$Comp -L d_and U16 -U 1 1 5C9388D0 -P 3850 5100 -F 0 "U16" H 3850 5100 60 0000 C CNN -F 1 "d_and" H 3900 5200 60 0000 C CNN -F 2 "" H 3850 5100 60 0000 C CNN -F 3 "" H 3850 5100 60 0000 C CNN - 1 3850 5100 - 1 0 0 -1 -$EndComp -$Comp -L d_and U27 -U 1 1 5C9388D6 -P 4850 5250 -F 0 "U27" H 4850 5250 60 0000 C CNN -F 1 "d_and" H 4900 5350 60 0000 C CNN -F 2 "" H 4850 5250 60 0000 C CNN -F 3 "" H 4850 5250 60 0000 C CNN - 1 4850 5250 - 1 0 0 -1 -$EndComp -$Comp -L d_and U10 -U 1 1 5C9388DC -P 3800 5700 -F 0 "U10" H 3800 5700 60 0000 C CNN -F 1 "d_and" H 3850 5800 60 0000 C CNN -F 2 "" H 3800 5700 60 0000 C CNN -F 3 "" H 3800 5700 60 0000 C CNN - 1 3800 5700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U22 -U 1 1 5C9388E2 -P 4800 5850 -F 0 "U22" H 4800 5850 60 0000 C CNN -F 1 "d_and" H 4850 5950 60 0000 C CNN -F 2 "" H 4800 5850 60 0000 C CNN -F 3 "" H 4800 5850 60 0000 C CNN - 1 4800 5850 - 1 0 0 -1 -$EndComp -$Comp -L d_and U12 -U 1 1 5C9388E8 -P 3800 6200 -F 0 "U12" H 3800 6200 60 0000 C CNN -F 1 "d_and" H 3850 6300 60 0000 C CNN -F 2 "" H 3800 6200 60 0000 C CNN -F 3 "" H 3800 6200 60 0000 C CNN - 1 3800 6200 - 1 0 0 -1 -$EndComp -$Comp -L d_and U23 -U 1 1 5C9388EE -P 4800 6350 -F 0 "U23" H 4800 6350 60 0000 C CNN -F 1 "d_and" H 4850 6450 60 0000 C CNN -F 2 "" H 4800 6350 60 0000 C CNN -F 3 "" H 4800 6350 60 0000 C CNN - 1 4800 6350 - 1 0 0 -1 -$EndComp -$Comp -L d_and U19 -U 1 1 5C9388F4 -P 3950 4550 -F 0 "U19" H 3950 4550 60 0000 C CNN -F 1 "d_and" H 4000 4650 60 0000 C CNN -F 2 "" H 3950 4550 60 0000 C CNN -F 3 "" H 3950 4550 60 0000 C CNN - 1 3950 4550 - 1 0 0 -1 -$EndComp -$Comp -L d_and U26 -U 1 1 5C9388FA -P 4850 4800 -F 0 "U26" H 4850 4800 60 0000 C CNN -F 1 "d_and" H 4900 4900 60 0000 C CNN -F 2 "" H 4850 4800 60 0000 C CNN -F 3 "" H 4850 4800 60 0000 C CNN - 1 4850 4800 - 1 0 0 -1 -$EndComp -$Comp -L d_or U30 -U 1 1 5C938900 -P 5900 5200 -F 0 "U30" H 5900 5200 60 0000 C CNN -F 1 "d_or" H 5900 5300 60 0000 C CNN -F 2 "" H 5900 5200 60 0000 C CNN -F 3 "" H 5900 5200 60 0000 C CNN - 1 5900 5200 - 1 0 0 -1 -$EndComp -$Comp -L d_or U31 -U 1 1 5C938906 -P 5900 5450 -F 0 "U31" H 5900 5450 60 0000 C CNN -F 1 "d_or" H 5900 5550 60 0000 C CNN -F 2 "" H 5900 5450 60 0000 C CNN -F 3 "" H 5900 5450 60 0000 C CNN - 1 5900 5450 - 1 0 0 -1 -$EndComp -$Comp -L d_or U33 -U 1 1 5C93890C -P 6850 5300 -F 0 "U33" H 6850 5300 60 0000 C CNN -F 1 "d_or" H 6850 5400 60 0000 C CNN -F 2 "" H 6850 5300 60 0000 C CNN -F 3 "" H 6850 5300 60 0000 C CNN - 1 6850 5300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4400 4500 4400 4700 -Wire Wire Line - 4400 5150 4400 5050 -Wire Wire Line - 4400 5050 4300 5050 -Wire Wire Line - 4350 5750 4350 5650 -Wire Wire Line - 4350 5650 4250 5650 -Wire Wire Line - 4350 6250 4350 6150 -Wire Wire Line - 4350 6150 4250 6150 -Wire Wire Line - 6400 5200 6400 5150 -Wire Wire Line - 6400 5150 6350 5150 -Wire Wire Line - 6400 5300 6400 5400 -Wire Wire Line - 6400 5400 6350 5400 -Wire Wire Line - 5450 5100 5350 5100 -Wire Wire Line - 5350 5100 5350 4750 -Wire Wire Line - 5350 4750 5300 4750 -Wire Wire Line - 5300 5200 5450 5200 -Wire Wire Line - 5450 5350 5300 5350 -Wire Wire Line - 5300 5350 5300 5800 -Wire Wire Line - 5300 5800 5250 5800 -Wire Wire Line - 5250 6300 5400 6300 -Wire Wire Line - 5400 6300 5400 5450 -Wire Wire Line - 5400 5450 5450 5450 -Wire Wire Line - 3100 4450 3500 4450 -Wire Wire Line - 3200 4550 3500 4550 -$Comp -L d_and U17 -U 1 1 5C938937 -P 3850 5350 -F 0 "U17" H 3850 5350 60 0000 C CNN -F 1 "d_and" H 3900 5450 60 0000 C CNN -F 2 "" H 3850 5350 60 0000 C CNN -F 3 "" H 3850 5350 60 0000 C CNN - 1 3850 5350 - 1 0 0 -1 -$EndComp -$Comp -L d_and U11 -U 1 1 5C93893D -P 3800 5950 -F 0 "U11" H 3800 5950 60 0000 C CNN -F 1 "d_and" H 3850 6050 60 0000 C CNN -F 2 "" H 3800 5950 60 0000 C CNN -F 3 "" H 3800 5950 60 0000 C CNN - 1 3800 5950 - 1 0 0 -1 -$EndComp -$Comp -L d_and U13 -U 1 1 5C938943 -P 3800 6450 -F 0 "U13" H 3800 6450 60 0000 C CNN -F 1 "d_and" H 3850 6550 60 0000 C CNN -F 2 "" H 3800 6450 60 0000 C CNN -F 3 "" H 3800 6450 60 0000 C CNN - 1 3800 6450 - 1 0 0 -1 -$EndComp -$Comp -L d_and U9 -U 1 1 5C938949 -P 3800 4800 -F 0 "U9" H 3800 4800 60 0000 C CNN -F 1 "d_and" H 3850 4900 60 0000 C CNN -F 2 "" H 3800 4800 60 0000 C CNN -F 3 "" H 3800 4800 60 0000 C CNN - 1 3800 4800 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3350 4800 3300 4800 -Wire Wire Line - 3300 4800 3300 6450 -Wire Wire Line - 3300 5350 3400 5350 -Wire Wire Line - 3300 5950 3350 5950 -Connection ~ 3300 5350 -Wire Wire Line - 3200 6450 3350 6450 -Connection ~ 3300 5950 -Wire Wire Line - 4350 5850 4350 5900 -Wire Wire Line - 4350 5900 4250 5900 -Wire Wire Line - 4400 5250 4400 5300 -Wire Wire Line - 4400 5300 4300 5300 -Wire Wire Line - 4400 4800 4300 4800 -Wire Wire Line - 4300 4800 4300 4750 -Wire Wire Line - 4300 4750 4250 4750 -Wire Wire Line - 4350 6350 4250 6350 -Wire Wire Line - 4250 6350 4250 6400 -Wire Wire Line - 3350 6350 1600 6350 -Wire Wire Line - 3350 5850 1600 5850 -Wire Wire Line - 3400 5250 1600 5250 -Wire Wire Line - 3350 4700 1600 4700 -Wire Wire Line - 3200 6600 3200 6450 -Wire Wire Line - 3000 6600 3200 6600 -Wire Wire Line - 1600 6600 2400 6600 -Connection ~ 3300 6450 -Connection ~ 2300 1350 -Connection ~ 3100 4450 -Connection ~ 3200 4550 -$Comp -L PORT U1 -U 1 1 5C93A0F9 -P 1350 2050 -F 0 "U1" H 1400 2150 30 0000 C CNN -F 1 "PORT" H 1350 2050 30 0000 C CNN -F 2 "" H 1350 2050 60 0000 C CNN -F 3 "" H 1350 2050 60 0000 C CNN - 1 1350 2050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C93A174 -P 1350 4700 -F 0 "U1" H 1400 4800 30 0000 C CNN -F 1 "PORT" H 1350 4700 30 0000 C CNN -F 2 "" H 1350 4700 60 0000 C CNN -F 3 "" H 1350 4700 60 0000 C CNN - 6 1350 4700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C93AA3C -P 1350 2600 -F 0 "U1" H 1400 2700 30 0000 C CNN -F 1 "PORT" H 1350 2600 30 0000 C CNN -F 2 "" H 1350 2600 60 0000 C CNN -F 3 "" H 1350 2600 60 0000 C CNN - 2 1350 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C93AACB -P 1350 3200 -F 0 "U1" H 1400 3300 30 0000 C CNN -F 1 "PORT" H 1350 3200 30 0000 C CNN -F 2 "" H 1350 3200 60 0000 C CNN -F 3 "" H 1350 3200 60 0000 C CNN - 3 1350 3200 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C93AB5F -P 1350 3700 -F 0 "U1" H 1400 3800 30 0000 C CNN -F 1 "PORT" H 1350 3700 30 0000 C CNN -F 2 "" H 1350 3700 60 0000 C CNN -F 3 "" H 1350 3700 60 0000 C CNN - 4 1350 3700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5C93AD97 -P 1350 5250 -F 0 "U1" H 1400 5350 30 0000 C CNN -F 1 "PORT" H 1350 5250 30 0000 C CNN -F 2 "" H 1350 5250 60 0000 C CNN -F 3 "" H 1350 5250 60 0000 C CNN - 7 1350 5250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5C93ADFC -P 1350 5850 -F 0 "U1" H 1400 5950 30 0000 C CNN -F 1 "PORT" H 1350 5850 30 0000 C CNN -F 2 "" H 1350 5850 60 0000 C CNN -F 3 "" H 1350 5850 60 0000 C CNN - 8 1350 5850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C93AE63 -P 1350 6350 -F 0 "U1" H 1400 6450 30 0000 C CNN -F 1 "PORT" H 1350 6350 30 0000 C CNN -F 2 "" H 1350 6350 60 0000 C CNN -F 3 "" H 1350 6350 60 0000 C CNN - 9 1350 6350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C93AECA -P 1350 3950 -F 0 "U1" H 1400 4050 30 0000 C CNN -F 1 "PORT" H 1350 3950 30 0000 C CNN -F 2 "" H 1350 3950 60 0000 C CNN -F 3 "" H 1350 3950 60 0000 C CNN - 5 1350 3950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C93AF79 -P 1350 6600 -F 0 "U1" H 1400 6700 30 0000 C CNN -F 1 "PORT" H 1350 6600 30 0000 C CNN -F 2 "" H 1350 6600 60 0000 C CNN -F 3 "" H 1350 6600 60 0000 C CNN - 10 1350 6600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C93B10A -P 1550 950 -F 0 "U1" H 1600 1050 30 0000 C CNN -F 1 "PORT" H 1550 950 30 0000 C CNN -F 2 "" H 1550 950 60 0000 C CNN -F 3 "" H 1550 950 60 0000 C CNN - 11 1550 950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5C93B179 -P 1550 1350 -F 0 "U1" H 1600 1450 30 0000 C CNN -F 1 "PORT" H 1550 1350 30 0000 C CNN -F 2 "" H 1550 1350 60 0000 C CNN -F 3 "" H 1550 1350 60 0000 C CNN - 12 1550 1350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7300 2600 7600 2600 -Wire Wire Line - 7300 5250 7650 5250 -$Comp -L PORT U1 -U 13 1 5C93B567 -P 7850 2600 -F 0 "U1" H 7900 2700 30 0000 C CNN -F 1 "PORT" H 7850 2600 30 0000 C CNN -F 2 "" H 7850 2600 60 0000 C CNN -F 3 "" H 7850 2600 60 0000 C CNN - 13 7850 2600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5C93B5DA -P 7900 5250 -F 0 "U1" H 7950 5350 30 0000 C CNN -F 1 "PORT" H 7900 5250 30 0000 C CNN -F 2 "" H 7900 5250 60 0000 C CNN -F 3 "" H 7900 5250 60 0000 C CNN - 14 7900 5250 - -1 0 0 1 -$EndComp -Connection ~ 2200 3450 -Wire Wire Line - 3200 5100 3400 5100 -Wire Wire Line - 3400 5000 2300 5000 -Connection ~ 2300 5000 -Wire Wire Line - 3100 5600 3350 5600 -Wire Wire Line - 2200 5700 3350 5700 -Wire Wire Line - 2200 6200 3350 6200 -Connection ~ 2200 5700 -Wire Wire Line - 2300 6100 3350 6100 -Wire Wire Line - 3400 2450 3200 2450 -Connection ~ 3200 2450 -Wire Wire Line - 3400 2350 2300 2350 -Connection ~ 2300 2350 -Wire Wire Line - 3350 3050 2200 3050 -Connection ~ 2200 3050 -Wire Wire Line - 3350 2950 3100 2950 -Connection ~ 3100 2950 -Wire Wire Line - 3350 3450 2300 3450 -Wire Wire Line - 2300 3450 2300 3400 -Connection ~ 2300 3400 -Wire Wire Line - 3350 3550 2200 3550 -Connection ~ 2200 3550 -$Comp -L d_inverter U34 -U 1 1 5C95C9D0 -P 2650 3950 -F 0 "U34" H 2650 3850 60 0000 C CNN -F 1 "d_inverter" H 2650 4100 60 0000 C CNN -F 2 "" H 2700 3900 60 0000 C CNN -F 3 "" H 2700 3900 60 0000 C CNN - 1 2650 3950 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U35 -U 1 1 5C95CD17 -P 2700 6600 -F 0 "U35" H 2700 6500 60 0000 C CNN -F 1 "d_inverter" H 2700 6750 60 0000 C CNN -F 2 "" H 2750 6550 60 0000 C CNN -F 3 "" H 2750 6550 60 0000 C CNN - 1 2700 6600 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74153/analysis b/src/SubcircuitLibrary/74153/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/74153/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and-cache.lib b/src/SubcircuitLibrary/74157/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/74157/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74157/3_and.cir b/src/SubcircuitLibrary/74157/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/74157/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/74157/3_and.cir.out b/src/SubcircuitLibrary/74157/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/74157/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/74157/3_and.pro b/src/SubcircuitLibrary/74157/3_and.pro deleted file mode 100644 index 2c9ac554..00000000 --- a/src/SubcircuitLibrary/74157/3_and.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/src/SubcircuitLibrary/74157/3_and.sch b/src/SubcircuitLibrary/74157/3_and.sch deleted file mode 100644 index 86be0215..00000000 --- a/src/SubcircuitLibrary/74157/3_and.sch +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/3_and.sub b/src/SubcircuitLibrary/74157/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/74157/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml b/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/74157/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157-cache.lib b/src/SubcircuitLibrary/74157/74157-cache.lib deleted file mode 100644 index de171255..00000000 --- a/src/SubcircuitLibrary/74157/74157-cache.lib +++ /dev/null @@ -1,95 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74157/74157-rescue.lib b/src/SubcircuitLibrary/74157/74157-rescue.lib deleted file mode 100644 index cac27fc1..00000000 --- a/src/SubcircuitLibrary/74157/74157-rescue.lib +++ /dev/null @@ -1,22 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and-RESCUE-74157 -# -DEF 3_and-RESCUE-74157 X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and-RESCUE-74157" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/74157/74157.cir b/src/SubcircuitLibrary/74157/74157.cir deleted file mode 100644 index 6920161c..00000000 --- a/src/SubcircuitLibrary/74157/74157.cir +++ /dev/null @@ -1,25 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\74157\74157.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:37:43 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad12_ d_or -U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad13_ d_or -U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U1-Pad14_ d_or -U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U1-Pad11_ d_or -U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT -U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter -X2 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U20-Pad1_ 3_and -X3 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad3_ Net-_U21-Pad1_ 3_and -X4 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad5_ Net-_U22-Pad1_ 3_and -X5 Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U23-Pad1_ 3_and -X6 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U20-Pad2_ 3_and -X7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U21-Pad2_ 3_and -X1 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad6_ Net-_U22-Pad2_ 3_and -X8 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U1-Pad8_ Net-_U23-Pad2_ 3_and - -.end diff --git a/src/SubcircuitLibrary/74157/74157.cir.out b/src/SubcircuitLibrary/74157/74157.cir.out deleted file mode 100644 index 3a11a42d..00000000 --- a/src/SubcircuitLibrary/74157/74157.cir.out +++ /dev/null @@ -1,45 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir - -.include 3_and.sub -* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or -* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or -* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or -* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or -* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port -* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter -x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and -x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and -x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and -x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and -x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and -x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and -x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and -x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and -a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 -a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 -a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 -a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 -a5 net-_u1-pad10_ net-_u3-pad2_ u3 -a6 net-_u1-pad9_ net-_u2-pad2_ u2 -* Schematic Name: d_or, NgSpice Name: d_or -.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/74157/74157.pro b/src/SubcircuitLibrary/74157/74157.pro deleted file mode 100644 index fcbb1fc8..00000000 --- a/src/SubcircuitLibrary/74157/74157.pro +++ /dev/null @@ -1,57 +0,0 @@ -update=03/28/19 22:30:06 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=intel -LibName3=audio -LibName4=interface -LibName5=digital-audio -LibName6=philips -LibName7=display -LibName8=cypress -LibName9=siliconi -LibName10=opto -LibName11=atmel -LibName12=contrib -LibName13=valves -LibName14=eSim_Analog -LibName15=eSim_Devices -LibName16=eSim_Digital -LibName17=eSim_Hybrid -LibName18=eSim_Miscellaneous -LibName19=eSim_Plot -LibName20=eSim_Power -LibName21=eSim_PSpice -LibName22=eSim_Sources -LibName23=eSim_User -LibName24=eSim_Subckt diff --git a/src/SubcircuitLibrary/74157/74157.sch b/src/SubcircuitLibrary/74157/74157.sch deleted file mode 100644 index 7fd3609e..00000000 --- a/src/SubcircuitLibrary/74157/74157.sch +++ /dev/null @@ -1,549 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:74157-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 1650 1850 2750 1850 -Wire Wire Line - 2750 3350 1650 3350 -Wire Wire Line - 2750 3050 2750 3350 -Wire Wire Line - 2800 4050 1650 4050 -Wire Wire Line - 2800 3550 2800 4050 -Wire Wire Line - 2200 2150 2200 4350 -Wire Wire Line - 2200 2150 1650 2150 -Wire Wire Line - 2150 2900 2150 4850 -Wire Wire Line - 2150 2900 1650 2900 -Wire Wire Line - 2100 3600 2100 5300 -Wire Wire Line - 2100 3600 1650 3600 -Wire Wire Line - 2050 4300 2050 5800 -Wire Wire Line - 1650 4300 2050 4300 -Wire Wire Line - 2200 5500 2200 6250 -$Comp -L d_or U20 -U 1 1 5C95E06C -P 6650 3300 -F 0 "U20" H 6650 3300 60 0000 C CNN -F 1 "d_or" H 6650 3400 60 0000 C CNN -F 2 "" H 6650 3300 60 0000 C CNN -F 3 "" H 6650 3300 60 0000 C CNN - 1 6650 3300 - 1 0 0 -1 -$EndComp -$Comp -L d_or U21 -U 1 1 5C95E114 -P 6650 3800 -F 0 "U21" H 6650 3800 60 0000 C CNN -F 1 "d_or" H 6650 3900 60 0000 C CNN -F 2 "" H 6650 3800 60 0000 C CNN -F 3 "" H 6650 3800 60 0000 C CNN - 1 6650 3800 - 1 0 0 -1 -$EndComp -$Comp -L d_or U22 -U 1 1 5C95E16E -P 6650 4250 -F 0 "U22" H 6650 4250 60 0000 C CNN -F 1 "d_or" H 6650 4350 60 0000 C CNN -F 2 "" H 6650 4250 60 0000 C CNN -F 3 "" H 6650 4250 60 0000 C CNN - 1 6650 4250 - 1 0 0 -1 -$EndComp -$Comp -L d_or U23 -U 1 1 5C95E1C9 -P 6650 4750 -F 0 "U23" H 6650 4750 60 0000 C CNN -F 1 "d_or" H 6650 4850 60 0000 C CNN -F 2 "" H 6650 4750 60 0000 C CNN -F 3 "" H 6650 4750 60 0000 C CNN - 1 6650 4750 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6200 3200 5950 3200 -Wire Wire Line - 5950 3200 5950 2000 -Wire Wire Line - 5950 2000 4750 2000 -Wire Wire Line - 6200 3700 5850 3700 -Wire Wire Line - 5850 3700 5850 2500 -Wire Wire Line - 5850 2500 4750 2500 -Wire Wire Line - 6200 4150 5750 4150 -Wire Wire Line - 5750 4150 5750 2950 -Wire Wire Line - 5750 2950 4750 2950 -Wire Wire Line - 6200 4650 5650 4650 -Wire Wire Line - 5650 4650 5650 3450 -Wire Wire Line - 5650 3450 4750 3450 -Wire Wire Line - 4750 4250 5450 4250 -Wire Wire Line - 5450 4250 5450 3300 -Wire Wire Line - 5450 3300 6200 3300 -Wire Wire Line - 4750 4750 5550 4750 -Wire Wire Line - 5550 4750 5550 3800 -Wire Wire Line - 5550 3800 6200 3800 -Wire Wire Line - 4700 5200 5600 5200 -Wire Wire Line - 5600 5200 5600 4250 -Wire Wire Line - 5600 4250 6200 4250 -Wire Wire Line - 4750 5700 5700 5700 -Wire Wire Line - 5700 5700 5700 4750 -Wire Wire Line - 5700 4750 6200 4750 -Wire Wire Line - 7100 3250 8300 3250 -Wire Wire Line - 7100 3750 8300 3750 -Wire Wire Line - 7100 4200 8300 4200 -Wire Wire Line - 7100 4700 8250 4700 -$Comp -L d_inverter U3 -U 1 1 5C95E74D -P 2750 6250 -F 0 "U3" H 2750 6150 60 0000 C CNN -F 1 "d_inverter" H 2750 6400 60 0000 C CNN -F 2 "" H 2800 6200 60 0000 C CNN -F 3 "" H 2800 6200 60 0000 C CNN - 1 2750 6250 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1700 6250 2450 6250 -Connection ~ 2200 6250 -$Comp -L PORT U1 -U 1 1 5C95E920 -P 1400 1850 -F 0 "U1" H 1450 1950 30 0000 C CNN -F 1 "PORT" H 1400 1850 30 0000 C CNN -F 2 "" H 1400 1850 60 0000 C CNN -F 3 "" H 1400 1850 60 0000 C CNN - 1 1400 1850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C95E9CF -P 1400 2150 -F 0 "U1" H 1450 2250 30 0000 C CNN -F 1 "PORT" H 1400 2150 30 0000 C CNN -F 2 "" H 1400 2150 60 0000 C CNN -F 3 "" H 1400 2150 60 0000 C CNN - 2 1400 2150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C95EA28 -P 1400 2700 -F 0 "U1" H 1450 2800 30 0000 C CNN -F 1 "PORT" H 1400 2700 30 0000 C CNN -F 2 "" H 1400 2700 60 0000 C CNN -F 3 "" H 1400 2700 60 0000 C CNN - 3 1400 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C95EA9C -P 1400 2900 -F 0 "U1" H 1450 3000 30 0000 C CNN -F 1 "PORT" H 1400 2900 30 0000 C CNN -F 2 "" H 1400 2900 60 0000 C CNN -F 3 "" H 1400 2900 60 0000 C CNN - 4 1400 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C95EAFD -P 1400 3350 -F 0 "U1" H 1450 3450 30 0000 C CNN -F 1 "PORT" H 1400 3350 30 0000 C CNN -F 2 "" H 1400 3350 60 0000 C CNN -F 3 "" H 1400 3350 60 0000 C CNN - 5 1400 3350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C95EB63 -P 1400 3600 -F 0 "U1" H 1450 3700 30 0000 C CNN -F 1 "PORT" H 1400 3600 30 0000 C CNN -F 2 "" H 1400 3600 60 0000 C CNN -F 3 "" H 1400 3600 60 0000 C CNN - 6 1400 3600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5C95EBC8 -P 1400 4050 -F 0 "U1" H 1450 4150 30 0000 C CNN -F 1 "PORT" H 1400 4050 30 0000 C CNN -F 2 "" H 1400 4050 60 0000 C CNN -F 3 "" H 1400 4050 60 0000 C CNN - 7 1400 4050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5C95EC38 -P 1400 4300 -F 0 "U1" H 1450 4400 30 0000 C CNN -F 1 "PORT" H 1400 4300 30 0000 C CNN -F 2 "" H 1400 4300 60 0000 C CNN -F 3 "" H 1400 4300 60 0000 C CNN - 8 1400 4300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C95ECA1 -P 1450 6250 -F 0 "U1" H 1500 6350 30 0000 C CNN -F 1 "PORT" H 1450 6250 30 0000 C CNN -F 2 "" H 1450 6250 60 0000 C CNN -F 3 "" H 1450 6250 60 0000 C CNN - 10 1450 6250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C95ED51 -P 1400 6650 -F 0 "U1" H 1450 6750 30 0000 C CNN -F 1 "PORT" H 1400 6650 30 0000 C CNN -F 2 "" H 1400 6650 60 0000 C CNN -F 3 "" H 1400 6650 60 0000 C CNN - 9 1400 6650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5C95EDCC -P 8550 3250 -F 0 "U1" H 8600 3350 30 0000 C CNN -F 1 "PORT" H 8550 3250 30 0000 C CNN -F 2 "" H 8550 3250 60 0000 C CNN -F 3 "" H 8550 3250 60 0000 C CNN - 12 8550 3250 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 13 1 5C95EEA6 -P 8550 3750 -F 0 "U1" H 8600 3850 30 0000 C CNN -F 1 "PORT" H 8550 3750 30 0000 C CNN -F 2 "" H 8550 3750 60 0000 C CNN -F 3 "" H 8550 3750 60 0000 C CNN - 13 8550 3750 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5C95EF2D -P 8550 4200 -F 0 "U1" H 8600 4300 30 0000 C CNN -F 1 "PORT" H 8550 4200 30 0000 C CNN -F 2 "" H 8550 4200 60 0000 C CNN -F 3 "" H 8550 4200 60 0000 C CNN - 14 8550 4200 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C95EFB5 -P 8500 4700 -F 0 "U1" H 8550 4800 30 0000 C CNN -F 1 "PORT" H 8500 4700 30 0000 C CNN -F 2 "" H 8500 4700 60 0000 C CNN -F 3 "" H 8500 4700 60 0000 C CNN - 11 8500 4700 - -1 0 0 1 -$EndComp -Text Notes 1950 1800 0 60 ~ 12 -A0\n -Text Notes 1950 2100 0 60 ~ 12 -A1 -Text Notes 1900 2650 0 60 ~ 12 -B0 -Text Notes 1900 2900 0 60 ~ 12 -B1\n -Text Notes 1900 3350 0 60 ~ 12 -C0\n -Text Notes 1900 3600 0 60 ~ 12 -C1\n -Text Notes 1800 4050 0 60 ~ 12 -D0 -Text Notes 1800 4300 0 60 ~ 12 -D1 -Text Notes 1850 6250 0 60 ~ 12 -SEL\n -Text Notes 1800 6650 0 60 ~ 12 -~EN -$Comp -L d_inverter U2 -U 1 1 5C95FD56 -P 2650 6650 -F 0 "U2" H 2650 6550 60 0000 C CNN -F 1 "d_inverter" H 2650 6800 60 0000 C CNN -F 2 "" H 2700 6600 60 0000 C CNN -F 3 "" H 2700 6600 60 0000 C CNN - 1 2650 6650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3400 6650 2950 6650 -Wire Wire Line - 1650 6650 2350 6650 -Text Notes 7850 3200 0 60 ~ 12 -YA -Text Notes 7850 3700 0 60 ~ 12 -YB -Text Notes 7850 4200 2 60 ~ 12 -YC -Text Notes 7800 4700 0 60 ~ 12 -YD -Wire Wire Line - 3450 2000 3900 2000 -Wire Wire Line - 3450 2000 3450 5700 -Wire Wire Line - 3450 2500 3900 2500 -Wire Wire Line - 3450 2950 3900 2950 -Connection ~ 3450 2500 -Wire Wire Line - 3450 3450 3900 3450 -Connection ~ 3450 2950 -Wire Wire Line - 3450 4250 3900 4250 -Connection ~ 3450 3450 -Wire Wire Line - 3450 4750 3900 4750 -Connection ~ 3450 4250 -Wire Wire Line - 3450 5200 3850 5200 -Connection ~ 3450 4750 -Wire Wire Line - 3400 5700 3900 5700 -Connection ~ 3450 5200 -Wire Wire Line - 3300 5600 3900 5600 -Wire Wire Line - 3300 4150 3300 5600 -Wire Wire Line - 3300 5100 3850 5100 -Wire Wire Line - 3300 4650 3900 4650 -Connection ~ 3300 5100 -Wire Wire Line - 3300 4150 3900 4150 -Connection ~ 3300 4650 -Wire Wire Line - 3250 3350 3900 3350 -Wire Wire Line - 3250 1900 3250 3350 -Wire Wire Line - 3250 2850 3900 2850 -Wire Wire Line - 3250 2400 3900 2400 -Connection ~ 3250 2850 -Wire Wire Line - 3250 1900 3900 1900 -Connection ~ 3250 2400 -Wire Wire Line - 3250 3000 3100 3000 -Wire Wire Line - 3100 3000 3100 6250 -Wire Wire Line - 3100 6250 3050 6250 -Connection ~ 3250 3000 -Wire Wire Line - 3300 5500 2200 5500 -Connection ~ 3300 5500 -Wire Wire Line - 3400 6650 3400 5700 -Connection ~ 3450 5700 -$Comp -L 3_and X2 -U 1 1 5C9D0110 -P 3450 2400 -F 0 "X2" H 4350 2700 60 0000 C CNN -F 1 "3_and" H 4400 2900 60 0000 C CNN -F 2 "" H 3450 2400 60 0000 C CNN -F 3 "" H 3450 2400 60 0000 C CNN - 1 3450 2400 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X3 -U 1 1 5C9D01B8 -P 3450 2900 -F 0 "X3" H 4350 3200 60 0000 C CNN -F 1 "3_and" H 4400 3400 60 0000 C CNN -F 2 "" H 3450 2900 60 0000 C CNN -F 3 "" H 3450 2900 60 0000 C CNN - 1 3450 2900 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X4 -U 1 1 5C9D0222 -P 3450 3350 -F 0 "X4" H 4350 3650 60 0000 C CNN -F 1 "3_and" H 4400 3850 60 0000 C CNN -F 2 "" H 3450 3350 60 0000 C CNN -F 3 "" H 3450 3350 60 0000 C CNN - 1 3450 3350 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X5 -U 1 1 5C9D0289 -P 3450 3850 -F 0 "X5" H 4350 4150 60 0000 C CNN -F 1 "3_and" H 4400 4350 60 0000 C CNN -F 2 "" H 3450 3850 60 0000 C CNN -F 3 "" H 3450 3850 60 0000 C CNN - 1 3450 3850 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X6 -U 1 1 5C9D0361 -P 3450 4650 -F 0 "X6" H 4350 4950 60 0000 C CNN -F 1 "3_and" H 4400 5150 60 0000 C CNN -F 2 "" H 3450 4650 60 0000 C CNN -F 3 "" H 3450 4650 60 0000 C CNN - 1 3450 4650 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X7 -U 1 1 5C9D0367 -P 3450 5150 -F 0 "X7" H 4350 5450 60 0000 C CNN -F 1 "3_and" H 4400 5650 60 0000 C CNN -F 2 "" H 3450 5150 60 0000 C CNN -F 3 "" H 3450 5150 60 0000 C CNN - 1 3450 5150 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X1 -U 1 1 5C9D036D -P 3400 5600 -F 0 "X1" H 4300 5900 60 0000 C CNN -F 1 "3_and" H 4350 6100 60 0000 C CNN -F 2 "" H 3400 5600 60 0000 C CNN -F 3 "" H 3400 5600 60 0000 C CNN - 1 3400 5600 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X8 -U 1 1 5C9D0373 -P 3450 6100 -F 0 "X8" H 4350 6400 60 0000 C CNN -F 1 "3_and" H 4400 6600 60 0000 C CNN -F 2 "" H 3450 6100 60 0000 C CNN -F 3 "" H 3450 6100 60 0000 C CNN - 1 3450 6100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3900 2100 2750 2100 -Wire Wire Line - 2750 2100 2750 1850 -Wire Wire Line - 3900 2600 1650 2600 -Wire Wire Line - 1650 2600 1650 2700 -Wire Wire Line - 3900 3050 2750 3050 -Wire Wire Line - 3900 3550 2800 3550 -Wire Wire Line - 2200 4350 3900 4350 -Wire Wire Line - 2150 4850 3900 4850 -Wire Wire Line - 2100 5300 3850 5300 -Wire Wire Line - 2050 5800 3900 5800 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/74157/74157.sub b/src/SubcircuitLibrary/74157/74157.sub deleted file mode 100644 index 545741f5..00000000 --- a/src/SubcircuitLibrary/74157/74157.sub +++ /dev/null @@ -1,39 +0,0 @@ -* Subcircuit 74157 -.subckt 74157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ -* c:\users\malli\esim\src\subcircuitlibrary\74157\74157.cir -.include 3_and.sub -* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad12_ d_or -* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u1-pad13_ d_or -* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u1-pad14_ d_or -* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u1-pad11_ d_or -* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter -* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter -x2 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad1_ net-_u20-pad1_ 3_and -x3 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad3_ net-_u21-pad1_ 3_and -x4 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad5_ net-_u22-pad1_ 3_and -x5 net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad7_ net-_u23-pad1_ 3_and -x6 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad2_ net-_u20-pad2_ 3_and -x7 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad4_ net-_u21-pad2_ 3_and -x1 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad6_ net-_u22-pad2_ 3_and -x8 net-_u1-pad10_ net-_u2-pad2_ net-_u1-pad8_ net-_u23-pad2_ 3_and -a1 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad12_ u20 -a2 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u1-pad13_ u21 -a3 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u1-pad14_ u22 -a4 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u1-pad11_ u23 -a5 net-_u1-pad10_ net-_u3-pad2_ u3 -a6 net-_u1-pad9_ net-_u2-pad2_ u2 -* Schematic Name: d_or, NgSpice Name: d_or -.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u21 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u22 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_or, NgSpice Name: d_or -.model u23 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 74157
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml b/src/SubcircuitLibrary/74157/74157_Previous_Values.xml deleted file mode 100644 index 85f14960..00000000 --- a/src/SubcircuitLibrary/74157/74157_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u4 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u12 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u13><u8 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u8><u16 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u16><u9 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u9><u17 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u17><u6 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u6><u14 name="type">d_and<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u7 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u7><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u10><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u11><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u22 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u23><u3 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/74157/analysis b/src/SubcircuitLibrary/74157/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/74157/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and-cache.lib b/src/SubcircuitLibrary/7485/3_and-cache.lib deleted file mode 100644 index af058641..00000000 --- a/src/SubcircuitLibrary/7485/3_and-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/3_and.cir b/src/SubcircuitLibrary/7485/3_and.cir deleted file mode 100644 index ba296cf0..00000000 --- a/src/SubcircuitLibrary/7485/3_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/7485/3_and.cir.out b/src/SubcircuitLibrary/7485/3_and.cir.out deleted file mode 100644 index d7cf79a0..00000000 --- a/src/SubcircuitLibrary/7485/3_and.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/7485/3_and.pro b/src/SubcircuitLibrary/7485/3_and.pro deleted file mode 100644 index 2c9ac554..00000000 --- a/src/SubcircuitLibrary/7485/3_and.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/src/SubcircuitLibrary/7485/3_and.sch b/src/SubcircuitLibrary/7485/3_and.sch deleted file mode 100644 index 86be0215..00000000 --- a/src/SubcircuitLibrary/7485/3_and.sch +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/3_and.sub b/src/SubcircuitLibrary/7485/3_and.sub deleted file mode 100644 index 3d9120bb..00000000 --- a/src/SubcircuitLibrary/7485/3_and.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml deleted file mode 100644 index abc5faaa..00000000 --- a/src/SubcircuitLibrary/7485/3_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and-cache.lib b/src/SubcircuitLibrary/7485/4_and-cache.lib deleted file mode 100644 index ac396288..00000000 --- a/src/SubcircuitLibrary/7485/4_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/4_and-rescue.lib b/src/SubcircuitLibrary/7485/4_and-rescue.lib deleted file mode 100644 index 6b2c17f7..00000000 --- a/src/SubcircuitLibrary/7485/4_and-rescue.lib +++ /dev/null @@ -1,22 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 3_and-RESCUE-4_and
-#
-DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
-F0 "X" 900 300 60 H V C CNN
-F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
-P 2 0 1 0 650 550 1000 550 N
-P 3 0 1 0 650 550 650 250 1000 250 N
-X in1 1 450 500 200 R 50 50 1 1 I
-X in2 2 450 400 200 R 50 50 1 1 I
-X in3 3 450 300 200 R 50 50 1 1 I
-X out 4 1300 400 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/7485/4_and.cir b/src/SubcircuitLibrary/7485/4_and.cir deleted file mode 100644 index 50d490fa..00000000 --- a/src/SubcircuitLibrary/7485/4_and.cir +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:01:09 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and -U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT - -.end diff --git a/src/SubcircuitLibrary/7485/4_and.cir.out b/src/SubcircuitLibrary/7485/4_and.cir.out deleted file mode 100644 index f40e5bc6..00000000 --- a/src/SubcircuitLibrary/7485/4_and.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port -a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/7485/4_and.pro b/src/SubcircuitLibrary/7485/4_and.pro deleted file mode 100644 index 6eb77fff..00000000 --- a/src/SubcircuitLibrary/7485/4_and.pro +++ /dev/null @@ -1,57 +0,0 @@ -update=03/26/19 18:58:33 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=texas -LibName2=intel -LibName3=audio -LibName4=interface -LibName5=digital-audio -LibName6=philips -LibName7=display -LibName8=cypress -LibName9=siliconi -LibName10=opto -LibName11=atmel -LibName12=contrib -LibName13=valves -LibName14=eSim_Analog -LibName15=eSim_Devices -LibName16=eSim_Digital -LibName17=eSim_Hybrid -LibName18=eSim_Miscellaneous -LibName19=eSim_Plot -LibName20=eSim_Power -LibName21=eSim_PSpice -LibName22=eSim_Sources -LibName23=eSim_Subckt -LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/4_and.sch b/src/SubcircuitLibrary/7485/4_and.sch deleted file mode 100644 index 883458e1..00000000 --- a/src/SubcircuitLibrary/7485/4_and.sch +++ /dev/null @@ -1,139 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5C9A2915 -P 3700 3500 -F 0 "X1" H 4600 3800 60 0000 C CNN -F 1 "3_and" H 4650 4000 60 0000 C CNN -F 2 "" H 3700 3500 60 0000 C CNN -F 3 "" H 3700 3500 60 0000 C CNN - 1 3700 3500 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C9A2940 -P 5450 3400 -F 0 "U2" H 5450 3400 60 0000 C CNN -F 1 "d_and" H 5500 3500 60 0000 C CNN -F 2 "" H 5450 3400 60 0000 C CNN -F 3 "" H 5450 3400 60 0000 C CNN - 1 5450 3400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5000 3100 5000 3300 -Wire Wire Line - 4150 3000 4150 2700 -Wire Wire Line - 4150 2700 3200 2700 -Wire Wire Line - 4150 3100 4000 3100 -Wire Wire Line - 4000 3100 4000 3000 -Wire Wire Line - 4000 3000 3200 3000 -Wire Wire Line - 4150 3200 4150 3300 -Wire Wire Line - 4150 3300 3250 3300 -Wire Wire Line - 5000 3400 5000 3550 -Wire Wire Line - 5000 3550 3250 3550 -Wire Wire Line - 5900 3350 6500 3350 -$Comp -L PORT U1 -U 1 1 5C9A29B1 -P 2950 2700 -F 0 "U1" H 3000 2800 30 0000 C CNN -F 1 "PORT" H 2950 2700 30 0000 C CNN -F 2 "" H 2950 2700 60 0000 C CNN -F 3 "" H 2950 2700 60 0000 C CNN - 1 2950 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A29E9 -P 2950 3000 -F 0 "U1" H 3000 3100 30 0000 C CNN -F 1 "PORT" H 2950 3000 30 0000 C CNN -F 2 "" H 2950 3000 60 0000 C CNN -F 3 "" H 2950 3000 60 0000 C CNN - 2 2950 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A2A0D -P 3000 3300 -F 0 "U1" H 3050 3400 30 0000 C CNN -F 1 "PORT" H 3000 3300 30 0000 C CNN -F 2 "" H 3000 3300 60 0000 C CNN -F 3 "" H 3000 3300 60 0000 C CNN - 3 3000 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2A3C -P 3000 3550 -F 0 "U1" H 3050 3650 30 0000 C CNN -F 1 "PORT" H 3000 3550 30 0000 C CNN -F 2 "" H 3000 3550 60 0000 C CNN -F 3 "" H 3000 3550 60 0000 C CNN - 4 3000 3550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A2A68 -P 6750 3350 -F 0 "U1" H 6800 3450 30 0000 C CNN -F 1 "PORT" H 6750 3350 30 0000 C CNN -F 2 "" H 6750 3350 60 0000 C CNN -F 3 "" H 6750 3350 60 0000 C CNN - 5 6750 3350 - -1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/4_and.sub b/src/SubcircuitLibrary/7485/4_and.sub deleted file mode 100644 index 8663f37e..00000000 --- a/src/SubcircuitLibrary/7485/4_and.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit 4_and -.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ -* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and -* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and -a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 4_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml deleted file mode 100644 index f2ba0130..00000000 --- a/src/SubcircuitLibrary/7485/4_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and-cache.lib b/src/SubcircuitLibrary/7485/5_and-cache.lib deleted file mode 100644 index ac396288..00000000 --- a/src/SubcircuitLibrary/7485/5_and-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/5_and.cir b/src/SubcircuitLibrary/7485/5_and.cir deleted file mode 100644 index 6a05b9b5..00000000 --- a/src/SubcircuitLibrary/7485/5_and.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and -U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and -U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT - -.end diff --git a/src/SubcircuitLibrary/7485/5_and.cir.out b/src/SubcircuitLibrary/7485/5_and.cir.out deleted file mode 100644 index 6a6b126a..00000000 --- a/src/SubcircuitLibrary/7485/5_and.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port -a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/7485/5_and.pro b/src/SubcircuitLibrary/7485/5_and.pro deleted file mode 100644 index c82e4e6d..00000000 --- a/src/SubcircuitLibrary/7485/5_and.pro +++ /dev/null @@ -1,50 +0,0 @@ -update=03/26/19 18:50:27 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=cypress -LibName2=siliconi -LibName3=opto -LibName4=atmel -LibName5=contrib -LibName6=valves -LibName7=eSim_Analog -LibName8=eSim_Devices -LibName9=eSim_Digital -LibName10=eSim_Hybrid -LibName11=eSim_Miscellaneous -LibName12=eSim_Plot -LibName13=eSim_Power -LibName14=eSim_PSpice -LibName15=eSim_Sources -LibName16=eSim_Subckt -LibName17=eSim_User diff --git a/src/SubcircuitLibrary/7485/5_and.sch b/src/SubcircuitLibrary/7485/5_and.sch deleted file mode 100644 index da927b09..00000000 --- a/src/SubcircuitLibrary/7485/5_and.sch +++ /dev/null @@ -1,158 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5C9A2741 -P 3800 3350 -F 0 "X1" H 4700 3650 60 0000 C CNN -F 1 "3_and" H 4750 3850 60 0000 C CNN -F 2 "" H 3800 3350 60 0000 C CNN -F 3 "" H 3800 3350 60 0000 C CNN - 1 3800 3350 - 1 0 0 -1 -$EndComp -$Comp -L d_and U2 -U 1 1 5C9A2764 -P 4650 3400 -F 0 "U2" H 4650 3400 60 0000 C CNN -F 1 "d_and" H 4700 3500 60 0000 C CNN -F 2 "" H 4650 3400 60 0000 C CNN -F 3 "" H 4650 3400 60 0000 C CNN - 1 4650 3400 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2791 -P 5550 3200 -F 0 "U3" H 5550 3200 60 0000 C CNN -F 1 "d_and" H 5600 3300 60 0000 C CNN -F 2 "" H 5550 3200 60 0000 C CNN -F 3 "" H 5550 3200 60 0000 C CNN - 1 5550 3200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5100 3100 5100 2950 -Wire Wire Line - 5100 3200 5100 3350 -Wire Wire Line - 4250 2850 4250 2700 -Wire Wire Line - 4250 2700 3600 2700 -Wire Wire Line - 4250 2950 4150 2950 -Wire Wire Line - 4150 2950 4150 2900 -Wire Wire Line - 4150 2900 3600 2900 -Wire Wire Line - 4200 3300 3600 3300 -Wire Wire Line - 4250 3050 4250 3100 -Wire Wire Line - 4250 3100 3600 3100 -Wire Wire Line - 4200 3400 4200 3500 -Wire Wire Line - 4200 3500 3600 3500 -Wire Wire Line - 6000 3150 6500 3150 -$Comp -L PORT U1 -U 1 1 5C9A2865 -P 3350 2700 -F 0 "U1" H 3400 2800 30 0000 C CNN -F 1 "PORT" H 3350 2700 30 0000 C CNN -F 2 "" H 3350 2700 60 0000 C CNN -F 3 "" H 3350 2700 60 0000 C CNN - 1 3350 2700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A28B6 -P 3350 2900 -F 0 "U1" H 3400 3000 30 0000 C CNN -F 1 "PORT" H 3350 2900 30 0000 C CNN -F 2 "" H 3350 2900 60 0000 C CNN -F 3 "" H 3350 2900 60 0000 C CNN - 2 3350 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A28D9 -P 3350 3100 -F 0 "U1" H 3400 3200 30 0000 C CNN -F 1 "PORT" H 3350 3100 30 0000 C CNN -F 2 "" H 3350 3100 60 0000 C CNN -F 3 "" H 3350 3100 60 0000 C CNN - 3 3350 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A28FF -P 3350 3300 -F 0 "U1" H 3400 3400 30 0000 C CNN -F 1 "PORT" H 3350 3300 30 0000 C CNN -F 2 "" H 3350 3300 60 0000 C CNN -F 3 "" H 3350 3300 60 0000 C CNN - 4 3350 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A2928 -P 3350 3500 -F 0 "U1" H 3400 3600 30 0000 C CNN -F 1 "PORT" H 3350 3500 30 0000 C CNN -F 2 "" H 3350 3500 60 0000 C CNN -F 3 "" H 3350 3500 60 0000 C CNN - 5 3350 3500 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C9A2958 -P 6750 3150 -F 0 "U1" H 6800 3250 30 0000 C CNN -F 1 "PORT" H 6750 3150 30 0000 C CNN -F 2 "" H 6750 3150 60 0000 C CNN -F 3 "" H 6750 3150 60 0000 C CNN - 6 6750 3150 - -1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_and.sub b/src/SubcircuitLibrary/7485/5_and.sub deleted file mode 100644 index 35b10e17..00000000 --- a/src/SubcircuitLibrary/7485/5_and.sub +++ /dev/null @@ -1,16 +0,0 @@ -* Subcircuit 5_and -.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ -* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and -a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_and
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml deleted file mode 100644 index ae2c08a7..00000000 --- a/src/SubcircuitLibrary/7485/5_and_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_nor-cache.lib b/src/SubcircuitLibrary/7485/5_nor-cache.lib deleted file mode 100644 index 7098010f..00000000 --- a/src/SubcircuitLibrary/7485/5_nor-cache.lib +++ /dev/null @@ -1,95 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 50 -100 60 H V C CNN -F1 "5_and" 100 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 -P 2 0 1 0 -250 250 150 250 N -P 3 0 1 0 -250 250 -250 -250 150 -250 N -X in1 1 -450 200 200 R 50 50 1 1 I -X in2 2 -450 100 200 R 50 50 1 1 I -X in3 3 -450 0 200 R 50 50 1 1 I -X in4 4 -450 -100 200 R 50 50 1 1 I -X in5 5 -450 -200 200 R 50 50 1 1 I -X out 6 550 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/5_nor.cir b/src/SubcircuitLibrary/7485/5_nor.cir deleted file mode 100644 index 0e4db1ea..00000000 --- a/src/SubcircuitLibrary/7485/5_nor.cir +++ /dev/null @@ -1,19 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_nor/5_nor.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 25 23:34:56 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and -U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter -U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter -U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter -U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter -U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter -U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT -X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and - -.end diff --git a/src/SubcircuitLibrary/7485/5_nor.cir.out b/src/SubcircuitLibrary/7485/5_nor.cir.out deleted file mode 100644 index bc90e004..00000000 --- a/src/SubcircuitLibrary/7485/5_nor.cir.out +++ /dev/null @@ -1,42 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir - -.include 5_and.sub -* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter -* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port -x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and -a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 net-_u1-pad2_ net-_u3-pad2_ u3 -a4 net-_u1-pad3_ net-_u4-pad2_ u4 -a5 net-_u1-pad4_ net-_u5-pad2_ u5 -a6 net-_u1-pad5_ net-_u6-pad2_ u6 -a7 net-_u1-pad6_ net-_u7-pad2_ u7 -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/7485/5_nor.pro b/src/SubcircuitLibrary/7485/5_nor.pro deleted file mode 100644 index 4716d4ae..00000000 --- a/src/SubcircuitLibrary/7485/5_nor.pro +++ /dev/null @@ -1,73 +0,0 @@ -update=Tue Jun 25 23:32:34 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_User -LibName37=eSim_Plot -LibName38=eSim_PSpice -LibName39=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt - diff --git a/src/SubcircuitLibrary/7485/5_nor.sch b/src/SubcircuitLibrary/7485/5_nor.sch deleted file mode 100644 index 6bb6fcb8..00000000 --- a/src/SubcircuitLibrary/7485/5_nor.sch +++ /dev/null @@ -1,275 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:eSim_Subckt -LIBS:c_gate-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U8 -U 1 1 5D126275 -P 5600 3300 -F 0 "U8" H 5600 3300 60 0000 C CNN -F 1 "d_and" H 5650 3400 60 0000 C CNN -F 2 "" H 5600 3300 60 0000 C CNN -F 3 "" H 5600 3300 60 0000 C CNN - 1 5600 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5150 3200 5150 2850 -Wire Wire Line - 4150 2650 4150 2350 -Wire Wire Line - 4150 2350 3600 2350 -Wire Wire Line - 4150 2750 4050 2750 -Wire Wire Line - 4050 2750 4050 2550 -Wire Wire Line - 4050 2550 3600 2550 -Wire Wire Line - 4150 2850 3700 2850 -Wire Wire Line - 3700 2850 3700 2750 -Wire Wire Line - 3700 2750 3600 2750 -Wire Wire Line - 4150 2950 3600 2950 -Wire Wire Line - 4150 3050 4150 3150 -Wire Wire Line - 4150 3150 3600 3150 -Wire Wire Line - 5150 3300 3600 3300 -$Comp -L d_inverter U2 -U 1 1 5D126276 -P 3300 2350 -F 0 "U2" H 3300 2250 60 0000 C CNN -F 1 "d_inverter" H 3300 2500 60 0000 C CNN -F 2 "" H 3350 2300 60 0000 C CNN -F 3 "" H 3350 2300 60 0000 C CNN - 1 3300 2350 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5D126277 -P 3300 2550 -F 0 "U3" H 3300 2450 60 0000 C CNN -F 1 "d_inverter" H 3300 2700 60 0000 C CNN -F 2 "" H 3350 2500 60 0000 C CNN -F 3 "" H 3350 2500 60 0000 C CNN - 1 3300 2550 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5D126278 -P 3300 2750 -F 0 "U4" H 3300 2650 60 0000 C CNN -F 1 "d_inverter" H 3300 2900 60 0000 C CNN -F 2 "" H 3350 2700 60 0000 C CNN -F 3 "" H 3350 2700 60 0000 C CNN - 1 3300 2750 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U5 -U 1 1 5D126279 -P 3300 2950 -F 0 "U5" H 3300 2850 60 0000 C CNN -F 1 "d_inverter" H 3300 3100 60 0000 C CNN -F 2 "" H 3350 2900 60 0000 C CNN -F 3 "" H 3350 2900 60 0000 C CNN - 1 3300 2950 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U6 -U 1 1 5D12627A -P 3300 3150 -F 0 "U6" H 3300 3050 60 0000 C CNN -F 1 "d_inverter" H 3300 3300 60 0000 C CNN -F 2 "" H 3350 3100 60 0000 C CNN -F 3 "" H 3350 3100 60 0000 C CNN - 1 3300 3150 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U7 -U 1 1 5D12627B -P 3300 3300 -F 0 "U7" H 3300 3200 60 0000 C CNN -F 1 "d_inverter" H 3300 3450 60 0000 C CNN -F 2 "" H 3350 3250 60 0000 C CNN -F 3 "" H 3350 3250 60 0000 C CNN - 1 3300 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3000 2350 2000 2350 -Wire Wire Line - 3000 2550 2000 2550 -Wire Wire Line - 3000 2750 2050 2750 -Wire Wire Line - 3000 2950 2050 2950 -Wire Wire Line - 3000 3150 2050 3150 -Wire Wire Line - 3000 3300 2050 3300 -Wire Wire Line - 6050 3250 6950 3250 -$Comp -L PORT U1 -U 1 1 5D12627C -P 1750 2350 -F 0 "U1" H 1800 2450 30 0000 C CNN -F 1 "PORT" H 1750 2350 30 0000 C CNN -F 2 "" H 1750 2350 60 0000 C CNN -F 3 "" H 1750 2350 60 0000 C CNN - 1 1750 2350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D12627D -P 1750 2550 -F 0 "U1" H 1800 2650 30 0000 C CNN -F 1 "PORT" H 1750 2550 30 0000 C CNN -F 2 "" H 1750 2550 60 0000 C CNN -F 3 "" H 1750 2550 60 0000 C CNN - 2 1750 2550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5D12627E -P 1800 2750 -F 0 "U1" H 1850 2850 30 0000 C CNN -F 1 "PORT" H 1800 2750 30 0000 C CNN -F 2 "" H 1800 2750 60 0000 C CNN -F 3 "" H 1800 2750 60 0000 C CNN - 3 1800 2750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5D12627F -P 1800 2950 -F 0 "U1" H 1850 3050 30 0000 C CNN -F 1 "PORT" H 1800 2950 30 0000 C CNN -F 2 "" H 1800 2950 60 0000 C CNN -F 3 "" H 1800 2950 60 0000 C CNN - 4 1800 2950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5D126280 -P 1800 3150 -F 0 "U1" H 1850 3250 30 0000 C CNN -F 1 "PORT" H 1800 3150 30 0000 C CNN -F 2 "" H 1800 3150 60 0000 C CNN -F 3 "" H 1800 3150 60 0000 C CNN - 5 1800 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5D126281 -P 1800 3300 -F 0 "U1" H 1850 3400 30 0000 C CNN -F 1 "PORT" H 1800 3300 30 0000 C CNN -F 2 "" H 1800 3300 60 0000 C CNN -F 3 "" H 1800 3300 60 0000 C CNN - 6 1800 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5D126282 -P 7200 3250 -F 0 "U1" H 7250 3350 30 0000 C CNN -F 1 "PORT" H 7200 3250 30 0000 C CNN -F 2 "" H 7200 3250 60 0000 C CNN -F 3 "" H 7200 3250 60 0000 C CNN - 7 7200 3250 - -1 0 0 1 -$EndComp -Text Notes 2400 2350 0 60 ~ 12 -in1 -Text Notes 2400 2550 0 60 ~ 12 -in2 -Text Notes 2400 2750 0 60 ~ 12 -in3 -Text Notes 2400 2950 0 60 ~ 12 -in4 -Text Notes 2400 3150 0 60 ~ 12 -in5 -Text Notes 2400 3300 0 60 ~ 12 -in6 -Text Notes 6350 3250 0 60 ~ 12 -out -$Comp -L 5_and X1 -U 1 1 5D1262D5 -P 4600 2850 -F 0 "X1" H 4650 2750 60 0000 C CNN -F 1 "5_and" H 4700 3000 60 0000 C CNN -F 2 "" H 4600 2850 60 0000 C CNN -F 3 "" H 4600 2850 60 0000 C CNN - 1 4600 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/5_nor.sub b/src/SubcircuitLibrary/7485/5_nor.sub deleted file mode 100644 index dbcdb750..00000000 --- a/src/SubcircuitLibrary/7485/5_nor.sub +++ /dev/null @@ -1,36 +0,0 @@ -* Subcircuit 5_nor -.subckt 5_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/5_nor/5_nor.cir -.include 5_and.sub -* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter -* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter -x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and -a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 net-_u1-pad2_ net-_u3-pad2_ u3 -a4 net-_u1-pad3_ net-_u4-pad2_ u4 -a5 net-_u1-pad4_ net-_u5-pad2_ u5 -a6 net-_u1-pad5_ net-_u6-pad2_ u6 -a7 net-_u1-pad6_ net-_u7-pad2_ u7 -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 5_nor
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml b/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml deleted file mode 100644 index 75f5258c..00000000 --- a/src/SubcircuitLibrary/7485/5_nor_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485-cache.lib b/src/SubcircuitLibrary/7485/7485-cache.lib deleted file mode 100644 index 6edb5033..00000000 --- a/src/SubcircuitLibrary/7485/7485-cache.lib +++ /dev/null @@ -1,175 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_and -# -DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 1500 1050 60 H V C CNN -F1 "4_and" 1550 1200 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 -P 2 0 1 0 1250 1300 1600 1300 N -P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N -X in1 1 1050 1250 200 R 50 50 1 1 I -X in2 2 1050 1150 200 R 50 50 1 1 I -X in3 3 1050 1050 200 R 50 50 1 1 I -X in4 4 1050 950 200 R 50 50 1 1 I -X out 5 1950 1100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 1350 800 60 H V C CNN -F1 "5_and" 1400 1050 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 -P 2 0 1 0 1050 1150 1450 1150 N -P 3 0 1 0 1050 1150 1050 650 1450 650 N -X in1 1 850 1100 200 R 50 50 1 1 I -X in2 2 850 1000 200 R 50 50 1 1 I -X in3 3 850 900 200 R 50 50 1 1 I -X in4 4 850 800 200 R 50 50 1 1 I -X in5 5 850 700 200 R 50 50 1 1 I -X out 6 1850 900 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# c_gate -# -DEF c_gate X 0 40 Y Y 1 F N -F0 "X" 5900 4450 60 H V C CNN -F1 "c_gate" 5950 4700 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 -P 2 0 1 0 5550 4850 6100 4850 N -P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N -X in1 1 5350 4800 200 R 50 50 1 1 I I -X in2 2 5350 4700 200 R 50 50 1 1 I I -X in3 3 5350 4600 200 R 50 50 1 1 I I -X in4 4 5350 4500 200 R 50 50 1 1 I I -X in5 5 5350 4400 200 R 50 50 1 1 I I -X in6 6 5350 4300 200 R 50 50 1 1 I I -X out 7 6500 4550 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_nand -# -DEF d_nand U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nand" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_nor -# -DEF d_nor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nor" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/7485.cir b/src/SubcircuitLibrary/7485/7485.cir deleted file mode 100644 index e15a357f..00000000 --- a/src/SubcircuitLibrary/7485/7485.cir +++ /dev/null @@ -1,42 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\7485\7485.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 20:14:28 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U6 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U14-Pad1_ d_and -U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad2_ d_nand -U7 Net-_U18-Pad2_ Net-_U1-Pad5_ Net-_U14-Pad2_ d_and -U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor -U19 Net-_U1-Pad5_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and -X12 Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X12-Pad4_ 3_and -X7 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_X2-Pad3_ 4_and -X9 Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X2-Pad4_ 5_and -X10 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad1_ Net-_X10-Pad6_ 5_and -X11 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X11-Pad6_ 5_and -X13 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad13_ 5_and -U18 Net-_U1-Pad4_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and -X8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U14-Pad3_ Net-_X1-Pad5_ 3_and -X3 Net-_U1-Pad8_ Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U15-Pad3_ Net-_X1-Pad4_ 4_and -X6 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_X1-Pad3_ 5_and -X5 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad3_ Net-_X1-Pad2_ 5_and -X4 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad1_ 5_and -U8 Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U15-Pad1_ d_and -U3 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand -U9 Net-_U3-Pad3_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_and -U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor -U12 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and -U5 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U12-Pad2_ d_nand -U13 Net-_U12-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad3_ d_and -U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor -U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and -U4 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U10-Pad2_ d_nand -U11 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U11-Pad3_ d_and -U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor -X2 Net-_U19-Pad3_ Net-_X12-Pad4_ Net-_X2-Pad3_ Net-_X2-Pad4_ Net-_X10-Pad6_ Net-_X11-Pad6_ Net-_U1-Pad12_ c_gate -X1 Net-_X1-Pad1_ Net-_X1-Pad2_ Net-_X1-Pad3_ Net-_X1-Pad4_ Net-_X1-Pad5_ Net-_U18-Pad3_ Net-_U1-Pad14_ c_gate -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT - -.end diff --git a/src/SubcircuitLibrary/7485/7485.cir.out b/src/SubcircuitLibrary/7485/7485.cir.out deleted file mode 100644 index afc7b865..00000000 --- a/src/SubcircuitLibrary/7485/7485.cir.out +++ /dev/null @@ -1,101 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir - -.include 4_and.sub -.include 3_and.sub -.include 5_and.sub -.include c_gate.sub -* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand -* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and -* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor -* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and -x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and -x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and -x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and -x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and -x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and -x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and -* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and -x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and -x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and -x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and -x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and -x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and -* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and -* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand -* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and -* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor -* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and -* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand -* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and -* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor -* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and -* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand -* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and -* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor -x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port -a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 -a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 -a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 -a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 -a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 -a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 -a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 -a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 -a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 -a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 -a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 -a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 -a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 -a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 -a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 -a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 -a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 -a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/7485/7485.pro b/src/SubcircuitLibrary/7485/7485.pro deleted file mode 100644 index 8fb4abb4..00000000 --- a/src/SubcircuitLibrary/7485/7485.pro +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 19:27:48 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_User -LibName25=eSim_Subckt diff --git a/src/SubcircuitLibrary/7485/7485.sch b/src/SubcircuitLibrary/7485/7485.sch deleted file mode 100644 index 0db5f0d6..00000000 --- a/src/SubcircuitLibrary/7485/7485.sch +++ /dev/null @@ -1,1127 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:7485-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U6 -U 1 1 5C9A2432 -P 3150 1200 -F 0 "U6" H 3150 1200 60 0000 C CNN -F 1 "d_and" H 3200 1300 60 0000 C CNN -F 2 "" H 3150 1200 60 0000 C CNN -F 3 "" H 3150 1200 60 0000 C CNN - 1 3150 1200 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U2 -U 1 1 5C9A246F -P 2100 1450 -F 0 "U2" H 2100 1450 60 0000 C CNN -F 1 "d_nand" H 2150 1550 60 0000 C CNN -F 2 "" H 2100 1450 60 0000 C CNN -F 3 "" H 2100 1450 60 0000 C CNN - 1 2100 1450 - 1 0 0 -1 -$EndComp -$Comp -L d_and U7 -U 1 1 5C9A24BA -P 3150 1600 -F 0 "U7" H 3150 1600 60 0000 C CNN -F 1 "d_and" H 3200 1700 60 0000 C CNN -F 2 "" H 3150 1600 60 0000 C CNN -F 3 "" H 3150 1600 60 0000 C CNN - 1 3150 1600 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U14 -U 1 1 5C9A252F -P 4050 1400 -F 0 "U14" H 4050 1400 60 0000 C CNN -F 1 "d_nor" H 4100 1500 60 0000 C CNN -F 2 "" H 4050 1400 60 0000 C CNN -F 3 "" H 4050 1400 60 0000 C CNN - 1 4050 1400 - 1 0 0 -1 -$EndComp -$Comp -L d_and U19 -U 1 1 5C9A2580 -P 6900 1000 -F 0 "U19" H 6900 1000 60 0000 C CNN -F 1 "d_and" H 6950 1100 60 0000 C CNN -F 2 "" H 6900 1000 60 0000 C CNN -F 3 "" H 6900 1000 60 0000 C CNN - 1 6900 1000 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X12 -U 1 1 5C9A2DC4 -P 6050 1650 -F 0 "X12" H 6950 1950 60 0000 C CNN -F 1 "3_and" H 7000 2150 60 0000 C CNN -F 2 "" H 6050 1650 60 0000 C CNN -F 3 "" H 6050 1650 60 0000 C CNN - 1 6050 1650 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X7 -U 1 1 5C9A2EB7 -P 5450 2750 -F 0 "X7" H 6950 3800 60 0000 C CNN -F 1 "4_and" H 7000 3950 60 0000 C CNN -F 2 "" H 5450 2750 60 0000 C CNN -F 3 "" H 5450 2750 60 0000 C CNN - 1 5450 2750 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X9 -U 1 1 5C9A2F2E -P 5650 3050 -F 0 "X9" H 7000 3850 60 0000 C CNN -F 1 "5_and" H 7050 4100 60 0000 C CNN -F 2 "" H 5650 3050 60 0000 C CNN -F 3 "" H 5650 3050 60 0000 C CNN - 1 5650 3050 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X10 -U 1 1 5C9A2F95 -P 5650 3600 -F 0 "X10" H 7000 4400 60 0000 C CNN -F 1 "5_and" H 7050 4650 60 0000 C CNN -F 2 "" H 5650 3600 60 0000 C CNN -F 3 "" H 5650 3600 60 0000 C CNN - 1 5650 3600 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X11 -U 1 1 5C9A3164 -P 5650 4150 -F 0 "X11" H 7000 4950 60 0000 C CNN -F 1 "5_and" H 7050 5200 60 0000 C CNN -F 2 "" H 5650 4150 60 0000 C CNN -F 3 "" H 5650 4150 60 0000 C CNN - 1 5650 4150 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X13 -U 1 1 5C9A31B3 -P 7550 4850 -F 0 "X13" H 8900 5650 60 0000 C CNN -F 1 "5_and" H 8950 5900 60 0000 C CNN -F 2 "" H 7550 4850 60 0000 C CNN -F 3 "" H 7550 4850 60 0000 C CNN - 1 7550 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_and U18 -U 1 1 5C9A32FD -P 6350 6900 -F 0 "U18" H 6350 6900 60 0000 C CNN -F 1 "d_and" H 6400 7000 60 0000 C CNN -F 2 "" H 6350 6900 60 0000 C CNN -F 3 "" H 6350 6900 60 0000 C CNN - 1 6350 6900 - 1 0 0 1 -$EndComp -$Comp -L 3_and X8 -U 1 1 5C9A3303 -P 5500 6250 -F 0 "X8" H 6400 6550 60 0000 C CNN -F 1 "3_and" H 6450 6750 60 0000 C CNN -F 2 "" H 5500 6250 60 0000 C CNN -F 3 "" H 5500 6250 60 0000 C CNN - 1 5500 6250 - 1 0 0 1 -$EndComp -$Comp -L 4_and X3 -U 1 1 5C9A3309 -P 4900 5150 -F 0 "X3" H 6400 6200 60 0000 C CNN -F 1 "4_and" H 6450 6350 60 0000 C CNN -F 2 "" H 4900 5150 60 0000 C CNN -F 3 "" H 4900 5150 60 0000 C CNN - 1 4900 5150 - 1 0 0 1 -$EndComp -$Comp -L 5_and X6 -U 1 1 5C9A330F -P 5100 4850 -F 0 "X6" H 6450 5650 60 0000 C CNN -F 1 "5_and" H 6500 5900 60 0000 C CNN -F 2 "" H 5100 4850 60 0000 C CNN -F 3 "" H 5100 4850 60 0000 C CNN - 1 5100 4850 - 1 0 0 1 -$EndComp -$Comp -L 5_and X5 -U 1 1 5C9A3315 -P 5100 4300 -F 0 "X5" H 6450 5100 60 0000 C CNN -F 1 "5_and" H 6500 5350 60 0000 C CNN -F 2 "" H 5100 4300 60 0000 C CNN -F 3 "" H 5100 4300 60 0000 C CNN - 1 5100 4300 - 1 0 0 1 -$EndComp -$Comp -L 5_and X4 -U 1 1 5C9A331B -P 5100 3750 -F 0 "X4" H 6450 4550 60 0000 C CNN -F 1 "5_and" H 6500 4800 60 0000 C CNN -F 2 "" H 5100 3750 60 0000 C CNN -F 3 "" H 5100 3750 60 0000 C CNN - 1 5100 3750 - 1 0 0 1 -$EndComp -$Comp -L d_and U8 -U 1 1 5C9A39D8 -P 3250 2600 -F 0 "U8" H 3250 2600 60 0000 C CNN -F 1 "d_and" H 3300 2700 60 0000 C CNN -F 2 "" H 3250 2600 60 0000 C CNN -F 3 "" H 3250 2600 60 0000 C CNN - 1 3250 2600 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U3 -U 1 1 5C9A39DE -P 2200 2850 -F 0 "U3" H 2200 2850 60 0000 C CNN -F 1 "d_nand" H 2250 2950 60 0000 C CNN -F 2 "" H 2200 2850 60 0000 C CNN -F 3 "" H 2200 2850 60 0000 C CNN - 1 2200 2850 - 1 0 0 -1 -$EndComp -$Comp -L d_and U9 -U 1 1 5C9A39E4 -P 3250 3000 -F 0 "U9" H 3250 3000 60 0000 C CNN -F 1 "d_and" H 3300 3100 60 0000 C CNN -F 2 "" H 3250 3000 60 0000 C CNN -F 3 "" H 3250 3000 60 0000 C CNN - 1 3250 3000 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U15 -U 1 1 5C9A39EA -P 4150 2800 -F 0 "U15" H 4150 2800 60 0000 C CNN -F 1 "d_nor" H 4200 2900 60 0000 C CNN -F 2 "" H 4150 2800 60 0000 C CNN -F 3 "" H 4150 2800 60 0000 C CNN - 1 4150 2800 - 1 0 0 -1 -$EndComp -$Comp -L d_and U12 -U 1 1 5C9A3B56 -P 3600 4950 -F 0 "U12" H 3600 4950 60 0000 C CNN -F 1 "d_and" H 3650 5050 60 0000 C CNN -F 2 "" H 3600 4950 60 0000 C CNN -F 3 "" H 3600 4950 60 0000 C CNN - 1 3600 4950 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U5 -U 1 1 5C9A3B5C -P 2550 5200 -F 0 "U5" H 2550 5200 60 0000 C CNN -F 1 "d_nand" H 2600 5300 60 0000 C CNN -F 2 "" H 2550 5200 60 0000 C CNN -F 3 "" H 2550 5200 60 0000 C CNN - 1 2550 5200 - 1 0 0 -1 -$EndComp -$Comp -L d_and U13 -U 1 1 5C9A3B62 -P 3600 5350 -F 0 "U13" H 3600 5350 60 0000 C CNN -F 1 "d_and" H 3650 5450 60 0000 C CNN -F 2 "" H 3600 5350 60 0000 C CNN -F 3 "" H 3600 5350 60 0000 C CNN - 1 3600 5350 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U17 -U 1 1 5C9A3B68 -P 4500 5150 -F 0 "U17" H 4500 5150 60 0000 C CNN -F 1 "d_nor" H 4550 5250 60 0000 C CNN -F 2 "" H 4500 5150 60 0000 C CNN -F 3 "" H 4500 5150 60 0000 C CNN - 1 4500 5150 - 1 0 0 -1 -$EndComp -$Comp -L d_and U10 -U 1 1 5C9A3C6D -P 3400 3750 -F 0 "U10" H 3400 3750 60 0000 C CNN -F 1 "d_and" H 3450 3850 60 0000 C CNN -F 2 "" H 3400 3750 60 0000 C CNN -F 3 "" H 3400 3750 60 0000 C CNN - 1 3400 3750 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U4 -U 1 1 5C9A3C73 -P 2350 4000 -F 0 "U4" H 2350 4000 60 0000 C CNN -F 1 "d_nand" H 2400 4100 60 0000 C CNN -F 2 "" H 2350 4000 60 0000 C CNN -F 3 "" H 2350 4000 60 0000 C CNN - 1 2350 4000 - 1 0 0 -1 -$EndComp -$Comp -L d_and U11 -U 1 1 5C9A3C79 -P 3400 4150 -F 0 "U11" H 3400 4150 60 0000 C CNN -F 1 "d_and" H 3450 4250 60 0000 C CNN -F 2 "" H 3400 4150 60 0000 C CNN -F 3 "" H 3400 4150 60 0000 C CNN - 1 3400 4150 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U16 -U 1 1 5C9A3C7F -P 4300 3950 -F 0 "U16" H 4300 3950 60 0000 C CNN -F 1 "d_nor" H 4350 4050 60 0000 C CNN -F 2 "" H 4300 3950 60 0000 C CNN -F 3 "" H 4300 3950 60 0000 C CNN - 1 4300 3950 - 1 0 0 -1 -$EndComp -$Comp -L c_gate X2 -U 1 1 5C9A4498 -P 3050 6600 -F 0 "X2" H 3100 6650 60 0000 C CNN -F 1 "c_gate" H 9000 11300 60 0000 C CNN -F 2 "" H 3050 6600 60 0000 C CNN -F 3 "" H 3050 6600 60 0000 C CNN - 1 3050 6600 - 1 0 0 -1 -$EndComp -$Comp -L c_gate X1 -U 1 1 5C9A465F -P 2850 10000 -F 0 "X1" H 2900 10050 60 0000 C CNN -F 1 "c_gate" H 8800 14700 60 0000 C CNN -F 2 "" H 2850 10000 60 0000 C CNN -F 3 "" H 2850 10000 60 0000 C CNN - 1 2850 10000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3600 1300 3600 1150 -Wire Wire Line - 3600 1400 3600 1550 -Wire Wire Line - 2700 1000 2700 1200 -Wire Wire Line - 2700 1200 2700 1400 -Wire Wire Line - 2700 1400 2700 1500 -Wire Wire Line - 2700 1500 2700 4700 -Wire Wire Line - 2700 1600 1550 1600 -Wire Wire Line - 1550 1600 1550 1450 -Wire Wire Line - 1100 1450 1500 1450 -Wire Wire Line - 1500 1450 1550 1450 -Wire Wire Line - 1550 1450 1650 1450 -Wire Wire Line - 1100 1350 1400 1350 -Wire Wire Line - 1400 1350 1550 1350 -Wire Wire Line - 1550 1350 1650 1350 -Wire Wire Line - 1550 1350 1550 1100 -Wire Wire Line - 1550 1100 2700 1100 -Wire Wire Line - 2550 1400 2700 1400 -Connection ~ 2700 1400 -Connection ~ 1550 1350 -Connection ~ 1550 1450 -Wire Wire Line - 3700 2700 3700 2550 -Wire Wire Line - 3700 2800 3700 2950 -Wire Wire Line - 2800 2000 2800 2600 -Wire Wire Line - 2800 2600 2800 2800 -Wire Wire Line - 2800 2800 2800 2900 -Wire Wire Line - 2800 2900 2800 4600 -Wire Wire Line - 2800 3000 1650 3000 -Wire Wire Line - 1650 3000 1650 2850 -Wire Wire Line - 1200 2850 1600 2850 -Wire Wire Line - 1600 2850 1650 2850 -Wire Wire Line - 1650 2850 1750 2850 -Wire Wire Line - 1200 2750 1450 2750 -Wire Wire Line - 1450 2750 1650 2750 -Wire Wire Line - 1650 2750 1750 2750 -Wire Wire Line - 1650 2750 1650 2500 -Wire Wire Line - 1650 2500 2800 2500 -Wire Wire Line - 2650 2800 2800 2800 -Connection ~ 2800 2800 -Connection ~ 1650 2750 -Connection ~ 1650 2850 -Wire Wire Line - 4050 5050 4050 4900 -Wire Wire Line - 4050 5150 4050 5300 -Wire Wire Line - 3150 4950 3150 5000 -Wire Wire Line - 3150 5000 3150 5150 -Wire Wire Line - 3150 5150 3150 5250 -Wire Wire Line - 3150 5250 3150 5850 -Wire Wire Line - 3150 5350 2000 5350 -Wire Wire Line - 2000 5350 2000 5200 -Wire Wire Line - 1250 5200 1500 5200 -Wire Wire Line - 1500 5200 2000 5200 -Wire Wire Line - 2000 5200 2100 5200 -Wire Wire Line - 1250 5100 1800 5100 -Wire Wire Line - 1800 5100 2000 5100 -Wire Wire Line - 2000 5100 2100 5100 -Wire Wire Line - 2000 5100 2000 4850 -Wire Wire Line - 2000 4850 3150 4850 -Wire Wire Line - 3000 5150 3150 5150 -Connection ~ 3150 5150 -Connection ~ 2000 5100 -Connection ~ 2000 5200 -Wire Wire Line - 3850 3850 3850 3700 -Wire Wire Line - 3850 3950 3850 4100 -Wire Wire Line - 2950 3200 2950 3750 -Wire Wire Line - 2950 3750 2950 3950 -Wire Wire Line - 2950 3950 2950 4050 -Wire Wire Line - 2950 4050 2950 4350 -Wire Wire Line - 2950 4150 1800 4150 -Wire Wire Line - 1800 4150 1800 4000 -Wire Wire Line - 1350 4000 1750 4000 -Wire Wire Line - 1750 4000 1800 4000 -Wire Wire Line - 1800 4000 1900 4000 -Wire Wire Line - 1200 3900 1600 3900 -Wire Wire Line - 1600 3900 1800 3900 -Wire Wire Line - 1800 3900 1900 3900 -Wire Wire Line - 1800 3900 1800 3650 -Wire Wire Line - 1800 3650 2950 3650 -Wire Wire Line - 2800 3950 2950 3950 -Connection ~ 2950 3950 -Connection ~ 1800 3900 -Connection ~ 1800 4000 -Wire Wire Line - 1400 1350 1400 7000 -Wire Wire Line - 1400 7000 5900 7000 -Connection ~ 1400 1350 -Wire Wire Line - 1250 5200 1250 5300 -Wire Wire Line - 5900 6900 2900 6900 -Wire Wire Line - 2900 6900 2900 4700 -Wire Wire Line - 2900 4700 2700 4700 -Connection ~ 2700 1500 -Wire Wire Line - 5950 6750 1450 6750 -Wire Wire Line - 1450 6750 1450 2750 -Connection ~ 1450 2750 -Wire Wire Line - 5950 6650 2950 6650 -Wire Wire Line - 2950 6650 2950 4600 -Wire Wire Line - 2950 4600 2800 4600 -Connection ~ 2800 2900 -Wire Wire Line - 5100 6550 5950 6550 -Wire Wire Line - 5100 1350 5100 1700 -Wire Wire Line - 5100 1700 5100 2150 -Wire Wire Line - 5100 2150 5100 2500 -Wire Wire Line - 5100 2500 5100 3050 -Wire Wire Line - 5100 3050 5100 3750 -Wire Wire Line - 5100 3750 5100 4850 -Wire Wire Line - 5100 4850 5100 5400 -Wire Wire Line - 5100 5400 5100 5750 -Wire Wire Line - 5100 5750 5100 6300 -Wire Wire Line - 5100 6300 5100 6550 -Wire Wire Line - 4500 1350 5100 1350 -Wire Wire Line - 5100 1350 6500 1350 -Wire Wire Line - 1500 1450 1500 900 -Wire Wire Line - 1500 900 6450 900 -Connection ~ 1500 1450 -Wire Wire Line - 2700 1000 6450 1000 -Connection ~ 2700 1200 -Wire Wire Line - 6500 1150 4500 1150 -Wire Wire Line - 4500 1150 4500 1900 -Wire Wire Line - 4500 1900 1600 1900 -Wire Wire Line - 1600 1900 1600 2850 -Connection ~ 1600 2850 -Wire Wire Line - 6500 1250 4550 1250 -Wire Wire Line - 4550 1250 4550 2000 -Wire Wire Line - 4550 2000 2800 2000 -Connection ~ 2800 2600 -Connection ~ 5100 1350 -Wire Wire Line - 6500 1500 4600 1500 -Wire Wire Line - 4600 1500 4600 2100 -Wire Wire Line - 4600 2100 1750 2100 -Wire Wire Line - 1750 2100 1750 4000 -Connection ~ 1750 4000 -Wire Wire Line - 6500 1600 4650 1600 -Wire Wire Line - 4650 1600 4650 3200 -Wire Wire Line - 4650 3200 2950 3200 -Connection ~ 2950 3750 -Wire Wire Line - 6500 1700 5100 1700 -Connection ~ 5100 1700 -Wire Wire Line - 6500 1800 5250 1800 -Wire Wire Line - 5250 1800 5250 2250 -Wire Wire Line - 5250 2250 5250 2600 -Wire Wire Line - 5250 2600 5250 2750 -Wire Wire Line - 5250 2750 5250 3150 -Wire Wire Line - 5250 3150 5250 3850 -Wire Wire Line - 5250 3850 5250 4750 -Wire Wire Line - 5250 4750 5250 5300 -Wire Wire Line - 5250 5300 5250 5650 -Wire Wire Line - 5250 5650 5250 6100 -Wire Wire Line - 5250 2750 4600 2750 -Wire Wire Line - 6500 1950 1500 1950 -Wire Wire Line - 1500 1950 1500 5200 -Connection ~ 1500 5200 -Wire Wire Line - 6500 2050 4950 2050 -Wire Wire Line - 4950 2050 4950 4300 -Wire Wire Line - 4950 4300 3150 4300 -Wire Wire Line - 3150 4300 3150 5000 -Connection ~ 3150 5000 -Wire Wire Line - 6500 2150 5100 2150 -Connection ~ 5100 2150 -Wire Wire Line - 6500 2250 5250 2250 -Connection ~ 5250 2250 -Wire Wire Line - 6500 2350 5350 2350 -Wire Wire Line - 5350 2350 5350 2700 -Wire Wire Line - 5350 2700 5350 3200 -Wire Wire Line - 5350 3200 5350 3900 -Wire Wire Line - 5350 3900 5350 4050 -Wire Wire Line - 5350 4050 5350 4650 -Wire Wire Line - 5350 4650 5350 5200 -Wire Wire Line - 5350 5200 5350 5550 -Wire Wire Line - 5350 3900 4750 3900 -Wire Wire Line - 6500 2500 5100 2500 -Connection ~ 5100 2500 -Wire Wire Line - 6500 2600 5250 2600 -Connection ~ 5250 2600 -Wire Wire Line - 6500 2700 5350 2700 -Connection ~ 5350 2700 -Wire Wire Line - 6500 2800 5450 2800 -Wire Wire Line - 5450 2800 5450 3350 -Wire Wire Line - 5450 3350 5450 4150 -Wire Wire Line - 5450 4150 5450 4550 -Wire Wire Line - 5450 4550 5450 5100 -Wire Wire Line - 4950 5100 5450 5100 -Wire Wire Line - 5450 5100 5950 5100 -Wire Wire Line - 6500 2900 5550 2900 -Wire Wire Line - 5550 2900 5550 3250 -Wire Wire Line - 5550 3250 1050 3250 -Wire Wire Line - 6500 3050 5100 3050 -Connection ~ 5100 3050 -Wire Wire Line - 5250 3150 6500 3150 -Connection ~ 5250 2750 -Wire Wire Line - 6500 3250 5700 3250 -Wire Wire Line - 5700 3250 5700 3200 -Wire Wire Line - 5700 3200 5350 3200 -Connection ~ 5350 3200 -Wire Wire Line - 6500 3350 5450 3350 -Connection ~ 5450 3350 -Wire Wire Line - 4800 3450 5950 3450 -Wire Wire Line - 5950 3450 6500 3450 -Wire Wire Line - 4800 3450 4800 3400 -Wire Wire Line - 4800 3400 2600 3400 -Wire Wire Line - 2050 3400 1050 3400 -Wire Wire Line - 5950 3450 5950 3950 -Wire Wire Line - 5950 3950 5950 4450 -Connection ~ 5950 3450 -Wire Wire Line - 5950 4550 5450 4550 -Connection ~ 5450 4550 -Wire Wire Line - 5350 4650 5950 4650 -Connection ~ 5350 3900 -Wire Wire Line - 5250 4750 5950 4750 -Connection ~ 5250 3150 -Wire Wire Line - 5950 4850 5100 4850 -Connection ~ 5100 4850 -Wire Wire Line - 5950 5400 5100 5400 -Connection ~ 5100 5400 -Wire Wire Line - 5950 5750 5100 5750 -Connection ~ 5100 5750 -Wire Wire Line - 5950 5000 4800 5000 -Wire Wire Line - 4800 5000 4800 3550 -Wire Wire Line - 4800 3550 1050 3550 -Connection ~ 5450 5100 -Wire Wire Line - 5350 5200 5950 5200 -Connection ~ 5350 4650 -Wire Wire Line - 5250 5300 5950 5300 -Connection ~ 5250 4750 -Wire Wire Line - 5950 5950 1800 5950 -Wire Wire Line - 1800 5950 1800 5100 -Connection ~ 1800 5100 -Wire Wire Line - 5950 6400 1600 6400 -Wire Wire Line - 1600 6400 1600 3900 -Connection ~ 1600 3900 -Wire Wire Line - 5950 6300 5100 6300 -Connection ~ 5100 6300 -Wire Wire Line - 5350 5550 5950 5550 -Connection ~ 5350 5200 -Wire Wire Line - 5250 5650 5950 5650 -Connection ~ 5250 5300 -Wire Wire Line - 3150 5850 5950 5850 -Connection ~ 3150 5250 -Wire Wire Line - 5250 6100 5950 6100 -Connection ~ 5250 5650 -Wire Wire Line - 5950 6200 3000 6200 -Wire Wire Line - 3000 6200 3000 4350 -Wire Wire Line - 3000 4350 2950 4350 -Connection ~ 2950 4050 -Wire Wire Line - 8400 3950 5950 3950 -Connection ~ 5950 3950 -Wire Wire Line - 8400 3750 5100 3750 -Connection ~ 5100 3750 -Wire Wire Line - 8400 3850 5250 3850 -Connection ~ 5250 3850 -Wire Wire Line - 8400 4050 5350 4050 -Connection ~ 5350 4050 -Wire Wire Line - 8400 4150 5450 4150 -Connection ~ 5450 4150 -Wire Wire Line - 8400 1800 8400 950 -Wire Wire Line - 8400 950 7350 950 -Wire Wire Line - 8400 1900 8200 1900 -Wire Wire Line - 8200 1900 8200 1250 -Wire Wire Line - 8200 1250 7350 1250 -Wire Wire Line - 8400 2000 8050 2000 -Wire Wire Line - 8050 2000 8050 1650 -Wire Wire Line - 8050 1650 7400 1650 -Wire Wire Line - 7500 2150 7800 2150 -Wire Wire Line - 7800 2150 7800 2100 -Wire Wire Line - 7800 2100 8400 2100 -Wire Wire Line - 8400 2200 7900 2200 -Wire Wire Line - 7900 2200 7900 2700 -Wire Wire Line - 7900 2700 7500 2700 -Wire Wire Line - 7500 3250 8050 3250 -Wire Wire Line - 8050 3250 8050 2300 -Wire Wire Line - 8050 2300 8400 2300 -Wire Wire Line - 8200 5200 8200 4650 -Wire Wire Line - 8200 4650 6950 4650 -Wire Wire Line - 8200 5300 8050 5300 -Wire Wire Line - 8050 5300 8050 5200 -Wire Wire Line - 8050 5200 6950 5200 -Wire Wire Line - 8200 5400 7250 5400 -Wire Wire Line - 7250 5400 7250 5750 -Wire Wire Line - 7250 5750 6950 5750 -Wire Wire Line - 6850 6250 6850 5850 -Wire Wire Line - 6850 5850 7350 5850 -Wire Wire Line - 7350 5850 7350 5500 -Wire Wire Line - 7350 5500 8200 5500 -Wire Wire Line - 6800 6950 6950 6950 -Wire Wire Line - 6950 6950 6950 6200 -Wire Wire Line - 6950 6200 7950 6200 -Wire Wire Line - 7950 6200 7950 5700 -Wire Wire Line - 7950 5700 8200 5700 -$Comp -L PORT U1 -U 4 1 5C9A8539 -P 850 1350 -F 0 "U1" H 900 1450 30 0000 C CNN -F 1 "PORT" H 850 1350 30 0000 C CNN -F 2 "" H 850 1350 60 0000 C CNN -F 3 "" H 850 1350 60 0000 C CNN - 4 850 1350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A8668 -P 850 1550 -F 0 "U1" H 900 1650 30 0000 C CNN -F 1 "PORT" H 850 1550 30 0000 C CNN -F 2 "" H 850 1550 60 0000 C CNN -F 3 "" H 850 1550 60 0000 C CNN - 5 850 1550 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1100 1550 1100 1450 -$Comp -L PORT U1 -U 6 1 5C9A8815 -P 950 2650 -F 0 "U1" H 1000 2750 30 0000 C CNN -F 1 "PORT" H 950 2650 30 0000 C CNN -F 2 "" H 950 2650 60 0000 C CNN -F 3 "" H 950 2650 60 0000 C CNN - 6 950 2650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1200 2650 1200 2750 -$Comp -L PORT U1 -U 7 1 5C9A8B82 -P 950 2850 -F 0 "U1" H 1000 2950 30 0000 C CNN -F 1 "PORT" H 950 2850 30 0000 C CNN -F 2 "" H 950 2850 60 0000 C CNN -F 3 "" H 950 2850 60 0000 C CNN - 7 950 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5C9A8C46 -P 950 3900 -F 0 "U1" H 1000 4000 30 0000 C CNN -F 1 "PORT" H 950 3900 30 0000 C CNN -F 2 "" H 950 3900 60 0000 C CNN -F 3 "" H 950 3900 60 0000 C CNN - 8 950 3900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C9A8D2C -P 950 4100 -F 0 "U1" H 1000 4200 30 0000 C CNN -F 1 "PORT" H 950 4100 30 0000 C CNN -F 2 "" H 950 4100 60 0000 C CNN -F 3 "" H 950 4100 60 0000 C CNN - 9 950 4100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C9A8DBD -P 1000 5100 -F 0 "U1" H 1050 5200 30 0000 C CNN -F 1 "PORT" H 1000 5100 30 0000 C CNN -F 2 "" H 1000 5100 60 0000 C CNN -F 3 "" H 1000 5100 60 0000 C CNN - 10 1000 5100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C9A8E65 -P 1000 5300 -F 0 "U1" H 1050 5400 30 0000 C CNN -F 1 "PORT" H 1000 5300 30 0000 C CNN -F 2 "" H 1000 5300 60 0000 C CNN -F 3 "" H 1000 5300 60 0000 C CNN - 11 1000 5300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A8EEE -P 800 3150 -F 0 "U1" H 850 3250 30 0000 C CNN -F 1 "PORT" H 800 3150 30 0000 C CNN -F 2 "" H 800 3150 60 0000 C CNN -F 3 "" H 800 3150 60 0000 C CNN - 1 800 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A8F9C -P 800 3400 -F 0 "U1" H 850 3500 30 0000 C CNN -F 1 "PORT" H 800 3400 30 0000 C CNN -F 2 "" H 800 3400 60 0000 C CNN -F 3 "" H 800 3400 60 0000 C CNN - 2 800 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A9031 -P 800 3600 -F 0 "U1" H 850 3700 30 0000 C CNN -F 1 "PORT" H 800 3600 30 0000 C CNN -F 2 "" H 800 3600 60 0000 C CNN -F 3 "" H 800 3600 60 0000 C CNN - 3 800 3600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1050 3250 1050 3150 -Wire Wire Line - 1050 3550 1050 3600 -Wire Wire Line - 1350 4000 1350 4100 -Wire Wire Line - 1350 4100 1200 4100 -Wire Wire Line - 9550 2050 9850 2050 -Wire Wire Line - 9400 3950 9850 3950 -Wire Wire Line - 9350 5450 9900 5450 -$Comp -L PORT U1 -U 12 1 5C9A9B26 -P 10100 2050 -F 0 "U1" H 10150 2150 30 0000 C CNN -F 1 "PORT" H 10100 2050 30 0000 C CNN -F 2 "" H 10100 2050 60 0000 C CNN -F 3 "" H 10100 2050 60 0000 C CNN - 12 10100 2050 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 13 1 5C9A9BCA -P 10100 3950 -F 0 "U1" H 10150 4050 30 0000 C CNN -F 1 "PORT" H 10100 3950 30 0000 C CNN -F 2 "" H 10100 3950 60 0000 C CNN -F 3 "" H 10100 3950 60 0000 C CNN - 13 10100 3950 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5C9A9CA0 -P 10150 5450 -F 0 "U1" H 10200 5550 30 0000 C CNN -F 1 "PORT" H 10150 5450 30 0000 C CNN -F 2 "" H 10150 5450 60 0000 C CNN -F 3 "" H 10150 5450 60 0000 C CNN - 14 10150 5450 - -1 0 0 1 -$EndComp -Text Notes 9650 2000 0 60 ~ 12 -A>B -Text Notes 9600 3900 0 60 ~ 12 -A=B\n -Text Notes 9600 5400 0 60 ~ 12 -A<B\n -Text Notes 1250 5100 0 60 ~ 12 -A0 -Text Notes 1200 5400 0 60 ~ 12 -B0 -Text Notes 1300 3900 2 60 ~ 12 -A1 -Text Notes 1300 4200 2 60 ~ 12 -B1 -Text Notes 1250 3250 2 60 ~ 12 -A<B -Text Notes 1250 3400 2 60 ~ 12 -A=B -Text Notes 1250 3550 2 60 ~ 12 -A>B -Text Notes 1350 2750 2 60 ~ 12 -A2 -Text Notes 1350 2950 2 60 ~ 12 -B2 -Text Notes 1300 1350 2 60 ~ 12 -A3 -Text Notes 1300 1550 2 60 ~ 12 -B3 -Wire Wire Line - 8200 5600 7450 5600 -Wire Wire Line - 7450 5600 7450 6050 -Wire Wire Line - 7450 6050 6900 6050 -Wire Wire Line - 6800 6650 6800 6300 -Wire Wire Line - 6800 6300 6900 6300 -Wire Wire Line - 6900 6300 6900 6050 -Wire Notes Line - 500 3000 1350 3000 -Wire Notes Line - 1350 3000 1350 3750 -Wire Notes Line - 1350 3750 500 3750 -Wire Notes Line - 500 3750 500 3000 -Text Notes 600 3000 3 60 ~ 12 -Cascading Inputs -Wire Notes Line - 9500 1550 9500 6050 -Wire Notes Line - 9500 6050 10550 6050 -Wire Notes Line - 10550 6050 10550 1550 -Wire Notes Line - 10550 1550 9500 1550 -Text Notes 9900 3400 0 60 ~ 12 -Outputs -Wire Wire Line - 2600 3400 2050 3400 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/7485.sub b/src/SubcircuitLibrary/7485/7485.sub deleted file mode 100644 index 5a45c57c..00000000 --- a/src/SubcircuitLibrary/7485/7485.sub +++ /dev/null @@ -1,95 +0,0 @@ -* Subcircuit 7485 -.subckt 7485 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ -* c:\users\malli\esim\src\subcircuitlibrary\7485\7485.cir -.include 4_and.sub -.include 3_and.sub -.include 5_and.sub -.include c_gate.sub -* u6 net-_u1-pad4_ net-_u18-pad2_ net-_u14-pad1_ d_and -* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad2_ d_nand -* u7 net-_u18-pad2_ net-_u1-pad5_ net-_u14-pad2_ d_and -* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor -* u19 net-_u1-pad5_ net-_u18-pad2_ net-_u19-pad3_ d_and -x12 net-_u1-pad7_ net-_u3-pad3_ net-_u14-pad3_ net-_x12-pad4_ 3_and -x7 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_x2-pad3_ 4_and -x9 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x2-pad4_ 5_and -x10 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad1_ net-_x10-pad6_ 5_and -x11 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x11-pad6_ 5_and -x13 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad2_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and -* u18 net-_u1-pad4_ net-_u18-pad2_ net-_u18-pad3_ d_and -x8 net-_u1-pad6_ net-_u3-pad3_ net-_u14-pad3_ net-_x1-pad5_ 3_and -x3 net-_u1-pad8_ net-_u14-pad3_ net-_u10-pad2_ net-_u15-pad3_ net-_x1-pad4_ 4_and -x6 net-_u1-pad10_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_x1-pad3_ 5_and -x5 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad3_ net-_x1-pad2_ 5_and -x4 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad2_ net-_x1-pad1_ 5_and -* u8 net-_u1-pad6_ net-_u3-pad3_ net-_u15-pad1_ d_and -* u3 net-_u1-pad6_ net-_u1-pad7_ net-_u3-pad3_ d_nand -* u9 net-_u3-pad3_ net-_u1-pad7_ net-_u15-pad2_ d_and -* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor -* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and -* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand -* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and -* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor -* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and -* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand -* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and -* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor -x2 net-_u19-pad3_ net-_x12-pad4_ net-_x2-pad3_ net-_x2-pad4_ net-_x10-pad6_ net-_x11-pad6_ net-_u1-pad12_ c_gate -x1 net-_x1-pad1_ net-_x1-pad2_ net-_x1-pad3_ net-_x1-pad4_ net-_x1-pad5_ net-_u18-pad3_ net-_u1-pad14_ c_gate -a1 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u14-pad1_ u6 -a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad2_ u2 -a3 [net-_u18-pad2_ net-_u1-pad5_ ] net-_u14-pad2_ u7 -a4 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 -a5 [net-_u1-pad5_ net-_u18-pad2_ ] net-_u19-pad3_ u19 -a6 [net-_u1-pad4_ net-_u18-pad2_ ] net-_u18-pad3_ u18 -a7 [net-_u1-pad6_ net-_u3-pad3_ ] net-_u15-pad1_ u8 -a8 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u3-pad3_ u3 -a9 [net-_u3-pad3_ net-_u1-pad7_ ] net-_u15-pad2_ u9 -a10 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 -a11 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 -a12 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 -a13 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 -a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 -a15 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 -a16 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 -a17 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 -a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 -* Schematic Name: d_and, NgSpice Name: d_and -.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u2 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u14 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u3 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u9 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u15 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u12 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u5 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u17 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nand, NgSpice Name: d_nand -.model u4 d_nand(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u11 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_nor, NgSpice Name: d_nor -.model u16 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 7485
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml b/src/SubcircuitLibrary/7485/7485_Previous_Values.xml deleted file mode 100644 index 6d8f93b6..00000000 --- a/src/SubcircuitLibrary/7485/7485_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u6 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u6><u2 name="type">d_nand<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u7 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u7><u14 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u14><u19 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u19><u18 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u3 name="type">d_nand<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u3><u9 name="type">d_and<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u9><u15 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u15><u12 name="type">d_and<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u12><u5 name="type">d_nand<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u5><u13 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u13><u17 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u10 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u10><u4 name="type">d_nand<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u4><u11 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u11><u16 name="type">d_nor<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u16></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x1><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate</field></x2><x8><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x8><x9><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x9><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x3><x10><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x10><x11><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x11><x12><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x12><x13><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x13><x6><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x6><x7><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4_and</field></x7><x4><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x4><x5><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/7485mod-cache.lib b/src/SubcircuitLibrary/7485/7485mod-cache.lib deleted file mode 100644 index 6edb5033..00000000 --- a/src/SubcircuitLibrary/7485/7485mod-cache.lib +++ /dev/null @@ -1,175 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 900 300 60 H V C CNN -F1 "3_and" 950 500 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 -P 2 0 1 0 650 550 1000 550 N -P 3 0 1 0 650 550 650 250 1000 250 N -X in1 1 450 500 200 R 50 50 1 1 I -X in2 2 450 400 200 R 50 50 1 1 I -X in3 3 450 300 200 R 50 50 1 1 I -X out 4 1300 400 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 4_and -# -DEF 4_and X 0 40 Y Y 1 F N -F0 "X" 1500 1050 60 H V C CNN -F1 "4_and" 1550 1200 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 1550 1100 206 760 -760 0 1 0 N 1600 1300 1600 900 -P 2 0 1 0 1250 1300 1600 1300 N -P 4 0 1 0 1250 1300 1250 900 1500 900 1600 900 N -X in1 1 1050 1250 200 R 50 50 1 1 I -X in2 2 1050 1150 200 R 50 50 1 1 I -X in3 3 1050 1050 200 R 50 50 1 1 I -X in4 4 1050 950 200 R 50 50 1 1 I -X out 5 1950 1100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 1350 800 60 H V C CNN -F1 "5_and" 1400 1050 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 -P 2 0 1 0 1050 1150 1450 1150 N -P 3 0 1 0 1050 1150 1050 650 1450 650 N -X in1 1 850 1100 200 R 50 50 1 1 I -X in2 2 850 1000 200 R 50 50 1 1 I -X in3 3 850 900 200 R 50 50 1 1 I -X in4 4 850 800 200 R 50 50 1 1 I -X in5 5 850 700 200 R 50 50 1 1 I -X out 6 1850 900 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# c_gate -# -DEF c_gate X 0 40 Y Y 1 F N -F0 "X" 5900 4450 60 H V C CNN -F1 "c_gate" 5950 4700 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 6000 4550 316 716 -716 0 1 0 N 6100 4850 6100 4250 -P 2 0 1 0 5550 4850 6100 4850 N -P 4 0 1 0 5550 4850 5550 4250 6050 4250 6100 4250 N -X in1 1 5350 4800 200 R 50 50 1 1 I I -X in2 2 5350 4700 200 R 50 50 1 1 I I -X in3 3 5350 4600 200 R 50 50 1 1 I I -X in4 4 5350 4500 200 R 50 50 1 1 I I -X in5 5 5350 4400 200 R 50 50 1 1 I I -X in6 6 5350 4300 200 R 50 50 1 1 I I -X out 7 6500 4550 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_nand -# -DEF d_nand U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nand" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_nor -# -DEF d_nor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_nor" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/7485mod.sch b/src/SubcircuitLibrary/7485/7485mod.sch deleted file mode 100644 index f7e537ad..00000000 --- a/src/SubcircuitLibrary/7485/7485mod.sch +++ /dev/null @@ -1,1007 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:7485-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U6 -U 1 1 5C9A2432 -P 3150 1200 -F 0 "U6" H 3150 1200 60 0000 C CNN -F 1 "d_and" H 3200 1300 60 0000 C CNN -F 2 "" H 3150 1200 60 0000 C CNN -F 3 "" H 3150 1200 60 0000 C CNN - 1 3150 1200 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U2 -U 1 1 5C9A246F -P 2100 1450 -F 0 "U2" H 2100 1450 60 0000 C CNN -F 1 "d_nand" H 2150 1550 60 0000 C CNN -F 2 "" H 2100 1450 60 0000 C CNN -F 3 "" H 2100 1450 60 0000 C CNN - 1 2100 1450 - 1 0 0 -1 -$EndComp -$Comp -L d_and U7 -U 1 1 5C9A24BA -P 3150 1600 -F 0 "U7" H 3150 1600 60 0000 C CNN -F 1 "d_and" H 3200 1700 60 0000 C CNN -F 2 "" H 3150 1600 60 0000 C CNN -F 3 "" H 3150 1600 60 0000 C CNN - 1 3150 1600 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U14 -U 1 1 5C9A252F -P 4050 1400 -F 0 "U14" H 4050 1400 60 0000 C CNN -F 1 "d_nor" H 4100 1500 60 0000 C CNN -F 2 "" H 4050 1400 60 0000 C CNN -F 3 "" H 4050 1400 60 0000 C CNN - 1 4050 1400 - 1 0 0 -1 -$EndComp -$Comp -L d_and U19 -U 1 1 5C9A2580 -P 6900 1000 -F 0 "U19" H 6900 1000 60 0000 C CNN -F 1 "d_and" H 6950 1100 60 0000 C CNN -F 2 "" H 6900 1000 60 0000 C CNN -F 3 "" H 6900 1000 60 0000 C CNN - 1 6900 1000 - 1 0 0 -1 -$EndComp -$Comp -L 3_and X12 -U 1 1 5C9A2DC4 -P 6050 1650 -F 0 "X12" H 6950 1950 60 0000 C CNN -F 1 "3_and" H 7000 2150 60 0000 C CNN -F 2 "" H 6050 1650 60 0000 C CNN -F 3 "" H 6050 1650 60 0000 C CNN - 1 6050 1650 - 1 0 0 -1 -$EndComp -$Comp -L 4_and X7 -U 1 1 5C9A2EB7 -P 5450 2750 -F 0 "X7" H 6950 3800 60 0000 C CNN -F 1 "4_and" H 7000 3950 60 0000 C CNN -F 2 "" H 5450 2750 60 0000 C CNN -F 3 "" H 5450 2750 60 0000 C CNN - 1 5450 2750 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X9 -U 1 1 5C9A2F2E -P 5650 3050 -F 0 "X9" H 7000 3850 60 0000 C CNN -F 1 "5_and" H 7050 4100 60 0000 C CNN -F 2 "" H 5650 3050 60 0000 C CNN -F 3 "" H 5650 3050 60 0000 C CNN - 1 5650 3050 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X10 -U 1 1 5C9A2F95 -P 5650 3600 -F 0 "X10" H 7000 4400 60 0000 C CNN -F 1 "5_and" H 7050 4650 60 0000 C CNN -F 2 "" H 5650 3600 60 0000 C CNN -F 3 "" H 5650 3600 60 0000 C CNN - 1 5650 3600 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X11 -U 1 1 5C9A3164 -P 5650 4150 -F 0 "X11" H 7000 4950 60 0000 C CNN -F 1 "5_and" H 7050 5200 60 0000 C CNN -F 2 "" H 5650 4150 60 0000 C CNN -F 3 "" H 5650 4150 60 0000 C CNN - 1 5650 4150 - 1 0 0 -1 -$EndComp -$Comp -L 5_and X13 -U 1 1 5C9A31B3 -P 7550 4850 -F 0 "X13" H 8900 5650 60 0000 C CNN -F 1 "5_and" H 8950 5900 60 0000 C CNN -F 2 "" H 7550 4850 60 0000 C CNN -F 3 "" H 7550 4850 60 0000 C CNN - 1 7550 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_and U18 -U 1 1 5C9A32FD -P 6350 6900 -F 0 "U18" H 6350 6900 60 0000 C CNN -F 1 "d_and" H 6400 7000 60 0000 C CNN -F 2 "" H 6350 6900 60 0000 C CNN -F 3 "" H 6350 6900 60 0000 C CNN - 1 6350 6900 - 1 0 0 1 -$EndComp -$Comp -L 3_and X8 -U 1 1 5C9A3303 -P 5500 6250 -F 0 "X8" H 6400 6550 60 0000 C CNN -F 1 "3_and" H 6450 6750 60 0000 C CNN -F 2 "" H 5500 6250 60 0000 C CNN -F 3 "" H 5500 6250 60 0000 C CNN - 1 5500 6250 - 1 0 0 1 -$EndComp -$Comp -L 4_and X3 -U 1 1 5C9A3309 -P 4900 5150 -F 0 "X3" H 6400 6200 60 0000 C CNN -F 1 "4_and" H 6450 6350 60 0000 C CNN -F 2 "" H 4900 5150 60 0000 C CNN -F 3 "" H 4900 5150 60 0000 C CNN - 1 4900 5150 - 1 0 0 1 -$EndComp -$Comp -L 5_and X6 -U 1 1 5C9A330F -P 5100 4850 -F 0 "X6" H 6450 5650 60 0000 C CNN -F 1 "5_and" H 6500 5900 60 0000 C CNN -F 2 "" H 5100 4850 60 0000 C CNN -F 3 "" H 5100 4850 60 0000 C CNN - 1 5100 4850 - 1 0 0 1 -$EndComp -$Comp -L 5_and X5 -U 1 1 5C9A3315 -P 5100 4300 -F 0 "X5" H 6450 5100 60 0000 C CNN -F 1 "5_and" H 6500 5350 60 0000 C CNN -F 2 "" H 5100 4300 60 0000 C CNN -F 3 "" H 5100 4300 60 0000 C CNN - 1 5100 4300 - 1 0 0 1 -$EndComp -$Comp -L 5_and X4 -U 1 1 5C9A331B -P 5100 3750 -F 0 "X4" H 6450 4550 60 0000 C CNN -F 1 "5_and" H 6500 4800 60 0000 C CNN -F 2 "" H 5100 3750 60 0000 C CNN -F 3 "" H 5100 3750 60 0000 C CNN - 1 5100 3750 - 1 0 0 1 -$EndComp -$Comp -L d_and U8 -U 1 1 5C9A39D8 -P 3250 2600 -F 0 "U8" H 3250 2600 60 0000 C CNN -F 1 "d_and" H 3300 2700 60 0000 C CNN -F 2 "" H 3250 2600 60 0000 C CNN -F 3 "" H 3250 2600 60 0000 C CNN - 1 3250 2600 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U3 -U 1 1 5C9A39DE -P 2200 2850 -F 0 "U3" H 2200 2850 60 0000 C CNN -F 1 "d_nand" H 2250 2950 60 0000 C CNN -F 2 "" H 2200 2850 60 0000 C CNN -F 3 "" H 2200 2850 60 0000 C CNN - 1 2200 2850 - 1 0 0 -1 -$EndComp -$Comp -L d_and U9 -U 1 1 5C9A39E4 -P 3250 3000 -F 0 "U9" H 3250 3000 60 0000 C CNN -F 1 "d_and" H 3300 3100 60 0000 C CNN -F 2 "" H 3250 3000 60 0000 C CNN -F 3 "" H 3250 3000 60 0000 C CNN - 1 3250 3000 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U15 -U 1 1 5C9A39EA -P 4150 2800 -F 0 "U15" H 4150 2800 60 0000 C CNN -F 1 "d_nor" H 4200 2900 60 0000 C CNN -F 2 "" H 4150 2800 60 0000 C CNN -F 3 "" H 4150 2800 60 0000 C CNN - 1 4150 2800 - 1 0 0 -1 -$EndComp -$Comp -L d_and U12 -U 1 1 5C9A3B56 -P 3600 4950 -F 0 "U12" H 3600 4950 60 0000 C CNN -F 1 "d_and" H 3650 5050 60 0000 C CNN -F 2 "" H 3600 4950 60 0000 C CNN -F 3 "" H 3600 4950 60 0000 C CNN - 1 3600 4950 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U5 -U 1 1 5C9A3B5C -P 2550 5200 -F 0 "U5" H 2550 5200 60 0000 C CNN -F 1 "d_nand" H 2600 5300 60 0000 C CNN -F 2 "" H 2550 5200 60 0000 C CNN -F 3 "" H 2550 5200 60 0000 C CNN - 1 2550 5200 - 1 0 0 -1 -$EndComp -$Comp -L d_and U13 -U 1 1 5C9A3B62 -P 3600 5350 -F 0 "U13" H 3600 5350 60 0000 C CNN -F 1 "d_and" H 3650 5450 60 0000 C CNN -F 2 "" H 3600 5350 60 0000 C CNN -F 3 "" H 3600 5350 60 0000 C CNN - 1 3600 5350 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U17 -U 1 1 5C9A3B68 -P 4500 5150 -F 0 "U17" H 4500 5150 60 0000 C CNN -F 1 "d_nor" H 4550 5250 60 0000 C CNN -F 2 "" H 4500 5150 60 0000 C CNN -F 3 "" H 4500 5150 60 0000 C CNN - 1 4500 5150 - 1 0 0 -1 -$EndComp -$Comp -L d_and U10 -U 1 1 5C9A3C6D -P 3400 3750 -F 0 "U10" H 3400 3750 60 0000 C CNN -F 1 "d_and" H 3450 3850 60 0000 C CNN -F 2 "" H 3400 3750 60 0000 C CNN -F 3 "" H 3400 3750 60 0000 C CNN - 1 3400 3750 - 1 0 0 -1 -$EndComp -$Comp -L d_nand U4 -U 1 1 5C9A3C73 -P 2350 4000 -F 0 "U4" H 2350 4000 60 0000 C CNN -F 1 "d_nand" H 2400 4100 60 0000 C CNN -F 2 "" H 2350 4000 60 0000 C CNN -F 3 "" H 2350 4000 60 0000 C CNN - 1 2350 4000 - 1 0 0 -1 -$EndComp -$Comp -L d_and U11 -U 1 1 5C9A3C79 -P 3400 4150 -F 0 "U11" H 3400 4150 60 0000 C CNN -F 1 "d_and" H 3450 4250 60 0000 C CNN -F 2 "" H 3400 4150 60 0000 C CNN -F 3 "" H 3400 4150 60 0000 C CNN - 1 3400 4150 - 1 0 0 -1 -$EndComp -$Comp -L d_nor U16 -U 1 1 5C9A3C7F -P 4300 3950 -F 0 "U16" H 4300 3950 60 0000 C CNN -F 1 "d_nor" H 4350 4050 60 0000 C CNN -F 2 "" H 4300 3950 60 0000 C CNN -F 3 "" H 4300 3950 60 0000 C CNN - 1 4300 3950 - 1 0 0 -1 -$EndComp -$Comp -L c_gate X2 -U 1 1 5C9A4498 -P 3050 6600 -F 0 "X2" H 3100 6650 60 0000 C CNN -F 1 "c_gate" H 9000 11300 60 0000 C CNN -F 2 "" H 3050 6600 60 0000 C CNN -F 3 "" H 3050 6600 60 0000 C CNN - 1 3050 6600 - 1 0 0 -1 -$EndComp -$Comp -L c_gate X1 -U 1 1 5C9A465F -P 2850 10000 -F 0 "X1" H 2900 10050 60 0000 C CNN -F 1 "c_gate" H 8800 14700 60 0000 C CNN -F 2 "" H 2850 10000 60 0000 C CNN -F 3 "" H 2850 10000 60 0000 C CNN - 1 2850 10000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3600 1300 3600 1150 -Wire Wire Line - 3600 1400 3600 1550 -Wire Wire Line - 2700 1000 2700 4700 -Wire Wire Line - 2700 1600 1550 1600 -Wire Wire Line - 1550 1600 1550 1450 -Wire Wire Line - 1100 1450 1650 1450 -Wire Wire Line - 1100 1350 1650 1350 -Wire Wire Line - 1550 1350 1550 1100 -Wire Wire Line - 1550 1100 2700 1100 -Wire Wire Line - 2550 1400 2700 1400 -Connection ~ 2700 1400 -Connection ~ 1550 1350 -Connection ~ 1550 1450 -Wire Wire Line - 3700 2700 3700 2550 -Wire Wire Line - 3700 2800 3700 2950 -Wire Wire Line - 2800 2000 2800 4600 -Wire Wire Line - 2800 3000 1650 3000 -Wire Wire Line - 1650 3000 1650 2850 -Wire Wire Line - 1200 2850 1750 2850 -Wire Wire Line - 1200 2750 1750 2750 -Wire Wire Line - 1650 2750 1650 2500 -Wire Wire Line - 1650 2500 2800 2500 -Wire Wire Line - 2650 2800 2800 2800 -Connection ~ 2800 2800 -Connection ~ 1650 2750 -Connection ~ 1650 2850 -Wire Wire Line - 4050 5050 4050 4900 -Wire Wire Line - 4050 5150 4050 5300 -Wire Wire Line - 3150 4950 3150 5850 -Wire Wire Line - 3150 5350 2000 5350 -Wire Wire Line - 2000 5350 2000 5200 -Wire Wire Line - 1250 5200 2100 5200 -Wire Wire Line - 1250 5100 2100 5100 -Wire Wire Line - 2000 5100 2000 4850 -Wire Wire Line - 2000 4850 3150 4850 -Wire Wire Line - 3000 5150 3150 5150 -Connection ~ 3150 5150 -Connection ~ 2000 5100 -Connection ~ 2000 5200 -Wire Wire Line - 3850 3850 3850 3700 -Wire Wire Line - 3850 3950 3850 4100 -Wire Wire Line - 2950 3200 2950 4350 -Wire Wire Line - 2950 4150 1800 4150 -Wire Wire Line - 1800 4150 1800 4000 -Wire Wire Line - 1350 4000 1900 4000 -Wire Wire Line - 1200 3900 1900 3900 -Wire Wire Line - 1800 3900 1800 3650 -Wire Wire Line - 1800 3650 2950 3650 -Wire Wire Line - 2800 3950 2950 3950 -Connection ~ 2950 3950 -Connection ~ 1800 3900 -Connection ~ 1800 4000 -Wire Wire Line - 1400 1350 1400 7000 -Wire Wire Line - 1400 7000 5900 7000 -Connection ~ 1400 1350 -Wire Wire Line - 1250 5200 1250 5300 -Wire Wire Line - 5900 6900 2900 6900 -Wire Wire Line - 2900 6900 2900 4700 -Wire Wire Line - 2900 4700 2700 4700 -Connection ~ 2700 1500 -Wire Wire Line - 5950 6750 1450 6750 -Wire Wire Line - 1450 6750 1450 2750 -Connection ~ 1450 2750 -Wire Wire Line - 5950 6650 2950 6650 -Wire Wire Line - 2950 6650 2950 4600 -Wire Wire Line - 2950 4600 2800 4600 -Connection ~ 2800 2900 -Wire Wire Line - 5100 6550 5950 6550 -Wire Wire Line - 5100 1350 5100 6550 -Wire Wire Line - 4500 1350 6500 1350 -Wire Wire Line - 1500 1450 1500 900 -Wire Wire Line - 1500 900 6450 900 -Connection ~ 1500 1450 -Wire Wire Line - 2700 1000 6450 1000 -Connection ~ 2700 1200 -Wire Wire Line - 6500 1150 4500 1150 -Wire Wire Line - 4500 1150 4500 1900 -Wire Wire Line - 4500 1900 1600 1900 -Wire Wire Line - 1600 1900 1600 2850 -Connection ~ 1600 2850 -Wire Wire Line - 6500 1250 4550 1250 -Wire Wire Line - 4550 1250 4550 2000 -Wire Wire Line - 4550 2000 2800 2000 -Connection ~ 2800 2600 -Connection ~ 5100 1350 -Wire Wire Line - 6500 1500 4600 1500 -Wire Wire Line - 4600 1500 4600 2100 -Wire Wire Line - 4600 2100 1750 2100 -Wire Wire Line - 1750 2100 1750 4000 -Connection ~ 1750 4000 -Wire Wire Line - 6500 1600 4650 1600 -Wire Wire Line - 4650 1600 4650 3200 -Wire Wire Line - 4650 3200 2950 3200 -Connection ~ 2950 3750 -Wire Wire Line - 6500 1700 5100 1700 -Connection ~ 5100 1700 -Wire Wire Line - 6500 1800 5250 1800 -Wire Wire Line - 5250 1800 5250 6100 -Wire Wire Line - 5250 2750 4600 2750 -Wire Wire Line - 6500 1950 1500 1950 -Wire Wire Line - 1500 1950 1500 5200 -Connection ~ 1500 5200 -Wire Wire Line - 6500 2050 4950 2050 -Wire Wire Line - 4950 2050 4950 4300 -Wire Wire Line - 4950 4300 3150 4300 -Wire Wire Line - 3150 4300 3150 5000 -Connection ~ 3150 5000 -Wire Wire Line - 6500 2150 5100 2150 -Connection ~ 5100 2150 -Wire Wire Line - 6500 2250 5250 2250 -Connection ~ 5250 2250 -Wire Wire Line - 6500 2350 5350 2350 -Wire Wire Line - 5350 2350 5350 5550 -Wire Wire Line - 5350 3900 4750 3900 -Wire Wire Line - 6500 2500 5100 2500 -Connection ~ 5100 2500 -Wire Wire Line - 6500 2600 5250 2600 -Connection ~ 5250 2600 -Wire Wire Line - 6500 2700 5350 2700 -Connection ~ 5350 2700 -Wire Wire Line - 6500 2800 5450 2800 -Wire Wire Line - 5450 2800 5450 5100 -Wire Wire Line - 4950 5100 5950 5100 -Wire Wire Line - 6500 2900 5550 2900 -Wire Wire Line - 5550 2900 5550 3250 -Wire Wire Line - 5550 3250 1050 3250 -Wire Wire Line - 6500 3050 5100 3050 -Connection ~ 5100 3050 -Wire Wire Line - 5250 3150 6500 3150 -Connection ~ 5250 2750 -Wire Wire Line - 6500 3250 5700 3250 -Wire Wire Line - 5700 3250 5700 3200 -Wire Wire Line - 5700 3200 5350 3200 -Connection ~ 5350 3200 -Wire Wire Line - 6500 3350 5450 3350 -Connection ~ 5450 3350 -Wire Wire Line - 4800 3450 6500 3450 -Wire Wire Line - 4800 3450 4800 3400 -Wire Wire Line - 4800 3400 1050 3400 -Wire Wire Line - 5950 3450 5950 4450 -Connection ~ 5950 3450 -Wire Wire Line - 5950 4550 5450 4550 -Connection ~ 5450 4550 -Wire Wire Line - 5350 4650 5950 4650 -Connection ~ 5350 3900 -Wire Wire Line - 5250 4750 5950 4750 -Connection ~ 5250 3150 -Wire Wire Line - 5950 4850 5100 4850 -Connection ~ 5100 4850 -Wire Wire Line - 5950 5400 5100 5400 -Connection ~ 5100 5400 -Wire Wire Line - 5950 5750 5100 5750 -Connection ~ 5100 5750 -Wire Wire Line - 5950 5000 4800 5000 -Wire Wire Line - 4800 5000 4800 3550 -Wire Wire Line - 4800 3550 1050 3550 -Connection ~ 5450 5100 -Wire Wire Line - 5350 5200 5950 5200 -Connection ~ 5350 4650 -Wire Wire Line - 5250 5300 5950 5300 -Connection ~ 5250 4750 -Wire Wire Line - 5950 5950 1800 5950 -Wire Wire Line - 1800 5950 1800 5100 -Connection ~ 1800 5100 -Wire Wire Line - 5950 6400 1600 6400 -Wire Wire Line - 1600 6400 1600 3900 -Connection ~ 1600 3900 -Wire Wire Line - 5950 6300 5100 6300 -Connection ~ 5100 6300 -Wire Wire Line - 5350 5550 5950 5550 -Connection ~ 5350 5200 -Wire Wire Line - 5250 5650 5950 5650 -Connection ~ 5250 5300 -Wire Wire Line - 3150 5850 5950 5850 -Connection ~ 3150 5250 -Wire Wire Line - 5250 6100 5950 6100 -Connection ~ 5250 5650 -Wire Wire Line - 5950 6200 3000 6200 -Wire Wire Line - 3000 6200 3000 4350 -Wire Wire Line - 3000 4350 2950 4350 -Connection ~ 2950 4050 -Wire Wire Line - 8400 3950 5950 3950 -Connection ~ 5950 3950 -Wire Wire Line - 8400 3750 5100 3750 -Connection ~ 5100 3750 -Wire Wire Line - 8400 3850 5250 3850 -Connection ~ 5250 3850 -Wire Wire Line - 8400 4050 5350 4050 -Connection ~ 5350 4050 -Wire Wire Line - 8400 4150 5450 4150 -Connection ~ 5450 4150 -Wire Wire Line - 8400 1800 8400 950 -Wire Wire Line - 8400 950 7350 950 -Wire Wire Line - 8400 1900 8200 1900 -Wire Wire Line - 8200 1900 8200 1250 -Wire Wire Line - 8200 1250 7350 1250 -Wire Wire Line - 8400 2000 8050 2000 -Wire Wire Line - 8050 2000 8050 1650 -Wire Wire Line - 8050 1650 7400 1650 -Wire Wire Line - 7500 2150 7800 2150 -Wire Wire Line - 7800 2150 7800 2100 -Wire Wire Line - 7800 2100 8400 2100 -Wire Wire Line - 8400 2200 7900 2200 -Wire Wire Line - 7900 2200 7900 2700 -Wire Wire Line - 7900 2700 7500 2700 -Wire Wire Line - 7500 3250 8050 3250 -Wire Wire Line - 8050 3250 8050 2300 -Wire Wire Line - 8050 2300 8400 2300 -Wire Wire Line - 8200 5200 8200 4650 -Wire Wire Line - 8200 4650 6950 4650 -Wire Wire Line - 8200 5300 8050 5300 -Wire Wire Line - 8050 5300 8050 5200 -Wire Wire Line - 8050 5200 6950 5200 -Wire Wire Line - 8200 5400 7250 5400 -Wire Wire Line - 7250 5400 7250 5750 -Wire Wire Line - 7250 5750 6950 5750 -Wire Wire Line - 6850 6250 6850 5850 -Wire Wire Line - 6850 5850 7350 5850 -Wire Wire Line - 7350 5850 7350 5500 -Wire Wire Line - 7350 5500 8200 5500 -Wire Wire Line - 6800 6950 6950 6950 -Wire Wire Line - 6950 6950 6950 6200 -Wire Wire Line - 6950 6200 7950 6200 -Wire Wire Line - 7950 6200 7950 5700 -Wire Wire Line - 7950 5700 8200 5700 -$Comp -L PORT U1 -U 4 1 5C9A8539 -P 850 1350 -F 0 "U1" H 900 1450 30 0000 C CNN -F 1 "PORT" H 850 1350 30 0000 C CNN -F 2 "" H 850 1350 60 0000 C CNN -F 3 "" H 850 1350 60 0000 C CNN - 4 850 1350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A8668 -P 850 1550 -F 0 "U1" H 900 1650 30 0000 C CNN -F 1 "PORT" H 850 1550 30 0000 C CNN -F 2 "" H 850 1550 60 0000 C CNN -F 3 "" H 850 1550 60 0000 C CNN - 5 850 1550 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1100 1550 1100 1450 -$Comp -L PORT U1 -U 6 1 5C9A8815 -P 950 2650 -F 0 "U1" H 1000 2750 30 0000 C CNN -F 1 "PORT" H 950 2650 30 0000 C CNN -F 2 "" H 950 2650 60 0000 C CNN -F 3 "" H 950 2650 60 0000 C CNN - 6 950 2650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1200 2650 1200 2750 -$Comp -L PORT U1 -U 7 1 5C9A8B82 -P 950 2850 -F 0 "U1" H 1000 2950 30 0000 C CNN -F 1 "PORT" H 950 2850 30 0000 C CNN -F 2 "" H 950 2850 60 0000 C CNN -F 3 "" H 950 2850 60 0000 C CNN - 7 950 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5C9A8C46 -P 950 3900 -F 0 "U1" H 1000 4000 30 0000 C CNN -F 1 "PORT" H 950 3900 30 0000 C CNN -F 2 "" H 950 3900 60 0000 C CNN -F 3 "" H 950 3900 60 0000 C CNN - 8 950 3900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C9A8D2C -P 950 4100 -F 0 "U1" H 1000 4200 30 0000 C CNN -F 1 "PORT" H 950 4100 30 0000 C CNN -F 2 "" H 950 4100 60 0000 C CNN -F 3 "" H 950 4100 60 0000 C CNN - 9 950 4100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C9A8DBD -P 1000 5100 -F 0 "U1" H 1050 5200 30 0000 C CNN -F 1 "PORT" H 1000 5100 30 0000 C CNN -F 2 "" H 1000 5100 60 0000 C CNN -F 3 "" H 1000 5100 60 0000 C CNN - 10 1000 5100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C9A8E65 -P 1000 5300 -F 0 "U1" H 1050 5400 30 0000 C CNN -F 1 "PORT" H 1000 5300 30 0000 C CNN -F 2 "" H 1000 5300 60 0000 C CNN -F 3 "" H 1000 5300 60 0000 C CNN - 11 1000 5300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A8EEE -P 800 3150 -F 0 "U1" H 850 3250 30 0000 C CNN -F 1 "PORT" H 800 3150 30 0000 C CNN -F 2 "" H 800 3150 60 0000 C CNN -F 3 "" H 800 3150 60 0000 C CNN - 1 800 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A8F9C -P 800 3400 -F 0 "U1" H 850 3500 30 0000 C CNN -F 1 "PORT" H 800 3400 30 0000 C CNN -F 2 "" H 800 3400 60 0000 C CNN -F 3 "" H 800 3400 60 0000 C CNN - 2 800 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A9031 -P 800 3600 -F 0 "U1" H 850 3700 30 0000 C CNN -F 1 "PORT" H 800 3600 30 0000 C CNN -F 2 "" H 800 3600 60 0000 C CNN -F 3 "" H 800 3600 60 0000 C CNN - 3 800 3600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1050 3250 1050 3150 -Wire Wire Line - 1050 3550 1050 3600 -Wire Wire Line - 1350 4000 1350 4100 -Wire Wire Line - 1350 4100 1200 4100 -Wire Wire Line - 9550 2050 9850 2050 -Wire Wire Line - 9400 3950 9850 3950 -Wire Wire Line - 9350 5450 9900 5450 -$Comp -L PORT U1 -U 12 1 5C9A9B26 -P 10100 2050 -F 0 "U1" H 10150 2150 30 0000 C CNN -F 1 "PORT" H 10100 2050 30 0000 C CNN -F 2 "" H 10100 2050 60 0000 C CNN -F 3 "" H 10100 2050 60 0000 C CNN - 12 10100 2050 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 13 1 5C9A9BCA -P 10100 3950 -F 0 "U1" H 10150 4050 30 0000 C CNN -F 1 "PORT" H 10100 3950 30 0000 C CNN -F 2 "" H 10100 3950 60 0000 C CNN -F 3 "" H 10100 3950 60 0000 C CNN - 13 10100 3950 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5C9A9CA0 -P 10150 5450 -F 0 "U1" H 10200 5550 30 0000 C CNN -F 1 "PORT" H 10150 5450 30 0000 C CNN -F 2 "" H 10150 5450 60 0000 C CNN -F 3 "" H 10150 5450 60 0000 C CNN - 14 10150 5450 - -1 0 0 1 -$EndComp -Text Notes 9650 2000 0 60 ~ 12 -A>B -Text Notes 9600 3900 0 60 ~ 12 -A=B\n -Text Notes 9600 5400 0 60 ~ 12 -A<B\n -Text Notes 1250 5100 0 60 ~ 12 -A0 -Text Notes 1200 5400 0 60 ~ 12 -B0 -Text Notes 1300 3900 2 60 ~ 12 -A1 -Text Notes 1300 4200 2 60 ~ 12 -B1 -Text Notes 1250 3250 2 60 ~ 12 -A<B -Text Notes 1250 3400 2 60 ~ 12 -A=B -Text Notes 1250 3550 2 60 ~ 12 -A>B -Text Notes 1350 2750 2 60 ~ 12 -A2 -Text Notes 1350 2950 2 60 ~ 12 -B2 -Text Notes 1300 1350 2 60 ~ 12 -A3 -Text Notes 1300 1550 2 60 ~ 12 -B3 -Wire Wire Line - 8200 5600 7450 5600 -Wire Wire Line - 7450 5600 7450 6050 -Wire Wire Line - 7450 6050 6900 6050 -Wire Wire Line - 6800 6650 6800 6300 -Wire Wire Line - 6800 6300 6900 6300 -Wire Wire Line - 6900 6300 6900 6050 -Wire Notes Line - 500 3000 1350 3000 -Wire Notes Line - 1350 3000 1350 3750 -Wire Notes Line - 1350 3750 500 3750 -Wire Notes Line - 500 3750 500 3000 -Text Notes 600 3000 3 60 ~ 12 -Cascading Inputs -Wire Notes Line - 9500 1550 9500 6050 -Wire Notes Line - 9500 6050 10550 6050 -Wire Notes Line - 10550 6050 10550 1550 -Wire Notes Line - 10550 1550 9500 1550 -Text Notes 9900 3400 0 60 ~ 12 -Outputs -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/analysis b/src/SubcircuitLibrary/7485/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/7485/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate-cache.lib b/src/SubcircuitLibrary/7485/c_gate-cache.lib deleted file mode 100644 index 05fb44d7..00000000 --- a/src/SubcircuitLibrary/7485/c_gate-cache.lib +++ /dev/null @@ -1,95 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 5_and -# -DEF 5_and X 0 40 Y Y 1 F N -F0 "X" 1350 800 60 H V C CNN -F1 "5_and" 1400 1050 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 1400 900 255 787 -787 0 1 0 N 1450 1150 1450 650 -P 2 0 1 0 1050 1150 1450 1150 N -P 3 0 1 0 1050 1150 1050 650 1450 650 N -X in1 1 850 1100 200 R 50 50 1 1 I -X in2 2 850 1000 200 R 50 50 1 1 I -X in3 3 850 900 200 R 50 50 1 1 I -X in4 4 850 800 200 R 50 50 1 1 I -X in5 5 850 700 200 R 50 50 1 1 I -X out 6 1850 900 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/7485/c_gate.cir b/src/SubcircuitLibrary/7485/c_gate.cir deleted file mode 100644 index 1ac12515..00000000 --- a/src/SubcircuitLibrary/7485/c_gate.cir +++ /dev/null @@ -1,19 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\c_gate\c_gate.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 19:11:36 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U8-Pad1_ 5_and -U8 Net-_U8-Pad1_ Net-_U7-Pad2_ Net-_U1-Pad7_ d_and -U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter -U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter -U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter -U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter -U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter -U7 Net-_U1-Pad6_ Net-_U7-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT - -.end diff --git a/src/SubcircuitLibrary/7485/c_gate.cir.out b/src/SubcircuitLibrary/7485/c_gate.cir.out deleted file mode 100644 index db7bb2f8..00000000 --- a/src/SubcircuitLibrary/7485/c_gate.cir.out +++ /dev/null @@ -1,42 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir - -.include 5_and.sub -x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and -* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter -* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port -a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 net-_u1-pad2_ net-_u3-pad2_ u3 -a4 net-_u1-pad3_ net-_u4-pad2_ u4 -a5 net-_u1-pad4_ net-_u5-pad2_ u5 -a6 net-_u1-pad5_ net-_u6-pad2_ u6 -a7 net-_u1-pad6_ net-_u7-pad2_ u7 -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/7485/c_gate.pro b/src/SubcircuitLibrary/7485/c_gate.pro deleted file mode 100644 index f0743529..00000000 --- a/src/SubcircuitLibrary/7485/c_gate.pro +++ /dev/null @@ -1,57 +0,0 @@ -update=03/26/19 19:06:59 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=texas -LibName2=intel -LibName3=audio -LibName4=interface -LibName5=digital-audio -LibName6=philips -LibName7=display -LibName8=cypress -LibName9=siliconi -LibName10=opto -LibName11=atmel -LibName12=contrib -LibName13=valves -LibName14=eSim_Analog -LibName15=eSim_Devices -LibName16=eSim_Digital -LibName17=eSim_Hybrid -LibName18=eSim_Miscellaneous -LibName19=eSim_Plot -LibName20=eSim_Power -LibName21=eSim_PSpice -LibName22=eSim_Sources -LibName23=eSim_Subckt -LibName24=eSim_User diff --git a/src/SubcircuitLibrary/7485/c_gate.sch b/src/SubcircuitLibrary/7485/c_gate.sch deleted file mode 100644 index 5d960c8d..00000000 --- a/src/SubcircuitLibrary/7485/c_gate.sch +++ /dev/null @@ -1,246 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:c_gate-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 5_and X1 -U 1 1 5C9A2B0B -P 3300 3750 -F 0 "X1" H 4650 4550 60 0000 C CNN -F 1 "5_and" H 4700 4800 60 0000 C CNN -F 2 "" H 3300 3750 60 0000 C CNN -F 3 "" H 3300 3750 60 0000 C CNN - 1 3300 3750 - 1 0 0 -1 -$EndComp -$Comp -L d_and U8 -U 1 1 5C9A2B3E -P 5600 3300 -F 0 "U8" H 5600 3300 60 0000 C CNN -F 1 "d_and" H 5650 3400 60 0000 C CNN -F 2 "" H 5600 3300 60 0000 C CNN -F 3 "" H 5600 3300 60 0000 C CNN - 1 5600 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5150 3200 5150 2850 -Wire Wire Line - 4150 2650 4150 2350 -Wire Wire Line - 4150 2350 3600 2350 -Wire Wire Line - 4150 2750 4050 2750 -Wire Wire Line - 4050 2750 4050 2550 -Wire Wire Line - 4050 2550 3600 2550 -Wire Wire Line - 4150 2850 3700 2850 -Wire Wire Line - 3700 2850 3700 2750 -Wire Wire Line - 3700 2750 3600 2750 -Wire Wire Line - 4150 2950 3600 2950 -Wire Wire Line - 4150 3050 4150 3150 -Wire Wire Line - 4150 3150 3600 3150 -Wire Wire Line - 5150 3300 3600 3300 -$Comp -L d_inverter U2 -U 1 1 5C9A2CDC -P 3300 2350 -F 0 "U2" H 3300 2250 60 0000 C CNN -F 1 "d_inverter" H 3300 2500 60 0000 C CNN -F 2 "" H 3350 2300 60 0000 C CNN -F 3 "" H 3350 2300 60 0000 C CNN - 1 3300 2350 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U3 -U 1 1 5C9A2D06 -P 3300 2550 -F 0 "U3" H 3300 2450 60 0000 C CNN -F 1 "d_inverter" H 3300 2700 60 0000 C CNN -F 2 "" H 3350 2500 60 0000 C CNN -F 3 "" H 3350 2500 60 0000 C CNN - 1 3300 2550 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5C9A2D26 -P 3300 2750 -F 0 "U4" H 3300 2650 60 0000 C CNN -F 1 "d_inverter" H 3300 2900 60 0000 C CNN -F 2 "" H 3350 2700 60 0000 C CNN -F 3 "" H 3350 2700 60 0000 C CNN - 1 3300 2750 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U5 -U 1 1 5C9A2D49 -P 3300 2950 -F 0 "U5" H 3300 2850 60 0000 C CNN -F 1 "d_inverter" H 3300 3100 60 0000 C CNN -F 2 "" H 3350 2900 60 0000 C CNN -F 3 "" H 3350 2900 60 0000 C CNN - 1 3300 2950 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U6 -U 1 1 5C9A2D73 -P 3300 3150 -F 0 "U6" H 3300 3050 60 0000 C CNN -F 1 "d_inverter" H 3300 3300 60 0000 C CNN -F 2 "" H 3350 3100 60 0000 C CNN -F 3 "" H 3350 3100 60 0000 C CNN - 1 3300 3150 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U7 -U 1 1 5C9A2D9E -P 3300 3300 -F 0 "U7" H 3300 3200 60 0000 C CNN -F 1 "d_inverter" H 3300 3450 60 0000 C CNN -F 2 "" H 3350 3250 60 0000 C CNN -F 3 "" H 3350 3250 60 0000 C CNN - 1 3300 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3000 2350 2000 2350 -Wire Wire Line - 3000 2550 2000 2550 -Wire Wire Line - 3000 2750 2050 2750 -Wire Wire Line - 3000 2950 2050 2950 -Wire Wire Line - 3000 3150 2050 3150 -Wire Wire Line - 3000 3300 2050 3300 -Wire Wire Line - 6050 3250 6950 3250 -$Comp -L PORT U1 -U 1 1 5C9A2F6F -P 1750 2350 -F 0 "U1" H 1800 2450 30 0000 C CNN -F 1 "PORT" H 1750 2350 30 0000 C CNN -F 2 "" H 1750 2350 60 0000 C CNN -F 3 "" H 1750 2350 60 0000 C CNN - 1 1750 2350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A2FAB -P 1750 2550 -F 0 "U1" H 1800 2650 30 0000 C CNN -F 1 "PORT" H 1750 2550 30 0000 C CNN -F 2 "" H 1750 2550 60 0000 C CNN -F 3 "" H 1750 2550 60 0000 C CNN - 2 1750 2550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A2FDD -P 1800 2750 -F 0 "U1" H 1850 2850 30 0000 C CNN -F 1 "PORT" H 1800 2750 30 0000 C CNN -F 2 "" H 1800 2750 60 0000 C CNN -F 3 "" H 1800 2750 60 0000 C CNN - 3 1800 2750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A301A -P 1800 2950 -F 0 "U1" H 1850 3050 30 0000 C CNN -F 1 "PORT" H 1800 2950 30 0000 C CNN -F 2 "" H 1800 2950 60 0000 C CNN -F 3 "" H 1800 2950 60 0000 C CNN - 4 1800 2950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C9A3052 -P 1800 3150 -F 0 "U1" H 1850 3250 30 0000 C CNN -F 1 "PORT" H 1800 3150 30 0000 C CNN -F 2 "" H 1800 3150 60 0000 C CNN -F 3 "" H 1800 3150 60 0000 C CNN - 5 1800 3150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C9A308D -P 1800 3300 -F 0 "U1" H 1850 3400 30 0000 C CNN -F 1 "PORT" H 1800 3300 30 0000 C CNN -F 2 "" H 1800 3300 60 0000 C CNN -F 3 "" H 1800 3300 60 0000 C CNN - 6 1800 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5C9A30DD -P 7200 3250 -F 0 "U1" H 7250 3350 30 0000 C CNN -F 1 "PORT" H 7200 3250 30 0000 C CNN -F 2 "" H 7200 3250 60 0000 C CNN -F 3 "" H 7200 3250 60 0000 C CNN - 7 7200 3250 - -1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/7485/c_gate.sub b/src/SubcircuitLibrary/7485/c_gate.sub deleted file mode 100644 index c6eaa478..00000000 --- a/src/SubcircuitLibrary/7485/c_gate.sub +++ /dev/null @@ -1,36 +0,0 @@ -* Subcircuit c_gate -.subckt c_gate net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ -* c:\users\malli\esim\src\subcircuitlibrary\c_gate\c_gate.cir -.include 5_and.sub -x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad1_ 5_and -* u8 net-_u8-pad1_ net-_u7-pad2_ net-_u1-pad7_ d_and -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter -* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter -* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter -* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter -* u7 net-_u1-pad6_ net-_u7-pad2_ d_inverter -a1 [net-_u8-pad1_ net-_u7-pad2_ ] net-_u1-pad7_ u8 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 net-_u1-pad2_ net-_u3-pad2_ u3 -a4 net-_u1-pad3_ net-_u4-pad2_ u4 -a5 net-_u1-pad4_ net-_u5-pad2_ u5 -a6 net-_u1-pad5_ net-_u6-pad2_ u6 -a7 net-_u1-pad6_ net-_u7-pad2_ u7 -* Schematic Name: d_and, NgSpice Name: d_and -.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u6 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends c_gate
\ No newline at end of file diff --git a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml b/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml deleted file mode 100644 index e51d62de..00000000 --- a/src/SubcircuitLibrary/7485/c_gate_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\5_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib deleted file mode 100644 index f5944a63..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register-cache.lib +++ /dev/null @@ -1,112 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_dff -# -DEF d_dff U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_dff" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 350 450 -350 -400 0 1 0 N -X Din 1 -550 350 200 R 50 50 1 1 I -X Clk 2 -550 -300 200 R 50 50 1 1 I C -X Set 3 0 650 200 D 50 50 1 1 I -X Reset 4 0 -600 200 U 50 50 1 1 I -X Dout 5 550 350 200 L 50 50 1 1 O -X Ndout 6 550 -300 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir deleted file mode 100644 index 52ab8ff8..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir +++ /dev/null @@ -1,56 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\9bit-Right_shift_register\9bit-Right_shift_register.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/24/19 01:43:15
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3 Net-_U20-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U26-Pad2_ ? d_dff
-U4 Net-_U25-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U30-Pad2_ ? d_dff
-U6 Net-_U29-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U34-Pad2_ ? d_dff
-U15 Net-_U15-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U15-Pad5_ ? d_dff
-U2 Net-_U14-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U2-Pad5_ ? d_dff
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? d_dff
-U18 Net-_U18-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U18-Pad5_ ? d_dff
-U11 Net-_U11-Pad1_ Net-_U10-Pad3_ Net-_U1-Pad1_ d_or
-U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or
-U20 Net-_U20-Pad1_ Net-_U19-Pad3_ Net-_U20-Pad3_ d_or
-U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
-U8 Net-_U7-Pad2_ Net-_U5-Pad1_ Net-_U11-Pad1_ d_and
-U7 Net-_U10-Pad1_ Net-_U7-Pad2_ d_inverter
-U13 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and
-U16 Net-_U10-Pad1_ Net-_U1-Pad5_ Net-_U14-Pad1_ d_and
-U12 Net-_U10-Pad1_ Net-_U12-Pad2_ d_inverter
-U19 Net-_U17-Pad2_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and
-U21 Net-_U10-Pad1_ Net-_U2-Pad5_ Net-_U20-Pad1_ d_and
-U17 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter
-U25 Net-_U23-Pad3_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_or
-U23 Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and
-U26 Net-_U10-Pad1_ Net-_U26-Pad2_ Net-_U25-Pad2_ d_and
-U22 Net-_U10-Pad1_ Net-_U22-Pad2_ d_inverter
-U29 Net-_U28-Pad3_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_or
-U28 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and
-U30 Net-_U10-Pad1_ Net-_U30-Pad2_ Net-_U29-Pad2_ d_and
-U27 Net-_U10-Pad1_ Net-_U27-Pad2_ d_inverter
-U33 Net-_U32-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or
-U40 Net-_U38-Pad3_ Net-_U40-Pad2_ Net-_U15-Pad1_ d_or
-U32 Net-_U31-Pad2_ Net-_U32-Pad2_ Net-_U32-Pad3_ d_and
-U34 Net-_U10-Pad1_ Net-_U34-Pad2_ Net-_U33-Pad2_ d_and
-U38 Net-_U37-Pad2_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_and
-U42 Net-_U10-Pad1_ Net-_U42-Pad2_ Net-_U40-Pad2_ d_and
-U31 Net-_U10-Pad1_ Net-_U31-Pad2_ d_inverter
-U37 Net-_U10-Pad1_ Net-_U37-Pad2_ d_inverter
-U39 Net-_U36-Pad3_ Net-_U39-Pad2_ Net-_U18-Pad1_ d_or
-U36 Net-_U36-Pad1_ Net-_U35-Pad2_ Net-_U36-Pad3_ d_and
-U41 Net-_U15-Pad5_ Net-_U10-Pad1_ Net-_U39-Pad2_ d_and
-U9 Net-_U33-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U42-Pad2_ ? d_dff
-U35 Net-_U10-Pad1_ Net-_U35-Pad2_ d_inverter
-U24 Net-_U24-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad3_ Net-_U10-Pad2_ ? d_dff
-U45 Net-_U45-Pad1_ Net-_U44-Pad3_ Net-_U24-Pad1_ d_or
-U46 Net-_U18-Pad5_ Net-_U10-Pad1_ Net-_U45-Pad1_ d_and
-U44 Net-_U44-Pad1_ Net-_U43-Pad2_ Net-_U44-Pad3_ d_and
-U43 Net-_U10-Pad1_ Net-_U43-Pad2_ d_inverter
-U5 Net-_U5-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U13-Pad2_ Net-_U44-Pad1_ Net-_U19-Pad2_ Net-_U23-Pad2_ Net-_U10-Pad2_ Net-_U2-Pad5_ Net-_U30-Pad2_ Net-_U42-Pad2_ Net-_U18-Pad5_ Net-_U28-Pad2_ Net-_U1-Pad5_ Net-_U26-Pad2_ Net-_U34-Pad2_ Net-_U15-Pad5_ Net-_U36-Pad1_ Net-_U32-Pad2_ Net-_U38-Pad2_ Net-_U10-Pad1_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out deleted file mode 100644 index cff41387..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.cir.out +++ /dev/null @@ -1,192 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir
-
-* u3 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff
-* u4 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff
-* u6 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff
-* u15 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff
-* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff
-* u18 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff
-* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or
-* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or
-* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or
-* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u8 net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and
-* u7 net-_u10-pad1_ net-_u7-pad2_ d_inverter
-* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and
-* u16 net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
-* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter
-* u19 net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and
-* u21 net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and
-* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter
-* u25 net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or
-* u23 net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
-* u26 net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and
-* u22 net-_u10-pad1_ net-_u22-pad2_ d_inverter
-* u29 net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or
-* u28 net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and
-* u30 net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and
-* u27 net-_u10-pad1_ net-_u27-pad2_ d_inverter
-* u33 net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
-* u40 net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or
-* u32 net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u34 net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and
-* u38 net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and
-* u42 net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and
-* u31 net-_u10-pad1_ net-_u31-pad2_ d_inverter
-* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter
-* u39 net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or
-* u36 net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and
-* u41 net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and
-* u9 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff
-* u35 net-_u10-pad1_ net-_u35-pad2_ d_inverter
-* u24 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff
-* u45 net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or
-* u46 net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and
-* u44 net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and
-* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter
-* u5 net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_ port
-a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3
-a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4
-a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6
-a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15
-a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2
-a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1
-a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18
-a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11
-a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14
-a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20
-a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8
-a13 net-_u10-pad1_ net-_u7-pad2_ u7
-a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
-a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16
-a16 net-_u10-pad1_ net-_u12-pad2_ u12
-a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19
-a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21
-a19 net-_u10-pad1_ net-_u17-pad2_ u17
-a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
-a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
-a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26
-a23 net-_u10-pad1_ net-_u22-pad2_ u22
-a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
-a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28
-a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30
-a27 net-_u10-pad1_ net-_u27-pad2_ u27
-a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
-a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40
-a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34
-a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38
-a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42
-a34 net-_u10-pad1_ net-_u31-pad2_ u31
-a35 net-_u10-pad1_ net-_u37-pad2_ u37
-a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39
-a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36
-a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41
-a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9
-a40 net-_u10-pad1_ net-_u35-pad2_ u35
-a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24
-a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45
-a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46
-a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44
-a45 net-_u10-pad1_ net-_u43-pad2_ u43
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.ac lin 0 0Hz 0Hz
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro deleted file mode 100644 index ec294cbd..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.pro +++ /dev/null @@ -1,85 +0,0 @@ -update=Sat Jun 22 13:15:27 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[schematic_editor] -version=1 -PageLayoutDescrFile= -PlotDirectoryName= -SubpartIdSeparator=0 -SubpartFirstId=65 -NetFmtName= -SpiceForceRefPrefix=0 -SpiceUseNetNumbers=0 -LabSize=60 -[eeschema] -version=1 -LibDir=../../Abhradip_9bit-ShiftRegister/9bit-ShiftRegister;../../../eSim-1.1.2/kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=microcontrollers -LibName13=dsp -LibName14=microchip -LibName15=analog_switches -LibName16=motorola -LibName17=texas -LibName18=intel -LibName19=audio -LibName20=interface -LibName21=digital-audio -LibName22=philips -LibName23=display -LibName24=cypress -LibName25=siliconi -LibName26=opto -LibName27=atmel -LibName28=contrib -LibName29=valves -LibName30=half-adder -LibName31=9bit-Right_shift_register-cache -LibName32=/home/mallikarjuna/Downloads/Abhradip/Abhradip_9bit-ShiftRegister/9bit-ShiftRegister/9bit-ShiftRegister-cache -LibName33=eSim_Analog -LibName34=eSim_Devices -LibName35=eSim_Digital -LibName36=eSim_Hybrid -LibName37=eSim_Miscellaneous -LibName38=eSim_Plot -LibName39=eSim_Power -LibName40=eSim_Sources -LibName41=eSim_Subckt -LibName42=eSim_User diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch deleted file mode 100644 index b14a8f30..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sch +++ /dev/null @@ -1,1495 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:9bit-Right_shift_register-cache -EELAYER 25 0 -EELAYER END -$Descr A3 16535 11693 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_dff U3 -U 1 1 5C9296A4 -P 5950 4850 -F 0 "U3" H 5950 4850 60 0000 C CNN -F 1 "d_dff" H 5950 5000 60 0000 C CNN -F 2 "" H 5950 4850 60 0000 C CNN -F 3 "" H 5950 4850 60 0000 C CNN - 1 5950 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U4 -U 1 1 5C9296E7 -P 7250 4850 -F 0 "U4" H 7250 4850 60 0000 C CNN -F 1 "d_dff" H 7250 5000 60 0000 C CNN -F 2 "" H 7250 4850 60 0000 C CNN -F 3 "" H 7250 4850 60 0000 C CNN - 1 7250 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U6 -U 1 1 5C92970E -P 8550 4850 -F 0 "U6" H 8550 4850 60 0000 C CNN -F 1 "d_dff" H 8550 5000 60 0000 C CNN -F 2 "" H 8550 4850 60 0000 C CNN -F 3 "" H 8550 4850 60 0000 C CNN - 1 8550 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U15 -U 1 1 5C92975C -P 11150 4850 -F 0 "U15" H 11150 4850 60 0000 C CNN -F 1 "d_dff" H 11150 5000 60 0000 C CNN -F 2 "" H 11150 4850 60 0000 C CNN -F 3 "" H 11150 4850 60 0000 C CNN - 1 11150 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U2 -U 1 1 5C929793 -P 4650 4850 -F 0 "U2" H 4650 4850 60 0000 C CNN -F 1 "d_dff" H 4650 5000 60 0000 C CNN -F 2 "" H 4650 4850 60 0000 C CNN -F 3 "" H 4650 4850 60 0000 C CNN - 1 4650 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U1 -U 1 1 5C9297E2 -P 3350 4850 -F 0 "U1" H 3350 4850 60 0000 C CNN -F 1 "d_dff" H 3350 5000 60 0000 C CNN -F 2 "" H 3350 4850 60 0000 C CNN -F 3 "" H 3350 4850 60 0000 C CNN - 1 3350 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_dff U18 -U 1 1 5C92A1EB -P 12450 4850 -F 0 "U18" H 12450 4850 60 0000 C CNN -F 1 "d_dff" H 12450 5000 60 0000 C CNN -F 2 "" H 12450 4850 60 0000 C CNN -F 3 "" H 12450 4850 60 0000 C CNN - 1 12450 4850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7900 3800 7900 2450 -Wire Wire Line - 8000 3700 8000 2550 -Wire Wire Line - 8100 3600 8100 2650 -Wire Wire Line - 8200 2750 8200 3500 -Wire Wire Line - 8200 2750 8900 2750 -Wire Wire Line - 8100 2650 9300 2650 -Wire Wire Line - 8000 2550 8900 2550 -Wire Wire Line - 7900 2450 9300 2450 -Wire Wire Line - 7800 2350 8900 2350 -Wire Wire Line - 6500 2250 9300 2250 -Wire Wire Line - 3900 2050 9300 2050 -$Comp -L d_or U11 -U 1 1 5C942586 -P 3450 6100 -F 0 "U11" H 3450 6100 60 0000 C CNN -F 1 "d_or" H 3450 6200 60 0000 C CNN -F 2 "" H 3450 6100 60 0000 C CNN -F 3 "" H 3450 6100 60 0000 C CNN - 1 3450 6100 - -1 0 0 1 -$EndComp -$Comp -L d_or U14 -U 1 1 5C9425C0 -P 4550 6100 -F 0 "U14" H 4550 6100 60 0000 C CNN -F 1 "d_or" H 4550 6200 60 0000 C CNN -F 2 "" H 4550 6100 60 0000 C CNN -F 3 "" H 4550 6100 60 0000 C CNN - 1 4550 6100 - -1 0 0 1 -$EndComp -$Comp -L d_or U20 -U 1 1 5C942640 -P 6450 7450 -F 0 "U20" H 6450 7450 60 0000 C CNN -F 1 "d_or" H 6450 7550 60 0000 C CNN -F 2 "" H 6450 7450 60 0000 C CNN -F 3 "" H 6450 7450 60 0000 C CNN - 1 6450 7450 - -1 0 0 1 -$EndComp -$Comp -L d_and U10 -U 1 1 5C9427D3 -P 3300 6950 -F 0 "U10" H 3300 6950 60 0000 C CNN -F 1 "d_and" H 3350 7050 60 0000 C CNN -F 2 "" H 3300 6950 60 0000 C CNN -F 3 "" H 3300 6950 60 0000 C CNN - 1 3300 6950 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U8 -U 1 1 5C942854 -P 2950 6950 -F 0 "U8" H 2950 6950 60 0000 C CNN -F 1 "d_and" H 3000 7050 60 0000 C CNN -F 2 "" H 2950 6950 60 0000 C CNN -F 3 "" H 2950 6950 60 0000 C CNN - 1 2950 6950 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U7 -U 1 1 5C942F4F -P 2850 7850 -F 0 "U7" H 2850 7750 60 0000 C CNN -F 1 "d_inverter" H 2850 8000 60 0000 C CNN -F 2 "" H 2900 7800 60 0000 C CNN -F 3 "" H 2900 7800 60 0000 C CNN - 1 2850 7850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U13 -U 1 1 5C943518 -P 4350 6850 -F 0 "U13" H 4350 6850 60 0000 C CNN -F 1 "d_and" H 4400 6950 60 0000 C CNN -F 2 "" H 4350 6850 60 0000 C CNN -F 3 "" H 4350 6850 60 0000 C CNN - 1 4350 6850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U16 -U 1 1 5C94358F -P 4700 6850 -F 0 "U16" H 4700 6850 60 0000 C CNN -F 1 "d_and" H 4750 6950 60 0000 C CNN -F 2 "" H 4700 6850 60 0000 C CNN -F 3 "" H 4700 6850 60 0000 C CNN - 1 4700 6850 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U12 -U 1 1 5C944206 -P 4250 7850 -F 0 "U12" H 4250 7750 60 0000 C CNN -F 1 "d_inverter" H 4250 8000 60 0000 C CNN -F 2 "" H 4300 7800 60 0000 C CNN -F 3 "" H 4300 7800 60 0000 C CNN - 1 4250 7850 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U19 -U 1 1 5C947143 -P 6350 8200 -F 0 "U19" H 6350 8200 60 0000 C CNN -F 1 "d_and" H 6400 8300 60 0000 C CNN -F 2 "" H 6350 8200 60 0000 C CNN -F 3 "" H 6350 8200 60 0000 C CNN - 1 6350 8200 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U21 -U 1 1 5C9471B3 -P 6700 8200 -F 0 "U21" H 6700 8200 60 0000 C CNN -F 1 "d_and" H 6750 8300 60 0000 C CNN -F 2 "" H 6700 8200 60 0000 C CNN -F 3 "" H 6700 8200 60 0000 C CNN - 1 6700 8200 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U17 -U 1 1 5C94722C -P 5950 8950 -F 0 "U17" H 5950 8850 60 0000 C CNN -F 1 "d_inverter" H 5950 9100 60 0000 C CNN -F 2 "" H 6000 8900 60 0000 C CNN -F 3 "" H 6000 8900 60 0000 C CNN - 1 5950 8950 - 1 0 0 -1 -$EndComp -$Comp -L d_or U25 -U 1 1 5C94A04A -P 7950 6250 -F 0 "U25" H 7950 6250 60 0000 C CNN -F 1 "d_or" H 7950 6350 60 0000 C CNN -F 2 "" H 7950 6250 60 0000 C CNN -F 3 "" H 7950 6250 60 0000 C CNN - 1 7950 6250 - -1 0 0 1 -$EndComp -$Comp -L d_and U23 -U 1 1 5C94A0C3 -P 7800 7050 -F 0 "U23" H 7800 7050 60 0000 C CNN -F 1 "d_and" H 7850 7150 60 0000 C CNN -F 2 "" H 7800 7050 60 0000 C CNN -F 3 "" H 7800 7050 60 0000 C CNN - 1 7800 7050 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U26 -U 1 1 5C94A14D -P 8150 7050 -F 0 "U26" H 8150 7050 60 0000 C CNN -F 1 "d_and" H 8200 7150 60 0000 C CNN -F 2 "" H 8150 7050 60 0000 C CNN -F 3 "" H 8150 7050 60 0000 C CNN - 1 8150 7050 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U22 -U 1 1 5C94A510 -P 7700 8000 -F 0 "U22" H 7700 7900 60 0000 C CNN -F 1 "d_inverter" H 7700 8150 60 0000 C CNN -F 2 "" H 7750 7950 60 0000 C CNN -F 3 "" H 7750 7950 60 0000 C CNN - 1 7700 8000 - 0 -1 -1 0 -$EndComp -$Comp -L d_or U29 -U 1 1 5C94E1FD -P 9900 5850 -F 0 "U29" H 9900 5850 60 0000 C CNN -F 1 "d_or" H 9900 5950 60 0000 C CNN -F 2 "" H 9900 5850 60 0000 C CNN -F 3 "" H 9900 5850 60 0000 C CNN - 1 9900 5850 - -1 0 0 1 -$EndComp -$Comp -L d_and U28 -U 1 1 5C94E286 -P 9750 6650 -F 0 "U28" H 9750 6650 60 0000 C CNN -F 1 "d_and" H 9800 6750 60 0000 C CNN -F 2 "" H 9750 6650 60 0000 C CNN -F 3 "" H 9750 6650 60 0000 C CNN - 1 9750 6650 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U30 -U 1 1 5C94E302 -P 10100 6650 -F 0 "U30" H 10100 6650 60 0000 C CNN -F 1 "d_and" H 10150 6750 60 0000 C CNN -F 2 "" H 10100 6650 60 0000 C CNN -F 3 "" H 10100 6650 60 0000 C CNN - 1 10100 6650 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U27 -U 1 1 5C94E385 -P 9650 7600 -F 0 "U27" H 9650 7500 60 0000 C CNN -F 1 "d_inverter" H 9650 7750 60 0000 C CNN -F 2 "" H 9700 7550 60 0000 C CNN -F 3 "" H 9700 7550 60 0000 C CNN - 1 9650 7600 - 0 -1 -1 0 -$EndComp -$Comp -L d_or U33 -U 1 1 5C94FC0A -P 11150 5850 -F 0 "U33" H 11150 5850 60 0000 C CNN -F 1 "d_or" H 11150 5950 60 0000 C CNN -F 2 "" H 11150 5850 60 0000 C CNN -F 3 "" H 11150 5850 60 0000 C CNN - 1 11150 5850 - -1 0 0 1 -$EndComp -$Comp -L d_or U40 -U 1 1 5C94FC89 -P 12450 5850 -F 0 "U40" H 12450 5850 60 0000 C CNN -F 1 "d_or" H 12450 5950 60 0000 C CNN -F 2 "" H 12450 5850 60 0000 C CNN -F 3 "" H 12450 5850 60 0000 C CNN - 1 12450 5850 - -1 0 0 1 -$EndComp -$Comp -L d_and U32 -U 1 1 5C94FD1B -P 11000 6650 -F 0 "U32" H 11000 6650 60 0000 C CNN -F 1 "d_and" H 11050 6750 60 0000 C CNN -F 2 "" H 11000 6650 60 0000 C CNN -F 3 "" H 11000 6650 60 0000 C CNN - 1 11000 6650 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U34 -U 1 1 5C94FDA6 -P 11350 6650 -F 0 "U34" H 11350 6650 60 0000 C CNN -F 1 "d_and" H 11400 6750 60 0000 C CNN -F 2 "" H 11350 6650 60 0000 C CNN -F 3 "" H 11350 6650 60 0000 C CNN - 1 11350 6650 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U38 -U 1 1 5C94FE38 -P 12300 6650 -F 0 "U38" H 12300 6650 60 0000 C CNN -F 1 "d_and" H 12350 6750 60 0000 C CNN -F 2 "" H 12300 6650 60 0000 C CNN -F 3 "" H 12300 6650 60 0000 C CNN - 1 12300 6650 - 0 -1 -1 0 -$EndComp -$Comp -L d_and U42 -U 1 1 5C94FEC5 -P 12600 6650 -F 0 "U42" H 12600 6650 60 0000 C CNN -F 1 "d_and" H 12650 6750 60 0000 C CNN -F 2 "" H 12600 6650 60 0000 C CNN -F 3 "" H 12600 6650 60 0000 C CNN - 1 12600 6650 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U31 -U 1 1 5C95027B -P 10900 7600 -F 0 "U31" H 10900 7500 60 0000 C CNN -F 1 "d_inverter" H 10900 7750 60 0000 C CNN -F 2 "" H 10950 7550 60 0000 C CNN -F 3 "" H 10950 7550 60 0000 C CNN - 1 10900 7600 - 0 -1 -1 0 -$EndComp -$Comp -L d_inverter U37 -U 1 1 5C950310 -P 12200 7600 -F 0 "U37" H 12200 7500 60 0000 C CNN -F 1 "d_inverter" H 12200 7750 60 0000 C CNN -F 2 "" H 12250 7550 60 0000 C CNN -F 3 "" H 12250 7550 60 0000 C CNN - 1 12200 7600 - 0 -1 -1 0 -$EndComp -$Comp -L d_or U39 -U 1 1 5C956491 -P 12350 3100 -F 0 "U39" H 12350 3100 60 0000 C CNN -F 1 "d_or" H 12350 3200 60 0000 C CNN -F 2 "" H 12350 3100 60 0000 C CNN -F 3 "" H 12350 3100 60 0000 C CNN - 1 12350 3100 - -1 0 0 1 -$EndComp -$Comp -L d_and U36 -U 1 1 5C956C09 -P 12200 2550 -F 0 "U36" H 12200 2550 60 0000 C CNN -F 1 "d_and" H 12250 2650 60 0000 C CNN -F 2 "" H 12200 2550 60 0000 C CNN -F 3 "" H 12200 2550 60 0000 C CNN - 1 12200 2550 - 0 1 1 0 -$EndComp -$Comp -L d_and U41 -U 1 1 5C95766B -P 12500 2550 -F 0 "U41" H 12500 2550 60 0000 C CNN -F 1 "d_and" H 12550 2650 60 0000 C CNN -F 2 "" H 12500 2550 60 0000 C CNN -F 3 "" H 12500 2550 60 0000 C CNN - 1 12500 2550 - 0 1 1 0 -$EndComp -Text Notes 10300 2100 0 60 ~ 0 -IN0 -Text Notes 12050 9000 0 60 ~ 0 -IN1 -Text Notes 10700 9000 0 60 ~ 0 -IN2 -Text Notes 9500 9000 0 60 ~ 0 -IN3 -Text Notes 7500 9050 0 60 ~ 0 -IN4 -Text Notes 6150 9050 0 60 ~ 0 -IN5 -Text Notes 4050 9100 0 60 ~ 0 -IN6 -Text Notes 2750 9050 0 60 ~ 0 -IN7 -Text Notes 12850 8650 0 60 ~ 0 -CI -Text Notes 8700 2850 0 60 ~ 0 -O0 -Text Notes 8500 2750 0 60 ~ 0 -O1 -Text Notes 8700 2650 0 60 ~ 0 -O2 -Text Notes 8500 2550 0 60 ~ 0 -O3 -Text Notes 8700 2450 0 60 ~ 0 -O4 -Text Notes 8500 2350 0 60 ~ 0 -O5 -Text Notes 8700 2250 0 60 ~ 0 -O6 -Text Notes 8500 2150 0 60 ~ 0 -O7 -$Comp -L d_dff U9 -U 1 1 5C92973B -P 9850 4850 -F 0 "U9" H 9850 4850 60 0000 C CNN -F 1 "d_dff" H 9850 5000 60 0000 C CNN -F 2 "" H 9850 4850 60 0000 C CNN -F 3 "" H 9850 4850 60 0000 C CNN - 1 9850 4850 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U35 -U 1 1 5C9582C3 -P 11500 2550 -F 0 "U35" H 11500 2450 60 0000 C CNN -F 1 "d_inverter" H 11500 2700 60 0000 C CNN -F 2 "" H 11550 2500 60 0000 C CNN -F 3 "" H 11550 2500 60 0000 C CNN - 1 11500 2550 - 0 1 1 0 -$EndComp -$Comp -L d_dff U24 -U 1 1 5C95D8E8 -P 3350 3000 -F 0 "U24" H 3350 3000 60 0000 C CNN -F 1 "d_dff" H 3350 3150 60 0000 C CNN -F 2 "" H 3350 3000 60 0000 C CNN -F 3 "" H 3350 3000 60 0000 C CNN - 1 3350 3000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3350 3600 3350 4200 -Wire Wire Line - 2600 4000 12450 4000 -Wire Wire Line - 12450 4000 12450 4200 -Connection ~ 11150 4000 -Wire Wire Line - 11150 4200 11150 4000 -Wire Wire Line - 9850 4200 9850 4000 -Connection ~ 9850 4000 -Wire Wire Line - 8550 4200 8550 4000 -Connection ~ 8550 4000 -Wire Wire Line - 5950 4200 5950 4000 -Connection ~ 5950 4000 -Wire Wire Line - 7250 4200 7250 4000 -Connection ~ 7250 4000 -Wire Wire Line - 4650 4200 4650 4000 -Connection ~ 4650 4000 -Wire Wire Line - 3350 5450 3350 5600 -Wire Wire Line - 2600 5600 12450 5600 -Wire Wire Line - 4650 5600 4650 5450 -Wire Wire Line - 5950 5600 5950 5450 -Connection ~ 4650 5600 -Wire Wire Line - 7250 5600 7250 5450 -Connection ~ 5950 5600 -Wire Wire Line - 8550 5600 8550 5450 -Connection ~ 7250 5600 -Wire Wire Line - 9850 5600 9850 5450 -Connection ~ 8550 5600 -Wire Wire Line - 11150 5600 11150 5450 -Connection ~ 9850 5600 -Wire Wire Line - 12450 5600 12450 5450 -Connection ~ 11150 5600 -Wire Wire Line - 2600 2050 2600 5600 -Connection ~ 3350 4000 -Connection ~ 3350 5600 -Connection ~ 2600 4000 -Wire Wire Line - 3350 2350 3350 2250 -Wire Wire Line - 3350 2250 2600 2250 -Wire Wire Line - 2600 2050 2850 2050 -Connection ~ 2600 2250 -Wire Wire Line - 2800 3300 2650 3300 -Wire Wire Line - 2650 3300 2650 5500 -Wire Wire Line - 2650 5150 2800 5150 -Wire Wire Line - 2650 5500 11850 5500 -Wire Wire Line - 4050 5500 4050 5150 -Wire Wire Line - 4050 5150 4100 5150 -Connection ~ 2650 5150 -Wire Wire Line - 5400 5150 5350 5150 -Wire Wire Line - 5350 5150 5350 5500 -Connection ~ 4050 5500 -Wire Wire Line - 6650 5500 6650 5150 -Wire Wire Line - 6650 5150 6700 5150 -Connection ~ 5350 5500 -Wire Wire Line - 7950 5500 7950 5150 -Wire Wire Line - 7950 5150 8000 5150 -Connection ~ 6650 5500 -Wire Wire Line - 9250 5500 9250 5150 -Wire Wire Line - 9250 5150 9300 5150 -Connection ~ 7950 5500 -Wire Wire Line - 10550 5500 10550 5150 -Wire Wire Line - 10550 5150 10600 5150 -Connection ~ 9250 5500 -Wire Wire Line - 11850 5500 11850 5150 -Wire Wire Line - 11850 5150 11900 5150 -Connection ~ 10550 5500 -Wire Wire Line - 2650 3500 3150 3500 -Wire Wire Line - 3150 3500 3150 3650 -Connection ~ 2650 3500 -Wire Wire Line - 3950 2650 3900 2650 -Wire Wire Line - 3950 2250 3950 2650 -Wire Wire Line - 3950 2250 3750 2250 -Wire Wire Line - 3750 2250 3750 1950 -Text Notes 8700 2050 0 60 ~ 0 -O8 -Wire Wire Line - 13000 4500 13100 4500 -Wire Wire Line - 13100 4500 13100 3500 -Wire Wire Line - 13100 3500 8200 3500 -Wire Wire Line - 8100 3600 11750 3600 -Wire Wire Line - 11750 3600 11750 4500 -Wire Wire Line - 11750 4500 11700 4500 -Wire Wire Line - 8000 3700 10450 3700 -Wire Wire Line - 10450 3700 10450 4500 -Wire Wire Line - 10450 4500 10400 4500 -Wire Wire Line - 7900 3800 9150 3800 -Wire Wire Line - 9150 3800 9150 4500 -Wire Wire Line - 9150 4500 9100 4500 -Wire Wire Line - 7800 2350 7800 4300 -Wire Wire Line - 7800 4300 7850 4300 -Wire Wire Line - 7850 4300 7850 4500 -Wire Wire Line - 7850 4500 7800 4500 -Wire Wire Line - 6500 2250 6500 4300 -Wire Wire Line - 6500 4300 6550 4300 -Wire Wire Line - 6550 4300 6550 4500 -Wire Wire Line - 6550 4500 6500 4500 -Wire Wire Line - 3900 2050 3900 2150 -Wire Wire Line - 3900 2150 4100 2150 -Wire Wire Line - 4100 2150 4100 4250 -Wire Wire Line - 4100 4250 3950 4250 -Wire Wire Line - 3950 4250 3950 4500 -Wire Wire Line - 3950 4500 3900 4500 -$Comp -L d_or U45 -U 1 1 5C9948BA -P 4650 3350 -F 0 "U45" H 4650 3350 60 0000 C CNN -F 1 "d_or" H 4650 3450 60 0000 C CNN -F 2 "" H 4650 3350 60 0000 C CNN -F 3 "" H 4650 3350 60 0000 C CNN - 1 4650 3350 - -1 0 0 1 -$EndComp -$Comp -L d_and U46 -U 1 1 5C994A8D -P 4850 2700 -F 0 "U46" H 4850 2700 60 0000 C CNN -F 1 "d_and" H 4900 2800 60 0000 C CNN -F 2 "" H 4850 2700 60 0000 C CNN -F 3 "" H 4850 2700 60 0000 C CNN - 1 4850 2700 - 0 1 1 0 -$EndComp -$Comp -L d_and U44 -U 1 1 5C994B61 -P 4550 2700 -F 0 "U44" H 4550 2700 60 0000 C CNN -F 1 "d_and" H 4600 2800 60 0000 C CNN -F 2 "" H 4550 2700 60 0000 C CNN -F 3 "" H 4550 2700 60 0000 C CNN - 1 4550 2700 - 0 1 1 0 -$EndComp -$Comp -L d_inverter U43 -U 1 1 5C994C4E -P 4300 2650 -F 0 "U43" H 4300 2550 60 0000 C CNN -F 1 "d_inverter" H 4300 2800 60 0000 C CNN -F 2 "" H 4350 2600 60 0000 C CNN -F 3 "" H 4350 2600 60 0000 C CNN - 1 4300 2650 - 0 1 1 0 -$EndComp -Wire Wire Line - 4300 2950 4400 2950 -Wire Wire Line - 4400 2950 4400 2200 -Wire Wire Line - 4400 2200 4550 2200 -Wire Wire Line - 4550 2200 4550 2250 -Wire Wire Line - 2850 7550 2850 7400 -Wire Wire Line - 2850 8150 2850 8700 -Wire Wire Line - 2850 8700 13000 8700 -Wire Wire Line - 12200 7900 12200 8700 -Connection ~ 12200 8700 -Wire Wire Line - 12200 7300 12200 7100 -Wire Wire Line - 12500 7100 12500 8700 -Connection ~ 12500 8700 -Wire Wire Line - 10900 7300 10900 7100 -Wire Wire Line - 10900 7900 10900 8700 -Connection ~ 10900 8700 -Wire Wire Line - 11250 7100 11250 8700 -Connection ~ 11250 8700 -Wire Wire Line - 9650 7100 9650 7300 -Wire Wire Line - 10000 7100 10000 8700 -Connection ~ 10000 8700 -Wire Wire Line - 9650 7900 9650 8700 -Connection ~ 9650 8700 -Wire Wire Line - 7700 7700 7700 7500 -Wire Wire Line - 7700 8300 7700 8700 -Connection ~ 7700 8700 -Wire Wire Line - 8050 7500 8050 8700 -Connection ~ 8050 8700 -Wire Wire Line - 5650 8950 5650 8700 -Connection ~ 5650 8700 -Wire Wire Line - 6250 8950 6250 8650 -Wire Wire Line - 6600 8650 6600 8700 -Connection ~ 6600 8700 -Wire Wire Line - 3200 7400 3200 8700 -Connection ~ 3200 8700 -Wire Wire Line - 4250 8700 4250 8150 -Connection ~ 4250 8700 -Wire Wire Line - 4250 7550 4250 7300 -Wire Wire Line - 4600 7300 4600 8700 -Connection ~ 4600 8700 -Wire Wire Line - 11500 2850 11500 2950 -Wire Wire Line - 11500 2950 12050 2950 -Wire Wire Line - 12050 2950 12050 2050 -Wire Wire Line - 12050 2050 12200 2050 -Wire Wire Line - 12200 2050 12200 2100 -Wire Wire Line - 11500 2250 11300 2250 -Wire Wire Line - 11300 1900 11300 3450 -Wire Wire Line - 5650 3450 13250 3450 -Wire Wire Line - 13250 3450 13250 8500 -Wire Wire Line - 13250 8500 12750 8500 -Wire Wire Line - 12750 8500 12750 8700 -Connection ~ 12750 8700 -Wire Wire Line - 11300 1900 12500 1900 -Wire Wire Line - 12500 1900 12500 2100 -Connection ~ 11300 2250 -Wire Wire Line - 5650 2000 5650 3450 -Connection ~ 11300 3450 -Wire Wire Line - 3750 1950 8900 1950 -Wire Wire Line - 4300 2350 4300 2000 -Wire Wire Line - 4300 2000 5650 2000 -Wire Wire Line - 4850 2250 4850 2000 -Connection ~ 4850 2000 -Wire Wire Line - 2800 2300 2800 2650 -Wire Wire Line - 2800 2300 4050 2300 -Wire Wire Line - 4050 2300 4050 3400 -Wire Wire Line - 4050 3400 4200 3400 -Wire Wire Line - 4600 3150 4600 3250 -Wire Wire Line - 4600 3250 5100 3250 -Wire Wire Line - 5100 3250 5100 3350 -Wire Wire Line - 4900 3150 5150 3150 -Wire Wire Line - 5150 3150 5150 3450 -Wire Wire Line - 5150 3450 5100 3450 -Wire Wire Line - 4650 2250 4650 2100 -Wire Wire Line - 4650 2100 5450 2100 -Wire Wire Line - 5450 2100 5450 2500 -Wire Wire Line - 4950 2250 5100 2250 -Wire Wire Line - 5100 2250 5100 3000 -Wire Wire Line - 5100 3000 8200 3000 -Connection ~ 8200 3000 -Wire Wire Line - 3950 2550 4000 2550 -Wire Wire Line - 4000 2550 4000 7450 -Wire Wire Line - 4000 7450 3300 7450 -Wire Wire Line - 3300 7450 3300 7400 -Connection ~ 3950 2550 -Wire Wire Line - 2800 4500 2750 4500 -Wire Wire Line - 2750 4500 2750 6150 -Wire Wire Line - 2750 6150 3000 6150 -Wire Wire Line - 2900 6500 2900 6300 -Wire Wire Line - 2900 6300 3900 6300 -Wire Wire Line - 3900 6300 3900 6200 -Wire Wire Line - 3900 6100 3950 6100 -Wire Wire Line - 3950 6100 3950 6450 -Wire Wire Line - 3950 6450 3250 6450 -Wire Wire Line - 3250 6450 3250 6500 -Wire Wire Line - 2950 7400 2950 9100 -Wire Wire Line - 2950 9100 2700 9100 -Wire Wire Line - 2700 9100 2700 9050 -Wire Wire Line - 3950 9100 4350 9100 -Wire Wire Line - 4350 9100 4350 7300 -Wire Wire Line - 4100 4150 4400 4150 -Wire Wire Line - 4400 4150 4400 5850 -Connection ~ 4100 4150 -Wire Wire Line - 4400 5850 5300 5850 -Wire Wire Line - 5300 5850 5300 7450 -Wire Wire Line - 5300 7450 4700 7450 -Wire Wire Line - 4700 7450 4700 7300 -Wire Wire Line - 4650 6400 5150 6400 -Wire Wire Line - 5150 6400 5150 6200 -Wire Wire Line - 5150 6200 5000 6200 -Wire Wire Line - 4100 6150 4100 5300 -Wire Wire Line - 4100 5300 4200 5300 -Wire Wire Line - 4200 5300 4200 4600 -Wire Wire Line - 4200 4600 4050 4600 -Wire Wire Line - 4050 4600 4050 4500 -Wire Wire Line - 4050 4500 4100 4500 -Wire Wire Line - 4300 6400 4300 6300 -Wire Wire Line - 4300 6300 5100 6300 -Wire Wire Line - 5100 6300 5100 6100 -Wire Wire Line - 5100 6100 5000 6100 -Wire Wire Line - 6350 8650 6350 9100 -Wire Wire Line - 6350 9100 5850 9100 -Wire Wire Line - 5400 4500 5350 4500 -Wire Wire Line - 5350 4500 5350 5100 -Wire Wire Line - 5350 5100 5300 5100 -Wire Wire Line - 5300 5100 5300 5350 -Wire Wire Line - 5300 5350 5600 5350 -Wire Wire Line - 5600 5350 5600 7500 -Wire Wire Line - 5600 7500 6000 7500 -Wire Wire Line - 5250 4500 5200 4500 -Wire Wire Line - 5200 2150 8900 2150 -Wire Wire Line - 5200 2150 5200 4250 -Wire Wire Line - 5200 4250 5250 4250 -Wire Wire Line - 5250 4250 5250 4500 -Wire Wire Line - 5250 4350 5750 4350 -Wire Wire Line - 5750 4350 5750 7250 -Wire Wire Line - 5750 7250 7250 7250 -Connection ~ 5250 4350 -Wire Wire Line - 7250 7250 7250 8850 -Wire Wire Line - 7250 8850 6700 8850 -Wire Wire Line - 6700 8850 6700 8650 -Wire Wire Line - 6650 7750 6650 7700 -Wire Wire Line - 6650 7700 7050 7700 -Wire Wire Line - 7050 7700 7050 7550 -Wire Wire Line - 7050 7550 6900 7550 -Wire Wire Line - 6300 7750 6300 7650 -Wire Wire Line - 6300 7650 7150 7650 -Wire Wire Line - 7150 7650 7150 7450 -Wire Wire Line - 7150 7450 6900 7450 -Wire Wire Line - 7450 9050 7800 9050 -Wire Wire Line - 7800 9050 7800 7500 -Wire Wire Line - 7750 6600 7750 6450 -Wire Wire Line - 7750 6450 8550 6450 -Wire Wire Line - 8550 6450 8550 6350 -Wire Wire Line - 8550 6350 8400 6350 -Wire Wire Line - 8400 6250 8600 6250 -Wire Wire Line - 8600 6250 8600 6500 -Wire Wire Line - 8600 6500 8100 6500 -Wire Wire Line - 8100 6500 8100 6600 -Wire Wire Line - 6600 4500 6700 4500 -Wire Wire Line - 6600 4500 6600 6300 -Wire Wire Line - 6600 6300 7500 6300 -Wire Wire Line - 6500 4150 7100 4150 -Wire Wire Line - 7100 4150 7100 6050 -Wire Wire Line - 7100 6050 8800 6050 -Wire Wire Line - 8800 6050 8800 7600 -Wire Wire Line - 8800 7600 8150 7600 -Wire Wire Line - 8150 7600 8150 7500 -Connection ~ 6500 4150 -Wire Wire Line - 9750 7100 9750 9050 -Wire Wire Line - 9750 9050 9400 9050 -Wire Wire Line - 11000 7100 11000 9050 -Wire Wire Line - 11000 9050 10650 9050 -Wire Wire Line - 12300 7100 12300 9050 -Wire Wire Line - 12300 9050 12050 9050 -Wire Wire Line - 12250 6200 12250 6100 -Wire Wire Line - 12250 6100 13000 6100 -Wire Wire Line - 13000 6100 13000 5950 -Wire Wire Line - 13000 5950 12900 5950 -Wire Wire Line - 12900 5850 13100 5850 -Wire Wire Line - 13100 5850 13100 6150 -Wire Wire Line - 13100 6150 12550 6150 -Wire Wire Line - 12550 6150 12550 6200 -Wire Wire Line - 8000 4500 7900 4500 -Wire Wire Line - 7900 4500 7900 5900 -Wire Wire Line - 7900 5900 9450 5900 -Wire Wire Line - 7800 4150 8400 4150 -Wire Wire Line - 8400 4150 8400 5700 -Wire Wire Line - 8400 5700 10550 5700 -Wire Wire Line - 10550 5700 10550 7250 -Wire Wire Line - 10550 7250 10100 7250 -Wire Wire Line - 10100 7250 10100 7100 -Connection ~ 7800 4150 -Wire Wire Line - 9700 6200 9700 6100 -Wire Wire Line - 9700 6100 10450 6100 -Wire Wire Line - 10450 6100 10450 5950 -Wire Wire Line - 10450 5950 10350 5950 -Wire Wire Line - 10350 5850 10500 5850 -Wire Wire Line - 10500 5850 10500 6150 -Wire Wire Line - 10500 6150 10050 6150 -Wire Wire Line - 10050 6150 10050 6200 -Wire Wire Line - 9300 4500 9200 4500 -Wire Wire Line - 9200 4500 9200 5300 -Wire Wire Line - 9200 5300 10650 5300 -Wire Wire Line - 10650 5300 10650 5900 -Wire Wire Line - 10650 5900 10700 5900 -Wire Wire Line - 9150 4200 9650 4200 -Wire Wire Line - 9650 4200 9650 4850 -Wire Wire Line - 9650 4850 10450 4850 -Wire Wire Line - 10450 4850 10450 5650 -Wire Wire Line - 10450 5650 11750 5650 -Connection ~ 9150 4200 -Wire Wire Line - 11750 5650 11750 7300 -Wire Wire Line - 11750 7300 11350 7300 -Wire Wire Line - 11350 7300 11350 7100 -Wire Wire Line - 10950 6200 10950 6100 -Wire Wire Line - 10950 6100 11650 6100 -Wire Wire Line - 11650 6100 11650 5950 -Wire Wire Line - 11650 5950 11600 5950 -Wire Wire Line - 11600 5850 11700 5850 -Wire Wire Line - 11700 5850 11700 6150 -Wire Wire Line - 11700 6150 11300 6150 -Wire Wire Line - 11300 6150 11300 6200 -Wire Wire Line - 10600 4500 10600 4950 -Wire Wire Line - 10600 4950 11350 4950 -Wire Wire Line - 11350 4950 11350 5450 -Wire Wire Line - 11350 5450 11950 5450 -Wire Wire Line - 11950 5450 11950 5900 -Wire Wire Line - 11950 5900 12000 5900 -Wire Wire Line - 10450 4200 11000 4200 -Wire Wire Line - 11000 4200 11000 4700 -Wire Wire Line - 11000 4700 11800 4700 -Wire Wire Line - 11800 4700 11800 5350 -Wire Wire Line - 11800 5350 13150 5350 -Wire Wire Line - 13150 5350 13150 7250 -Connection ~ 10450 4200 -Wire Wire Line - 13150 7250 12600 7250 -Wire Wire Line - 12600 7250 12600 7100 -Wire Wire Line - 11900 4500 11800 4500 -Wire Wire Line - 11800 4500 11800 3150 -Wire Wire Line - 11800 3150 11900 3150 -Wire Wire Line - 12550 3000 12900 3000 -Wire Wire Line - 12900 3000 12900 3100 -Wire Wire Line - 12900 3100 12800 3100 -Wire Wire Line - 12250 3000 12400 3000 -Wire Wire Line - 12400 3000 12400 2850 -Wire Wire Line - 12400 2850 13200 2850 -Wire Wire Line - 13200 2850 13200 3200 -Wire Wire Line - 13200 3200 12800 3200 -Wire Wire Line - 10200 2000 12300 2000 -Wire Wire Line - 12300 2000 12300 2100 -Wire Wire Line - 11650 3600 11650 1950 -Wire Wire Line - 11650 1950 12600 1950 -Wire Wire Line - 12600 1950 12600 2100 -Connection ~ 11650 3600 -$Comp -L PORT U5 -U 12 1 5C982725 -P 9150 2750 -F 0 "U5" H 9200 2850 30 0000 C CNN -F 1 "PORT" H 9150 2750 30 0000 C CNN -F 2 "" H 9150 2750 60 0000 C CNN -F 3 "" H 9150 2750 60 0000 C CNN - 12 9150 2750 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 17 1 5C9827C2 -P 9550 2650 -F 0 "U5" H 9600 2750 30 0000 C CNN -F 1 "PORT" H 9550 2650 30 0000 C CNN -F 2 "" H 9550 2650 60 0000 C CNN -F 3 "" H 9550 2650 60 0000 C CNN - 17 9550 2650 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 11 1 5C98283D -P 9150 2550 -F 0 "U5" H 9200 2650 30 0000 C CNN -F 1 "PORT" H 9150 2550 30 0000 C CNN -F 2 "" H 9150 2550 60 0000 C CNN -F 3 "" H 9150 2550 60 0000 C CNN - 11 9150 2550 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 16 1 5C9828CC -P 9550 2450 -F 0 "U5" H 9600 2550 30 0000 C CNN -F 1 "PORT" H 9550 2450 30 0000 C CNN -F 2 "" H 9550 2450 60 0000 C CNN -F 3 "" H 9550 2450 60 0000 C CNN - 16 9550 2450 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 10 1 5C982957 -P 9150 2350 -F 0 "U5" H 9200 2450 30 0000 C CNN -F 1 "PORT" H 9150 2350 30 0000 C CNN -F 2 "" H 9150 2350 60 0000 C CNN -F 3 "" H 9150 2350 60 0000 C CNN - 10 9150 2350 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 15 1 5C9829D6 -P 9550 2250 -F 0 "U5" H 9600 2350 30 0000 C CNN -F 1 "PORT" H 9550 2250 30 0000 C CNN -F 2 "" H 9550 2250 60 0000 C CNN -F 3 "" H 9550 2250 60 0000 C CNN - 15 9550 2250 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 9 1 5C982A5D -P 9150 2150 -F 0 "U5" H 9200 2250 30 0000 C CNN -F 1 "PORT" H 9150 2150 30 0000 C CNN -F 2 "" H 9150 2150 60 0000 C CNN -F 3 "" H 9150 2150 60 0000 C CNN - 9 9150 2150 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 14 1 5C982AE0 -P 9550 2050 -F 0 "U5" H 9600 2150 30 0000 C CNN -F 1 "PORT" H 9550 2050 30 0000 C CNN -F 2 "" H 9550 2050 60 0000 C CNN -F 3 "" H 9550 2050 60 0000 C CNN - 14 9550 2050 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 8 1 5C982B81 -P 9150 1950 -F 0 "U5" H 9200 2050 30 0000 C CNN -F 1 "PORT" H 9150 1950 30 0000 C CNN -F 2 "" H 9150 1950 60 0000 C CNN -F 3 "" H 9150 1950 60 0000 C CNN - 8 9150 1950 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 21 1 5C983602 -P 13250 8700 -F 0 "U5" H 13300 8800 30 0000 C CNN -F 1 "PORT" H 13250 8700 30 0000 C CNN -F 2 "" H 13250 8700 60 0000 C CNN -F 3 "" H 13250 8700 60 0000 C CNN - 21 13250 8700 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 18 1 5C983C2F -P 9950 2000 -F 0 "U5" H 10000 2100 30 0000 C CNN -F 1 "PORT" H 9950 2000 30 0000 C CNN -F 2 "" H 9950 2000 60 0000 C CNN -F 3 "" H 9950 2000 60 0000 C CNN - 18 9950 2000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 20 1 5C984048 -P 11800 9050 -F 0 "U5" H 11850 9150 30 0000 C CNN -F 1 "PORT" H 11800 9050 30 0000 C CNN -F 2 "" H 11800 9050 60 0000 C CNN -F 3 "" H 11800 9050 60 0000 C CNN - 20 11800 9050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 19 1 5C9840D3 -P 10400 9050 -F 0 "U5" H 10450 9150 30 0000 C CNN -F 1 "PORT" H 10400 9050 30 0000 C CNN -F 2 "" H 10400 9050 60 0000 C CNN -F 3 "" H 10400 9050 60 0000 C CNN - 19 10400 9050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 13 1 5C984164 -P 9150 9050 -F 0 "U5" H 9200 9150 30 0000 C CNN -F 1 "PORT" H 9150 9050 30 0000 C CNN -F 2 "" H 9150 9050 60 0000 C CNN -F 3 "" H 9150 9050 60 0000 C CNN - 13 9150 9050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 7 1 5C985678 -P 7200 9050 -F 0 "U5" H 7250 9150 30 0000 C CNN -F 1 "PORT" H 7200 9050 30 0000 C CNN -F 2 "" H 7200 9050 60 0000 C CNN -F 3 "" H 7200 9050 60 0000 C CNN - 7 7200 9050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 6 1 5C985709 -P 5600 9100 -F 0 "U5" H 5650 9200 30 0000 C CNN -F 1 "PORT" H 5600 9100 30 0000 C CNN -F 2 "" H 5600 9100 60 0000 C CNN -F 3 "" H 5600 9100 60 0000 C CNN - 6 5600 9100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 4 1 5C98579A -P 3700 9100 -F 0 "U5" H 3750 9200 30 0000 C CNN -F 1 "PORT" H 3700 9100 30 0000 C CNN -F 2 "" H 3700 9100 60 0000 C CNN -F 3 "" H 3700 9100 60 0000 C CNN - 4 3700 9100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 1 1 5C98582D -P 2700 8800 -F 0 "U5" H 2750 8900 30 0000 C CNN -F 1 "PORT" H 2700 8800 30 0000 C CNN -F 2 "" H 2700 8800 60 0000 C CNN -F 3 "" H 2700 8800 60 0000 C CNN - 1 2700 8800 - 0 1 1 0 -$EndComp -$Comp -L PORT U5 -U 5 1 5C98694B -P 5450 2750 -F 0 "U5" H 5500 2850 30 0000 C CNN -F 1 "PORT" H 5450 2750 30 0000 C CNN -F 2 "" H 5450 2750 60 0000 C CNN -F 3 "" H 5450 2750 60 0000 C CNN - 5 5450 2750 - 0 -1 -1 0 -$EndComp -Text Notes 5400 2450 1 60 ~ 0 -IN8 -Text Notes 2650 2000 0 60 ~ 0 -GND -$Comp -L PORT U5 -U 2 1 5C986B72 -P 3100 2050 -F 0 "U5" H 3150 2150 30 0000 C CNN -F 1 "PORT" H 3100 2050 30 0000 C CNN -F 2 "" H 3100 2050 60 0000 C CNN -F 3 "" H 3100 2050 60 0000 C CNN - 2 3100 2050 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 3 1 5C986C25 -P 3150 3900 -F 0 "U5" H 3200 4000 30 0000 C CNN -F 1 "PORT" H 3150 3900 30 0000 C CNN -F 2 "" H 3150 3900 60 0000 C CNN -F 3 "" H 3150 3900 60 0000 C CNN - 3 3150 3900 - 0 -1 -1 0 -$EndComp -Text Notes 2850 3600 0 60 ~ 0 -CLK -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub deleted file mode 100644 index e94cb0f4..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register.sub +++ /dev/null @@ -1,186 +0,0 @@ -* Subcircuit 9bit-Right_shift_register
-.subckt 9bit-Right_shift_register net-_u5-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u13-pad2_ net-_u44-pad1_ net-_u19-pad2_ net-_u23-pad2_ net-_u10-pad2_ net-_u2-pad5_ net-_u30-pad2_ net-_u42-pad2_ net-_u18-pad5_ net-_u28-pad2_ net-_u1-pad5_ net-_u26-pad2_ net-_u34-pad2_ net-_u15-pad5_ net-_u36-pad1_ net-_u32-pad2_ net-_u38-pad2_ net-_u10-pad1_
-* c:\esim\esim\src\subcircuitlibrary\9bit-right_shift_register\9bit-right_shift_register.cir
-* u3 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? d_dff
-* u4 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? d_dff
-* u6 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? d_dff
-* u15 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? d_dff
-* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? d_dff
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? d_dff
-* u18 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? d_dff
-* u11 net-_u11-pad1_ net-_u10-pad3_ net-_u1-pad1_ d_or
-* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or
-* u20 net-_u20-pad1_ net-_u19-pad3_ net-_u20-pad3_ d_or
-* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
-* u8 net-_u7-pad2_ net-_u5-pad1_ net-_u11-pad1_ d_and
-* u7 net-_u10-pad1_ net-_u7-pad2_ d_inverter
-* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_and
-* u16 net-_u10-pad1_ net-_u1-pad5_ net-_u14-pad1_ d_and
-* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter
-* u19 net-_u17-pad2_ net-_u19-pad2_ net-_u19-pad3_ d_and
-* u21 net-_u10-pad1_ net-_u2-pad5_ net-_u20-pad1_ d_and
-* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter
-* u25 net-_u23-pad3_ net-_u25-pad2_ net-_u25-pad3_ d_or
-* u23 net-_u22-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
-* u26 net-_u10-pad1_ net-_u26-pad2_ net-_u25-pad2_ d_and
-* u22 net-_u10-pad1_ net-_u22-pad2_ d_inverter
-* u29 net-_u28-pad3_ net-_u29-pad2_ net-_u29-pad3_ d_or
-* u28 net-_u27-pad2_ net-_u28-pad2_ net-_u28-pad3_ d_and
-* u30 net-_u10-pad1_ net-_u30-pad2_ net-_u29-pad2_ d_and
-* u27 net-_u10-pad1_ net-_u27-pad2_ d_inverter
-* u33 net-_u32-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or
-* u40 net-_u38-pad3_ net-_u40-pad2_ net-_u15-pad1_ d_or
-* u32 net-_u31-pad2_ net-_u32-pad2_ net-_u32-pad3_ d_and
-* u34 net-_u10-pad1_ net-_u34-pad2_ net-_u33-pad2_ d_and
-* u38 net-_u37-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and
-* u42 net-_u10-pad1_ net-_u42-pad2_ net-_u40-pad2_ d_and
-* u31 net-_u10-pad1_ net-_u31-pad2_ d_inverter
-* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter
-* u39 net-_u36-pad3_ net-_u39-pad2_ net-_u18-pad1_ d_or
-* u36 net-_u36-pad1_ net-_u35-pad2_ net-_u36-pad3_ d_and
-* u41 net-_u15-pad5_ net-_u10-pad1_ net-_u39-pad2_ d_and
-* u9 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? d_dff
-* u35 net-_u10-pad1_ net-_u35-pad2_ d_inverter
-* u24 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? d_dff
-* u45 net-_u45-pad1_ net-_u44-pad3_ net-_u24-pad1_ d_or
-* u46 net-_u18-pad5_ net-_u10-pad1_ net-_u45-pad1_ d_and
-* u44 net-_u44-pad1_ net-_u43-pad2_ net-_u44-pad3_ d_and
-* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter
-a1 net-_u20-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u26-pad2_ ? u3
-a2 net-_u25-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u30-pad2_ ? u4
-a3 net-_u29-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u34-pad2_ ? u6
-a4 net-_u15-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u15-pad5_ ? u15
-a5 net-_u14-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u2-pad5_ ? u2
-a6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad5_ ? u1
-a7 net-_u18-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u18-pad5_ ? u18
-a8 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u1-pad1_ u11
-a9 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14
-a10 [net-_u20-pad1_ net-_u19-pad3_ ] net-_u20-pad3_ u20
-a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a12 [net-_u7-pad2_ net-_u5-pad1_ ] net-_u11-pad1_ u8
-a13 net-_u10-pad1_ net-_u7-pad2_ u7
-a14 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
-a15 [net-_u10-pad1_ net-_u1-pad5_ ] net-_u14-pad1_ u16
-a16 net-_u10-pad1_ net-_u12-pad2_ u12
-a17 [net-_u17-pad2_ net-_u19-pad2_ ] net-_u19-pad3_ u19
-a18 [net-_u10-pad1_ net-_u2-pad5_ ] net-_u20-pad1_ u21
-a19 net-_u10-pad1_ net-_u17-pad2_ u17
-a20 [net-_u23-pad3_ net-_u25-pad2_ ] net-_u25-pad3_ u25
-a21 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
-a22 [net-_u10-pad1_ net-_u26-pad2_ ] net-_u25-pad2_ u26
-a23 net-_u10-pad1_ net-_u22-pad2_ u22
-a24 [net-_u28-pad3_ net-_u29-pad2_ ] net-_u29-pad3_ u29
-a25 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u28-pad3_ u28
-a26 [net-_u10-pad1_ net-_u30-pad2_ ] net-_u29-pad2_ u30
-a27 net-_u10-pad1_ net-_u27-pad2_ u27
-a28 [net-_u32-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33
-a29 [net-_u38-pad3_ net-_u40-pad2_ ] net-_u15-pad1_ u40
-a30 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u32-pad3_ u32
-a31 [net-_u10-pad1_ net-_u34-pad2_ ] net-_u33-pad2_ u34
-a32 [net-_u37-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38
-a33 [net-_u10-pad1_ net-_u42-pad2_ ] net-_u40-pad2_ u42
-a34 net-_u10-pad1_ net-_u31-pad2_ u31
-a35 net-_u10-pad1_ net-_u37-pad2_ u37
-a36 [net-_u36-pad3_ net-_u39-pad2_ ] net-_u18-pad1_ u39
-a37 [net-_u36-pad1_ net-_u35-pad2_ ] net-_u36-pad3_ u36
-a38 [net-_u15-pad5_ net-_u10-pad1_ ] net-_u39-pad2_ u41
-a39 net-_u33-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u42-pad2_ ? u9
-a40 net-_u10-pad1_ net-_u35-pad2_ u35
-a41 net-_u24-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad3_ net-_u10-pad2_ ? u24
-a42 [net-_u45-pad1_ net-_u44-pad3_ ] net-_u24-pad1_ u45
-a43 [net-_u18-pad5_ net-_u10-pad1_ ] net-_u45-pad1_ u46
-a44 [net-_u44-pad1_ net-_u43-pad2_ ] net-_u44-pad3_ u44
-a45 net-_u10-pad1_ net-_u43-pad2_ u43
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u3 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u4 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u6 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u15 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u2 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u1 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u18 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u20 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u7 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u12 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u17 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u25 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u23 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u26 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u29 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u28 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u30 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u27 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u33 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u40 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u32 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u34 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u38 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u42 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u31 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u37 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u39 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u36 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u41 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u9 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u35 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_dff, NgSpice Name: d_dff
-.model u24 d_dff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 data_load=1.0e-12 fall_delay=1.0e-9 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u45 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u46 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u44 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u43 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 9bit-Right_shift_register
\ No newline at end of file diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml b/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml deleted file mode 100644 index 28c290d4..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/9bit-Right_shift_register_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u3 name="type">d_dff<field1 name="Enter IC (default=0)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter value for Set Load (default=1.0e-12)" /><field4 name="Enter Clk Delay (default=1.0e-9)" /><field5 name="Enter value for Clk Load (default=1.0e-12)" /><field6 name="Enter Reset Delay (default=1.0)" /><field7 name="Enter value for Data Load (default=1.0e-12)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter value for Reset Load (default=1.0e-12)" /><field10 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_dff<field11 name="Enter IC (default=0)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter value for Set Load (default=1.0e-12)" /><field14 name="Enter Clk Delay (default=1.0e-9)" /><field15 name="Enter value for Clk Load (default=1.0e-12)" /><field16 name="Enter Reset Delay (default=1.0)" /><field17 name="Enter value for Data Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter value for Reset Load (default=1.0e-12)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /></u4><u6 name="type">d_dff<field21 name="Enter IC (default=0)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter value for Set Load (default=1.0e-12)" /><field24 name="Enter Clk Delay (default=1.0e-9)" /><field25 name="Enter value for Clk Load (default=1.0e-12)" /><field26 name="Enter Reset Delay (default=1.0)" /><field27 name="Enter value for Data Load (default=1.0e-12)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter value for Reset Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u6><u15 name="type">d_dff<field31 name="Enter IC (default=0)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter value for Set Load (default=1.0e-12)" /><field34 name="Enter Clk Delay (default=1.0e-9)" /><field35 name="Enter value for Clk Load (default=1.0e-12)" /><field36 name="Enter Reset Delay (default=1.0)" /><field37 name="Enter value for Data Load (default=1.0e-12)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter value for Reset Load (default=1.0e-12)" /><field40 name="Enter Rise Delay (default=1.0e-9)" /></u15><u2 name="type">d_dff<field41 name="Enter IC (default=0)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter value for Set Load (default=1.0e-12)" /><field44 name="Enter Clk Delay (default=1.0e-9)" /><field45 name="Enter value for Clk Load (default=1.0e-12)" /><field46 name="Enter Reset Delay (default=1.0)" /><field47 name="Enter value for Data Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter value for Reset Load (default=1.0e-12)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /></u2><u1 name="type">d_dff<field51 name="Enter IC (default=0)" /><field52 name="Enter Set Delay (default=1.0e-9)" /><field53 name="Enter value for Set Load (default=1.0e-12)" /><field54 name="Enter Clk Delay (default=1.0e-9)" /><field55 name="Enter value for Clk Load (default=1.0e-12)" /><field56 name="Enter Reset Delay (default=1.0)" /><field57 name="Enter value for Data Load (default=1.0e-12)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter value for Reset Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u1><u18 name="type">d_dff<field61 name="Enter IC (default=0)" /><field62 name="Enter Set Delay (default=1.0e-9)" /><field63 name="Enter value for Set Load (default=1.0e-12)" /><field64 name="Enter Clk Delay (default=1.0e-9)" /><field65 name="Enter value for Clk Load (default=1.0e-12)" /><field66 name="Enter Reset Delay (default=1.0)" /><field67 name="Enter value for Data Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter value for Reset Load (default=1.0e-12)" /><field70 name="Enter Rise Delay (default=1.0e-9)" /></u18><u11 name="type">d_or<field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /><field73 name="Enter Rise Delay (default=1.0e-9)" /></u11><u14 name="type">d_or<field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /><field76 name="Enter Rise Delay (default=1.0e-9)" /></u14><u20 name="type">d_or<field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /><field79 name="Enter Rise Delay (default=1.0e-9)" /></u20><u10 name="type">d_and<field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /><field82 name="Enter Rise Delay (default=1.0e-9)" /></u10><u8 name="type">d_and<field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /><field85 name="Enter Rise Delay (default=1.0e-9)" /></u8><u7 name="type">d_inverter<field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /><field88 name="Enter Rise Delay (default=1.0e-9)" /></u7><u13 name="type">d_and<field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /><field91 name="Enter Rise Delay (default=1.0e-9)" /></u13><u16 name="type">d_and<field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /><field94 name="Enter Rise Delay (default=1.0e-9)" /></u16><u12 name="type">d_inverter<field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /><field97 name="Enter Rise Delay (default=1.0e-9)" /></u12><u19 name="type">d_and<field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /><field100 name="Enter Rise Delay (default=1.0e-9)" /></u19><u21 name="type">d_and<field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Rise Delay (default=1.0e-9)" /></u21><u17 name="type">d_inverter<field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /><field106 name="Enter Rise Delay (default=1.0e-9)" /></u17><u25 name="type">d_or<field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /></u25><u23 name="type">d_and<field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /><field112 name="Enter Rise Delay (default=1.0e-9)" /></u23><u26 name="type">d_and<field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /><field115 name="Enter Rise Delay (default=1.0e-9)" /></u26><u22 name="type">d_inverter<field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /><field118 name="Enter Rise Delay (default=1.0e-9)" /></u22><u29 name="type">d_or<field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /><field121 name="Enter Rise Delay (default=1.0e-9)" /></u29><u28 name="type">d_and<field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /><field124 name="Enter Rise Delay (default=1.0e-9)" /></u28><u30 name="type">d_and<field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /><field127 name="Enter Rise Delay (default=1.0e-9)" /></u30><u27 name="type">d_inverter<field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /><field130 name="Enter Rise Delay (default=1.0e-9)" /></u27><u33 name="type">d_or<field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /><field133 name="Enter Rise Delay (default=1.0e-9)" /></u33><u40 name="type">d_or<field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /><field136 name="Enter Rise Delay (default=1.0e-9)" /></u40><u32 name="type">d_and<field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /></u32><u34 name="type">d_and<field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /><field142 name="Enter Rise Delay (default=1.0e-9)" /></u34><u38 name="type">d_and<field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /><field145 name="Enter Rise Delay (default=1.0e-9)" /></u38><u42 name="type">d_and<field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /><field148 name="Enter Rise Delay (default=1.0e-9)" /></u42><u31 name="type">d_inverter<field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /><field151 name="Enter Rise Delay (default=1.0e-9)" /></u31><u37 name="type">d_inverter<field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /><field154 name="Enter Rise Delay (default=1.0e-9)" /></u37><u39 name="type">d_or<field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /><field157 name="Enter Rise Delay (default=1.0e-9)" /></u39><u36 name="type">d_and<field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /><field160 name="Enter Rise Delay (default=1.0e-9)" /></u36><u41 name="type">d_and<field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /><field163 name="Enter Rise Delay (default=1.0e-9)" /></u41><u9 name="type">d_dff<field164 name="Enter IC (default=0)" /><field165 name="Enter Set Delay (default=1.0e-9)" /><field166 name="Enter value for Set Load (default=1.0e-12)" /><field167 name="Enter Clk Delay (default=1.0e-9)" /><field168 name="Enter value for Clk Load (default=1.0e-12)" /><field169 name="Enter Reset Delay (default=1.0)" /><field170 name="Enter value for Data Load (default=1.0e-12)" /><field171 name="Enter Fall Delay (default=1.0e-9)" /><field172 name="Enter value for Reset Load (default=1.0e-12)" /><field173 name="Enter Rise Delay (default=1.0e-9)" /></u9><u35 name="type">d_inverter<field174 name="Enter Fall Delay (default=1.0e-9)" /><field175 name="Enter Input Load (default=1.0e-12)" /><field176 name="Enter Rise Delay (default=1.0e-9)" /></u35><u24 name="type">d_dff<field177 name="Enter IC (default=0)" /><field178 name="Enter Set Delay (default=1.0e-9)" /><field179 name="Enter value for Set Load (default=1.0e-12)" /><field180 name="Enter Clk Delay (default=1.0e-9)" /><field181 name="Enter value for Clk Load (default=1.0e-12)" /><field182 name="Enter Reset Delay (default=1.0)" /><field183 name="Enter value for Data Load (default=1.0e-12)" /><field184 name="Enter Fall Delay (default=1.0e-9)" /><field185 name="Enter value for Reset Load (default=1.0e-12)" /><field186 name="Enter Rise Delay (default=1.0e-9)" /></u24><u45 name="type">d_or<field187 name="Enter Fall Delay (default=1.0e-9)" /><field188 name="Enter Input Load (default=1.0e-12)" /><field189 name="Enter Rise Delay (default=1.0e-9)" /></u45><u46 name="type">d_and<field190 name="Enter Fall Delay (default=1.0e-9)" /><field191 name="Enter Input Load (default=1.0e-12)" /><field192 name="Enter Rise Delay (default=1.0e-9)" /></u46><u44 name="type">d_and<field193 name="Enter Fall Delay (default=1.0e-9)" /><field194 name="Enter Input Load (default=1.0e-12)" /><field195 name="Enter Rise Delay (default=1.0e-9)" /></u44><u43 name="type">d_inverter<field196 name="Enter Fall Delay (default=1.0e-9)" /><field197 name="Enter Input Load (default=1.0e-12)" /><field198 name="Enter Rise Delay (default=1.0e-9)" /></u43></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis b/src/SubcircuitLibrary/9bit-Right_shift_register/analysis deleted file mode 100644 index 52ccc5ec..00000000 --- a/src/SubcircuitLibrary/9bit-Right_shift_register/analysis +++ /dev/null @@ -1 +0,0 @@ -.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/AD620-cache.lib b/src/SubcircuitLibrary/AD620/AD620-cache.lib deleted file mode 100644 index b2ef0045..00000000 --- a/src/SubcircuitLibrary/AD620/AD620-cache.lib +++ /dev/null @@ -1,82 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# eSim_R -# -DEF eSim_R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "eSim_R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -# lm_741 -# -DEF lm_741 X 0 40 Y Y 1 F N -F0 "X" -200 0 60 H V C CNN -F1 "lm_741" -350 400 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N -X off_null 1 -50 400 200 D 50 38 1 1 I -X in- 2 -550 150 200 R 50 38 1 1 I -X in+ 3 -550 -100 200 R 50 38 1 1 I -X V- 4 -150 -450 200 U 50 38 1 1 I -X off_null 5 50 350 200 D 50 38 1 1 I -X out 6 550 0 200 L 50 38 1 1 O -X V+ 7 -150 450 200 D 50 38 1 1 I -X NC 8 150 -300 200 U 50 38 1 1 N -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/AD620/AD620.cir b/src/SubcircuitLibrary/AD620/AD620.cir deleted file mode 100644 index c82fdfd6..00000000 --- a/src/SubcircuitLibrary/AD620/AD620.cir +++ /dev/null @@ -1,26 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\AD620\AD620.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/19 16:16:13
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X2 Net-_R8-Pad1_ Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_R10-Pad2_ Net-_R10-Pad1_ Net-_R1-Pad1_ Net-_U1-Pad7_ ? lm_741
-X1 Net-_R7-Pad2_ Net-_R2-Pad1_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R9-Pad2_ Net-_R2-Pad2_ Net-_U1-Pad7_ ? lm_741
-X3 Net-_R11-Pad2_ Net-_R4-Pad1_ Net-_R3-Pad1_ Net-_R10-Pad2_ Net-_R12-Pad2_ Net-_R6-Pad1_ Net-_U1-Pad7_ ? lm_741
-R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 24.7k
-R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 24.7k
-R4 Net-_R4-Pad1_ Net-_R1-Pad1_ 10k
-R3 Net-_R3-Pad1_ Net-_R2-Pad2_ 10k
-R6 Net-_R6-Pad1_ Net-_R4-Pad1_ 10k
-R5 Net-_R5-Pad1_ Net-_R3-Pad1_ 10k
-U1 Net-_R1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R10-Pad2_ Net-_R5-Pad1_ Net-_R6-Pad1_ Net-_U1-Pad7_ Net-_R2-Pad1_ PORT
-R8 Net-_R8-Pad1_ Net-_R10-Pad2_ 0.297k
-R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 1k
-R7 Net-_R10-Pad2_ Net-_R7-Pad2_ 0.297k
-R9 Net-_R10-Pad2_ Net-_R9-Pad2_ 1k
-R12 Net-_R10-Pad2_ Net-_R12-Pad2_ 1k
-R11 Net-_R10-Pad2_ Net-_R11-Pad2_ 0.75732k
-
-.end
diff --git a/src/SubcircuitLibrary/AD620/AD620.cir.out b/src/SubcircuitLibrary/AD620/AD620.cir.out deleted file mode 100644 index 082780e2..00000000 --- a/src/SubcircuitLibrary/AD620/AD620.cir.out +++ /dev/null @@ -1,28 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir
-
-.include lm_741.sub
-x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741
-x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741
-x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741
-r1 net-_r1-pad1_ net-_r1-pad2_ 24.7k
-r2 net-_r2-pad1_ net-_r2-pad2_ 24.7k
-r4 net-_r4-pad1_ net-_r1-pad1_ 10k
-r3 net-_r3-pad1_ net-_r2-pad2_ 10k
-r6 net-_r6-pad1_ net-_r4-pad1_ 10k
-r5 net-_r5-pad1_ net-_r3-pad1_ 10k
-* u1 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_ port
-r8 net-_r8-pad1_ net-_r10-pad2_ 0.297k
-r10 net-_r10-pad1_ net-_r10-pad2_ 1k
-r7 net-_r10-pad2_ net-_r7-pad2_ 0.297k
-r9 net-_r10-pad2_ net-_r9-pad2_ 1k
-r12 net-_r10-pad2_ net-_r12-pad2_ 1k
-r11 net-_r10-pad2_ net-_r11-pad2_ 0.75732k
-.tran 0e-03 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/AD620/AD620.pro b/src/SubcircuitLibrary/AD620/AD620.pro deleted file mode 100644 index 21e55e98..00000000 --- a/src/SubcircuitLibrary/AD620/AD620.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=Thu Jun 27 12:48:03 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_Sources -LibName10=eSim_User -LibName11=eSim_Subckt diff --git a/src/SubcircuitLibrary/AD620/AD620.sch b/src/SubcircuitLibrary/AD620/AD620.sch deleted file mode 100644 index 8724fe19..00000000 --- a/src/SubcircuitLibrary/AD620/AD620.sch +++ /dev/null @@ -1,424 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:AD620-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L lm_741 X2 -U 1 1 5CEE7415 -P 3800 2750 -F 0 "X2" H 3600 2750 60 0000 C CNN -F 1 "lm_741" H 3700 2500 60 0000 C CNN -F 2 "" H 3800 2750 60 0000 C CNN -F 3 "" H 3800 2750 60 0000 C CNN - 1 3800 2750 - 1 0 0 1 -$EndComp -$Comp -L lm_741 X1 -U 1 1 5CEE7416 -P 3750 5650 -F 0 "X1" H 3550 5650 60 0000 C CNN -F 1 "lm_741" H 3650 5400 60 0000 C CNN -F 2 "" H 3750 5650 60 0000 C CNN -F 3 "" H 3750 5650 60 0000 C CNN - 1 3750 5650 - 1 0 0 -1 -$EndComp -$Comp -L lm_741 X3 -U 1 1 5CEE7417 -P 6800 4050 -F 0 "X3" H 6600 4050 60 0000 C CNN -F 1 "lm_741" H 6700 3800 60 0000 C CNN -F 2 "" H 6800 4050 60 0000 C CNN -F 3 "" H 6800 4050 60 0000 C CNN - 1 6800 4050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3600 7150 1700 7150 -Wire Wire Line - 3600 6100 3600 7150 -Wire Wire Line - 6650 6700 3600 6700 -Wire Wire Line - 6650 4500 6650 6700 -Connection ~ 3600 6700 -$Comp -L eSim_R R1 -U 1 1 5CEE741A -P 4550 3350 -F 0 "R1" H 4600 3480 50 0000 C CNN -F 1 "24.7k" H 4600 3400 50 0000 C CNN -F 2 "" H 4600 3330 30 0000 C CNN -F 3 "" V 4600 3400 30 0000 C CNN - 1 4550 3350 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R2 -U 1 1 5CEE741C -P 4550 5000 -F 0 "R2" H 4600 5130 50 0000 C CNN -F 1 "24.7k" H 4600 5050 50 0000 C CNN -F 2 "" H 4600 4980 30 0000 C CNN -F 3 "" V 4600 5050 30 0000 C CNN - 1 4550 5000 - 0 1 1 0 -$EndComp -Wire Wire Line - 4600 5200 4600 5650 -Wire Wire Line - 4300 5650 4900 5650 -Wire Wire Line - 4600 4450 4600 4900 -Wire Wire Line - 4600 3550 4600 4150 -Wire Wire Line - 4600 3250 4600 2750 -Wire Wire Line - 4350 2750 5000 2750 -Wire Wire Line - 4600 3800 2900 3800 -Wire Wire Line - 2900 3800 2900 2900 -Wire Wire Line - 2900 2900 3250 2900 -Connection ~ 4600 3800 -Wire Wire Line - 4600 4700 2900 4700 -Wire Wire Line - 2900 4700 2900 5500 -Wire Wire Line - 2900 5500 3200 5500 -Connection ~ 4600 4700 -$Comp -L eSim_R R4 -U 1 1 5CEE741D -P 5200 2700 -F 0 "R4" H 5250 2830 50 0000 C CNN -F 1 "10k" H 5250 2750 50 0000 C CNN -F 2 "" H 5250 2680 30 0000 C CNN -F 3 "" V 5250 2750 30 0000 C CNN - 1 5200 2700 - -1 0 0 1 -$EndComp -$Comp -L eSim_R R3 -U 1 1 5CEE741E -P 5100 5600 -F 0 "R3" H 5150 5730 50 0000 C CNN -F 1 "10k" H 5150 5650 50 0000 C CNN -F 2 "" H 5150 5580 30 0000 C CNN -F 3 "" V 5150 5650 30 0000 C CNN - 1 5100 5600 - -1 0 0 1 -$EndComp -Connection ~ 4600 5650 -Wire Wire Line - 5200 5650 6200 5650 -Wire Wire Line - 5950 5650 5950 4150 -Wire Wire Line - 5950 4150 6250 4150 -Wire Wire Line - 6250 3900 5950 3900 -Wire Wire Line - 5950 3900 5950 2750 -Wire Wire Line - 5300 2750 6450 2750 -Connection ~ 4600 2750 -$Comp -L eSim_R R6 -U 1 1 5CEE741F -P 6650 2700 -F 0 "R6" H 6700 2830 50 0000 C CNN -F 1 "10k" H 6700 2750 50 0000 C CNN -F 2 "" H 6700 2680 30 0000 C CNN -F 3 "" V 6700 2750 30 0000 C CNN - 1 6650 2700 - -1 0 0 1 -$EndComp -$Comp -L eSim_R R5 -U 1 1 5CEE7420 -P 6400 5600 -F 0 "R5" H 6450 5730 50 0000 C CNN -F 1 "10k" H 6450 5650 50 0000 C CNN -F 2 "" H 6450 5580 30 0000 C CNN -F 3 "" V 6450 5650 30 0000 C CNN - 1 6400 5600 - -1 0 0 1 -$EndComp -Connection ~ 5950 5650 -Connection ~ 5950 2750 -Wire Wire Line - 6750 2750 7650 2750 -Wire Wire Line - 7350 4050 7850 4050 -Wire Wire Line - 2200 1150 6300 1150 -Wire Wire Line - 6300 1150 6300 3600 -Wire Wire Line - 6300 3600 6650 3600 -Wire Wire Line - 2700 1150 2700 3550 -Wire Wire Line - 2700 3550 3650 3550 -Wire Wire Line - 3650 3550 3650 3200 -Connection ~ 2700 1150 -Wire Wire Line - 3600 5200 3600 3550 -Connection ~ 3600 3550 -Wire Wire Line - 2000 1800 2000 7150 -Wire Wire Line - 2000 1800 3650 1800 -Wire Wire Line - 3650 1800 3650 2300 -Connection ~ 2000 7150 -Connection ~ 7650 4050 -Wire Wire Line - 6500 5650 7200 5650 -Wire Wire Line - 1850 2650 3250 2650 -$Comp -L PORT U1 -U 2 1 5CEE7CF8 -P 1600 2650 -F 0 "U1" H 1650 2750 30 0000 C CNN -F 1 "PORT" H 1600 2650 30 0000 C CNN -F 2 "" H 1600 2650 60 0000 C CNN -F 3 "" H 1600 2650 60 0000 C CNN - 2 1600 2650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CEE7E32 -P 1500 5800 -F 0 "U1" H 1550 5900 30 0000 C CNN -F 1 "PORT" H 1500 5800 30 0000 C CNN -F 2 "" H 1500 5800 60 0000 C CNN -F 3 "" H 1500 5800 60 0000 C CNN - 3 1500 5800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CEE7FF8 -P 1450 7150 -F 0 "U1" H 1500 7250 30 0000 C CNN -F 1 "PORT" H 1450 7150 30 0000 C CNN -F 2 "" H 1450 7150 60 0000 C CNN -F 3 "" H 1450 7150 60 0000 C CNN - 4 1450 7150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5CEE80BC -P 1950 1150 -F 0 "U1" H 2000 1250 30 0000 C CNN -F 1 "PORT" H 1950 1150 30 0000 C CNN -F 2 "" H 1950 1150 60 0000 C CNN -F 3 "" H 1950 1150 60 0000 C CNN - 7 1950 1150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CEE8180 -P 4350 4150 -F 0 "U1" H 4400 4250 30 0000 C CNN -F 1 "PORT" H 4350 4150 30 0000 C CNN -F 2 "" H 4350 4150 60 0000 C CNN -F 3 "" H 4350 4150 60 0000 C CNN - 1 4350 4150 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CEE8456 -P 4350 4450 -F 0 "U1" H 4400 4550 30 0000 C CNN -F 1 "PORT" H 4350 4450 30 0000 C CNN -F 2 "" H 4350 4450 60 0000 C CNN -F 3 "" H 4350 4450 60 0000 C CNN - 8 4350 4450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CEE84A1 -P 7450 5650 -F 0 "U1" H 7500 5750 30 0000 C CNN -F 1 "PORT" H 7450 5650 30 0000 C CNN -F 2 "" H 7450 5650 60 0000 C CNN -F 3 "" H 7450 5650 60 0000 C CNN - 5 7450 5650 - -1 0 0 1 -$EndComp -Wire Wire Line - 7650 2750 7650 4050 -$Comp -L PORT U1 -U 6 1 5CEE8938 -P 8100 4050 -F 0 "U1" H 8150 4150 30 0000 C CNN -F 1 "PORT" H 8100 4050 30 0000 C CNN -F 2 "" H 8100 4050 60 0000 C CNN -F 3 "" H 8100 4050 60 0000 C CNN - 6 8100 4050 - -1 0 0 1 -$EndComp -Wire Wire Line - 1750 5800 3200 5800 -Wire Wire Line - 3200 5800 3200 5750 -$Comp -L eSim_R R8 -U 1 1 5CEFB54F -P 3700 3350 -F 0 "R8" H 3750 3480 50 0000 C CNN -F 1 "0.297k" H 3750 3400 50 0000 C CNN -F 2 "" H 3750 3330 30 0000 C CNN -F 3 "" V 3750 3400 30 0000 C CNN - 1 3700 3350 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R10 -U 1 1 5CEFB5A3 -P 4000 3350 -F 0 "R10" H 4050 3480 50 0000 C CNN -F 1 "1k" H 4050 3400 50 0000 C CNN -F 2 "" H 4050 3330 30 0000 C CNN -F 3 "" V 4050 3400 30 0000 C CNN - 1 4000 3350 - 0 1 1 0 -$EndComp -Wire Wire Line - 4050 3250 4050 3100 -Wire Wire Line - 4050 3100 3850 3100 -Wire Wire Line - 3750 3150 3750 3250 -Wire Wire Line - 3750 3550 3750 3650 -Wire Wire Line - 3750 3650 4050 3650 -Wire Wire Line - 4050 3650 4050 3550 -Wire Wire Line - 3900 3650 3900 3950 -Wire Wire Line - 3900 3950 2000 3950 -Connection ~ 2000 3950 -Connection ~ 3900 3650 -$Comp -L eSim_R R7 -U 1 1 5CEFB900 -P 3650 4950 -F 0 "R7" H 3700 5080 50 0000 C CNN -F 1 "0.297k" H 3700 5000 50 0000 C CNN -F 2 "" H 3700 4930 30 0000 C CNN -F 3 "" V 3700 5000 30 0000 C CNN - 1 3650 4950 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R9 -U 1 1 5CEFB962 -P 3950 4950 -F 0 "R9" H 4000 5080 50 0000 C CNN -F 1 "1k" H 4000 5000 50 0000 C CNN -F 2 "" H 4000 4930 30 0000 C CNN -F 3 "" V 4000 5000 30 0000 C CNN - 1 3950 4950 - 0 1 1 0 -$EndComp -Wire Wire Line - 4000 4800 4000 4850 -Wire Wire Line - 3700 4800 4000 4800 -Wire Wire Line - 3700 4800 3700 4850 -Wire Wire Line - 3700 5150 3700 5250 -Wire Wire Line - 3800 5300 3800 5150 -Wire Wire Line - 3800 5150 4000 5150 -Wire Wire Line - 3900 4800 3900 4500 -Wire Wire Line - 3900 4500 2000 4500 -Connection ~ 2000 4500 -Connection ~ 3900 4800 -$Comp -L eSim_R R12 -U 1 1 5CEFB846 -P 7050 3350 -F 0 "R12" H 7100 3480 50 0000 C CNN -F 1 "1k" H 7100 3400 50 0000 C CNN -F 2 "" H 7100 3330 30 0000 C CNN -F 3 "" V 7100 3400 30 0000 C CNN - 1 7050 3350 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R11 -U 1 1 5CEFB8CA -P 6700 3350 -F 0 "R11" H 6750 3480 50 0000 C CNN -F 1 "0.75732k" H 6750 3400 50 0000 C CNN -F 2 "" H 6750 3330 30 0000 C CNN -F 3 "" V 6750 3400 30 0000 C CNN - 1 6700 3350 - 0 1 1 0 -$EndComp -Wire Wire Line - 6750 3550 6750 3650 -Wire Wire Line - 6750 3250 6750 3100 -Wire Wire Line - 6750 3100 7500 3100 -Wire Wire Line - 7100 3100 7100 3250 -Wire Wire Line - 7100 3550 7100 3700 -Wire Wire Line - 7100 3700 6850 3700 -Wire Wire Line - 7500 3100 7500 4650 -Wire Wire Line - 7500 4650 6650 4650 -Connection ~ 6650 4650 -Connection ~ 7100 3100 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/AD620/AD620.sub b/src/SubcircuitLibrary/AD620/AD620.sub deleted file mode 100644 index 1be97dbd..00000000 --- a/src/SubcircuitLibrary/AD620/AD620.sub +++ /dev/null @@ -1,22 +0,0 @@ -* Subcircuit AD620
-.subckt AD620 net-_r1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_r10-pad2_ net-_r5-pad1_ net-_r6-pad1_ net-_u1-pad7_ net-_r2-pad1_
-* c:\users\malli\esim\src\subcircuitlibrary\ad620\ad620.cir
-.include lm_741.sub
-x2 net-_r8-pad1_ net-_r1-pad2_ net-_u1-pad2_ net-_r10-pad2_ net-_r10-pad1_ net-_r1-pad1_ net-_u1-pad7_ ? lm_741
-x1 net-_r7-pad2_ net-_r2-pad1_ net-_u1-pad3_ net-_r10-pad2_ net-_r9-pad2_ net-_r2-pad2_ net-_u1-pad7_ ? lm_741
-x3 net-_r11-pad2_ net-_r4-pad1_ net-_r3-pad1_ net-_r10-pad2_ net-_r12-pad2_ net-_r6-pad1_ net-_u1-pad7_ ? lm_741
-r1 net-_r1-pad1_ net-_r1-pad2_ 24.7k
-r2 net-_r2-pad1_ net-_r2-pad2_ 24.7k
-r4 net-_r4-pad1_ net-_r1-pad1_ 10k
-r3 net-_r3-pad1_ net-_r2-pad2_ 10k
-r6 net-_r6-pad1_ net-_r4-pad1_ 10k
-r5 net-_r5-pad1_ net-_r3-pad1_ 10k
-r8 net-_r8-pad1_ net-_r10-pad2_ 0.297k
-r10 net-_r10-pad1_ net-_r10-pad2_ 1k
-r7 net-_r10-pad2_ net-_r7-pad2_ 0.297k
-r9 net-_r10-pad2_ net-_r9-pad2_ 1k
-r12 net-_r10-pad2_ net-_r12-pad2_ 1k
-r11 net-_r10-pad2_ net-_r11-pad2_ 0.75732k
-* Control Statements
-
-.ends AD620
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml b/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml deleted file mode 100644 index 3a4f8217..00000000 --- a/src/SubcircuitLibrary/AD620/AD620_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/NPN.lib b/src/SubcircuitLibrary/AD620/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/AD620/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/AD620/PNP.lib b/src/SubcircuitLibrary/AD620/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/AD620/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/AD620/analysis b/src/SubcircuitLibrary/AD620/analysis deleted file mode 100644 index cf94dd7f..00000000 --- a/src/SubcircuitLibrary/AD620/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-03 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/lm_741-cache.lib b/src/SubcircuitLibrary/AD620/lm_741-cache.lib deleted file mode 100644 index 6e908886..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741-cache.lib +++ /dev/null @@ -1,119 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_C
-#
-DEF eSim_C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "eSim_C" 25 -100 50 H V L CNN
-F2 "" 38 -150 30 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 40 40 1 1 P
-X ~ 2 0 -150 110 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir b/src/SubcircuitLibrary/AD620/lm_741.cir deleted file mode 100644 index b7989199..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741.cir +++ /dev/null @@ -1,43 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
-Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
-Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP
-Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP
-Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
-Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP
-Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP
-Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN
-Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN
-R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k
-R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k
-R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k
-Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN
-Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN
-R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k
-R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k
-Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
-Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
-Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN
-R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k
-R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k
-C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p
-Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN
-Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN
-R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k
-R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50
-Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN
-Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN
-Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN
-R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25
-R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50
-Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP
-U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT
-
-.end
diff --git a/src/SubcircuitLibrary/AD620/lm_741.cir.out b/src/SubcircuitLibrary/AD620/lm_741.cir.out deleted file mode 100644 index 0184209e..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741.cir.out +++ /dev/null @@ -1,46 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
-
-.include npn_1.lib
-.include pnp_1.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
-q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
-q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
-q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
-q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
-q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
-q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
-r1 net-_q7-pad3_ net-_q12-pad3_ 1k
-r2 net-_q3-pad3_ net-_q12-pad3_ 50k
-r3 net-_q8-pad3_ net-_q12-pad3_ 1k
-q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
-q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
-r4 net-_q13-pad3_ net-_q12-pad3_ 5k
-r11 net-_q10-pad1_ net-_q12-pad1_ 39k
-q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
-r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k
-r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k
-c1 net-_c1-pad1_ net-_c1-pad2_ 30p
-q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
-q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
-r5 net-_q15-pad2_ net-_q12-pad3_ 50k
-r6 net-_q15-pad3_ net-_q12-pad3_ 50
-q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
-q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
-q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
-r9 net-_q18-pad3_ net-_q20-pad3_ 25
-r10 net-_q20-pad3_ net-_q19-pad3_ 50
-q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
-* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/AD620/lm_741.pro b/src/SubcircuitLibrary/AD620/lm_741.pro deleted file mode 100644 index d7d4217f..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=05/25/19 14:52:30
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/AD620/lm_741.sch b/src/SubcircuitLibrary/AD620/lm_741.sch deleted file mode 100644 index 6a74cf22..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741.sch +++ /dev/null @@ -1,697 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:lm_741-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_NPN Q1
-U 1 1 5CE90A7B
-P 2650 2700
-F 0 "Q1" H 2550 2750 50 0000 R CNN
-F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN
-F 2 "" H 2850 2800 29 0000 C CNN
-F 3 "" H 2650 2700 60 0000 C CNN
- 1 2650 2700
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q2
-U 1 1 5CE90A7C
-P 4300 2700
-F 0 "Q2" H 4200 2750 50 0000 R CNN
-F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN
-F 2 "" H 4500 2800 29 0000 C CNN
-F 3 "" H 4300 2700 60 0000 C CNN
- 1 4300 2700
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q6
-U 1 1 5CE90A7D
-P 3000 3200
-F 0 "Q6" H 2900 3250 50 0000 R CNN
-F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN
-F 2 "" H 3200 3300 29 0000 C CNN
-F 3 "" H 3000 3200 60 0000 C CNN
- 1 3000 3200
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q5
-U 1 1 5CE90A7E
-P 3950 3200
-F 0 "Q5" H 3850 3250 50 0000 R CNN
-F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN
-F 2 "" H 4150 3300 29 0000 C CNN
-F 3 "" H 3950 3200 60 0000 C CNN
- 1 3950 3200
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5CE90A7F
-P 3300 4000
-F 0 "Q3" H 3200 4050 50 0000 R CNN
-F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN
-F 2 "" H 3500 4100 29 0000 C CNN
-F 3 "" H 3300 4000 60 0000 C CNN
- 1 3300 4000
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q4
-U 1 1 5CE90A80
-P 3850 2000
-F 0 "Q4" H 3750 2050 50 0000 R CNN
-F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN
-F 2 "" H 4050 2100 29 0000 C CNN
-F 3 "" H 3850 2000 60 0000 C CNN
- 1 3850 2000
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q9
-U 1 1 5CE90A81
-P 5200 2000
-F 0 "Q9" H 5100 2050 50 0000 R CNN
-F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN
-F 2 "" H 5400 2100 29 0000 C CNN
-F 3 "" H 5200 2000 60 0000 C CNN
- 1 5200 2000
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_NPN Q8
-U 1 1 5CE90A82
-P 3950 4600
-F 0 "Q8" H 3850 4650 50 0000 R CNN
-F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN
-F 2 "" H 4150 4700 29 0000 C CNN
-F 3 "" H 3950 4600 60 0000 C CNN
- 1 3950 4600
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q7
-U 1 1 5CE90A83
-P 3000 4600
-F 0 "Q7" H 2900 4650 50 0000 R CNN
-F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN
-F 2 "" H 3200 4700 29 0000 C CNN
-F 3 "" H 3000 4600 60 0000 C CNN
- 1 3000 4600
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R1
-U 1 1 5CE90A84
-P 2850 5200
-F 0 "R1" H 2900 5330 50 0000 C CNN
-F 1 "1k" H 2900 5250 50 0000 C CNN
-F 2 "" H 2900 5180 30 0000 C CNN
-F 3 "" V 2900 5250 30 0000 C CNN
- 1 2850 5200
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R2
-U 1 1 5CE90A85
-P 3550 5200
-F 0 "R2" H 3600 5330 50 0000 C CNN
-F 1 "50k" H 3600 5250 50 0000 C CNN
-F 2 "" H 3600 5180 30 0000 C CNN
-F 3 "" V 3600 5250 30 0000 C CNN
- 1 3550 5200
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R3
-U 1 1 5CE90A86
-P 4000 5200
-F 0 "R3" H 4050 5330 50 0000 C CNN
-F 1 "1k" H 4050 5250 50 0000 C CNN
-F 2 "" H 4050 5180 30 0000 C CNN
-F 3 "" V 4050 5250 30 0000 C CNN
- 1 4000 5200
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q12
-U 1 1 5CE90A87
-P 6300 4700
-F 0 "Q12" H 6200 4750 50 0000 R CNN
-F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN
-F 2 "" H 6500 4800 29 0000 C CNN
-F 3 "" H 6300 4700 60 0000 C CNN
- 1 6300 4700
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q13
-U 1 1 5CE90A88
-P 5400 4700
-F 0 "Q13" H 5300 4750 50 0000 R CNN
-F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN
-F 2 "" H 5600 4800 29 0000 C CNN
-F 3 "" H 5400 4700 60 0000 C CNN
- 1 5400 4700
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R4
-U 1 1 5CE90A89
-P 5250 5200
-F 0 "R4" H 5300 5330 50 0000 C CNN
-F 1 "5k" H 5300 5250 50 0000 C CNN
-F 2 "" H 5300 5180 30 0000 C CNN
-F 3 "" V 5300 5250 30 0000 C CNN
- 1 5250 5200
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5CE90A8A
-P 6350 2750
-F 0 "R11" H 6400 2880 50 0000 C CNN
-F 1 "39k" H 6400 2800 50 0000 C CNN
-F 2 "" H 6400 2730 30 0000 C CNN
-F 3 "" V 6400 2800 30 0000 C CNN
- 1 6350 2750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_PNP Q10
-U 1 1 5CE90A8B
-P 6500 1950
-F 0 "Q10" H 6400 2000 50 0000 R CNN
-F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN
-F 2 "" H 6700 2050 29 0000 C CNN
-F 3 "" H 6500 1950 60 0000 C CNN
- 1 6500 1950
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q11
-U 1 1 5CE90A8C
-P 7500 1950
-F 0 "Q11" H 7400 2000 50 0000 R CNN
-F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN
-F 2 "" H 7700 2050 29 0000 C CNN
-F 3 "" H 7500 1950 60 0000 C CNN
- 1 7500 1950
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_NPN Q14
-U 1 1 5CE90A8D
-P 7500 3050
-F 0 "Q14" H 7400 3100 50 0000 R CNN
-F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN
-F 2 "" H 7700 3150 29 0000 C CNN
-F 3 "" H 7500 3050 60 0000 C CNN
- 1 7500 3050
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R8
-U 1 1 5CE90A8E
-P 7300 2600
-F 0 "R8" H 7350 2730 50 0000 C CNN
-F 1 "4.5k" H 7350 2650 50 0000 C CNN
-F 2 "" H 7350 2580 30 0000 C CNN
-F 3 "" V 7350 2650 30 0000 C CNN
- 1 7300 2600
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_R R7
-U 1 1 5CE90A8F
-P 7300 3400
-F 0 "R7" H 7350 3530 50 0000 C CNN
-F 1 "7.5k" H 7350 3450 50 0000 C CNN
-F 2 "" H 7350 3380 30 0000 C CNN
-F 3 "" V 7350 3450 30 0000 C CNN
- 1 7300 3400
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_C C1
-U 1 1 5CE90A90
-P 6600 3200
-F 0 "C1" H 6625 3300 50 0000 L CNN
-F 1 "30p" H 6625 3100 50 0000 L CNN
-F 2 "" H 6638 3050 30 0000 C CNN
-F 3 "" H 6600 3200 60 0000 C CNN
- 1 6600 3200
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q16
-U 1 1 5CE90A91
-P 7050 3950
-F 0 "Q16" H 6950 4000 50 0000 R CNN
-F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN
-F 2 "" H 7250 4050 29 0000 C CNN
-F 3 "" H 7050 3950 60 0000 C CNN
- 1 7050 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q15
-U 1 1 5CE90A92
-P 7500 4300
-F 0 "Q15" H 7400 4350 50 0000 R CNN
-F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN
-F 2 "" H 7700 4400 29 0000 C CNN
-F 3 "" H 7500 4300 60 0000 C CNN
- 1 7500 4300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R5
-U 1 1 5CE90A93
-P 7100 5050
-F 0 "R5" H 7150 5180 50 0000 C CNN
-F 1 "50k" H 7150 5100 50 0000 C CNN
-F 2 "" H 7150 5030 30 0000 C CNN
-F 3 "" V 7150 5100 30 0000 C CNN
- 1 7100 5050
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R6
-U 1 1 5CE90A94
-P 7550 5050
-F 0 "R6" H 7600 5180 50 0000 C CNN
-F 1 "50" H 7600 5100 50 0000 C CNN
-F 2 "" H 7600 5030 30 0000 C CNN
-F 3 "" V 7600 5100 30 0000 C CNN
- 1 7550 5050
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q17
-U 1 1 5CE90A95
-P 6800 4700
-F 0 "Q17" H 6700 4750 50 0000 R CNN
-F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN
-F 2 "" H 7000 4800 29 0000 C CNN
-F 3 "" H 6800 4700 60 0000 C CNN
- 1 6800 4700
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q18
-U 1 1 5CE90A96
-P 8800 2300
-F 0 "Q18" H 8700 2350 50 0000 R CNN
-F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN
-F 2 "" H 9000 2400 29 0000 C CNN
-F 3 "" H 8800 2300 60 0000 C CNN
- 1 8800 2300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q20
-U 1 1 5CE90A97
-P 8400 2750
-F 0 "Q20" H 8300 2800 50 0000 R CNN
-F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN
-F 2 "" H 8600 2850 29 0000 C CNN
-F 3 "" H 8400 2750 60 0000 C CNN
- 1 8400 2750
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R9
-U 1 1 5CE90A98
-P 8850 3000
-F 0 "R9" H 8900 3130 50 0000 C CNN
-F 1 "25" H 8900 3050 50 0000 C CNN
-F 2 "" H 8900 2980 30 0000 C CNN
-F 3 "" V 8900 3050 30 0000 C CNN
- 1 8850 3000
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R10
-U 1 1 5CE90A99
-P 8850 3750
-F 0 "R10" H 8900 3880 50 0000 C CNN
-F 1 "50" H 8900 3800 50 0000 C CNN
-F 2 "" H 8900 3730 30 0000 C CNN
-F 3 "" V 8900 3800 30 0000 C CNN
- 1 8850 3750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_PNP Q19
-U 1 1 5CE90A9A
-P 8800 4600
-F 0 "Q19" H 8700 4650 50 0000 R CNN
-F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN
-F 2 "" H 9000 4700 29 0000 C CNN
-F 3 "" H 8800 4600 60 0000 C CNN
- 1 8800 4600
- 1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5CE90A9B
-P 1900 1200
-F 0 "U1" H 1950 1300 30 0000 C CNN
-F 1 "PORT" H 1900 1200 30 0000 C CNN
-F 2 "" H 1900 1200 60 0000 C CNN
-F 3 "" H 1900 1200 60 0000 C CNN
- 3 1900 1200
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5CE90A9C
-P 4500 1050
-F 0 "U1" H 4550 1150 30 0000 C CNN
-F 1 "PORT" H 4500 1050 30 0000 C CNN
-F 2 "" H 4500 1050 60 0000 C CNN
-F 3 "" H 4500 1050 60 0000 C CNN
- 2 4500 1050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5CE90A9D
-P 9750 1650
-F 0 "U1" H 9800 1750 30 0000 C CNN
-F 1 "PORT" H 9750 1650 30 0000 C CNN
-F 2 "" H 9750 1650 60 0000 C CNN
-F 3 "" H 9750 1650 60 0000 C CNN
- 7 9750 1650
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5CE90A9E
-P 9750 3500
-F 0 "U1" H 9800 3600 30 0000 C CNN
-F 1 "PORT" H 9750 3500 30 0000 C CNN
-F 2 "" H 9750 3500 60 0000 C CNN
-F 3 "" H 9750 3500 60 0000 C CNN
- 6 9750 3500
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5CE90A9F
-P 9700 5550
-F 0 "U1" H 9750 5650 30 0000 C CNN
-F 1 "PORT" H 9700 5550 30 0000 C CNN
-F 2 "" H 9700 5550 60 0000 C CNN
-F 3 "" H 9700 5550 60 0000 C CNN
- 4 9700 5550
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 3200 3200 3750 3200
-Wire Wire Line
- 2750 2900 2750 2950
-Wire Wire Line
- 2750 2950 2900 2950
-Wire Wire Line
- 2900 2950 2900 3000
-Wire Wire Line
- 4200 2900 4200 2950
-Wire Wire Line
- 4200 2950 4050 2950
-Wire Wire Line
- 4050 2950 4050 3000
-Wire Wire Line
- 2900 3400 2900 4400
-Wire Wire Line
- 2900 4000 3100 4000
-Wire Wire Line
- 4200 2000 4200 2500
-Wire Wire Line
- 4200 2350 2750 2350
-Wire Wire Line
- 2750 2350 2750 2500
-Wire Wire Line
- 5000 2000 4050 2000
-Connection ~ 4200 2350
-Connection ~ 4200 2000
-Wire Wire Line
- 3750 2200 3750 2350
-Connection ~ 3750 2350
-Wire Wire Line
- 3750 1800 3750 1650
-Wire Wire Line
- 3400 1650 7600 1650
-Wire Wire Line
- 3400 1650 3400 3800
-Wire Wire Line
- 5300 1650 5300 1800
-Connection ~ 3750 1650
-Wire Wire Line
- 5300 2200 5300 4500
-Wire Wire Line
- 5300 3500 3650 3500
-Wire Wire Line
- 3650 3500 3650 3200
-Connection ~ 3650 3200
-Connection ~ 2900 4000
-Wire Wire Line
- 4050 4400 4050 3400
-Wire Wire Line
- 3400 4200 3400 4600
-Wire Wire Line
- 3200 4600 3750 4600
-Connection ~ 3400 4600
-Wire Wire Line
- 4050 5100 4050 4800
-Wire Wire Line
- 3600 5100 3600 4600
-Connection ~ 3600 4600
-Wire Wire Line
- 2900 5100 2900 4800
-Wire Wire Line
- 2900 5400 2900 5550
-Wire Wire Line
- 2900 5550 9450 5550
-Wire Wire Line
- 4050 5550 4050 5400
-Wire Wire Line
- 3600 5400 3600 5550
-Connection ~ 3600 5550
-Wire Wire Line
- 6100 4700 5600 4700
-Wire Wire Line
- 6400 2950 6400 4500
-Wire Wire Line
- 6400 4250 5900 4250
-Wire Wire Line
- 5900 4250 5900 4700
-Connection ~ 5900 4700
-Wire Wire Line
- 5300 5100 5300 4900
-Wire Wire Line
- 5300 5550 5300 5400
-Connection ~ 4050 5550
-Wire Wire Line
- 6400 5550 6400 4900
-Connection ~ 5300 5550
-Connection ~ 5300 3500
-Wire Wire Line
- 6400 1650 6400 1750
-Connection ~ 5300 1650
-Wire Wire Line
- 6400 2150 6400 2650
-Connection ~ 6400 4250
-Wire Wire Line
- 6700 1950 7300 1950
-Wire Wire Line
- 7000 1950 7000 2250
-Wire Wire Line
- 7000 2250 6400 2250
-Connection ~ 6400 2250
-Wire Wire Line
- 7600 1650 7600 1750
-Connection ~ 6400 1650
-Connection ~ 7000 1950
-Wire Wire Line
- 7600 3250 7600 4100
-Wire Wire Line
- 7600 3450 7400 3450
-Wire Wire Line
- 6900 3450 7100 3450
-Wire Wire Line
- 6900 2650 6900 3450
-Wire Wire Line
- 6900 3050 7300 3050
-Wire Wire Line
- 7600 2150 7600 2850
-Wire Wire Line
- 7600 2650 7400 2650
-Wire Wire Line
- 7100 2650 6900 2650
-Connection ~ 6900 3050
-Connection ~ 7600 2650
-Wire Wire Line
- 7300 4300 7150 4300
-Wire Wire Line
- 7150 4150 7150 4950
-Connection ~ 7600 3450
-Wire Wire Line
- 7600 3700 7150 3700
-Wire Wire Line
- 7150 3700 7150 3750
-Connection ~ 7600 3700
-Wire Wire Line
- 6600 3050 6600 2450
-Wire Wire Line
- 6600 2450 7600 2450
-Connection ~ 7600 2450
-Wire Wire Line
- 6600 3350 6600 3950
-Wire Wire Line
- 4050 3950 6850 3950
-Wire Wire Line
- 6700 3950 6700 4500
-Connection ~ 6700 3950
-Wire Wire Line
- 6700 4900 6700 5550
-Connection ~ 6400 5550
-Connection ~ 7150 4300
-Wire Wire Line
- 7600 4950 7600 4500
-Wire Wire Line
- 7000 4700 7600 4700
-Connection ~ 7600 4700
-Wire Wire Line
- 7600 5550 7600 5250
-Connection ~ 6700 5550
-Wire Wire Line
- 7150 5250 7150 5550
-Connection ~ 7150 5550
-Wire Wire Line
- 7600 2300 8600 2300
-Wire Wire Line
- 8300 2300 8300 2550
-Connection ~ 8300 2300
-Connection ~ 7600 2300
-Wire Wire Line
- 8900 2100 8900 1650
-Wire Wire Line
- 7550 1650 9500 1650
-Connection ~ 7550 1650
-Connection ~ 8900 1650
-Wire Wire Line
- 8900 2500 8900 2900
-Wire Wire Line
- 8900 2750 8600 2750
-Connection ~ 8900 2750
-Wire Wire Line
- 8300 2950 8300 3350
-Wire Wire Line
- 8300 3350 8900 3350
-Wire Wire Line
- 8900 3200 8900 3650
-Wire Wire Line
- 8900 4400 8900 3950
-Connection ~ 8900 3350
-Wire Wire Line
- 8900 3500 9500 3500
-Connection ~ 8900 3500
-Wire Wire Line
- 8900 5550 8900 4800
-Connection ~ 7600 5550
-Connection ~ 8900 5550
-Wire Wire Line
- 8600 4600 8100 4600
-Wire Wire Line
- 8100 4600 8100 3850
-Wire Wire Line
- 8100 3850 7600 3850
-Connection ~ 7600 3850
-Connection ~ 4050 3950
-Connection ~ 6600 3950
-Wire Wire Line
- 4500 2700 4750 2700
-Wire Wire Line
- 4750 2700 4750 1050
-Wire Wire Line
- 2450 2700 2150 2700
-Wire Wire Line
- 2150 2700 2150 1200
-$Comp
-L PORT U1
-U 5 1 5CE90AA0
-P 1850 4850
-F 0 "U1" H 1900 4950 30 0000 C CNN
-F 1 "PORT" H 1850 4850 30 0000 C CNN
-F 2 "" H 1850 4850 60 0000 C CNN
-F 3 "" H 1850 4850 60 0000 C CNN
- 5 1850 4850
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5CE90AA1
-P 1850 5100
-F 0 "U1" H 1900 5200 30 0000 C CNN
-F 1 "PORT" H 1850 5100 30 0000 C CNN
-F 2 "" H 1850 5100 60 0000 C CNN
-F 3 "" H 1850 5100 60 0000 C CNN
- 1 1850 5100
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 2100 5100 2700 5100
-Wire Wire Line
- 2700 5100 2700 5050
-Wire Wire Line
- 2700 5050 2900 5050
-Connection ~ 2900 5050
-Wire Wire Line
- 2100 4850 2550 4850
-Wire Wire Line
- 2550 4850 2550 4900
-Wire Wire Line
- 2550 4900 4050 4900
-Connection ~ 4050 4900
-$Comp
-L PORT U1
-U 8 1 5CE9368F
-P 9600 6050
-F 0 "U1" H 9650 6150 30 0000 C CNN
-F 1 "PORT" H 9600 6050 30 0000 C CNN
-F 2 "" H 9600 6050 60 0000 C CNN
-F 3 "" H 9600 6050 60 0000 C CNN
- 8 9600 6050
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 9350 6050 9100 6050
-NoConn ~ 9100 6050
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/AD620/lm_741.sub b/src/SubcircuitLibrary/AD620/lm_741.sub deleted file mode 100644 index 3842c902..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741.sub +++ /dev/null @@ -1,40 +0,0 @@ -* Subcircuit lm_741
-.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ?
-* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
-.include npn_1.lib
-.include pnp_1.lib
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
-q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
-q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
-q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
-q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
-q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
-q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
-q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
-r1 net-_q7-pad3_ net-_q12-pad3_ 1k
-r2 net-_q3-pad3_ net-_q12-pad3_ 50k
-r3 net-_q8-pad3_ net-_q12-pad3_ 1k
-q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
-q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
-r4 net-_q13-pad3_ net-_q12-pad3_ 5k
-r11 net-_q10-pad1_ net-_q12-pad1_ 39k
-q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
-q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
-r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k
-r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k
-c1 net-_c1-pad1_ net-_c1-pad2_ 30p
-q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
-q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
-r5 net-_q15-pad2_ net-_q12-pad3_ 50k
-r6 net-_q15-pad3_ net-_q12-pad3_ 50
-q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
-q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
-q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
-r9 net-_q18-pad3_ net-_q20-pad3_ 25
-r10 net-_q20-pad3_ net-_q19-pad3_ 50
-q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
-* Control Statements
-
-.ends lm_741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml deleted file mode 100644 index b61322bb..00000000 --- a/src/SubcircuitLibrary/AD620/lm_741_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/npn_1.lib b/src/SubcircuitLibrary/AD620/npn_1.lib deleted file mode 100644 index 4a863e3e..00000000 --- a/src/SubcircuitLibrary/AD620/npn_1.lib +++ /dev/null @@ -1,29 +0,0 @@ -.model npn_1 NPN(
-+ Vtf=1.7
-+ Cjc=0.5p
-+ Nc=2
-+ Tr=46.91n
-+ Ne=1.307
-+ Cje=0.5p
-+ Isc=0
-+ Xtb=1.5
-+ Rb=500
-+ Rc=1
-+ Tf=411.1p
-+ Xti=3
-+ Ikr=0
-+ Bf=125
-+ Fc=.5
-+ Ise=14.34f
-+ Br=6.092
-+ Ikf=.2847
-+ Mje=.377
-+ Mjc=.3416
-+ Vaf=74.03
-+ Vjc=.75
-+ Vje=.75
-+ Xtf=3
-+ Itf=.6
-+ Is=14.34f
-+ Eg=1.11
-)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/AD620/pnp_1.lib b/src/SubcircuitLibrary/AD620/pnp_1.lib deleted file mode 100644 index c486429f..00000000 --- a/src/SubcircuitLibrary/AD620/pnp_1.lib +++ /dev/null @@ -1,29 +0,0 @@ -.model pnp_1 PNP(
-+ Vtf=1.7
-+ Cjc=1.5p
-+ Nc=2
-+ Tr=46.91n
-+ Ne=1.307
-+ Cje=0.3p
-+ Isc=0
-+ Xtb=1.5
-+ Rb=250
-+ Rc=1
-+ Tf=411.1p
-+ Xti=3
-+ Ikr=0
-+ Bf=25
-+ Fc=.5
-+ Ise=14.34f
-+ Br=6.092
-+ Ikf=.2847
-+ Mje=.377
-+ Mjc=.3416
-+ Vaf=74.03
-+ Vjc=.75
-+ Vje=.75
-+ Xtf=3
-+ Itf=.6
-+ Is=14.34f
-+ Eg=1.11
-)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CA3096/CA3096-cache.lib b/src/SubcircuitLibrary/CA3096/CA3096-cache.lib deleted file mode 100644 index 16f09ee3..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096-cache.lib +++ /dev/null @@ -1,83 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# eSim_NPN -# -DEF eSim_NPN Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -ALIAS BC547 Q2N2222 -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -# eSim_PNP -# -DEF eSim_PNP Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_PNP" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/CA3096/CA3096.cir b/src/SubcircuitLibrary/CA3096/CA3096.cir deleted file mode 100644 index 5a3af0fb..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096.cir +++ /dev/null @@ -1,16 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CA3096/CA3096.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 12:00:17 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN -Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN -Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_PNP -Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_PNP -U1 Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_Q2-Pad2_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q4-Pad3_ Net-_Q5-Pad2_ Net-_Q5-Pad1_ Net-_Q5-Pad3_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ ? PORT -Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN - -.end diff --git a/src/SubcircuitLibrary/CA3096/CA3096.cir.out b/src/SubcircuitLibrary/CA3096/CA3096.cir.out deleted file mode 100644 index 89c57845..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096.cir.out +++ /dev/null @@ -1,19 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ca3096/ca3096.cir - -.include PNP.lib -.include NPN.lib -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A -q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A -* u1 net-_q1-pad2_ net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ net-_q2-pad2_ net-_q2-pad1_ net-_q3-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ ? port -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 -.tran 10e-03 100e-03 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/CA3096/CA3096.pro b/src/SubcircuitLibrary/CA3096/CA3096.pro deleted file mode 100644 index d91a953f..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096.pro +++ /dev/null @@ -1,82 +0,0 @@ -update=Sat Jun 22 11:58:40 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=microcontrollers -LibName13=dsp -LibName14=microchip -LibName15=analog_switches -LibName16=motorola -LibName17=texas -LibName18=intel -LibName19=audio -LibName20=interface -LibName21=digital-audio -LibName22=philips -LibName23=display -LibName24=cypress -LibName25=siliconi -LibName26=opto -LibName27=atmel -LibName28=contrib -LibName29=valves -LibName30=eSim_Analog -LibName31=eSim_Devices -LibName32=eSim_Digital -LibName33=eSim_Hybrid -LibName34=eSim_Miscellaneous -LibName35=eSim_Plot -LibName36=eSim_Power -LibName37=eSim_Sources -LibName38=eSim_Subckt -LibName39=eSim_User -LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName41=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName42=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName43=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName44=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName45=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName46=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName47=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName48=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName49=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CA3096/CA3096.sch b/src/SubcircuitLibrary/CA3096/CA3096.sch deleted file mode 100644 index 3c08258c..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096.sch +++ /dev/null @@ -1,328 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:CA3096-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L eSim_NPN Q1 -U 1 1 5C98EEF5 -P 4150 4250 -F 0 "Q1" H 4050 4300 50 0000 R CNN -F 1 "eSim_NPN" H 4100 4400 50 0000 R CNN -F 2 "" H 4350 4350 29 0000 C CNN -F 3 "" H 4150 4250 60 0000 C CNN - 1 4150 4250 - -1 0 0 1 -$EndComp -$Comp -L eSim_NPN Q2 -U 1 1 5C98EFC9 -P 4250 4950 -F 0 "Q2" H 4150 5000 50 0000 R CNN -F 1 "eSim_NPN" H 4200 5100 50 0000 R CNN -F 2 "" H 4450 5050 29 0000 C CNN -F 3 "" H 4250 4950 60 0000 C CNN - 1 4250 4950 - 1 0 0 1 -$EndComp -$Comp -L eSim_PNP Q5 -U 1 1 5C98F076 -P 5300 5400 -F 0 "Q5" H 5200 5450 50 0000 R CNN -F 1 "eSim_PNP" H 5250 5550 50 0000 R CNN -F 2 "" H 5500 5500 29 0000 C CNN -F 3 "" H 5300 5400 60 0000 C CNN - 1 5300 5400 - -1 0 0 -1 -$EndComp -$Comp -L eSim_PNP Q4 -U 1 1 5C98F0A7 -P 5300 4650 -F 0 "Q4" H 5200 4700 50 0000 R CNN -F 1 "eSim_PNP" H 5250 4800 50 0000 R CNN -F 2 "" H 5500 4750 29 0000 C CNN -F 3 "" H 5300 4650 60 0000 C CNN - 1 5300 4650 - -1 0 0 -1 -$EndComp -Wire Wire Line - 4350 3800 4350 4250 -Wire Wire Line - 4350 5450 4350 5150 -Wire Wire Line - 5200 5600 5200 5700 -Wire Wire Line - 5200 4850 5200 4950 -Wire Wire Line - 5200 4200 5200 4450 -$Comp -L PORT U1 -U 1 1 5C98F1D4 -P 2950 3800 -F 0 "U1" H 3000 3900 30 0000 C CNN -F 1 "PORT" H 2950 3800 30 0000 C CNN -F 2 "" H 2950 3800 60 0000 C CNN -F 3 "" H 2950 3800 60 0000 C CNN - 1 2950 3800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C98F222 -P 2950 4450 -F 0 "U1" H 3000 4550 30 0000 C CNN -F 1 "PORT" H 2950 4450 30 0000 C CNN -F 2 "" H 2950 4450 60 0000 C CNN -F 3 "" H 2950 4450 60 0000 C CNN - 3 2950 4450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5C98F272 -P 2950 4950 -F 0 "U1" H 3000 5050 30 0000 C CNN -F 1 "PORT" H 2950 4950 30 0000 C CNN -F 2 "" H 2950 4950 60 0000 C CNN -F 3 "" H 2950 4950 60 0000 C CNN - 5 2950 4950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5C98F29F -P 2950 5450 -F 0 "U1" H 3000 5550 30 0000 C CNN -F 1 "PORT" H 2950 5450 30 0000 C CNN -F 2 "" H 2950 5450 60 0000 C CNN -F 3 "" H 2950 5450 60 0000 C CNN - 6 2950 5450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5C98F38F -P 6150 6050 -F 0 "U1" H 6200 6150 30 0000 C CNN -F 1 "PORT" H 6150 6050 30 0000 C CNN -F 2 "" H 6150 6050 60 0000 C CNN -F 3 "" H 6150 6050 60 0000 C CNN - 9 6150 6050 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 11 1 5C98F4ED -P 6150 5400 -F 0 "U1" H 6200 5500 30 0000 C CNN -F 1 "PORT" H 6150 5400 30 0000 C CNN -F 2 "" H 6150 5400 60 0000 C CNN -F 3 "" H 6150 5400 60 0000 C CNN - 11 6150 5400 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 12 1 5C98F52C -P 6150 5200 -F 0 "U1" H 6200 5300 30 0000 C CNN -F 1 "PORT" H 6150 5200 30 0000 C CNN -F 2 "" H 6150 5200 60 0000 C CNN -F 3 "" H 6150 5200 60 0000 C CNN - 12 6150 5200 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5C98F5BA -P 6150 4650 -F 0 "U1" H 6200 4750 30 0000 C CNN -F 1 "PORT" H 6150 4650 30 0000 C CNN -F 2 "" H 6150 4650 60 0000 C CNN -F 3 "" H 6150 4650 60 0000 C CNN - 14 6150 4650 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 15 1 5C98F5FF -P 6150 4200 -F 0 "U1" H 6200 4300 30 0000 C CNN -F 1 "PORT" H 6150 4200 30 0000 C CNN -F 2 "" H 6150 4200 60 0000 C CNN -F 3 "" H 6150 4200 60 0000 C CNN - 15 6150 4200 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 10 1 5C9C8B88 -P 6150 4950 -F 0 "U1" H 6200 5050 30 0000 C CNN -F 1 "PORT" H 6150 4950 30 0000 C CNN -F 2 "" H 6150 4950 60 0000 C CNN -F 3 "" H 6150 4950 60 0000 C CNN - 10 6150 4950 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 13 1 5C9C9E21 -P 6150 5700 -F 0 "U1" H 6200 5800 30 0000 C CNN -F 1 "PORT" H 6150 5700 30 0000 C CNN -F 2 "" H 6150 5700 60 0000 C CNN -F 3 "" H 6150 5700 60 0000 C CNN - 13 6150 5700 - -1 0 0 1 -$EndComp -Wire Wire Line - 3200 3800 4350 3800 -Wire Wire Line - 3200 4450 4050 4450 -Wire Wire Line - 3200 4750 4350 4750 -Wire Wire Line - 3200 4950 4050 4950 -Wire Wire Line - 3200 5450 4350 5450 -Wire Wire Line - 4050 5850 3200 5850 -Wire Wire Line - 3200 5650 4350 5650 -Wire Wire Line - 5900 6050 4350 6050 -Wire Wire Line - 5200 5700 5900 5700 -Wire Wire Line - 5900 5400 5500 5400 -Wire Wire Line - 5200 5200 5900 5200 -Wire Wire Line - 5200 4950 5900 4950 -Wire Wire Line - 5500 4650 5900 4650 -Wire Wire Line - 5200 4200 5900 4200 -Wire Wire Line - 4050 4050 3200 4050 -$Comp -L PORT U1 -U 7 1 5C9CB60F -P 2950 5650 -F 0 "U1" H 3000 5750 30 0000 C CNN -F 1 "PORT" H 2950 5650 30 0000 C CNN -F 2 "" H 2950 5650 60 0000 C CNN -F 3 "" H 2950 5650 60 0000 C CNN - 7 2950 5650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9CB58F -P 2950 4750 -F 0 "U1" H 3000 4850 30 0000 C CNN -F 1 "PORT" H 2950 4750 30 0000 C CNN -F 2 "" H 2950 4750 60 0000 C CNN -F 3 "" H 2950 4750 60 0000 C CNN - 4 2950 4750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9CB511 -P 2950 4050 -F 0 "U1" H 3000 4150 30 0000 C CNN -F 1 "PORT" H 2950 4050 30 0000 C CNN -F 2 "" H 2950 4050 60 0000 C CNN -F 3 "" H 2950 4050 60 0000 C CNN - 2 2950 4050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5C9CBE1D -P 2950 5850 -F 0 "U1" H 3000 5950 30 0000 C CNN -F 1 "PORT" H 2950 5850 30 0000 C CNN -F 2 "" H 2950 5850 60 0000 C CNN -F 3 "" H 2950 5850 60 0000 C CNN - 8 2950 5850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 16 1 5D0DDF9F -P 6200 3950 -F 0 "U1" H 6250 4050 30 0000 C CNN -F 1 "PORT" H 6200 3950 30 0000 C CNN -F 2 "" H 6200 3950 60 0000 C CNN -F 3 "" H 6200 3950 60 0000 C CNN - 16 6200 3950 - -1 0 0 1 -$EndComp -NoConn ~ 5950 3950 -$Comp -L eSim_NPN Q3 -U 1 1 5C98F006 -P 4250 5850 -F 0 "Q3" H 4150 5900 50 0000 R CNN -F 1 "eSim_NPN" H 4200 6000 50 0000 R CNN -F 2 "" H 4450 5950 29 0000 C CNN -F 3 "" H 4250 5850 60 0000 C CNN - 1 4250 5850 - 1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CA3096/CA3096.sub b/src/SubcircuitLibrary/CA3096/CA3096.sub deleted file mode 100644 index f79667b7..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096.sub +++ /dev/null @@ -1,13 +0,0 @@ -* Subcircuit CA3096 -.subckt CA3096 net-_q1-pad2_ net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ net-_q2-pad2_ net-_q2-pad1_ net-_q3-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad1_ net-_q5-pad3_ net-_q4-pad2_ net-_q4-pad1_ ? -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ca3096/ca3096.cir -.include PNP.lib -.include NPN.lib -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2907A -q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 -* Control Statements - -.ends CA3096
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CA3096/CA3096.xml b/src/SubcircuitLibrary/CA3096/CA3096.xml deleted file mode 100644 index 24f50baa..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096.xml +++ /dev/null @@ -1,191 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<export version="D"> - <design> - <source>C:/esim_1/eSim/src/SubcircuitLibrary/CA3096/CA3096.sch</source> - <date>03/31/19 09:48:27</date> - <tool>Eeschema 4.0.2-stable</tool> - <sheet number="1" name="/" tstamps="/"> - <title_block> - <title/> - <company/> - <rev/> - <date/> - <source>CA3096.sch</source> - <comment number="1" value=""/> - <comment number="2" value=""/> - <comment number="3" value=""/> - <comment number="4" value=""/> - </title_block> - </sheet> - </design> - <components> - <comp ref="Q1"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98EEF5</tstamp> - </comp> - <comp ref="Q2"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98EFC9</tstamp> - </comp> - <comp ref="Q3"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98F006</tstamp> - </comp> - <comp ref="Q5"> - <value>eSim_PNP</value> - <libsource lib="eSim_Devices" part="eSim_PNP"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98F076</tstamp> - </comp> - <comp ref="Q4"> - <value>eSim_PNP</value> - <libsource lib="eSim_Devices" part="eSim_PNP"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98F0A7</tstamp> - </comp> - <comp ref="U1"> - <value>PORT</value> - <libsource lib="eSim_Miscellaneous" part="PORT"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98F1D4</tstamp> - </comp> - </components> - <libparts> - <libpart lib="eSim_Miscellaneous" part="PORT"> - <fields> - <field name="Reference">U</field> - <field name="Value">PORT</field> - </fields> - <pins> - <pin num="1" name="~" type="input"/> - <pin num="2" name="~" type="input"/> - <pin num="3" name="~" type="input"/> - <pin num="4" name="~" type="input"/> - <pin num="5" name="~" type="input"/> - <pin num="6" name="~" type="input"/> - <pin num="7" name="~" type="input"/> - <pin num="8" name="~" type="input"/> - <pin num="9" name="~" type="input"/> - <pin num="10" name="~" type="input"/> - <pin num="11" name="~" type="input"/> - <pin num="12" name="~" type="input"/> - <pin num="13" name="~" type="input"/> - <pin num="14" name="~" type="input"/> - <pin num="15" name="~" type="input"/> - <pin num="16" name="~" type="input"/> - <pin num="17" name="~" type="input"/> - <pin num="18" name="~" type="input"/> - <pin num="19" name="~" type="input"/> - <pin num="20" name="~" type="input"/> - <pin num="21" name="~" type="input"/> - <pin num="22" name="~" type="input"/> - <pin num="23" name="~" type="input"/> - <pin num="24" name="~" type="input"/> - <pin num="25" name="~" type="input"/> - <pin num="26" name="~" type="input"/> - </pins> - </libpart> - <libpart lib="eSim_Devices" part="eSim_NPN"> - <aliases> - <alias>BC547</alias> - <alias>Q2N2222</alias> - </aliases> - <fields> - <field name="Reference">Q</field> - <field name="Value">eSim_NPN</field> - </fields> - <pins> - <pin num="1" name="C" type="openCol"/> - <pin num="2" name="B" type="input"/> - <pin num="3" name="E" type="openEm"/> - </pins> - </libpart> - <libpart lib="eSim_Devices" part="eSim_PNP"> - <fields> - <field name="Reference">Q</field> - <field name="Value">eSim_PNP</field> - </fields> - <pins> - <pin num="1" name="C" type="openCol"/> - <pin num="2" name="B" type="input"/> - <pin num="3" name="E" type="openEm"/> - </pins> - </libpart> - </libparts> - <libraries> - <library logical="eSim_Devices"> - <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri> - </library> - <library logical="eSim_Miscellaneous"> - <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri> - </library> - </libraries> - <nets> - <net code="1" name="Net-(Q5-Pad2)"> - <node ref="U1" pin="11"/> - <node ref="Q5" pin="2"/> - </net> - <net code="2" name="Net-(Q2-Pad2)"> - <node ref="U1" pin="5"/> - <node ref="Q2" pin="2"/> - </net> - <net code="3" name="Net-(Q3-Pad2)"> - <node ref="U1" pin="8"/> - <node ref="Q3" pin="2"/> - </net> - <net code="4" name="Net-(Q4-Pad2)"> - <node ref="U1" pin="14"/> - <node ref="Q4" pin="2"/> - </net> - <net code="5" name="Net-(Q1-Pad1)"> - <node ref="U1" pin="3"/> - <node ref="Q1" pin="1"/> - </net> - <net code="6" name="Net-(Q2-Pad3)"> - <node ref="Q2" pin="3"/> - <node ref="U1" pin="4"/> - </net> - <net code="7" name="Net-(Q3-Pad3)"> - <node ref="Q3" pin="3"/> - <node ref="U1" pin="7"/> - </net> - <net code="8" name="Net-(Q3-Pad1)"> - <node ref="U1" pin="9"/> - <node ref="Q3" pin="1"/> - </net> - <net code="9" name="Net-(Q5-Pad1)"> - <node ref="U1" pin="12"/> - <node ref="Q5" pin="1"/> - </net> - <net code="10" name="Net-(Q1-Pad2)"> - <node ref="U1" pin="1"/> - <node ref="Q1" pin="2"/> - </net> - <net code="11" name="Net-(Q1-Pad3)"> - <node ref="U1" pin="2"/> - <node ref="Q1" pin="3"/> - </net> - <net code="12" name="Net-(Q2-Pad1)"> - <node ref="Q2" pin="1"/> - <node ref="U1" pin="6"/> - </net> - <net code="13" name="Net-(Q5-Pad3)"> - <node ref="Q5" pin="3"/> - <node ref="U1" pin="13"/> - </net> - <net code="14" name="Net-(Q4-Pad1)"> - <node ref="U1" pin="15"/> - <node ref="Q4" pin="1"/> - </net> - <net code="15" name="Net-(Q4-Pad3)"> - <node ref="Q4" pin="3"/> - <node ref="U1" pin="10"/> - </net> - </nets> -</export> diff --git a/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml b/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml deleted file mode 100644 index 82a40fb6..00000000 --- a/src/SubcircuitLibrary/CA3096/CA3096_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CA3096/D.lib b/src/SubcircuitLibrary/CA3096/D.lib deleted file mode 100644 index 8a7fb4da..00000000 --- a/src/SubcircuitLibrary/CA3096/D.lib +++ /dev/null @@ -1,2 +0,0 @@ -.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) - diff --git a/src/SubcircuitLibrary/CA3096/NPN.lib b/src/SubcircuitLibrary/CA3096/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/CA3096/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/CA3096/PNP.lib b/src/SubcircuitLibrary/CA3096/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/CA3096/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/CA3096/analysis b/src/SubcircuitLibrary/CA3096/analysis deleted file mode 100644 index d5e13546..00000000 --- a/src/SubcircuitLibrary/CA3096/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib deleted file mode 100644 index f7d63760..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic-cache.lib +++ /dev/null @@ -1,185 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Logic_adder -# -DEF Logic_adder X 0 40 Y Y 1 F N -F0 "X" 0 -250 60 H V C CNN -F1 "Logic_adder" 50 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -550 550 550 -600 0 1 0 N -X IN1 1 -750 350 200 R 50 50 1 1 I -X IN2 2 -750 -50 200 R 50 50 1 1 I -X CIN 3 -750 -450 200 R 50 50 1 1 I -X SUM 4 750 350 200 L 50 50 1 1 O -X COUT 5 750 -300 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# MUX -# -DEF MUX X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "MUX" 0 100 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -300 350 250 -150 0 1 0 N -X sel 1 0 550 200 D 50 50 1 1 I -X a0 2 -500 150 200 R 50 50 1 1 I -X a1 3 -500 -50 200 R 50 50 1 1 I -X y 4 450 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 75 50 H I C CNN -F1 "PWR_FLAG" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -X pwr 1 0 0 0 U 50 50 0 0 w -P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N -ENDDRAW -ENDDEF -# -# adc_bridge_1 -# -DEF adc_bridge_1 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "adc_bridge_1" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -50 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X OUT1 2 550 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -# eSim_GND -# -DEF eSim_GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "eSim_GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir deleted file mode 100644 index fee511ed..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir +++ /dev/null @@ -1,29 +0,0 @@ -* /home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 8 18:40:34 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_and -U5 Net-_U2-Pad2_ Net-_U2-Pad1_ Net-_U5-Pad3_ d_xor -U6 Net-_U2-Pad3_ Net-_U3-Pad1_ Net-_U6-Pad3_ d_xor -U7 Net-_U3-Pad3_ Net-_U7-Pad2_ Net-_U7-Pad3_ d_xor -U8 Net-_U3-Pad3_ Net-_U8-Pad2_ Net-_U8-Pad3_ d_xor -U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT -X3 Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U9-Pad2_ Net-_U2-Pad2_ Net-_X1-Pad3_ Logic_adder -X1 Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_X1-Pad3_ Net-_U2-Pad1_ Net-_X1-Pad5_ Logic_adder -X2 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_X1-Pad5_ Net-_U3-Pad1_ Net-_X2-Pad5_ Logic_adder -X4 Net-_U1-Pad4_ Net-_U1-Pad8_ Net-_X2-Pad5_ Net-_U7-Pad2_ Net-_U8-Pad2_ Logic_adder -X7 Net-_U1-Pad9_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad10_ MUX -X5 Net-_U1-Pad9_ Net-_U2-Pad1_ Net-_U5-Pad3_ Net-_U1-Pad11_ MUX -X8 Net-_U1-Pad9_ Net-_U3-Pad1_ Net-_U6-Pad3_ Net-_U1-Pad12_ MUX -X6 Net-_U1-Pad9_ Net-_U7-Pad2_ Net-_U7-Pad3_ Net-_U1-Pad13_ MUX -X9 Net-_U1-Pad9_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U1-Pad14_ MUX -v1 Net-_U9-Pad1_ GND 0 -U9 Net-_U9-Pad1_ Net-_U9-Pad2_ adc_bridge_1 - -.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out deleted file mode 100644 index 9bfd2402..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.cir.out +++ /dev/null @@ -1,56 +0,0 @@ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir - -.include LOGIC_ADDER.sub -.include MUX.sub -* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and -* u5 net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor -* u6 net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor -* u7 net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor -* u8 net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor -* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port -x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER -x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER -x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER -x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER -x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX -x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX -x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX -x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX -x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX -v1 net-_u9-pad1_ gnd 0 -* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1 -a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5 -a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6 -a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7 -a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8 -a7 net-_u2-pad2_ net-_u4-pad2_ u4 -a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge -.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro deleted file mode 100644 index a546f71d..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.pro +++ /dev/null @@ -1,46 +0,0 @@ -update=Sat Jun 8 13:24:24 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User -LibName11=eSim_Subckt -LibName12=power - diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch deleted file mode 100644 index e7eac906..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sch +++ /dev/null @@ -1,654 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_PSpice -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:power -LIBS:CSLA_BEC1_logic-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5CFB5959 -P 4800 3500 -F 0 "U2" H 4800 3500 60 0000 C CNN -F 1 "d_and" H 4850 3600 60 0000 C CNN -F 2 "" H 4800 3500 60 0000 C CNN -F 3 "" H 4800 3500 60 0000 C CNN - 1 4800 3500 - 0 1 1 0 -$EndComp -$Comp -L d_and U3 -U 1 1 5CFB595A -P 4850 5350 -F 0 "U3" H 4850 5350 60 0000 C CNN -F 1 "d_and" H 4900 5450 60 0000 C CNN -F 2 "" H 4850 5350 60 0000 C CNN -F 3 "" H 4850 5350 60 0000 C CNN - 1 4850 5350 - 0 1 1 0 -$EndComp -$Comp -L d_xor U5 -U 1 1 5CFB595B -P 5750 2900 -F 0 "U5" H 5750 2900 60 0000 C CNN -F 1 "d_xor" H 5800 3000 47 0000 C CNN -F 2 "" H 5750 2900 60 0000 C CNN -F 3 "" H 5750 2900 60 0000 C CNN - 1 5750 2900 - 1 0 0 -1 -$EndComp -$Comp -L d_xor U6 -U 1 1 5CFB595C -P 5800 4450 -F 0 "U6" H 5800 4450 60 0000 C CNN -F 1 "d_xor" H 5850 4550 47 0000 C CNN -F 2 "" H 5800 4450 60 0000 C CNN -F 3 "" H 5800 4450 60 0000 C CNN - 1 5800 4450 - 1 0 0 -1 -$EndComp -$Comp -L d_xor U7 -U 1 1 5CFB595D -P 5900 5250 -F 0 "U7" H 5900 5250 60 0000 C CNN -F 1 "d_xor" H 5950 5350 47 0000 C CNN -F 2 "" H 5900 5250 60 0000 C CNN -F 3 "" H 5900 5250 60 0000 C CNN - 1 5900 5250 - 1 0 0 -1 -$EndComp -$Comp -L d_xor U8 -U 1 1 5CFB595E -P 5900 6700 -F 0 "U8" H 5900 6700 60 0000 C CNN -F 1 "d_xor" H 5950 6800 47 0000 C CNN -F 2 "" H 5900 6700 60 0000 C CNN -F 3 "" H 5900 6700 60 0000 C CNN - 1 5900 6700 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U4 -U 1 1 5CFB595F -P 5600 1300 -F 0 "U4" H 5600 1200 60 0000 C CNN -F 1 "d_inverter" H 5600 1450 60 0000 C CNN -F 2 "" H 5650 1250 60 0000 C CNN -F 3 "" H 5650 1250 60 0000 C CNN - 1 5600 1300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CFB6267 -P 1950 1300 -F 0 "U1" H 2000 1400 30 0000 C CNN -F 1 "PORT" H 1950 1300 30 0000 C CNN -F 2 "" H 1950 1300 60 0000 C CNN -F 3 "" H 1950 1300 60 0000 C CNN - 1 1950 1300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CFB62F5 -P 1950 1700 -F 0 "U1" H 2000 1800 30 0000 C CNN -F 1 "PORT" H 1950 1700 30 0000 C CNN -F 2 "" H 1950 1700 60 0000 C CNN -F 3 "" H 1950 1700 60 0000 C CNN - 5 1950 1700 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5CFB6357 -P 1950 2100 -F 0 "U1" H 2000 2200 30 0000 C CNN -F 1 "PORT" H 1950 2100 30 0000 C CNN -F 2 "" H 1950 2100 60 0000 C CNN -F 3 "" H 1950 2100 60 0000 C CNN - 9 1950 2100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5CFB63B0 -P 2150 2900 -F 0 "U1" H 2200 3000 30 0000 C CNN -F 1 "PORT" H 2150 2900 30 0000 C CNN -F 2 "" H 2150 2900 60 0000 C CNN -F 3 "" H 2150 2900 60 0000 C CNN - 2 2150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CFB641E -P 2300 3300 -F 0 "U1" H 2350 3400 30 0000 C CNN -F 1 "PORT" H 2300 3300 30 0000 C CNN -F 2 "" H 2300 3300 60 0000 C CNN -F 3 "" H 2300 3300 60 0000 C CNN - 6 2300 3300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CFB647F -P 1900 4450 -F 0 "U1" H 1950 4550 30 0000 C CNN -F 1 "PORT" H 1900 4450 30 0000 C CNN -F 2 "" H 1900 4450 60 0000 C CNN -F 3 "" H 1900 4450 60 0000 C CNN - 3 1900 4450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5CFB6565 -P 2150 4850 -F 0 "U1" H 2200 4950 30 0000 C CNN -F 1 "PORT" H 2150 4850 30 0000 C CNN -F 2 "" H 2150 4850 60 0000 C CNN -F 3 "" H 2150 4850 60 0000 C CNN - 7 2150 4850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CFB65D4 -P 2000 5900 -F 0 "U1" H 2050 6000 30 0000 C CNN -F 1 "PORT" H 2000 5900 30 0000 C CNN -F 2 "" H 2000 5900 60 0000 C CNN -F 3 "" H 2000 5900 60 0000 C CNN - 4 2000 5900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CFB6660 -P 2300 6300 -F 0 "U1" H 2350 6400 30 0000 C CNN -F 1 "PORT" H 2300 6300 30 0000 C CNN -F 2 "" H 2300 6300 60 0000 C CNN -F 3 "" H 2300 6300 60 0000 C CNN - 8 2300 6300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CFB66D3 -P 8700 2250 -F 0 "U1" H 8750 2350 30 0000 C CNN -F 1 "PORT" H 8700 2250 30 0000 C CNN -F 2 "" H 8700 2250 60 0000 C CNN -F 3 "" H 8700 2250 60 0000 C CNN - 10 8700 2250 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CFB6922 -P 8700 2600 -F 0 "U1" H 8750 2700 30 0000 C CNN -F 1 "PORT" H 8700 2600 30 0000 C CNN -F 2 "" H 8700 2600 60 0000 C CNN -F 3 "" H 8700 2600 60 0000 C CNN - 11 8700 2600 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CFB6A11 -P 8700 3200 -F 0 "U1" H 8750 3300 30 0000 C CNN -F 1 "PORT" H 8700 3200 30 0000 C CNN -F 2 "" H 8700 3200 60 0000 C CNN -F 3 "" H 8700 3200 60 0000 C CNN - 12 8700 3200 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CFB6AE5 -P 8700 3500 -F 0 "U1" H 8750 3600 30 0000 C CNN -F 1 "PORT" H 8700 3500 30 0000 C CNN -F 2 "" H 8700 3500 60 0000 C CNN -F 3 "" H 8700 3500 60 0000 C CNN - 13 8700 3500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CFB6B58 -P 8700 3800 -F 0 "U1" H 8750 3900 30 0000 C CNN -F 1 "PORT" H 8700 3800 30 0000 C CNN -F 2 "" H 8700 3800 60 0000 C CNN -F 3 "" H 8700 3800 60 0000 C CNN - 14 8700 3800 - -1 0 0 1 -$EndComp -$Comp -L Logic_adder X3 -U 1 1 5CFB6531 -P 3850 1650 -F 0 "X3" H 3850 1400 60 0000 C CNN -F 1 "Logic_adder" H 3900 1650 60 0000 C CNN -F 2 "" H 3850 1650 60 0000 C CNN -F 3 "" H 3850 1650 60 0000 C CNN - 1 3850 1650 - 1 0 0 -1 -$EndComp -$Comp -L Logic_adder X1 -U 1 1 5CFB6824 -P 3750 3250 -F 0 "X1" H 3750 3000 60 0000 C CNN -F 1 "Logic_adder" H 3800 3250 60 0000 C CNN -F 2 "" H 3750 3250 60 0000 C CNN -F 3 "" H 3750 3250 60 0000 C CNN - 1 3750 3250 - 1 0 0 -1 -$EndComp -$Comp -L Logic_adder X2 -U 1 1 5CFB691C -P 3800 4800 -F 0 "X2" H 3800 4550 60 0000 C CNN -F 1 "Logic_adder" H 3850 4800 60 0000 C CNN -F 2 "" H 3800 4800 60 0000 C CNN -F 3 "" H 3800 4800 60 0000 C CNN - 1 3800 4800 - 1 0 0 -1 -$EndComp -$Comp -L Logic_adder X4 -U 1 1 5CFB69DF -P 3850 6250 -F 0 "X4" H 3850 6000 60 0000 C CNN -F 1 "Logic_adder" H 3900 6250 60 0000 C CNN -F 2 "" H 3850 6250 60 0000 C CNN -F 3 "" H 3850 6250 60 0000 C CNN - 1 3850 6250 - 1 0 0 -1 -$EndComp -$Comp -L MUX X7 -U 1 1 5CFB6AF5 -P 7500 1450 -F 0 "X7" H 7500 1450 60 0000 C CNN -F 1 "MUX" H 7500 1550 60 0000 C CNN -F 2 "" H 7500 1450 60 0001 C CNN -F 3 "" H 7500 1450 60 0001 C CNN - 1 7500 1450 - 1 0 0 -1 -$EndComp -$Comp -L MUX X5 -U 1 1 5CFB6BC8 -P 7450 2950 -F 0 "X5" H 7450 2950 60 0000 C CNN -F 1 "MUX" H 7450 3050 60 0000 C CNN -F 2 "" H 7450 2950 60 0001 C CNN -F 3 "" H 7450 2950 60 0001 C CNN - 1 7450 2950 - 1 0 0 -1 -$EndComp -$Comp -L MUX X8 -U 1 1 5CFB6C73 -P 7500 4100 -F 0 "X8" H 7500 4100 60 0000 C CNN -F 1 "MUX" H 7500 4200 60 0000 C CNN -F 2 "" H 7500 4100 60 0001 C CNN -F 3 "" H 7500 4100 60 0001 C CNN - 1 7500 4100 - 1 0 0 -1 -$EndComp -$Comp -L MUX X6 -U 1 1 5CFB6D3F -P 7450 5250 -F 0 "X6" H 7450 5250 60 0000 C CNN -F 1 "MUX" H 7450 5350 60 0000 C CNN -F 2 "" H 7450 5250 60 0001 C CNN -F 3 "" H 7450 5250 60 0001 C CNN - 1 7450 5250 - 1 0 0 -1 -$EndComp -$Comp -L MUX X9 -U 1 1 5CFB6E26 -P 7550 6200 -F 0 "X9" H 7550 6200 60 0000 C CNN -F 1 "MUX" H 7550 6300 60 0000 C CNN -F 2 "" H 7550 6200 60 0001 C CNN -F 3 "" H 7550 6200 60 0001 C CNN - 1 7550 6200 - 1 0 0 -1 -$EndComp -$Comp -L eSim_GND #PWR01 -U 1 1 5CFBB921 -P 800 2450 -F 0 "#PWR01" H 800 2200 50 0001 C CNN -F 1 "eSim_GND" H 800 2300 50 0000 C CNN -F 2 "" H 800 2450 50 0001 C CNN -F 3 "" H 800 2450 50 0001 C CNN - 1 800 2450 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5CFBBABC -P 1300 2300 -F 0 "v1" H 1100 2400 60 0000 C CNN -F 1 "0" H 1100 2250 60 0000 C CNN -F 2 "R1" H 1000 2300 60 0000 C CNN -F 3 "" H 1300 2300 60 0000 C CNN - 1 1300 2300 - 0 1 1 0 -$EndComp -$Comp -L adc_bridge_1 U9 -U 1 1 5CFBB81E -P 2500 2350 -F 0 "U9" H 2500 2350 60 0000 C CNN -F 1 "adc_bridge_1" H 2500 2500 60 0000 C CNN -F 2 "" H 2500 2350 60 0000 C CNN -F 3 "" H 2500 2350 60 0000 C CNN - 1 2500 2350 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 5CFBBCDC -P 750 2350 -F 0 "#FLG02" H 750 2425 50 0001 C CNN -F 1 "PWR_FLAG" H 750 2500 50 0000 C CNN -F 2 "" H 750 2350 50 0001 C CNN -F 3 "" H 750 2350 50 0001 C CNN - 1 750 2350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1750 2300 1900 2300 -Wire Wire Line - 750 2400 850 2400 -Wire Wire Line - 850 2300 850 2450 -Connection ~ 850 2400 -Wire Wire Line - 850 2450 800 2450 -Wire Wire Line - 750 2350 750 2400 -Wire Wire Line - 3050 2300 3050 2100 -Wire Wire Line - 3050 2100 3100 2100 -Connection ~ 6600 2100 -Connection ~ 6600 600 -Wire Wire Line - 6600 600 6600 5650 -Connection ~ 6600 3550 -Wire Wire Line - 6600 2100 7450 2100 -Wire Wire Line - 6600 3550 7500 3550 -Wire Wire Line - 6600 4700 7450 4700 -Wire Wire Line - 4600 3700 4550 3700 -Wire Wire Line - 4700 2100 4650 2100 -Wire Wire Line - 7050 6300 7050 6250 -Wire Wire Line - 7050 6000 7050 6050 -Wire Wire Line - 6950 5350 6950 5300 -Wire Wire Line - 6950 5050 6950 5100 -Wire Wire Line - 7000 4150 6900 4150 -Wire Wire Line - 6900 3950 6900 3900 -Wire Wire Line - 7000 3950 6900 3950 -Wire Wire Line - 8150 4000 7950 4000 -Wire Wire Line - 6950 3050 6850 3050 -Wire Wire Line - 6950 3000 6950 3050 -Wire Wire Line - 6950 2750 6950 2800 -Wire Wire Line - 6950 1550 6900 1550 -Wire Wire Line - 6950 1500 6950 1550 -Wire Wire Line - 7000 1500 6950 1500 -Wire Wire Line - 7000 1250 6900 1250 -Wire Wire Line - 7000 1300 7000 1250 -Wire Wire Line - 4500 3550 4600 3550 -Wire Wire Line - 4700 6550 4600 6550 -Wire Wire Line - 4550 5100 4650 5100 -Wire Wire Line - 4700 1950 4600 1950 -Wire Wire Line - 6600 5650 7550 5650 -Wire Wire Line - 5400 6000 7050 6000 -Wire Wire Line - 5350 5050 6950 5050 -Wire Wire Line - 5350 5900 5350 5050 -Wire Wire Line - 6400 5350 6950 5350 -Wire Wire Line - 6400 5200 6400 5350 -Wire Wire Line - 6650 6650 6650 6300 -Wire Wire Line - 5400 6700 5400 6000 -Wire Wire Line - 6900 3900 5350 3900 -Wire Wire Line - 6900 4150 6900 4400 -Wire Wire Line - 6900 4400 6250 4400 -Connection ~ 5200 2900 -Wire Wire Line - 5200 2900 5200 2600 -Wire Wire Line - 5200 2600 6350 2600 -Wire Wire Line - 6350 2600 6350 2750 -Wire Wire Line - 6350 2750 6950 2750 -Wire Wire Line - 6850 3050 6850 2850 -Wire Wire Line - 6850 2850 6200 2850 -Wire Wire Line - 4550 4450 5350 4450 -Wire Wire Line - 4600 1300 5300 1300 -Wire Wire Line - 4500 2900 5300 2900 -Wire Wire Line - 4700 1950 4700 2100 -Wire Wire Line - 4600 3550 4600 3700 -Wire Wire Line - 4650 5250 4600 5250 -Wire Wire Line - 4650 5100 4650 5250 -Wire Wire Line - 4600 5900 5450 5900 -Wire Wire Line - 4700 6700 5450 6700 -Wire Wire Line - 4700 6550 4700 6700 -Wire Wire Line - 2200 1300 3100 1300 -Wire Wire Line - 2200 1700 3100 1700 -Wire Wire Line - 2700 2100 2700 600 -Wire Wire Line - 2550 3300 3000 3300 -Wire Wire Line - 2400 2900 3000 2900 -Wire Wire Line - 2200 2100 2700 2100 -Wire Wire Line - 8000 6100 8450 6100 -Wire Wire Line - 8450 6100 8450 3800 -Wire Wire Line - 8300 3500 8450 3500 -Wire Wire Line - 8300 5150 8300 3500 -Wire Wire Line - 7900 5150 8300 5150 -Wire Wire Line - 8150 3200 8450 3200 -Wire Wire Line - 8300 2600 8450 2600 -Wire Wire Line - 8300 2850 8300 2600 -Wire Wire Line - 7900 2850 8300 2850 -Wire Wire Line - 8450 1350 8450 2250 -Wire Wire Line - 7950 1350 8450 1350 -Wire Wire Line - 8150 3200 8150 4000 -Wire Wire Line - 6650 6300 7050 6300 -Wire Wire Line - 5350 4450 5350 3900 -Wire Wire Line - 7450 2100 7450 2400 -Wire Wire Line - 6900 1550 6900 1300 -Wire Wire Line - 6900 1300 5900 1300 -Wire Wire Line - 6900 1250 6900 1050 -Wire Wire Line - 7500 600 7500 900 -Wire Wire Line - 6350 5200 6400 5200 -Wire Wire Line - 2700 600 7500 600 -Wire Wire Line - 2250 5900 3100 5900 -Wire Wire Line - 2550 6300 3100 6300 -Wire Wire Line - 2400 4850 3050 4850 -Wire Wire Line - 2150 4450 3050 4450 -Wire Wire Line - 5450 5900 5450 5250 -Wire Wire Line - 5400 5150 5450 5150 -Wire Wire Line - 5400 5800 5400 5150 -Wire Wire Line - 6350 6650 6650 6650 -Connection ~ 5350 5900 -Connection ~ 5400 6700 -Wire Wire Line - 4900 6600 5450 6600 -Wire Wire Line - 4900 5800 4900 6600 -Wire Wire Line - 4900 5800 5400 5800 -Connection ~ 4950 4450 -Wire Wire Line - 4950 4450 4950 4900 -Wire Wire Line - 4850 3950 4850 4900 -Wire Wire Line - 2800 6700 3100 6700 -Wire Wire Line - 2800 5600 2800 6700 -Wire Wire Line - 4600 5600 2800 5600 -Wire Wire Line - 4600 5250 4600 5600 -Wire Wire Line - 2750 5250 3050 5250 -Wire Wire Line - 2750 4100 2750 5250 -Wire Wire Line - 4550 4100 2750 4100 -Wire Wire Line - 4550 3700 4550 4100 -Connection ~ 4850 4350 -Wire Wire Line - 4850 4350 5350 4350 -Connection ~ 4900 2900 -Wire Wire Line - 4900 2900 4900 3050 -Connection ~ 4800 2750 -Wire Wire Line - 5300 2750 5300 2800 -Wire Wire Line - 4800 2750 5300 2750 -Connection ~ 4800 1300 -Wire Wire Line - 4800 1300 4800 3050 -Wire Wire Line - 2700 3700 3000 3700 -Wire Wire Line - 2700 2500 2700 3700 -Wire Wire Line - 4650 2500 2700 2500 -Wire Wire Line - 4650 2100 4650 2500 -Wire Wire Line - 6900 1050 5300 1050 -Wire Wire Line - 5300 1050 5300 1300 -Connection ~ 6600 4700 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub deleted file mode 100644 index fd844be7..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic.sub +++ /dev/null @@ -1,50 +0,0 @@ -* Subcircuit CSLA_BEC1_logic -.subckt CSLA_BEC1_logic net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ -* /home/mallikarjuna/downloads/esim-1.1.2/src/subcircuitlibrary/csla_bec1_logic/csla_bec1_logic.cir -.include LOGIC_ADDER.sub -.include MUX.sub -* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and -* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_and -* u5 net-_u2-pad2_ net-_u2-pad1_ net-_u5-pad3_ d_xor -* u6 net-_u2-pad3_ net-_u3-pad1_ net-_u6-pad3_ d_xor -* u7 net-_u3-pad3_ net-_u7-pad2_ net-_u7-pad3_ d_xor -* u8 net-_u3-pad3_ net-_u8-pad2_ net-_u8-pad3_ d_xor -* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter -x3 net-_u1-pad1_ net-_u1-pad5_ net-_u9-pad2_ net-_u2-pad2_ net-_x1-pad3_ LOGIC_ADDER -x1 net-_u1-pad2_ net-_u1-pad6_ net-_x1-pad3_ net-_u2-pad1_ net-_x1-pad5_ LOGIC_ADDER -x2 net-_u1-pad3_ net-_u1-pad7_ net-_x1-pad5_ net-_u3-pad1_ net-_x2-pad5_ LOGIC_ADDER -x4 net-_u1-pad4_ net-_u1-pad8_ net-_x2-pad5_ net-_u7-pad2_ net-_u8-pad2_ LOGIC_ADDER -x7 net-_u1-pad9_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad10_ MUX -x5 net-_u1-pad9_ net-_u2-pad1_ net-_u5-pad3_ net-_u1-pad11_ MUX -x8 net-_u1-pad9_ net-_u3-pad1_ net-_u6-pad3_ net-_u1-pad12_ MUX -x6 net-_u1-pad9_ net-_u7-pad2_ net-_u7-pad3_ net-_u1-pad13_ MUX -x9 net-_u1-pad9_ net-_u8-pad2_ net-_u8-pad3_ net-_u1-pad14_ MUX -v1 net-_u9-pad1_ gnd 0 -* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1 -a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 -a3 [net-_u2-pad2_ net-_u2-pad1_ ] net-_u5-pad3_ u5 -a4 [net-_u2-pad3_ net-_u3-pad1_ ] net-_u6-pad3_ u6 -a5 [net-_u3-pad3_ net-_u7-pad2_ ] net-_u7-pad3_ u7 -a6 [net-_u3-pad3_ net-_u8-pad2_ ] net-_u8-pad3_ u8 -a7 net-_u2-pad2_ net-_u4-pad2_ u4 -a8 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u6 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u7 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u8 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge -.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) -* Control Statements - -.ends CSLA_BEC1_logic
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml deleted file mode 100644 index 55dd75da..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/CSLA_BEC1_logic_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source><v1 name="Source type">0</v1></source><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_xor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u8><u4 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u4><u9 name="type">adc_bridge<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter value for in_high (default=2.0)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter value for in_low (default=1.0)" /></u9></model><devicemodel /><subcircuit><x8><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x8><x9><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x9><x2><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x2><x3><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x3><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x1><x6><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x6><x7><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x7><x4><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LOGIC_ADDER</field></x4><x5><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/MUX</field></x5></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib deleted file mode 100644 index 34588988..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER-cache.lib +++ /dev/null @@ -1,82 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir deleted file mode 100644 index ec177d39..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir +++ /dev/null @@ -1,16 +0,0 @@ -* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 A B Net-_U2-Pad3_ d_and
-U4 Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and
-U3 A B Net-_U3-Pad3_ d_xor
-U5 Net-_U3-Pad3_ CIN SUM d_xor
-U6 Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or
-U1 A B CIN SUM CARRY PORT
-
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out deleted file mode 100644 index df9bcde6..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.cir.out +++ /dev/null @@ -1,32 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-
-* u2 a b net-_u2-pad3_ d_and
-* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3 a b net-_u3-pad3_ d_xor
-* u5 net-_u3-pad3_ cin sum d_xor
-* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
-* u1 a b cin sum carry port
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro deleted file mode 100644 index a2b9fa1f..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=Sat Jun 8 13:01:54 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch deleted file mode 100644 index d39a1b78..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sch +++ /dev/null @@ -1,245 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:LOGIC_ADDER-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5AB647D1
-P 4100 2200
-F 0 "U2" H 4100 2200 60 0000 C CNN
-F 1 "d_and" H 4150 2300 60 0000 C CNN
-F 2 "" H 4100 2200 60 0000 C CNN
-F 3 "" H 4100 2200 60 0000 C CNN
- 1 4100 2200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5AB648AD
-P 5250 2300
-F 0 "U4" H 5250 2300 60 0000 C CNN
-F 1 "d_and" H 5300 2400 60 0000 C CNN
-F 2 "" H 5250 2300 60 0000 C CNN
-F 3 "" H 5250 2300 60 0000 C CNN
- 1 5250 2300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U3
-U 1 1 5AB648E7
-P 4100 2750
-F 0 "U3" H 4100 2750 60 0000 C CNN
-F 1 "d_xor" H 4150 2850 47 0000 C CNN
-F 2 "" H 4100 2750 60 0000 C CNN
-F 3 "" H 4100 2750 60 0000 C CNN
- 1 4100 2750
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U5
-U 1 1 5AB6498F
-P 5250 2600
-F 0 "U5" H 5250 2600 60 0000 C CNN
-F 1 "d_xor" H 5300 2700 47 0000 C CNN
-F 2 "" H 5250 2600 60 0000 C CNN
-F 3 "" H 5250 2600 60 0000 C CNN
- 1 5250 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5AB64A11
-P 6250 2250
-F 0 "U6" H 6250 2250 60 0000 C CNN
-F 1 "d_or" H 6250 2350 60 0000 C CNN
-F 2 "" H 6250 2250 60 0000 C CNN
-F 3 "" H 6250 2250 60 0000 C CNN
- 1 6250 2250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5AB64A78
-P 2650 2100
-F 0 "U1" H 2700 2200 30 0000 C CNN
-F 1 "PORT" H 2650 2100 30 0000 C CNN
-F 2 "" H 2650 2100 60 0000 C CNN
-F 3 "" H 2650 2100 60 0000 C CNN
- 1 2650 2100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5AB64BE9
-P 2650 2300
-F 0 "U1" H 2700 2400 30 0000 C CNN
-F 1 "PORT" H 2650 2300 30 0000 C CNN
-F 2 "" H 2650 2300 60 0000 C CNN
-F 3 "" H 2650 2300 60 0000 C CNN
- 2 2650 2300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5AB64C18
-P 6300 2550
-F 0 "U1" H 6350 2650 30 0000 C CNN
-F 1 "PORT" H 6300 2550 30 0000 C CNN
-F 2 "" H 6300 2550 60 0000 C CNN
-F 3 "" H 6300 2550 60 0000 C CNN
- 4 6300 2550
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5AB64C59
-P 2650 2900
-F 0 "U1" H 2700 3000 30 0000 C CNN
-F 1 "PORT" H 2650 2900 30 0000 C CNN
-F 2 "" H 2650 2900 60 0000 C CNN
-F 3 "" H 2650 2900 60 0000 C CNN
- 3 2650 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5AB64C94
-P 7150 2200
-F 0 "U1" H 7200 2300 30 0000 C CNN
-F 1 "PORT" H 7150 2200 30 0000 C CNN
-F 2 "" H 7150 2200 60 0000 C CNN
-F 3 "" H 7150 2200 60 0000 C CNN
- 5 7150 2200
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 2900 2100 3650 2100
-Wire Wire Line
- 2900 2250 3650 2250
-Wire Wire Line
- 3650 2250 3650 2200
-Wire Wire Line
- 3400 2100 3400 2650
-Wire Wire Line
- 3400 2650 3650 2650
-Connection ~ 3400 2100
-Wire Wire Line
- 3150 2250 3150 2750
-Wire Wire Line
- 3150 2750 3650 2750
-Connection ~ 3150 2250
-Wire Wire Line
- 4550 2700 4550 2500
-Wire Wire Line
- 4550 2500 4800 2500
-Wire Wire Line
- 2900 2900 4800 2900
-Wire Wire Line
- 4800 2900 4800 2600
-Wire Wire Line
- 4700 2500 4700 2200
-Wire Wire Line
- 4700 2200 4800 2200
-Connection ~ 4700 2500
-Wire Wire Line
- 4800 2300 4600 2300
-Wire Wire Line
- 4600 2300 4600 2900
-Connection ~ 4600 2900
-Wire Wire Line
- 5700 2250 5800 2250
-Wire Wire Line
- 4550 2150 4550 2000
-Wire Wire Line
- 4550 2000 5800 2000
-Wire Wire Line
- 5800 2000 5800 2150
-Wire Wire Line
- 5700 2550 6050 2550
-Wire Wire Line
- 6700 2200 6900 2200
-Wire Wire Line
- 2900 2250 2900 2300
-Text GLabel 3000 1850 0 60 Input ~ 0
-A
-Text GLabel 3000 2500 0 60 Input ~ 0
-B
-Text GLabel 3000 3250 0 60 Input ~ 0
-CIN
-Wire Wire Line
- 3000 3250 3050 3250
-Wire Wire Line
- 3050 3250 3050 2900
-Connection ~ 3050 2900
-Wire Wire Line
- 3000 1850 3100 1850
-Wire Wire Line
- 3100 1850 3100 2100
-Connection ~ 3100 2100
-Wire Wire Line
- 3000 2500 3000 2250
-Connection ~ 3000 2250
-Text GLabel 6750 1700 0 60 Output ~ 0
-CARRY
-Text GLabel 5950 2800 0 60 Output ~ 0
-SUM
-Wire Wire Line
- 6750 1700 6800 1700
-Wire Wire Line
- 6800 1700 6800 2200
-Connection ~ 6800 2200
-Wire Wire Line
- 5950 2550 5950 2800
-Connection ~ 5950 2550
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub deleted file mode 100644 index a1e1cfac..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER.sub +++ /dev/null @@ -1,26 +0,0 @@ -* Subcircuit LOGIC_ADDER
-.subckt LOGIC_ADDER a b cin sum carry
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-* u2 a b net-_u2-pad3_ d_and
-* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3 a b net-_u3-pad3_ d_xor
-* u5 net-_u3-pad3_ cin sum d_xor
-* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends LOGIC_ADDER
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml deleted file mode 100644 index ab59f216..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/LOGIC_ADDER_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib deleted file mode 100644 index 9fa4b3f9..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX-cache.lib +++ /dev/null @@ -1,76 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir deleted file mode 100644 index 8d97f9a1..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir +++ /dev/null @@ -1,15 +0,0 @@ -* C:\eSim\eSim\src\SubcircuitLibrary\MUX\MUX.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:29:10 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and
-U4 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U4-Pad3_ d_and
-U5 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad4_ d_or
-U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
-
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out deleted file mode 100644 index 342293e7..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.cir.out +++ /dev/null @@ -1,28 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
-
-* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
-* u4 net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
-a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
-a4 net-_u1-pad1_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro deleted file mode 100644 index 07f53b67..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.pro +++ /dev/null @@ -1,43 +0,0 @@ -update=Sat Jun 8 12:53:13 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch deleted file mode 100644 index eb095e0e..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sch +++ /dev/null @@ -1,172 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U3
-U 1 1 5AB62CE3
-P 5050 2550
-F 0 "U3" H 5050 2550 60 0000 C CNN
-F 1 "d_and" H 5100 2650 60 0000 C CNN
-F 2 "" H 5050 2550 60 0000 C CNN
-F 3 "" H 5050 2550 60 0000 C CNN
- 1 5050 2550
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5AB62D59
-P 5050 3400
-F 0 "U4" H 5050 3400 60 0000 C CNN
-F 1 "d_and" H 5100 3500 60 0000 C CNN
-F 2 "" H 5050 3400 60 0000 C CNN
-F 3 "" H 5050 3400 60 0000 C CNN
- 1 5050 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U5
-U 1 1 5AB62DBD
-P 6300 2950
-F 0 "U5" H 6300 2950 60 0000 C CNN
-F 1 "d_or" H 6300 3050 60 0000 C CNN
-F 2 "" H 6300 2950 60 0000 C CNN
-F 3 "" H 6300 2950 60 0000 C CNN
- 1 6300 2950
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5500 2500 5550 2500
-Wire Wire Line
- 5550 2500 5550 2850
-Wire Wire Line
- 5550 2850 5850 2850
-Wire Wire Line
- 5500 3350 5550 3350
-Wire Wire Line
- 5550 3350 5550 2950
-Wire Wire Line
- 5550 2950 5850 2950
-$Comp
-L d_inverter U2
-U 1 1 5AB62FFA
-P 4200 2550
-F 0 "U2" H 4200 2450 60 0000 C CNN
-F 1 "d_inverter" H 4200 2700 60 0000 C CNN
-F 2 "" H 4250 2500 60 0000 C CNN
-F 3 "" H 4250 2500 60 0000 C CNN
- 1 4200 2550
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4500 2550 4600 2550
-$Comp
-L PORT U1
-U 1 1 5AB6307B
-P 3450 3300
-F 0 "U1" H 3500 3400 30 0000 C CNN
-F 1 "PORT" H 3450 3300 30 0000 C CNN
-F 2 "" H 3450 3300 60 0000 C CNN
-F 3 "" H 3450 3300 60 0000 C CNN
- 1 3450 3300
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3900 2550 3900 3300
-Wire Wire Line
- 3700 3300 4600 3300
-Connection ~ 3900 3300
-$Comp
-L PORT U1
-U 2 1 5AB631BF
-P 4100 2050
-F 0 "U1" H 4150 2150 30 0000 C CNN
-F 1 "PORT" H 4100 2050 30 0000 C CNN
-F 2 "" H 4100 2050 60 0000 C CNN
-F 3 "" H 4100 2050 60 0000 C CNN
- 2 4100 2050
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4350 2050 4600 2050
-Wire Wire Line
- 4600 2050 4600 2450
-$Comp
-L PORT U1
-U 3 1 5AB6340B
-P 4200 3850
-F 0 "U1" H 4250 3950 30 0000 C CNN
-F 1 "PORT" H 4200 3850 30 0000 C CNN
-F 2 "" H 4200 3850 60 0000 C CNN
-F 3 "" H 4200 3850 60 0000 C CNN
- 3 4200 3850
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4600 3400 4600 3850
-Wire Wire Line
- 4600 3850 4450 3850
-$Comp
-L PORT U1
-U 4 1 5AB63737
-P 7100 2900
-F 0 "U1" H 7150 3000 30 0000 C CNN
-F 1 "PORT" H 7100 2900 30 0000 C CNN
-F 2 "" H 7100 2900 60 0000 C CNN
-F 3 "" H 7100 2900 60 0000 C CNN
- 4 7100 2900
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 6750 2900 6850 2900
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub deleted file mode 100644 index 473dc907..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX.sub +++ /dev/null @@ -1,22 +0,0 @@ -* Subcircuit MUX
-.subckt MUX net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
-* c:\esim\esim\src\subcircuitlibrary\mux\mux.cir
-* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
-* u4 net-_u1-pad1_ net-_u1-pad3_ net-_u4-pad3_ d_and
-* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
-* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
-a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
-a2 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u4-pad3_ u4
-a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
-a4 net-_u1-pad1_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends MUX
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml b/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml deleted file mode 100644 index 6f43d20b..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/MUX_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u5><u2 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis b/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/CSLA_BEC1_logic/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/IB3858/IB3858-cache.lib b/src/SubcircuitLibrary/IB3858/IB3858-cache.lib deleted file mode 100644 index df4966f4..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_L -# -DEF eSim_L L 0 40 N N 1 F N -F0 "L" 1950 500 50 H V C CNN -F1 "eSim_L" 1950 650 50 H V C CNN -F2 "" 1950 550 60 V V C CNN -F3 "" 1950 550 60 V V C CNN -DRAW -A 1802 550 48 11 1789 0 1 0 N 1849 551 1754 551 -A 1899 550 51 11 1789 0 1 0 N 1949 551 1848 551 -A 1999 550 51 11 1789 0 1 0 N 2049 551 1948 551 -A 2100 550 50 11 1789 0 1 0 N 2149 551 2050 551 -X 1 1 1650 550 100 R 70 70 1 1 P -X 2 2 2250 550 100 L 70 70 1 1 P -ENDDRAW -ENDDEF -# -# eSim_R -# -DEF eSim_R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "eSim_R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/IB3858/IB3858.cir b/src/SubcircuitLibrary/IB3858/IB3858.cir deleted file mode 100644 index e89f69e1..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858.cir +++ /dev/null @@ -1,16 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/IB3858/IB3858.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 24 16:30:15 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -R1 Net-_R1-Pad1_ Net-_L1-Pad1_ 5.2 -L1 Net-_L1-Pad1_ Net-_C1-Pad1_ 3.08m -L2 Net-_C1-Pad1_ Net-_C1-Pad2_ 61.100458m -C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 896.8481u -R2 Net-_C1-Pad1_ Net-_C1-Pad2_ 73.6254 -U1 Net-_R1-Pad1_ Net-_C1-Pad2_ PORT - -.end diff --git a/src/SubcircuitLibrary/IB3858/IB3858.cir.out b/src/SubcircuitLibrary/IB3858/IB3858.cir.out deleted file mode 100644 index 3b84dfd6..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858.cir.out +++ /dev/null @@ -1,17 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ib3858/ib3858.cir - -r1 net-_r1-pad1_ net-_l1-pad1_ 5.2 -l1 net-_l1-pad1_ net-_c1-pad1_ 3.08m -l2 net-_c1-pad1_ net-_c1-pad2_ 61.100458m -c1 net-_c1-pad1_ net-_c1-pad2_ 896.8481u -r2 net-_c1-pad1_ net-_c1-pad2_ 73.6254 -* u1 net-_r1-pad1_ net-_c1-pad2_ port -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/IB3858/IB3858.pro b/src/SubcircuitLibrary/IB3858/IB3858.pro deleted file mode 100644 index 148e9ed5..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858.pro +++ /dev/null @@ -1,73 +0,0 @@ -update=22/05/2015 07:44:53 -version=1 -last_client=kicad -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice - diff --git a/src/SubcircuitLibrary/IB3858/IB3858.sch b/src/SubcircuitLibrary/IB3858/IB3858.sch deleted file mode 100644 index bbc79e75..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858.sch +++ /dev/null @@ -1,157 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:speaker-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L eSim_R R1 -U 1 1 5D10AD49 -P 6050 3150 -F 0 "R1" H 6100 3280 50 0000 C CNN -F 1 "5.2" H 6100 3200 50 0000 C CNN -F 2 "" H 6100 3130 30 0000 C CNN -F 3 "" V 6100 3200 30 0000 C CNN - 1 6050 3150 - 1 0 0 -1 -$EndComp -$Comp -L eSim_L L1 -U 1 1 5D10AD4A -P 4800 3650 -F 0 "L1" H 6750 4150 50 0000 C CNN -F 1 "3.08m" H 6750 4300 50 0000 C CNN -F 2 "" V 6750 4200 60 0000 C CNN -F 3 "" V 6750 4200 60 0000 C CNN - 1 4800 3650 - 1 0 0 -1 -$EndComp -$Comp -L eSim_L L2 -U 1 1 5D10AD4B -P 7300 1750 -F 0 "L2" H 9250 2250 50 0000 C CNN -F 1 "61.100458m" H 9250 2400 50 0000 C CNN -F 2 "" V 9250 2300 60 0000 C CNN -F 3 "" V 9250 2300 60 0000 C CNN - 1 7300 1750 - 0 1 1 0 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5D10AD4C -P 7350 3700 -F 0 "C1" H 7375 3800 50 0000 L CNN -F 1 "896.8481u" H 7375 3600 50 0000 L CNN -F 2 "" H 7388 3550 30 0000 C CNN -F 3 "" H 7350 3700 60 0000 C CNN - 1 7350 3700 - 1 0 0 -1 -$EndComp -$Comp -L eSim_R R2 -U 1 1 5D10AD4D -P 8450 3700 -F 0 "R2" H 8500 3830 50 0000 C CNN -F 1 "73.6254" H 8500 3750 50 0000 C CNN -F 2 "" H 8500 3680 30 0000 C CNN -F 3 "" V 8500 3750 30 0000 C CNN - 1 8450 3700 - 0 1 1 0 -$EndComp -Wire Wire Line - 7350 3850 7350 4350 -Connection ~ 7850 4350 -Wire Wire Line - 7850 4000 7850 4350 -Wire Wire Line - 8500 4350 8500 3900 -Connection ~ 7850 3100 -Wire Wire Line - 8500 3100 8500 3600 -Connection ~ 7350 3100 -Wire Wire Line - 7850 3100 7850 3400 -Wire Wire Line - 7350 3100 7350 3550 -Wire Wire Line - 7050 3100 8500 3100 -Wire Wire Line - 6250 3100 6450 3100 -Wire Wire Line - 7050 4350 8500 4350 -$Comp -L PORT U1 -U 1 1 5D10B0D2 -P 5250 3100 -F 0 "U1" H 5300 3200 30 0000 C CNN -F 1 "PORT" H 5250 3100 30 0000 C CNN -F 2 "" H 5250 3100 60 0000 C CNN -F 3 "" H 5250 3100 60 0000 C CNN - 1 5250 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D10B10F -P 6800 4350 -F 0 "U1" H 6850 4450 30 0000 C CNN -F 1 "PORT" H 6800 4350 30 0000 C CNN -F 2 "" H 6800 4350 60 0000 C CNN -F 3 "" H 6800 4350 60 0000 C CNN - 2 6800 4350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5950 3100 5500 3100 -Connection ~ 7350 4350 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/IB3858/IB3858.sub b/src/SubcircuitLibrary/IB3858/IB3858.sub deleted file mode 100644 index cc9a9809..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858.sub +++ /dev/null @@ -1,11 +0,0 @@ -* Subcircuit IB3858 -.subckt IB3858 net-_r1-pad1_ net-_c1-pad2_ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ib3858/ib3858.cir -r1 net-_r1-pad1_ net-_l1-pad1_ 5.2 -l1 net-_l1-pad1_ net-_c1-pad1_ 3.08m -l2 net-_c1-pad1_ net-_c1-pad2_ 61.100458m -c1 net-_c1-pad1_ net-_c1-pad2_ 896.8481u -r2 net-_c1-pad1_ net-_c1-pad2_ 73.6254 -* Control Statements - -.ends IB3858
\ No newline at end of file diff --git a/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml b/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml deleted file mode 100644 index 56ce5d3f..00000000 --- a/src/SubcircuitLibrary/IB3858/IB3858_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/IB3858/analysis b/src/SubcircuitLibrary/IB3858/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/IB3858/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib b/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib deleted file mode 100644 index cc25b0c9..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS-cache.lib +++ /dev/null @@ -1,146 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 w -X - 2 0 -450 300 U 50 50 1 1 w -ENDDRAW -ENDDEF -# -# GND -# -DEF GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_MOS_N -# -DEF eSim_MOS_N M 0 0 Y N 1 F N -F0 "M" 0 -150 50 H V R CNN -F1 "eSim_MOS_N" 100 -50 50 H V R CNN -F2 "" 300 -300 29 H V C CNN -F3 "" 100 -200 60 H V C CNN -DRAW -C 150 -200 111 0 1 10 N -P 2 0 1 10 130 -290 130 -250 N -P 2 0 1 0 130 -270 200 -270 N -P 2 0 1 10 130 -220 130 -180 N -P 2 0 1 0 130 -200 200 -200 N -P 2 0 1 10 130 -150 130 -110 N -P 2 0 1 0 130 -130 200 -130 N -P 2 0 1 0 200 -300 200 -270 N -P 2 0 1 0 200 -130 200 -100 N -P 3 0 1 10 110 -275 110 -125 110 -125 N -P 3 0 1 0 200 -200 300 -200 300 -250 N -P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F -X D 1 200 0 100 D 50 50 1 1 P -X G 2 -100 -200 210 R 50 50 1 1 P -X S 3 200 -400 100 U 50 50 1 1 P -X B 4 300 -350 98 U 47 47 1 1 P -ENDDRAW -ENDDEF -# -# eSim_MOS_P -# -DEF eSim_MOS_P M 0 0 Y N 1 F N -F0 "M" -50 50 50 H V R CNN -F1 "eSim_MOS_P" 50 150 50 H V R CNN -F2 "" 250 100 29 H V C CNN -F3 "" 50 0 60 H V C CNN -DRAW -C 100 0 111 0 1 10 N -P 2 0 1 0 80 -70 150 -70 N -P 2 0 1 10 80 -50 80 -90 N -P 2 0 1 0 80 0 150 0 N -P 2 0 1 10 80 20 80 -20 N -P 2 0 1 0 80 70 150 70 N -P 2 0 1 10 80 90 80 50 N -P 2 0 1 0 150 -70 150 -100 N -P 2 0 1 0 150 100 150 70 N -P 3 0 1 10 60 75 60 -75 60 -75 N -P 3 0 1 0 150 0 250 0 250 -50 N -P 4 0 1 0 140 0 100 -15 100 15 140 0 F -X D 1 150 200 100 D 50 50 1 1 P -X G 2 -150 0 210 R 50 50 1 1 P -X S 3 150 -200 100 U 50 50 1 1 P -X B 4 250 -150 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir deleted file mode 100644 index 44f1df81..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir +++ /dev/null @@ -1,15 +0,0 @@ -* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT -M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N -M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P -v1 Net-_M2-Pad1_ GND 5 -C1 Net-_C1-Pad1_ GND 1u - -.end diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out b/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out deleted file mode 100644 index cb2b6641..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir - -.include NMOS-180nm.lib -.include PMOS-180nm.lib -* u1 net-_m1-pad2_ net-_c1-pad1_ port -m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 -m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -v1 net-_m2-pad1_ gnd 5 -c1 net-_c1-pad1_ gnd 1u -.tran 0e-03 0e-03 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro b/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro deleted file mode 100644 index b3f410b6..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.pro +++ /dev/null @@ -1,73 +0,0 @@ -update=Sun Aug 25 15:54:56 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_User -LibName37=eSim_Plot -LibName38=eSim_PSpice -LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt - diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch deleted file mode 100644 index 13a7fc09..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sch +++ /dev/null @@ -1,189 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:eSim_Subckt -LIBS:INVCMOS-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "29 apr 2015" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5900 4000 5900 4150 -Connection ~ 5800 2450 -Connection ~ 5800 4150 -Wire Wire Line - 5900 4150 5800 4150 -Connection ~ 5050 3350 -Wire Wire Line - 4000 3350 5050 3350 -Wire Wire Line - 5050 3850 5500 3850 -Wire Wire Line - 5050 2700 5050 3850 -Wire Wire Line - 5050 2700 5500 2700 -Wire Wire Line - 5800 3650 5800 2900 -Wire Wire Line - 5800 2500 5800 2300 -Connection ~ 4200 3350 -$Comp -L PORT U1 -U 1 1 5D6263BC -P 3750 3350 -F 0 "U1" H 3800 3450 30 0000 C CNN -F 1 "PORT" H 3750 3350 30 0000 C CNN -F 2 "" H 3750 3350 60 0000 C CNN -F 3 "" H 3750 3350 60 0000 C CNN - 1 3750 3350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6050 3250 5800 3250 -Connection ~ 5800 3250 -Wire Wire Line - 5800 4050 5800 4550 -$Comp -L eSim_MOS_N M1 -U 1 1 5D6265DB -P 5600 3650 -F 0 "M1" H 5600 3500 50 0000 R CNN -F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN -F 2 "" H 5900 3350 29 0000 C CNN -F 3 "" H 5700 3450 60 0000 C CNN - 1 5600 3650 - 1 0 0 -1 -$EndComp -$Comp -L eSim_MOS_P M2 -U 1 1 5D626659 -P 5650 2700 -F 0 "M2" H 5600 2750 50 0000 R CNN -F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN -F 2 "" H 5900 2800 29 0000 C CNN -F 3 "" H 5700 2700 60 0000 C CNN - 1 5650 2700 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5900 2850 6050 2850 -Wire Wire Line - 6050 2850 6050 2450 -Wire Wire Line - 6050 2450 5800 2450 -Connection ~ 6000 3250 -Connection ~ 5800 4300 -$Comp -L GND #PWR1 -U 1 1 5D626C59 -P 5800 4550 -F 0 "#PWR1" H 5800 4300 50 0001 C CNN -F 1 "GND" H 5800 4400 50 0000 C CNN -F 2 "" H 5800 4550 50 0001 C CNN -F 3 "" H 5800 4550 50 0001 C CNN - 1 5800 4550 - 1 0 0 -1 -$EndComp -$Comp -L DC v1 -U 1 1 5D626C7F -P 6250 2300 -F 0 "v1" H 6050 2400 60 0000 C CNN -F 1 "5" H 6050 2250 60 0000 C CNN -F 2 "R1" H 5950 2300 60 0000 C CNN -F 3 "" H 6250 2300 60 0000 C CNN - 1 6250 2300 - 0 -1 -1 0 -$EndComp -$Comp -L GND #PWR2 -U 1 1 5D626CF6 -P 6850 2300 -F 0 "#PWR2" H 6850 2050 50 0001 C CNN -F 1 "GND" H 6850 2150 50 0000 C CNN -F 2 "" H 6850 2300 50 0001 C CNN -F 3 "" H 6850 2300 50 0001 C CNN - 1 6850 2300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6850 2300 6700 2300 -$Comp -L PORT U1 -U 2 1 5D626DCB -P 6300 3250 -F 0 "U1" H 6350 3350 30 0000 C CNN -F 1 "PORT" H 6300 3250 30 0000 C CNN -F 2 "" H 6300 3250 60 0000 C CNN -F 3 "" H 6300 3250 60 0000 C CNN - 2 6300 3250 - -1 0 0 1 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5D62796C -P 6050 3850 -F 0 "C1" H 6075 3950 50 0000 L CNN -F 1 "1u" H 6075 3750 50 0000 L CNN -F 2 "" H 6088 3700 30 0000 C CNN -F 3 "" H 6050 3850 60 0000 C CNN - 1 6050 3850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6050 3700 6050 3400 -Wire Wire Line - 6050 3400 6000 3400 -Wire Wire Line - 6000 3400 6000 3250 -Wire Wire Line - 6050 4000 6050 4300 -Wire Wire Line - 6050 4300 5800 4300 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub b/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub deleted file mode 100644 index 2319995c..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit INVCMOS -.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ -* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir -.include NMOS-180nm.lib -.include PMOS-180nm.lib -m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 -m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -v1 net-_m2-pad1_ gnd 5 -c1 net-_c1-pad1_ gnd 1u -* Control Statements - -.ends INVCMOS
\ No newline at end of file diff --git a/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml b/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml deleted file mode 100644 index e5bb98c7..00000000 --- a/src/SubcircuitLibrary/INVCMOS/INVCMOS_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib deleted file mode 100644 index 51e9b119..00000000 --- a/src/SubcircuitLibrary/INVCMOS/NMOS-180nm.lib +++ /dev/null @@ -1,13 +0,0 @@ -.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 -+ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 -+ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 -+ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 -+ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 -+ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 -+ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 -+ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 -+ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 -+ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 -+ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 -+ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 -+ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib b/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib deleted file mode 100644 index 032b5b95..00000000 --- a/src/SubcircuitLibrary/INVCMOS/PMOS-180nm.lib +++ /dev/null @@ -1,11 +0,0 @@ -.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 -+ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 -+ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 -+ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 -+ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 -+ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 -+ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 -+ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 -+ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 -+ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 -+ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/src/SubcircuitLibrary/INVCMOS/analysis b/src/SubcircuitLibrary/INVCMOS/analysis deleted file mode 100644 index 334c5333..00000000 --- a/src/SubcircuitLibrary/INVCMOS/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-03 0e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM108/LM108-cache.lib b/src/SubcircuitLibrary/LM108/LM108-cache.lib deleted file mode 100644 index 1d0c038e..00000000 --- a/src/SubcircuitLibrary/LM108/LM108-cache.lib +++ /dev/null @@ -1,120 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-X ~ 9 250 0 100 L 30 30 9 1 I
-X ~ 10 250 0 100 L 30 30 10 1 I
-X ~ 11 250 0 100 L 30 30 11 1 I
-X ~ 12 250 0 100 L 30 30 12 1 I
-X ~ 13 250 0 100 L 30 30 13 1 I
-X ~ 14 250 0 100 L 30 30 14 1 I
-X ~ 15 250 0 100 L 30 30 15 1 I
-X ~ 16 250 0 100 L 30 30 16 1 I
-X ~ 17 250 0 100 L 30 30 17 1 I
-X ~ 18 250 0 100 L 30 30 18 1 I
-X ~ 19 250 0 100 L 30 30 19 1 I
-X ~ 20 250 0 100 L 30 30 20 1 I
-X ~ 21 250 0 100 L 30 30 21 1 I
-X ~ 22 250 0 100 L 30 30 22 1 I
-X ~ 23 250 0 100 L 30 30 23 1 I
-X ~ 24 250 0 100 L 30 30 24 1 I
-X ~ 25 250 0 100 L 30 30 25 1 I
-X ~ 26 250 0 100 L 30 30 26 1 I
-ENDDRAW
-ENDDEF
-#
-# eSim_NJF
-#
-DEF eSim_NJF J 0 0 Y N 1 F N
-F0 "J" -100 50 50 H V R CNN
-F1 "eSim_NJF" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 3 0 1 10 10 75 10 -75 10 -75 N
-P 3 0 1 0 100 -100 100 -50 10 -50 N
-P 3 0 1 0 100 100 100 55 10 55 N
-P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
-X D 1 100 200 100 D 50 50 1 1 C
-X G 2 -200 0 210 R 50 50 1 1 I
-X S 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM108/LM108.cir b/src/SubcircuitLibrary/LM108/LM108.cir deleted file mode 100644 index f8d793b5..00000000 --- a/src/SubcircuitLibrary/LM108/LM108.cir +++ /dev/null @@ -1,59 +0,0 @@ -* C:\esim_1\eSim\src\SubcircuitLibrary\LM108\LM108.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 16:57:39
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R2 v+ Net-_Q2-Pad3_ 20k
-Q2 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q2-Pad3_ eSim_PNP
-Q5 Net-_Q13-Pad1_ Net-_Q2-Pad1_ Net-_Q11-Pad3_ eSim_PNP
-Q3 Net-_Q2-Pad1_ Net-_Q14-Pad1_ Net-_Q1-Pad1_ eSim_NPN
-Q7 CompensationA Net-_Q14-Pad1_ Net-_Q7-Pad3_ eSim_NPN
-Q9 CompensationA CompensationA Net-_Q9-Pad3_ eSim_PNP
-Q11 Net-_Q11-Pad1_ CompensationA Net-_Q11-Pad3_ eSim_PNP
-R3 v+ Net-_Q9-Pad3_ 20K
-R7 v+ Net-_Q11-Pad3_ 10K
-Q1 Net-_Q1-Pad1_ Input- Net-_Q1-Pad3_ eSim_NPN
-Q4 Net-_Q4-Pad1_ Input+ Input- eSim_NPN
-Q6 Net-_Q4-Pad1_ Input- Input+ eSim_NPN
-R1 Net-_Q1-Pad3_ Net-_Q10-Pad1_ 2K
-R5 Net-_Q4-Pad1_ Net-_Q12-Pad3_ 50K
-Q8 Net-_Q7-Pad3_ Input+ Net-_Q8-Pad3_ eSim_NPN
-R8 v+ Net-_Q15-Pad3_ 10K
-Q15 Net-_Q14-Pad1_ Net-_J1-Pad3_ Net-_Q15-Pad3_ eSim_PNP
-R12 CompensationB Net-_Q11-Pad1_ 5.6k
-Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN
-Q17 Net-_Q11-Pad1_ Net-_Q13-Pad1_ Net-_Q13-Pad3_ eSim_NPN
-Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_Q12-Pad3_ eSim_NPN
-R4 Net-_Q8-Pad3_ Net-_Q10-Pad1_ 2k
-Q12 V- Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_PNP
-Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
-Q18 Net-_J1-Pad3_ Net-_J1-Pad1_ Net-_Q18-Pad3_ eSim_NPN
-J1 Net-_J1-Pad1_ V- Net-_J1-Pad3_ eSim_NJF
-R13 Net-_J1-Pad1_ Net-_Q16-Pad2_ 940
-R14 Net-_Q18-Pad3_ Net-_Q24-Pad2_ 20k
-Q24 Net-_Q13-Pad3_ Net-_Q24-Pad2_ Net-_Q24-Pad3_ eSim_NPN
-R6 Net-_Q10-Pad3_ Net-_R10-Pad1_ 6.4K
-R9 Net-_Q10-Pad2_ Net-_R10-Pad1_ 60K
-R11 Net-_Q18-Pad3_ Net-_Q19-Pad3_ 20K
-R10 Net-_R10-Pad1_ Net-_Q19-Pad3_ 500
-R15 Net-_Q19-Pad3_ V- 1K
-Q19 Net-_Q16-Pad2_ Net-_Q18-Pad3_ Net-_Q19-Pad3_ eSim_NPN
-R17 Net-_Q24-Pad3_ V- 820
-Q21 v+ Net-_J1-Pad3_ Net-_Q20-Pad1_ eSim_NPN
-Q20 Net-_Q20-Pad1_ Net-_Q11-Pad1_ Net-_Q13-Pad3_ eSim_NPN
-R16 Net-_J1-Pad3_ Net-_Q23-Pad1_ 2K
-Q23 Net-_Q23-Pad1_ Net-_J1-Pad3_ Net-_Q22-Pad3_ eSim_NPN
-Q26 v+ Net-_Q23-Pad1_ Net-_Q25-Pad2_ eSim_NPN
-Q25 Net-_Q23-Pad1_ Net-_Q25-Pad2_ Output eSim_NPN
-Q22 V- Net-_Q13-Pad3_ Net-_Q22-Pad3_ eSim_PNP
-Q27 V- Net-_Q13-Pad3_ Net-_Q27-Pad3_ eSim_PNP
-R18 Net-_Q25-Pad2_ Net-_Q27-Pad3_ 240
-R19 Net-_Q25-Pad2_ Output 90
-U1 CompensationA Input+ Input- V- Output v+ CompensationB PORT
-Q29 Net-_J1-Pad3_ Net-_J1-Pad3_ v+ eSim_PNP
-Q16 Net-_J1-Pad3_ Net-_Q16-Pad2_ Net-_Q10-Pad2_ eSim_NPN
-
-.end
diff --git a/src/SubcircuitLibrary/LM108/LM108.cir.out b/src/SubcircuitLibrary/LM108/LM108.cir.out deleted file mode 100644 index 6e2ff4a1..00000000 --- a/src/SubcircuitLibrary/LM108/LM108.cir.out +++ /dev/null @@ -1,63 +0,0 @@ -* c:\esim_1\esim\src\subcircuitlibrary\lm108\lm108.cir
-
-.include PNP.lib
-.include NJF.lib
-.include NPN.lib
-r2 v+ net-_q2-pad3_ 20k
-q2 net-_q2-pad1_ net-_q2-pad1_ net-_q2-pad3_ Q2N2907A
-q5 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad3_ Q2N2907A
-q3 net-_q2-pad1_ net-_q14-pad1_ net-_q1-pad1_ Q2N2222
-q7 compensationa net-_q14-pad1_ net-_q7-pad3_ Q2N2222
-q9 compensationa compensationa net-_q9-pad3_ Q2N2907A
-q11 net-_q11-pad1_ compensationa net-_q11-pad3_ Q2N2907A
-r3 v+ net-_q9-pad3_ 20k
-r7 v+ net-_q11-pad3_ 10k
-q1 net-_q1-pad1_ input- net-_q1-pad3_ Q2N2222
-q4 net-_q4-pad1_ input+ input- Q2N2222
-q6 net-_q4-pad1_ input- input+ Q2N2222
-r1 net-_q1-pad3_ net-_q10-pad1_ 2k
-r5 net-_q4-pad1_ net-_q12-pad3_ 50k
-q8 net-_q7-pad3_ input+ net-_q8-pad3_ Q2N2222
-r8 v+ net-_q15-pad3_ 10k
-q15 net-_q14-pad1_ net-_j1-pad3_ net-_q15-pad3_ Q2N2907A
-r12 compensationb net-_q11-pad1_ 5.6k
-q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q17 net-_q11-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q14 net-_q14-pad1_ net-_q14-pad1_ net-_q12-pad3_ Q2N2222
-r4 net-_q8-pad3_ net-_q10-pad1_ 2k
-q12 v- net-_q10-pad1_ net-_q12-pad3_ Q2N2907A
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q18 net-_j1-pad3_ net-_j1-pad1_ net-_q18-pad3_ Q2N2222
-j1 net-_j1-pad1_ v- net-_j1-pad3_ J2N3819
-r13 net-_j1-pad1_ net-_q16-pad2_ 940
-r14 net-_q18-pad3_ net-_q24-pad2_ 20k
-q24 net-_q13-pad3_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222
-r6 net-_q10-pad3_ net-_r10-pad1_ 6.4k
-r9 net-_q10-pad2_ net-_r10-pad1_ 60k
-r11 net-_q18-pad3_ net-_q19-pad3_ 20k
-r10 net-_r10-pad1_ net-_q19-pad3_ 500
-r15 net-_q19-pad3_ v- 1k
-q19 net-_q16-pad2_ net-_q18-pad3_ net-_q19-pad3_ Q2N2222
-r17 net-_q24-pad3_ v- 820
-q21 v+ net-_j1-pad3_ net-_q20-pad1_ Q2N2222
-q20 net-_q20-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-r16 net-_j1-pad3_ net-_q23-pad1_ 2k
-q23 net-_q23-pad1_ net-_j1-pad3_ net-_q22-pad3_ Q2N2222
-q26 v+ net-_q23-pad1_ net-_q25-pad2_ Q2N2222
-q25 net-_q23-pad1_ net-_q25-pad2_ output Q2N2222
-q22 v- net-_q13-pad3_ net-_q22-pad3_ Q2N2907A
-q27 v- net-_q13-pad3_ net-_q27-pad3_ Q2N2907A
-r18 net-_q25-pad2_ net-_q27-pad3_ 240
-r19 net-_q25-pad2_ output 90
-* u1 compensationa input+ input- v- output v+ compensationb port
-q29 net-_j1-pad3_ net-_j1-pad3_ v+ Q2N2907A
-q16 net-_j1-pad3_ net-_q16-pad2_ net-_q10-pad2_ Q2N2222
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LM108/LM108.pro b/src/SubcircuitLibrary/LM108/LM108.pro deleted file mode 100644 index c76222d6..00000000 --- a/src/SubcircuitLibrary/LM108/LM108.pro +++ /dev/null @@ -1,83 +0,0 @@ -update=03/31/19 17:48:06
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../../../Program Files (x86)/KiCad/share/library
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_PSpice
-LibName38=eSim_Sources
-LibName39=eSim_User
-LibName40=eSim_Subckt
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Spice
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
-LabSize=60
diff --git a/src/SubcircuitLibrary/LM108/LM108.sch b/src/SubcircuitLibrary/LM108/LM108.sch deleted file mode 100644 index a9735ce5..00000000 --- a/src/SubcircuitLibrary/LM108/LM108.sch +++ /dev/null @@ -1,1013 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_User
-LIBS:eSim_Subckt
-LIBS:LM108-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_R R2
-U 1 1 5C9DB838
-P 2750 1400
-F 0 "R2" H 2800 1530 50 0000 C CNN
-F 1 "20k" H 2800 1450 50 0000 C CNN
-F 2 "" H 2800 1380 30 0000 C CNN
-F 3 "" V 2800 1450 30 0000 C CNN
- 1 2750 1400
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_PNP Q2
-U 1 1 5C9DB867
-P 2900 1975
-F 0 "Q2" H 2800 2025 50 0000 R CNN
-F 1 "eSim_PNP" H 2850 2125 50 0000 R CNN
-F 2 "" H 3100 2075 29 0000 C CNN
-F 3 "" H 2900 1975 60 0000 C CNN
- 1 2900 1975
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q5
-U 1 1 5C9DB8A6
-P 3350 1975
-F 0 "Q5" H 3250 2025 50 0000 R CNN
-F 1 "eSim_PNP" H 3300 2125 50 0000 R CNN
-F 2 "" H 3550 2075 29 0000 C CNN
-F 3 "" H 3350 1975 60 0000 C CNN
- 1 3350 1975
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5C9DB912
-P 2900 2625
-F 0 "Q3" H 2800 2675 50 0000 R CNN
-F 1 "eSim_NPN" H 2850 2775 50 0000 R CNN
-F 2 "" H 3100 2725 29 0000 C CNN
-F 3 "" H 2900 2625 60 0000 C CNN
- 1 2900 2625
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q7
-U 1 1 5C9DB94B
-P 3600 2625
-F 0 "Q7" H 3500 2675 50 0000 R CNN
-F 1 "eSim_NPN" H 3550 2775 50 0000 R CNN
-F 2 "" H 3800 2725 29 0000 C CNN
-F 3 "" H 3600 2625 60 0000 C CNN
- 1 3600 2625
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q9
-U 1 1 5C9DB994
-P 3800 2075
-F 0 "Q9" H 3700 2125 50 0000 R CNN
-F 1 "eSim_PNP" H 3750 2225 50 0000 R CNN
-F 2 "" H 4000 2175 29 0000 C CNN
-F 3 "" H 3800 2075 60 0000 C CNN
- 1 3800 2075
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q11
-U 1 1 5C9DB9EF
-P 4275 2075
-F 0 "Q11" H 4175 2125 50 0000 R CNN
-F 1 "eSim_PNP" H 4225 2225 50 0000 R CNN
-F 2 "" H 4475 2175 29 0000 C CNN
-F 3 "" H 4275 2075 60 0000 C CNN
- 1 4275 2075
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 2800 1600 2800 1775
-Wire Wire Line
- 3100 1975 3150 1975
-Wire Wire Line
- 3125 1975 3125 2225
-Wire Wire Line
- 3125 2225 2800 2225
-Wire Wire Line
- 2800 2175 2800 2425
-Connection ~ 3125 1975
-Wire Wire Line
- 4000 2075 4075 2075
-Wire Wire Line
- 3700 2275 3700 2425
-Wire Wire Line
- 4050 1100 4050 2325
-Wire Wire Line
- 4050 2325 3700 2325
-Connection ~ 3700 2325
-Connection ~ 4050 2075
-Connection ~ 2800 2225
-Wire Wire Line
- 3100 2625 3400 2625
-$Comp
-L eSim_R R3
-U 1 1 5C9DBD46
-P 3650 1400
-F 0 "R3" H 3700 1530 50 0000 C CNN
-F 1 "20K" H 3700 1450 50 0000 C CNN
-F 2 "" H 3700 1380 30 0000 C CNN
-F 3 "" V 3700 1450 30 0000 C CNN
- 1 3650 1400
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R7
-U 1 1 5C9DBD83
-P 4325 1400
-F 0 "R7" H 4375 1530 50 0000 C CNN
-F 1 "10K" H 4375 1450 50 0000 C CNN
-F 2 "" H 4375 1380 30 0000 C CNN
-F 3 "" V 4375 1450 30 0000 C CNN
- 1 4325 1400
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 3700 1600 3700 1875
-Wire Wire Line
- 4375 1600 4375 1875
-Wire Wire Line
- 3450 1775 3450 1700
-Wire Wire Line
- 3450 1700 4375 1700
-Connection ~ 4375 1700
-Wire Wire Line
- 2800 1300 2800 1225
-Wire Wire Line
- 2800 1225 7575 1225
-Wire Wire Line
- 3700 1225 3700 1300
-Wire Wire Line
- 4375 1225 4375 1300
-Connection ~ 3700 1225
-$Comp
-L eSim_NPN Q1
-U 1 1 5C9DBEE9
-P 2650 3375
-F 0 "Q1" H 2550 3425 50 0000 R CNN
-F 1 "eSim_NPN" H 2600 3525 50 0000 R CNN
-F 2 "" H 2850 3475 29 0000 C CNN
-F 3 "" H 2650 3375 60 0000 C CNN
- 1 2650 3375
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 2750 3175 2750 2825
-Wire Wire Line
- 2750 2825 2800 2825
-Wire Wire Line
- 2450 3375 2375 3375
-$Comp
-L eSim_NPN Q4
-U 1 1 5C9DBF74
-P 2950 3975
-F 0 "Q4" H 2850 4025 50 0000 R CNN
-F 1 "eSim_NPN" H 2900 4125 50 0000 R CNN
-F 2 "" H 3150 4075 29 0000 C CNN
-F 3 "" H 2950 3975 60 0000 C CNN
- 1 2950 3975
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q6
-U 1 1 5C9DBFBB
-P 3500 3975
-F 0 "Q6" H 3400 4025 50 0000 R CNN
-F 1 "eSim_NPN" H 3450 4125 50 0000 R CNN
-F 2 "" H 3700 4075 29 0000 C CNN
-F 3 "" H 3500 3975 60 0000 C CNN
- 1 3500 3975
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3600 3775 3600 3650
-Wire Wire Line
- 2850 3650 4050 3650
-Wire Wire Line
- 2850 3650 2850 3775
-Wire Wire Line
- 3150 3975 3150 4175
-Wire Wire Line
- 3150 4175 3600 4175
-Wire Wire Line
- 3300 4250 3300 3975
-Wire Wire Line
- 2450 4250 3300 4250
-Wire Wire Line
- 2850 4250 2850 4175
-Wire Wire Line
- 2450 4250 2450 3375
-Connection ~ 2850 4250
-$Comp
-L eSim_R R1
-U 1 1 5C9DC222
-P 2700 5000
-F 0 "R1" H 2750 5130 50 0000 C CNN
-F 1 "2K" H 2750 5050 50 0000 C CNN
-F 2 "" H 2750 4980 30 0000 C CNN
-F 3 "" V 2750 5050 30 0000 C CNN
- 1 2700 5000
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 2750 3575 2750 4900
-$Comp
-L eSim_R R5
-U 1 1 5C9DC2A7
-P 4150 3700
-F 0 "R5" H 4200 3830 50 0000 C CNN
-F 1 "50K" H 4200 3750 50 0000 C CNN
-F 2 "" H 4200 3680 30 0000 C CNN
-F 3 "" V 4200 3750 30 0000 C CNN
- 1 4150 3700
- 1 0 0 -1
-$EndComp
-Connection ~ 3600 3650
-$Comp
-L eSim_NPN Q8
-U 1 1 5C9DC459
-P 3625 4425
-F 0 "Q8" H 3525 4475 50 0000 R CNN
-F 1 "eSim_NPN" H 3575 4575 50 0000 R CNN
-F 2 "" H 3825 4525 29 0000 C CNN
-F 3 "" H 3625 4425 60 0000 C CNN
- 1 3625 4425
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3400 4425 3400 4175
-Wire Wire Line
- 2400 4425 3425 4425
-Connection ~ 3400 4175
-Wire Wire Line
- 3725 4225 3725 2825
-Wire Wire Line
- 3725 2825 3700 2825
-$Comp
-L eSim_R R8
-U 1 1 5C9DCB0B
-P 4575 1400
-F 0 "R8" H 4625 1530 50 0000 C CNN
-F 1 "10K" H 4625 1450 50 0000 C CNN
-F 2 "" H 4625 1380 30 0000 C CNN
-F 3 "" V 4625 1450 30 0000 C CNN
- 1 4575 1400
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 4625 1225 4625 1300
-Connection ~ 4375 1225
-$Comp
-L eSim_PNP Q15
-U 1 1 5C9DCBA9
-P 4775 1850
-F 0 "Q15" H 4675 1900 50 0000 R CNN
-F 1 "eSim_PNP" H 4725 2000 50 0000 R CNN
-F 2 "" H 4975 1950 29 0000 C CNN
-F 3 "" H 4775 1850 60 0000 C CNN
- 1 4775 1850
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 4675 1650 4625 1650
-Wire Wire Line
- 4625 1650 4625 1600
-Connection ~ 4625 1225
-$Comp
-L eSim_R R12
-U 1 1 5C9DC058
-P 5550 1925
-F 0 "R12" H 5600 2055 50 0000 C CNN
-F 1 "5.6k" H 5600 1975 50 0000 C CNN
-F 2 "" H 5600 1905 30 0000 C CNN
-F 3 "" V 5600 1975 30 0000 C CNN
- 1 5550 1925
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 5600 2125 5600 2550
-Wire Wire Line
- 4375 2275 5725 2275
-$Comp
-L eSim_NPN Q13
-U 1 1 5C9DC257
-P 4525 2750
-F 0 "Q13" H 4425 2800 50 0000 R CNN
-F 1 "eSim_NPN" H 4475 2900 50 0000 R CNN
-F 2 "" H 4725 2850 29 0000 C CNN
-F 3 "" H 4525 2750 60 0000 C CNN
- 1 4525 2750
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q17
-U 1 1 5C9DC2B6
-P 5500 2750
-F 0 "Q17" H 5400 2800 50 0000 R CNN
-F 1 "eSim_NPN" H 5450 2900 50 0000 R CNN
-F 2 "" H 5700 2850 29 0000 C CNN
-F 3 "" H 5500 2750 60 0000 C CNN
- 1 5500 2750
- 1 0 0 -1
-$EndComp
-Connection ~ 5600 2275
-Wire Wire Line
- 4725 2750 5300 2750
-Wire Wire Line
- 3450 2175 3450 2400
-Wire Wire Line
- 3450 2400 5050 2400
-Wire Wire Line
- 4425 2400 4425 2550
-Wire Wire Line
- 5050 2400 5050 2750
-Connection ~ 5050 2750
-Connection ~ 4425 2400
-Wire Wire Line
- 4425 2950 4425 3075
-Wire Wire Line
- 4425 3075 7275 3075
-Wire Wire Line
- 5600 3075 5600 2950
-$Comp
-L eSim_NPN Q14
-U 1 1 5C9DC732
-P 4525 3400
-F 0 "Q14" H 4425 3450 50 0000 R CNN
-F 1 "eSim_NPN" H 4475 3550 50 0000 R CNN
-F 2 "" H 4725 3500 29 0000 C CNN
-F 3 "" H 4525 3400 60 0000 C CNN
- 1 4525 3400
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 3200 3200 4725 3200
-Wire Wire Line
- 4725 2225 4725 3400
-Wire Wire Line
- 4725 2225 4675 2225
-Wire Wire Line
- 4675 2225 4675 2050
-Connection ~ 4725 3200
-Wire Wire Line
- 3200 3200 3200 2625
-Connection ~ 3200 2625
-Connection ~ 4425 3200
-Wire Wire Line
- 4425 3600 4425 5125
-Wire Wire Line
- 4425 3650 4350 3650
-$Comp
-L eSim_R R4
-U 1 1 5C9DCD74
-P 3675 5000
-F 0 "R4" H 3725 5130 50 0000 C CNN
-F 1 "2k" H 3725 5050 50 0000 C CNN
-F 2 "" H 3725 4980 30 0000 C CNN
-F 3 "" V 3725 5050 30 0000 C CNN
- 1 3675 5000
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 3725 4625 3725 4900
-Wire Wire Line
- 3725 5200 3725 5600
-Wire Wire Line
- 2750 5325 4125 5325
-Wire Wire Line
- 2750 5325 2750 5200
-$Comp
-L eSim_PNP Q12
-U 1 1 5C9DD197
-P 4325 5325
-F 0 "Q12" H 4225 5375 50 0000 R CNN
-F 1 "eSim_PNP" H 4275 5475 50 0000 R CNN
-F 2 "" H 4525 5425 29 0000 C CNN
-F 3 "" H 4325 5325 60 0000 C CNN
- 1 4325 5325
- 1 0 0 1
-$EndComp
-Connection ~ 3725 5325
-Connection ~ 4425 3650
-$Comp
-L eSim_NPN Q10
-U 1 1 5C9DD5DD
-P 3825 5800
-F 0 "Q10" H 3725 5850 50 0000 R CNN
-F 1 "eSim_NPN" H 3775 5950 50 0000 R CNN
-F 2 "" H 4025 5900 29 0000 C CNN
-F 3 "" H 3825 5800 60 0000 C CNN
- 1 3825 5800
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 4825 5225 4825 5875
-Wire Wire Line
- 4825 5800 4025 5800
-$Comp
-L eSim_NPN Q18
-U 1 1 5C9DDBBA
-P 5650 4175
-F 0 "Q18" H 5550 4225 50 0000 R CNN
-F 1 "eSim_NPN" H 5600 4325 50 0000 R CNN
-F 2 "" H 5850 4275 29 0000 C CNN
-F 3 "" H 5650 4175 60 0000 C CNN
- 1 5650 4175
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NJF J1
-U 1 1 5C9DDDE9
-P 6400 4100
-F 0 "J1" H 6300 4150 50 0000 R CNN
-F 1 "eSim_NJF" H 6350 4250 50 0000 R CNN
-F 2 "" H 6600 4200 29 0000 C CNN
-F 3 "" H 6400 4100 60 0000 C CNN
- 1 6400 4100
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_R R13
-U 1 1 5C9DFBCC
-P 6250 4625
-F 0 "R13" H 6300 4755 50 0000 C CNN
-F 1 "940" H 6300 4675 50 0000 C CNN
-F 2 "" H 6300 4605 30 0000 C CNN
-F 3 "" V 6300 4675 30 0000 C CNN
- 1 6250 4625
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 6300 4300 6300 4525
-Wire Wire Line
- 5125 5025 6300 5025
-Wire Wire Line
- 6300 4825 6300 5475
-$Comp
-L eSim_R R14
-U 1 1 5C9DFE3D
-P 6500 4550
-F 0 "R14" H 6550 4680 50 0000 C CNN
-F 1 "20k" H 6550 4600 50 0000 C CNN
-F 2 "" H 6550 4530 30 0000 C CNN
-F 3 "" V 6550 4600 30 0000 C CNN
- 1 6500 4550
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 6400 4500 5550 4500
-Wire Wire Line
- 5550 4375 5550 5875
-Wire Wire Line
- 4425 5525 6850 5525
-Wire Wire Line
- 6850 4100 6850 6250
-Wire Wire Line
- 6850 4100 6600 4100
-$Comp
-L eSim_NPN Q24
-U 1 1 5C9E055D
-P 7225 4500
-F 0 "Q24" H 7125 4550 50 0000 R CNN
-F 1 "eSim_NPN" H 7175 4650 50 0000 R CNN
-F 2 "" H 7425 4600 29 0000 C CNN
-F 3 "" H 7225 4500 60 0000 C CNN
- 1 7225 4500
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7025 4500 6700 4500
-$Comp
-L eSim_R R6
-U 1 1 5C9E0948
-P 4225 6300
-F 0 "R6" H 4275 6430 50 0000 C CNN
-F 1 "6.4K" H 4275 6350 50 0000 C CNN
-F 2 "" H 4275 6280 30 0000 C CNN
-F 3 "" V 4275 6350 30 0000 C CNN
- 1 4225 6300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R9
-U 1 1 5C9E09B9
-P 4775 5975
-F 0 "R9" H 4825 6105 50 0000 C CNN
-F 1 "60K" H 4825 6025 50 0000 C CNN
-F 2 "" H 4825 5955 30 0000 C CNN
-F 3 "" V 4825 6025 30 0000 C CNN
- 1 4775 5975
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5C9E0B22
-P 5500 5975
-F 0 "R11" H 5550 6105 50 0000 C CNN
-F 1 "20K" H 5550 6025 50 0000 C CNN
-F 2 "" H 5550 5955 30 0000 C CNN
-F 3 "" V 5550 6025 30 0000 C CNN
- 1 5500 5975
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R10
-U 1 1 5C9E0B8F
-P 5125 6300
-F 0 "R10" H 5175 6430 50 0000 C CNN
-F 1 "500" H 5175 6350 50 0000 C CNN
-F 2 "" H 5175 6280 30 0000 C CNN
-F 3 "" V 5175 6350 30 0000 C CNN
- 1 5125 6300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R15
-U 1 1 5C9E0BFA
-P 6500 6300
-F 0 "R15" H 6550 6430 50 0000 C CNN
-F 1 "1K" H 6550 6350 50 0000 C CNN
-F 2 "" H 6550 6280 30 0000 C CNN
-F 3 "" V 6550 6350 30 0000 C CNN
- 1 6500 6300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q19
-U 1 1 5C9E0C83
-P 5750 5675
-F 0 "Q19" H 5650 5725 50 0000 R CNN
-F 1 "eSim_NPN" H 5700 5825 50 0000 R CNN
-F 2 "" H 5950 5775 29 0000 C CNN
-F 3 "" H 5750 5675 60 0000 C CNN
- 1 5750 5675
- 1 0 0 -1
-$EndComp
-Connection ~ 5550 4500
-Connection ~ 5550 5675
-Wire Wire Line
- 5550 6175 5550 6250
-Wire Wire Line
- 5325 6250 6400 6250
-Wire Wire Line
- 4425 6250 5025 6250
-Wire Wire Line
- 4825 6250 4825 6175
-Connection ~ 4825 6250
-Connection ~ 4825 5800
-Wire Wire Line
- 4125 6250 3725 6250
-Wire Wire Line
- 3725 6250 3725 6000
-Connection ~ 5550 6250
-Wire Wire Line
- 5850 5875 6225 5875
-Wire Wire Line
- 6225 5875 6225 6250
-Connection ~ 6225 6250
-Wire Wire Line
- 6700 6250 8600 6250
-Connection ~ 6850 5525
-Wire Wire Line
- 6300 5475 5850 5475
-Connection ~ 6300 5025
-$Comp
-L eSim_R R17
-U 1 1 5C9E17A1
-P 7275 5325
-F 0 "R17" H 7325 5455 50 0000 C CNN
-F 1 "820" H 7325 5375 50 0000 C CNN
-F 2 "" H 7325 5305 30 0000 C CNN
-F 3 "" V 7325 5375 30 0000 C CNN
- 1 7275 5325
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 7325 4700 7325 5225
-Wire Wire Line
- 7325 6250 7325 5525
-Connection ~ 6850 6250
-$Comp
-L eSim_NPN Q21
-U 1 1 5C9E2938
-P 6125 1525
-F 0 "Q21" H 6025 1575 50 0000 R CNN
-F 1 "eSim_NPN" H 6075 1675 50 0000 R CNN
-F 2 "" H 6325 1625 29 0000 C CNN
-F 3 "" H 6125 1525 60 0000 C CNN
- 1 6125 1525
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q20
-U 1 1 5C9E29AB
-P 5925 2275
-F 0 "Q20" H 5825 2325 50 0000 R CNN
-F 1 "eSim_NPN" H 5875 2425 50 0000 R CNN
-F 2 "" H 6125 2375 29 0000 C CNN
-F 3 "" H 5925 2275 60 0000 C CNN
- 1 5925 2275
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 6025 1725 6025 2075
-Wire Wire Line
- 5700 1300 5700 1675
-Wire Wire Line
- 7575 1300 8450 1300
-Wire Wire Line
- 6375 1300 6375 1800
-Wire Wire Line
- 6325 1525 6675 1525
-$Comp
-L eSim_R R16
-U 1 1 5C9E2CC0
-P 6775 1575
-F 0 "R16" H 6825 1705 50 0000 C CNN
-F 1 "2K" H 6825 1625 50 0000 C CNN
-F 2 "" H 6825 1555 30 0000 C CNN
-F 3 "" V 6825 1625 30 0000 C CNN
- 1 6775 1575
- 1 0 0 -1
-$EndComp
-Connection ~ 6375 1525
-$Comp
-L eSim_NPN Q23
-U 1 1 5C9E2F0C
-P 6875 1800
-F 0 "Q23" H 6775 1850 50 0000 R CNN
-F 1 "eSim_NPN" H 6825 1950 50 0000 R CNN
-F 2 "" H 7075 1900 29 0000 C CNN
-F 3 "" H 6875 1800 60 0000 C CNN
- 1 6875 1800
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 6975 1525 6975 1600
-Wire Wire Line
- 6375 1800 6675 1800
-$Comp
-L eSim_NPN Q26
-U 1 1 5C9E318C
-P 7475 1525
-F 0 "Q26" H 7375 1575 50 0000 R CNN
-F 1 "eSim_NPN" H 7425 1675 50 0000 R CNN
-F 2 "" H 7675 1625 29 0000 C CNN
-F 3 "" H 7475 1525 60 0000 C CNN
- 1 7475 1525
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 6975 1525 7275 1525
-$Comp
-L eSim_NPN Q25
-U 1 1 5C9E32C5
-P 7300 1800
-F 0 "Q25" H 7200 1850 50 0000 R CNN
-F 1 "eSim_NPN" H 7250 1950 50 0000 R CNN
-F 2 "" H 7500 1900 29 0000 C CNN
-F 3 "" H 7300 1800 60 0000 C CNN
- 1 7300 1800
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 7200 1600 7200 1525
-Connection ~ 7200 1525
-Wire Wire Line
- 7575 1725 7575 2275
-Wire Wire Line
- 7500 1800 7825 1800
-Wire Wire Line
- 7575 1225 7575 1325
-$Comp
-L eSim_PNP Q22
-U 1 1 5C9E36C9
-P 6850 2775
-F 0 "Q22" H 6750 2825 50 0000 R CNN
-F 1 "eSim_PNP" H 6800 2925 50 0000 R CNN
-F 2 "" H 7050 2875 29 0000 C CNN
-F 3 "" H 6850 2775 60 0000 C CNN
- 1 6850 2775
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 6975 2000 6975 2575
-Wire Wire Line
- 6975 2575 6950 2575
-Connection ~ 5600 3075
-Wire Wire Line
- 6025 3075 6025 2475
-Wire Wire Line
- 6650 2775 6650 3325
-Connection ~ 6025 3075
-$Comp
-L eSim_PNP Q27
-U 1 1 5C9E3F8C
-P 7475 3075
-F 0 "Q27" H 7375 3125 50 0000 R CNN
-F 1 "eSim_PNP" H 7425 3225 50 0000 R CNN
-F 2 "" H 7675 3175 29 0000 C CNN
-F 3 "" H 7475 3075 60 0000 C CNN
- 1 7475 3075
- 1 0 0 1
-$EndComp
-Connection ~ 6650 3075
-$Comp
-L eSim_R R18
-U 1 1 5C9E431A
-P 7525 2375
-F 0 "R18" H 7575 2505 50 0000 C CNN
-F 1 "240" H 7575 2425 50 0000 C CNN
-F 2 "" H 7575 2355 30 0000 C CNN
-F 3 "" V 7575 2425 30 0000 C CNN
- 1 7525 2375
- 0 1 1 0
-$EndComp
-Connection ~ 7575 1800
-Wire Wire Line
- 7575 2575 7575 2875
-$Comp
-L eSim_R R19
-U 1 1 5C9E45DF
-P 7925 1850
-F 0 "R19" H 7975 1980 50 0000 C CNN
-F 1 "90" H 7975 1900 50 0000 C CNN
-F 2 "" H 7975 1830 30 0000 C CNN
-F 3 "" V 7975 1900 30 0000 C CNN
- 1 7925 1850
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7200 2000 8250 2000
-Wire Wire Line
- 8250 2000 8250 1800
-Wire Wire Line
- 8125 1800 8475 1800
-Wire Wire Line
- 7325 4300 7325 3325
-Wire Wire Line
- 7325 3325 6650 3325
-Wire Wire Line
- 6950 2975 7300 2975
-Wire Wire Line
- 7300 2975 7300 2750
-Wire Wire Line
- 7300 2750 7875 2750
-Wire Wire Line
- 7875 2750 7875 6250
-Connection ~ 7325 6250
-Wire Wire Line
- 7575 3275 7575 6250
-Connection ~ 7575 6250
-Connection ~ 7875 6250
-Connection ~ 8250 1800
-Connection ~ 7575 1300
-$Comp
-L PORT U1
-U 7 1 5C9EBDC2
-P 8700 1300
-F 0 "U1" H 8750 1400 30 0000 C CNN
-F 1 "PORT" H 8700 1300 30 0000 C CNN
-F 2 "" H 8700 1300 60 0000 C CNN
-F 3 "" H 8700 1300 60 0000 C CNN
- 7 8700 1300
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9EBE57
-P 8725 1800
-F 0 "U1" H 8775 1900 30 0000 C CNN
-F 1 "PORT" H 8725 1800 30 0000 C CNN
-F 2 "" H 8725 1800 60 0000 C CNN
-F 3 "" H 8725 1800 60 0000 C CNN
- 6 8725 1800
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9EC714
-P 8850 6250
-F 0 "U1" H 8900 6350 30 0000 C CNN
-F 1 "PORT" H 8850 6250 30 0000 C CNN
-F 2 "" H 8850 6250 60 0000 C CNN
-F 3 "" H 8850 6250 60 0000 C CNN
- 4 8850 6250
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9ED09C
-P 2125 3375
-F 0 "U1" H 2175 3475 30 0000 C CNN
-F 1 "PORT" H 2125 3375 30 0000 C CNN
-F 2 "" H 2125 3375 60 0000 C CNN
-F 3 "" H 2125 3375 60 0000 C CNN
- 2 2125 3375
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9ED12F
-P 2150 4425
-F 0 "U1" H 2200 4525 30 0000 C CNN
-F 1 "PORT" H 2150 4425 30 0000 C CNN
-F 2 "" H 2150 4425 60 0000 C CNN
-F 3 "" H 2150 4425 60 0000 C CNN
- 3 2150 4425
- 1 0 0 -1
-$EndComp
-Connection ~ 3400 4425
-Text GLabel 8425 1075 0 60 Input ~ 0
-v+
-Wire Wire Line
- 8425 1075 8450 1075
-Wire Wire Line
- 8450 1075 8450 1300
-Text GLabel 8475 1675 0 60 Input ~ 0
-Output
-Wire Wire Line
- 8475 1800 8475 1675
-Text GLabel 8600 6150 0 60 Input ~ 0
-V-
-Wire Wire Line
- 8600 6250 8600 6150
-Text GLabel 2375 4600 0 60 Input ~ 0
-Input+
-Wire Wire Line
- 2375 4600 2450 4600
-Wire Wire Line
- 2450 4600 2450 4425
-Connection ~ 2450 4425
-Text GLabel 2350 3525 0 60 Input ~ 0
-Input-
-Wire Wire Line
- 2350 3525 2375 3525
-Wire Wire Line
- 2375 3525 2375 3375
-Wire Wire Line
- 6025 1225 6025 1325
-Connection ~ 6025 1225
-Wire Wire Line
- 5700 1300 6375 1300
-Wire Wire Line
- 5600 1825 5600 1125
-$Comp
-L PORT U1
-U 1 1 5C9FE719
-P 4050 850
-F 0 "U1" H 4100 950 30 0000 C CNN
-F 1 "PORT" H 4050 850 30 0000 C CNN
-F 2 "" H 4050 850 60 0000 C CNN
-F 3 "" H 4050 850 60 0000 C CNN
- 1 4050 850
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9FF058
-P 5600 875
-F 0 "U1" H 5650 975 30 0000 C CNN
-F 1 "PORT" H 5600 875 30 0000 C CNN
-F 2 "" H 5600 875 60 0000 C CNN
-F 3 "" H 5600 875 60 0000 C CNN
- 8 5600 875
- 0 1 1 0
-$EndComp
-Text GLabel 5500 1125 0 60 Input ~ 0
-CompensationB
-Wire Wire Line
- 5600 1125 5500 1125
-Text GLabel 3875 1075 0 60 Input ~ 0
-CompensationA
-Wire Wire Line
- 3875 1075 3975 1075
-Wire Wire Line
- 3975 1075 3975 1150
-Wire Wire Line
- 3975 1150 4050 1150
-Connection ~ 4050 1150
-Wire Wire Line
- 5850 4175 5850 4375
-Wire Wire Line
- 5850 4375 6300 4375
-Connection ~ 6300 4375
-$Comp
-L eSim_PNP Q28
-U 1 1 5CA09126
-P 5075 1475
-F 0 "Q28" H 4975 1525 50 0000 R CNN
-F 1 "eSim_PNP" H 5025 1625 50 0000 R CNN
-F 2 "" H 5275 1575 29 0000 C CNN
-F 3 "" H 5075 1475 60 0000 C CNN
- 1 5075 1475
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q29
-U 1 1 5CA091C3
-P 5400 1475
-F 0 "Q29" H 5300 1525 50 0000 R CNN
-F 1 "eSim_PNP" H 5350 1625 50 0000 R CNN
-F 2 "" H 5600 1575 29 0000 C CNN
-F 3 "" H 5400 1475 60 0000 C CNN
- 1 5400 1475
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 5500 1275 5500 1225
-Connection ~ 5500 1225
-Wire Wire Line
- 4875 1475 4875 1675
-Wire Wire Line
- 4875 1675 4975 1675
-Wire Wire Line
- 5175 1675 5175 1850
-Wire Wire Line
- 5700 1675 5500 1675
-$Comp
-L eSim_NPN Q16
-U 1 1 5CA0B93F
-P 4925 5025
-F 0 "Q16" H 4825 5075 50 0000 R CNN
-F 1 "eSim_NPN" H 4875 5175 50 0000 R CNN
-F 2 "" H 5125 5125 29 0000 C CNN
-F 3 "" H 4925 5025 60 0000 C CNN
- 1 4925 5025
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 5200 1475 5200 1275
-Wire Wire Line
- 5200 1275 5175 1275
-Wire Wire Line
- 5175 1850 4975 1850
-Wire Wire Line
- 4975 1675 4975 3975
-Wire Wire Line
- 4825 3975 6100 3975
-Connection ~ 4975 1850
-Wire Wire Line
- 6100 3975 6100 3900
-Wire Wire Line
- 6100 3900 6300 3900
-Connection ~ 5550 3975
-Wire Wire Line
- 4825 3975 4825 4825
-Connection ~ 4975 3975
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LM108/LM108.sub b/src/SubcircuitLibrary/LM108/LM108.sub deleted file mode 100644 index b04676f7..00000000 --- a/src/SubcircuitLibrary/LM108/LM108.sub +++ /dev/null @@ -1,57 +0,0 @@ -* Subcircuit LM108
-.subckt LM108 compensationa input+ input- v- output v+ compensationb
-* c:\esim_1\esim\src\subcircuitlibrary\lm108\lm108.cir
-.include PNP.lib
-.include NJF.lib
-.include NPN.lib
-r2 v+ net-_q2-pad3_ 20k
-q2 net-_q2-pad1_ net-_q2-pad1_ net-_q2-pad3_ Q2N2907A
-q5 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad3_ Q2N2907A
-q3 net-_q2-pad1_ net-_q14-pad1_ net-_q1-pad1_ Q2N2222
-q7 compensationa net-_q14-pad1_ net-_q7-pad3_ Q2N2222
-q9 compensationa compensationa net-_q9-pad3_ Q2N2907A
-q11 net-_q11-pad1_ compensationa net-_q11-pad3_ Q2N2907A
-r3 v+ net-_q9-pad3_ 20k
-r7 v+ net-_q11-pad3_ 10k
-q1 net-_q1-pad1_ input- net-_q1-pad3_ Q2N2222
-q4 net-_q4-pad1_ input+ input- Q2N2222
-q6 net-_q4-pad1_ input- input+ Q2N2222
-r1 net-_q1-pad3_ net-_q10-pad1_ 2k
-r5 net-_q4-pad1_ net-_q12-pad3_ 50k
-q8 net-_q7-pad3_ input+ net-_q8-pad3_ Q2N2222
-r8 v+ net-_q15-pad3_ 10k
-q15 net-_q14-pad1_ net-_j1-pad3_ net-_q15-pad3_ Q2N2907A
-r12 compensationb net-_q11-pad1_ 5.6k
-q13 net-_q13-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q17 net-_q11-pad1_ net-_q13-pad1_ net-_q13-pad3_ Q2N2222
-q14 net-_q14-pad1_ net-_q14-pad1_ net-_q12-pad3_ Q2N2222
-r4 net-_q8-pad3_ net-_q10-pad1_ 2k
-q12 v- net-_q10-pad1_ net-_q12-pad3_ Q2N2907A
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q18 net-_j1-pad3_ net-_j1-pad1_ net-_q18-pad3_ Q2N2222
-j1 net-_j1-pad1_ v- net-_j1-pad3_ J2N3819
-r13 net-_j1-pad1_ net-_q16-pad2_ 940
-r14 net-_q18-pad3_ net-_q24-pad2_ 20k
-q24 net-_q13-pad3_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222
-r6 net-_q10-pad3_ net-_r10-pad1_ 6.4k
-r9 net-_q10-pad2_ net-_r10-pad1_ 60k
-r11 net-_q18-pad3_ net-_q19-pad3_ 20k
-r10 net-_r10-pad1_ net-_q19-pad3_ 500
-r15 net-_q19-pad3_ v- 1k
-q19 net-_q16-pad2_ net-_q18-pad3_ net-_q19-pad3_ Q2N2222
-r17 net-_q24-pad3_ v- 820
-q21 v+ net-_j1-pad3_ net-_q20-pad1_ Q2N2222
-q20 net-_q20-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-r16 net-_j1-pad3_ net-_q23-pad1_ 2k
-q23 net-_q23-pad1_ net-_j1-pad3_ net-_q22-pad3_ Q2N2222
-q26 v+ net-_q23-pad1_ net-_q25-pad2_ Q2N2222
-q25 net-_q23-pad1_ net-_q25-pad2_ output Q2N2222
-q22 v- net-_q13-pad3_ net-_q22-pad3_ Q2N2907A
-q27 v- net-_q13-pad3_ net-_q27-pad3_ Q2N2907A
-r18 net-_q25-pad2_ net-_q27-pad3_ 240
-r19 net-_q25-pad2_ output 90
-q29 net-_j1-pad3_ net-_j1-pad3_ v+ Q2N2907A
-q16 net-_j1-pad3_ net-_q16-pad2_ net-_q10-pad2_ Q2N2222
-* Control Statements
-
-.ends LM108
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml b/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml deleted file mode 100644 index c3161654..00000000 --- a/src/SubcircuitLibrary/LM108/LM108_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><j1><field>C:/esim_1/eSim/src/deviceModelLibrary/JFET/NJF.lib</field></j1><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q20><q21><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q21><q22><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q22><q23><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q23><q24><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q24><q25><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q25><q26><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q26><q27><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q27><q29><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q29><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q15><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q12><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM108/NJF.lib b/src/SubcircuitLibrary/LM108/NJF.lib deleted file mode 100644 index dbb2cbae..00000000 --- a/src/SubcircuitLibrary/LM108/NJF.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 -+ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u -+ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 -+ Af=1) diff --git a/src/SubcircuitLibrary/LM108/NPN.lib b/src/SubcircuitLibrary/LM108/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/LM108/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM108/PNP.lib b/src/SubcircuitLibrary/LM108/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/LM108/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LM3046/LM3046-cache.lib b/src/SubcircuitLibrary/LM3046/LM3046-cache.lib deleted file mode 100644 index 27505ab7..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046-cache.lib +++ /dev/null @@ -1,77 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 75 50 H I C CNN -F1 "PWR_FLAG" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -X pwr 1 0 0 0 U 50 50 0 0 w -P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N -ENDDRAW -ENDDEF -# -# eSim_NPN -# -DEF eSim_NPN Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -ALIAS BC547 Q2N2222 -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir b/src/SubcircuitLibrary/LM3046/LM3046.cir deleted file mode 100644 index f9716c63..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046.cir +++ /dev/null @@ -1,16 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM3046/LM3046.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 22 11:57:18 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN -Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN -Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_NPN -Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN -Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN -U1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ Net-_Q5-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ Net-_Q4-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ Net-_Q2-Pad1_ PORT - -.end diff --git a/src/SubcircuitLibrary/LM3046/LM3046.cir.out b/src/SubcircuitLibrary/LM3046/LM3046.cir.out deleted file mode 100644 index 801e68d2..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir - -.include NPN.lib -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 -q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 -* u1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ port -.tran 10e-03 100e-03 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/LM3046/LM3046.pro b/src/SubcircuitLibrary/LM3046/LM3046.pro deleted file mode 100644 index 38ae7a8e..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046.pro +++ /dev/null @@ -1,73 +0,0 @@ -update=Fri Jun 21 16:28:59 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../eSim-1.1.2/kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=microcontrollers -LibName13=dsp -LibName14=microchip -LibName15=analog_switches -LibName16=motorola -LibName17=texas -LibName18=intel -LibName19=audio -LibName20=interface -LibName21=digital-audio -LibName22=philips -LibName23=display -LibName24=cypress -LibName25=siliconi -LibName26=opto -LibName27=atmel -LibName28=contrib -LibName29=valves -LibName30=eSim_Analog -LibName31=eSim_Devices -LibName32=eSim_Digital -LibName33=eSim_Hybrid -LibName34=eSim_Plot -LibName35=eSim_Power -LibName36=eSim_PSpice -LibName37=eSim_Sources -LibName38=eSim_Subckt -LibName39=eSim_User -LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sch b/src/SubcircuitLibrary/LM3046/LM3046.sch deleted file mode 100644 index 3ba1a18a..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046.sch +++ /dev/null @@ -1,326 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Miscellaneous -LIBS:LM3046-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L eSim_NPN Q1 -U 1 1 5C98EC0E -P 4150 3500 -F 0 "Q1" H 4050 3550 50 0000 R CNN -F 1 "eSim_NPN" H 4100 3650 50 0000 R CNN -F 2 "" H 4350 3600 29 0000 C CNN -F 3 "" H 4150 3500 60 0000 C CNN - 1 4150 3500 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q2 -U 1 1 5C98EC83 -P 4200 2400 -F 0 "Q2" H 4100 2450 50 0000 R CNN -F 1 "eSim_NPN" H 4150 2550 50 0000 R CNN -F 2 "" H 4400 2500 29 0000 C CNN -F 3 "" H 4200 2400 60 0000 C CNN - 1 4200 2400 - -1 0 0 1 -$EndComp -$Comp -L eSim_NPN Q4 -U 1 1 5C98ECC0 -P 5400 2400 -F 0 "Q4" H 5300 2450 50 0000 R CNN -F 1 "eSim_NPN" H 5350 2550 50 0000 R CNN -F 2 "" H 5600 2500 29 0000 C CNN -F 3 "" H 5400 2400 60 0000 C CNN - 1 5400 2400 - -1 0 0 1 -$EndComp -$Comp -L eSim_NPN Q5 -U 1 1 5C98ED6B -P 6350 3450 -F 0 "Q5" H 6250 3500 50 0000 R CNN -F 1 "eSim_NPN" H 6300 3600 50 0000 R CNN -F 2 "" H 6550 3550 29 0000 C CNN -F 3 "" H 6350 3450 60 0000 C CNN - 1 6350 3450 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q3 -U 1 1 5C98EDA0 -P 5150 3500 -F 0 "Q3" H 5050 3550 50 0000 R CNN -F 1 "eSim_NPN" H 5100 3650 50 0000 R CNN -F 2 "" H 5350 3600 29 0000 C CNN -F 3 "" H 5150 3500 60 0000 C CNN - 1 5150 3500 - -1 0 0 -1 -$EndComp -Wire Wire Line - 4250 3700 5050 3700 -Wire Wire Line - 4650 3700 4650 4250 -Connection ~ 4650 3700 -Wire Wire Line - 5350 3500 5350 4250 -Wire Wire Line - 5050 3300 5700 3300 -Wire Wire Line - 5700 3300 5700 4250 -Wire Wire Line - 6150 3450 6000 3450 -Wire Wire Line - 6000 3450 6000 4250 -Wire Wire Line - 6450 3250 6450 1700 -Wire Wire Line - 6450 3650 6450 4250 -Wire Wire Line - 3950 3500 3950 4250 -Wire Wire Line - 4250 3300 4250 3200 -Wire Wire Line - 4250 3200 3500 3200 -Wire Wire Line - 3500 3200 3500 4250 -Wire Wire Line - 4100 2200 4100 1700 -Wire Wire Line - 4100 2600 3500 2600 -Wire Wire Line - 3500 2600 3500 1700 -Wire Wire Line - 4400 2400 4400 1700 -Wire Wire Line - 5300 2200 5300 1700 -Wire Wire Line - 5300 2600 4800 2600 -Wire Wire Line - 4800 2600 4800 1700 -Wire Wire Line - 5600 2400 5900 2400 -Wire Wire Line - 5900 2400 5900 1700 -$Comp -L PORT U1 -U 1 1 5C98EEE0 -P 3500 4500 -F 0 "U1" H 3550 4600 30 0000 C CNN -F 1 "PORT" H 3500 4500 30 0000 C CNN -F 2 "" H 3500 4500 60 0000 C CNN -F 3 "" H 3500 4500 60 0000 C CNN - 1 3500 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 2 1 5C98EF2D -P 3950 4500 -F 0 "U1" H 4000 4600 30 0000 C CNN -F 1 "PORT" H 3950 4500 30 0000 C CNN -F 2 "" H 3950 4500 60 0000 C CNN -F 3 "" H 3950 4500 60 0000 C CNN - 2 3950 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 3 1 5C98EF86 -P 4650 4500 -F 0 "U1" H 4700 4600 30 0000 C CNN -F 1 "PORT" H 4650 4500 30 0000 C CNN -F 2 "" H 4650 4500 60 0000 C CNN -F 3 "" H 4650 4500 60 0000 C CNN - 3 4650 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 4 1 5C98EFBD -P 5350 4500 -F 0 "U1" H 5400 4600 30 0000 C CNN -F 1 "PORT" H 5350 4500 30 0000 C CNN -F 2 "" H 5350 4500 60 0000 C CNN -F 3 "" H 5350 4500 60 0000 C CNN - 4 5350 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 5 1 5C98EFF0 -P 5700 4500 -F 0 "U1" H 5750 4600 30 0000 C CNN -F 1 "PORT" H 5700 4500 30 0000 C CNN -F 2 "" H 5700 4500 60 0000 C CNN -F 3 "" H 5700 4500 60 0000 C CNN - 5 5700 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 6 1 5C98F02D -P 6000 4500 -F 0 "U1" H 6050 4600 30 0000 C CNN -F 1 "PORT" H 6000 4500 30 0000 C CNN -F 2 "" H 6000 4500 60 0000 C CNN -F 3 "" H 6000 4500 60 0000 C CNN - 6 6000 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 7 1 5C98F05E -P 6450 4500 -F 0 "U1" H 6500 4600 30 0000 C CNN -F 1 "PORT" H 6450 4500 30 0000 C CNN -F 2 "" H 6450 4500 60 0000 C CNN -F 3 "" H 6450 4500 60 0000 C CNN - 7 6450 4500 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 8 1 5C98F0C3 -P 6450 1450 -F 0 "U1" H 6500 1550 30 0000 C CNN -F 1 "PORT" H 6450 1450 30 0000 C CNN -F 2 "" H 6450 1450 60 0000 C CNN -F 3 "" H 6450 1450 60 0000 C CNN - 8 6450 1450 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 5C9CD7BF -P 6050 4250 -F 0 "#FLG01" H 6050 4345 50 0001 C CNN -F 1 "PWR_FLAG" H 6050 4430 50 0000 C CNN -F 2 "" H 6050 4250 50 0000 C CNN -F 3 "" H 6050 4250 50 0000 C CNN - 1 6050 4250 - 0 1 1 0 -$EndComp -Wire Wire Line - 6000 4250 6050 4250 -Wire Wire Line - 5600 2450 5600 2400 -$Comp -L PORT U1 -U 9 1 5D0CBFBB -P 5900 1450 -F 0 "U1" H 5950 1550 30 0000 C CNN -F 1 "PORT" H 5900 1450 30 0000 C CNN -F 2 "" H 5900 1450 60 0000 C CNN -F 3 "" H 5900 1450 60 0000 C CNN - 9 5900 1450 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 10 1 5D0CC62F -P 5300 1450 -F 0 "U1" H 5350 1550 30 0000 C CNN -F 1 "PORT" H 5300 1450 30 0000 C CNN -F 2 "" H 5300 1450 60 0000 C CNN -F 3 "" H 5300 1450 60 0000 C CNN - 10 5300 1450 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 11 1 5D0CC70E -P 4800 1450 -F 0 "U1" H 4850 1550 30 0000 C CNN -F 1 "PORT" H 4800 1450 30 0000 C CNN -F 2 "" H 4800 1450 60 0000 C CNN -F 3 "" H 4800 1450 60 0000 C CNN - 11 4800 1450 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 12 1 5D0CC84E -P 4400 1450 -F 0 "U1" H 4450 1550 30 0000 C CNN -F 1 "PORT" H 4400 1450 30 0000 C CNN -F 2 "" H 4400 1450 60 0000 C CNN -F 3 "" H 4400 1450 60 0000 C CNN - 12 4400 1450 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 14 1 5D0CC96F -P 3500 1450 -F 0 "U1" H 3550 1550 30 0000 C CNN -F 1 "PORT" H 3500 1450 30 0000 C CNN -F 2 "" H 3500 1450 60 0000 C CNN -F 3 "" H 3500 1450 60 0000 C CNN - 14 3500 1450 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 13 1 5D0CC9BD -P 4100 1450 -F 0 "U1" H 4150 1550 30 0000 C CNN -F 1 "PORT" H 4100 1450 30 0000 C CNN -F 2 "" H 4100 1450 60 0000 C CNN -F 3 "" H 4100 1450 60 0000 C CNN - 13 4100 1450 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM3046/LM3046.sub b/src/SubcircuitLibrary/LM3046/LM3046.sub deleted file mode 100644 index 251364bb..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit LM3046 -.subckt LM3046 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad3_ net-_q5-pad1_ net-_q4-pad2_ net-_q4-pad3_ net-_q4-pad1_ net-_q2-pad2_ net-_q2-pad3_ net-_q2-pad1_ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm3046/lm3046.cir -.include NPN.lib -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q4 net-_q4-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2222 -q5 net-_q5-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222 -* Control Statements - -.ends LM3046
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM3046/LM3046.xml b/src/SubcircuitLibrary/LM3046/LM3046.xml deleted file mode 100644 index 94884e43..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046.xml +++ /dev/null @@ -1,177 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<export version="D"> - <design> - <source>C:/esim_1/eSim/src/SubcircuitLibrary/LM3046/LM3046.sch</source> - <date>03/27/19 23:15:04</date> - <tool>Eeschema 4.0.2-stable</tool> - <sheet number="1" name="/" tstamps="/"> - <title_block> - <title/> - <company/> - <rev/> - <date/> - <source>LM3046.sch</source> - <comment number="1" value=""/> - <comment number="2" value=""/> - <comment number="3" value=""/> - <comment number="4" value=""/> - </title_block> - </sheet> - </design> - <components> - <comp ref="Q1"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98EC0E</tstamp> - </comp> - <comp ref="Q2"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98EC83</tstamp> - </comp> - <comp ref="Q4"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98ECC0</tstamp> - </comp> - <comp ref="Q5"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98ED6B</tstamp> - </comp> - <comp ref="Q3"> - <value>eSim_NPN</value> - <libsource lib="eSim_Devices" part="eSim_NPN"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98EDA0</tstamp> - </comp> - <comp ref="U1"> - <value>PORT</value> - <libsource lib="eSim_Miscellaneous" part="PORT"/> - <sheetpath names="/" tstamps="/"/> - <tstamp>5C98EEE0</tstamp> - </comp> - </components> - <libparts> - <libpart lib="eSim_Miscellaneous" part="PORT"> - <fields> - <field name="Reference">U</field> - <field name="Value">PORT</field> - </fields> - <pins> - <pin num="1" name="~" type="BiDi"/> - <pin num="2" name="~" type="BiDi"/> - <pin num="3" name="~" type="BiDi"/> - <pin num="4" name="~" type="BiDi"/> - <pin num="5" name="~" type="BiDi"/> - <pin num="6" name="~" type="BiDi"/> - <pin num="7" name="~" type="BiDi"/> - <pin num="8" name="~" type="BiDi"/> - <pin num="9" name="~" type="BiDi"/> - <pin num="10" name="~" type="BiDi"/> - <pin num="11" name="~" type="BiDi"/> - <pin num="12" name="~" type="BiDi"/> - <pin num="13" name="~" type="BiDi"/> - <pin num="14" name="~" type="BiDi"/> - <pin num="15" name="~" type="BiDi"/> - <pin num="16" name="~" type="BiDi"/> - <pin num="17" name="~" type="BiDi"/> - <pin num="18" name="~" type="BiDi"/> - <pin num="19" name="~" type="BiDi"/> - <pin num="20" name="~" type="BiDi"/> - <pin num="21" name="~" type="BiDi"/> - <pin num="22" name="~" type="BiDi"/> - <pin num="23" name="~" type="BiDi"/> - <pin num="24" name="~" type="BiDi"/> - <pin num="25" name="~" type="BiDi"/> - <pin num="26" name="~" type="BiDi"/> - </pins> - </libpart> - <libpart lib="eSim_Devices" part="eSim_NPN"> - <aliases> - <alias>BC547</alias> - <alias>Q2N2222</alias> - </aliases> - <fields> - <field name="Reference">Q</field> - <field name="Value">eSim_NPN</field> - </fields> - <pins> - <pin num="1" name="C" type="openCol"/> - <pin num="2" name="B" type="input"/> - <pin num="3" name="E" type="openEm"/> - </pins> - </libpart> - </libparts> - <libraries> - <library logical="eSim_Miscellaneous"> - <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Miscellaneous.lib</uri> - </library> - <library logical="eSim_Devices"> - <uri>C:\Program Files (x86)\KiCad\share\library\eSim_Devices.lib</uri> - </library> - </libraries> - <nets> - <net code="1" name="Net-(Q1-Pad1)"> - <node ref="Q1" pin="1"/> - <node ref="U1" pin="1"/> - </net> - <net code="2" name="Net-(Q2-Pad3)"> - <node ref="Q2" pin="3"/> - <node ref="U1" pin="13"/> - </net> - <net code="3" name="Net-(Q2-Pad1)"> - <node ref="Q2" pin="1"/> - <node ref="U1" pin="14"/> - </net> - <net code="4" name="Net-(Q2-Pad2)"> - <node ref="Q2" pin="2"/> - <node ref="U1" pin="12"/> - </net> - <net code="5" name="Net-(Q4-Pad3)"> - <node ref="Q4" pin="3"/> - <node ref="U1" pin="10"/> - </net> - <net code="6" name="Net-(Q4-Pad1)"> - <node ref="Q4" pin="1"/> - <node ref="U1" pin="11"/> - </net> - <net code="7" name="Net-(Q4-Pad2)"> - <node ref="Q4" pin="2"/> - <node ref="U1" pin="9"/> - </net> - <net code="8" name="Net-(Q1-Pad3)"> - <node ref="Q3" pin="3"/> - <node ref="Q1" pin="3"/> - <node ref="U1" pin="3"/> - </net> - <net code="9" name="Net-(Q3-Pad2)"> - <node ref="Q3" pin="2"/> - <node ref="U1" pin="4"/> - </net> - <net code="10" name="Net-(Q1-Pad2)"> - <node ref="Q1" pin="2"/> - <node ref="U1" pin="2"/> - </net> - <net code="11" name="Net-(Q5-Pad1)"> - <node ref="Q5" pin="1"/> - <node ref="U1" pin="8"/> - </net> - <net code="12" name="Net-(Q5-Pad2)"> - <node ref="U1" pin="6"/> - <node ref="Q5" pin="2"/> - </net> - <net code="13" name="Net-(Q5-Pad3)"> - <node ref="U1" pin="7"/> - <node ref="Q5" pin="3"/> - </net> - <net code="14" name="Net-(Q3-Pad1)"> - <node ref="U1" pin="5"/> - <node ref="Q3" pin="1"/> - </net> - </nets> -</export> diff --git a/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml b/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml deleted file mode 100644 index 0b34a8e5..00000000 --- a/src/SubcircuitLibrary/LM3046/LM3046_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM3046/NPN.lib b/src/SubcircuitLibrary/LM3046/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/LM3046/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM3046/analysis b/src/SubcircuitLibrary/LM3046/analysis deleted file mode 100644 index d5e13546..00000000 --- a/src/SubcircuitLibrary/LM3046/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM565/LM565-cache.lib b/src/SubcircuitLibrary/LM565/LM565-cache.lib deleted file mode 100644 index dd2449b9..00000000 --- a/src/SubcircuitLibrary/LM565/LM565-cache.lib +++ /dev/null @@ -1,114 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-X ~ 9 250 0 100 L 30 30 9 1 I
-X ~ 10 250 0 100 L 30 30 10 1 I
-X ~ 11 250 0 100 L 30 30 11 1 I
-X ~ 12 250 0 100 L 30 30 12 1 I
-X ~ 13 250 0 100 L 30 30 13 1 I
-X ~ 14 250 0 100 L 30 30 14 1 I
-X ~ 15 250 0 100 L 30 30 15 1 I
-X ~ 16 250 0 100 L 30 30 16 1 I
-X ~ 17 250 0 100 L 30 30 17 1 I
-X ~ 18 250 0 100 L 30 30 18 1 I
-X ~ 19 250 0 100 L 30 30 19 1 I
-X ~ 20 250 0 100 L 30 30 20 1 I
-X ~ 21 250 0 100 L 30 30 21 1 I
-X ~ 22 250 0 100 L 30 30 22 1 I
-X ~ 23 250 0 100 L 30 30 23 1 I
-X ~ 24 250 0 100 L 30 30 24 1 I
-X ~ 25 250 0 100 L 30 30 25 1 I
-X ~ 26 250 0 100 L 30 30 26 1 I
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
-F3 "" 0 0 50 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LM565/LM565.cir b/src/SubcircuitLibrary/LM565/LM565.cir deleted file mode 100644 index c1f63f94..00000000 --- a/src/SubcircuitLibrary/LM565/LM565.cir +++ /dev/null @@ -1,78 +0,0 @@ -* C:\esim_1\eSim\src\SubcircuitLibrary\LM565\LM565.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 18:47:10
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-R1 +Vcc Net-_Q1-Pad1_ 7.2k
-R3 +Vcc Net-_Q14-Pad2_ 7.2k
-Q4 Net-_Q14-Pad2_ Net-_Q14-Pad2_ Net-_Q1-Pad1_ eSim_NPN
-Q5 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q14-Pad2_ eSim_NPN
-Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ +Vcc eSim_NPN
-R4 +Vcc Net-_Q3-Pad2_ 5.7k
-R6 +Vcc Reference_output 1.75k
-R7 Reference_output Net-_Q1-Pad2_ 3.8k
-Q12 +Vcc Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_NPN
-Q14 Vco_control_voltage Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN
-R12 +Vcc Vco_control_voltage 3.6K
-Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
-Q3 Net-_Q14-Pad2_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN
-Q7 Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN
-Q9 Net-_Q14-Pad2_ Net-_Q1-Pad2_ Net-_Q7-Pad3_ eSim_NPN
-R5 Net-_Q3-Pad2_ -Vcc 13k
-Q2 Net-_Q1-Pad3_ Input Net-_Q2-Pad3_ eSim_NPN
-Q8 Net-_Q7-Pad3_ Input Net-_Q2-Pad3_ eSim_NPN
-Q6 Net-_Q2-Pad3_ Net-_Q11-Pad1_ Net-_Q6-Pad3_ eSim_NPN
-R2 Net-_Q6-Pad3_ -Vcc 200
-R8 Net-_Q1-Pad2_ Net-_Q11-Pad1_ 8.1K
-R10 Net-_Q12-Pad3_ Net-_Q13-Pad1_ 1K
-R13 Net-_Q14-Pad3_ Net-_Q13-Pad1_ 1K
-Q13 Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_Q13-Pad3_ eSim_NPN
-Q11 Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_NPN
-R9 Net-_Q11-Pad3_ -Vcc 200
-R11 Net-_Q13-Pad3_ -Vcc 205
-Q16 Timming_resistor Vco_control_voltage Net-_Q15-Pad2_ eSim_NPN
-Q18 Net-_Q15-Pad2_ Net-_Q18-Pad2_ Net-_Q17-Pad1_ eSim_NPN
-Q20 Net-_Q18-Pad2_ Net-_Q18-Pad2_ Net-_Q17-Pad1_ eSim_NPN
-Q17 Net-_Q17-Pad1_ Net-_Q17-Pad1_ Net-_Q17-Pad3_ eSim_NPN
-Q21 Timing_capacitor Timing_capacitor Net-_Q17-Pad1_ eSim_PNP
-Q22 Timing_capacitor Net-_Q17-Pad3_ Net-_Q19-Pad2_ eSim_NPN
-Q19 Net-_Q17-Pad3_ Net-_Q19-Pad2_ Net-_Q19-Pad3_ eSim_NPN
-Q23 Net-_Q19-Pad2_ Net-_Q19-Pad2_ Net-_Q23-Pad3_ eSim_NPN
-R14 Net-_Q19-Pad3_ Net-_Q24-Pad1_ 530
-R15 Net-_Q23-Pad3_ Net-_Q24-Pad1_ 530
-Q25 +Vcc Timing_capacitor Net-_Q25-Pad3_ eSim_NPN
-R17 +Vcc Net-_Q28-Pad1_ 6.5K
-Q28 Net-_Q28-Pad1_ Net-_Q28-Pad1_ Net-_Q25-Pad3_ eSim_PNP
-Q27 ? Net-_Q25-Pad3_ Net-_Q27-Pad3_ eSim_NPN
-Q30 Net-_Q28-Pad1_ Net-_Q27-Pad3_ Net-_Q30-Pad3_ eSim_NPN
-Q31 ? Net-_Q28-Pad1_ Net-_Q31-Pad3_ eSim_NPN
-Q32 Net-_Q32-Pad1_ Net-_Q32-Pad1_ Net-_Q28-Pad1_ eSim_PNP
-R19 +Vcc Net-_Q32-Pad1_ 4.7k
-Q33 Net-_Q32-Pad1_ Net-_Q31-Pad3_ Net-_Q30-Pad3_ eSim_NPN
-R18 Net-_Q31-Pad3_ Net-_Q30-Pad3_ 8.4K
-Q35 +Vcc Net-_Q32-Pad1_ Vco_output eSim_NPN
-R20 Net-_Q30-Pad3_ -Vcc 2.6K
-R22 Vco_output -Vcc 4.8K
-Q24 Net-_Q24-Pad1_ Net-_Q24-Pad2_ -Vcc eSim_NPN
-Q26 Net-_Q24-Pad1_ Net-_Q24-Pad1_ Net-_Q26-Pad3_ eSim_PNP
-R16 Net-_Q24-Pad2_ -Vcc 7K
-Q29 Net-_Q26-Pad3_ Net-_Q26-Pad3_ Net-_Q24-Pad2_ eSim_NPN
-Q34 Net-_Q25-Pad3_ Net-_Q11-Pad1_ Net-_Q34-Pad3_ eSim_NPN
-R21 Net-_Q34-Pad3_ -Vcc 2.4K
-Q36 -Vcc Vco_output Net-_Q36-Pad3_ eSim_PNP
-Q38 Net-_Q37-Pad2_ Net-_Q38-Pad2_ Net-_Q36-Pad3_ eSim_PNP
-R23 +Vcc Net-_Q36-Pad3_ 16K
-R24 Net-_Q37-Pad2_ Net-_Q26-Pad3_ 5.8k
-Q37 Net-_Q36-Pad3_ Net-_Q37-Pad2_ Net-_Q26-Pad3_ eSim_NPN
-Q40 Net-_Q38-Pad2_ Net-_Q11-Pad1_ Net-_Q40-Pad3_ eSim_NPN
-R26 Net-_Q40-Pad3_ -Vcc 200
-R25 +Vcc Net-_Q38-Pad2_ 4.3k
-Q39 ? Net-_Q38-Pad2_ +Vcc eSim_NPN
-U1 -Vcc Input Input Vco_output +Vcc Reference_output Vco_control_voltage Timming_resistor Timing_capacitor +Vcc PORT
-Q15 ? Net-_Q15-Pad2_ Vco_control_voltage eSim_NPN
-Q41 Net-_Q18-Pad2_ Net-_Q15-Pad2_ Timming_resistor eSim_PNP
-
-.end
diff --git a/src/SubcircuitLibrary/LM565/LM565.cir.out b/src/SubcircuitLibrary/LM565/LM565.cir.out deleted file mode 100644 index e39ed5f4..00000000 --- a/src/SubcircuitLibrary/LM565/LM565.cir.out +++ /dev/null @@ -1,81 +0,0 @@ -* c:\esim_1\esim\src\subcircuitlibrary\lm565\lm565.cir
-
-.include PNP.lib
-.include NPN.lib
-r1 +vcc net-_q1-pad1_ 7.2k
-r3 +vcc net-_q14-pad2_ 7.2k
-q4 net-_q14-pad2_ net-_q14-pad2_ net-_q1-pad1_ Q2N2222
-q5 net-_q1-pad1_ net-_q1-pad1_ net-_q14-pad2_ Q2N2222
-q10 net-_q10-pad1_ net-_q10-pad1_ +vcc Q2N2222
-r4 +vcc net-_q3-pad2_ 5.7k
-r6 +vcc reference_output 1.75k
-r7 reference_output net-_q1-pad2_ 3.8k
-q12 +vcc net-_q1-pad1_ net-_q12-pad3_ Q2N2222
-q14 vco_control_voltage net-_q14-pad2_ net-_q14-pad3_ Q2N2222
-r12 +vcc vco_control_voltage 3.6k
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q3 net-_q14-pad2_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
-q7 net-_q1-pad1_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q9 net-_q14-pad2_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222
-r5 net-_q3-pad2_ -vcc 13k
-q2 net-_q1-pad3_ input net-_q2-pad3_ Q2N2222
-q8 net-_q7-pad3_ input net-_q2-pad3_ Q2N2222
-q6 net-_q2-pad3_ net-_q11-pad1_ net-_q6-pad3_ Q2N2222
-r2 net-_q6-pad3_ -vcc 200
-r8 net-_q1-pad2_ net-_q11-pad1_ 8.1k
-r10 net-_q12-pad3_ net-_q13-pad1_ 1k
-r13 net-_q14-pad3_ net-_q13-pad1_ 1k
-q13 net-_q13-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222
-r9 net-_q11-pad3_ -vcc 200
-r11 net-_q13-pad3_ -vcc 205
-q16 timming_resistor vco_control_voltage net-_q15-pad2_ Q2N2222
-q18 net-_q15-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q20 net-_q18-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q17 net-_q17-pad1_ net-_q17-pad1_ net-_q17-pad3_ Q2N2222
-q21 timing_capacitor timing_capacitor net-_q17-pad1_ Q2N2907A
-q22 timing_capacitor net-_q17-pad3_ net-_q19-pad2_ Q2N2222
-q19 net-_q17-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222
-q23 net-_q19-pad2_ net-_q19-pad2_ net-_q23-pad3_ Q2N2222
-r14 net-_q19-pad3_ net-_q24-pad1_ 530
-r15 net-_q23-pad3_ net-_q24-pad1_ 530
-q25 +vcc timing_capacitor net-_q25-pad3_ Q2N2222
-r17 +vcc net-_q28-pad1_ 6.5k
-q28 net-_q28-pad1_ net-_q28-pad1_ net-_q25-pad3_ Q2N2907A
-q27 ? net-_q25-pad3_ net-_q27-pad3_ Q2N2222
-q30 net-_q28-pad1_ net-_q27-pad3_ net-_q30-pad3_ Q2N2222
-q31 ? net-_q28-pad1_ net-_q31-pad3_ Q2N2222
-q32 net-_q32-pad1_ net-_q32-pad1_ net-_q28-pad1_ Q2N2907A
-r19 +vcc net-_q32-pad1_ 4.7k
-q33 net-_q32-pad1_ net-_q31-pad3_ net-_q30-pad3_ Q2N2222
-r18 net-_q31-pad3_ net-_q30-pad3_ 8.4k
-q35 +vcc net-_q32-pad1_ vco_output Q2N2222
-r20 net-_q30-pad3_ -vcc 2.6k
-r22 vco_output -vcc 4.8k
-q24 net-_q24-pad1_ net-_q24-pad2_ -vcc Q2N2222
-q26 net-_q24-pad1_ net-_q24-pad1_ net-_q26-pad3_ Q2N2907A
-r16 net-_q24-pad2_ -vcc 7k
-q29 net-_q26-pad3_ net-_q26-pad3_ net-_q24-pad2_ Q2N2222
-q34 net-_q25-pad3_ net-_q11-pad1_ net-_q34-pad3_ Q2N2222
-r21 net-_q34-pad3_ -vcc 2.4k
-q36 -vcc vco_output net-_q36-pad3_ Q2N2907A
-q38 net-_q37-pad2_ net-_q38-pad2_ net-_q36-pad3_ Q2N2907A
-r23 +vcc net-_q36-pad3_ 16k
-r24 net-_q37-pad2_ net-_q26-pad3_ 5.8k
-q37 net-_q36-pad3_ net-_q37-pad2_ net-_q26-pad3_ Q2N2222
-q40 net-_q38-pad2_ net-_q11-pad1_ net-_q40-pad3_ Q2N2222
-r26 net-_q40-pad3_ -vcc 200
-r25 +vcc net-_q38-pad2_ 4.3k
-q39 ? net-_q38-pad2_ +vcc Q2N2222
-* u1 -vcc input input vco_output +vcc reference_output vco_control_voltage timming_resistor timing_capacitor +vcc port
-q15 ? net-_q15-pad2_ vco_control_voltage Q2N2222
-q41 net-_q18-pad2_ net-_q15-pad2_ timming_resistor Q2N2907A
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LM565/LM565.pro b/src/SubcircuitLibrary/LM565/LM565.pro deleted file mode 100644 index 94072b3e..00000000 --- a/src/SubcircuitLibrary/LM565/LM565.pro +++ /dev/null @@ -1,83 +0,0 @@ -update=03/31/19 19:39:59
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../../../Program Files (x86)/KiCad/share/library
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_PSpice
-LibName38=eSim_Sources
-LibName39=eSim_Subckt
-LibName40=eSim_User
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
-LabSize=60
diff --git a/src/SubcircuitLibrary/LM565/LM565.sch b/src/SubcircuitLibrary/LM565/LM565.sch deleted file mode 100644 index 9f5ad21c..00000000 --- a/src/SubcircuitLibrary/LM565/LM565.sch +++ /dev/null @@ -1,1365 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:LM565-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_R R1
-U 1 1 5C9D9F95
-P 850 975
-F 0 "R1" H 900 1105 50 0000 C CNN
-F 1 "7.2k" H 900 1025 50 0000 C CNN
-F 2 "" H 900 955 30 0000 C CNN
-F 3 "" V 900 1025 30 0000 C CNN
- 1 850 975
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R3
-U 1 1 5C9D9FE0
-P 1550 975
-F 0 "R3" H 1600 1105 50 0000 C CNN
-F 1 "7.2k" H 1600 1025 50 0000 C CNN
-F 2 "" H 1600 955 30 0000 C CNN
-F 3 "" V 1600 1025 30 0000 C CNN
- 1 1550 975
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q4
-U 1 1 5C9DA013
-P 1250 1500
-F 0 "Q4" H 1150 1550 50 0000 R CNN
-F 1 "eSim_NPN" H 1200 1650 50 0000 R CNN
-F 2 "" H 1450 1600 29 0000 C CNN
-F 3 "" H 1250 1500 60 0000 C CNN
- 1 1250 1500
- 0 1 -1 0
-$EndComp
-$Comp
-L eSim_NPN Q5
-U 1 1 5C9DA091
-P 1250 2200
-F 0 "Q5" H 1150 2250 50 0000 R CNN
-F 1 "eSim_NPN" H 1200 2350 50 0000 R CNN
-F 2 "" H 1450 2300 29 0000 C CNN
-F 3 "" H 1250 2200 60 0000 C CNN
- 1 1250 2200
- 0 -1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q10
-U 1 1 5C9DA0EA
-P 2125 1075
-F 0 "Q10" H 2025 1125 50 0000 R CNN
-F 1 "eSim_NPN" H 2075 1225 50 0000 R CNN
-F 2 "" H 2325 1175 29 0000 C CNN
-F 3 "" H 2125 1075 60 0000 C CNN
- 1 2125 1075
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_R R4
-U 1 1 5C9DA12E
-P 2425 975
-F 0 "R4" H 2475 1105 50 0000 C CNN
-F 1 "5.7k" H 2475 1025 50 0000 C CNN
-F 2 "" H 2475 955 30 0000 C CNN
-F 3 "" V 2475 1025 30 0000 C CNN
- 1 2425 975
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R6
-U 1 1 5C9DA17B
-P 2925 975
-F 0 "R6" H 2975 1105 50 0000 C CNN
-F 1 "1.75k" H 2975 1025 50 0000 C CNN
-F 2 "" H 2975 955 30 0000 C CNN
-F 3 "" V 2975 1025 30 0000 C CNN
- 1 2925 975
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R7
-U 1 1 5C9DA25C
-P 2925 2100
-F 0 "R7" H 2975 2230 50 0000 C CNN
-F 1 "3.8k" H 2975 2150 50 0000 C CNN
-F 2 "" H 2975 2080 30 0000 C CNN
-F 3 "" V 2975 2150 30 0000 C CNN
- 1 2925 2100
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q12
-U 1 1 5C9DA38D
-P 3175 2525
-F 0 "Q12" H 3075 2575 50 0000 R CNN
-F 1 "eSim_NPN" H 3125 2675 50 0000 R CNN
-F 2 "" H 3375 2625 29 0000 C CNN
-F 3 "" H 3175 2525 60 0000 C CNN
- 1 3175 2525
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q14
-U 1 1 5C9DA3C8
-P 3850 2525
-F 0 "Q14" H 3750 2575 50 0000 R CNN
-F 1 "eSim_NPN" H 3800 2675 50 0000 R CNN
-F 2 "" H 4050 2625 29 0000 C CNN
-F 3 "" H 3850 2525 60 0000 C CNN
- 1 3850 2525
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R12
-U 1 1 5C9DA421
-P 3700 1000
-F 0 "R12" H 3750 1130 50 0000 C CNN
-F 1 "3.6K" H 3750 1050 50 0000 C CNN
-F 2 "" H 3750 980 30 0000 C CNN
-F 3 "" V 3750 1050 30 0000 C CNN
- 1 3700 1000
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q1
-U 1 1 5C9DA843
-P 800 3100
-F 0 "Q1" H 700 3150 50 0000 R CNN
-F 1 "eSim_NPN" H 750 3250 50 0000 R CNN
-F 2 "" H 1000 3200 29 0000 C CNN
-F 3 "" H 800 3100 60 0000 C CNN
- 1 800 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5C9DA87E
-P 1200 3100
-F 0 "Q3" H 1100 3150 50 0000 R CNN
-F 1 "eSim_NPN" H 1150 3250 50 0000 R CNN
-F 2 "" H 1400 3200 29 0000 C CNN
-F 3 "" H 1200 3100 60 0000 C CNN
- 1 1200 3100
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q7
-U 1 1 5C9DA8BB
-P 1625 3100
-F 0 "Q7" H 1525 3150 50 0000 R CNN
-F 1 "eSim_NPN" H 1575 3250 50 0000 R CNN
-F 2 "" H 1825 3200 29 0000 C CNN
-F 3 "" H 1625 3100 60 0000 C CNN
- 1 1625 3100
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q9
-U 1 1 5C9DAACB
-P 2050 3100
-F 0 "Q9" H 1950 3150 50 0000 R CNN
-F 1 "eSim_NPN" H 2000 3250 50 0000 R CNN
-F 2 "" H 2250 3200 29 0000 C CNN
-F 3 "" H 2050 3100 60 0000 C CNN
- 1 2050 3100
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R5
-U 1 1 5C9DAE75
-P 2425 3300
-F 0 "R5" H 2475 3430 50 0000 C CNN
-F 1 "13k" H 2475 3350 50 0000 C CNN
-F 2 "" H 2475 3280 30 0000 C CNN
-F 3 "" V 2475 3350 30 0000 C CNN
- 1 2425 3300
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q2
-U 1 1 5C9DBA96
-P 925 3950
-F 0 "Q2" H 825 4000 50 0000 R CNN
-F 1 "eSim_NPN" H 875 4100 50 0000 R CNN
-F 2 "" H 1125 4050 29 0000 C CNN
-F 3 "" H 925 3950 60 0000 C CNN
- 1 925 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q8
-U 1 1 5C9DBADD
-P 1950 3950
-F 0 "Q8" H 1850 4000 50 0000 R CNN
-F 1 "eSim_NPN" H 1900 4100 50 0000 R CNN
-F 2 "" H 2150 4050 29 0000 C CNN
-F 3 "" H 1950 3950 60 0000 C CNN
- 1 1950 3950
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q6
-U 1 1 5C9DBDEB
-P 1525 4850
-F 0 "Q6" H 1425 4900 50 0000 R CNN
-F 1 "eSim_NPN" H 1475 5000 50 0000 R CNN
-F 2 "" H 1725 4950 29 0000 C CNN
-F 3 "" H 1525 4850 60 0000 C CNN
- 1 1525 4850
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R2
-U 1 1 5C9DBE93
-P 1375 5300
-F 0 "R2" H 1425 5430 50 0000 C CNN
-F 1 "200" H 1425 5350 50 0000 C CNN
-F 2 "" H 1425 5280 30 0000 C CNN
-F 3 "" V 1425 5350 30 0000 C CNN
- 1 1375 5300
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R8
-U 1 1 5C9DC899
-P 2925 3200
-F 0 "R8" H 2975 3330 50 0000 C CNN
-F 1 "8.1K" H 2975 3250 50 0000 C CNN
-F 2 "" H 2975 3180 30 0000 C CNN
-F 3 "" V 2975 3250 30 0000 C CNN
- 1 2925 3200
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R10
-U 1 1 5C9DD1D1
-P 3225 3150
-F 0 "R10" H 3275 3280 50 0000 C CNN
-F 1 "1K" H 3275 3200 50 0000 C CNN
-F 2 "" H 3275 3130 30 0000 C CNN
-F 3 "" V 3275 3200 30 0000 C CNN
- 1 3225 3150
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R13
-U 1 1 5C9DD2D0
-P 3700 3150
-F 0 "R13" H 3750 3280 50 0000 C CNN
-F 1 "1K" H 3750 3200 50 0000 C CNN
-F 2 "" H 3750 3130 30 0000 C CNN
-F 3 "" V 3750 3200 30 0000 C CNN
- 1 3700 3150
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q13
-U 1 1 5C9DCD03
-P 3450 4850
-F 0 "Q13" H 3350 4900 50 0000 R CNN
-F 1 "eSim_NPN" H 3400 5000 50 0000 R CNN
-F 2 "" H 3650 4950 29 0000 C CNN
-F 3 "" H 3450 4850 60 0000 C CNN
- 1 3450 4850
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q11
-U 1 1 5C9DCCAE
-P 2875 4850
-F 0 "Q11" H 2775 4900 50 0000 R CNN
-F 1 "eSim_NPN" H 2825 5000 50 0000 R CNN
-F 2 "" H 3075 4950 29 0000 C CNN
-F 3 "" H 2875 4850 60 0000 C CNN
- 1 2875 4850
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R9
-U 1 1 5C9DDAF5
-P 2925 5375
-F 0 "R9" H 2975 5505 50 0000 C CNN
-F 1 "200" H 2975 5425 50 0000 C CNN
-F 2 "" H 2975 5355 30 0000 C CNN
-F 3 "" V 2975 5425 30 0000 C CNN
- 1 2925 5375
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5C9DDB52
-P 3500 5400
-F 0 "R11" H 3550 5530 50 0000 C CNN
-F 1 "205" H 3550 5450 50 0000 C CNN
-F 2 "" H 3550 5380 30 0000 C CNN
-F 3 "" V 3550 5450 30 0000 C CNN
- 1 3500 5400
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q16
-U 1 1 5C9DE652
-P 4525 1150
-F 0 "Q16" H 4425 1200 50 0000 R CNN
-F 1 "eSim_NPN" H 4475 1300 50 0000 R CNN
-F 2 "" H 4725 1250 29 0000 C CNN
-F 3 "" H 4525 1150 60 0000 C CNN
- 1 4525 1150
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q18
-U 1 1 5C9DF30A
-P 4725 2200
-F 0 "Q18" H 4625 2250 50 0000 R CNN
-F 1 "eSim_NPN" H 4675 2350 50 0000 R CNN
-F 2 "" H 4925 2300 29 0000 C CNN
-F 3 "" H 4725 2200 60 0000 C CNN
- 1 4725 2200
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q20
-U 1 1 5C9DF387
-P 5150 2200
-F 0 "Q20" H 5050 2250 50 0000 R CNN
-F 1 "eSim_NPN" H 5100 2350 50 0000 R CNN
-F 2 "" H 5350 2300 29 0000 C CNN
-F 3 "" H 5150 2200 60 0000 C CNN
- 1 5150 2200
- 1 0 0 -1
-$EndComp
-NoConn ~ 4200 1550
-$Comp
-L eSim_NPN Q17
-U 1 1 5C9E05DE
-P 4525 2900
-F 0 "Q17" H 4425 2950 50 0000 R CNN
-F 1 "eSim_NPN" H 4475 3050 50 0000 R CNN
-F 2 "" H 4725 3000 29 0000 C CNN
-F 3 "" H 4525 2900 60 0000 C CNN
- 1 4525 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q21
-U 1 1 5C9E063F
-P 5150 2900
-F 0 "Q21" H 5050 2950 50 0000 R CNN
-F 1 "eSim_PNP" H 5100 3050 50 0000 R CNN
-F 2 "" H 5350 3000 29 0000 C CNN
-F 3 "" H 5150 2900 60 0000 C CNN
- 1 5150 2900
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 900 1175 900 2900
-Wire Wire Line
- 900 1400 1050 1400
-Wire Wire Line
- 1450 1400 4050 1400
-Wire Wire Line
- 1600 1400 1600 1175
-Wire Wire Line
- 900 2000 1250 2000
-Connection ~ 900 1400
-Wire Wire Line
- 900 2300 1050 2300
-Connection ~ 900 2000
-Wire Wire Line
- 900 875 2975 875
-Connection ~ 2475 875
-Connection ~ 2225 875
-Connection ~ 1600 875
-Wire Wire Line
- 1925 1075 1925 1275
-Wire Wire Line
- 1925 1275 2475 1275
-Wire Wire Line
- 2475 1175 2475 3200
-Connection ~ 2225 1275
-Wire Wire Line
- 2975 1175 2975 2000
-Wire Wire Line
- 2975 1325 2725 1325
-Wire Wire Line
- 2725 1325 2725 775
-Connection ~ 2975 1325
-Wire Wire Line
- 2225 875 2225 775
-Wire Wire Line
- 3275 2325 3275 875
-Wire Wire Line
- 2950 875 9575 875
-Connection ~ 2950 875
-Wire Wire Line
- 3750 875 3750 900
-Connection ~ 3275 875
-Wire Wire Line
- 3750 1200 3750 2325
-Wire Wire Line
- 4050 1400 4050 2525
-Connection ~ 1600 1400
-Wire Wire Line
- 1250 1700 1800 1700
-Wire Wire Line
- 1800 1400 1800 2650
-Connection ~ 1800 1400
-Wire Wire Line
- 1800 2300 1450 2300
-Connection ~ 1800 1700
-Wire Wire Line
- 900 2525 2975 2525
-Connection ~ 900 2300
-Wire Wire Line
- 1425 3100 1400 3100
-Wire Wire Line
- 1725 3300 1950 3300
-Wire Wire Line
- 900 3300 1100 3300
-Connection ~ 900 2525
-Wire Wire Line
- 1800 2650 1950 2650
-Wire Wire Line
- 1950 2650 1950 2900
-Connection ~ 1800 2300
-Wire Wire Line
- 1800 2600 1100 2600
-Wire Wire Line
- 1100 2600 1100 2900
-Connection ~ 1800 2600
-Wire Wire Line
- 1725 2900 1725 2525
-Connection ~ 1725 2525
-Wire Wire Line
- 1425 2800 2475 2800
-Wire Wire Line
- 1425 2800 1425 3100
-Connection ~ 2475 2800
-Wire Wire Line
- 2250 3100 2350 3100
-Wire Wire Line
- 2350 2975 2350 3525
-Wire Wire Line
- 2350 3525 525 3525
-Wire Wire Line
- 525 3525 525 3100
-Wire Wire Line
- 525 3100 600 3100
-Wire Wire Line
- 1025 3750 1025 3300
-Connection ~ 1025 3300
-Wire Wire Line
- 1850 3750 1850 3300
-Connection ~ 1850 3300
-Wire Wire Line
- 1025 4150 1850 4150
-Wire Wire Line
- 2150 3950 2150 4425
-Wire Wire Line
- 1425 4650 1425 4150
-Connection ~ 1425 4150
-Wire Wire Line
- 1425 5050 1425 5200
-Wire Wire Line
- 2475 3500 2475 6000
-Wire Wire Line
- 1425 6000 9575 6000
-Wire Wire Line
- 1425 6000 1425 5500
-Wire Wire Line
- 2975 2300 2975 3100
-Wire Wire Line
- 2975 2975 2350 2975
-Connection ~ 2350 3100
-Connection ~ 2975 2975
-Wire Wire Line
- 3750 3050 3750 2725
-Wire Wire Line
- 3275 2725 3275 3050
-Wire Wire Line
- 3275 3350 3275 3450
-Wire Wire Line
- 3275 3450 3750 3450
-Wire Wire Line
- 3750 3450 3750 3350
-Connection ~ 3550 3450
-Wire Wire Line
- 3550 3450 3550 4650
-Connection ~ 2975 4525
-Wire Wire Line
- 2675 4850 2675 4525
-Wire Wire Line
- 2675 4525 2975 4525
-Wire Wire Line
- 2975 3400 2975 4650
-Connection ~ 2675 4850
-Wire Wire Line
- 1725 4850 3250 4850
-Wire Wire Line
- 2975 5050 2975 5275
-Wire Wire Line
- 3550 5050 3550 5300
-Wire Wire Line
- 2975 6000 2975 5575
-Connection ~ 2475 6000
-Wire Wire Line
- 3550 6000 3550 5600
-Connection ~ 2975 6000
-Wire Wire Line
- 4500 1350 4950 1350
-Wire Wire Line
- 3950 1150 4325 1150
-Wire Wire Line
- 3950 800 3950 1225
-Wire Wire Line
- 3950 1225 3750 1225
-Connection ~ 3750 1225
-Connection ~ 4200 1150
-Connection ~ 3950 1150
-Wire Wire Line
- 4625 950 5250 950
-Connection ~ 4625 1350
-Wire Wire Line
- 4900 950 4900 800
-Connection ~ 4900 950
-Wire Wire Line
- 4950 2200 4925 2200
-Wire Wire Line
- 5250 950 5250 1150
-Wire Wire Line
- 5250 1550 5250 2000
-Wire Wire Line
- 4625 1350 4625 2000
-Wire Wire Line
- 5250 1800 4925 1800
-Wire Wire Line
- 4925 1800 4925 2200
-Connection ~ 5250 1800
-Wire Wire Line
- 4625 2400 4625 2700
-Wire Wire Line
- 5250 2400 5250 2700
-Wire Wire Line
- 4225 2550 5250 2550
-Connection ~ 4625 2550
-Connection ~ 5250 2550
-Wire Wire Line
- 4225 2550 4225 2900
-Wire Wire Line
- 4225 2900 4325 2900
-Wire Wire Line
- 5250 3100 5250 3525
-Wire Wire Line
- 5575 3200 4900 3200
-Wire Wire Line
- 4900 3200 4900 2900
-Wire Wire Line
- 4900 2900 4950 2900
-Wire Wire Line
- 5575 800 5575 3200
-Connection ~ 5250 3200
-$Comp
-L eSim_NPN Q22
-U 1 1 5C9E12AB
-P 5150 3725
-F 0 "Q22" H 5050 3775 50 0000 R CNN
-F 1 "eSim_NPN" H 5100 3875 50 0000 R CNN
-F 2 "" H 5350 3825 29 0000 C CNN
-F 3 "" H 5150 3725 60 0000 C CNN
- 1 5150 3725
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4950 3725 4625 3725
-Wire Wire Line
- 4625 3100 4625 4625
-$Comp
-L eSim_NPN Q19
-U 1 1 5C9E1696
-P 4725 4825
-F 0 "Q19" H 4625 4875 50 0000 R CNN
-F 1 "eSim_NPN" H 4675 4975 50 0000 R CNN
-F 2 "" H 4925 4925 29 0000 C CNN
-F 3 "" H 4725 4825 60 0000 C CNN
- 1 4725 4825
- -1 0 0 -1
-$EndComp
-Connection ~ 4625 3725
-$Comp
-L eSim_NPN Q23
-U 1 1 5C9E190B
-P 5150 4825
-F 0 "Q23" H 5050 4875 50 0000 R CNN
-F 1 "eSim_NPN" H 5100 4975 50 0000 R CNN
-F 2 "" H 5350 4925 29 0000 C CNN
-F 3 "" H 5150 4825 60 0000 C CNN
- 1 5150 4825
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 4950 4825 4925 4825
-Wire Wire Line
- 5250 3925 5250 4625
-Wire Wire Line
- 5250 4275 4925 4275
-Wire Wire Line
- 4925 4275 4925 4825
-Connection ~ 5250 4275
-$Comp
-L eSim_R R14
-U 1 1 5C9E1F6D
-P 4575 5350
-F 0 "R14" H 4625 5480 50 0000 C CNN
-F 1 "530" H 4625 5400 50 0000 C CNN
-F 2 "" H 4625 5330 30 0000 C CNN
-F 3 "" V 4625 5400 30 0000 C CNN
- 1 4575 5350
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R15
-U 1 1 5C9E219A
-P 5200 5350
-F 0 "R15" H 5250 5480 50 0000 C CNN
-F 1 "530" H 5250 5400 50 0000 C CNN
-F 2 "" H 5250 5330 30 0000 C CNN
-F 3 "" V 5250 5400 30 0000 C CNN
- 1 5200 5350
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q25
-U 1 1 5C9E2EDE
-P 6050 1400
-F 0 "Q25" H 5950 1450 50 0000 R CNN
-F 1 "eSim_NPN" H 6000 1550 50 0000 R CNN
-F 2 "" H 6250 1500 29 0000 C CNN
-F 3 "" H 6050 1400 60 0000 C CNN
- 1 6050 1400
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5850 1400 5575 1400
-Connection ~ 5575 1400
-$Comp
-L eSim_R R17
-U 1 1 5C9E3164
-P 6800 1350
-F 0 "R17" H 6850 1480 50 0000 C CNN
-F 1 "6.5K" H 6850 1400 50 0000 C CNN
-F 2 "" H 6850 1330 30 0000 C CNN
-F 3 "" V 6850 1400 30 0000 C CNN
- 1 6800 1350
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 6850 800 6850 1250
-Wire Wire Line
- 6850 975 6150 975
-Wire Wire Line
- 6150 975 6150 1200
-Connection ~ 6850 975
-Connection ~ 6850 875
-Connection ~ 3750 875
-$Comp
-L eSim_PNP Q28
-U 1 1 5C9E3F7F
-P 6525 1875
-F 0 "Q28" H 6425 1925 50 0000 R CNN
-F 1 "eSim_PNP" H 6475 2025 50 0000 R CNN
-F 2 "" H 6725 1975 29 0000 C CNN
-F 3 "" H 6525 1875 60 0000 C CNN
- 1 6525 1875
- 0 1 -1 0
-$EndComp
-Wire Wire Line
- 6325 1775 6150 1775
-Wire Wire Line
- 6150 1600 6150 4625
-$Comp
-L eSim_NPN Q27
-U 1 1 5C9E4448
-P 6350 2500
-F 0 "Q27" H 6250 2550 50 0000 R CNN
-F 1 "eSim_NPN" H 6300 2650 50 0000 R CNN
-F 2 "" H 6550 2600 29 0000 C CNN
-F 3 "" H 6350 2500 60 0000 C CNN
- 1 6350 2500
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q30
-U 1 1 5C9E4653
-P 6750 2750
-F 0 "Q30" H 6650 2800 50 0000 R CNN
-F 1 "eSim_NPN" H 6700 2900 50 0000 R CNN
-F 2 "" H 6950 2850 29 0000 C CNN
-F 3 "" H 6750 2750 60 0000 C CNN
- 1 6750 2750
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 6550 2750 6450 2750
-Wire Wire Line
- 6450 2750 6450 2700
-Connection ~ 6150 1775
-$Comp
-L eSim_NPN Q31
-U 1 1 5C9E49F3
-P 7075 2350
-F 0 "Q31" H 6975 2400 50 0000 R CNN
-F 1 "eSim_NPN" H 7025 2500 50 0000 R CNN
-F 2 "" H 7275 2450 29 0000 C CNN
-F 3 "" H 7075 2350 60 0000 C CNN
- 1 7075 2350
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q32
-U 1 1 5C9E4B46
-P 7125 1875
-F 0 "Q32" H 7025 1925 50 0000 R CNN
-F 1 "eSim_PNP" H 7075 2025 50 0000 R CNN
-F 2 "" H 7325 1975 29 0000 C CNN
-F 3 "" H 7125 1875 60 0000 C CNN
- 1 7125 1875
- 0 1 -1 0
-$EndComp
-Wire Wire Line
- 6850 1550 6850 2550
-Wire Wire Line
- 6725 1775 6925 1775
-Connection ~ 6850 1775
-$Comp
-L eSim_R R19
-U 1 1 5C9E5284
-P 7400 1225
-F 0 "R19" H 7450 1355 50 0000 C CNN
-F 1 "4.7k" H 7450 1275 50 0000 C CNN
-F 2 "" H 7450 1205 30 0000 C CNN
-F 3 "" V 7450 1275 30 0000 C CNN
- 1 7400 1225
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 7450 1425 7450 2350
-Wire Wire Line
- 7325 1775 7625 1775
-Wire Wire Line
- 7450 2075 7125 2075
-Connection ~ 7450 1775
-$Comp
-L eSim_NPN Q33
-U 1 1 5C9E59CA
-P 7375 2725
-F 0 "Q33" H 7275 2775 50 0000 R CNN
-F 1 "eSim_NPN" H 7325 2875 50 0000 R CNN
-F 2 "" H 7575 2825 29 0000 C CNN
-F 3 "" H 7375 2725 60 0000 C CNN
- 1 7375 2725
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7450 2350 7475 2350
-Wire Wire Line
- 7475 2350 7475 2525
-Connection ~ 7450 2075
-Wire Wire Line
- 7175 2550 7175 3000
-$Comp
-L eSim_R R18
-U 1 1 5C9E62BC
-P 7125 3100
-F 0 "R18" H 7175 3230 50 0000 C CNN
-F 1 "8.4K" H 7175 3150 50 0000 C CNN
-F 2 "" H 7175 3080 30 0000 C CNN
-F 3 "" V 7175 3150 30 0000 C CNN
- 1 7125 3100
- 0 1 1 0
-$EndComp
-Connection ~ 7175 2725
-Wire Wire Line
- 6850 2950 6850 3300
-Wire Wire Line
- 6850 3300 7475 3300
-Wire Wire Line
- 7475 2925 7475 3600
-Connection ~ 7175 3300
-Wire Wire Line
- 7450 875 7450 1125
-$Comp
-L eSim_NPN Q35
-U 1 1 5C9E6F03
-P 7825 1775
-F 0 "Q35" H 7725 1825 50 0000 R CNN
-F 1 "eSim_NPN" H 7775 1925 50 0000 R CNN
-F 2 "" H 8025 1875 29 0000 C CNN
-F 3 "" H 7825 1775 60 0000 C CNN
- 1 7825 1775
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7925 875 7925 1575
-Connection ~ 7450 875
-$Comp
-L eSim_R R20
-U 1 1 5C9E7FB4
-P 7425 3700
-F 0 "R20" H 7475 3830 50 0000 C CNN
-F 1 "2.6K" H 7475 3750 50 0000 C CNN
-F 2 "" H 7475 3680 30 0000 C CNN
-F 3 "" V 7475 3750 30 0000 C CNN
- 1 7425 3700
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R22
-U 1 1 5C9E803D
-P 7875 3675
-F 0 "R22" H 7925 3805 50 0000 C CNN
-F 1 "4.8K" H 7925 3725 50 0000 C CNN
-F 2 "" H 7925 3655 30 0000 C CNN
-F 3 "" V 7925 3725 30 0000 C CNN
- 1 7875 3675
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 7925 1975 7925 3575
-Connection ~ 7475 3300
-$Comp
-L eSim_NPN Q24
-U 1 1 5C9E8FD5
-P 5650 5800
-F 0 "Q24" H 5550 5850 50 0000 R CNN
-F 1 "eSim_NPN" H 5600 5950 50 0000 R CNN
-F 2 "" H 5850 5900 29 0000 C CNN
-F 3 "" H 5650 5800 60 0000 C CNN
- 1 5650 5800
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 5250 5025 5250 5250
-Wire Wire Line
- 4625 5025 4625 5250
-Wire Wire Line
- 5250 5550 5250 5650
-Wire Wire Line
- 5250 5650 4625 5650
-Wire Wire Line
- 4625 5650 4625 5550
-Connection ~ 3550 6000
-Wire Wire Line
- 5550 5600 5250 5600
-Connection ~ 5250 5600
-$Comp
-L eSim_PNP Q26
-U 1 1 5C9EA5DE
-P 6150 4925
-F 0 "Q26" H 6050 4975 50 0000 R CNN
-F 1 "eSim_PNP" H 6100 5075 50 0000 R CNN
-F 2 "" H 6350 5025 29 0000 C CNN
-F 3 "" H 6150 4925 60 0000 C CNN
- 1 6150 4925
- 0 -1 -1 0
-$EndComp
-Wire Wire Line
- 5950 4825 5550 4825
-Wire Wire Line
- 5550 4825 5550 5600
-Wire Wire Line
- 6150 5125 6150 5250
-Wire Wire Line
- 6150 5250 5550 5250
-Connection ~ 5550 5250
-$Comp
-L eSim_R R16
-U 1 1 5C9EA881
-P 6100 5800
-F 0 "R16" H 6150 5930 50 0000 C CNN
-F 1 "7K" H 6150 5850 50 0000 C CNN
-F 2 "" H 6150 5780 30 0000 C CNN
-F 3 "" V 6150 5850 30 0000 C CNN
- 1 6100 5800
- 0 1 1 0
-$EndComp
-Connection ~ 5550 6000
-Wire Wire Line
- 5850 5800 5850 5575
-Wire Wire Line
- 5850 5575 6150 5575
-Wire Wire Line
- 6150 5575 6150 5700
-$Comp
-L eSim_NPN Q29
-U 1 1 5C9EAB2D
-P 6725 5400
-F 0 "Q29" H 6625 5450 50 0000 R CNN
-F 1 "eSim_NPN" H 6675 5550 50 0000 R CNN
-F 2 "" H 6925 5500 29 0000 C CNN
-F 3 "" H 6725 5400 60 0000 C CNN
- 1 6725 5400
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 6625 5600 6150 5600
-Connection ~ 6150 5600
-Wire Wire Line
- 6625 5200 6625 4825
-Wire Wire Line
- 6350 4825 9075 4825
-Wire Wire Line
- 6925 5400 7000 5400
-Wire Wire Line
- 7000 5400 7000 4825
-Connection ~ 6625 4825
-$Comp
-L eSim_NPN Q34
-U 1 1 5C9EB3F8
-P 7625 5075
-F 0 "Q34" H 7525 5125 50 0000 R CNN
-F 1 "eSim_NPN" H 7575 5225 50 0000 R CNN
-F 2 "" H 7825 5175 29 0000 C CNN
-F 3 "" H 7625 5075 60 0000 C CNN
- 1 7625 5075
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R21
-U 1 1 5C9EB4C7
-P 7475 5750
-F 0 "R21" H 7525 5880 50 0000 C CNN
-F 1 "2.4K" H 7525 5800 50 0000 C CNN
-F 2 "" H 7525 5730 30 0000 C CNN
-F 3 "" V 7525 5800 30 0000 C CNN
- 1 7475 5750
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 7525 5275 7525 5650
-Wire Wire Line
- 7525 6000 7525 5950
-Connection ~ 6150 6000
-Wire Wire Line
- 7525 4875 7525 4625
-Wire Wire Line
- 7525 4625 6150 4625
-Connection ~ 6150 2500
-NoConn ~ 6450 2300
-NoConn ~ 7175 2150
-Wire Wire Line
- 7475 3900 7475 4425
-Wire Wire Line
- 7475 4425 7875 4425
-Wire Wire Line
- 7875 4425 7875 6000
-Connection ~ 7525 6000
-Wire Wire Line
- 7925 6000 7925 3875
-Connection ~ 7875 6000
-$Comp
-L eSim_PNP Q36
-U 1 1 5C9EEDA4
-P 8475 2300
-F 0 "Q36" H 8375 2350 50 0000 R CNN
-F 1 "eSim_PNP" H 8425 2450 50 0000 R CNN
-F 2 "" H 8675 2400 29 0000 C CNN
-F 3 "" H 8475 2300 60 0000 C CNN
- 1 8475 2300
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 7925 2300 8275 2300
-Connection ~ 7925 2300
-Wire Wire Line
- 8575 2500 8575 6275
-Connection ~ 7925 6000
-$Comp
-L eSim_PNP Q38
-U 1 1 5C9F04CE
-P 9175 2300
-F 0 "Q38" H 9075 2350 50 0000 R CNN
-F 1 "eSim_PNP" H 9125 2450 50 0000 R CNN
-F 2 "" H 9375 2400 29 0000 C CNN
-F 3 "" H 9175 2300 60 0000 C CNN
- 1 9175 2300
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 8575 2100 9075 2100
-$Comp
-L eSim_R R23
-U 1 1 5C9F0909
-P 8800 1275
-F 0 "R23" H 8850 1405 50 0000 C CNN
-F 1 "16K" H 8850 1325 50 0000 C CNN
-F 2 "" H 8850 1255 30 0000 C CNN
-F 3 "" V 8850 1325 30 0000 C CNN
- 1 8800 1275
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 8850 1475 8850 2625
-Connection ~ 8850 2100
-Wire Wire Line
- 8850 875 8850 1175
-Connection ~ 7925 875
-Wire Wire Line
- 8175 2300 8175 800
-Connection ~ 8175 2300
-$Comp
-L eSim_R R24
-U 1 1 5C9F1F80
-P 9025 3775
-F 0 "R24" H 9075 3905 50 0000 C CNN
-F 1 "5.8k" H 9075 3825 50 0000 C CNN
-F 2 "" H 9075 3755 30 0000 C CNN
-F 3 "" V 9075 3825 30 0000 C CNN
- 1 9025 3775
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 9075 2500 9075 3675
-Connection ~ 8575 6000
-$Comp
-L eSim_NPN Q37
-U 1 1 5C9F3715
-P 8850 3025
-F 0 "Q37" H 8750 3075 50 0000 R CNN
-F 1 "eSim_NPN" H 8800 3175 50 0000 R CNN
-F 2 "" H 9050 3125 29 0000 C CNN
-F 3 "" H 8850 3025 60 0000 C CNN
- 1 8850 3025
- -1 0 0 -1
-$EndComp
-Wire Wire Line
- 8750 2825 8750 2625
-Wire Wire Line
- 8750 2625 8850 2625
-Wire Wire Line
- 9075 3025 9050 3025
-Connection ~ 9075 3025
-Wire Wire Line
- 9075 4825 9075 3975
-Connection ~ 7000 4825
-Wire Wire Line
- 8750 3225 8750 4825
-Connection ~ 8750 4825
-$Comp
-L eSim_NPN Q40
-U 1 1 5C9F5A03
-P 9475 5100
-F 0 "Q40" H 9375 5150 50 0000 R CNN
-F 1 "eSim_NPN" H 9425 5250 50 0000 R CNN
-F 2 "" H 9675 5200 29 0000 C CNN
-F 3 "" H 9475 5100 60 0000 C CNN
- 1 9475 5100
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 7825 5100 9275 5100
-Wire Wire Line
- 7825 5100 7825 5075
-$Comp
-L eSim_R R26
-U 1 1 5C9F5D68
-P 9525 5600
-F 0 "R26" H 9575 5730 50 0000 C CNN
-F 1 "200" H 9575 5650 50 0000 C CNN
-F 2 "" H 9575 5580 30 0000 C CNN
-F 3 "" V 9575 5650 30 0000 C CNN
- 1 9525 5600
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 9575 5300 9575 5500
-Wire Wire Line
- 9575 6000 9575 5800
-Wire Wire Line
- 9575 1300 9575 4900
-Wire Wire Line
- 9575 2300 9375 2300
-$Comp
-L eSim_R R25
-U 1 1 5C9F78A7
-P 9525 1100
-F 0 "R25" H 9575 1230 50 0000 C CNN
-F 1 "4.3k" H 9575 1150 50 0000 C CNN
-F 2 "" H 9575 1080 30 0000 C CNN
-F 3 "" V 9575 1150 30 0000 C CNN
- 1 9525 1100
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 9575 875 9575 1000
-Connection ~ 8850 875
-Connection ~ 9575 2300
-$Comp
-L eSim_NPN Q39
-U 1 1 5C9F7E6C
-P 9300 1325
-F 0 "Q39" H 9200 1375 50 0000 R CNN
-F 1 "eSim_NPN" H 9250 1475 50 0000 R CNN
-F 2 "" H 9500 1425 29 0000 C CNN
-F 3 "" H 9300 1325 60 0000 C CNN
- 1 9300 1325
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 9200 1125 9200 875
-Connection ~ 9200 875
-Wire Wire Line
- 9500 1325 9575 1325
-Connection ~ 9575 1325
-NoConn ~ 9200 1525
-Wire Wire Line
- 8375 5100 8375 6275
-Wire Wire Line
- 8375 6275 1975 6275
-Wire Wire Line
- 1975 6275 1975 4850
-Connection ~ 1975 4850
-Connection ~ 8375 5100
-$Comp
-L PORT U1
-U 1 1 5C9FA174
-P 8575 6525
-F 0 "U1" H 8625 6625 30 0000 C CNN
-F 1 "PORT" H 8575 6525 30 0000 C CNN
-F 2 "" H 8575 6525 60 0000 C CNN
-F 3 "" H 8575 6525 60 0000 C CNN
- 1 8575 6525
- 0 -1 -1 0
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9FBFA4
-P 475 3950
-F 0 "U1" H 525 4050 30 0000 C CNN
-F 1 "PORT" H 475 3950 30 0000 C CNN
-F 2 "" H 475 3950 60 0000 C CNN
-F 3 "" H 475 3950 60 0000 C CNN
- 3 475 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9FC1B0
-P 600 4425
-F 0 "U1" H 650 4525 30 0000 C CNN
-F 1 "PORT" H 600 4425 30 0000 C CNN
-F 2 "" H 600 4425 60 0000 C CNN
-F 3 "" H 600 4425 60 0000 C CNN
- 2 600 4425
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 2150 4425 850 4425
-$Comp
-L PORT U1
-U 5 1 5C9FD8AC
-P 2225 525
-F 0 "U1" H 2275 625 30 0000 C CNN
-F 1 "PORT" H 2225 525 30 0000 C CNN
-F 2 "" H 2225 525 60 0000 C CNN
-F 3 "" H 2225 525 60 0000 C CNN
- 5 2225 525
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9FD96B
-P 2725 525
-F 0 "U1" H 2775 625 30 0000 C CNN
-F 1 "PORT" H 2725 525 30 0000 C CNN
-F 2 "" H 2725 525 60 0000 C CNN
-F 3 "" H 2725 525 60 0000 C CNN
- 6 2725 525
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C9FDA44
-P 3950 550
-F 0 "U1" H 4000 650 30 0000 C CNN
-F 1 "PORT" H 3950 550 30 0000 C CNN
-F 2 "" H 3950 550 60 0000 C CNN
-F 3 "" H 3950 550 60 0000 C CNN
- 7 3950 550
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9FDAFF
-P 4900 550
-F 0 "U1" H 4950 650 30 0000 C CNN
-F 1 "PORT" H 4900 550 30 0000 C CNN
-F 2 "" H 4900 550 60 0000 C CNN
-F 3 "" H 4900 550 60 0000 C CNN
- 8 4900 550
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 9 1 5C9FDBB4
-P 5575 550
-F 0 "U1" H 5625 650 30 0000 C CNN
-F 1 "PORT" H 5575 550 30 0000 C CNN
-F 2 "" H 5575 550 60 0000 C CNN
-F 3 "" H 5575 550 60 0000 C CNN
- 9 5575 550
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 10 1 5C9FDC77
-P 6850 550
-F 0 "U1" H 6900 650 30 0000 C CNN
-F 1 "PORT" H 6850 550 30 0000 C CNN
-F 2 "" H 6850 550 60 0000 C CNN
-F 3 "" H 6850 550 60 0000 C CNN
- 10 6850 550
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9FE0D8
-P 8175 550
-F 0 "U1" H 8225 650 30 0000 C CNN
-F 1 "PORT" H 8175 550 30 0000 C CNN
-F 2 "" H 8175 550 60 0000 C CNN
-F 3 "" H 8175 550 60 0000 C CNN
- 4 8175 550
- 0 1 1 0
-$EndComp
-Text GLabel 2125 775 0 60 Input ~ 0
-Phase_comparator_vco_input
-Wire Wire Line
- 2225 775 2125 775
-Text GLabel 2775 775 2 60 Input ~ 0
-Reference_output
-Wire Wire Line
- 2725 775 2775 775
-Text GLabel 3975 800 2 55 Input ~ 0
-Vco_control_voltage
-Wire Wire Line
- 3975 800 3950 800
-Text GLabel 4900 800 2 39 Input ~ 0
-Timming_resistor
-Text GLabel 5575 800 2 39 Input ~ 0
-Timing_capacitor
-Text GLabel 6850 800 0 39 Input ~ 0
-+Vcc
-Text GLabel 8175 800 0 39 Input ~ 0
-Vco_output
-Text GLabel 8575 6275 2 39 Input ~ 0
--Vcc
-Text GLabel 675 4075 0 39 Input ~ 0
-Input
-Wire Wire Line
- 675 4075 725 4075
-Wire Wire Line
- 725 4075 725 3950
-Text GLabel 850 4250 0 39 Input ~ 0
-Input
-Wire Wire Line
- 850 4250 875 4250
-Wire Wire Line
- 875 4250 875 4425
-Connection ~ 875 4425
-Wire Wire Line
- 6525 2350 6525 2075
-Wire Wire Line
- 6525 2350 6875 2350
-Connection ~ 6850 2350
-$Comp
-L eSim_NPN Q15
-U 1 1 5CA0DF1A
-P 4300 1350
-F 0 "Q15" H 4200 1400 50 0000 R CNN
-F 1 "eSim_NPN" H 4250 1500 50 0000 R CNN
-F 2 "" H 4500 1450 29 0000 C CNN
-F 3 "" H 4300 1350 60 0000 C CNN
- 1 4300 1350
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q41
-U 1 1 5CA0E6BE
-P 5150 1350
-F 0 "Q41" H 5050 1400 50 0000 R CNN
-F 1 "eSim_PNP" H 5100 1500 50 0000 R CNN
-F 2 "" H 5350 1450 29 0000 C CNN
-F 3 "" H 5150 1350 60 0000 C CNN
- 1 5150 1350
- 1 0 0 1
-$EndComp
-$Comp
-L PWR_FLAG #FLG01
-U 1 1 5CA131E0
-P 2300 3950
-F 0 "#FLG01" H 2300 4045 50 0001 C CNN
-F 1 "PWR_FLAG" H 2300 4130 50 0000 C CNN
-F 2 "" H 2300 3950 50 0000 C CNN
-F 3 "" H 2300 3950 50 0000 C CNN
- 1 2300 3950
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 2150 3950 2300 3950
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LM565/LM565.sub b/src/SubcircuitLibrary/LM565/LM565.sub deleted file mode 100644 index 31747d1e..00000000 --- a/src/SubcircuitLibrary/LM565/LM565.sub +++ /dev/null @@ -1,75 +0,0 @@ -* Subcircuit LM565
-.subckt LM565 -vcc input input vco_output +vcc reference_output vco_control_voltage timming_resistor timing_capacitor +vcc
-* c:\esim_1\esim\src\subcircuitlibrary\lm565\lm565.cir
-.include PNP.lib
-.include NPN.lib
-r1 +vcc net-_q1-pad1_ 7.2k
-r3 +vcc net-_q14-pad2_ 7.2k
-q4 net-_q14-pad2_ net-_q14-pad2_ net-_q1-pad1_ Q2N2222
-q5 net-_q1-pad1_ net-_q1-pad1_ net-_q14-pad2_ Q2N2222
-q10 net-_q10-pad1_ net-_q10-pad1_ +vcc Q2N2222
-r4 +vcc net-_q3-pad2_ 5.7k
-r6 +vcc reference_output 1.75k
-r7 reference_output net-_q1-pad2_ 3.8k
-q12 +vcc net-_q1-pad1_ net-_q12-pad3_ Q2N2222
-q14 vco_control_voltage net-_q14-pad2_ net-_q14-pad3_ Q2N2222
-r12 +vcc vco_control_voltage 3.6k
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
-q3 net-_q14-pad2_ net-_q3-pad2_ net-_q1-pad3_ Q2N2222
-q7 net-_q1-pad1_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q9 net-_q14-pad2_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222
-r5 net-_q3-pad2_ -vcc 13k
-q2 net-_q1-pad3_ input net-_q2-pad3_ Q2N2222
-q8 net-_q7-pad3_ input net-_q2-pad3_ Q2N2222
-q6 net-_q2-pad3_ net-_q11-pad1_ net-_q6-pad3_ Q2N2222
-r2 net-_q6-pad3_ -vcc 200
-r8 net-_q1-pad2_ net-_q11-pad1_ 8.1k
-r10 net-_q12-pad3_ net-_q13-pad1_ 1k
-r13 net-_q14-pad3_ net-_q13-pad1_ 1k
-q13 net-_q13-pad1_ net-_q11-pad1_ net-_q13-pad3_ Q2N2222
-q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222
-r9 net-_q11-pad3_ -vcc 200
-r11 net-_q13-pad3_ -vcc 205
-q16 timming_resistor vco_control_voltage net-_q15-pad2_ Q2N2222
-q18 net-_q15-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q20 net-_q18-pad2_ net-_q18-pad2_ net-_q17-pad1_ Q2N2222
-q17 net-_q17-pad1_ net-_q17-pad1_ net-_q17-pad3_ Q2N2222
-q21 timing_capacitor timing_capacitor net-_q17-pad1_ Q2N2907A
-q22 timing_capacitor net-_q17-pad3_ net-_q19-pad2_ Q2N2222
-q19 net-_q17-pad3_ net-_q19-pad2_ net-_q19-pad3_ Q2N2222
-q23 net-_q19-pad2_ net-_q19-pad2_ net-_q23-pad3_ Q2N2222
-r14 net-_q19-pad3_ net-_q24-pad1_ 530
-r15 net-_q23-pad3_ net-_q24-pad1_ 530
-q25 +vcc timing_capacitor net-_q25-pad3_ Q2N2222
-r17 +vcc net-_q28-pad1_ 6.5k
-q28 net-_q28-pad1_ net-_q28-pad1_ net-_q25-pad3_ Q2N2907A
-q27 ? net-_q25-pad3_ net-_q27-pad3_ Q2N2222
-q30 net-_q28-pad1_ net-_q27-pad3_ net-_q30-pad3_ Q2N2222
-q31 ? net-_q28-pad1_ net-_q31-pad3_ Q2N2222
-q32 net-_q32-pad1_ net-_q32-pad1_ net-_q28-pad1_ Q2N2907A
-r19 +vcc net-_q32-pad1_ 4.7k
-q33 net-_q32-pad1_ net-_q31-pad3_ net-_q30-pad3_ Q2N2222
-r18 net-_q31-pad3_ net-_q30-pad3_ 8.4k
-q35 +vcc net-_q32-pad1_ vco_output Q2N2222
-r20 net-_q30-pad3_ -vcc 2.6k
-r22 vco_output -vcc 4.8k
-q24 net-_q24-pad1_ net-_q24-pad2_ -vcc Q2N2222
-q26 net-_q24-pad1_ net-_q24-pad1_ net-_q26-pad3_ Q2N2907A
-r16 net-_q24-pad2_ -vcc 7k
-q29 net-_q26-pad3_ net-_q26-pad3_ net-_q24-pad2_ Q2N2222
-q34 net-_q25-pad3_ net-_q11-pad1_ net-_q34-pad3_ Q2N2222
-r21 net-_q34-pad3_ -vcc 2.4k
-q36 -vcc vco_output net-_q36-pad3_ Q2N2907A
-q38 net-_q37-pad2_ net-_q38-pad2_ net-_q36-pad3_ Q2N2907A
-r23 +vcc net-_q36-pad3_ 16k
-r24 net-_q37-pad2_ net-_q26-pad3_ 5.8k
-q37 net-_q36-pad3_ net-_q37-pad2_ net-_q26-pad3_ Q2N2222
-q40 net-_q38-pad2_ net-_q11-pad1_ net-_q40-pad3_ Q2N2222
-r26 net-_q40-pad3_ -vcc 200
-r25 +vcc net-_q38-pad2_ 4.3k
-q39 ? net-_q38-pad2_ +vcc Q2N2222
-q15 ? net-_q15-pad2_ vco_control_voltage Q2N2222
-q41 net-_q18-pad2_ net-_q15-pad2_ timming_resistor Q2N2907A
-* Control Statements
-
-.ends LM565
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml b/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml deleted file mode 100644 index c60f46f5..00000000 --- a/src/SubcircuitLibrary/LM565/LM565_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><q35><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q35><q40><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q40><q41><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q41><q34><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q34><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q20><q21><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q21><q22><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q22><q23><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q23><q24><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q24><q25><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q25><q26><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q26><q27><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q27><q28><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q28><q29><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q29><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q33><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q33><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12><q39><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q39><q38><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q38><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q32><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q32><q31><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q31><q30><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q30><q37><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q37><q36><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q36></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM565/NPN.lib b/src/SubcircuitLibrary/LM565/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/LM565/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM565/PNP.lib b/src/SubcircuitLibrary/LM565/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/LM565/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib b/src/SubcircuitLibrary/LM7812/LM7812-cache.lib deleted file mode 100644 index c02b3211..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812-cache.lib +++ /dev/null @@ -1,135 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -F2 "" -70 0 50 V V C CNN -F3 "" 0 0 50 H V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S -40 -100 40 100 0 1 10 N -X ~ 1 0 150 50 D 50 50 1 1 P -X ~ 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_NPN-RESCUE-LM7812 -# -DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -# eSim_PNP-RESCUE-LM7812 -# -DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -# zener -# -DEF zener U 0 40 Y Y 1 F N -F0 "U" -50 -100 60 H V C CNN -F1 "zener" 0 100 60 H V C CNN -F2 "" 50 0 60 H V C CNN -F3 "" 50 0 60 H V C CNN -DRAW -P 2 0 1 0 100 -50 50 -100 N -P 2 0 1 0 100 50 100 -50 N -P 2 0 1 0 100 50 150 100 N -P 4 0 1 0 0 50 0 -50 100 0 0 50 N -X ~ IN -200 0 200 R 50 43 1 1 I -X ~ OUT 300 0 200 L 50 43 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib b/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib deleted file mode 100644 index e6cfa7d6..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812-rescue.lib +++ /dev/null @@ -1,42 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# eSim_NPN-RESCUE-LM7812 -# -DEF eSim_NPN-RESCUE-LM7812 Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN-RESCUE-LM7812" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -# eSim_PNP-RESCUE-LM7812 -# -DEF eSim_PNP-RESCUE-LM7812 Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_PNP-RESCUE-LM7812" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir b/src/SubcircuitLibrary/LM7812/LM7812.cir deleted file mode 100644 index 3f0d3adf..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812.cir +++ /dev/null @@ -1,51 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/LM7812/LM7812.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 10 16:26:28 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k -R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 -R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k -R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k -U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener -Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN -R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 -Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN -Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN -R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k -Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN -R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k -Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN -R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k -Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN -Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN -Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN -R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k -R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k -Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP -Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP -R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 -R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 -Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN -Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN -Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN -R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k -C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p -R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k -Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP -Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN -R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k -R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 10.38k -R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k -U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener -Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN -Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN -R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 -R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 -R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 -U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT - -.end diff --git a/src/SubcircuitLibrary/LM7812/LM7812.cir.out b/src/SubcircuitLibrary/LM7812/LM7812.cir.out deleted file mode 100644 index 73404965..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812.cir.out +++ /dev/null @@ -1,60 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir - -.include PNP.lib -.include NPN.lib -r1 net-_q16-pad1_ net-_q1-pad2_ 100k -r2 net-_q16-pad1_ net-_q1-pad1_ 500 -r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k -r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k -* u1 net-_q10-pad3_ net-_q1-pad2_ zener -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -r5 net-_q10-pad2_ net-_q10-pad3_ 500 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 -r6 net-_q2-pad3_ net-_q3-pad1_ 1k -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 -r7 net-_q3-pad2_ net-_q10-pad3_ 6k -q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 -r10 net-_q6-pad3_ net-_q10-pad3_ 1k -q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 -q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 -q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 -r12 net-_q12-pad3_ net-_q2-pad3_ 6k -r9 net-_q2-pad3_ net-_c1-pad2_ 20k -q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A -q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A -r8 net-_q16-pad1_ net-_q5-pad3_ 100 -r11 net-_q16-pad1_ net-_q9-pad3_ 50 -q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 -q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 -q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 -r13 net-_q11-pad3_ net-_q10-pad3_ 6k -c1 net-_c1-pad1_ net-_c1-pad2_ 30p -r14 net-_q10-pad1_ net-_c1-pad1_ 6k -q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A -q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 -r17 net-_q12-pad2_ net-_q10-pad3_ 5k -r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k -r15 net-_q16-pad1_ net-_r15-pad2_ 10k -* u2 net-_q15-pad2_ net-_r15-pad2_ zener -q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 -q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 -r18 net-_q16-pad3_ net-_q12-pad1_ 200 -r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 -r19 net-_q17-pad3_ net-_q15-pad2_ 240 -* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port -a1 net-_q10-pad3_ net-_q1-pad2_ u1 -a2 net-_q15-pad2_ net-_r15-pad2_ u2 -* Schematic Name: zener, NgSpice Name: zener -.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -* Schematic Name: zener, NgSpice Name: zener -.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/LM7812/LM7812.pro b/src/SubcircuitLibrary/LM7812/LM7812.pro deleted file mode 100644 index 12d08139..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812.pro +++ /dev/null @@ -1,46 +0,0 @@ -update=Mon Aug 26 14:09:03 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=LM7812-rescue -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_PSpice -LibName10=eSim_Sources -LibName11=eSim_Subckt -LibName12=eSim_User - diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sch b/src/SubcircuitLibrary/LM7812/LM7812.sch deleted file mode 100644 index ca95c2ca..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812.sch +++ /dev/null @@ -1,758 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:LM7812-rescue -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:LM7812-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L R R1 -U 1 1 5CE41429 -P 1250 1600 -F 0 "R1" V 1330 1600 50 0000 C CNN -F 1 "100k" V 1250 1600 50 0000 C CNN -F 2 "" V 1180 1600 50 0001 C CNN -F 3 "" H 1250 1600 50 0001 C CNN - 1 1250 1600 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5CE4148B -P 1950 1600 -F 0 "R2" V 2030 1600 50 0000 C CNN -F 1 "500" V 1950 1600 50 0000 C CNN -F 2 "" V 1880 1600 50 0001 C CNN -F 3 "" H 1950 1600 50 0001 C CNN - 1 1950 1600 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 5CE414A5 -P 1950 3050 -F 0 "R3" V 2030 3050 50 0000 C CNN -F 1 "3.3k" V 1950 3050 50 0000 C CNN -F 2 "" V 1880 3050 50 0001 C CNN -F 3 "" H 1950 3050 50 0001 C CNN - 1 1950 3050 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 5CE414CA -P 1950 3750 -F 0 "R4" V 2030 3750 50 0000 C CNN -F 1 "2.7k" V 1950 3750 50 0000 C CNN -F 2 "" V 1880 3750 50 0001 C CNN -F 3 "" H 1950 3750 50 0001 C CNN - 1 1950 3750 - 1 0 0 -1 -$EndComp -$Comp -L zener U1 -U 1 1 5CE414FA -P 1250 3350 -F 0 "U1" H 1200 3250 60 0000 C CNN -F 1 "zener" H 1250 3450 60 0000 C CNN -F 2 "" H 1300 3350 60 0000 C CNN -F 3 "" H 1300 3350 60 0000 C CNN - 1 1250 3350 - 0 -1 -1 0 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q1 -U 1 1 5CE41586 -P 1850 2350 -F 0 "Q1" H 1750 2400 50 0000 R CNN -F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN -F 2 "" H 2050 2450 29 0000 C CNN -F 3 "" H 1850 2350 60 0000 C CNN - 1 1850 2350 - 1 0 0 -1 -$EndComp -$Comp -L R R5 -U 1 1 5CE418C5 -P 1950 4600 -F 0 "R5" V 2030 4600 50 0000 C CNN -F 1 "500" V 1950 4600 50 0000 C CNN -F 2 "" V 1880 4600 50 0001 C CNN -F 3 "" H 1950 4600 50 0001 C CNN - 1 1950 4600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1250 1750 1250 3050 -Wire Wire Line - 1250 1450 1250 1300 -Wire Wire Line - 1250 1300 1950 1300 -Wire Wire Line - 1950 1300 1950 1450 -Wire Wire Line - 1950 2150 1950 1750 -Wire Wire Line - 1950 2550 1950 2900 -Wire Wire Line - 1950 3200 1950 3600 -Wire Wire Line - 1950 3900 1950 4450 -Wire Wire Line - 1250 3550 1250 5200 -Wire Wire Line - 1250 5200 3200 5200 -Wire Wire Line - 1950 5200 1950 4750 -Wire Wire Line - 1650 2350 1250 2350 -Connection ~ 1250 2350 -$Comp -L eSim_NPN-RESCUE-LM7812 Q2 -U 1 1 5CE41D6C -P 2650 3350 -F 0 "Q2" H 2550 3400 50 0000 R CNN -F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN -F 2 "" H 2850 3450 29 0000 C CNN -F 3 "" H 2650 3350 60 0000 C CNN - 1 2650 3350 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q4 -U 1 1 5CE41E26 -P 3100 4100 -F 0 "Q4" H 3000 4150 50 0000 R CNN -F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN -F 2 "" H 3300 4200 29 0000 C CNN -F 3 "" H 3100 4100 60 0000 C CNN - 1 3100 4100 - 1 0 0 -1 -$EndComp -$Comp -L R R6 -U 1 1 5CE41EA8 -P 2750 3850 -F 0 "R6" V 2830 3850 50 0000 C CNN -F 1 "1k" V 2750 3850 50 0000 C CNN -F 2 "" V 2680 3850 50 0001 C CNN -F 3 "" H 2750 3850 50 0001 C CNN - 1 2750 3850 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q3 -U 1 1 5CE41EFE -P 2850 4650 -F 0 "Q3" H 2750 4700 50 0000 R CNN -F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN -F 2 "" H 3050 4750 29 0000 C CNN -F 3 "" H 2850 4650 60 0000 C CNN - 1 2850 4650 - -1 0 0 -1 -$EndComp -Wire Wire Line - 2750 3550 2750 3700 -Wire Wire Line - 2750 4000 2750 4450 -Wire Wire Line - 2900 4100 2750 4100 -Connection ~ 2750 4100 -Wire Wire Line - 3200 4300 3200 4750 -Wire Wire Line - 3050 4650 3450 4650 -Wire Wire Line - 2450 3350 1950 3350 -Connection ~ 1950 3350 -Wire Wire Line - 2750 3600 3600 3600 -Wire Wire Line - 3200 3600 3200 3900 -Connection ~ 2750 3600 -$Comp -L R R7 -U 1 1 5CE42281 -P 3200 4900 -F 0 "R7" V 3280 4900 50 0000 C CNN -F 1 "6k" V 3200 4900 50 0000 C CNN -F 2 "" V 3130 4900 50 0001 C CNN -F 3 "" H 3200 4900 50 0001 C CNN - 1 3200 4900 - 1 0 0 -1 -$EndComp -Connection ~ 3200 4650 -Wire Wire Line - 3200 5050 3200 5250 -Connection ~ 1950 5200 -Wire Wire Line - 2750 4850 2750 5200 -Connection ~ 2750 5200 -$Comp -L eSim_NPN-RESCUE-LM7812 Q6 -U 1 1 5CE424FB -P 3650 4650 -F 0 "Q6" H 3550 4700 50 0000 R CNN -F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN -F 2 "" H 3850 4750 29 0000 C CNN -F 3 "" H 3650 4650 60 0000 C CNN - 1 3650 4650 - 1 0 0 -1 -$EndComp -$Comp -L R R10 -U 1 1 5CE42584 -P 3750 5100 -F 0 "R10" V 3830 5100 50 0000 C CNN -F 1 "1k" V 3750 5100 50 0000 C CNN -F 2 "" V 3680 5100 50 0001 C CNN -F 3 "" H 3750 5100 50 0001 C CNN - 1 3750 5100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3750 4850 3750 4950 -Wire Wire Line - 3200 5250 3750 5250 -Connection ~ 3200 5200 -$Comp -L eSim_NPN-RESCUE-LM7812 Q7 -U 1 1 5CE427DA -P 3700 2750 -F 0 "Q7" H 3600 2800 50 0000 R CNN -F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN -F 2 "" H 3900 2850 29 0000 C CNN -F 3 "" H 3700 2750 60 0000 C CNN - 1 3700 2750 - -1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q8 -U 1 1 5CE428D0 -P 3700 3400 -F 0 "Q8" H 3600 3450 50 0000 R CNN -F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN -F 2 "" H 3900 3500 29 0000 C CNN -F 3 "" H 3700 3400 60 0000 C CNN - 1 3700 3400 - -1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q12 -U 1 1 5CE4293A -P 4350 3000 -F 0 "Q12" H 4250 3050 50 0000 R CNN -F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN -F 2 "" H 4550 3100 29 0000 C CNN -F 3 "" H 4350 3000 60 0000 C CNN - 1 4350 3000 - -1 0 0 -1 -$EndComp -Wire Wire Line - 3600 2950 3600 3200 -Wire Wire Line - 4250 3200 4250 3400 -Wire Wire Line - 4250 3400 3900 3400 -Wire Wire Line - 4250 2750 4250 2800 -Wire Wire Line - 3900 2750 4250 2750 -Connection ~ 3200 3600 -$Comp -L R R12 -U 1 1 5CE42C4F -P 4350 3450 -F 0 "R12" V 4430 3450 50 0000 C CNN -F 1 "6k" V 4350 3450 50 0000 C CNN -F 2 "" V 4280 3450 50 0001 C CNN -F 3 "" H 4350 3450 50 0001 C CNN - 1 4350 3450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4350 3300 4250 3300 -Connection ~ 4250 3300 -Wire Wire Line - 3700 3600 4350 3600 -Wire Wire Line - 3700 3600 3700 3650 -Wire Wire Line - 3700 3650 3550 3650 -Wire Wire Line - 3550 3650 3550 3600 -Connection ~ 3550 3600 -$Comp -L R R9 -U 1 1 5CE42EA3 -P 3750 3950 -F 0 "R9" V 3830 3950 50 0000 C CNN -F 1 "20k" V 3750 3950 50 0000 C CNN -F 2 "" V 3680 3950 50 0001 C CNN -F 3 "" H 3750 3950 50 0001 C CNN - 1 3750 3950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3750 4100 3750 4450 -Wire Wire Line - 3750 3800 3750 3600 -Connection ~ 3750 3600 -Wire Wire Line - 2750 3150 2750 2450 -Wire Wire Line - 2750 2450 3600 2450 -Wire Wire Line - 3600 2450 3600 2550 -$Comp -L eSim_PNP-RESCUE-LM7812 Q5 -U 1 1 5CE43397 -P 3450 1700 -F 0 "Q5" H 3350 1750 50 0000 R CNN -F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN -F 2 "" H 3650 1800 29 0000 C CNN -F 3 "" H 3450 1700 60 0000 C CNN - 1 3450 1700 - -1 0 0 1 -$EndComp -$Comp -L eSim_PNP-RESCUE-LM7812 Q9 -U 1 1 5CE4353C -P 4100 1700 -F 0 "Q9" H 4000 1750 50 0000 R CNN -F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN -F 2 "" H 4300 1800 29 0000 C CNN -F 3 "" H 4100 1700 60 0000 C CNN - 1 4100 1700 - 1 0 0 1 -$EndComp -$Comp -L R R8 -U 1 1 5CE435B8 -P 3350 1250 -F 0 "R8" V 3430 1250 50 0000 C CNN -F 1 "100" V 3350 1250 50 0000 C CNN -F 2 "" V 3280 1250 50 0001 C CNN -F 3 "" H 3350 1250 50 0001 C CNN - 1 3350 1250 - 1 0 0 -1 -$EndComp -$Comp -L R R11 -U 1 1 5CE4368E -P 4200 1250 -F 0 "R11" V 4280 1250 50 0000 C CNN -F 1 "50" V 4200 1250 50 0000 C CNN -F 2 "" V 4130 1250 50 0001 C CNN -F 3 "" H 4200 1250 50 0001 C CNN - 1 4200 1250 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q10 -U 1 1 5CE43705 -P 4100 2200 -F 0 "Q10" H 4000 2250 50 0000 R CNN -F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN -F 2 "" H 4300 2300 29 0000 C CNN -F 3 "" H 4100 2200 60 0000 C CNN - 1 4100 2200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3350 1400 3350 1500 -Wire Wire Line - 3650 1700 3900 1700 -Wire Wire Line - 4200 1400 4200 1500 -Wire Wire Line - 3350 1100 3350 1050 -Wire Wire Line - 1650 1050 7800 1050 -Wire Wire Line - 4200 1050 4200 1100 -Wire Wire Line - 4200 1900 4200 2000 -Wire Wire Line - 3750 1700 3750 2000 -Wire Wire Line - 3750 2000 3350 2000 -Wire Wire Line - 3350 1900 3350 2450 -Connection ~ 3750 1700 -Connection ~ 3350 2450 -Connection ~ 3350 2000 -Wire Wire Line - 2300 2200 3900 2200 -Wire Wire Line - 2300 2200 2300 4200 -Wire Wire Line - 2300 4200 1950 4200 -Connection ~ 1950 4200 -Wire Wire Line - 2200 2400 4200 2400 -Wire Wire Line - 2200 2400 2200 5200 -Connection ~ 2200 5200 -$Comp -L eSim_NPN-RESCUE-LM7812 Q11 -U 1 1 5CE4439E -P 4300 4400 -F 0 "Q11" H 4200 4450 50 0000 R CNN -F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN -F 2 "" H 4500 4500 29 0000 C CNN -F 3 "" H 4300 4400 60 0000 C CNN - 1 4300 4400 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q13 -U 1 1 5CE44419 -P 4600 4800 -F 0 "Q13" H 4500 4850 50 0000 R CNN -F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN -F 2 "" H 4800 4900 29 0000 C CNN -F 3 "" H 4600 4800 60 0000 C CNN - 1 4600 4800 - 1 0 0 -1 -$EndComp -$Comp -L R R13 -U 1 1 5CE444B9 -P 4400 5050 -F 0 "R13" V 4480 5050 50 0000 C CNN -F 1 "6k" V 4400 5050 50 0000 C CNN -F 2 "" V 4330 5050 50 0001 C CNN -F 3 "" H 4400 5050 50 0001 C CNN - 1 4400 5050 - 1 0 0 -1 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5CE4451D -P 4050 4150 -F 0 "C1" H 4075 4250 50 0000 L CNN -F 1 "30p" H 4075 4050 50 0000 L CNN -F 2 "" H 4088 4000 30 0000 C CNN -F 3 "" H 4050 4150 60 0000 C CNN - 1 4050 4150 - 0 1 1 0 -$EndComp -Wire Wire Line - 4100 4400 3750 4400 -Connection ~ 3750 4400 -Wire Wire Line - 3900 4150 3750 4150 -Connection ~ 3750 4150 -Wire Wire Line - 4700 4150 4200 4150 -Wire Wire Line - 4400 4150 4400 4200 -Wire Wire Line - 4400 4600 4400 4900 -Connection ~ 4400 4800 -Wire Wire Line - 4400 5200 4400 5300 -Wire Wire Line - 3650 5300 6400 5300 -Wire Wire Line - 3650 5300 3650 5250 -Connection ~ 3650 5250 -Wire Wire Line - 4700 5300 4700 5000 -Connection ~ 4400 5300 -Wire Wire Line - 4700 3800 4700 4600 -Connection ~ 4400 4150 -$Comp -L R R14 -U 1 1 5CE44FFF -P 4700 3650 -F 0 "R14" V 4780 3650 50 0000 C CNN -F 1 "6k" V 4700 3650 50 0000 C CNN -F 2 "" V 4630 3650 50 0001 C CNN -F 3 "" H 4700 3650 50 0001 C CNN - 1 4700 3650 - 1 0 0 -1 -$EndComp -Connection ~ 4700 4150 -$Comp -L eSim_PNP-RESCUE-LM7812 Q14 -U 1 1 5CE45652 -P 5050 3950 -F 0 "Q14" H 4950 4000 50 0000 R CNN -F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN -F 2 "" H 5250 4050 29 0000 C CNN -F 3 "" H 5050 3950 60 0000 C CNN - 1 5050 3950 - 1 0 0 1 -$EndComp -Wire Wire Line - 4850 3950 4700 3950 -Connection ~ 4700 3950 -Wire Wire Line - 4700 3500 4700 3450 -Wire Wire Line - 4700 3450 5150 3450 -Wire Wire Line - 5150 3450 5150 3750 -Wire Wire Line - 5150 5300 5150 4150 -Connection ~ 4700 5300 -Wire Wire Line - 4750 3450 4750 1950 -Wire Wire Line - 4200 1950 5300 1950 -Connection ~ 4200 1950 -Connection ~ 4750 3450 -$Comp -L eSim_NPN-RESCUE-LM7812 Q15 -U 1 1 5CE463AD -P 5400 2150 -F 0 "Q15" H 5300 2200 50 0000 R CNN -F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN -F 2 "" H 5600 2250 29 0000 C CNN -F 3 "" H 5400 2150 60 0000 C CNN - 1 5400 2150 - -1 0 0 -1 -$EndComp -Connection ~ 4750 1950 -Wire Wire Line - 4150 2750 4150 2600 -Wire Wire Line - 4150 2600 6100 2600 -Wire Wire Line - 5300 2600 5300 2350 -Connection ~ 4150 2750 -$Comp -L R R17 -U 1 1 5CE46DDE -P 6050 4250 -F 0 "R17" V 6130 4250 50 0000 C CNN -F 1 "5k" V 6050 4250 50 0000 C CNN -F 2 "" V 5980 4250 50 0001 C CNN -F 3 "" H 6050 4250 50 0001 C CNN - 1 6050 4250 - 1 0 0 -1 -$EndComp -$Comp -L R R16 -U 1 1 5CE46F8E -P 6050 3050 -F 0 "R16" V 6130 3050 50 0000 C CNN -F 1 "10.38k" V 6050 3050 50 0000 C CNN -F 2 "" V 5980 3050 50 0001 C CNN -F 3 "" H 6050 3050 50 0001 C CNN - 1 6050 3050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6050 3200 6050 4100 -Wire Wire Line - 6050 5300 6050 4400 -Connection ~ 5150 5300 -Wire Wire Line - 6050 2600 6050 2900 -Connection ~ 5300 2600 -Wire Wire Line - 4550 3000 5100 3000 -Wire Wire Line - 5100 3000 5100 3250 -Wire Wire Line - 5100 3250 5350 3250 -Wire Wire Line - 5350 3250 5350 3600 -Wire Wire Line - 5350 3600 6050 3600 -Connection ~ 6050 3600 -Wire Wire Line - 1650 1050 1650 1300 -Connection ~ 1650 1300 -Connection ~ 3350 1050 -$Comp -L R R15 -U 1 1 5CE47F7A -P 5850 1300 -F 0 "R15" V 5930 1300 50 0000 C CNN -F 1 "10k" V 5850 1300 50 0000 C CNN -F 2 "" V 5780 1300 50 0001 C CNN -F 3 "" H 5850 1300 50 0001 C CNN - 1 5850 1300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5850 1050 5850 1150 -Connection ~ 4200 1050 -$Comp -L zener U2 -U 1 1 5CE48686 -P 5850 1900 -F 0 "U2" H 5800 1800 60 0000 C CNN -F 1 "zener" H 5850 2000 60 0000 C CNN -F 2 "" H 5900 1900 60 0000 C CNN -F 3 "" H 5900 1900 60 0000 C CNN - 1 5850 1900 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 5850 1450 5850 1600 -Wire Wire Line - 5850 2100 5850 2250 -Wire Wire Line - 5850 2150 5600 2150 -$Comp -L eSim_NPN-RESCUE-LM7812 Q16 -U 1 1 5CE4907A -P 6550 1600 -F 0 "Q16" H 6450 1650 50 0000 R CNN -F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN -F 2 "" H 6750 1700 29 0000 C CNN -F 3 "" H 6550 1600 60 0000 C CNN - 1 6550 1600 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN-RESCUE-LM7812 Q17 -U 1 1 5CE4942E -P 7300 1950 -F 0 "Q17" H 7200 2000 50 0000 R CNN -F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN -F 2 "" H 7500 2050 29 0000 C CNN -F 3 "" H 7300 1950 60 0000 C CNN - 1 7300 1950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6650 1800 6650 2300 -Wire Wire Line - 6650 1950 7100 1950 -Wire Wire Line - 7400 1050 7400 1750 -Connection ~ 5850 1050 -Wire Wire Line - 6650 1400 6650 1050 -Connection ~ 6650 1050 -$Comp -L R R18 -U 1 1 5CE498BA -P 6650 2450 -F 0 "R18" V 6730 2450 50 0000 C CNN -F 1 "200" V 6650 2450 50 0000 C CNN -F 2 "" V 6580 2450 50 0001 C CNN -F 3 "" H 6650 2450 50 0001 C CNN - 1 6650 2450 - 1 0 0 -1 -$EndComp -$Comp -L R R20 -U 1 1 5CE4999A -P 7400 2450 -F 0 "R20" V 7480 2450 50 0000 C CNN -F 1 "0.3" V 7400 2450 50 0000 C CNN -F 2 "" V 7330 2450 50 0001 C CNN -F 3 "" H 7400 2450 50 0001 C CNN - 1 7400 2450 - 1 0 0 -1 -$EndComp -$Comp -L R R19 -U 1 1 5CE49AF5 -P 7000 2250 -F 0 "R19" V 7080 2250 50 0000 C CNN -F 1 "240" V 7000 2250 50 0000 C CNN -F 2 "" V 6930 2250 50 0001 C CNN -F 3 "" H 7000 2250 50 0001 C CNN - 1 7000 2250 - 0 1 1 0 -$EndComp -Connection ~ 6650 1950 -Wire Wire Line - 5850 2250 6850 2250 -Connection ~ 5850 2150 -Wire Wire Line - 7400 2150 7400 2300 -Wire Wire Line - 7150 2250 7400 2250 -Connection ~ 7400 2250 -Wire Wire Line - 6100 2600 6100 2650 -Wire Wire Line - 6100 2650 7400 2650 -Wire Wire Line - 7400 2650 7400 2600 -Connection ~ 6050 2600 -Wire Wire Line - 6650 2600 6650 2650 -Connection ~ 6650 2650 -$Comp -L PORT U3 -U 1 1 5CE4AAF6 -P 8050 1050 -F 0 "U3" H 8100 1150 30 0000 C CNN -F 1 "PORT" H 8050 1050 30 0000 C CNN -F 2 "" H 8050 1050 60 0000 C CNN -F 3 "" H 8050 1050 60 0000 C CNN - 1 8050 1050 - -1 0 0 1 -$EndComp -Connection ~ 7400 1050 -$Comp -L PORT U3 -U 3 1 5CE4B13E -P 7700 3000 -F 0 "U3" H 7750 3100 30 0000 C CNN -F 1 "PORT" H 7700 3000 30 0000 C CNN -F 2 "" H 7700 3000 60 0000 C CNN -F 3 "" H 7700 3000 60 0000 C CNN - 3 7700 3000 - -1 0 0 1 -$EndComp -$Comp -L PORT U3 -U 2 1 5CE4B701 -P 6650 5300 -F 0 "U3" H 6700 5400 30 0000 C CNN -F 1 "PORT" H 6650 5300 30 0000 C CNN -F 2 "" H 6650 5300 60 0000 C CNN -F 3 "" H 6650 5300 60 0000 C CNN - 2 6650 5300 - -1 0 0 1 -$EndComp -Connection ~ 6050 5300 -Wire Wire Line - 6350 1600 5950 1600 -Wire Wire Line - 5950 1600 5950 1550 -Wire Wire Line - 5950 1550 5000 1550 -Wire Wire Line - 5000 1550 5000 1950 -Connection ~ 5000 1950 -Wire Wire Line - 7300 2650 7300 3000 -Wire Wire Line - 7300 3000 7450 3000 -Connection ~ 7300 2650 -Connection ~ 2500 5200 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/LM7812/LM7812.sub b/src/SubcircuitLibrary/LM7812/LM7812.sub deleted file mode 100644 index 0dd95154..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812.sub +++ /dev/null @@ -1,54 +0,0 @@ -* Subcircuit LM7812 -.subckt LM7812 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/lm7812/lm7812.cir -.include PNP.lib -.include NPN.lib -r1 net-_q16-pad1_ net-_q1-pad2_ 100k -r2 net-_q16-pad1_ net-_q1-pad1_ 500 -r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k -r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k -* u1 net-_q10-pad3_ net-_q1-pad2_ zener -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -r5 net-_q10-pad2_ net-_q10-pad3_ 500 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 -r6 net-_q2-pad3_ net-_q3-pad1_ 1k -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 -r7 net-_q3-pad2_ net-_q10-pad3_ 6k -q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 -r10 net-_q6-pad3_ net-_q10-pad3_ 1k -q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 -q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 -q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 -r12 net-_q12-pad3_ net-_q2-pad3_ 6k -r9 net-_q2-pad3_ net-_c1-pad2_ 20k -q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A -q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A -r8 net-_q16-pad1_ net-_q5-pad3_ 100 -r11 net-_q16-pad1_ net-_q9-pad3_ 50 -q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 -q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 -q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 -r13 net-_q11-pad3_ net-_q10-pad3_ 6k -c1 net-_c1-pad1_ net-_c1-pad2_ 30p -r14 net-_q10-pad1_ net-_c1-pad1_ 6k -q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A -q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 -r17 net-_q12-pad2_ net-_q10-pad3_ 5k -r16 net-_q12-pad1_ net-_q12-pad2_ 10.38k -r15 net-_q16-pad1_ net-_r15-pad2_ 10k -* u2 net-_q15-pad2_ net-_r15-pad2_ zener -q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 -q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 -r18 net-_q16-pad3_ net-_q12-pad1_ 200 -r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 -r19 net-_q17-pad3_ net-_q15-pad2_ 240 -a1 net-_q10-pad3_ net-_q1-pad2_ u1 -a2 net-_q15-pad2_ net-_r15-pad2_ u2 -* Schematic Name: zener, NgSpice Name: zener -.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -* Schematic Name: zener, NgSpice Name: zener -.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -* Control Statements - -.ends LM7812
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml b/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml deleted file mode 100644 index 263f360c..00000000 --- a/src/SubcircuitLibrary/LM7812/LM7812_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/NPN.lib b/src/SubcircuitLibrary/LM7812/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/LM7812/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/PNP.lib b/src/SubcircuitLibrary/LM7812/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/LM7812/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/LM7812/Q_PNP.lib b/src/SubcircuitLibrary/LM7812/Q_PNP.lib deleted file mode 100644 index 154ed2d8..00000000 --- a/src/SubcircuitLibrary/LM7812/Q_PNP.lib +++ /dev/null @@ -1 +0,0 @@ -.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LM7812/analysis b/src/SubcircuitLibrary/LM7812/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/LM7812/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib deleted file mode 100644 index 34588988..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER-cache.lib +++ /dev/null @@ -1,82 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 8 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_xor
-#
-DEF d_xor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_xor" 50 100 47 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 150 -50 -200 -50 N
-P 2 0 1 0 150 150 -200 150 N
-X IN1 1 -450 100 215 R 50 43 1 1 I
-X IN2 2 -450 0 215 R 50 43 1 1 I
-X OUT 3 450 50 200 L 50 39 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir deleted file mode 100644 index ec177d39..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir +++ /dev/null @@ -1,16 +0,0 @@ -* C:\eSim\eSim\src\SubcircuitLibrary\LOGIC_ADDER\LOGIC_ADDER.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 3/24/2018 7:23:20 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 A B Net-_U2-Pad3_ d_and
-U4 Net-_U3-Pad3_ CIN Net-_U4-Pad3_ d_and
-U3 A B Net-_U3-Pad3_ d_xor
-U5 Net-_U3-Pad3_ CIN SUM d_xor
-U6 Net-_U2-Pad3_ Net-_U4-Pad3_ CARRY d_or
-U1 A B CIN SUM CARRY PORT
-
-.end
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out deleted file mode 100644 index df9bcde6..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.cir.out +++ /dev/null @@ -1,32 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-
-* u2 a b net-_u2-pad3_ d_and
-* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3 a b net-_u3-pad3_ d_xor
-* u5 net-_u3-pad3_ cin sum d_xor
-* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
-* u1 a b cin sum carry port
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro deleted file mode 100644 index a2b9fa1f..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=Sat Jun 8 13:01:54 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName2=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName3=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName4=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName5=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName6=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_PSpice -LibName7=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName8=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName9=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName10=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName11=/home/mallikarjuna/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch deleted file mode 100644 index d39a1b78..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sch +++ /dev/null @@ -1,245 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:LOGIC_ADDER-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5AB647D1
-P 4100 2200
-F 0 "U2" H 4100 2200 60 0000 C CNN
-F 1 "d_and" H 4150 2300 60 0000 C CNN
-F 2 "" H 4100 2200 60 0000 C CNN
-F 3 "" H 4100 2200 60 0000 C CNN
- 1 4100 2200
- 1 0 0 -1
-$EndComp
-$Comp
-L d_and U4
-U 1 1 5AB648AD
-P 5250 2300
-F 0 "U4" H 5250 2300 60 0000 C CNN
-F 1 "d_and" H 5300 2400 60 0000 C CNN
-F 2 "" H 5250 2300 60 0000 C CNN
-F 3 "" H 5250 2300 60 0000 C CNN
- 1 5250 2300
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U3
-U 1 1 5AB648E7
-P 4100 2750
-F 0 "U3" H 4100 2750 60 0000 C CNN
-F 1 "d_xor" H 4150 2850 47 0000 C CNN
-F 2 "" H 4100 2750 60 0000 C CNN
-F 3 "" H 4100 2750 60 0000 C CNN
- 1 4100 2750
- 1 0 0 -1
-$EndComp
-$Comp
-L d_xor U5
-U 1 1 5AB6498F
-P 5250 2600
-F 0 "U5" H 5250 2600 60 0000 C CNN
-F 1 "d_xor" H 5300 2700 47 0000 C CNN
-F 2 "" H 5250 2600 60 0000 C CNN
-F 3 "" H 5250 2600 60 0000 C CNN
- 1 5250 2600
- 1 0 0 -1
-$EndComp
-$Comp
-L d_or U6
-U 1 1 5AB64A11
-P 6250 2250
-F 0 "U6" H 6250 2250 60 0000 C CNN
-F 1 "d_or" H 6250 2350 60 0000 C CNN
-F 2 "" H 6250 2250 60 0000 C CNN
-F 3 "" H 6250 2250 60 0000 C CNN
- 1 6250 2250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5AB64A78
-P 2650 2100
-F 0 "U1" H 2700 2200 30 0000 C CNN
-F 1 "PORT" H 2650 2100 30 0000 C CNN
-F 2 "" H 2650 2100 60 0000 C CNN
-F 3 "" H 2650 2100 60 0000 C CNN
- 1 2650 2100
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5AB64BE9
-P 2650 2300
-F 0 "U1" H 2700 2400 30 0000 C CNN
-F 1 "PORT" H 2650 2300 30 0000 C CNN
-F 2 "" H 2650 2300 60 0000 C CNN
-F 3 "" H 2650 2300 60 0000 C CNN
- 2 2650 2300
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5AB64C18
-P 6300 2550
-F 0 "U1" H 6350 2650 30 0000 C CNN
-F 1 "PORT" H 6300 2550 30 0000 C CNN
-F 2 "" H 6300 2550 60 0000 C CNN
-F 3 "" H 6300 2550 60 0000 C CNN
- 4 6300 2550
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5AB64C59
-P 2650 2900
-F 0 "U1" H 2700 3000 30 0000 C CNN
-F 1 "PORT" H 2650 2900 30 0000 C CNN
-F 2 "" H 2650 2900 60 0000 C CNN
-F 3 "" H 2650 2900 60 0000 C CNN
- 3 2650 2900
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5AB64C94
-P 7150 2200
-F 0 "U1" H 7200 2300 30 0000 C CNN
-F 1 "PORT" H 7150 2200 30 0000 C CNN
-F 2 "" H 7150 2200 60 0000 C CNN
-F 3 "" H 7150 2200 60 0000 C CNN
- 5 7150 2200
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 2900 2100 3650 2100
-Wire Wire Line
- 2900 2250 3650 2250
-Wire Wire Line
- 3650 2250 3650 2200
-Wire Wire Line
- 3400 2100 3400 2650
-Wire Wire Line
- 3400 2650 3650 2650
-Connection ~ 3400 2100
-Wire Wire Line
- 3150 2250 3150 2750
-Wire Wire Line
- 3150 2750 3650 2750
-Connection ~ 3150 2250
-Wire Wire Line
- 4550 2700 4550 2500
-Wire Wire Line
- 4550 2500 4800 2500
-Wire Wire Line
- 2900 2900 4800 2900
-Wire Wire Line
- 4800 2900 4800 2600
-Wire Wire Line
- 4700 2500 4700 2200
-Wire Wire Line
- 4700 2200 4800 2200
-Connection ~ 4700 2500
-Wire Wire Line
- 4800 2300 4600 2300
-Wire Wire Line
- 4600 2300 4600 2900
-Connection ~ 4600 2900
-Wire Wire Line
- 5700 2250 5800 2250
-Wire Wire Line
- 4550 2150 4550 2000
-Wire Wire Line
- 4550 2000 5800 2000
-Wire Wire Line
- 5800 2000 5800 2150
-Wire Wire Line
- 5700 2550 6050 2550
-Wire Wire Line
- 6700 2200 6900 2200
-Wire Wire Line
- 2900 2250 2900 2300
-Text GLabel 3000 1850 0 60 Input ~ 0
-A
-Text GLabel 3000 2500 0 60 Input ~ 0
-B
-Text GLabel 3000 3250 0 60 Input ~ 0
-CIN
-Wire Wire Line
- 3000 3250 3050 3250
-Wire Wire Line
- 3050 3250 3050 2900
-Connection ~ 3050 2900
-Wire Wire Line
- 3000 1850 3100 1850
-Wire Wire Line
- 3100 1850 3100 2100
-Connection ~ 3100 2100
-Wire Wire Line
- 3000 2500 3000 2250
-Connection ~ 3000 2250
-Text GLabel 6750 1700 0 60 Output ~ 0
-CARRY
-Text GLabel 5950 2800 0 60 Output ~ 0
-SUM
-Wire Wire Line
- 6750 1700 6800 1700
-Wire Wire Line
- 6800 1700 6800 2200
-Connection ~ 6800 2200
-Wire Wire Line
- 5950 2550 5950 2800
-Connection ~ 5950 2550
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub deleted file mode 100644 index a1e1cfac..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER.sub +++ /dev/null @@ -1,26 +0,0 @@ -* Subcircuit LOGIC_ADDER
-.subckt LOGIC_ADDER a b cin sum carry
-* c:\esim\esim\src\subcircuitlibrary\logic_adder\logic_adder.cir
-* u2 a b net-_u2-pad3_ d_and
-* u4 net-_u3-pad3_ cin net-_u4-pad3_ d_and
-* u3 a b net-_u3-pad3_ d_xor
-* u5 net-_u3-pad3_ cin sum d_xor
-* u6 net-_u2-pad3_ net-_u4-pad3_ carry d_or
-a1 [a b ] net-_u2-pad3_ u2
-a2 [net-_u3-pad3_ cin ] net-_u4-pad3_ u4
-a3 [a b ] net-_u3-pad3_ u3
-a4 [net-_u3-pad3_ cin ] sum u5
-a5 [net-_u2-pad3_ net-_u4-pad3_ ] carry u6
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_xor, NgSpice Name: d_xor
-.model u5 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends LOGIC_ADDER
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml b/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml deleted file mode 100644 index ab59f216..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/LOGIC_ADDER_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_xor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u3><u5 name="type">d_xor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/LOGIC_ADDER/analysis b/src/SubcircuitLibrary/LOGIC_ADDER/analysis deleted file mode 100644 index d5e13546..00000000 --- a/src/SubcircuitLibrary/LOGIC_ADDER/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/NE566/NE566-cache.lib b/src/SubcircuitLibrary/NE566/NE566-cache.lib deleted file mode 100644 index db4e06a4..00000000 --- a/src/SubcircuitLibrary/NE566/NE566-cache.lib +++ /dev/null @@ -1,125 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 I
-X ~ 2 250 0 100 L 30 30 2 1 I
-X ~ 3 250 0 100 L 30 30 3 1 I
-X ~ 4 250 0 100 L 30 30 4 1 I
-X ~ 5 250 0 100 L 30 30 5 1 I
-X ~ 6 250 0 100 L 30 30 6 1 I
-X ~ 7 250 0 100 L 30 30 7 1 I
-X ~ 8 250 0 100 L 30 30 8 1 I
-X ~ 9 250 0 100 L 30 30 9 1 I
-X ~ 10 250 0 100 L 30 30 10 1 I
-X ~ 11 250 0 100 L 30 30 11 1 I
-X ~ 12 250 0 100 L 30 30 12 1 I
-X ~ 13 250 0 100 L 30 30 13 1 I
-X ~ 14 250 0 100 L 30 30 14 1 I
-X ~ 15 250 0 100 L 30 30 15 1 I
-X ~ 16 250 0 100 L 30 30 16 1 I
-X ~ 17 250 0 100 L 30 30 17 1 I
-X ~ 18 250 0 100 L 30 30 18 1 I
-X ~ 19 250 0 100 L 30 30 19 1 I
-X ~ 20 250 0 100 L 30 30 20 1 I
-X ~ 21 250 0 100 L 30 30 21 1 I
-X ~ 22 250 0 100 L 30 30 22 1 I
-X ~ 23 250 0 100 L 30 30 23 1 I
-X ~ 24 250 0 100 L 30 30 24 1 I
-X ~ 25 250 0 100 L 30 30 25 1 I
-X ~ 26 250 0 100 L 30 30 26 1 I
-ENDDRAW
-ENDDEF
-#
-# eSim_Diode
-#
-DEF eSim_Diode D 0 40 N N 1 F N
-F0 "D" 0 100 50 H V C CNN
-F1 "eSim_Diode" 0 -100 50 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- TO-???*
- *SingleDiode
- *_Diode_*
- *SingleDiode*
- D_*
-$ENDFPLIST
-DRAW
-T 0 -100 50 60 0 0 0 A Normal 0 C C
-T 0 100 50 60 0 0 0 K Normal 0 C C
-P 2 0 1 6 50 50 50 -50 N
-P 3 0 1 0 -50 50 50 0 -50 -50 F
-X A 1 -150 0 100 R 40 40 1 1 P
-X K 2 150 0 100 L 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 C
-X B 2 -200 0 225 R 50 50 1 1 I
-X E 3 100 -200 100 U 50 50 1 1 E
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/src/SubcircuitLibrary/NE566/NE566.cir b/src/SubcircuitLibrary/NE566/NE566.cir deleted file mode 100644 index 4d52179b..00000000 --- a/src/SubcircuitLibrary/NE566/NE566.cir +++ /dev/null @@ -1,57 +0,0 @@ -* C:\esim_1\eSim\src\SubcircuitLibrary\NE566\NE566.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/31/19 13:55:47
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q1 Net-_Q1-Pad1_ Net-_D10-Pad2_ Net-_D10-Pad1_ eSim_NPN
-Q2 Net-_D10-Pad1_ Net-_Q2-Pad2_ Net-_D1-Pad1_ eSim_NPN
-Q5 Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_D1-Pad1_ eSim_NPN
-D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
-D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode
-Q6 Net-_D3-Pad2_ Net-_D1-Pad2_ Net-_Q3-Pad2_ eSim_NPN
-Q8 Net-_D9-Pad2_ Net-_D3-Pad2_ Net-_D5-Pad1_ eSim_NPN
-Q7 Net-_Q3-Pad2_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN
-Q3 Net-_D1-Pad2_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
-R1 Net-_Q3-Pad3_ Net-_D4-Pad2_ 5k
-R3 Net-_Q7-Pad3_ Net-_D4-Pad2_ 5k
-D4 Net-_D2-Pad1_ Net-_D4-Pad2_ eSim_Diode
-Q4 Net-_D4-Pad2_ Net-_D2-Pad2_ Net-_Q15-Pad1_ eSim_NPN
-D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode
-R2 Net-_D2-Pad2_ Net-_Q15-Pad1_ 5k
-R4 Net-_Q9-Pad3_ Net-_Q15-Pad1_ 5k
-Q10 Net-_D9-Pad2_ Net-_D5-Pad1_ Net-_Q10-Pad3_ eSim_NPN
-Q9 Net-_D5-Pad1_ Net-_Q11-Pad2_ Net-_Q9-Pad3_ eSim_NPN
-Q11 Net-_Q10-Pad3_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
-D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
-D6 Net-_D5-Pad1_ Net-_D6-Pad2_ eSim_Diode
-Q12 Net-_D5-Pad2_ Net-_D6-Pad2_ Net-_Q12-Pad3_ eSim_NPN
-D8 Net-_D5-Pad2_ Net-_D8-Pad2_ eSim_Diode
-D7 Net-_D5-Pad2_ Net-_D7-Pad2_ eSim_Diode
-R6 Net-_D9-Pad2_ Net-_D5-Pad2_ 5k
-R8 Net-_D9-Pad2_ Net-_D8-Pad2_ 5k
-Q14 Net-_D9-Pad2_ Net-_D8-Pad2_ Net-_Q14-Pad3_ eSim_NPN
-Q13 Net-_D8-Pad2_ Net-_D7-Pad2_ Net-_Q12-Pad3_ eSim_NPN
-R7 Net-_D7-Pad2_ Net-_Q12-Pad3_ 5k
-Q15 Net-_Q15-Pad1_ Net-_Q14-Pad3_ Net-_Q15-Pad3_ eSim_PNP
-Q16 Net-_Q15-Pad3_ Net-_Q16-Pad2_ Net-_D2-Pad1_ eSim_PNP
-Q17 Net-_Q16-Pad2_ Net-_D9-Pad1_ Net-_Q15-Pad3_ eSim_PNP
-R13 Net-_D9-Pad2_ Net-_D9-Pad1_ 5k
-D9 Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode
-R15 Net-_D9-Pad2_ Net-_Q11-Pad2_ 5k
-R12 Net-_Q16-Pad2_ Net-_D2-Pad1_ 5k
-R5 Net-_Q11-Pad3_ Net-_Q15-Pad1_ 5k
-R9 Net-_Q12-Pad3_ Net-_Q15-Pad1_ 5k
-R10 Net-_Q14-Pad3_ Net-_Q15-Pad1_ 5k
-Q18 Net-_D9-Pad1_ Net-_Q11-Pad2_ Net-_Q18-Pad3_ eSim_NPN
-Q19 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_Q19-Pad3_ eSim_NPN
-R14 Net-_Q18-Pad3_ Net-_Q15-Pad1_ 5k
-R16 Net-_Q19-Pad3_ Net-_Q15-Pad1_ 5k
-U1 Net-_Q15-Pad1_ Net-_Q14-Pad3_ Net-_Q10-Pad3_ Net-_D10-Pad2_ Net-_Q1-Pad1_ Net-_D3-Pad2_ Net-_D9-Pad2_ PORT
-R11 Net-_D9-Pad2_ Net-_Q15-Pad3_ 5k
-D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode
-Q20 Net-_Q2-Pad2_ Net-_D10-Pad1_ Net-_Q1-Pad1_ eSim_PNP
-
-.end
diff --git a/src/SubcircuitLibrary/NE566/NE566.cir.out b/src/SubcircuitLibrary/NE566/NE566.cir.out deleted file mode 100644 index c83f8b00..00000000 --- a/src/SubcircuitLibrary/NE566/NE566.cir.out +++ /dev/null @@ -1,61 +0,0 @@ -* c:\esim_1\esim\src\subcircuitlibrary\ne566\ne566.cir
-
-.include PNP.lib
-.include D.lib
-.include NPN.lib
-q1 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2222
-q2 net-_d10-pad1_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-q5 net-_q2-pad2_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
-d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
-q6 net-_d3-pad2_ net-_d1-pad2_ net-_q3-pad2_ Q2N2222
-q8 net-_d9-pad2_ net-_d3-pad2_ net-_d5-pad1_ Q2N2222
-q7 net-_q3-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q3 net-_d1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
-r1 net-_q3-pad3_ net-_d4-pad2_ 5k
-r3 net-_q7-pad3_ net-_d4-pad2_ 5k
-d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
-q4 net-_d4-pad2_ net-_d2-pad2_ net-_q15-pad1_ Q2N2222
-d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
-r2 net-_d2-pad2_ net-_q15-pad1_ 5k
-r4 net-_q9-pad3_ net-_q15-pad1_ 5k
-q10 net-_d9-pad2_ net-_d5-pad1_ net-_q10-pad3_ Q2N2222
-q9 net-_d5-pad1_ net-_q11-pad2_ net-_q9-pad3_ Q2N2222
-q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
-d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
-d6 net-_d5-pad1_ net-_d6-pad2_ 1N4148
-q12 net-_d5-pad2_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
-d8 net-_d5-pad2_ net-_d8-pad2_ 1N4148
-d7 net-_d5-pad2_ net-_d7-pad2_ 1N4148
-r6 net-_d9-pad2_ net-_d5-pad2_ 5k
-r8 net-_d9-pad2_ net-_d8-pad2_ 5k
-q14 net-_d9-pad2_ net-_d8-pad2_ net-_q14-pad3_ Q2N2222
-q13 net-_d8-pad2_ net-_d7-pad2_ net-_q12-pad3_ Q2N2222
-r7 net-_d7-pad2_ net-_q12-pad3_ 5k
-q15 net-_q15-pad1_ net-_q14-pad3_ net-_q15-pad3_ Q2N2907A
-q16 net-_q15-pad3_ net-_q16-pad2_ net-_d2-pad1_ Q2N2222
-q17 net-_q16-pad2_ net-_d9-pad1_ net-_q15-pad3_ Q2N2222
-r13 net-_d9-pad2_ net-_d9-pad1_ 5k
-d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
-r15 net-_d9-pad2_ net-_q11-pad2_ 5k
-r12 net-_q16-pad2_ net-_d2-pad1_ 5k
-r5 net-_q11-pad3_ net-_q15-pad1_ 5k
-r9 net-_q12-pad3_ net-_q15-pad1_ 5k
-r10 net-_q14-pad3_ net-_q15-pad1_ 5k
-q18 net-_d9-pad1_ net-_q11-pad2_ net-_q18-pad3_ Q2N2222
-q19 net-_q11-pad2_ net-_q11-pad2_ net-_q19-pad3_ Q2N2222
-r14 net-_q18-pad3_ net-_q15-pad1_ 5k
-r16 net-_q19-pad3_ net-_q15-pad1_ 5k
-* u1 net-_q15-pad1_ net-_q14-pad3_ net-_q10-pad3_ net-_d10-pad2_ net-_q1-pad1_ net-_d3-pad2_ net-_d9-pad2_ port
-r11 net-_d9-pad2_ net-_q15-pad3_ 5k
-d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
-q20 net-_q2-pad2_ net-_d10-pad1_ net-_q1-pad1_ Q2N2222
-.tran 10e-03 100e-03 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/NE566/NE566.pro b/src/SubcircuitLibrary/NE566/NE566.pro deleted file mode 100644 index 4b1e556f..00000000 --- a/src/SubcircuitLibrary/NE566/NE566.pro +++ /dev/null @@ -1,83 +0,0 @@ -update=03/31/19 14:14:07
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../../../Users/hp/AppData/Roaming/SPB_Data/eSim-Workspace/Function_generator_using_NE566
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=microcontrollers
-LibName13=dsp
-LibName14=microchip
-LibName15=analog_switches
-LibName16=motorola
-LibName17=texas
-LibName18=intel
-LibName19=audio
-LibName20=interface
-LibName21=digital-audio
-LibName22=philips
-LibName23=display
-LibName24=cypress
-LibName25=siliconi
-LibName26=opto
-LibName27=atmel
-LibName28=contrib
-LibName29=valves
-LibName30=eSim_Analog
-LibName31=eSim_Devices
-LibName32=eSim_Digital
-LibName33=eSim_Hybrid
-LibName34=eSim_Miscellaneous
-LibName35=eSim_Plot
-LibName36=eSim_Power
-LibName37=eSim_PSpice
-LibName38=eSim_Sources
-LibName39=eSim_Subckt
-LibName40=eSim_User
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=
-SpiceForceRefPrefix=0
-SpiceUseNetNumbers=0
-LabSize=60
diff --git a/src/SubcircuitLibrary/NE566/NE566.sch b/src/SubcircuitLibrary/NE566/NE566.sch deleted file mode 100644 index f4c9144d..00000000 --- a/src/SubcircuitLibrary/NE566/NE566.sch +++ /dev/null @@ -1,920 +0,0 @@ -EESchema Schematic File Version 2
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-LIBS:NE566-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_NPN Q1
-U 1 1 5C9D1243
-P 1650 1650
-F 0 "Q1" H 1550 1700 50 0000 R CNN
-F 1 "eSim_NPN" H 1600 1800 50 0000 R CNN
-F 2 "" H 1850 1750 29 0000 C CNN
-F 3 "" H 1650 1650 60 0000 C CNN
- 1 1650 1650
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q2
-U 1 1 5C9D1262
-P 1850 2450
-F 0 "Q2" H 1750 2500 50 0000 R CNN
-F 1 "eSim_NPN" H 1800 2600 50 0000 R CNN
-F 2 "" H 2050 2550 29 0000 C CNN
-F 3 "" H 1850 2450 60 0000 C CNN
- 1 1850 2450
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q5
-U 1 1 5C9D1293
-P 2650 2450
-F 0 "Q5" H 2550 2500 50 0000 R CNN
-F 1 "eSim_NPN" H 2600 2600 50 0000 R CNN
-F 2 "" H 2850 2550 29 0000 C CNN
-F 3 "" H 2650 2450 60 0000 C CNN
- 1 2650 2450
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_Diode D1
-U 1 1 5C9D12F5
-P 1750 3150
-F 0 "D1" H 1750 3250 50 0000 C CNN
-F 1 "eSim_Diode" H 1750 3050 50 0000 C CNN
-F 2 "" H 1750 3150 60 0000 C CNN
-F 3 "" H 1750 3150 60 0000 C CNN
- 1 1750 3150
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_Diode D3
-U 1 1 5C9D136F
-P 2750 3150
-F 0 "D3" H 2750 3250 50 0000 C CNN
-F 1 "eSim_Diode" H 2750 3050 50 0000 C CNN
-F 2 "" H 2750 3150 60 0000 C CNN
-F 3 "" H 2750 3150 60 0000 C CNN
- 1 2750 3150
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q6
-U 1 1 5C9D13AA
-P 2650 4100
-F 0 "Q6" H 2550 4150 50 0000 R CNN
-F 1 "eSim_NPN" H 2600 4250 50 0000 R CNN
-F 2 "" H 2850 4200 29 0000 C CNN
-F 3 "" H 2650 4100 60 0000 C CNN
- 1 2650 4100
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q8
-U 1 1 5C9D13D9
-P 3550 3550
-F 0 "Q8" H 3450 3600 50 0000 R CNN
-F 1 "eSim_NPN" H 3500 3700 50 0000 R CNN
-F 2 "" H 3750 3650 29 0000 C CNN
-F 3 "" H 3550 3550 60 0000 C CNN
- 1 3550 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q7
-U 1 1 5C9D13FE
-P 2650 4900
-F 0 "Q7" H 2550 4950 50 0000 R CNN
-F 1 "eSim_NPN" H 2600 5050 50 0000 R CNN
-F 2 "" H 2850 5000 29 0000 C CNN
-F 3 "" H 2650 4900 60 0000 C CNN
- 1 2650 4900
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q3
-U 1 1 5C9D142B
-P 1850 4900
-F 0 "Q3" H 1750 4950 50 0000 R CNN
-F 1 "eSim_NPN" H 1800 5050 50 0000 R CNN
-F 2 "" H 2050 5000 29 0000 C CNN
-F 3 "" H 1850 4900 60 0000 C CNN
- 1 1850 4900
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R1
-U 1 1 5C9D148A
-P 1700 5550
-F 0 "R1" H 1750 5680 50 0000 C CNN
-F 1 "5k" H 1750 5600 50 0000 C CNN
-F 2 "" H 1750 5530 30 0000 C CNN
-F 3 "" V 1750 5600 30 0000 C CNN
- 1 1700 5550
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R3
-U 1 1 5C9D14C1
-P 2700 5500
-F 0 "R3" H 2750 5630 50 0000 C CNN
-F 1 "5k" H 2750 5550 50 0000 C CNN
-F 2 "" H 2750 5480 30 0000 C CNN
-F 3 "" V 2750 5550 30 0000 C CNN
- 1 2700 5500
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_Diode D4
-U 1 1 5C9D153A
-P 2750 6100
-F 0 "D4" H 2750 6200 50 0000 C CNN
-F 1 "eSim_Diode" H 2750 6000 50 0000 C CNN
-F 2 "" H 2750 6100 60 0000 C CNN
-F 3 "" H 2750 6100 60 0000 C CNN
- 1 2750 6100
- 0 -1 -1 0
-$EndComp
-$Comp
-L eSim_NPN Q4
-U 1 1 5C9D156F
-P 1850 6500
-F 0 "Q4" H 1750 6550 50 0000 R CNN
-F 1 "eSim_NPN" H 1800 6650 50 0000 R CNN
-F 2 "" H 2050 6600 29 0000 C CNN
-F 3 "" H 1850 6500 60 0000 C CNN
- 1 1850 6500
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_Diode D2
-U 1 1 5C9D15BE
-P 2500 6500
-F 0 "D2" H 2500 6600 50 0000 C CNN
-F 1 "eSim_Diode" H 2500 6400 50 0000 C CNN
-F 2 "" H 2500 6500 60 0000 C CNN
-F 3 "" H 2500 6500 60 0000 C CNN
- 1 2500 6500
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_R R2
-U 1 1 5C9D1601
-P 2150 6750
-F 0 "R2" H 2200 6880 50 0000 C CNN
-F 1 "5k" H 2200 6800 50 0000 C CNN
-F 2 "" H 2200 6730 30 0000 C CNN
-F 3 "" V 2200 6800 30 0000 C CNN
- 1 2150 6750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R4
-U 1 1 5C9D163C
-P 3600 6750
-F 0 "R4" H 3650 6880 50 0000 C CNN
-F 1 "5k" H 3650 6800 50 0000 C CNN
-F 2 "" H 3650 6730 30 0000 C CNN
-F 3 "" V 3650 6800 30 0000 C CNN
- 1 3600 6750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q10
-U 1 1 5C9D172D
-P 3850 4600
-F 0 "Q10" H 3750 4650 50 0000 R CNN
-F 1 "eSim_NPN" H 3800 4750 50 0000 R CNN
-F 2 "" H 4050 4700 29 0000 C CNN
-F 3 "" H 3850 4600 60 0000 C CNN
- 1 3850 4600
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q9
-U 1 1 5C9D17A2
-P 3750 5900
-F 0 "Q9" H 3650 5950 50 0000 R CNN
-F 1 "eSim_NPN" H 3700 6050 50 0000 R CNN
-F 2 "" H 3950 6000 29 0000 C CNN
-F 3 "" H 3750 5900 60 0000 C CNN
- 1 3750 5900
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q11
-U 1 1 5C9D17FB
-P 4600 5900
-F 0 "Q11" H 4500 5950 50 0000 R CNN
-F 1 "eSim_NPN" H 4550 6050 50 0000 R CNN
-F 2 "" H 4800 6000 29 0000 C CNN
-F 3 "" H 4600 5900 60 0000 C CNN
- 1 4600 5900
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_Diode D5
-U 1 1 5C9D183E
-P 4300 2950
-F 0 "D5" H 4300 3050 50 0000 C CNN
-F 1 "eSim_Diode" H 4300 2850 50 0000 C CNN
-F 2 "" H 4300 2950 60 0000 C CNN
-F 3 "" H 4300 2950 60 0000 C CNN
- 1 4300 2950
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_Diode D6
-U 1 1 5C9D18B3
-P 4300 3950
-F 0 "D6" H 4300 4050 50 0000 C CNN
-F 1 "eSim_Diode" H 4300 3850 50 0000 C CNN
-F 2 "" H 4300 3950 60 0000 C CNN
-F 3 "" H 4300 3950 60 0000 C CNN
- 1 4300 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q12
-U 1 1 5C9D1968
-P 4850 3950
-F 0 "Q12" H 4750 4000 50 0000 R CNN
-F 1 "eSim_NPN" H 4800 4100 50 0000 R CNN
-F 2 "" H 5050 4050 29 0000 C CNN
-F 3 "" H 4850 3950 60 0000 C CNN
- 1 4850 3950
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_Diode D8
-U 1 1 5C9D19B5
-P 5150 2350
-F 0 "D8" H 5150 2450 50 0000 C CNN
-F 1 "eSim_Diode" H 5150 2250 50 0000 C CNN
-F 2 "" H 5150 2350 60 0000 C CNN
-F 3 "" H 5150 2350 60 0000 C CNN
- 1 5150 2350
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_Diode D7
-U 1 1 5C9D1A10
-P 5200 3300
-F 0 "D7" H 5200 3400 50 0000 C CNN
-F 1 "eSim_Diode" H 5200 3200 50 0000 C CNN
-F 2 "" H 5200 3300 60 0000 C CNN
-F 3 "" H 5200 3300 60 0000 C CNN
- 1 5200 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R6
-U 1 1 5C9D1A5F
-P 4900 1250
-F 0 "R6" H 4950 1380 50 0000 C CNN
-F 1 "5k" H 4950 1300 50 0000 C CNN
-F 2 "" H 4950 1230 30 0000 C CNN
-F 3 "" V 4950 1300 30 0000 C CNN
- 1 4900 1250
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R8
-U 1 1 5C9D1ABE
-P 5900 1250
-F 0 "R8" H 5950 1380 50 0000 C CNN
-F 1 "5k" H 5950 1300 50 0000 C CNN
-F 2 "" H 5950 1230 30 0000 C CNN
-F 3 "" V 5950 1300 30 0000 C CNN
- 1 5900 1250
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q14
-U 1 1 5C9D1B3D
-P 6400 1850
-F 0 "Q14" H 6300 1900 50 0000 R CNN
-F 1 "eSim_NPN" H 6350 2000 50 0000 R CNN
-F 2 "" H 6600 1950 29 0000 C CNN
-F 3 "" H 6400 1850 60 0000 C CNN
- 1 6400 1850
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q13
-U 1 1 5C9D1C1E
-P 5850 3300
-F 0 "Q13" H 5750 3350 50 0000 R CNN
-F 1 "eSim_NPN" H 5800 3450 50 0000 R CNN
-F 2 "" H 6050 3400 29 0000 C CNN
-F 3 "" H 5850 3300 60 0000 C CNN
- 1 5850 3300
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R7
-U 1 1 5C9D1C7F
-P 5450 3550
-F 0 "R7" H 5500 3680 50 0000 C CNN
-F 1 "5k" H 5500 3600 50 0000 C CNN
-F 2 "" H 5500 3530 30 0000 C CNN
-F 3 "" V 5500 3600 30 0000 C CNN
- 1 5450 3550
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_PNP Q15
-U 1 1 5C9D1DA7
-P 7100 2750
-F 0 "Q15" H 7000 2800 50 0000 R CNN
-F 1 "eSim_PNP" H 7050 2900 50 0000 R CNN
-F 2 "" H 7300 2850 29 0000 C CNN
-F 3 "" H 7100 2750 60 0000 C CNN
- 1 7100 2750
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q16
-U 1 1 5C9D1E16
-P 8000 2750
-F 0 "Q16" H 7900 2800 50 0000 R CNN
-F 1 "eSim_PNP" H 7950 2900 50 0000 R CNN
-F 2 "" H 8200 2850 29 0000 C CNN
-F 3 "" H 8000 2750 60 0000 C CNN
- 1 8000 2750
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q17
-U 1 1 5C9D1EFF
-P 8650 2650
-F 0 "Q17" H 8550 2700 50 0000 R CNN
-F 1 "eSim_PNP" H 8600 2800 50 0000 R CNN
-F 2 "" H 8850 2750 29 0000 C CNN
-F 3 "" H 8650 2650 60 0000 C CNN
- 1 8650 2650
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_R R13
-U 1 1 5C9D1FB4
-P 9000 1400
-F 0 "R13" H 9050 1530 50 0000 C CNN
-F 1 "5k" H 9050 1450 50 0000 C CNN
-F 2 "" H 9050 1380 30 0000 C CNN
-F 3 "" V 9050 1450 30 0000 C CNN
- 1 9000 1400
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_Diode D9
-U 1 1 5C9D2065
-P 8500 1450
-F 0 "D9" H 8500 1550 50 0000 C CNN
-F 1 "eSim_Diode" H 8500 1350 50 0000 C CNN
-F 2 "" H 8500 1450 60 0000 C CNN
-F 3 "" H 8500 1450 60 0000 C CNN
- 1 8500 1450
- 0 -1 -1 0
-$EndComp
-$Comp
-L eSim_R R15
-U 1 1 5C9D20D8
-P 10450 1750
-F 0 "R15" H 10500 1880 50 0000 C CNN
-F 1 "5k" H 10500 1800 50 0000 C CNN
-F 2 "" H 10500 1730 30 0000 C CNN
-F 3 "" V 10500 1800 30 0000 C CNN
- 1 10450 1750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R12
-U 1 1 5C9D215D
-P 8500 4200
-F 0 "R12" H 8550 4330 50 0000 C CNN
-F 1 "5k" H 8550 4250 50 0000 C CNN
-F 2 "" H 8550 4180 30 0000 C CNN
-F 3 "" V 8550 4250 30 0000 C CNN
- 1 8500 4200
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R5
-U 1 1 5C9D2300
-P 4450 6750
-F 0 "R5" H 4500 6880 50 0000 C CNN
-F 1 "5k" H 4500 6800 50 0000 C CNN
-F 2 "" H 4500 6730 30 0000 C CNN
-F 3 "" V 4500 6800 30 0000 C CNN
- 1 4450 6750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R9
-U 1 1 5C9D2395
-P 5950 6750
-F 0 "R9" H 6000 6880 50 0000 C CNN
-F 1 "5k" H 6000 6800 50 0000 C CNN
-F 2 "" H 6000 6730 30 0000 C CNN
-F 3 "" V 6000 6800 30 0000 C CNN
- 1 5950 6750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R10
-U 1 1 5C9D242E
-P 6450 6750
-F 0 "R10" H 6500 6880 50 0000 C CNN
-F 1 "5k" H 6500 6800 50 0000 C CNN
-F 2 "" H 6500 6730 30 0000 C CNN
-F 3 "" V 6500 6800 30 0000 C CNN
- 1 6450 6750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_NPN Q18
-U 1 1 5C9D24BF
-P 9650 5900
-F 0 "Q18" H 9550 5950 50 0000 R CNN
-F 1 "eSim_NPN" H 9600 6050 50 0000 R CNN
-F 2 "" H 9850 6000 29 0000 C CNN
-F 3 "" H 9650 5900 60 0000 C CNN
- 1 9650 5900
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q19
-U 1 1 5C9D2540
-P 10350 5900
-F 0 "Q19" H 10250 5950 50 0000 R CNN
-F 1 "eSim_NPN" H 10300 6050 50 0000 R CNN
-F 2 "" H 10550 6000 29 0000 C CNN
-F 3 "" H 10350 5900 60 0000 C CNN
- 1 10350 5900
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_R R14
-U 1 1 5C9D25BD
-P 9500 6750
-F 0 "R14" H 9550 6880 50 0000 C CNN
-F 1 "5k" H 9550 6800 50 0000 C CNN
-F 2 "" H 9550 6730 30 0000 C CNN
-F 3 "" V 9550 6800 30 0000 C CNN
- 1 9500 6750
- 0 1 1 0
-$EndComp
-$Comp
-L eSim_R R16
-U 1 1 5C9D2650
-P 10450 6750
-F 0 "R16" H 10500 6880 50 0000 C CNN
-F 1 "5k" H 10500 6800 50 0000 C CNN
-F 2 "" H 10500 6730 30 0000 C CNN
-F 3 "" V 10500 6800 30 0000 C CNN
- 1 10450 6750
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D2BB3
-P 650 1650
-F 0 "U1" H 700 1750 30 0000 C CNN
-F 1 "PORT" H 650 1650 30 0000 C CNN
-F 2 "" H 650 1650 60 0000 C CNN
-F 3 "" H 650 1650 60 0000 C CNN
- 5 650 1650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 6 1 5C9D68D0
-P 2100 800
-F 0 "U1" H 2150 900 30 0000 C CNN
-F 1 "PORT" H 2100 800 30 0000 C CNN
-F 2 "" H 2100 800 60 0000 C CNN
-F 3 "" H 2100 800 60 0000 C CNN
- 6 2100 800
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_R R11
-U 1 1 5C9D8B9B
-P 7150 1350
-F 0 "R11" H 7200 1480 50 0000 C CNN
-F 1 "5k" H 7200 1400 50 0000 C CNN
-F 2 "" H 7200 1330 30 0000 C CNN
-F 3 "" V 7200 1400 30 0000 C CNN
- 1 7150 1350
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 8 1 5C9D98CB
-P 3650 550
-F 0 "U1" H 3700 650 30 0000 C CNN
-F 1 "PORT" H 3650 550 30 0000 C CNN
-F 2 "" H 3650 550 60 0000 C CNN
-F 3 "" H 3650 550 60 0000 C CNN
- 8 3650 550
- 0 1 1 0
-$EndComp
-$Comp
-L PORT U1
-U 7 1 5C9E5DF3
-P 3150 3950
-F 0 "U1" H 3200 4050 30 0000 C CNN
-F 1 "PORT" H 3150 3950 30 0000 C CNN
-F 2 "" H 3150 3950 60 0000 C CNN
-F 3 "" H 3150 3950 60 0000 C CNN
- 7 3150 3950
- 0 -1 -1 0
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9E625B
-P 4950 5150
-F 0 "U1" H 5000 5250 30 0000 C CNN
-F 1 "PORT" H 4950 5150 30 0000 C CNN
-F 2 "" H 4950 5150 60 0000 C CNN
-F 3 "" H 4950 5150 60 0000 C CNN
- 4 4950 5150
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9E6ECC
-P 6800 5100
-F 0 "U1" H 6850 5200 30 0000 C CNN
-F 1 "PORT" H 6800 5100 30 0000 C CNN
-F 2 "" H 6800 5100 60 0000 C CNN
-F 3 "" H 6800 5100 60 0000 C CNN
- 3 6800 5100
- -1 0 0 1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9E7FDD
-P 11100 7250
-F 0 "U1" H 11150 7350 30 0000 C CNN
-F 1 "PORT" H 11100 7250 30 0000 C CNN
-F 2 "" H 11100 7250 60 0000 C CNN
-F 3 "" H 11100 7250 60 0000 C CNN
- 1 11100 7250
- 0 -1 -1 0
-$EndComp
-Text Notes 500 1450 0 79 ~ 0
-Modulation Input\n
-Text Notes 2200 800 0 79 ~ 0
-R1(External)
-Text Notes 3300 5750 1 79 ~ 0
-C1(External)\n
-Text Notes 4500 5050 0 79 ~ 0
-Triangle Wave Output
-Text Notes 6500 5000 0 79 ~ 0
-Square Wave Output\n
-Text Notes 10950 7000 0 79 ~ 0
-GND\n
-Text Notes 3425 625 0 79 ~ 0
-V+\n
-$Comp
-L eSim_Diode D10
-U 1 1 5C9F4364
-P 1300 1850
-F 0 "D10" H 1300 1950 50 0000 C CNN
-F 1 "eSim_Diode" H 1300 1750 50 0000 C CNN
-F 2 "" H 1300 1850 60 0000 C CNN
-F 3 "" H 1300 1850 60 0000 C CNN
- 1 1300 1850
- 0 -1 -1 0
-$EndComp
-Text Notes 950 1650 0 79 ~ 0
-Vc\n
-Wire Wire Line
- 1750 1850 1750 2250
-Wire Wire Line
- 900 1650 1450 1650
-Wire Wire Line
- 2750 2000 2750 2250
-Wire Wire Line
- 2050 2450 2450 2450
-Wire Wire Line
- 2750 2200 2250 2200
-Wire Wire Line
- 2250 2200 2250 2450
-Connection ~ 2250 2450
-Connection ~ 2750 2200
-Wire Wire Line
- 2100 1800 2450 1800
-Wire Wire Line
- 2100 2000 2100 1800
-Wire Wire Line
- 1300 2000 2100 2000
-Connection ~ 1750 2000
-Wire Wire Line
- 2750 1450 1750 1450
-Wire Wire Line
- 2750 2650 2750 3000
-Wire Wire Line
- 1750 2650 1750 3000
-Wire Wire Line
- 2750 2850 1750 2850
-Connection ~ 1750 2850
-Connection ~ 2750 2850
-Wire Wire Line
- 2750 3300 2750 3900
-Wire Wire Line
- 2450 4100 1750 4100
-Wire Wire Line
- 1750 3300 1750 4700
-Connection ~ 1750 4100
-Wire Wire Line
- 2750 4300 2750 4700
-Wire Wire Line
- 2050 4900 2450 4900
-Wire Wire Line
- 2750 3550 3350 3550
-Connection ~ 2750 3550
-Wire Wire Line
- 2750 4500 2250 4500
-Wire Wire Line
- 2250 4500 2250 4900
-Connection ~ 2250 4900
-Connection ~ 2750 4500
-Wire Wire Line
- 2750 5100 2750 5400
-Wire Wire Line
- 2750 5700 2750 5950
-Wire Wire Line
- 1750 5100 1750 5450
-Wire Wire Line
- 1750 5750 1750 6300
-Wire Wire Line
- 1750 5900 2750 5900
-Connection ~ 2750 5900
-Connection ~ 1750 5900
-Wire Wire Line
- 2750 6250 2750 6500
-Wire Wire Line
- 2650 6500 8550 6500
-Wire Wire Line
- 1750 6700 1750 7000
-Wire Wire Line
- 2050 6500 2350 6500
-Wire Wire Line
- 2200 6500 2200 6650
-Connection ~ 2200 6500
-Wire Wire Line
- 1750 7000 11100 7000
-Wire Wire Line
- 2200 7000 2200 6950
-Connection ~ 2200 7000
-Wire Wire Line
- 4500 6950 4500 7000
-Connection ~ 4500 7000
-Wire Wire Line
- 6000 7000 6000 6950
-Wire Wire Line
- 9550 6950 9550 7000
-Connection ~ 9550 7000
-Wire Wire Line
- 10500 6950 10500 7000
-Connection ~ 10500 7000
-Wire Wire Line
- 4500 6100 4500 6650
-Wire Wire Line
- 3650 3750 3650 5700
-Connection ~ 3650 4600
-Wire Wire Line
- 3950 4800 4500 4800
-Wire Wire Line
- 4500 4800 4500 5700
-Wire Wire Line
- 1750 1450 1750 800
-Wire Wire Line
- 1750 800 1850 800
-Wire Wire Line
- 3650 800 10500 800
-Wire Wire Line
- 10500 1950 10500 5700
-Wire Wire Line
- 10500 5700 10450 5700
-Wire Wire Line
- 9850 5900 10150 5900
-Wire Wire Line
- 10500 5550 10000 5550
-Wire Wire Line
- 10000 5550 10000 5900
-Connection ~ 10000 5900
-Connection ~ 10500 5550
-Wire Wire Line
- 10450 6100 10450 6650
-Wire Wire Line
- 10450 6650 10500 6650
-Wire Wire Line
- 9550 6100 9550 6650
-Wire Wire Line
- 9550 1600 9550 5700
-Wire Wire Line
- 8500 1600 9550 1600
-Wire Wire Line
- 9050 800 9050 1300
-Connection ~ 9050 800
-Connection ~ 9050 1600
-Wire Wire Line
- 8500 1300 8500 800
-Connection ~ 8500 800
-Wire Wire Line
- 9550 2650 8850 2650
-Connection ~ 9550 2650
-Wire Wire Line
- 7200 2450 8550 2450
-Wire Wire Line
- 7900 2450 7900 2550
-Wire Wire Line
- 7200 1550 7200 2550
-Connection ~ 7900 2450
-Wire Wire Line
- 7200 800 7200 1250
-Connection ~ 7200 800
-Connection ~ 7200 2450
-Wire Wire Line
- 3650 3350 3650 800
-Connection ~ 3650 800
-Wire Wire Line
- 3950 4400 3950 800
-Connection ~ 3950 800
-Wire Wire Line
- 4950 1150 4950 800
-Connection ~ 4950 800
-Wire Wire Line
- 5950 1150 5950 800
-Connection ~ 5950 800
-Wire Wire Line
- 6200 1850 5950 1850
-Wire Wire Line
- 5950 1450 5950 3100
-Wire Wire Line
- 4950 1450 4950 3750
-Wire Wire Line
- 4950 2350 5000 2350
-Wire Wire Line
- 5950 2350 5300 2350
-Connection ~ 5950 1850
-Wire Wire Line
- 3650 3950 4150 3950
-Connection ~ 3650 3950
-Wire Wire Line
- 4150 2950 3850 2950
-Wire Wire Line
- 3850 2950 3850 3950
-Connection ~ 3850 3950
-Wire Wire Line
- 4950 2950 4450 2950
-Connection ~ 4950 2350
-Connection ~ 4950 2950
-Wire Wire Line
- 4650 3950 4450 3950
-Wire Wire Line
- 3650 6950 3650 7000
-Connection ~ 3650 7000
-Wire Wire Line
- 3650 6650 3650 6100
-Wire Wire Line
- 10000 5900 3950 5900
-Connection ~ 4800 5900
-Wire Wire Line
- 8550 6500 8550 4400
-Connection ~ 2750 6500
-Wire Wire Line
- 8550 2850 8550 4100
-Wire Wire Line
- 8200 2750 8350 2750
-Wire Wire Line
- 8350 2750 8350 3000
-Wire Wire Line
- 8350 3000 8550 3000
-Connection ~ 8550 3000
-Wire Wire Line
- 7900 2950 7900 6500
-Connection ~ 7900 6500
-Wire Wire Line
- 7200 2950 7200 7000
-Wire Wire Line
- 6500 1650 6500 800
-Connection ~ 6500 800
-Connection ~ 7200 7000
-Connection ~ 6000 7000
-Wire Wire Line
- 6500 6950 6500 7000
-Connection ~ 6500 7000
-Wire Wire Line
- 5350 3300 5650 3300
-Wire Wire Line
- 5500 3300 5500 3450
-Connection ~ 5500 3300
-Wire Wire Line
- 4950 4150 6000 4150
-Wire Wire Line
- 5950 4150 5950 3500
-Wire Wire Line
- 5500 3750 5500 4150
-Connection ~ 5500 4150
-Wire Wire Line
- 6000 4150 6000 6650
-Connection ~ 5950 4150
-Connection ~ 5950 2350
-Wire Wire Line
- 3150 3550 3150 3700
-Connection ~ 3150 3550
-Wire Wire Line
- 4700 5150 4500 5150
-Connection ~ 4500 5150
-Wire Notes Line
- 2200 800 2900 800
-Wire Notes Line
- 3150 4050 3150 7000
-Wire Wire Line
- 1300 1700 1300 1650
-Connection ~ 1300 1650
-Wire Wire Line
- 5050 3300 4950 3300
-Connection ~ 4950 3300
-$Comp
-L eSim_PNP Q20
-U 1 1 5CA087B6
-P 2650 1800
-F 0 "Q20" H 2550 1850 50 0000 R CNN
-F 1 "eSim_PNP" H 2600 1950 50 0000 R CNN
-F 2 "" H 2850 1900 29 0000 C CNN
-F 3 "" H 2650 1800 60 0000 C CNN
- 1 2650 1800
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 2750 1450 2750 1600
-Wire Notes Line
- 2925 800 3600 800
-Wire Wire Line
- 10500 800 10500 1650
-Wire Wire Line
- 6500 2050 6500 6650
-Wire Wire Line
- 6500 5100 6550 5100
-Connection ~ 6500 5100
-Wire Wire Line
- 6900 2750 6500 2750
-Connection ~ 6500 2750
-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/NE566/NE566.sub b/src/SubcircuitLibrary/NE566/NE566.sub deleted file mode 100644 index 5b2fc943..00000000 --- a/src/SubcircuitLibrary/NE566/NE566.sub +++ /dev/null @@ -1,55 +0,0 @@ -* Subcircuit NE566
-.subckt NE566 net-_q15-pad1_ net-_q14-pad3_ net-_q10-pad3_ net-_d10-pad2_ net-_q1-pad1_ net-_d3-pad2_ net-_d9-pad2_
-* c:\esim_1\esim\src\subcircuitlibrary\ne566\ne566.cir
-.include PNP.lib
-.include D.lib
-.include NPN.lib
-q1 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2222
-q2 net-_d10-pad1_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-q5 net-_q2-pad2_ net-_q2-pad2_ net-_d1-pad1_ Q2N2222
-d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
-d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
-q6 net-_d3-pad2_ net-_d1-pad2_ net-_q3-pad2_ Q2N2222
-q8 net-_d9-pad2_ net-_d3-pad2_ net-_d5-pad1_ Q2N2222
-q7 net-_q3-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222
-q3 net-_d1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
-r1 net-_q3-pad3_ net-_d4-pad2_ 5k
-r3 net-_q7-pad3_ net-_d4-pad2_ 5k
-d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
-q4 net-_d4-pad2_ net-_d2-pad2_ net-_q15-pad1_ Q2N2222
-d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
-r2 net-_d2-pad2_ net-_q15-pad1_ 5k
-r4 net-_q9-pad3_ net-_q15-pad1_ 5k
-q10 net-_d9-pad2_ net-_d5-pad1_ net-_q10-pad3_ Q2N2222
-q9 net-_d5-pad1_ net-_q11-pad2_ net-_q9-pad3_ Q2N2222
-q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
-d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
-d6 net-_d5-pad1_ net-_d6-pad2_ 1N4148
-q12 net-_d5-pad2_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
-d8 net-_d5-pad2_ net-_d8-pad2_ 1N4148
-d7 net-_d5-pad2_ net-_d7-pad2_ 1N4148
-r6 net-_d9-pad2_ net-_d5-pad2_ 5k
-r8 net-_d9-pad2_ net-_d8-pad2_ 5k
-q14 net-_d9-pad2_ net-_d8-pad2_ net-_q14-pad3_ Q2N2222
-q13 net-_d8-pad2_ net-_d7-pad2_ net-_q12-pad3_ Q2N2222
-r7 net-_d7-pad2_ net-_q12-pad3_ 5k
-q15 net-_q15-pad1_ net-_q14-pad3_ net-_q15-pad3_ Q2N2907A
-q16 net-_q15-pad3_ net-_q16-pad2_ net-_d2-pad1_ Q2N2222
-q17 net-_q16-pad2_ net-_d9-pad1_ net-_q15-pad3_ Q2N2222
-r13 net-_d9-pad2_ net-_d9-pad1_ 5k
-d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
-r15 net-_d9-pad2_ net-_q11-pad2_ 5k
-r12 net-_q16-pad2_ net-_d2-pad1_ 5k
-r5 net-_q11-pad3_ net-_q15-pad1_ 5k
-r9 net-_q12-pad3_ net-_q15-pad1_ 5k
-r10 net-_q14-pad3_ net-_q15-pad1_ 5k
-q18 net-_d9-pad1_ net-_q11-pad2_ net-_q18-pad3_ Q2N2222
-q19 net-_q11-pad2_ net-_q11-pad2_ net-_q19-pad3_ Q2N2222
-r14 net-_q18-pad3_ net-_q15-pad1_ 5k
-r16 net-_q19-pad3_ net-_q15-pad1_ 5k
-r11 net-_d9-pad2_ net-_q15-pad3_ 5k
-d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
-q20 net-_q2-pad2_ net-_d10-pad1_ net-_q1-pad1_ Q2N2222
-* Control Statements
-
-.ends NE566
\ No newline at end of file diff --git a/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml b/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml deleted file mode 100644 index cd7c0b08..00000000 --- a/src/SubcircuitLibrary/NE566/NE566_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><q20><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q20><d8><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d8><d9><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d9><d6><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d6><d7><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d7><d4><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d5><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d5><d2><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1><q1><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q5><q4><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q9><q8><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q15><q14><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q14><q17><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q17><q16><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q16><q11><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12><d10><field>C:/esim_1/eSim/src/deviceModelLibrary/Diode/D.lib</field></d10><q19><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q19><q18><field>C:/esim_1/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/diac/analysis b/src/SubcircuitLibrary/diac/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/diac/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/diac/diac.cir b/src/SubcircuitLibrary/diac/diac.cir deleted file mode 100644 index 91629b91..00000000 --- a/src/SubcircuitLibrary/diac/diac.cir +++ /dev/null @@ -1,13 +0,0 @@ -* /opt/eSim/src/SubcircuitLibrary/diac/diac.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:35:49 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U3 1 2 PORT -U1 1 1 2 aswitch -U2 1 1 2 aswitch - -.end diff --git a/src/SubcircuitLibrary/diac/diac.cir.out b/src/SubcircuitLibrary/diac/diac.cir.out deleted file mode 100644 index a1e31f14..00000000 --- a/src/SubcircuitLibrary/diac/diac.cir.out +++ /dev/null @@ -1,21 +0,0 @@ -* /opt/esim/src/subcircuitlibrary/diac/diac.cir - -* u3 1 2 port -* u1 1 1 2 aswitch -* u2 1 1 2 aswitch -a1 1 (1 2) u1 -a2 1 (1 2) u2 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) - -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/diac/diac.pro b/src/SubcircuitLibrary/diac/diac.pro deleted file mode 100644 index c8563047..00000000 --- a/src/SubcircuitLibrary/diac/diac.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=Tue Dec 8 14:06:36 2015 -last_client=eeschema -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=eSim_Analog -LibName33=eSim_Devices -LibName34=eSim_Digital -LibName35=eSim_Hybrid -LibName36=eSim_Miscellaneous -LibName37=eSim_Sources -LibName38=eSim_Subckt -LibName39=eSim_User diff --git a/src/SubcircuitLibrary/diac/diac.sch b/src/SubcircuitLibrary/diac/diac.sch deleted file mode 100644 index 163665e7..00000000 --- a/src/SubcircuitLibrary/diac/diac.sch +++ /dev/null @@ -1,148 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "22 sep 2014" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 4150 2750 4150 4300 -Connection ~ 4400 3750 -Wire Wire Line - 4400 4450 5050 4450 -Wire Wire Line - 4400 4450 4400 3450 -Wire Wire Line - 5500 3350 5500 4050 -Connection ~ 4600 3400 -Wire Wire Line - 4600 4050 4600 2750 -Wire Wire Line - 4600 2750 4150 2750 -Wire Wire Line - 4400 3450 4150 3450 -Connection ~ 4150 3450 -Wire Wire Line - 4400 3750 5050 3750 -$Comp -L PWR_FLAG #FLG01 -U 1 1 5417D647 -P 4150 4300 -F 0 "#FLG01" H 4150 4570 30 0001 C CNN -F 1 "PWR_FLAG" H 4150 4530 30 0000 C CNN -F 2 "" H 4150 4300 60 0001 C CNN -F 3 "" H 4150 4300 60 0001 C CNN - 1 4150 4300 - 0 1 1 0 -$EndComp -$Comp -L PORT U3 -U 2 1 5417D62C -P 5750 3350 -F 0 "U3" H 5750 3300 30 0000 C CNN -F 1 "PORT" H 5750 3350 30 0000 C CNN -F 2 "" H 5750 3350 60 0001 C CNN -F 3 "" H 5750 3350 60 0001 C CNN - 2 5750 3350 - -1 0 0 1 -$EndComp -$Comp -L PORT U3 -U 1 1 5417D624 -P 4150 2500 -F 0 "U3" H 4150 2450 30 0000 C CNN -F 1 "PORT" H 4150 2500 30 0000 C CNN -F 2 "" H 4150 2500 60 0001 C CNN -F 3 "" H 4150 2500 60 0001 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 5417D5DC -P 4150 4300 -F 0 "#PWR02" H 4150 4300 30 0001 C CNN -F 1 "GND" H 4150 4230 30 0001 C CNN -F 2 "" H 4150 4300 60 0001 C CNN -F 3 "" H 4150 4300 60 0001 C CNN - 1 4150 4300 - 1 0 0 -1 -$EndComp -$Comp -L aswitch U1 -U 1 1 56669812 -P 4600 3550 -F 0 "U1" H 5050 3850 60 0000 C CNN -F 1 "aswitch" H 5050 3750 60 0000 C CNN -F 2 "" H 5050 3650 60 0000 C CNN -F 3 "" H 5050 3650 60 0000 C CNN - 1 4600 3550 - 1 0 0 -1 -$EndComp -$Comp -L aswitch U2 -U 1 1 5666987C -P 4600 4200 -F 0 "U2" H 5050 4500 60 0000 C CNN -F 1 "aswitch" H 5050 4400 60 0000 C CNN -F 2 "" H 5050 4300 60 0000 C CNN -F 3 "" H 5050 4300 60 0000 C CNN - 1 4600 4200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5050 4450 5050 4300 -Wire Wire Line - 5050 3750 5050 3650 -Wire Wire Line - 5500 4050 5450 4050 -Wire Wire Line - 5500 3400 5450 3400 -Connection ~ 5500 3400 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/diac/diac.sub b/src/SubcircuitLibrary/diac/diac.sub deleted file mode 100644 index 7f28ecc2..00000000 --- a/src/SubcircuitLibrary/diac/diac.sub +++ /dev/null @@ -1,15 +0,0 @@ -* Subcircuit diac -.subckt diac 1 2 -* /opt/esim/src/subcircuitlibrary/diac/diac.cir -* u1 1 1 2 aswitch -* u2 1 1 2 aswitch -a1 1 (1 2) u1 -a2 1 (1 2) u2 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) - -* Control Statements - -.ends diac diff --git a/src/SubcircuitLibrary/diac/diac_Previous_Values.xml b/src/SubcircuitLibrary/diac/diac_Previous_Values.xml deleted file mode 100644 index 96df431c..00000000 --- a/src/SubcircuitLibrary/diac/diac_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">25</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-25</field10></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/analysis b/src/SubcircuitLibrary/full_adder/analysis deleted file mode 100644 index 52ccc5ec..00000000 --- a/src/SubcircuitLibrary/full_adder/analysis +++ /dev/null @@ -1 +0,0 @@ -.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib deleted file mode 100644 index 623a7f41..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# half_adder -# -DEF half_adder X 0 40 Y Y 1 F N -F0 "X" 900 500 60 H V C CNN -F1 "half_adder" 900 400 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 500 800 1250 0 0 1 0 N -X IN1 1 300 700 200 R 50 50 1 1 I -X IN2 2 300 100 200 R 50 50 1 1 I -X SUM 3 1450 700 200 L 50 50 1 1 O -X COUT 4 1450 100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir b/src/SubcircuitLibrary/full_adder/full_adder.cir deleted file mode 100644 index 6461b5b6..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder.cir +++ /dev/null @@ -1,12 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -X1 8 7 6 2 half_adder -X2 5 6 4 3 half_adder -U1 8 7 5 4 1 PORT -U2 3 2 1 d_or - -.end diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir.out b/src/SubcircuitLibrary/full_adder/full_adder.cir.out deleted file mode 100644 index b90ce70d..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder.cir.out +++ /dev/null @@ -1,19 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 - -.include half_adder.sub -x1 8 7 6 2 half_adder -x2 5 6 4 3 half_adder -* u1 8 7 5 4 1 port -* u2 3 2 1 d_or -a1 [3 2 ] 1 u2 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/full_adder/full_adder.pro b/src/SubcircuitLibrary/full_adder/full_adder.pro deleted file mode 100644 index c0db0775..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder.pro +++ /dev/null @@ -1,69 +0,0 @@ -update=Wed Jun 24 12:19:16 2015 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog -LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices -LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital -LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid -LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources -LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sch b/src/SubcircuitLibrary/full_adder/full_adder.sch deleted file mode 100644 index 8bd400f2..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder.sch +++ /dev/null @@ -1,180 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Sources -LIBS:eSim_Subckt -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L half_adder X1 -U 1 1 558AA064 -P 3800 3350 -F 0 "X1" H 4700 3850 60 0000 C CNN -F 1 "half_adder" H 4700 3750 60 0000 C CNN -F 2 "" H 3800 3350 60 0000 C CNN -F 3 "" H 3800 3350 60 0000 C CNN - 1 3800 3350 - 1 0 0 -1 -$EndComp -$Comp -L half_adder X2 -U 1 1 558AA0C1 -P 5700 3350 -F 0 "X2" H 6600 3850 60 0000 C CNN -F 1 "half_adder" H 6600 3750 60 0000 C CNN -F 2 "" H 5700 3350 60 0000 C CNN -F 3 "" H 5700 3350 60 0000 C CNN - 1 5700 3350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 558AA277 -P 3450 2650 -F 0 "U1" H 3500 2750 30 0000 C CNN -F 1 "PORT" H 3450 2650 30 0000 C CNN -F 2 "" H 3450 2650 60 0000 C CNN -F 3 "" H 3450 2650 60 0000 C CNN - 1 3450 2650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 558AA29E -P 3450 3250 -F 0 "U1" H 3500 3350 30 0000 C CNN -F 1 "PORT" H 3450 3250 30 0000 C CNN -F 2 "" H 3450 3250 60 0000 C CNN -F 3 "" H 3450 3250 60 0000 C CNN - 2 3450 3250 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 558AA2D8 -P 5650 2300 -F 0 "U1" H 5700 2400 30 0000 C CNN -F 1 "PORT" H 5650 2300 30 0000 C CNN -F 2 "" H 5650 2300 60 0000 C CNN -F 3 "" H 5650 2300 60 0000 C CNN - 3 5650 2300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 558AA378 -P 7900 2650 -F 0 "U1" H 7950 2750 30 0000 C CNN -F 1 "PORT" H 7900 2650 30 0000 C CNN -F 2 "" H 7900 2650 60 0000 C CNN -F 3 "" H 7900 2650 60 0000 C CNN - 4 7900 2650 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 5 1 558AA3E0 -P 8700 3400 -F 0 "U1" H 8750 3500 30 0000 C CNN -F 1 "PORT" H 8700 3400 30 0000 C CNN -F 2 "" H 8700 3400 60 0000 C CNN -F 3 "" H 8700 3400 60 0000 C CNN - 5 8700 3400 - -1 0 0 1 -$EndComp -$Comp -L d_or U2 -U 1 1 558AA43B -P 7900 3450 -F 0 "U2" H 7900 3450 60 0000 C CNN -F 1 "d_or" H 7900 3550 60 0000 C CNN -F 2 "" H 7900 3450 60 0000 C CNN -F 3 "" H 7900 3450 60 0000 C CNN - 1 7900 3450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3700 2650 4100 2650 -Wire Wire Line - 3700 3250 4100 3250 -Wire Wire Line - 5250 2650 5650 2650 -Wire Wire Line - 5650 2650 5650 3250 -Wire Wire Line - 5650 3250 6000 3250 -Wire Wire Line - 5900 2300 5900 2650 -Wire Wire Line - 5900 2650 6000 2650 -Wire Wire Line - 7150 2650 7650 2650 -Wire Wire Line - 7150 3250 7350 3250 -Wire Wire Line - 7350 3250 7350 3350 -Wire Wire Line - 7350 3350 7450 3350 -Wire Wire Line - 5250 3250 5400 3250 -Wire Wire Line - 5400 3250 5400 3450 -Wire Wire Line - 5400 3450 7450 3450 -Wire Wire Line - 8350 3400 8450 3400 -Text Notes 3850 2500 0 60 ~ 0 -IN1 -Text Notes 3850 3150 0 60 ~ 0 -IN2 -Text Notes 6000 2350 0 60 ~ 0 -CIN -Text Notes 7350 2550 0 60 ~ 0 -SUM -Text Notes 8300 3200 0 60 ~ 0 -COUT -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sub b/src/SubcircuitLibrary/full_adder/full_adder.sub deleted file mode 100644 index 5f261f78..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder.sub +++ /dev/null @@ -1,13 +0,0 @@ -* Subcircuit full_adder -.subckt full_adder 8 7 5 4 1 -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 -.include half_adder.sub -x1 8 7 6 2 half_adder -x2 5 6 4 3 half_adder -* u2 3 2 1 d_or -a1 [3 2 ] 1 u2 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends full_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml deleted file mode 100644 index b63184d6..00000000 --- a/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib deleted file mode 100644 index 68785220..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir b/src/SubcircuitLibrary/full_adder/half_adder.cir deleted file mode 100644 index 8b2e7e06..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder.cir +++ /dev/null @@ -1,11 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 1 4 3 d_xor -U3 1 4 2 d_and -U1 1 4 3 2 PORT - -.end diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir.out b/src/SubcircuitLibrary/full_adder/half_adder.cir.out deleted file mode 100644 index b1b6b1e7..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 - -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -* u1 1 4 3 2 port -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/full_adder/half_adder.pro b/src/SubcircuitLibrary/full_adder/half_adder.pro deleted file mode 100644 index 695ae0f6..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder.pro +++ /dev/null @@ -1,69 +0,0 @@ -update=Wed Jun 24 11:27:22 2015 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog -LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices -LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital -LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid -LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources -LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sch b/src/SubcircuitLibrary/full_adder/half_adder.sch deleted file mode 100644 index bf9bcbf0..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder.sch +++ /dev/null @@ -1,152 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Sources -LIBS:eSim_Subckt -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_xor U2 -U 1 1 558A946A -P 5650 3050 -F 0 "U2" H 5650 3050 60 0000 C CNN -F 1 "d_xor" H 5700 3150 47 0000 C CNN -F 2 "" H 5650 3050 60 0000 C CNN -F 3 "" H 5650 3050 60 0000 C CNN - 1 5650 3050 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 558A94D5 -P 5700 3800 -F 0 "U3" H 5700 3800 60 0000 C CNN -F 1 "d_and" H 5750 3900 60 0000 C CNN -F 2 "" H 5700 3800 60 0000 C CNN -F 3 "" H 5700 3800 60 0000 C CNN - 1 5700 3800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 558A94F6 -P 4150 3000 -F 0 "U1" H 4200 3100 30 0000 C CNN -F 1 "PORT" H 4150 3000 30 0000 C CNN -F 2 "" H 4150 3000 60 0000 C CNN -F 3 "" H 4150 3000 60 0000 C CNN - 1 4150 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 558A9543 -P 4150 3450 -F 0 "U1" H 4200 3550 30 0000 C CNN -F 1 "PORT" H 4150 3450 30 0000 C CNN -F 2 "" H 4150 3450 60 0000 C CNN -F 3 "" H 4150 3450 60 0000 C CNN - 2 4150 3450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 558A9573 -P 6650 3000 -F 0 "U1" H 6700 3100 30 0000 C CNN -F 1 "PORT" H 6650 3000 30 0000 C CNN -F 2 "" H 6650 3000 60 0000 C CNN -F 3 "" H 6650 3000 60 0000 C CNN - 3 6650 3000 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 558A9606 -P 6700 3750 -F 0 "U1" H 6750 3850 30 0000 C CNN -F 1 "PORT" H 6700 3750 30 0000 C CNN -F 2 "" H 6700 3750 60 0000 C CNN -F 3 "" H 6700 3750 60 0000 C CNN - 4 6700 3750 - -1 0 0 1 -$EndComp -Wire Wire Line - 5200 2950 4450 2950 -Wire Wire Line - 4450 2950 4450 3000 -Wire Wire Line - 4450 3000 4400 3000 -Wire Wire Line - 4400 3450 4550 3450 -Wire Wire Line - 4550 3450 4550 3050 -Wire Wire Line - 4550 3050 5200 3050 -Wire Wire Line - 5250 3700 5000 3700 -Wire Wire Line - 5000 3700 5000 2950 -Connection ~ 5000 2950 -Wire Wire Line - 5250 3800 4850 3800 -Wire Wire Line - 4850 3800 4850 3050 -Connection ~ 4850 3050 -Wire Wire Line - 6100 3000 6400 3000 -Wire Wire Line - 6150 3750 6450 3750 -Text Notes 4550 2950 0 60 ~ 0 -IN1\n\n -Text Notes 4600 3150 0 60 ~ 0 -IN2 -Text Notes 6200 2950 0 60 ~ 0 -SUM\n -Text Notes 6200 3650 0 60 ~ 0 -COUT\n -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sub b/src/SubcircuitLibrary/full_adder/half_adder.sub deleted file mode 100644 index e9f92223..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit half_adder -.subckt half_adder 1 4 3 2 -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends half_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml deleted file mode 100644 index b915f0da..00000000 --- a/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/analysis b/src/SubcircuitLibrary/full_sub/analysis deleted file mode 100644 index 660a46cc..00000000 --- a/src/SubcircuitLibrary/full_sub/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib b/src/SubcircuitLibrary/full_sub/full_sub-cache.lib deleted file mode 100644 index 6949ac1a..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub-cache.lib +++ /dev/null @@ -1,79 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_or -# -DEF d_or U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_or" 0 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 -250 -50 150 -50 N -P 2 0 1 0 -250 150 150 150 N -X IN1 1 -450 100 215 R 50 50 1 1 I -X IN2 2 -450 0 215 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# half_sub -# -DEF half_sub X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "half_sub" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -300 300 300 -300 0 1 0 N -X A 1 -500 200 200 R 50 50 1 1 I -X B 2 -500 -100 200 R 50 50 1 1 I -X D 3 500 150 200 L 50 50 1 1 O -X BORROW 4 500 -100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib b/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib deleted file mode 100644 index 803b5ece..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub-rescue.lib +++ /dev/null @@ -1,20 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# half_sub-RESCUE-full_sub -# -DEF half_sub-RESCUE-full_sub X 0 40 Y Y 1 F N -F0 "X" 0 0 60 H V C CNN -F1 "half_sub-RESCUE-full_sub" 0 0 60 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -S -1450 850 1550 -1050 0 1 0 N -X A 1 -1100 850 200 R 50 50 1 1 I -X B 2 -350 850 200 R 50 50 1 1 I -X D 3 -800 -1050 200 L 50 50 1 1 O -X BORROW 4 0 -1050 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir b/src/SubcircuitLibrary/full_sub/full_sub.cir deleted file mode 100644 index 67359421..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub.cir +++ /dev/null @@ -1,14 +0,0 @@ -* C:\esim\eSim\src\SubcircuitLibrary\full_sub\full_sub.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/07/19 10:58:59 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_or -U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad3_ PORT -X1 Net-_U5-Pad1_ Net-_U5-Pad2_ Net-_X1-Pad3_ Net-_U3-Pad1_ half_sub -X2 Net-_U5-Pad3_ Net-_X1-Pad3_ Net-_U5-Pad4_ Net-_U3-Pad2_ half_sub - -.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.cir.out b/src/SubcircuitLibrary/full_sub/full_sub.cir.out deleted file mode 100644 index 5e58cc0a..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub.cir.out +++ /dev/null @@ -1,19 +0,0 @@ -* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir - -.include half_sub.sub -* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or -* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ port -x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub -x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub -a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/full_sub/full_sub.pro b/src/SubcircuitLibrary/full_sub/full_sub.pro deleted file mode 100644 index 1a0c3543..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=03/07/19 10:55:03 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=full_sub-rescue -LibName2=adc-dac -LibName3=memory -LibName4=xilinx -LibName5=microcontrollers -LibName6=dsp -LibName7=microchip -LibName8=analog_switches -LibName9=motorola -LibName10=texas -LibName11=intel -LibName12=audio -LibName13=interface -LibName14=digital-audio -LibName15=philips -LibName16=display -LibName17=cypress -LibName18=siliconi -LibName19=opto -LibName20=atmel -LibName21=contrib -LibName22=power -LibName23=device -LibName24=transistors -LibName25=conn -LibName26=linear -LibName27=regul -LibName28=74xx -LibName29=cmos4000 -LibName30=eSim_Analog -LibName31=eSim_Devices -LibName32=eSim_Digital -LibName33=eSim_Hybrid -LibName34=eSim_Miscellaneous -LibName35=eSim_Power -LibName36=eSim_Sources -LibName37=eSim_Subckt -LibName38=eSim_User -LibName39=eSim_Plot -LibName40=eSim_PSpice - diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sch b/src/SubcircuitLibrary/full_sub/full_sub.sch deleted file mode 100644 index 99ca85e5..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub.sch +++ /dev/null @@ -1,211 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:full_sub-rescue -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:full_sub-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_or U3 -U 1 1 5C80734A -P 9350 4050 -F 0 "U3" H 9350 4050 60 0000 C CNN -F 1 "d_or" H 9350 4150 60 0000 C CNN -F 2 "" H 9350 4050 60 0000 C CNN -F 3 "" H 9350 4050 60 0000 C CNN - 1 9350 4050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4850 3600 5800 3600 -Wire Wire Line - 4650 2800 8600 2800 -Wire Wire Line - 8600 2800 8600 3950 -Wire Wire Line - 8600 3950 8900 3950 -Wire Wire Line - 8100 4450 8650 4450 -Wire Wire Line - 8650 4450 8650 4050 -Wire Wire Line - 8650 4050 8900 4050 -Wire Wire Line - 2800 3450 2800 3250 -Wire Wire Line - 2800 3250 3300 3250 -Wire Wire Line - 1450 3550 3300 3550 -Wire Wire Line - 4050 5100 5200 5100 -Wire Wire Line - 5800 3600 5800 5250 -Wire Wire Line - 8250 5250 9350 5250 -Wire Wire Line - 9350 5250 9350 4900 -Wire Wire Line - 9350 4900 10750 4900 -Wire Wire Line - 9800 4000 9800 4600 -Wire Wire Line - 9800 4600 9550 4600 -Wire Wire Line - 9550 4600 9550 4800 -Wire Wire Line - 9550 4800 10750 4800 -$Comp -L PORT U5 -U 1 1 5C80A4E8 -P 1200 3450 -F 0 "U5" H 1250 3550 30 0000 C CNN -F 1 "PORT" H 1200 3450 30 0000 C CNN -F 2 "" H 1200 3450 60 0000 C CNN -F 3 "" H 1200 3450 60 0000 C CNN - 1 1200 3450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 2 1 5C80A51E -P 1200 3650 -F 0 "U5" H 1250 3750 30 0000 C CNN -F 1 "PORT" H 1200 3650 30 0000 C CNN -F 2 "" H 1200 3650 60 0000 C CNN -F 3 "" H 1200 3650 60 0000 C CNN - 2 1200 3650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 3 1 5C80A54E -P 3800 5100 -F 0 "U5" H 3850 5200 30 0000 C CNN -F 1 "PORT" H 3800 5100 30 0000 C CNN -F 2 "" H 3800 5100 60 0000 C CNN -F 3 "" H 3800 5100 60 0000 C CNN - 3 3800 5100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U5 -U 5 1 5C80A828 -P 11000 4800 -F 0 "U5" H 11050 4900 30 0000 C CNN -F 1 "PORT" H 11000 4800 30 0000 C CNN -F 2 "" H 11000 4800 60 0000 C CNN -F 3 "" H 11000 4800 60 0000 C CNN - 5 11000 4800 - -1 0 0 1 -$EndComp -$Comp -L PORT U5 -U 4 1 5C80AB2A -P 11000 4950 -F 0 "U5" H 11050 5050 30 0000 C CNN -F 1 "PORT" H 11000 4950 30 0000 C CNN -F 2 "" H 11000 4950 60 0000 C CNN -F 3 "" H 11000 4950 60 0000 C CNN - 4 11000 4950 - -1 0 0 1 -$EndComp -Wire Wire Line - 1450 3450 2800 3450 -Wire Wire Line - 1450 3650 1450 3550 -Wire Wire Line - 10750 4900 10750 4950 -$Comp -L half_sub X1 -U 1 1 5C80AC4D -P 3800 3450 -F 0 "X1" H 3800 3450 60 0000 C CNN -F 1 "half_sub" H 3800 3450 60 0000 C CNN -F 2 "" H 3800 3450 60 0001 C CNN -F 3 "" H 3800 3450 60 0001 C CNN - 1 3800 3450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4300 3550 4650 3550 -Wire Wire Line - 4650 3550 4650 2800 -Wire Wire Line - 4300 3300 4850 3300 -Wire Wire Line - 4850 3300 4850 3600 -$Comp -L half_sub X2 -U 1 1 5C80AD72 -P 7300 5150 -F 0 "X2" H 7300 5150 60 0000 C CNN -F 1 "half_sub" H 7300 5150 60 0000 C CNN -F 2 "" H 7300 5150 60 0001 C CNN -F 3 "" H 7300 5150 60 0001 C CNN - 1 7300 5150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5800 5250 6800 5250 -Wire Wire Line - 5200 5100 5200 4950 -Wire Wire Line - 5200 4950 6800 4950 -Wire Wire Line - 7800 5000 8250 5000 -Wire Wire Line - 8250 5000 8250 5250 -Wire Wire Line - 7800 5250 8100 5250 -Wire Wire Line - 8100 5250 8100 4450 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/full_sub.sub b/src/SubcircuitLibrary/full_sub/full_sub.sub deleted file mode 100644 index 9c9dcc5a..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub.sub +++ /dev/null @@ -1,13 +0,0 @@ -* Subcircuit full_sub -.subckt full_sub net-_u5-pad1_ net-_u5-pad2_ net-_u5-pad3_ net-_u5-pad4_ net-_u3-pad3_ -* c:\esim\esim\src\subcircuitlibrary\full_sub\full_sub.cir -.include half_sub.sub -* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_or -x1 net-_u5-pad1_ net-_u5-pad2_ net-_x1-pad3_ net-_u3-pad1_ half_sub -x2 net-_u5-pad3_ net-_x1-pad3_ net-_u5-pad4_ net-_u3-pad2_ half_sub -a1 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3 -* Schematic Name: d_or, NgSpice Name: d_or -.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends full_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml deleted file mode 100644 index fcdb63e0..00000000 --- a/src/SubcircuitLibrary/full_sub/full_sub_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x2><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x2><x1><field>C:\esim\eSim\src\SubcircuitLibrary\half_sub</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub-cache.lib b/src/SubcircuitLibrary/full_sub/half_sub-cache.lib deleted file mode 100644 index bd15e664..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub-cache.lib +++ /dev/null @@ -1,95 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir b/src/SubcircuitLibrary/full_sub/half_sub.cir deleted file mode 100644 index f20f0368..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub.cir +++ /dev/null @@ -1,14 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor -U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter -U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.cir.out b/src/SubcircuitLibrary/full_sub/half_sub.cir.out deleted file mode 100644 index 91816956..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir - -* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/full_sub/half_sub.pro b/src/SubcircuitLibrary/full_sub/half_sub.pro deleted file mode 100644 index 90e3ded9..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Wed 06 Mar 2019 11:10:38 PM IST -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice -LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt - diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sch b/src/SubcircuitLibrary/full_sub/half_sub.sch deleted file mode 100644 index e70b1675..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub.sch +++ /dev/null @@ -1,150 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_xor U3 -U 1 1 5C7FDDA3 -P 4400 3150 -F 0 "U3" H 4400 3150 60 0000 C CNN -F 1 "d_xor" H 4450 3250 47 0000 C CNN -F 2 "" H 4400 3150 60 0000 C CNN -F 3 "" H 4400 3150 60 0000 C CNN - 1 4400 3150 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U2 -U 1 1 5C7FDDD8 -P 3400 3750 -F 0 "U2" H 3400 3650 60 0000 C CNN -F 1 "d_inverter" H 3400 3900 60 0000 C CNN -F 2 "" H 3450 3700 60 0000 C CNN -F 3 "" H 3450 3700 60 0000 C CNN - 1 3400 3750 - 1 0 0 -1 -$EndComp -$Comp -L d_and U4 -U 1 1 5C7FDE57 -P 4450 3750 -F 0 "U4" H 4450 3750 60 0000 C CNN -F 1 "d_and" H 4500 3850 60 0000 C CNN -F 2 "" H 4450 3750 60 0000 C CNN -F 3 "" H 4450 3750 60 0000 C CNN - 1 4450 3750 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 3150 3950 3650 -Wire Wire Line - 3950 3650 4000 3650 -Wire Wire Line - 3700 3750 4000 3750 -Wire Wire Line - 3100 3750 3100 3050 -Wire Wire Line - 2950 3050 3950 3050 -$Comp -L PORT U1 -U 1 1 5C7FDF5A -P 2700 3050 -F 0 "U1" H 2750 3150 30 0000 C CNN -F 1 "PORT" H 2700 3050 30 0000 C CNN -F 2 "" H 2700 3050 60 0000 C CNN -F 3 "" H 2700 3050 60 0000 C CNN - 1 2700 3050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C7FDF97 -P 3500 3350 -F 0 "U1" H 3550 3450 30 0000 C CNN -F 1 "PORT" H 3500 3350 30 0000 C CNN -F 2 "" H 3500 3350 60 0000 C CNN -F 3 "" H 3500 3350 60 0000 C CNN - 2 3500 3350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C7FE00A -P 5300 3100 -F 0 "U1" H 5350 3200 30 0000 C CNN -F 1 "PORT" H 5300 3100 30 0000 C CNN -F 2 "" H 5300 3100 60 0000 C CNN -F 3 "" H 5300 3100 60 0000 C CNN - 3 5300 3100 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C7FE064 -P 5350 3700 -F 0 "U1" H 5400 3800 30 0000 C CNN -F 1 "PORT" H 5350 3700 30 0000 C CNN -F 2 "" H 5350 3700 60 0000 C CNN -F 3 "" H 5350 3700 60 0000 C CNN - 4 5350 3700 - -1 0 0 1 -$EndComp -Connection ~ 3100 3050 -Wire Wire Line - 3750 3350 3950 3350 -Connection ~ 3950 3350 -Wire Wire Line - 4850 3100 5050 3100 -Wire Wire Line - 4900 3700 5100 3700 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/full_sub/half_sub.sub b/src/SubcircuitLibrary/full_sub/half_sub.sub deleted file mode 100644 index a61a3409..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub.sub +++ /dev/null @@ -1,18 +0,0 @@ -* Subcircuit half_sub -.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir -* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends half_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml deleted file mode 100644 index 115ba703..00000000 --- a/src/SubcircuitLibrary/full_sub/half_sub_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/analysis b/src/SubcircuitLibrary/half_adder/analysis deleted file mode 100644 index 52ccc5ec..00000000 --- a/src/SubcircuitLibrary/half_adder/analysis +++ /dev/null @@ -1 +0,0 @@ -.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib deleted file mode 100644 index 68785220..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib +++ /dev/null @@ -1,63 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir b/src/SubcircuitLibrary/half_adder/half_adder.cir deleted file mode 100644 index 8b2e7e06..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder.cir +++ /dev/null @@ -1,11 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U2 1 4 3 d_xor -U3 1 4 2 d_and -U1 1 4 3 2 PORT - -.end diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir.out b/src/SubcircuitLibrary/half_adder/half_adder.cir.out deleted file mode 100644 index b1b6b1e7..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 - -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -* u1 1 4 3 2 port -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/half_adder/half_adder.pro b/src/SubcircuitLibrary/half_adder/half_adder.pro deleted file mode 100644 index 695ae0f6..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder.pro +++ /dev/null @@ -1,69 +0,0 @@ -update=Wed Jun 24 11:27:22 2015 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog -LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices -LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital -LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid -LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources -LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sch b/src/SubcircuitLibrary/half_adder/half_adder.sch deleted file mode 100644 index bf9bcbf0..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder.sch +++ /dev/null @@ -1,152 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Sources -LIBS:eSim_Subckt -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_xor U2 -U 1 1 558A946A -P 5650 3050 -F 0 "U2" H 5650 3050 60 0000 C CNN -F 1 "d_xor" H 5700 3150 47 0000 C CNN -F 2 "" H 5650 3050 60 0000 C CNN -F 3 "" H 5650 3050 60 0000 C CNN - 1 5650 3050 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 558A94D5 -P 5700 3800 -F 0 "U3" H 5700 3800 60 0000 C CNN -F 1 "d_and" H 5750 3900 60 0000 C CNN -F 2 "" H 5700 3800 60 0000 C CNN -F 3 "" H 5700 3800 60 0000 C CNN - 1 5700 3800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 558A94F6 -P 4150 3000 -F 0 "U1" H 4200 3100 30 0000 C CNN -F 1 "PORT" H 4150 3000 30 0000 C CNN -F 2 "" H 4150 3000 60 0000 C CNN -F 3 "" H 4150 3000 60 0000 C CNN - 1 4150 3000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 558A9543 -P 4150 3450 -F 0 "U1" H 4200 3550 30 0000 C CNN -F 1 "PORT" H 4150 3450 30 0000 C CNN -F 2 "" H 4150 3450 60 0000 C CNN -F 3 "" H 4150 3450 60 0000 C CNN - 2 4150 3450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 558A9573 -P 6650 3000 -F 0 "U1" H 6700 3100 30 0000 C CNN -F 1 "PORT" H 6650 3000 30 0000 C CNN -F 2 "" H 6650 3000 60 0000 C CNN -F 3 "" H 6650 3000 60 0000 C CNN - 3 6650 3000 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 558A9606 -P 6700 3750 -F 0 "U1" H 6750 3850 30 0000 C CNN -F 1 "PORT" H 6700 3750 30 0000 C CNN -F 2 "" H 6700 3750 60 0000 C CNN -F 3 "" H 6700 3750 60 0000 C CNN - 4 6700 3750 - -1 0 0 1 -$EndComp -Wire Wire Line - 5200 2950 4450 2950 -Wire Wire Line - 4450 2950 4450 3000 -Wire Wire Line - 4450 3000 4400 3000 -Wire Wire Line - 4400 3450 4550 3450 -Wire Wire Line - 4550 3450 4550 3050 -Wire Wire Line - 4550 3050 5200 3050 -Wire Wire Line - 5250 3700 5000 3700 -Wire Wire Line - 5000 3700 5000 2950 -Connection ~ 5000 2950 -Wire Wire Line - 5250 3800 4850 3800 -Wire Wire Line - 4850 3800 4850 3050 -Connection ~ 4850 3050 -Wire Wire Line - 6100 3000 6400 3000 -Wire Wire Line - 6150 3750 6450 3750 -Text Notes 4550 2950 0 60 ~ 0 -IN1\n\n -Text Notes 4600 3150 0 60 ~ 0 -IN2 -Text Notes 6200 2950 0 60 ~ 0 -SUM\n -Text Notes 6200 3650 0 60 ~ 0 -COUT\n -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sub b/src/SubcircuitLibrary/half_adder/half_adder.sub deleted file mode 100644 index e9f92223..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder.sub +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit half_adder -.subckt half_adder 1 4 3 2 -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends half_adder
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml deleted file mode 100644 index b915f0da..00000000 --- a/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/analysis b/src/SubcircuitLibrary/half_sub/analysis deleted file mode 100644 index 660a46cc..00000000 --- a/src/SubcircuitLibrary/half_sub/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/half_sub-cache.lib b/src/SubcircuitLibrary/half_sub/half_sub-cache.lib deleted file mode 100644 index bd15e664..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub-cache.lib +++ /dev/null @@ -1,95 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_xor -# -DEF d_xor U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_xor" 50 100 47 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 -A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 -A -25 -124 325 574 323 0 1 0 N 150 150 250 50 -A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 -P 2 0 1 0 150 -50 -200 -50 N -P 2 0 1 0 150 150 -200 150 N -X IN1 1 -450 100 215 R 50 43 1 1 I -X IN2 2 -450 0 215 R 50 43 1 1 I -X OUT 3 450 50 200 L 50 39 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir b/src/SubcircuitLibrary/half_sub/half_sub.cir deleted file mode 100644 index f20f0368..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub.cir +++ /dev/null @@ -1,14 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/half_sub/half_sub.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Wed 06 Mar 2019 08:19:54 PM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor -U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter -U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.cir.out b/src/SubcircuitLibrary/half_sub/half_sub.cir.out deleted file mode 100644 index 91816956..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub.cir.out +++ /dev/null @@ -1,24 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir - -* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 10e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/half_sub/half_sub.pro b/src/SubcircuitLibrary/half_sub/half_sub.pro deleted file mode 100644 index 90e3ded9..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub.pro +++ /dev/null @@ -1,74 +0,0 @@ -update=Wed 06 Mar 2019 11:10:38 PM IST -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice -LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt - diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sch b/src/SubcircuitLibrary/half_sub/half_sub.sch deleted file mode 100644 index e70b1675..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub.sch +++ /dev/null @@ -1,150 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_xor U3 -U 1 1 5C7FDDA3 -P 4400 3150 -F 0 "U3" H 4400 3150 60 0000 C CNN -F 1 "d_xor" H 4450 3250 47 0000 C CNN -F 2 "" H 4400 3150 60 0000 C CNN -F 3 "" H 4400 3150 60 0000 C CNN - 1 4400 3150 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U2 -U 1 1 5C7FDDD8 -P 3400 3750 -F 0 "U2" H 3400 3650 60 0000 C CNN -F 1 "d_inverter" H 3400 3900 60 0000 C CNN -F 2 "" H 3450 3700 60 0000 C CNN -F 3 "" H 3450 3700 60 0000 C CNN - 1 3400 3750 - 1 0 0 -1 -$EndComp -$Comp -L d_and U4 -U 1 1 5C7FDE57 -P 4450 3750 -F 0 "U4" H 4450 3750 60 0000 C CNN -F 1 "d_and" H 4500 3850 60 0000 C CNN -F 2 "" H 4450 3750 60 0000 C CNN -F 3 "" H 4450 3750 60 0000 C CNN - 1 4450 3750 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 3150 3950 3650 -Wire Wire Line - 3950 3650 4000 3650 -Wire Wire Line - 3700 3750 4000 3750 -Wire Wire Line - 3100 3750 3100 3050 -Wire Wire Line - 2950 3050 3950 3050 -$Comp -L PORT U1 -U 1 1 5C7FDF5A -P 2700 3050 -F 0 "U1" H 2750 3150 30 0000 C CNN -F 1 "PORT" H 2700 3050 30 0000 C CNN -F 2 "" H 2700 3050 60 0000 C CNN -F 3 "" H 2700 3050 60 0000 C CNN - 1 2700 3050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C7FDF97 -P 3500 3350 -F 0 "U1" H 3550 3450 30 0000 C CNN -F 1 "PORT" H 3500 3350 30 0000 C CNN -F 2 "" H 3500 3350 60 0000 C CNN -F 3 "" H 3500 3350 60 0000 C CNN - 2 3500 3350 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C7FE00A -P 5300 3100 -F 0 "U1" H 5350 3200 30 0000 C CNN -F 1 "PORT" H 5300 3100 30 0000 C CNN -F 2 "" H 5300 3100 60 0000 C CNN -F 3 "" H 5300 3100 60 0000 C CNN - 3 5300 3100 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C7FE064 -P 5350 3700 -F 0 "U1" H 5400 3800 30 0000 C CNN -F 1 "PORT" H 5350 3700 30 0000 C CNN -F 2 "" H 5350 3700 60 0000 C CNN -F 3 "" H 5350 3700 60 0000 C CNN - 4 5350 3700 - -1 0 0 1 -$EndComp -Connection ~ 3100 3050 -Wire Wire Line - 3750 3350 3950 3350 -Connection ~ 3950 3350 -Wire Wire Line - 4850 3100 5050 3100 -Wire Wire Line - 4900 3700 5100 3700 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/half_sub/half_sub.sub b/src/SubcircuitLibrary/half_sub/half_sub.sub deleted file mode 100644 index a61a3409..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub.sub +++ /dev/null @@ -1,18 +0,0 @@ -* Subcircuit half_sub -.subckt half_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/half_sub/half_sub.cir -* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor -* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter -* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u3 -a2 net-_u1-pad1_ net-_u2-pad2_ u2 -a3 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u1-pad4_ u4 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u3 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends half_sub
\ No newline at end of file diff --git a/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml b/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml deleted file mode 100644 index 115ba703..00000000 --- a/src/SubcircuitLibrary/half_sub/half_sub_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u2><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/NPN.lib b/src/SubcircuitLibrary/lm555n/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/lm555n/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis deleted file mode 100644 index a0953567..00000000 --- a/src/SubcircuitLibrary/lm555n/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib b/src/SubcircuitLibrary/lm555n/lm555n-cache.lib deleted file mode 100644 index 824af11e..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n-cache.lib +++ /dev/null @@ -1,205 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# GND-RESCUE-lm555n -# -DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 75 50 H I C CNN -F1 "PWR_FLAG" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -X pwr 1 0 0 0 U 50 50 0 0 w -P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N -ENDDRAW -ENDDEF -# -# R-RESCUE-lm555n -# -DEF R-RESCUE-lm555n R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# VCVS -# -DEF VCVS E 0 40 Y Y 1 F N -F0 "E" 0 150 50 H V C CNN -F1 "VCVS" -200 -50 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# adc_bridge_1 -# -DEF adc_bridge_1 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "adc_bridge_1" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -50 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X OUT1 2 550 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_inverter -# -DEF d_inverter U 0 40 Y Y 1 F N -F0 "U" 0 -100 60 H V C CNN -F1 "d_inverter" 0 150 60 H V C CNN -F2 "" 50 -50 60 H V C CNN -F3 "" 50 -50 60 H V C CNN -DRAW -P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N -X ~ 1 -300 0 200 R 50 50 1 1 I -X ~ 2 300 0 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# d_srlatch -# -DEF d_srlatch U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_srlatch" 50 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S 600 550 -600 -600 0 1 0 N -X S 1 -800 400 200 R 50 50 1 1 I -X R 2 -800 -450 200 R 50 50 1 1 I -X EN 3 -800 0 200 R 50 50 1 1 I -X Set 4 0 750 200 D 50 50 1 1 I -X Reset 5 0 -800 200 U 50 50 1 1 I -X Out 6 800 400 200 L 50 50 1 1 O -X Nout 7 800 -450 200 L 50 50 1 1 O I -ENDDRAW -ENDDEF -# -# dac_bridge_1 -# -DEF dac_bridge_1 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "dac_bridge_1" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -50 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X OUT1 2 550 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# eSim_NPN -# -DEF eSim_NPN Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -ALIAS BC547 Q2N2222 -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 P -X B 2 -200 0 225 R 50 50 1 1 P -X E 3 100 -200 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# limit -# -DEF limit U 0 40 Y Y 1 F N -F0 "U" 50 -50 60 H V C CNN -F1 "limit" 50 50 60 H V C CNN -F2 "" 0 50 60 H V C CNN -F3 "" 0 50 60 H V C CNN -DRAW -C 300 0 0 0 1 0 N -P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N -X IN 1 -400 0 200 R 50 50 1 1 I -X OUT 2 600 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib b/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib deleted file mode 100644 index fffeca36..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n-rescue.lib +++ /dev/null @@ -1,18 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# d_inverter-RESCUE-lm555n -# -DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N -F0 "U" -150 100 40 H V C CNN -F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN -F2 "" 0 0 60 H I C CNN -F3 "" 0 0 60 H I C CNN -DRAW -P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N -X in 1 -250 0 150 R 25 25 1 1 I -X out 2 250 0 150 L 25 25 1 1 O I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir deleted file mode 100644 index 682d4945..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n.cir +++ /dev/null @@ -1,31 +0,0 @@ -* /home/ash98/Downloads/lm555n/lm555n.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -E2 Net-_E2-Pad1_ GND /c /d 10000 -U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT -R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 -R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 -R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 -E1 Net-_E1-Pad1_ GND /b /a 10000 -R4 /b /a 2E6 -R5 /c /d 2E6 -R3 /c Net-_Q1-Pad3_ 5000 -R2 /a /c 5000 -R1 Net-_R1-Pad1_ /a 5000 -U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch -U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter -U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 -U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 -U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 -U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit -U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit -U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 -U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 -Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN - -.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out deleted file mode 100644 index a81070a1..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out +++ /dev/null @@ -1,42 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist -.include npn_1.lib -* Inverter d_inverter -* SR Latch d_srlatch -e2 18 0 23 14 10000 -* Limiter limit8 -* Digital to Analog converter dac8 -* Analog to Digital converter adc8 -u1 22 14 7 6 15 16 3 13 port -r8 9 2 1500 -q1 3 2 22 npn_1 -r7 18 20 25 -r6 17 19 25 -e1 17 0 16 15 10000 -r4 16 15 2e6 -r5 23 14 2e6 -r3 23 22 5000 -r2 15 23 5000 -r1 13 15 5000 -a1 5 21 u5 -.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) -a2 1 4 5 21 21 8 10 u6 -.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 -+sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 -+sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) -a3 19 11 u4 -a4 20 12 u4 -.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) -a5 [8] [7] u3 -a6 [10] [9] u3 -.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) -a7 [11] [4] u2 -a8 [12] [1] u2 -a9 [6] [5] u2 -.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) - -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro deleted file mode 100644 index 0a5408b6..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n.pro +++ /dev/null @@ -1,57 +0,0 @@ -update=Tue Apr 2 17:35:59 2019 -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/FreeEDA/library -[eeschema/libraries] -LibName1=lm555n-rescue -LibName2=power -LibName3=device -LibName4=transistors -LibName5=conn -LibName6=linear -LibName7=regul -LibName8=74xx -LibName9=cmos4000 -LibName10=adc-dac -LibName11=memory -LibName12=xilinx -LibName13=special -LibName14=microcontrollers -LibName15=dsp -LibName16=microchip -LibName17=analog_switches -LibName18=motorola -LibName19=texas -LibName20=intel -LibName21=audio -LibName22=interface -LibName23=digital-audio -LibName24=philips -LibName25=display -LibName26=cypress -LibName27=siliconi -LibName28=opto -LibName29=atmel -LibName30=contrib -LibName31=valves -LibName32=analogSpice -LibName33=analogXSpice -LibName34=converterSpice -LibName35=digitalSpice -LibName36=linearSpice -LibName37=measurementSpice -LibName38=portSpice -LibName39=sourcesSpice -LibName40=digitalXSpice -LibName41=eSim_User -LibName42=eSim_Subckt -LibName43=eSim_Sources -LibName44=eSim_PSpice -LibName45=eSim_Power -LibName46=eSim_Plot -LibName47=eSim_Miscellaneous -LibName48=eSim_Hybrid -LibName49=eSim_Digital -LibName50=eSim_Devices -LibName51=eSim_Analog diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch deleted file mode 100644 index 28110b13..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n.sch +++ /dev/null @@ -1,518 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:lm555n-rescue -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:eSim_Sources -LIBS:eSim_PSpice -LIBS:eSim_Power -LIBS:eSim_Plot -LIBS:eSim_Miscellaneous -LIBS:eSim_Hybrid -LIBS:eSim_Digital -LIBS:eSim_Devices -LIBS:eSim_Analog -LIBS:lm555n-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "17 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3700 3050 0 60 ~ 0 -IC 555 -Wire Wire Line - 2650 3000 2850 3000 -Wire Wire Line - 2650 4750 2650 4650 -Connection ~ 2350 3550 -Connection ~ 2350 4900 -Wire Wire Line - 2350 4100 2350 4200 -Wire Wire Line - 9100 4900 9100 4800 -Wire Wire Line - 8500 4600 8500 4250 -Wire Wire Line - 3350 3250 3050 3250 -Wire Wire Line - 3050 3250 3050 3750 -Wire Wire Line - 3500 4350 3500 4500 -Wire Wire Line - 3650 3550 4200 3550 -Wire Wire Line - 3850 3250 4200 3250 -Wire Wire Line - 3150 3550 3150 3700 -Wire Wire Line - 3150 3700 3500 3700 -Wire Wire Line - 3500 3700 3500 3750 -Connection ~ 3500 4450 -Wire Wire Line - 3700 4450 3700 4400 -Wire Wire Line - 3050 4350 3050 4450 -Wire Wire Line - 3050 4450 3700 4450 -Wire Wire Line - 9100 4250 9000 4250 -Wire Wire Line - 9100 4400 9100 4350 -Wire Wire Line - 9100 4350 9200 4350 -Wire Wire Line - 10100 2950 10350 2950 -Wire Wire Line - 2350 4900 2350 4700 -Wire Wire Line - 2350 3500 2350 3600 -Wire Wire Line - 2250 3000 2350 3000 -Wire Wire Line - 2350 4150 2650 4150 -Connection ~ 2350 4150 -Wire Wire Line - 2250 3550 2650 3550 -Wire Wire Line - 2650 3550 2650 3500 -Wire Wire Line - 4300 4750 4300 4650 -Text Label 2800 4100 0 60 ~ 0 -d -$Comp -L VCVS E2 -U 1 1 50AA12FF -P 3000 4050 -F 0 "E2" H 2800 4150 50 0000 C CNN -F 1 "10000" H 2800 4000 50 0000 C CNN -F 2 "" H 3000 4050 60 0001 C CNN -F 3 "" H 3000 4050 60 0001 C CNN - 1 3000 4050 - 0 1 1 0 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 50AA39A3 -P 3700 4400 -F 0 "#FLG01" H 3700 4670 30 0001 C CNN -F 1 "PWR_FLAG" H 3700 4630 30 0000 C CNN -F 2 "" H 3700 4400 60 0001 C CNN -F 3 "" H 3700 4400 60 0001 C CNN - 1 3700 4400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 50AA2210 -P 2000 3550 -F 0 "U1" H 2000 3500 30 0000 C CNN -F 1 "PORT" H 2000 3550 30 0000 C CNN -F 2 "" H 2000 3550 60 0001 C CNN -F 3 "" H 2000 3550 60 0001 C CNN - 5 2000 3550 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 50AA21C7 -P 2000 4900 -F 0 "U1" H 2000 4850 30 0000 C CNN -F 1 "PORT" H 2000 4900 30 0000 C CNN -F 2 "" H 2000 4900 60 0001 C CNN -F 3 "" H 2000 4900 60 0001 C CNN - 1 2000 4900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 50AA21BC -P 2650 5000 -F 0 "U1" H 2650 4950 30 0000 C CNN -F 1 "PORT" H 2650 5000 30 0000 C CNN -F 2 "" H 2650 5000 60 0001 C CNN -F 3 "" H 2650 5000 60 0001 C CNN - 2 2650 5000 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 4 1 50AA21A9 -P 4300 5000 -F 0 "U1" H 4300 4950 30 0000 C CNN -F 1 "PORT" H 4300 5000 30 0000 C CNN -F 2 "" H 4300 5000 60 0001 C CNN -F 3 "" H 4300 5000 60 0001 C CNN - 4 4300 5000 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 7 1 50AA21A0 -P 9450 4350 -F 0 "U1" H 9450 4300 30 0000 C CNN -F 1 "PORT" H 9450 4350 30 0000 C CNN -F 2 "" H 9450 4350 60 0001 C CNN -F 3 "" H 9450 4350 60 0001 C CNN - 7 9450 4350 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 3 1 50AA2181 -P 10600 2950 -F 0 "U1" H 10600 2900 30 0000 C CNN -F 1 "PORT" H 10600 2950 30 0000 C CNN -F 2 "" H 10600 2950 60 0001 C CNN -F 3 "" H 10600 2950 60 0001 C CNN - 3 10600 2950 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 6 1 50AA2171 -P 3100 3000 -F 0 "U1" H 3100 2950 30 0000 C CNN -F 1 "PORT" H 3100 3000 30 0000 C CNN -F 2 "" H 3100 3000 60 0001 C CNN -F 3 "" H 3100 3000 60 0001 C CNN - 6 3100 3000 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 8 1 50AA2162 -P 2000 3000 -F 0 "U1" H 2000 2950 30 0000 C CNN -F 1 "PORT" H 2000 3000 30 0000 C CNN -F 2 "" H 2000 3000 60 0001 C CNN -F 3 "" H 2000 3000 60 0001 C CNN - 8 2000 3000 - 1 0 0 -1 -$EndComp -$Comp -L R-RESCUE-lm555n R8 -U 1 1 50AA20DA -P 8750 4250 -F 0 "R8" V 8830 4250 50 0000 C CNN -F 1 "1500" V 8750 4250 50 0000 C CNN -F 2 "" H 8750 4250 60 0001 C CNN -F 3 "" H 8750 4250 60 0001 C CNN - 1 8750 4250 - 0 1 1 0 -$EndComp -$Comp -L GND-RESCUE-lm555n #PWR02 -U 1 1 50AA140C -P 3500 4500 -F 0 "#PWR02" H 3500 4500 30 0001 C CNN -F 1 "GND" H 3500 4430 30 0001 C CNN -F 2 "" H 3500 4500 60 0001 C CNN -F 3 "" H 3500 4500 60 0001 C CNN - 1 3500 4500 - 1 0 0 -1 -$EndComp -Text Label 2800 4000 0 60 ~ 0 -c -Text Label 2650 4650 0 60 ~ 0 -d -Text Label 2650 4150 0 60 ~ 0 -c -$Comp -L R-RESCUE-lm555n R7 -U 1 1 50AA12F7 -P 3600 3250 -F 0 "R7" V 3680 3250 50 0000 C CNN -F 1 "25" V 3600 3250 50 0000 C CNN -F 2 "" H 3600 3250 60 0001 C CNN -F 3 "" H 3600 3250 60 0001 C CNN - 1 3600 3250 - 0 -1 -1 0 -$EndComp -$Comp -L R-RESCUE-lm555n R6 -U 1 1 50AA12B0 -P 3400 3550 -F 0 "R6" V 3480 3550 50 0000 C CNN -F 1 "25" V 3400 3550 50 0000 C CNN -F 2 "" H 3400 3550 60 0001 C CNN -F 3 "" H 3400 3550 60 0001 C CNN - 1 3400 3550 - 0 -1 -1 0 -$EndComp -Text Label 3250 4000 0 60 ~ 0 -b -Text Label 3250 4100 0 60 ~ 0 -a -Text Label 2650 3000 0 60 ~ 0 -b -Text Label 2650 3500 0 60 ~ 0 -a -$Comp -L VCVS E1 -U 1 1 50AA11B6 -P 3450 4050 -F 0 "E1" H 3250 4150 50 0000 C CNN -F 1 "10000" H 3250 4000 50 0000 C CNN -F 2 "" H 3450 4050 60 0001 C CNN -F 3 "" H 3450 4050 60 0001 C CNN - 1 3450 4050 - 0 1 1 0 -$EndComp -$Comp -L R-RESCUE-lm555n R4 -U 1 1 50A9E00B -P 2650 3250 -F 0 "R4" V 2730 3250 50 0000 C CNN -F 1 "2E6" V 2650 3250 50 0000 C CNN -F 2 "" H 2650 3250 60 0001 C CNN -F 3 "" H 2650 3250 60 0001 C CNN - 1 2650 3250 - 1 0 0 -1 -$EndComp -$Comp -L R-RESCUE-lm555n R5 -U 1 1 50A9E001 -P 2650 4400 -F 0 "R5" V 2730 4400 50 0000 C CNN -F 1 "2E6" V 2650 4400 50 0000 C CNN -F 2 "" H 2650 4400 60 0001 C CNN -F 3 "" H 2650 4400 60 0001 C CNN - 1 2650 4400 - 1 0 0 -1 -$EndComp -$Comp -L R-RESCUE-lm555n R3 -U 1 1 50A9DF09 -P 2350 4450 -F 0 "R3" V 2430 4450 50 0000 C CNN -F 1 "5000" V 2350 4450 50 0000 C CNN -F 2 "" H 2350 4450 60 0001 C CNN -F 3 "" H 2350 4450 60 0001 C CNN - 1 2350 4450 - 1 0 0 -1 -$EndComp -$Comp -L R-RESCUE-lm555n R2 -U 1 1 50A9DF03 -P 2350 3850 -F 0 "R2" V 2430 3850 50 0000 C CNN -F 1 "5000" V 2350 3850 50 0000 C CNN -F 2 "" H 2350 3850 60 0001 C CNN -F 3 "" H 2350 3850 60 0001 C CNN - 1 2350 3850 - 1 0 0 -1 -$EndComp -$Comp -L R-RESCUE-lm555n R1 -U 1 1 50A9DEFE -P 2350 3250 -F 0 "R1" V 2430 3250 50 0000 C CNN -F 1 "5000" V 2350 3250 50 0000 C CNN -F 2 "" H 2350 3250 60 0001 C CNN -F 3 "" H 2350 3250 60 0001 C CNN - 1 2350 3250 - 1 0 0 -1 -$EndComp -$Comp -L d_srlatch U8 -U 1 1 5E01E563 -P 8000 3350 -F 0 "U8" H 8000 3350 60 0000 C CNN -F 1 "d_srlatch" H 8050 3500 60 0000 C CNN -F 2 "" H 8000 3350 60 0000 C CNN -F 3 "" H 8000 3350 60 0000 C CNN - 1 8000 3350 - 1 0 0 -1 -$EndComp -$Comp -L d_inverter U7 -U 1 1 5E01F10F -P 7450 4400 -F 0 "U7" H 7450 4300 60 0000 C CNN -F 1 "d_inverter" H 7450 4550 60 0000 C CNN -F 2 "" H 7500 4350 60 0000 C CNN -F 3 "" H 7500 4350 60 0000 C CNN - 1 7450 4400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 7750 4400 8150 4400 -Wire Wire Line - 8000 4400 8000 4150 -$Comp -L adc_bridge_1 U5 -U 1 1 5E01F2C7 -P 6350 3400 -F 0 "U5" H 6350 3400 60 0000 C CNN -F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN -F 2 "" H 6350 3400 60 0000 C CNN -F 3 "" H 6350 3400 60 0000 C CNN - 1 6350 3400 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6900 3350 7200 3350 -Wire Wire Line - 4300 4650 5600 4650 -Wire Wire Line - 5600 4650 5600 3350 -Wire Wire Line - 5600 3350 5750 3350 -$Comp -L adc_bridge_1 U4 -U 1 1 5E01F3F2 -P 6350 3000 -F 0 "U4" H 6350 3000 60 0000 C CNN -F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN -F 2 "" H 6350 3000 60 0000 C CNN -F 3 "" H 6350 3000 60 0000 C CNN - 1 6350 3000 - 1 0 0 -1 -$EndComp -$Comp -L adc_bridge_1 U6 -U 1 1 5E01F469 -P 6350 3850 -F 0 "U6" H 6350 3850 60 0000 C CNN -F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN -F 2 "" H 6350 3850 60 0000 C CNN -F 3 "" H 6350 3850 60 0000 C CNN - 1 6350 3850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6900 3800 7200 3800 -Wire Wire Line - 7200 2950 6900 2950 -$Comp -L limit U3 -U 1 1 5E01F5DC -P 4900 2950 -F 0 "U3" H 4950 2900 60 0000 C CNN -F 1 "limit" H 4950 3000 60 0000 C CNN -F 2 "" H 4900 3000 60 0000 C CNN -F 3 "" H 4900 3000 60 0000 C CNN - 1 4900 2950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5500 2950 5750 2950 -Wire Wire Line - 4200 3250 4200 2950 -Wire Wire Line - 4200 2950 4500 2950 -$Comp -L limit U2 -U 1 1 5E01F79D -P 4800 3800 -F 0 "U2" H 4850 3750 60 0000 C CNN -F 1 "limit" H 4850 3850 60 0000 C CNN -F 2 "" H 4800 3850 60 0000 C CNN -F 3 "" H 4800 3850 60 0000 C CNN - 1 4800 3800 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5400 3800 5750 3800 -Wire Wire Line - 4200 3550 4200 3800 -Wire Wire Line - 4200 3800 4400 3800 -Wire Wire Line - 7050 3350 7050 4400 -Wire Wire Line - 7050 4400 7150 4400 -Connection ~ 7050 3350 -Wire Wire Line - 8000 2600 8150 2600 -Wire Wire Line - 8150 2600 8150 4400 -Connection ~ 8000 4400 -$Comp -L dac_bridge_1 U9 -U 1 1 5E01FCD2 -P 9550 3000 -F 0 "U9" H 9550 3000 60 0000 C CNN -F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN -F 2 "" H 9550 3000 60 0000 C CNN -F 3 "" H 9550 3000 60 0000 C CNN - 1 9550 3000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8800 2950 8950 2950 -$Comp -L dac_bridge_1 U10 -U 1 1 5E01FE8E -P 9600 3850 -F 0 "U10" H 9600 3850 60 0000 C CNN -F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN -F 2 "" H 9600 3850 60 0000 C CNN -F 3 "" H 9600 3850 60 0000 C CNN - 1 9600 3850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 9000 3800 8800 3800 -Wire Wire Line - 9100 4000 9100 4250 -Wire Wire Line - 9100 4000 10300 4000 -Wire Wire Line - 10300 4000 10300 3800 -Wire Wire Line - 10300 3800 10150 3800 -$Comp -L eSim_NPN Q1 -U 1 1 5E01E782 -P 9000 4600 -F 0 "Q1" H 8900 4650 50 0000 R CNN -F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN -F 2 "" H 9200 4700 29 0000 C CNN -F 3 "" H 9000 4600 60 0000 C CNN - 1 9000 4600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8800 4600 8500 4600 -Wire Wire Line - 2250 4900 9100 4900 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub deleted file mode 100644 index b524f5c6..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n.sub +++ /dev/null @@ -1,39 +0,0 @@ -* Subcircuit lm555n -.subckt lm555n 22 14 7 6 15 16 3 13 -.include npn_1.lib -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist -* Inverter d_inverter -* SR Latch d_srlatch -e2 18 0 23 14 10000 -* Limiter limit8 -* Digital to Analog converter dac8 -* Analog to Digital converter adc8 -r8 9 2 1500 -q1 3 2 22 npn_1 -r7 18 20 25 -r6 17 19 25 -e1 17 0 16 15 10000 -r4 16 15 2e6 -r5 23 14 2e6 -r3 23 22 5000 -r2 15 23 5000 -r1 13 15 5000 -a1 5 21 u5 -.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) -a2 1 4 5 21 21 8 10 u6 -.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 -+sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 -+sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) -a3 19 11 u4 -a4 20 12 u4 -.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) -a5 [8] [7] u3 -a6 [10] [9] u3 -.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) -a7 [11] [4] u2 -a8 [12] [1] u2 -a9 [6] [5] u2 -.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) -*control statements - -.ends lm555n diff --git a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml deleted file mode 100644 index 58d33ec5..00000000 --- a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm555n/npn_1.lib b/src/SubcircuitLibrary/lm555n/npn_1.lib deleted file mode 100644 index a1818ed8..00000000 --- a/src/SubcircuitLibrary/lm555n/npn_1.lib +++ /dev/null @@ -1,29 +0,0 @@ -.model npn_1 NPN( -+ Vtf=1.7 -+ Cjc=0.5p -+ Nc=2 -+ Tr=46.91n -+ Ne=1.307 -+ Cje=0.5p -+ Isc=0 -+ Xtb=1.5 -+ Rb=500 -+ Rc=1 -+ Tf=411.1p -+ Xti=3 -+ Ikr=0 -+ Bf=125 -+ Fc=.5 -+ Ise=14.34f -+ Br=6.092 -+ Ikf=.2847 -+ Mje=.377 -+ Mjc=.3416 -+ Vaf=74.03 -+ Vjc=.75 -+ Vje=.75 -+ Xtf=3 -+ Itf=.6 -+ Is=14.34f -+ Eg=1.11 -)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/NPN.lib b/src/SubcircuitLibrary/lm7805/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/lm7805/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm7805/PNP.lib b/src/SubcircuitLibrary/lm7805/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/lm7805/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/lm7805/Q_PNP.lib b/src/SubcircuitLibrary/lm7805/Q_PNP.lib deleted file mode 100644 index 154ed2d8..00000000 --- a/src/SubcircuitLibrary/lm7805/Q_PNP.lib +++ /dev/null @@ -1 +0,0 @@ -.model Q_PNP PNP(IS=10F NF=1.16 NR=1.16 BF=80 CJC=1P CJE=2P TF=10P TR=1N)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/analysis b/src/SubcircuitLibrary/lm7805/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/lm7805/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib b/src/SubcircuitLibrary/lm7805/lm7805-cache.lib deleted file mode 100644 index aaf8454e..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805-cache.lib +++ /dev/null @@ -1,136 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -F2 "" -70 0 50 V V C CNN -F3 "" 0 0 50 H V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S -40 -100 40 100 0 1 10 N -X ~ 1 0 150 50 D 50 50 1 1 P -X ~ 2 0 -150 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_NPN -# -DEF eSim_NPN Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -ALIAS BC547 Q2N2222 -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 P -X B 2 -200 0 225 R 50 50 1 1 P -X E 3 100 -200 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# eSim_PNP -# -DEF eSim_PNP Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_PNP" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F -X C 1 100 200 100 D 50 50 1 1 P -X B 2 -200 0 225 R 50 50 1 1 P -X E 3 100 -200 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# zener -# -DEF zener U 0 40 Y Y 1 F N -F0 "U" -50 -100 60 H V C CNN -F1 "zener" 0 100 60 H V C CNN -F2 "" 50 0 60 H V C CNN -F3 "" 50 0 60 H V C CNN -DRAW -P 2 0 1 0 100 -50 50 -100 N -P 2 0 1 0 100 50 100 -50 N -P 2 0 1 0 100 50 150 100 N -P 4 0 1 0 0 50 0 -50 100 0 0 50 N -X ~ IN -200 0 200 R 50 43 1 1 I -X ~ OUT 300 0 200 L 50 43 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir b/src/SubcircuitLibrary/lm7805/lm7805.cir deleted file mode 100644 index 081b4920..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805.cir +++ /dev/null @@ -1,51 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\lm7805\lm7805.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/26/19 17:24:42 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -R1 Net-_Q16-Pad1_ Net-_Q1-Pad2_ 100k -R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500 -R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3k -R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7k -U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ zener -Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN -R5 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 500 -Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN -Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN -R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1k -Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q10-Pad3_ eSim_NPN -R7 Net-_Q3-Pad2_ Net-_Q10-Pad3_ 6k -Q6 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q6-Pad3_ eSim_NPN -R10 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 1k -Q7 Net-_Q2-Pad1_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN -Q8 Net-_Q7-Pad3_ Net-_Q12-Pad3_ Net-_Q2-Pad3_ eSim_NPN -Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN -R12 Net-_Q12-Pad3_ Net-_Q2-Pad3_ 6k -R9 Net-_Q2-Pad3_ Net-_C1-Pad2_ 20k -Q5 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_PNP -Q9 Net-_Q10-Pad1_ Net-_Q2-Pad1_ Net-_Q9-Pad3_ eSim_PNP -R8 Net-_Q16-Pad1_ Net-_Q5-Pad3_ 100 -R11 Net-_Q16-Pad1_ Net-_Q9-Pad3_ 50 -Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN -Q11 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN -Q13 Net-_C1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad3_ eSim_NPN -R13 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 6k -C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p -R14 Net-_Q10-Pad1_ Net-_C1-Pad1_ 6k -Q14 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP -Q15 Net-_Q10-Pad1_ Net-_Q15-Pad2_ Net-_Q12-Pad1_ eSim_NPN -R17 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 5k -R16 Net-_Q12-Pad1_ Net-_Q12-Pad2_ 1.385k -R15 Net-_Q16-Pad1_ Net-_R15-Pad2_ 10k -U2 Net-_Q15-Pad2_ Net-_R15-Pad2_ zener -Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN -Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN -R18 Net-_Q16-Pad3_ Net-_Q12-Pad1_ 200 -R20 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 0.3 -R19 Net-_Q17-Pad3_ Net-_Q15-Pad2_ 240 -U3 Net-_Q16-Pad1_ Net-_Q10-Pad3_ Net-_Q12-Pad1_ PORT - -.end diff --git a/src/SubcircuitLibrary/lm7805/lm7805.cir.out b/src/SubcircuitLibrary/lm7805/lm7805.cir.out deleted file mode 100644 index f122fba6..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805.cir.out +++ /dev/null @@ -1,60 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir - -.include PNP.lib -.include NPN.lib -r1 net-_q16-pad1_ net-_q1-pad2_ 100k -r2 net-_q16-pad1_ net-_q1-pad1_ 500 -r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k -r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k -* u1 net-_q10-pad3_ net-_q1-pad2_ zener -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -r5 net-_q10-pad2_ net-_q10-pad3_ 500 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 -r6 net-_q2-pad3_ net-_q3-pad1_ 1k -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 -r7 net-_q3-pad2_ net-_q10-pad3_ 6k -q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 -r10 net-_q6-pad3_ net-_q10-pad3_ 1k -q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 -q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 -q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 -r12 net-_q12-pad3_ net-_q2-pad3_ 6k -r9 net-_q2-pad3_ net-_c1-pad2_ 20k -q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A -q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A -r8 net-_q16-pad1_ net-_q5-pad3_ 100 -r11 net-_q16-pad1_ net-_q9-pad3_ 50 -q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 -q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 -q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 -r13 net-_q11-pad3_ net-_q10-pad3_ 6k -c1 net-_c1-pad1_ net-_c1-pad2_ 30p -r14 net-_q10-pad1_ net-_c1-pad1_ 6k -q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A -q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 -r17 net-_q12-pad2_ net-_q10-pad3_ 5k -r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k -r15 net-_q16-pad1_ net-_r15-pad2_ 10k -* u2 net-_q15-pad2_ net-_r15-pad2_ zener -q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 -q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 -r18 net-_q16-pad3_ net-_q12-pad1_ 200 -r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 -r19 net-_q17-pad3_ net-_q15-pad2_ 240 -* u3 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ port -a1 net-_q10-pad3_ net-_q1-pad2_ u1 -a2 net-_q15-pad2_ net-_r15-pad2_ u2 -* Schematic Name: zener, NgSpice Name: zener -.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -* Schematic Name: zener, NgSpice Name: zener -.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/lm7805/lm7805.pro b/src/SubcircuitLibrary/lm7805/lm7805.pro deleted file mode 100644 index d410e2fa..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=Mon Aug 26 14:34:23 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Plot -LibName7=eSim_Power -LibName8=eSim_PSpice -LibName9=eSim_Sources -LibName10=eSim_Subckt -LibName11=eSim_User - diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sch b/src/SubcircuitLibrary/lm7805/lm7805.sch deleted file mode 100644 index 701d163d..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805.sch +++ /dev/null @@ -1,757 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:lm7805-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L R R1 -U 1 1 5CE41429 -P 1250 1600 -F 0 "R1" V 1330 1600 50 0000 C CNN -F 1 "100k" V 1250 1600 50 0000 C CNN -F 2 "" V 1180 1600 50 0001 C CNN -F 3 "" H 1250 1600 50 0001 C CNN - 1 1250 1600 - 1 0 0 -1 -$EndComp -$Comp -L R R2 -U 1 1 5CE4148B -P 1950 1600 -F 0 "R2" V 2030 1600 50 0000 C CNN -F 1 "500" V 1950 1600 50 0000 C CNN -F 2 "" V 1880 1600 50 0001 C CNN -F 3 "" H 1950 1600 50 0001 C CNN - 1 1950 1600 - 1 0 0 -1 -$EndComp -$Comp -L R R3 -U 1 1 5CE414A5 -P 1950 3050 -F 0 "R3" V 2030 3050 50 0000 C CNN -F 1 "3.3k" V 1950 3050 50 0000 C CNN -F 2 "" V 1880 3050 50 0001 C CNN -F 3 "" H 1950 3050 50 0001 C CNN - 1 1950 3050 - 1 0 0 -1 -$EndComp -$Comp -L R R4 -U 1 1 5CE414CA -P 1950 3750 -F 0 "R4" V 2030 3750 50 0000 C CNN -F 1 "2.7k" V 1950 3750 50 0000 C CNN -F 2 "" V 1880 3750 50 0001 C CNN -F 3 "" H 1950 3750 50 0001 C CNN - 1 1950 3750 - 1 0 0 -1 -$EndComp -$Comp -L zener U1 -U 1 1 5CE414FA -P 1250 3350 -F 0 "U1" H 1200 3250 60 0000 C CNN -F 1 "zener" H 1250 3450 60 0000 C CNN -F 2 "" H 1300 3350 60 0000 C CNN -F 3 "" H 1300 3350 60 0000 C CNN - 1 1250 3350 - 0 -1 -1 0 -$EndComp -$Comp -L eSim_NPN Q1 -U 1 1 5CE41586 -P 1850 2350 -F 0 "Q1" H 1750 2400 50 0000 R CNN -F 1 "eSim_NPN" H 1800 2500 50 0000 R CNN -F 2 "" H 2050 2450 29 0000 C CNN -F 3 "" H 1850 2350 60 0000 C CNN - 1 1850 2350 - 1 0 0 -1 -$EndComp -$Comp -L R R5 -U 1 1 5CE418C5 -P 1950 4600 -F 0 "R5" V 2030 4600 50 0000 C CNN -F 1 "500" V 1950 4600 50 0000 C CNN -F 2 "" V 1880 4600 50 0001 C CNN -F 3 "" H 1950 4600 50 0001 C CNN - 1 1950 4600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1250 1750 1250 3050 -Wire Wire Line - 1250 1450 1250 1300 -Wire Wire Line - 1250 1300 1950 1300 -Wire Wire Line - 1950 1300 1950 1450 -Wire Wire Line - 1950 2150 1950 1750 -Wire Wire Line - 1950 2550 1950 2900 -Wire Wire Line - 1950 3200 1950 3600 -Wire Wire Line - 1950 3900 1950 4450 -Wire Wire Line - 1250 3550 1250 5200 -Wire Wire Line - 1250 5200 3200 5200 -Wire Wire Line - 1950 5200 1950 4750 -Wire Wire Line - 1650 2350 1250 2350 -Connection ~ 1250 2350 -$Comp -L eSim_NPN Q2 -U 1 1 5CE41D6C -P 2650 3350 -F 0 "Q2" H 2550 3400 50 0000 R CNN -F 1 "eSim_NPN" H 2600 3500 50 0000 R CNN -F 2 "" H 2850 3450 29 0000 C CNN -F 3 "" H 2650 3350 60 0000 C CNN - 1 2650 3350 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q4 -U 1 1 5CE41E26 -P 3100 4100 -F 0 "Q4" H 3000 4150 50 0000 R CNN -F 1 "eSim_NPN" H 3050 4250 50 0000 R CNN -F 2 "" H 3300 4200 29 0000 C CNN -F 3 "" H 3100 4100 60 0000 C CNN - 1 3100 4100 - 1 0 0 -1 -$EndComp -$Comp -L R R6 -U 1 1 5CE41EA8 -P 2750 3850 -F 0 "R6" V 2830 3850 50 0000 C CNN -F 1 "1k" V 2750 3850 50 0000 C CNN -F 2 "" V 2680 3850 50 0001 C CNN -F 3 "" H 2750 3850 50 0001 C CNN - 1 2750 3850 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q3 -U 1 1 5CE41EFE -P 2850 4650 -F 0 "Q3" H 2750 4700 50 0000 R CNN -F 1 "eSim_NPN" H 2800 4800 50 0000 R CNN -F 2 "" H 3050 4750 29 0000 C CNN -F 3 "" H 2850 4650 60 0000 C CNN - 1 2850 4650 - -1 0 0 -1 -$EndComp -Wire Wire Line - 2750 3550 2750 3700 -Wire Wire Line - 2750 4000 2750 4450 -Wire Wire Line - 2900 4100 2750 4100 -Connection ~ 2750 4100 -Wire Wire Line - 3200 4300 3200 4750 -Wire Wire Line - 3050 4650 3450 4650 -Wire Wire Line - 2450 3350 1950 3350 -Connection ~ 1950 3350 -Wire Wire Line - 2750 3600 3600 3600 -Wire Wire Line - 3200 3600 3200 3900 -Connection ~ 2750 3600 -$Comp -L R R7 -U 1 1 5CE42281 -P 3200 4900 -F 0 "R7" V 3280 4900 50 0000 C CNN -F 1 "6k" V 3200 4900 50 0000 C CNN -F 2 "" V 3130 4900 50 0001 C CNN -F 3 "" H 3200 4900 50 0001 C CNN - 1 3200 4900 - 1 0 0 -1 -$EndComp -Connection ~ 3200 4650 -Wire Wire Line - 3200 5050 3200 5250 -Connection ~ 1950 5200 -Wire Wire Line - 2750 4850 2750 5200 -Connection ~ 2750 5200 -$Comp -L eSim_NPN Q6 -U 1 1 5CE424FB -P 3650 4650 -F 0 "Q6" H 3550 4700 50 0000 R CNN -F 1 "eSim_NPN" H 3600 4800 50 0000 R CNN -F 2 "" H 3850 4750 29 0000 C CNN -F 3 "" H 3650 4650 60 0000 C CNN - 1 3650 4650 - 1 0 0 -1 -$EndComp -$Comp -L R R10 -U 1 1 5CE42584 -P 3750 5100 -F 0 "R10" V 3830 5100 50 0000 C CNN -F 1 "1k" V 3750 5100 50 0000 C CNN -F 2 "" V 3680 5100 50 0001 C CNN -F 3 "" H 3750 5100 50 0001 C CNN - 1 3750 5100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3750 4850 3750 4950 -Wire Wire Line - 3200 5250 3750 5250 -Connection ~ 3200 5200 -$Comp -L eSim_NPN Q7 -U 1 1 5CE427DA -P 3700 2750 -F 0 "Q7" H 3600 2800 50 0000 R CNN -F 1 "eSim_NPN" H 3650 2900 50 0000 R CNN -F 2 "" H 3900 2850 29 0000 C CNN -F 3 "" H 3700 2750 60 0000 C CNN - 1 3700 2750 - -1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q8 -U 1 1 5CE428D0 -P 3700 3400 -F 0 "Q8" H 3600 3450 50 0000 R CNN -F 1 "eSim_NPN" H 3650 3550 50 0000 R CNN -F 2 "" H 3900 3500 29 0000 C CNN -F 3 "" H 3700 3400 60 0000 C CNN - 1 3700 3400 - -1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q12 -U 1 1 5CE4293A -P 4350 3000 -F 0 "Q12" H 4250 3050 50 0000 R CNN -F 1 "eSim_NPN" H 4300 3150 50 0000 R CNN -F 2 "" H 4550 3100 29 0000 C CNN -F 3 "" H 4350 3000 60 0000 C CNN - 1 4350 3000 - -1 0 0 -1 -$EndComp -Wire Wire Line - 3600 2950 3600 3200 -Wire Wire Line - 4250 3200 4250 3400 -Wire Wire Line - 4250 3400 3900 3400 -Wire Wire Line - 4250 2750 4250 2800 -Wire Wire Line - 3900 2750 4250 2750 -Connection ~ 3200 3600 -$Comp -L R R12 -U 1 1 5CE42C4F -P 4350 3450 -F 0 "R12" V 4430 3450 50 0000 C CNN -F 1 "6k" V 4350 3450 50 0000 C CNN -F 2 "" V 4280 3450 50 0001 C CNN -F 3 "" H 4350 3450 50 0001 C CNN - 1 4350 3450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4350 3300 4250 3300 -Connection ~ 4250 3300 -Wire Wire Line - 3700 3600 4350 3600 -Wire Wire Line - 3700 3600 3700 3650 -Wire Wire Line - 3700 3650 3550 3650 -Wire Wire Line - 3550 3650 3550 3600 -Connection ~ 3550 3600 -$Comp -L R R9 -U 1 1 5CE42EA3 -P 3750 3950 -F 0 "R9" V 3830 3950 50 0000 C CNN -F 1 "20k" V 3750 3950 50 0000 C CNN -F 2 "" V 3680 3950 50 0001 C CNN -F 3 "" H 3750 3950 50 0001 C CNN - 1 3750 3950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3750 4100 3750 4450 -Wire Wire Line - 3750 3800 3750 3600 -Connection ~ 3750 3600 -Wire Wire Line - 2750 3150 2750 2450 -Wire Wire Line - 2750 2450 3600 2450 -Wire Wire Line - 3600 2450 3600 2550 -$Comp -L eSim_PNP Q5 -U 1 1 5CE43397 -P 3450 1700 -F 0 "Q5" H 3350 1750 50 0000 R CNN -F 1 "eSim_PNP" H 3400 1850 50 0000 R CNN -F 2 "" H 3650 1800 29 0000 C CNN -F 3 "" H 3450 1700 60 0000 C CNN - 1 3450 1700 - -1 0 0 1 -$EndComp -$Comp -L eSim_PNP Q9 -U 1 1 5CE4353C -P 4100 1700 -F 0 "Q9" H 4000 1750 50 0000 R CNN -F 1 "eSim_PNP" H 4050 1850 50 0000 R CNN -F 2 "" H 4300 1800 29 0000 C CNN -F 3 "" H 4100 1700 60 0000 C CNN - 1 4100 1700 - 1 0 0 1 -$EndComp -$Comp -L R R8 -U 1 1 5CE435B8 -P 3350 1250 -F 0 "R8" V 3430 1250 50 0000 C CNN -F 1 "100" V 3350 1250 50 0000 C CNN -F 2 "" V 3280 1250 50 0001 C CNN -F 3 "" H 3350 1250 50 0001 C CNN - 1 3350 1250 - 1 0 0 -1 -$EndComp -$Comp -L R R11 -U 1 1 5CE4368E -P 4200 1250 -F 0 "R11" V 4280 1250 50 0000 C CNN -F 1 "50" V 4200 1250 50 0000 C CNN -F 2 "" V 4130 1250 50 0001 C CNN -F 3 "" H 4200 1250 50 0001 C CNN - 1 4200 1250 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q10 -U 1 1 5CE43705 -P 4100 2200 -F 0 "Q10" H 4000 2250 50 0000 R CNN -F 1 "eSim_NPN" H 4050 2350 50 0000 R CNN -F 2 "" H 4300 2300 29 0000 C CNN -F 3 "" H 4100 2200 60 0000 C CNN - 1 4100 2200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3350 1400 3350 1500 -Wire Wire Line - 3650 1700 3900 1700 -Wire Wire Line - 4200 1400 4200 1500 -Wire Wire Line - 3350 1100 3350 1050 -Wire Wire Line - 1650 1050 7800 1050 -Wire Wire Line - 4200 1050 4200 1100 -Wire Wire Line - 4200 1900 4200 2000 -Wire Wire Line - 3750 1700 3750 2000 -Wire Wire Line - 3750 2000 3350 2000 -Wire Wire Line - 3350 1900 3350 2450 -Connection ~ 3750 1700 -Connection ~ 3350 2450 -Connection ~ 3350 2000 -Wire Wire Line - 2300 2200 3900 2200 -Wire Wire Line - 2300 2200 2300 4200 -Wire Wire Line - 2300 4200 1950 4200 -Connection ~ 1950 4200 -Wire Wire Line - 2200 2400 4200 2400 -Wire Wire Line - 2200 2400 2200 5200 -Connection ~ 2200 5200 -$Comp -L eSim_NPN Q11 -U 1 1 5CE4439E -P 4300 4400 -F 0 "Q11" H 4200 4450 50 0000 R CNN -F 1 "eSim_NPN" H 4250 4550 50 0000 R CNN -F 2 "" H 4500 4500 29 0000 C CNN -F 3 "" H 4300 4400 60 0000 C CNN - 1 4300 4400 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q13 -U 1 1 5CE44419 -P 4600 4800 -F 0 "Q13" H 4500 4850 50 0000 R CNN -F 1 "eSim_NPN" H 4550 4950 50 0000 R CNN -F 2 "" H 4800 4900 29 0000 C CNN -F 3 "" H 4600 4800 60 0000 C CNN - 1 4600 4800 - 1 0 0 -1 -$EndComp -$Comp -L R R13 -U 1 1 5CE444B9 -P 4400 5050 -F 0 "R13" V 4480 5050 50 0000 C CNN -F 1 "6k" V 4400 5050 50 0000 C CNN -F 2 "" V 4330 5050 50 0001 C CNN -F 3 "" H 4400 5050 50 0001 C CNN - 1 4400 5050 - 1 0 0 -1 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5CE4451D -P 4050 4150 -F 0 "C1" H 4075 4250 50 0000 L CNN -F 1 "30p" H 4075 4050 50 0000 L CNN -F 2 "" H 4088 4000 30 0000 C CNN -F 3 "" H 4050 4150 60 0000 C CNN - 1 4050 4150 - 0 1 1 0 -$EndComp -Wire Wire Line - 4100 4400 3750 4400 -Connection ~ 3750 4400 -Wire Wire Line - 3900 4150 3750 4150 -Connection ~ 3750 4150 -Wire Wire Line - 4700 4150 4200 4150 -Wire Wire Line - 4400 4150 4400 4200 -Wire Wire Line - 4400 4600 4400 4900 -Connection ~ 4400 4800 -Wire Wire Line - 4400 5200 4400 5300 -Wire Wire Line - 3650 5300 6400 5300 -Wire Wire Line - 3650 5300 3650 5250 -Connection ~ 3650 5250 -Wire Wire Line - 4700 5300 4700 5000 -Connection ~ 4400 5300 -Wire Wire Line - 4700 3800 4700 4600 -Connection ~ 4400 4150 -$Comp -L R R14 -U 1 1 5CE44FFF -P 4700 3650 -F 0 "R14" V 4780 3650 50 0000 C CNN -F 1 "6k" V 4700 3650 50 0000 C CNN -F 2 "" V 4630 3650 50 0001 C CNN -F 3 "" H 4700 3650 50 0001 C CNN - 1 4700 3650 - 1 0 0 -1 -$EndComp -Connection ~ 4700 4150 -$Comp -L eSim_PNP Q14 -U 1 1 5CE45652 -P 5050 3950 -F 0 "Q14" H 4950 4000 50 0000 R CNN -F 1 "eSim_PNP" H 5000 4100 50 0000 R CNN -F 2 "" H 5250 4050 29 0000 C CNN -F 3 "" H 5050 3950 60 0000 C CNN - 1 5050 3950 - 1 0 0 1 -$EndComp -Wire Wire Line - 4850 3950 4700 3950 -Connection ~ 4700 3950 -Wire Wire Line - 4700 3500 4700 3450 -Wire Wire Line - 4700 3450 5150 3450 -Wire Wire Line - 5150 3450 5150 3750 -Wire Wire Line - 5150 5300 5150 4150 -Connection ~ 4700 5300 -Wire Wire Line - 4750 3450 4750 1950 -Wire Wire Line - 4200 1950 5300 1950 -Connection ~ 4200 1950 -Connection ~ 4750 3450 -$Comp -L eSim_NPN Q15 -U 1 1 5CE463AD -P 5400 2150 -F 0 "Q15" H 5300 2200 50 0000 R CNN -F 1 "eSim_NPN" H 5350 2300 50 0000 R CNN -F 2 "" H 5600 2250 29 0000 C CNN -F 3 "" H 5400 2150 60 0000 C CNN - 1 5400 2150 - -1 0 0 -1 -$EndComp -Connection ~ 4750 1950 -Wire Wire Line - 4150 2750 4150 2600 -Wire Wire Line - 4150 2600 6100 2600 -Wire Wire Line - 5300 2600 5300 2350 -Connection ~ 4150 2750 -$Comp -L R R17 -U 1 1 5CE46DDE -P 6050 4250 -F 0 "R17" V 6130 4250 50 0000 C CNN -F 1 "5k" V 6050 4250 50 0000 C CNN -F 2 "" V 5980 4250 50 0001 C CNN -F 3 "" H 6050 4250 50 0001 C CNN - 1 6050 4250 - 1 0 0 -1 -$EndComp -$Comp -L R R16 -U 1 1 5CE46F8E -P 6050 3050 -F 0 "R16" V 6130 3050 50 0000 C CNN -F 1 "1.385k" V 6050 3050 50 0000 C CNN -F 2 "" V 5980 3050 50 0001 C CNN -F 3 "" H 6050 3050 50 0001 C CNN - 1 6050 3050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6050 3200 6050 4100 -Wire Wire Line - 6050 5300 6050 4400 -Connection ~ 5150 5300 -Wire Wire Line - 6050 2600 6050 2900 -Connection ~ 5300 2600 -Wire Wire Line - 4550 3000 5100 3000 -Wire Wire Line - 5100 3000 5100 3250 -Wire Wire Line - 5100 3250 5350 3250 -Wire Wire Line - 5350 3250 5350 3600 -Wire Wire Line - 5350 3600 6050 3600 -Connection ~ 6050 3600 -Wire Wire Line - 1650 1050 1650 1300 -Connection ~ 1650 1300 -Connection ~ 3350 1050 -$Comp -L R R15 -U 1 1 5CE47F7A -P 5850 1300 -F 0 "R15" V 5930 1300 50 0000 C CNN -F 1 "10k" V 5850 1300 50 0000 C CNN -F 2 "" V 5780 1300 50 0001 C CNN -F 3 "" H 5850 1300 50 0001 C CNN - 1 5850 1300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5850 1050 5850 1150 -Connection ~ 4200 1050 -$Comp -L zener U2 -U 1 1 5CE48686 -P 5850 1900 -F 0 "U2" H 5800 1800 60 0000 C CNN -F 1 "zener" H 5850 2000 60 0000 C CNN -F 2 "" H 5900 1900 60 0000 C CNN -F 3 "" H 5900 1900 60 0000 C CNN - 1 5850 1900 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 5850 1450 5850 1600 -Wire Wire Line - 5850 2100 5850 2250 -Wire Wire Line - 5850 2150 5600 2150 -$Comp -L eSim_NPN Q16 -U 1 1 5CE4907A -P 6550 1600 -F 0 "Q16" H 6450 1650 50 0000 R CNN -F 1 "eSim_NPN" H 6500 1750 50 0000 R CNN -F 2 "" H 6750 1700 29 0000 C CNN -F 3 "" H 6550 1600 60 0000 C CNN - 1 6550 1600 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q17 -U 1 1 5CE4942E -P 7300 1950 -F 0 "Q17" H 7200 2000 50 0000 R CNN -F 1 "eSim_NPN" H 7250 2100 50 0000 R CNN -F 2 "" H 7500 2050 29 0000 C CNN -F 3 "" H 7300 1950 60 0000 C CNN - 1 7300 1950 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6650 1800 6650 2300 -Wire Wire Line - 6650 1950 7100 1950 -Wire Wire Line - 7400 1050 7400 1750 -Connection ~ 5850 1050 -Wire Wire Line - 6650 1400 6650 1050 -Connection ~ 6650 1050 -$Comp -L R R18 -U 1 1 5CE498BA -P 6650 2450 -F 0 "R18" V 6730 2450 50 0000 C CNN -F 1 "200" V 6650 2450 50 0000 C CNN -F 2 "" V 6580 2450 50 0001 C CNN -F 3 "" H 6650 2450 50 0001 C CNN - 1 6650 2450 - 1 0 0 -1 -$EndComp -$Comp -L R R20 -U 1 1 5CE4999A -P 7400 2450 -F 0 "R20" V 7480 2450 50 0000 C CNN -F 1 "0.3" V 7400 2450 50 0000 C CNN -F 2 "" V 7330 2450 50 0001 C CNN -F 3 "" H 7400 2450 50 0001 C CNN - 1 7400 2450 - 1 0 0 -1 -$EndComp -$Comp -L R R19 -U 1 1 5CE49AF5 -P 7000 2250 -F 0 "R19" V 7080 2250 50 0000 C CNN -F 1 "240" V 7000 2250 50 0000 C CNN -F 2 "" V 6930 2250 50 0001 C CNN -F 3 "" H 7000 2250 50 0001 C CNN - 1 7000 2250 - 0 1 1 0 -$EndComp -Connection ~ 6650 1950 -Wire Wire Line - 5850 2250 6850 2250 -Connection ~ 5850 2150 -Wire Wire Line - 7400 2150 7400 2300 -Wire Wire Line - 7150 2250 7400 2250 -Connection ~ 7400 2250 -Wire Wire Line - 6100 2600 6100 2650 -Wire Wire Line - 6100 2650 7400 2650 -Wire Wire Line - 7400 2650 7400 2600 -Connection ~ 6050 2600 -Wire Wire Line - 6650 2600 6650 2650 -Connection ~ 6650 2650 -$Comp -L PORT U3 -U 1 1 5CE4AAF6 -P 8050 1050 -F 0 "U3" H 8100 1150 30 0000 C CNN -F 1 "PORT" H 8050 1050 30 0000 C CNN -F 2 "" H 8050 1050 60 0000 C CNN -F 3 "" H 8050 1050 60 0000 C CNN - 1 8050 1050 - -1 0 0 1 -$EndComp -Connection ~ 7400 1050 -$Comp -L PORT U3 -U 3 1 5CE4B13E -P 7700 3000 -F 0 "U3" H 7750 3100 30 0000 C CNN -F 1 "PORT" H 7700 3000 30 0000 C CNN -F 2 "" H 7700 3000 60 0000 C CNN -F 3 "" H 7700 3000 60 0000 C CNN - 3 7700 3000 - -1 0 0 1 -$EndComp -$Comp -L PORT U3 -U 2 1 5CE4B701 -P 6650 5300 -F 0 "U3" H 6700 5400 30 0000 C CNN -F 1 "PORT" H 6650 5300 30 0000 C CNN -F 2 "" H 6650 5300 60 0000 C CNN -F 3 "" H 6650 5300 60 0000 C CNN - 2 6650 5300 - -1 0 0 1 -$EndComp -Connection ~ 6050 5300 -Wire Wire Line - 6350 1600 5950 1600 -Wire Wire Line - 5950 1600 5950 1550 -Wire Wire Line - 5950 1550 5000 1550 -Wire Wire Line - 5000 1550 5000 1950 -Connection ~ 5000 1950 -Wire Wire Line - 7300 2650 7300 3000 -Wire Wire Line - 7300 3000 7450 3000 -Connection ~ 7300 2650 -Connection ~ 2500 5200 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm7805/lm7805.sub b/src/SubcircuitLibrary/lm7805/lm7805.sub deleted file mode 100644 index 7ee1489c..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805.sub +++ /dev/null @@ -1,54 +0,0 @@ -* Subcircuit lm7805 -.subckt lm7805 net-_q16-pad1_ net-_q10-pad3_ net-_q12-pad1_ -* c:\users\malli\esim\src\subcircuitlibrary\lm7805\lm7805.cir -.include PNP.lib -.include NPN.lib -r1 net-_q16-pad1_ net-_q1-pad2_ 100k -r2 net-_q16-pad1_ net-_q1-pad1_ 500 -r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k -r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k -* u1 net-_q10-pad3_ net-_q1-pad2_ zener -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 -r5 net-_q10-pad2_ net-_q10-pad3_ 500 -q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 -q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ Q2N2222 -r6 net-_q2-pad3_ net-_q3-pad1_ 1k -q3 net-_q3-pad1_ net-_q3-pad2_ net-_q10-pad3_ Q2N2222 -r7 net-_q3-pad2_ net-_q10-pad3_ 6k -q6 net-_c1-pad2_ net-_q3-pad2_ net-_q6-pad3_ Q2N2222 -r10 net-_q6-pad3_ net-_q10-pad3_ 1k -q7 net-_q2-pad1_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 -q8 net-_q7-pad3_ net-_q12-pad3_ net-_q2-pad3_ Q2N2222 -q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 -r12 net-_q12-pad3_ net-_q2-pad3_ 6k -r9 net-_q2-pad3_ net-_c1-pad2_ 20k -q5 net-_q2-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2907A -q9 net-_q10-pad1_ net-_q2-pad1_ net-_q9-pad3_ Q2N2907A -r8 net-_q16-pad1_ net-_q5-pad3_ 100 -r11 net-_q16-pad1_ net-_q9-pad3_ 50 -q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 -q11 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 -q13 net-_c1-pad1_ net-_q11-pad3_ net-_q10-pad3_ Q2N2222 -r13 net-_q11-pad3_ net-_q10-pad3_ 6k -c1 net-_c1-pad1_ net-_c1-pad2_ 30p -r14 net-_q10-pad1_ net-_c1-pad1_ 6k -q14 net-_q10-pad3_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A -q15 net-_q10-pad1_ net-_q15-pad2_ net-_q12-pad1_ Q2N2222 -r17 net-_q12-pad2_ net-_q10-pad3_ 5k -r16 net-_q12-pad1_ net-_q12-pad2_ 1.385k -r15 net-_q16-pad1_ net-_r15-pad2_ 10k -* u2 net-_q15-pad2_ net-_r15-pad2_ zener -q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 -q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ Q2N2222 -r18 net-_q16-pad3_ net-_q12-pad1_ 200 -r20 net-_q17-pad3_ net-_q12-pad1_ 0.3 -r19 net-_q17-pad3_ net-_q15-pad2_ 240 -a1 net-_q10-pad3_ net-_q1-pad2_ u1 -a2 net-_q15-pad2_ net-_r15-pad2_ u2 -* Schematic Name: zener, NgSpice Name: zener -.model u1 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -* Schematic Name: zener, NgSpice Name: zener -.model u2 zener(n_forward=1.0 v_breakdown=5.6 i_sat=1.0e-12 limit_switch=FALSE i_breakdown=2.0e-2 ) -* Control Statements - -.ends lm7805
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml b/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml deleted file mode 100644 index 7395bd7c..00000000 --- a/src/SubcircuitLibrary/lm7805/lm7805_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Saturation Current (default=1.0e-12)" /><field2 name="Enter Forward Emission Coefficient (default=1.0)" /><field3 name="Enter Breakdown Voltage (default=5.6)" /><field4 name="Enter Breakdown Current (default=2.0e-2)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Saturation Current (default=1.0e-12)" /><field7 name="Enter Forward Emission Coefficient (default=1.0)" /><field8 name="Enter Breakdown Voltage (default=5.6)" /><field9 name="Enter Breakdown Current (default=2.0e-2)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2></model><devicemodel><q1><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q1><q3><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q3><q2><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q2><q5><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q5><q4><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q4><q7><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q7><q6><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q6><q9><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q9><q8><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q8><q15><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q15><q14><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/PNP.lib</field></q14><q17><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q17><q16><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q16><q11><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q11><q10><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q10><q13><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q13><q12><field>C:/Users/Bhargav/eSim/src/deviceModelLibrary/Transistor/NPN.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/NPN.lib b/src/SubcircuitLibrary/lm_741/NPN.lib deleted file mode 100644 index 6509fe7a..00000000 --- a/src/SubcircuitLibrary/lm_741/NPN.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 -+ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p -+ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p -+ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/src/SubcircuitLibrary/lm_741/PNP.lib b/src/SubcircuitLibrary/lm_741/PNP.lib deleted file mode 100644 index 7edda0ea..00000000 --- a/src/SubcircuitLibrary/lm_741/PNP.lib +++ /dev/null @@ -1,4 +0,0 @@ -.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 -+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 -+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 -+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/src/SubcircuitLibrary/lm_741/analysis b/src/SubcircuitLibrary/lm_741/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/lm_741/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib b/src/SubcircuitLibrary/lm_741/lm_741-cache.lib deleted file mode 100644 index 04e3fecd..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741-cache.lib +++ /dev/null @@ -1,119 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_NPN -# -DEF eSim_NPN Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_NPN" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -ALIAS BC547 Q2N2222 -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -# eSim_PNP -# -DEF eSim_PNP Q 0 0 Y N 1 F N -F0 "Q" -100 50 50 H V R CNN -F1 "eSim_PNP" -50 150 50 H V R CNN -F2 "" 200 100 29 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 50 0 111 0 1 10 N -P 2 0 1 0 25 25 100 100 N -P 3 0 1 0 25 -25 100 -100 100 -100 N -P 3 0 1 20 25 75 25 -75 25 -75 N -P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F -X C 1 100 200 100 D 50 50 1 1 C -X B 2 -200 0 225 R 50 50 1 1 I -X E 3 100 -200 100 U 50 50 1 1 E -ENDDRAW -ENDDEF -# -# eSim_R -# -DEF eSim_R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "eSim_R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir b/src/SubcircuitLibrary/lm_741/lm_741.cir deleted file mode 100644 index 4a5917ea..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741.cir +++ /dev/null @@ -1,43 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN -Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN -Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP -Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP -Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN -Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP -Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP -Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN -Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN -R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k -R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k -R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k -Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN -Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN -R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k -R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k -Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP -Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP -Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN -R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k -R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k -C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p -Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN -Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN -R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k -R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 -Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN -Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN -Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN -R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 -R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 -Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP -U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT - -.end diff --git a/src/SubcircuitLibrary/lm_741/lm_741.cir.out b/src/SubcircuitLibrary/lm_741/lm_741.cir.out deleted file mode 100644 index a00bd86a..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741.cir.out +++ /dev/null @@ -1,46 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir - -.include npn_1.lib -.include pnp_1.lib -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 -q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 -q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 -q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 -q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 -q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 -q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 -q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 -q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 -r1 net-_q7-pad3_ net-_q12-pad3_ 1k -r2 net-_q3-pad3_ net-_q12-pad3_ 50k -r3 net-_q8-pad3_ net-_q12-pad3_ 1k -q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 -q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 -r4 net-_q13-pad3_ net-_q12-pad3_ 5k -r11 net-_q10-pad1_ net-_q12-pad1_ 39k -q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 -q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 -q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 -r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k -r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k -c1 net-_c1-pad1_ net-_c1-pad2_ 30p -q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 -q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 -r5 net-_q15-pad2_ net-_q12-pad3_ 50k -r6 net-_q15-pad3_ net-_q12-pad3_ 50 -q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 -q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 -q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 -r9 net-_q18-pad3_ net-_q20-pad3_ 25 -r10 net-_q20-pad3_ net-_q19-pad3_ 50 -q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 -* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/lm_741/lm_741.pro b/src/SubcircuitLibrary/lm_741/lm_741.pro deleted file mode 100644 index cbe83f35..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=Fri Jun 7 21:53:51 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Plot -LibName8=eSim_Power -LibName9=eSim_PSpice -LibName10=eSim_Sources -LibName11=eSim_Subckt -LibName12=eSim_User diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sch b/src/SubcircuitLibrary/lm_741/lm_741.sch deleted file mode 100644 index b017fd2b..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741.sch +++ /dev/null @@ -1,697 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:lm_741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L eSim_NPN Q1 -U 1 1 5CE90A7B -P 2650 2700 -F 0 "Q1" H 2550 2750 50 0000 R CNN -F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN -F 2 "" H 2850 2800 29 0000 C CNN -F 3 "" H 2650 2700 60 0000 C CNN - 1 2650 2700 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q2 -U 1 1 5CE90A7C -P 4300 2700 -F 0 "Q2" H 4200 2750 50 0000 R CNN -F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN -F 2 "" H 4500 2800 29 0000 C CNN -F 3 "" H 4300 2700 60 0000 C CNN - 1 4300 2700 - -1 0 0 -1 -$EndComp -$Comp -L eSim_PNP Q6 -U 1 1 5CE90A7D -P 3000 3200 -F 0 "Q6" H 2900 3250 50 0000 R CNN -F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN -F 2 "" H 3200 3300 29 0000 C CNN -F 3 "" H 3000 3200 60 0000 C CNN - 1 3000 3200 - -1 0 0 1 -$EndComp -$Comp -L eSim_PNP Q5 -U 1 1 5CE90A7E -P 3950 3200 -F 0 "Q5" H 3850 3250 50 0000 R CNN -F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN -F 2 "" H 4150 3300 29 0000 C CNN -F 3 "" H 3950 3200 60 0000 C CNN - 1 3950 3200 - 1 0 0 1 -$EndComp -$Comp -L eSim_NPN Q3 -U 1 1 5CE90A7F -P 3300 4000 -F 0 "Q3" H 3200 4050 50 0000 R CNN -F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN -F 2 "" H 3500 4100 29 0000 C CNN -F 3 "" H 3300 4000 60 0000 C CNN - 1 3300 4000 - 1 0 0 -1 -$EndComp -$Comp -L eSim_PNP Q4 -U 1 1 5CE90A80 -P 3850 2000 -F 0 "Q4" H 3750 2050 50 0000 R CNN -F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN -F 2 "" H 4050 2100 29 0000 C CNN -F 3 "" H 3850 2000 60 0000 C CNN - 1 3850 2000 - -1 0 0 1 -$EndComp -$Comp -L eSim_PNP Q9 -U 1 1 5CE90A81 -P 5200 2000 -F 0 "Q9" H 5100 2050 50 0000 R CNN -F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN -F 2 "" H 5400 2100 29 0000 C CNN -F 3 "" H 5200 2000 60 0000 C CNN - 1 5200 2000 - 1 0 0 1 -$EndComp -$Comp -L eSim_NPN Q8 -U 1 1 5CE90A82 -P 3950 4600 -F 0 "Q8" H 3850 4650 50 0000 R CNN -F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN -F 2 "" H 4150 4700 29 0000 C CNN -F 3 "" H 3950 4600 60 0000 C CNN - 1 3950 4600 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q7 -U 1 1 5CE90A83 -P 3000 4600 -F 0 "Q7" H 2900 4650 50 0000 R CNN -F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN -F 2 "" H 3200 4700 29 0000 C CNN -F 3 "" H 3000 4600 60 0000 C CNN - 1 3000 4600 - -1 0 0 -1 -$EndComp -$Comp -L eSim_R R1 -U 1 1 5CE90A84 -P 2850 5200 -F 0 "R1" H 2900 5330 50 0000 C CNN -F 1 "1k" H 2900 5250 50 0000 C CNN -F 2 "" H 2900 5180 30 0000 C CNN -F 3 "" V 2900 5250 30 0000 C CNN - 1 2850 5200 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R2 -U 1 1 5CE90A85 -P 3550 5200 -F 0 "R2" H 3600 5330 50 0000 C CNN -F 1 "50k" H 3600 5250 50 0000 C CNN -F 2 "" H 3600 5180 30 0000 C CNN -F 3 "" V 3600 5250 30 0000 C CNN - 1 3550 5200 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R3 -U 1 1 5CE90A86 -P 4000 5200 -F 0 "R3" H 4050 5330 50 0000 C CNN -F 1 "1k" H 4050 5250 50 0000 C CNN -F 2 "" H 4050 5180 30 0000 C CNN -F 3 "" V 4050 5250 30 0000 C CNN - 1 4000 5200 - 0 1 1 0 -$EndComp -$Comp -L eSim_NPN Q12 -U 1 1 5CE90A87 -P 6300 4700 -F 0 "Q12" H 6200 4750 50 0000 R CNN -F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN -F 2 "" H 6500 4800 29 0000 C CNN -F 3 "" H 6300 4700 60 0000 C CNN - 1 6300 4700 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q13 -U 1 1 5CE90A88 -P 5400 4700 -F 0 "Q13" H 5300 4750 50 0000 R CNN -F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN -F 2 "" H 5600 4800 29 0000 C CNN -F 3 "" H 5400 4700 60 0000 C CNN - 1 5400 4700 - -1 0 0 -1 -$EndComp -$Comp -L eSim_R R4 -U 1 1 5CE90A89 -P 5250 5200 -F 0 "R4" H 5300 5330 50 0000 C CNN -F 1 "5k" H 5300 5250 50 0000 C CNN -F 2 "" H 5300 5180 30 0000 C CNN -F 3 "" V 5300 5250 30 0000 C CNN - 1 5250 5200 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R11 -U 1 1 5CE90A8A -P 6350 2750 -F 0 "R11" H 6400 2880 50 0000 C CNN -F 1 "39k" H 6400 2800 50 0000 C CNN -F 2 "" H 6400 2730 30 0000 C CNN -F 3 "" V 6400 2800 30 0000 C CNN - 1 6350 2750 - 0 1 1 0 -$EndComp -$Comp -L eSim_PNP Q10 -U 1 1 5CE90A8B -P 6500 1950 -F 0 "Q10" H 6400 2000 50 0000 R CNN -F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN -F 2 "" H 6700 2050 29 0000 C CNN -F 3 "" H 6500 1950 60 0000 C CNN - 1 6500 1950 - -1 0 0 1 -$EndComp -$Comp -L eSim_PNP Q11 -U 1 1 5CE90A8C -P 7500 1950 -F 0 "Q11" H 7400 2000 50 0000 R CNN -F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN -F 2 "" H 7700 2050 29 0000 C CNN -F 3 "" H 7500 1950 60 0000 C CNN - 1 7500 1950 - 1 0 0 1 -$EndComp -$Comp -L eSim_NPN Q14 -U 1 1 5CE90A8D -P 7500 3050 -F 0 "Q14" H 7400 3100 50 0000 R CNN -F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN -F 2 "" H 7700 3150 29 0000 C CNN -F 3 "" H 7500 3050 60 0000 C CNN - 1 7500 3050 - 1 0 0 -1 -$EndComp -$Comp -L eSim_R R8 -U 1 1 5CE90A8E -P 7300 2600 -F 0 "R8" H 7350 2730 50 0000 C CNN -F 1 "4.5k" H 7350 2650 50 0000 C CNN -F 2 "" H 7350 2580 30 0000 C CNN -F 3 "" V 7350 2650 30 0000 C CNN - 1 7300 2600 - -1 0 0 1 -$EndComp -$Comp -L eSim_R R7 -U 1 1 5CE90A8F -P 7300 3400 -F 0 "R7" H 7350 3530 50 0000 C CNN -F 1 "7.5k" H 7350 3450 50 0000 C CNN -F 2 "" H 7350 3380 30 0000 C CNN -F 3 "" V 7350 3450 30 0000 C CNN - 1 7300 3400 - -1 0 0 1 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5CE90A90 -P 6600 3200 -F 0 "C1" H 6625 3300 50 0000 L CNN -F 1 "30p" H 6625 3100 50 0000 L CNN -F 2 "" H 6638 3050 30 0000 C CNN -F 3 "" H 6600 3200 60 0000 C CNN - 1 6600 3200 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q16 -U 1 1 5CE90A91 -P 7050 3950 -F 0 "Q16" H 6950 4000 50 0000 R CNN -F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN -F 2 "" H 7250 4050 29 0000 C CNN -F 3 "" H 7050 3950 60 0000 C CNN - 1 7050 3950 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q15 -U 1 1 5CE90A92 -P 7500 4300 -F 0 "Q15" H 7400 4350 50 0000 R CNN -F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN -F 2 "" H 7700 4400 29 0000 C CNN -F 3 "" H 7500 4300 60 0000 C CNN - 1 7500 4300 - 1 0 0 -1 -$EndComp -$Comp -L eSim_R R5 -U 1 1 5CE90A93 -P 7100 5050 -F 0 "R5" H 7150 5180 50 0000 C CNN -F 1 "50k" H 7150 5100 50 0000 C CNN -F 2 "" H 7150 5030 30 0000 C CNN -F 3 "" V 7150 5100 30 0000 C CNN - 1 7100 5050 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R6 -U 1 1 5CE90A94 -P 7550 5050 -F 0 "R6" H 7600 5180 50 0000 C CNN -F 1 "50" H 7600 5100 50 0000 C CNN -F 2 "" H 7600 5030 30 0000 C CNN -F 3 "" V 7600 5100 30 0000 C CNN - 1 7550 5050 - 0 1 1 0 -$EndComp -$Comp -L eSim_NPN Q17 -U 1 1 5CE90A95 -P 6800 4700 -F 0 "Q17" H 6700 4750 50 0000 R CNN -F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN -F 2 "" H 7000 4800 29 0000 C CNN -F 3 "" H 6800 4700 60 0000 C CNN - 1 6800 4700 - -1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q18 -U 1 1 5CE90A96 -P 8800 2300 -F 0 "Q18" H 8700 2350 50 0000 R CNN -F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN -F 2 "" H 9000 2400 29 0000 C CNN -F 3 "" H 8800 2300 60 0000 C CNN - 1 8800 2300 - 1 0 0 -1 -$EndComp -$Comp -L eSim_NPN Q20 -U 1 1 5CE90A97 -P 8400 2750 -F 0 "Q20" H 8300 2800 50 0000 R CNN -F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN -F 2 "" H 8600 2850 29 0000 C CNN -F 3 "" H 8400 2750 60 0000 C CNN - 1 8400 2750 - -1 0 0 -1 -$EndComp -$Comp -L eSim_R R9 -U 1 1 5CE90A98 -P 8850 3000 -F 0 "R9" H 8900 3130 50 0000 C CNN -F 1 "25" H 8900 3050 50 0000 C CNN -F 2 "" H 8900 2980 30 0000 C CNN -F 3 "" V 8900 3050 30 0000 C CNN - 1 8850 3000 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R10 -U 1 1 5CE90A99 -P 8850 3750 -F 0 "R10" H 8900 3880 50 0000 C CNN -F 1 "50" H 8900 3800 50 0000 C CNN -F 2 "" H 8900 3730 30 0000 C CNN -F 3 "" V 8900 3800 30 0000 C CNN - 1 8850 3750 - 0 1 1 0 -$EndComp -$Comp -L eSim_PNP Q19 -U 1 1 5CE90A9A -P 8800 4600 -F 0 "Q19" H 8700 4650 50 0000 R CNN -F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN -F 2 "" H 9000 4700 29 0000 C CNN -F 3 "" H 8800 4600 60 0000 C CNN - 1 8800 4600 - 1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CE90A9B -P 1900 1200 -F 0 "U1" H 1950 1300 30 0000 C CNN -F 1 "PORT" H 1900 1200 30 0000 C CNN -F 2 "" H 1900 1200 60 0000 C CNN -F 3 "" H 1900 1200 60 0000 C CNN - 3 1900 1200 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5CE90A9C -P 4500 1050 -F 0 "U1" H 4550 1150 30 0000 C CNN -F 1 "PORT" H 4500 1050 30 0000 C CNN -F 2 "" H 4500 1050 60 0000 C CNN -F 3 "" H 4500 1050 60 0000 C CNN - 2 4500 1050 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 7 1 5CE90A9D -P 9750 1650 -F 0 "U1" H 9800 1750 30 0000 C CNN -F 1 "PORT" H 9750 1650 30 0000 C CNN -F 2 "" H 9750 1650 60 0000 C CNN -F 3 "" H 9750 1650 60 0000 C CNN - 7 9750 1650 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CE90A9E -P 9750 3500 -F 0 "U1" H 9800 3600 30 0000 C CNN -F 1 "PORT" H 9750 3500 30 0000 C CNN -F 2 "" H 9750 3500 60 0000 C CNN -F 3 "" H 9750 3500 60 0000 C CNN - 6 9750 3500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CE90A9F -P 9700 5550 -F 0 "U1" H 9750 5650 30 0000 C CNN -F 1 "PORT" H 9700 5550 30 0000 C CNN -F 2 "" H 9700 5550 60 0000 C CNN -F 3 "" H 9700 5550 60 0000 C CNN - 4 9700 5550 - -1 0 0 1 -$EndComp -Wire Wire Line - 3200 3200 3750 3200 -Wire Wire Line - 2750 2900 2750 2950 -Wire Wire Line - 2750 2950 2900 2950 -Wire Wire Line - 2900 2950 2900 3000 -Wire Wire Line - 4200 2900 4200 2950 -Wire Wire Line - 4200 2950 4050 2950 -Wire Wire Line - 4050 2950 4050 3000 -Wire Wire Line - 2900 3400 2900 4400 -Wire Wire Line - 2900 4000 3100 4000 -Wire Wire Line - 4200 2000 4200 2500 -Wire Wire Line - 4200 2350 2750 2350 -Wire Wire Line - 2750 2350 2750 2500 -Wire Wire Line - 5000 2000 4050 2000 -Connection ~ 4200 2350 -Connection ~ 4200 2000 -Wire Wire Line - 3750 2200 3750 2350 -Connection ~ 3750 2350 -Wire Wire Line - 3750 1800 3750 1650 -Wire Wire Line - 3400 1650 7600 1650 -Wire Wire Line - 3400 1650 3400 3800 -Wire Wire Line - 5300 1650 5300 1800 -Connection ~ 3750 1650 -Wire Wire Line - 5300 2200 5300 4500 -Wire Wire Line - 5300 3500 3650 3500 -Wire Wire Line - 3650 3500 3650 3200 -Connection ~ 3650 3200 -Connection ~ 2900 4000 -Wire Wire Line - 4050 4400 4050 3400 -Wire Wire Line - 3400 4200 3400 4600 -Wire Wire Line - 3200 4600 3750 4600 -Connection ~ 3400 4600 -Wire Wire Line - 4050 5100 4050 4800 -Wire Wire Line - 3600 5100 3600 4600 -Connection ~ 3600 4600 -Wire Wire Line - 2900 5100 2900 4800 -Wire Wire Line - 2900 5400 2900 5550 -Wire Wire Line - 2900 5550 9450 5550 -Wire Wire Line - 4050 5550 4050 5400 -Wire Wire Line - 3600 5400 3600 5550 -Connection ~ 3600 5550 -Wire Wire Line - 6100 4700 5600 4700 -Wire Wire Line - 6400 2950 6400 4500 -Wire Wire Line - 6400 4250 5900 4250 -Wire Wire Line - 5900 4250 5900 4700 -Connection ~ 5900 4700 -Wire Wire Line - 5300 5100 5300 4900 -Wire Wire Line - 5300 5550 5300 5400 -Connection ~ 4050 5550 -Wire Wire Line - 6400 5550 6400 4900 -Connection ~ 5300 5550 -Connection ~ 5300 3500 -Wire Wire Line - 6400 1650 6400 1750 -Connection ~ 5300 1650 -Wire Wire Line - 6400 2150 6400 2650 -Connection ~ 6400 4250 -Wire Wire Line - 6700 1950 7300 1950 -Wire Wire Line - 7000 1950 7000 2250 -Wire Wire Line - 7000 2250 6400 2250 -Connection ~ 6400 2250 -Wire Wire Line - 7600 1650 7600 1750 -Connection ~ 6400 1650 -Connection ~ 7000 1950 -Wire Wire Line - 7600 3250 7600 4100 -Wire Wire Line - 7600 3450 7400 3450 -Wire Wire Line - 6900 3450 7100 3450 -Wire Wire Line - 6900 2650 6900 3450 -Wire Wire Line - 6900 3050 7300 3050 -Wire Wire Line - 7600 2150 7600 2850 -Wire Wire Line - 7600 2650 7400 2650 -Wire Wire Line - 7100 2650 6900 2650 -Connection ~ 6900 3050 -Connection ~ 7600 2650 -Wire Wire Line - 7300 4300 7150 4300 -Wire Wire Line - 7150 4150 7150 4950 -Connection ~ 7600 3450 -Wire Wire Line - 7600 3700 7150 3700 -Wire Wire Line - 7150 3700 7150 3750 -Connection ~ 7600 3700 -Wire Wire Line - 6600 3050 6600 2450 -Wire Wire Line - 6600 2450 7600 2450 -Connection ~ 7600 2450 -Wire Wire Line - 6600 3350 6600 3950 -Wire Wire Line - 4050 3950 6850 3950 -Wire Wire Line - 6700 3950 6700 4500 -Connection ~ 6700 3950 -Wire Wire Line - 6700 4900 6700 5550 -Connection ~ 6400 5550 -Connection ~ 7150 4300 -Wire Wire Line - 7600 4950 7600 4500 -Wire Wire Line - 7000 4700 7600 4700 -Connection ~ 7600 4700 -Wire Wire Line - 7600 5550 7600 5250 -Connection ~ 6700 5550 -Wire Wire Line - 7150 5250 7150 5550 -Connection ~ 7150 5550 -Wire Wire Line - 7600 2300 8600 2300 -Wire Wire Line - 8300 2300 8300 2550 -Connection ~ 8300 2300 -Connection ~ 7600 2300 -Wire Wire Line - 8900 2100 8900 1650 -Wire Wire Line - 7550 1650 9500 1650 -Connection ~ 7550 1650 -Connection ~ 8900 1650 -Wire Wire Line - 8900 2500 8900 2900 -Wire Wire Line - 8900 2750 8600 2750 -Connection ~ 8900 2750 -Wire Wire Line - 8300 2950 8300 3350 -Wire Wire Line - 8300 3350 8900 3350 -Wire Wire Line - 8900 3200 8900 3650 -Wire Wire Line - 8900 4400 8900 3950 -Connection ~ 8900 3350 -Wire Wire Line - 8900 3500 9500 3500 -Connection ~ 8900 3500 -Wire Wire Line - 8900 5550 8900 4800 -Connection ~ 7600 5550 -Connection ~ 8900 5550 -Wire Wire Line - 8600 4600 8100 4600 -Wire Wire Line - 8100 4600 8100 3850 -Wire Wire Line - 8100 3850 7600 3850 -Connection ~ 7600 3850 -Connection ~ 4050 3950 -Connection ~ 6600 3950 -Wire Wire Line - 4500 2700 4750 2700 -Wire Wire Line - 4750 2700 4750 1050 -Wire Wire Line - 2450 2700 2150 2700 -Wire Wire Line - 2150 2700 2150 1200 -$Comp -L PORT U1 -U 5 1 5CE90AA0 -P 1850 4850 -F 0 "U1" H 1900 4950 30 0000 C CNN -F 1 "PORT" H 1850 4850 30 0000 C CNN -F 2 "" H 1850 4850 60 0000 C CNN -F 3 "" H 1850 4850 60 0000 C CNN - 5 1850 4850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CE90AA1 -P 1850 5100 -F 0 "U1" H 1900 5200 30 0000 C CNN -F 1 "PORT" H 1850 5100 30 0000 C CNN -F 2 "" H 1850 5100 60 0000 C CNN -F 3 "" H 1850 5100 60 0000 C CNN - 1 1850 5100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2100 5100 2700 5100 -Wire Wire Line - 2700 5100 2700 5050 -Wire Wire Line - 2700 5050 2900 5050 -Connection ~ 2900 5050 -Wire Wire Line - 2100 4850 2550 4850 -Wire Wire Line - 2550 4850 2550 4900 -Wire Wire Line - 2550 4900 4050 4900 -Connection ~ 4050 4900 -$Comp -L PORT U1 -U 8 1 5CE9368F -P 9600 6050 -F 0 "U1" H 9650 6150 30 0000 C CNN -F 1 "PORT" H 9600 6050 30 0000 C CNN -F 2 "" H 9600 6050 60 0000 C CNN -F 3 "" H 9600 6050 60 0000 C CNN - 8 9600 6050 - -1 0 0 1 -$EndComp -Wire Wire Line - 9350 6050 9100 6050 -NoConn ~ 9100 6050 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/lm_741/lm_741.sub b/src/SubcircuitLibrary/lm_741/lm_741.sub deleted file mode 100644 index fa8d27b1..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741.sub +++ /dev/null @@ -1,40 +0,0 @@ -* Subcircuit lm_741 -.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? -* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir -.include npn_1.lib -.include pnp_1.lib -q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 -q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 -q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 -q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 -q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 -q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 -q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 -q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 -q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 -r1 net-_q7-pad3_ net-_q12-pad3_ 1k -r2 net-_q3-pad3_ net-_q12-pad3_ 50k -r3 net-_q8-pad3_ net-_q12-pad3_ 1k -q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 -q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 -r4 net-_q13-pad3_ net-_q12-pad3_ 5k -r11 net-_q10-pad1_ net-_q12-pad1_ 39k -q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 -q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 -q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 -r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k -r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k -c1 net-_c1-pad1_ net-_c1-pad2_ 30p -q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 -q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 -r5 net-_q15-pad2_ net-_q12-pad3_ 50k -r6 net-_q15-pad3_ net-_q12-pad3_ 50 -q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 -q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 -q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 -r9 net-_q18-pad3_ net-_q20-pad3_ 25 -r10 net-_q20-pad3_ net-_q19-pad3_ 50 -q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 -* Control Statements - -.ends lm_741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml b/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml deleted file mode 100644 index b61322bb..00000000 --- a/src/SubcircuitLibrary/lm_741/lm_741_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/npn_1.lib b/src/SubcircuitLibrary/lm_741/npn_1.lib deleted file mode 100644 index a1818ed8..00000000 --- a/src/SubcircuitLibrary/lm_741/npn_1.lib +++ /dev/null @@ -1,29 +0,0 @@ -.model npn_1 NPN( -+ Vtf=1.7 -+ Cjc=0.5p -+ Nc=2 -+ Tr=46.91n -+ Ne=1.307 -+ Cje=0.5p -+ Isc=0 -+ Xtb=1.5 -+ Rb=500 -+ Rc=1 -+ Tf=411.1p -+ Xti=3 -+ Ikr=0 -+ Bf=125 -+ Fc=.5 -+ Ise=14.34f -+ Br=6.092 -+ Ikf=.2847 -+ Mje=.377 -+ Mjc=.3416 -+ Vaf=74.03 -+ Vjc=.75 -+ Vje=.75 -+ Xtf=3 -+ Itf=.6 -+ Is=14.34f -+ Eg=1.11 -)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/lm_741/pnp_1.lib b/src/SubcircuitLibrary/lm_741/pnp_1.lib deleted file mode 100644 index a4ee06da..00000000 --- a/src/SubcircuitLibrary/lm_741/pnp_1.lib +++ /dev/null @@ -1,29 +0,0 @@ -.model pnp_1 PNP( -+ Vtf=1.7 -+ Cjc=1.5p -+ Nc=2 -+ Tr=46.91n -+ Ne=1.307 -+ Cje=0.3p -+ Isc=0 -+ Xtb=1.5 -+ Rb=250 -+ Rc=1 -+ Tf=411.1p -+ Xti=3 -+ Ikr=0 -+ Bf=25 -+ Fc=.5 -+ Ise=14.34f -+ Br=6.092 -+ Ikf=.2847 -+ Mje=.377 -+ Mjc=.3416 -+ Vaf=74.03 -+ Vjc=.75 -+ Vje=.75 -+ Xtf=3 -+ Itf=.6 -+ Is=14.34f -+ Eg=1.11 -)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/analysis b/src/SubcircuitLibrary/opto_isolator_switch/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib deleted file mode 100644 index 88d58478..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch-cache.lib +++ /dev/null @@ -1,99 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# CCCS -# -DEF CCCS F 0 40 Y Y 1 F N -F0 "F" 0 150 50 H V C CNN -F1 "CCCS" -200 -50 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_R -# -DEF eSim_R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "eSim_R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir deleted file mode 100644 index 5fc9dd50..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir +++ /dev/null @@ -1,15 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jun 20 15:52:58 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -R1 Net-_R1-Pad1_ Net-_F1-Pad3_ 1000 -F1 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_F1-Pad3_ Net-_F1-Pad4_ 3 -R2 Net-_C1-Pad2_ Net-_F1-Pad4_ 1000 -U1 Net-_R1-Pad1_ Net-_F1-Pad4_ Net-_C1-Pad1_ Net-_C1-Pad2_ PORT -C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 14n - -.end diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out deleted file mode 100644 index afeeaa02..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/opto_isolator_switch/opto_isolator_switch.cir - -r1 net-_r1-pad1_ net-_f1-pad3_ 1000 -* f1 -r2 net-_c1-pad2_ net-_f1-pad4_ 1000 -* u1 net-_r1-pad1_ net-_f1-pad4_ net-_c1-pad1_ net-_c1-pad2_ port -c1 net-_c1-pad1_ net-_c1-pad2_ 14n -Vf1 net-_f1-pad3_ net-_f1-pad4_ 0 -f1 net-_c1-pad1_ net-_c1-pad2_ Vf1 3 -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro deleted file mode 100644 index 47ae9917..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.pro +++ /dev/null @@ -1,83 +0,0 @@ -update=Thu Jun 20 15:32:48 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=device -LibName23=transistors -LibName24=conn -LibName25=linear -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_User -LibName38=eSim_Plot -LibName39=eSim_PSpice -LibName40=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog -LibName41=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName42=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName43=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName44=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName45=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName46=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName47=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName48=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName49=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User - diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch deleted file mode 100644 index 3f1c7298..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sch +++ /dev/null @@ -1,178 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:eSim_Plot -LIBS:eSim_PSpice -LIBS:opto_isolator_switch-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L eSim_R R1 -U 1 1 5D0B5974 -P 4350 3450 -F 0 "R1" H 4400 3580 50 0000 C CNN -F 1 "1000" H 4400 3500 50 0000 C CNN -F 2 "" H 4400 3430 30 0000 C CNN -F 3 "" V 4400 3500 30 0000 C CNN - 1 4350 3450 - 1 0 0 -1 -$EndComp -$Comp -L CCCS F1 -U 1 1 5D0B59A2 -P 5200 3450 -F 0 "F1" H 5200 3600 50 0000 C CNN -F 1 "3" H 5000 3400 50 0000 C CNN -F 2 "" H 5200 3450 60 0000 C CNN -F 3 "" H 5200 3450 60 0000 C CNN - 1 5200 3450 - 0 1 1 0 -$EndComp -$Comp -L eSim_R R2 -U 1 1 5D0B59D5 -P 5200 4050 -F 0 "R2" H 5250 4180 50 0000 C CNN -F 1 "1000" H 5250 4100 50 0000 C CNN -F 2 "" H 5250 4030 30 0000 C CNN -F 3 "" V 5250 4100 30 0000 C CNN - 1 5200 4050 - 0 1 1 0 -$EndComp -Wire Wire Line - 4550 3400 5000 3400 -Wire Wire Line - 5000 3500 4750 3500 -Wire Wire Line - 4750 3500 4750 3700 -Wire Wire Line - 5250 3950 5250 3750 -Wire Wire Line - 5250 3150 5250 3000 -Wire Wire Line - 5250 3000 5650 3000 -Wire Wire Line - 5650 3000 5650 3350 -Wire Wire Line - 5650 3350 5700 3350 -Wire Wire Line - 5250 4250 5250 4350 -Wire Wire Line - 4250 3400 4000 3400 -$Comp -L PORT U1 -U 1 1 5D0B5AC7 -P 3750 3400 -F 0 "U1" H 3800 3500 30 0000 C CNN -F 1 "PORT" H 3750 3400 30 0000 C CNN -F 2 "" H 3750 3400 60 0000 C CNN -F 3 "" H 3750 3400 60 0000 C CNN - 1 3750 3400 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5D0B5B16 -P 4750 3950 -F 0 "U1" H 4800 4050 30 0000 C CNN -F 1 "PORT" H 4750 3950 30 0000 C CNN -F 2 "" H 4750 3950 60 0000 C CNN -F 3 "" H 4750 3950 60 0000 C CNN - 2 4750 3950 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 4 1 5D0B5B84 -P 6050 3800 -F 0 "U1" H 6100 3900 30 0000 C CNN -F 1 "PORT" H 6050 3800 30 0000 C CNN -F 2 "" H 6050 3800 60 0000 C CNN -F 3 "" H 6050 3800 60 0000 C CNN - 4 6050 3800 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 3 1 5D0B5BF0 -P 5950 3350 -F 0 "U1" H 6000 3450 30 0000 C CNN -F 1 "PORT" H 5950 3350 30 0000 C CNN -F 2 "" H 5950 3350 60 0000 C CNN -F 3 "" H 5950 3350 60 0000 C CNN - 3 5950 3350 - -1 0 0 1 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5D0B5EB6 -P 5500 3350 -F 0 "C1" H 5525 3450 50 0000 L CNN -F 1 "14n" H 5525 3250 50 0000 L CNN -F 2 "" H 5538 3200 30 0000 C CNN -F 3 "" H 5500 3350 60 0000 C CNN - 1 5500 3350 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5500 3200 5500 3000 -Connection ~ 5500 3000 -Wire Wire Line - 5500 3500 5500 3800 -Wire Wire Line - 5250 3800 5800 3800 -Connection ~ 5250 3800 -Connection ~ 5500 3800 -Wire Wire Line - 5250 4350 4900 4350 -Wire Wire Line - 4900 4350 4900 3500 -Connection ~ 4900 3500 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub deleted file mode 100644 index 4f386a6f..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit opto_isolator_switch -.subckt opto_isolator_switch net-_r1-pad1_ net-_f1-pad4_ net-_c1-pad1_ net-_c1-pad2_ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/opto_isolator_switch/opto_isolator_switch.cir -r1 net-_r1-pad1_ net-_f1-pad3_ 1000 -* f1 -r2 net-_c1-pad2_ net-_f1-pad4_ 1000 -c1 net-_c1-pad1_ net-_c1-pad2_ 14n -Vf1 net-_f1-pad3_ net-_f1-pad4_ 0 -f1 net-_c1-pad1_ net-_c1-pad2_ Vf1 3 -* Control Statements - -.ends opto_isolator_switch
\ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml b/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml deleted file mode 100644 index 2c2d65c1..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/opto_isolator_switch_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt b/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt deleted file mode 100644 index e69de29b..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_i.txt +++ /dev/null diff --git a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt b/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt deleted file mode 100644 index e69de29b..00000000 --- a/src/SubcircuitLibrary/opto_isolator_switch/plot_data_v.txt +++ /dev/null diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib deleted file mode 100644 index ef18bb50..00000000 --- a/src/SubcircuitLibrary/scr/D.lib +++ /dev/null @@ -1,20 +0,0 @@ -.MODEL D1N750 D( -+ Vj=.75 -+ Nbvl=14.976 -+ Cjo=175p -+ Rs=.25 -+ Isr=1.859n -+ Eg=1.11 -+ M=.5516 -+ Nbv=1.6989 -+ N=1 -+ Tbv1=-21.277u -+ Bv=8.1 -+ Fc=.5 -+ Ikf=0 -+ Nr=2 -+ Ibv=20.245m -+ Is=880.5E-18 -+ Xti=3 -+ Ibvl=1.9556m -)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib deleted file mode 100644 index a2f61dce..00000000 --- a/src/SubcircuitLibrary/scr/PowerDiode.lib +++ /dev/null @@ -1,20 +0,0 @@ -.MODEL PowerDiode D( -+ Vj=.75 -+ Nbvl=14.976 -+ Cjo=175p -+ Rs=.25 -+ Isr=1.859n -+ Eg=1.11 -+ M=.5516 -+ Nbv=1.6989 -+ N=1 -+ Tbv1=-21.277u -+ bv=1800 -+ Fc=.5 -+ Ikf=0 -+ Nr=2 -+ Ibv=20.245m -+ Is=2.2E-15 -+ Xti=3 -+ Ibvl=1.9556m -)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/analysis b/src/SubcircuitLibrary/scr/analysis deleted file mode 100644 index 687c71ec..00000000 --- a/src/SubcircuitLibrary/scr/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-12 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib deleted file mode 100644 index 0a685b80..00000000 --- a/src/SubcircuitLibrary/scr/scr-cache.lib +++ /dev/null @@ -1,150 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "C" 25 -100 50 H V L CNN -F2 "" 38 -150 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 50 50 1 1 P -X ~ 2 0 -150 110 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# CCCS -# -DEF CCCS F 0 40 Y Y 1 F N -F0 "F" 0 150 50 H V C CNN -F1 "CCCS" -200 -50 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# DIODE -# -DEF DIODE D 0 40 N N 1 F N -F0 "D" 0 100 40 H V C CNN -F1 "DIODE" 0 -100 40 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - D? - S* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -200 0 150 R 40 40 1 1 P -X K 2 200 0 150 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# R-RESCUE-scr -# -DEF R-RESCUE-scr R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "R-RESCUE-scr" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -# aswitch -# -DEF aswitch U 0 40 Y Y 1 F N -F0 "U" 450 300 60 H V C CNN -F1 "aswitch" 450 200 60 H V C CNN -F2 "" 450 100 60 H V C CNN -F3 "" 450 100 60 H V C CNN -DRAW -S 200 250 650 100 0 1 0 N -X ~ 2 0 150 200 R 50 50 1 1 O -X ~ 3 850 150 200 L 50 50 1 1 O -X ~ 1_IN 450 -100 200 U 50 20 1 1 I -ENDDRAW -ENDDEF -# -# dc-RESCUE-scr -# -DEF dc-RESCUE-scr v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/scr/scr-rescue.lib b/src/SubcircuitLibrary/scr/scr-rescue.lib deleted file mode 100644 index 64237b7d..00000000 --- a/src/SubcircuitLibrary/scr/scr-rescue.lib +++ /dev/null @@ -1,39 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# R-RESCUE-scr -# -DEF R-RESCUE-scr R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "R-RESCUE-scr" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -# dc-RESCUE-scr -# -DEF dc-RESCUE-scr v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "dc-RESCUE-scr" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/scr/scr.cir b/src/SubcircuitLibrary/scr/scr.cir deleted file mode 100644 index 4b279764..00000000 --- a/src/SubcircuitLibrary/scr/scr.cir +++ /dev/null @@ -1,20 +0,0 @@ -* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:47:20 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 3 7 1 PORT -F2 3 9 2 3 100 -D1 5 2 D -C1 3 9 10u -F1 3 9 4 3 10 -v1 8 4 dc -v2 6 5 dc -U1 9 1 6 aswitch -R1 7 8 50 -R2 3 9 1 - -.end diff --git a/src/SubcircuitLibrary/scr/scr.cir.out b/src/SubcircuitLibrary/scr/scr.cir.out deleted file mode 100644 index d600f25d..00000000 --- a/src/SubcircuitLibrary/scr/scr.cir.out +++ /dev/null @@ -1,29 +0,0 @@ -* /opt/esim/src/subcircuitlibrary/scr/scr.cir - -.include PowerDiode.lib -* u2 3 7 1 port -* f2 -d1 5 2 PowerDiode -c1 3 9 10u -* f1 -v1 8 4 dc 0 -v2 6 5 dc 0 -* u1 9 1 6 aswitch -r1 7 8 50 -r2 3 9 1 -Vf2 2 3 0 -f2 3 9 Vf2 100 -Vf1 4 3 0 -f1 3 9 Vf1 10 -a1 9 (1 6) u1 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) -.tran 0e-12 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro deleted file mode 100644 index ca0df803..00000000 --- a/src/SubcircuitLibrary/scr/scr.pro +++ /dev/null @@ -1,45 +0,0 @@ -update=Wed Jul 31 19:51:09 2019 -last_client=kicad -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=scr-rescue -LibName2=eSim_Analog -LibName3=eSim_Devices -LibName4=eSim_Digital -LibName5=eSim_Hybrid -LibName6=eSim_Miscellaneous -LibName7=eSim_Sources -LibName8=eSim_Subckt -LibName9=eSim_User -LibName10=power -LibName11=device -LibName12=transistors -LibName13=conn -LibName14=linear -LibName15=regul -LibName16=74xx -LibName17=cmos4000 -LibName18=adc-dac -LibName19=memory -LibName20=xilinx -LibName21=special -LibName22=microcontrollers -LibName23=dsp -LibName24=microchip -LibName25=analog_switches -LibName26=motorola -LibName27=texas -LibName28=intel -LibName29=audio -LibName30=interface -LibName31=digital-audio -LibName32=philips -LibName33=display -LibName34=cypress -LibName35=siliconi -LibName36=opto -LibName37=atmel -LibName38=contrib -LibName39=valves diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch deleted file mode 100644 index 69244f56..00000000 --- a/src/SubcircuitLibrary/scr/scr.sch +++ /dev/null @@ -1,242 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:scr-rescue -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:scr-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "21 aug 2014" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 3600 3250 3600 3150 -Connection ~ 5550 4950 -Wire Wire Line - 5800 3900 5800 3850 -Wire Wire Line - 5800 3850 6150 3850 -Wire Wire Line - 6150 3850 6150 4950 -Wire Wire Line - 6150 4950 3600 4950 -Connection ~ 4300 4950 -Wire Wire Line - 4300 4950 4300 4050 -Wire Wire Line - 4300 4050 3850 4050 -Wire Wire Line - 4700 5400 4700 5950 -Wire Wire Line - 4250 5950 4250 5500 -Connection ~ 4250 4950 -Wire Wire Line - 4250 4950 4250 5200 -Wire Wire Line - 5550 3600 5550 3450 -Wire Wire Line - 5550 4950 5550 4250 -Wire Wire Line - 3600 4950 3600 4400 -Wire Wire Line - 3600 2300 3600 2850 -Wire Wire Line - 3600 2300 3150 2300 -Wire Wire Line - 3600 4150 3600 4300 -Wire Wire Line - 5550 4150 5550 4000 -Wire Wire Line - 5550 2550 5550 2250 -Wire Wire Line - 4700 4950 4700 5100 -Connection ~ 4700 4950 -Wire Wire Line - 6650 2000 6650 5950 -Connection ~ 4700 5950 -Wire Wire Line - 3850 4650 3850 5950 -Wire Wire Line - 3850 5950 6650 5950 -Connection ~ 4250 5950 -Wire Wire Line - 5800 4500 5800 5950 -Connection ~ 5800 5950 -$Comp -L PORT U2 -U 3 1 53F4C93D -P 6650 2250 -F 0 "U2" H 6650 2200 30 0000 C CNN -F 1 "PORT" H 6650 2250 30 0000 C CNN -F 2 "" H 6650 2250 60 0001 C CNN -F 3 "" H 6650 2250 60 0001 C CNN - 3 6650 2250 - -1 0 0 1 -$EndComp -$Comp -L PORT U2 -U 2 1 53F4C934 -P 2900 2300 -F 0 "U2" H 2900 2250 30 0000 C CNN -F 1 "PORT" H 2900 2300 30 0000 C CNN -F 2 "" H 2900 2300 60 0001 C CNN -F 3 "" H 2900 2300 60 0001 C CNN - 2 2900 2300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U2 -U 1 1 53F4C92A -P 6400 4950 -F 0 "U2" H 6400 4900 30 0000 C CNN -F 1 "PORT" H 6400 4950 30 0000 C CNN -F 2 "" H 6400 4950 60 0001 C CNN -F 3 "" H 6400 4950 60 0001 C CNN - 1 6400 4950 - -1 0 0 1 -$EndComp -$Comp -L CCCS F2 -U 1 1 53F4C735 -P 5750 4200 -F 0 "F2" H 5550 4300 50 0000 C CNN -F 1 "100" H 5550 4150 50 0000 C CNN -F 2 "" H 5750 4200 60 0001 C CNN -F 3 "" H 5750 4200 60 0001 C CNN - 1 5750 4200 - 0 1 1 0 -$EndComp -$Comp -L DIODE D1 -U 1 1 53F4C6D9 -P 5550 3800 -F 0 "D1" H 5550 3900 40 0000 C CNN -F 1 "D" H 5550 3700 40 0000 C CNN -F 2 "" H 5550 3800 60 0001 C CNN -F 3 "" H 5550 3800 60 0001 C CNN - 1 5550 3800 - 0 1 1 0 -$EndComp -$Comp -L C C1 -U 1 1 53F4C6C2 -P 4700 5250 -F 0 "C1" H 4750 5350 50 0000 L CNN -F 1 "10u" H 4750 5150 50 0000 L CNN -F 2 "" H 4700 5250 60 0001 C CNN -F 3 "" H 4700 5250 60 0001 C CNN - 1 4700 5250 - 1 0 0 -1 -$EndComp -$Comp -L CCCS F1 -U 1 1 53F4C67F -P 3800 4350 -F 0 "F1" H 3600 4450 50 0000 C CNN -F 1 "10" H 3600 4300 50 0000 C CNN -F 2 "" H 3800 4350 60 0001 C CNN -F 3 "" H 3800 4350 60 0001 C CNN - 1 3800 4350 - 0 1 1 0 -$EndComp -$Comp -L dc-RESCUE-scr v1 -U 1 1 565DBF58 -P 3600 3700 -F 0 "v1" H 3400 3800 60 0000 C CNN -F 1 "dc" H 3400 3650 60 0000 C CNN -F 2 "R1" H 3300 3700 60 0000 C CNN -F 3 "" H 3600 3700 60 0000 C CNN - 1 3600 3700 - 1 0 0 -1 -$EndComp -$Comp -L dc-RESCUE-scr v2 -U 1 1 565DC066 -P 5550 3000 -F 0 "v2" H 5350 3100 60 0000 C CNN -F 1 "dc" H 5350 2950 60 0000 C CNN -F 2 "R1" H 5250 3000 60 0000 C CNN -F 3 "" H 5550 3000 60 0000 C CNN - 1 5550 3000 - 1 0 0 -1 -$EndComp -$Comp -L aswitch U1 -U 1 1 565DC87E -P 6400 2100 -F 0 "U1" H 6850 2400 60 0000 C CNN -F 1 "aswitch" H 6850 2300 60 0000 C CNN -F 2 "" H 6850 2200 60 0000 C CNN -F 3 "" H 6850 2200 60 0000 C CNN - 1 6400 2100 - -1 0 0 1 -$EndComp -Wire Wire Line - 5950 2000 6650 2000 -$Comp -L R-RESCUE-scr R1 -U 1 1 5666B019 -P 3550 2950 -F 0 "R1" H 3600 3080 50 0000 C CNN -F 1 "50" H 3600 3000 50 0000 C CNN -F 2 "" H 3600 2930 30 0000 C CNN -F 3 "" V 3600 3000 30 0000 C CNN - 1 3550 2950 - 0 1 1 0 -$EndComp -$Comp -L R-RESCUE-scr R2 -U 1 1 5666B17A -P 4200 5300 -F 0 "R2" H 4250 5430 50 0000 C CNN -F 1 "1" H 4250 5350 50 0000 C CNN -F 2 "" H 4250 5280 30 0000 C CNN -F 3 "" V 4250 5350 30 0000 C CNN - 1 4200 5300 - 0 1 1 0 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/scr/scr.sub b/src/SubcircuitLibrary/scr/scr.sub deleted file mode 100644 index 398c8921..00000000 --- a/src/SubcircuitLibrary/scr/scr.sub +++ /dev/null @@ -1,23 +0,0 @@ -* Subcircuit scr -.subckt scr 3 7 1 -* /opt/esim/src/subcircuitlibrary/scr/scr.cir -.include PowerDiode.lib -* f2 -d1 5 2 PowerDiode -c1 3 9 10u -* f1 -v1 8 4 dc 0 -v2 6 5 dc 0 -* u1 9 1 6 aswitch -r1 7 8 50 -r2 3 9 1 -Vf2 2 3 0 -f2 3 9 Vf2 100 -Vf1 4 3 0 -f1 3 9 Vf1 10 -a1 9 (1 6) u1 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) -* Control Statements - -.ends scr diff --git a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml deleted file mode 100644 index 8ff6e8d3..00000000 --- a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/userDiode.lib b/src/SubcircuitLibrary/scr/userDiode.lib deleted file mode 100644 index 89b96f4a..00000000 --- a/src/SubcircuitLibrary/scr/userDiode.lib +++ /dev/null @@ -1 +0,0 @@ -.MODEL D1N750 D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=880.5E-18 Xti=3 Ibvl=1.9556m ) diff --git a/src/SubcircuitLibrary/triac/PowerDiode.lib b/src/SubcircuitLibrary/triac/PowerDiode.lib deleted file mode 100644 index d6fb6469..00000000 --- a/src/SubcircuitLibrary/triac/PowerDiode.lib +++ /dev/null @@ -1 +0,0 @@ -.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m ) diff --git a/src/SubcircuitLibrary/triac/analysis b/src/SubcircuitLibrary/triac/analysis deleted file mode 100644 index ebd5c0a9..00000000 --- a/src/SubcircuitLibrary/triac/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/triac/triac-cache.lib b/src/SubcircuitLibrary/triac/triac-cache.lib deleted file mode 100644 index 0466a3e6..00000000 --- a/src/SubcircuitLibrary/triac/triac-cache.lib +++ /dev/null @@ -1,139 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C? - C_????_* - C_???? - SMD*_c - Capacitor* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# CCCS -# -DEF CCCS F 0 40 Y Y 1 F N -F0 "F" 0 150 50 H V C CNN -F1 "CCCS" -200 -50 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# D -# -DEF D D 0 40 N N 1 F N -F0 "D" 0 100 50 H V C CNN -F1 "D" 0 -100 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - Diode_* - D-Pak_TO252AA - *SingleDiode - *_Diode_* - *SingleDiode* -$ENDFPLIST -DRAW -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -150 0 100 R 40 40 1 1 P -X K 2 150 0 100 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -# aswitch -# -DEF aswitch U 0 40 Y Y 1 F N -F0 "U" 450 300 60 H V C CNN -F1 "aswitch" 450 200 60 H V C CNN -F2 "" 450 100 60 H V C CNN -F3 "" 450 100 60 H V C CNN -DRAW -S 200 250 650 100 0 1 0 N -X ~ 2 0 150 200 R 50 50 1 1 O -X ~ 3 850 150 200 L 50 50 1 1 O -X ~ 1_IN 450 -100 200 U 50 20 1 1 I -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/triac/triac.cir b/src/SubcircuitLibrary/triac/triac.cir deleted file mode 100644 index c533d42f..00000000 --- a/src/SubcircuitLibrary/triac/triac.cir +++ /dev/null @@ -1,23 +0,0 @@ -* /opt/eSim/src/SubcircuitLibrary/triac/triac.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:32:06 2015 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U3 8 11 10 PORT -F3 8 9 1 8 10 -v3 7 2 DC -F2 8 9 3 5 10 -v2 6 3 DC -C1 8 9 10u -F1 8 9 4 8 100 -v1 10 4 DC -U1 9 11 6 aswitch -U2 9 2 11 aswitch -R1 8 9 1 -D1 5 8 D -D2 1 7 D - -.end diff --git a/src/SubcircuitLibrary/triac/triac.cir.out b/src/SubcircuitLibrary/triac/triac.cir.out deleted file mode 100644 index d2eb7c77..00000000 --- a/src/SubcircuitLibrary/triac/triac.cir.out +++ /dev/null @@ -1,38 +0,0 @@ -* /opt/esim/src/subcircuitlibrary/triac/triac.cir - -.include PowerDiode.lib -* u3 8 11 10 port -* f3 -v3 7 2 dc 0 -* f2 -v2 6 3 dc 0 -c1 8 9 10u -* f1 -v1 10 4 dc 0 -* u1 9 11 6 aswitch -* u2 9 2 11 aswitch -r1 8 9 1 -d1 5 8 PowerDiode -d2 1 7 PowerDiode -Vf3 1 8 0 -f3 8 9 Vf3 10 -Vf2 3 5 0 -f2 8 9 Vf2 10 -Vf1 4 8 0 -f1 8 9 Vf1 100 -a1 9 (11 6) u1 -a2 9 (2 11) u2 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) - -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/triac/triac.pro b/src/SubcircuitLibrary/triac/triac.pro deleted file mode 100644 index 5b1f5f89..00000000 --- a/src/SubcircuitLibrary/triac/triac.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=Tue Dec 8 14:16:32 2015 -last_client=eeschema -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=eSim_Analog -LibName2=eSim_Devices -LibName3=eSim_Digital -LibName4=eSim_Hybrid -LibName5=eSim_Miscellaneous -LibName6=eSim_Sources -LibName7=eSim_Subckt -LibName8=eSim_User -LibName9=power -LibName10=device -LibName11=transistors -LibName12=conn -LibName13=linear -LibName14=regul -LibName15=74xx -LibName16=cmos4000 -LibName17=adc-dac -LibName18=memory -LibName19=xilinx -LibName20=special -LibName21=microcontrollers -LibName22=dsp -LibName23=microchip -LibName24=analog_switches -LibName25=motorola -LibName26=texas -LibName27=intel -LibName28=audio -LibName29=interface -LibName30=digital-audio -LibName31=philips -LibName32=display -LibName33=cypress -LibName34=siliconi -LibName35=opto -LibName36=atmel -LibName37=contrib -LibName38=valves diff --git a/src/SubcircuitLibrary/triac/triac.sch b/src/SubcircuitLibrary/triac/triac.sch deleted file mode 100644 index f30533a0..00000000 --- a/src/SubcircuitLibrary/triac/triac.sch +++ /dev/null @@ -1,308 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:triac-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "22 sep 2014" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L PORT U3 -U 3 1 541D1606 -P 1250 1750 -F 0 "U3" H 1250 1700 30 0000 C CNN -F 1 "PORT" H 1250 1750 30 0000 C CNN -F 2 "" H 1250 1750 60 0001 C CNN -F 3 "" H 1250 1750 60 0001 C CNN - 3 1250 1750 - 1 0 0 -1 -$EndComp -$Comp -L PORT U3 -U 2 1 541D1601 -P 1300 900 -F 0 "U3" H 1300 850 30 0000 C CNN -F 1 "PORT" H 1300 900 30 0000 C CNN -F 2 "" H 1300 900 60 0001 C CNN -F 3 "" H 1300 900 60 0001 C CNN - 2 1300 900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U3 -U 1 1 541D15F6 -P 1150 4050 -F 0 "U3" H 1150 4000 30 0000 C CNN -F 1 "PORT" H 1150 4050 30 0000 C CNN -F 2 "" H 1150 4050 60 0001 C CNN -F 3 "" H 1150 4050 60 0001 C CNN - 1 1150 4050 - 1 0 0 -1 -$EndComp -$Comp -L CCCS F3 -U 1 1 541D1417 -P 6250 3100 -F 0 "F3" H 6050 3200 50 0000 C CNN -F 1 "10" H 6050 3050 50 0000 C CNN -F 2 "" H 6250 3100 60 0001 C CNN -F 3 "" H 6250 3100 60 0001 C CNN - 1 6250 3100 - 0 1 1 0 -$EndComp -$Comp -L DC v3 -U 1 1 541D13FB -P 6050 1950 -F 0 "v3" H 5850 2050 60 0000 C CNN -F 1 "DC" H 5850 1900 60 0000 C CNN -F 2 "R1" H 5750 1950 60 0000 C CNN -F 3 "" H 6050 1950 60 0001 C CNN - 1 6050 1950 - -1 0 0 1 -$EndComp -$Comp -L CCCS F2 -U 1 1 541D13A3 -P 3900 2550 -F 0 "F2" H 3700 2650 50 0000 C CNN -F 1 "10" H 3700 2500 50 0000 C CNN -F 2 "" H 3900 2550 60 0001 C CNN -F 3 "" H 3900 2550 60 0001 C CNN - 1 3900 2550 - 0 1 1 0 -$EndComp -$Comp -L DC v2 -U 1 1 541D1398 -P 3700 1850 -F 0 "v2" H 3500 1950 60 0000 C CNN -F 1 "DC" H 3500 1800 60 0000 C CNN -F 2 "R1" H 3400 1850 60 0000 C CNN -F 3 "" H 3700 1850 60 0001 C CNN - 1 3700 1850 - 1 0 0 -1 -$EndComp -$Comp -L C C1 -U 1 1 541D137C -P 3300 4350 -F 0 "C1" H 3350 4450 50 0000 L CNN -F 1 "10u" H 3350 4250 50 0000 L CNN -F 2 "" H 3300 4350 60 0001 C CNN -F 3 "" H 3300 4350 60 0001 C CNN - 1 3300 4350 - 1 0 0 -1 -$EndComp -$Comp -L CCCS F1 -U 1 1 541D1363 -P 2100 3600 -F 0 "F1" H 1900 3700 50 0000 C CNN -F 1 "100" H 1900 3550 50 0000 C CNN -F 2 "" H 2100 3600 60 0001 C CNN -F 3 "" H 2100 3600 60 0001 C CNN - 1 2100 3600 - 0 1 1 0 -$EndComp -$Comp -L DC v1 -U 1 1 541D1357 -P 1900 2900 -F 0 "v1" H 1700 3000 60 0000 C CNN -F 1 "DC" H 1700 2850 60 0000 C CNN -F 2 "R1" H 1600 2900 60 0000 C CNN -F 3 "" H 1900 2900 60 0001 C CNN - 1 1900 2900 - 1 0 0 -1 -$EndComp -$Comp -L aswitch U1 -U 1 1 56669B8A -P 4600 1100 -F 0 "U1" H 5050 1400 60 0000 C CNN -F 1 "aswitch" H 5050 1300 60 0000 C CNN -F 2 "" H 5050 1200 60 0000 C CNN -F 3 "" H 5050 1200 60 0000 C CNN - 1 4600 1100 - -1 0 0 1 -$EndComp -$Comp -L aswitch U2 -U 1 1 56669DB5 -P 6400 1350 -F 0 "U2" H 6850 1650 60 0000 C CNN -F 1 "aswitch" H 6850 1550 60 0000 C CNN -F 2 "" H 6850 1450 60 0000 C CNN -F 3 "" H 6850 1450 60 0000 C CNN - 1 6400 1350 - 1 0 0 -1 -$EndComp -Connection ~ 4600 900 -Wire Wire Line - 4600 1250 4600 900 -Wire Wire Line - 1900 1750 1500 1750 -Connection ~ 6300 4900 -Wire Wire Line - 6300 3400 6300 4900 -Connection ~ 3950 4900 -Wire Wire Line - 3950 2850 3950 4900 -Connection ~ 2700 4050 -Wire Wire Line - 2700 3300 2700 4050 -Wire Wire Line - 2150 3300 2700 3300 -Connection ~ 3300 4900 -Wire Wire Line - 7450 4900 7450 700 -Connection ~ 3700 4050 -Wire Wire Line - 6050 4050 6050 3150 -Wire Wire Line - 6050 2400 6050 2500 -Wire Wire Line - 3700 1250 3750 1250 -Wire Wire Line - 3700 1400 3700 1250 -Wire Wire Line - 3700 2850 3700 2600 -Connection ~ 2750 4050 -Wire Wire Line - 2750 4050 2750 4150 -Wire Wire Line - 1900 3350 1900 3550 -Wire Wire Line - 1900 2450 1900 1750 -Wire Wire Line - 1900 4050 1900 3650 -Wire Wire Line - 3300 4050 3300 4200 -Wire Wire Line - 3700 3150 3700 4050 -Connection ~ 3300 4050 -Wire Wire Line - 3700 2500 3700 2300 -Wire Wire Line - 6050 1200 6050 1500 -Wire Wire Line - 6400 1200 6050 1200 -Wire Wire Line - 6050 2800 6050 3050 -Wire Wire Line - 2750 4450 2750 4900 -Wire Wire Line - 3300 4500 3300 4900 -Connection ~ 7450 1400 -Wire Wire Line - 2150 4900 2150 3900 -Wire Wire Line - 2150 4900 7450 4900 -Connection ~ 2750 4900 -Wire Wire Line - 4450 2250 3950 2250 -Wire Wire Line - 4450 4050 4450 2250 -Connection ~ 4450 4050 -Wire Wire Line - 6650 2800 6300 2800 -Wire Wire Line - 6650 4050 6650 2800 -Connection ~ 6050 4050 -Wire Wire Line - 1550 900 7250 900 -Wire Wire Line - 1400 4050 6650 4050 -Connection ~ 1900 4050 -Wire Wire Line - 7450 700 4150 700 -Wire Wire Line - 4150 700 4150 1000 -Wire Wire Line - 6850 1450 7350 1450 -Wire Wire Line - 7350 1450 7350 1400 -Wire Wire Line - 7350 1400 7450 1400 -Wire Wire Line - 7250 900 7250 1200 -$Comp -L R R1 -U 1 1 5666A886 -P 2700 4250 -F 0 "R1" H 2750 4380 50 0000 C CNN -F 1 "1" H 2750 4300 50 0000 C CNN -F 2 "" H 2750 4230 30 0000 C CNN -F 3 "" V 2750 4300 30 0000 C CNN - 1 2700 4250 - 0 1 1 0 -$EndComp -$Comp -L D D1 -U 1 1 5666A9A7 -P 3700 3000 -F 0 "D1" H 3700 3100 50 0000 C CNN -F 1 "D" H 3700 2900 50 0000 C CNN -F 2 "" H 3700 3000 60 0000 C CNN -F 3 "" H 3700 3000 60 0000 C CNN - 1 3700 3000 - 0 1 1 0 -$EndComp -$Comp -L D D2 -U 1 1 5666A9E4 -P 6050 2650 -F 0 "D2" H 6050 2750 50 0000 C CNN -F 1 "D" H 6050 2550 50 0000 C CNN -F 2 "" H 6050 2650 60 0000 C CNN -F 3 "" H 6050 2650 60 0000 C CNN - 1 6050 2650 - 0 -1 -1 0 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/triac/triac.sub b/src/SubcircuitLibrary/triac/triac.sub deleted file mode 100644 index 760908b0..00000000 --- a/src/SubcircuitLibrary/triac/triac.sub +++ /dev/null @@ -1,32 +0,0 @@ -* Subcircuit triac -.subckt triac 8 11 10 -* /opt/esim/src/subcircuitlibrary/triac/triac.cir -.include PowerDiode.lib -* f3 -v3 7 2 dc 0 -* f2 -v2 6 3 dc 0 -c1 8 9 10u -* f1 -v1 10 4 dc 0 -* u1 9 11 6 aswitch -* u2 9 2 11 aswitch -r1 8 9 1 -d1 5 8 PowerDiode -d2 1 7 PowerDiode -Vf3 1 8 0 -f3 8 9 Vf3 10 -Vf2 3 5 0 -f2 8 9 Vf2 10 -Vf1 4 8 0 -f1 8 9 Vf1 100 -a1 9 (11 6) u1 -a2 9 (2 11) u2 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) - -* Control Statements - -.ends triac diff --git a/src/SubcircuitLibrary/triac/triac_Previous_Values.xml b/src/SubcircuitLibrary/triac/triac_Previous_Values.xml deleted file mode 100644 index 80da52b3..00000000 --- a/src/SubcircuitLibrary/triac/triac_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">1</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-1</field10></u2></model><devicemodel><d2><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d2><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/analysis b/src/SubcircuitLibrary/ua741/analysis deleted file mode 100644 index 52ccc5ec..00000000 --- a/src/SubcircuitLibrary/ua741/analysis +++ /dev/null @@ -1 +0,0 @@ -.ac lin 0 0Hz 0Hz
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/ua741-cache.lib b/src/SubcircuitLibrary/ua741/ua741-cache.lib deleted file mode 100644 index 9114d342..00000000 --- a/src/SubcircuitLibrary/ua741/ua741-cache.lib +++ /dev/null @@ -1,100 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Saturday 17 November 2012 08:10:48 AM IST -#encoding utf-8 -# -# C -# -DEF C C 0 10 N Y 1 F N -F0 "C" 50 100 50 H V L CNN -F1 "C" 50 -100 50 H V L CNN -$FPLIST - SM* - C? - C1-1 -$ENDFPLIST -DRAW -P 2 0 1 10 -100 -30 100 -30 N -P 2 0 1 10 -100 30 100 30 N -X ~ 1 0 200 170 D 40 40 1 1 P -X ~ 2 0 -200 170 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# GND -# -DEF ~GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 0 30 H I C CNN -F1 "GND" 0 -70 30 H I C CNN -DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N -X GND 1 0 0 0 U 30 30 1 1 W N -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 8 F N -F0 "U" 0 -50 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 I -X ~ 2 250 0 100 L 30 30 2 1 I -X ~ 3 250 0 100 L 30 30 3 1 I -X ~ 4 250 0 100 L 30 30 4 1 I -X ~ 5 250 0 100 L 30 30 5 1 I -X ~ 6 250 0 100 L 30 30 6 1 I -X ~ 7 250 0 100 L 30 30 7 1 I -X ~ 8 250 0 100 L 30 30 8 1 I -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 270 30 H I C CNN -F1 "PWR_FLAG" 0 230 30 H V C CNN -DRAW -X pwr 1 0 0 0 U 20 20 0 0 w -P 3 0 1 0 0 0 0 100 0 100 N -P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N -ENDDRAW -ENDDEF -# -# R -# -DEF R R 0 0 N Y 1 F N -F0 "R" 80 0 50 V V C CNN -F1 "R" 0 0 50 V V C CNN -$FPLIST - R? - SM0603 - SM0805 - R?-* -$ENDFPLIST -DRAW -S -40 150 40 -150 0 1 12 N -X ~ 1 0 250 100 D 60 60 1 1 P -X ~ 2 0 -250 100 U 60 60 1 1 P -ENDDRAW -ENDDEF -# -# VCVS -# -DEF VCVS E 0 40 Y Y 1 F N -F0 "E" -200 100 50 H V C CNN -F1 "VCVS" -200 -50 50 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/ua741/ua741.cir b/src/SubcircuitLibrary/ua741/ua741.cir deleted file mode 100644 index de797429..00000000 --- a/src/SubcircuitLibrary/ua741/ua741.cir +++ /dev/null @@ -1,15 +0,0 @@ -* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -*Sheet Name:/ -U1 6 7 3 PORT -Rout1 3 2 75 -Eout1 2 0 1 0 1 -Cbw1 1 0 31.85e-9 -Rbw1 1 4 0.5e6 -Ein1 4 0 7 6 100e3 -Rin1 7 6 2e6 - -.end diff --git a/src/SubcircuitLibrary/ua741/ua741.cir.out b/src/SubcircuitLibrary/ua741/ua741.cir.out deleted file mode 100644 index 72e68514..00000000 --- a/src/SubcircuitLibrary/ua741/ua741.cir.out +++ /dev/null @@ -1,18 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist - -* u1 6 7 3 port -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/ua741/ua741.pro b/src/SubcircuitLibrary/ua741/ua741.pro deleted file mode 100644 index 5dbb81a5..00000000 --- a/src/SubcircuitLibrary/ua741/ua741.pro +++ /dev/null @@ -1,72 +0,0 @@ -update=Monday 17 December 2012 06:14:06 PM IST -last_client=eeschema -[eeschema] -version=1 -LibDir=/home/yogesh/FreeEDA/library -NetFmt=1 -HPGLSpd=20 -HPGLDm=15 -HPGLNum=1 -offX_A4=0 -offY_A4=0 -offX_A3=0 -offY_A3=0 -offX_A2=0 -offY_A2=0 -offX_A1=0 -offY_A1=0 -offX_A0=0 -offY_A0=0 -offX_A=0 -offY_A=0 -offX_B=0 -offY_B=0 -offX_C=0 -offY_C=0 -offX_D=0 -offY_D=0 -offX_E=0 -offY_E=0 -RptD_X=0 -RptD_Y=100 -RptLab=1 -LabSize=60 -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=transistors -LibName4=conn -LibName5=linear -LibName6=regul -LibName7=74xx -LibName8=cmos4000 -LibName9=adc-dac -LibName10=memory -LibName11=xilinx -LibName12=special -LibName13=microcontrollers -LibName14=dsp -LibName15=microchip -LibName16=analog_switches -LibName17=motorola -LibName18=texas -LibName19=intel -LibName20=audio -LibName21=interface -LibName22=digital-audio -LibName23=philips -LibName24=display -LibName25=cypress -LibName26=siliconi -LibName27=opto -LibName28=atmel -LibName29=contrib -LibName30=valves -LibName31=analogSpice -LibName32=converterSpice -LibName33=digitalSpice -LibName34=linearSpice -LibName35=measurementSpice -LibName36=portSpice -LibName37=sourcesSpice -LibName38=analogXSpice diff --git a/src/SubcircuitLibrary/ua741/ua741.sch b/src/SubcircuitLibrary/ua741/ua741.sch deleted file mode 100644 index 7dfc5e1a..00000000 --- a/src/SubcircuitLibrary/ua741/ua741.sch +++ /dev/null @@ -1,219 +0,0 @@ -EESchema Schematic File Version 2 date Wednesday 19 December 2012 10:15:16 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:analogXSpice -LIBS:ua741-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Text Notes 3800 2400 0 60 ~ 0 -Op-Amp -Text Notes 3750 2850 0 60 ~ 0 -VCCS -Text Notes 5800 2500 0 60 ~ 0 -out -Text Notes 2750 3100 0 60 ~ 0 -- -Text Notes 2700 2600 0 60 ~ 0 -+ -$Comp -L PORT U1 -U 6 1 5082C027 -P 6250 2500 -F 0 "U1" H 6250 2450 30 0000 C CNN -F 1 "PORT" H 6250 2500 30 0000 C CNN - 6 6250 2500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 2 1 5082C011 -P 2300 3100 -F 0 "U1" H 2300 3050 30 0000 C CNN -F 1 "PORT" H 2300 3100 30 0000 C CNN - 2 2300 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5082C00B -P 2250 2600 -F 0 "U1" H 2250 2550 30 0000 C CNN -F 1 "PORT" H 2250 2600 30 0000 C CNN - 3 2250 2600 - 1 0 0 -1 -$EndComp -Connection ~ 3700 3200 -Wire Wire Line - 3450 3200 3700 3200 -Connection ~ 5000 3300 -Wire Wire Line - 3700 3300 5250 3300 -Wire Wire Line - 5250 3300 5250 3200 -Connection ~ 4550 3300 -Wire Wire Line - 5000 3300 5000 2950 -Connection ~ 3700 3300 -Wire Wire Line - 4550 3300 4550 3100 -Wire Wire Line - 3900 2500 3700 2500 -Wire Wire Line - 3700 2500 3700 2550 -Wire Wire Line - 3450 2900 3300 2900 -Wire Wire Line - 3300 2900 3300 3200 -Wire Wire Line - 3300 3200 2950 3200 -Connection ~ 2950 3100 -Wire Wire Line - 2950 3200 2950 3100 -Wire Wire Line - 3000 2600 2500 2600 -Wire Wire Line - 2550 3100 3000 3100 -Wire Wire Line - 2950 2600 2950 2500 -Connection ~ 2950 2600 -Wire Wire Line - 2950 2500 3300 2500 -Wire Wire Line - 3300 2500 3300 2800 -Wire Wire Line - 3300 2800 3450 2800 -Wire Wire Line - 3700 3150 3700 3400 -Wire Wire Line - 4550 2500 4550 2700 -Wire Wire Line - 4400 2500 5000 2500 -Wire Wire Line - 5000 2500 5000 2850 -Connection ~ 4550 2500 -Wire Wire Line - 5250 2600 5250 2500 -Wire Wire Line - 5250 2500 5350 2500 -Wire Wire Line - 5850 2500 6000 2500 -$Comp -L PWR_FLAG #FLG01 -U 1 1 508152A0 -P 3450 3200 -F 0 "#FLG01" H 3450 3470 30 0001 C CNN -F 1 "PWR_FLAG" H 3450 3430 30 0000 C CNN - 1 3450 3200 - 1 0 0 -1 -$EndComp -$Comp -L R Rout1 -U 1 1 50813F5B -P 5600 2500 -F 0 "Rout1" V 5680 2500 50 0000 C CNN -F 1 "75" V 5600 2500 50 0000 C CNN - 1 5600 2500 - 0 1 1 0 -$EndComp -$Comp -L VCVS Eout1 -U 1 1 50813F0F -P 5200 2900 -F 0 "Eout1" H 5000 3000 50 0000 C CNN -F 1 "1" H 5000 2850 50 0000 C CNN - 1 5200 2900 - 0 1 1 0 -$EndComp -$Comp -L C Cbw1 -U 1 1 50813EE0 -P 4550 2900 -F 0 "Cbw1" H 4600 3000 50 0000 L CNN -F 1 "31.85e-9" H 4600 2800 50 0000 L CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L R Rbw1 -U 1 1 50813EAB -P 4150 2500 -F 0 "Rbw1" V 4230 2500 50 0000 C CNN -F 1 "0.5e6" V 4150 2500 50 0000 C CNN - 1 4150 2500 - 0 1 1 0 -$EndComp -$Comp -L GND #PWR02 -U 1 1 50813E0D -P 3700 3400 -F 0 "#PWR02" H 3700 3400 30 0001 C CNN -F 1 "GND" H 3700 3330 30 0001 C CNN - 1 3700 3400 - 1 0 0 -1 -$EndComp -$Comp -L VCVS Ein1 -U 1 1 50813D7C -P 3650 2850 -F 0 "Ein1" H 3450 2950 50 0000 C CNN -F 1 "100e3" H 3450 2800 50 0000 C CNN - 1 3650 2850 - 0 1 1 0 -$EndComp -$Comp -L R Rin1 -U 1 1 50813C57 -P 3000 2850 -F 0 "Rin1" V 3080 2850 50 0000 C CNN -F 1 "2e6" V 3000 2850 50 0000 C CNN - 1 3000 2850 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ua741/ua741.sub b/src/SubcircuitLibrary/ua741/ua741.sub deleted file mode 100644 index ad26c001..00000000 --- a/src/SubcircuitLibrary/ua741/ua741.sub +++ /dev/null @@ -1,12 +0,0 @@ -* Subcircuit ua741 -.subckt ua741 6 7 3 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist -rout1 3 2 75 -eout1 2 0 1 0 1 -cbw1 1 0 31.85e-9 -rbw1 1 4 0.5e6 -ein1 4 0 7 6 100e3 -rin1 7 6 2e6 -* Control Statements - -.ends ua741
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml b/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml deleted file mode 100644 index 9c7bb530..00000000 --- a/src/SubcircuitLibrary/ua741/ua741_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/D.lib b/src/SubcircuitLibrary/ujt/D.lib deleted file mode 100644 index 8a7fb4da..00000000 --- a/src/SubcircuitLibrary/ujt/D.lib +++ /dev/null @@ -1,2 +0,0 @@ -.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) - diff --git a/src/SubcircuitLibrary/ujt/analysis b/src/SubcircuitLibrary/ujt/analysis deleted file mode 100644 index ffc57a6b..00000000 --- a/src/SubcircuitLibrary/ujt/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 5e-03 100e-03 0e-03
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/emitter.lib b/src/SubcircuitLibrary/ujt/emitter.lib deleted file mode 100644 index 3e78b1ee..00000000 --- a/src/SubcircuitLibrary/ujt/emitter.lib +++ /dev/null @@ -1,11 +0,0 @@ -.model emitter D( -+ Vj=1 -+ Cjo=1.700E-12 -+ Rs=4.755E-01 -+ Is=21.3P -+ M=1.959E-01 -+ N=1.8 -+ Bv=1.000E+02 -+ tt=3.030E-09 -+ Ibv=1.000E-04 -) diff --git a/src/SubcircuitLibrary/ujt/plot_data_i.txt b/src/SubcircuitLibrary/ujt/plot_data_i.txt deleted file mode 100644 index e69de29b..00000000 --- a/src/SubcircuitLibrary/ujt/plot_data_i.txt +++ /dev/null diff --git a/src/SubcircuitLibrary/ujt/plot_data_v.txt b/src/SubcircuitLibrary/ujt/plot_data_v.txt deleted file mode 100644 index e69de29b..00000000 --- a/src/SubcircuitLibrary/ujt/plot_data_v.txt +++ /dev/null diff --git a/src/SubcircuitLibrary/ujt/ujt-cache.lib b/src/SubcircuitLibrary/ujt/ujt-cache.lib deleted file mode 100644 index ff75f664..00000000 --- a/src/SubcircuitLibrary/ujt/ujt-cache.lib +++ /dev/null @@ -1,137 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# CCVS -# -DEF CCVS H 0 40 Y Y 1 F N -F0 "H" 0 150 50 H V C CNN -F1 "CCVS" -200 -50 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -S -100 100 100 -100 0 1 0 N -X + 1 -300 50 200 R 35 35 1 1 P -X - 2 300 50 200 L 35 35 1 1 P -X +c 3 -50 -200 100 U 35 35 1 1 P -X -c 4 50 -200 100 U 35 35 1 1 P -ENDDRAW -ENDDEF -# -# NLDS -# -DEF NLDS BB 0 40 Y Y 1 F N -F0 "BB" 0 0 60 H V C CNN -F1 "NLDS" 0 0 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 0 0 141 0 1 0 N -X 1 1 0 350 200 D 50 50 1 1 B -X 2 2 0 -350 200 U 50 50 1 1 B -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# eSim_C -# -DEF eSim_C C 0 10 N Y 1 F N -F0 "C" 25 100 50 H V L CNN -F1 "eSim_C" 25 -100 50 H V L CNN -F2 "" 38 -150 30 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 20 -80 -30 80 -30 N -P 2 0 1 20 -80 30 80 30 N -X ~ 1 0 150 110 D 40 40 1 1 P -X ~ 2 0 -150 110 U 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_Diode -# -DEF eSim_Diode D 0 40 N N 1 F N -F0 "D" 0 100 50 H V C CNN -F1 "eSim_Diode" 0 -100 50 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - TO-???* - *SingleDiode - *_Diode_* - *SingleDiode* - D_* -$ENDFPLIST -DRAW -T 0 -100 50 60 0 0 0 A Normal 0 C C -T 0 100 50 60 0 0 0 K Normal 0 C C -P 2 0 1 6 50 50 50 -50 N -P 3 0 1 0 -50 50 50 0 -50 -50 F -X A 1 -150 0 100 R 40 40 1 1 P -X K 2 150 0 100 L 40 40 1 1 P -ENDDRAW -ENDDEF -# -# eSim_R -# -DEF eSim_R R 0 0 N Y 1 F N -F0 "R" 50 130 50 H V C CNN -F1 "eSim_R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -$FPLIST - R_* - Resistor_* -$ENDFPLIST -DRAW -S 150 10 -50 90 0 1 10 N -X ~ 1 -100 50 50 R 60 60 1 1 P -X ~ 2 200 50 50 L 60 60 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/src/SubcircuitLibrary/ujt/ujt.cir b/src/SubcircuitLibrary/ujt/ujt.cir deleted file mode 100644 index e0e911d7..00000000 --- a/src/SubcircuitLibrary/ujt/ujt.cir +++ /dev/null @@ -1,18 +0,0 @@ -* /home/bhargav/Downloads/eSim-1.1.2/src/SubcircuitLibrary/ujt/ujt.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 15 12:43:54 2019 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -R3 /0 /6 1000k -H1 /6 /0 /4 /5 1k -C1 /5 /7 35p -R1 /7 /2 38.15k -R2 /3 /5 2.518k -U1 /1 /2 /3 PORT -B1 /5 /7 I=0.00028*V(5,7)+0.00575*V(5,7)*V(6) -D1 /1 /4 eSim_Diode - -.end diff --git a/src/SubcircuitLibrary/ujt/ujt.cir.out b/src/SubcircuitLibrary/ujt/ujt.cir.out deleted file mode 100644 index 2045c539..00000000 --- a/src/SubcircuitLibrary/ujt/ujt.cir.out +++ /dev/null @@ -1,22 +0,0 @@ -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir - -.include emitter.lib -r3 /0 /6 1000k -* h1 -c1 /5 /7 35p -r1 /7 /2 38.15k -r2 /3 /5 2.518k -* u1 /1 /2 /3 port -b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) -d1 /1 /4 emitter -Vh1 /4 /5 0 -h1 /6 /0 Vh1 1k -.tran 5e-03 100e-03 0e-03 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/src/SubcircuitLibrary/ujt/ujt.pro b/src/SubcircuitLibrary/ujt/ujt.pro deleted file mode 100644 index 24c5e186..00000000 --- a/src/SubcircuitLibrary/ujt/ujt.pro +++ /dev/null @@ -1,44 +0,0 @@ -update=Tue Jun 11 16:36:40 2019 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../../kicadSchematicLibrary -[eeschema/libraries] -LibName1=power -LibName2=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_User -LibName3=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt -LibName4=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Sources -LibName5=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Power -LibName6=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Plot -LibName7=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Miscellaneous -LibName8=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Hybrid -LibName9=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Digital -LibName10=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Devices -LibName11=/home/bhargav/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Analog diff --git a/src/SubcircuitLibrary/ujt/ujt.sch b/src/SubcircuitLibrary/ujt/ujt.sch deleted file mode 100644 index a82bddf7..00000000 --- a/src/SubcircuitLibrary/ujt/ujt.sch +++ /dev/null @@ -1,199 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:eSim_User -LIBS:eSim_Subckt -LIBS:eSim_Sources -LIBS:eSim_Power -LIBS:eSim_Plot -LIBS:eSim_Miscellaneous -LIBS:eSim_Hybrid -LIBS:eSim_Digital -LIBS:eSim_Devices -LIBS:eSim_Analog -LIBS:ujt-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L eSim_R R3 -U 1 1 5CF5F733 -P 6650 3400 -F 0 "R3" H 6700 3530 50 0000 C CNN -F 1 "1000k" H 6700 3450 50 0000 C CNN -F 2 "" H 6700 3380 30 0000 C CNN -F 3 "" V 6700 3450 30 0000 C CNN - 1 6650 3400 - 0 1 -1 0 -$EndComp -$Comp -L CCVS H1 -U 1 1 5CF5F77B -P 6150 3350 -F 0 "H1" H 6150 3500 50 0000 C CNN -F 1 "1k" H 5950 3300 50 0000 C CNN -F 2 "" H 6150 3350 60 0000 C CNN -F 3 "" H 6150 3350 60 0000 C CNN - 1 6150 3350 - 0 1 1 0 -$EndComp -$Comp -L eSim_C C1 -U 1 1 5CF61B3A -P 5150 4700 -F 0 "C1" H 5175 4800 50 0000 L CNN -F 1 "35p" H 5175 4600 50 0000 L CNN -F 2 "" H 5188 4550 30 0000 C CNN -F 3 "" H 5150 4700 60 0000 C CNN - 1 5150 4700 - 1 0 0 -1 -$EndComp -$Comp -L eSim_R R1 -U 1 1 5CF6211F -P 4300 4850 -F 0 "R1" H 4350 4980 50 0000 C CNN -F 1 "38.15k" H 4350 4900 50 0000 C CNN -F 2 "" H 4350 4830 30 0000 C CNN -F 3 "" V 4350 4900 30 0000 C CNN - 1 4300 4850 - 0 -1 -1 0 -$EndComp -$Comp -L eSim_R R2 -U 1 1 5CF6218A -P 4550 3650 -F 0 "R2" H 4600 3780 50 0000 C CNN -F 1 "2.518k" H 4600 3700 50 0000 C CNN -F 2 "" H 4600 3630 30 0000 C CNN -F 3 "" V 4600 3700 30 0000 C CNN - 1 4550 3650 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 2 1 5CF6830A -P 4250 4150 -F 0 "U1" H 4300 4250 30 0000 C CNN -F 1 "PORT" H 4250 4150 30 0000 C CNN -F 2 "" H 4250 4150 60 0000 C CNN -F 3 "" H 4250 4150 60 0000 C CNN - 2 4250 4150 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 1 1 5CF689AD -P 5950 2200 -F 0 "U1" H 6000 2300 30 0000 C CNN -F 1 "PORT" H 5950 2200 30 0000 C CNN -F 2 "" H 5950 2200 60 0000 C CNN -F 3 "" H 5950 2200 60 0000 C CNN - 1 5950 2200 - 0 1 1 0 -$EndComp -$Comp -L PORT U1 -U 3 1 5CF69586 -P 4600 3000 -F 0 "U1" H 4650 3100 30 0000 C CNN -F 1 "PORT" H 4600 3000 30 0000 C CNN -F 2 "" H 4600 3000 60 0000 C CNN -F 3 "" H 4600 3000 60 0000 C CNN - 3 4600 3000 - 0 1 1 0 -$EndComp -Text Label 5600 4100 0 60 ~ 0 -5 -Text Label 5950 3150 0 60 ~ 0 -4 -Text Label 5950 2600 0 60 ~ 0 -1 -Text Label 6450 3050 0 60 ~ 0 -6 -Text Label 6450 3650 0 60 ~ 0 -0 -$Comp -L NLDS B1 -U 1 1 5CFD2C88 -P 5950 4800 -F 0 "B1" H 5950 4800 60 0000 C CNN -F 1 "I=0.00028*V(5,7)+0.00575*V(5,7)*V(6)" H 7050 4900 60 0000 C CNN -F 2 "" H 5950 4800 60 0000 C CNN -F 3 "" H 5950 4800 60 0000 C CNN - 1 5950 4800 - 1 0 0 -1 -$EndComp -Text Label 5350 5250 0 60 ~ 0 -7 -Text Label 4600 3450 0 60 ~ 0 -3 -Text Label 4250 4500 0 60 ~ 0 -2 -$Comp -L eSim_Diode D1 -U 1 1 5CFF8BB7 -P 5950 2850 -F 0 "D1" H 5950 2950 50 0000 C CNN -F 1 "eSim_Diode" H 5950 2750 50 0000 C CNN -F 2 "" H 5950 2850 60 0000 C CNN -F 3 "" H 5950 2850 60 0000 C CNN - 1 5950 2850 - 0 1 1 0 -$EndComp -Wire Wire Line - 6200 3050 6700 3050 -Wire Wire Line - 6700 3050 6700 3200 -Wire Wire Line - 6200 3650 6300 3650 -Wire Wire Line - 6300 3650 6700 3650 -Wire Wire Line - 5950 2450 5950 2700 -Wire Wire Line - 5950 3000 5950 3300 -Wire Wire Line - 5950 3400 5950 3850 -Wire Wire Line - 5950 3850 5950 4100 -Wire Wire Line - 5950 4100 5950 4450 -Wire Wire Line - 5150 4100 5150 4550 -Wire Wire Line - 4600 4100 5150 4100 -Wire Wire Line - 5150 4100 5950 4100 -Connection ~ 5950 4100 -Wire Wire Line - 5150 4850 5150 5250 -Wire Wire Line - 4250 5250 5150 5250 -Wire Wire Line - 5150 5250 5950 5250 -Wire Wire Line - 4250 5250 4250 4950 -Wire Wire Line - 4600 4100 4600 3850 -Connection ~ 5150 4100 -Wire Wire Line - 4250 4650 4250 4400 -Wire Wire Line - 4600 3550 4600 3250 -Wire Wire Line - 5950 5250 5950 5150 -Connection ~ 5150 5250 -Wire Wire Line - 6700 3650 6700 3500 -$EndSCHEMATC diff --git a/src/SubcircuitLibrary/ujt/ujt.sub b/src/SubcircuitLibrary/ujt/ujt.sub deleted file mode 100644 index 2fb1db35..00000000 --- a/src/SubcircuitLibrary/ujt/ujt.sub +++ /dev/null @@ -1,16 +0,0 @@ -* Subcircuit ujt -.subckt ujt /1 /2 /3 -* /home/bhargav/downloads/esim-1.1.2/src/subcircuitlibrary/ujt/ujt.cir -.include emitter.lib -r3 /0 /6 1000k -* h1 -c1 /5 /7 35p -r1 /7 /2 38.15k -r2 /3 /5 2.518k -b1 /5 /7 i=0.00028*v(5,7)+0.00575*v(5,7)*v(6) -d1 /1 /4 emitter -Vh1 /4 /5 0 -h1 /6 /0 Vh1 1k -* Control Statements - -.ends ujt
\ No newline at end of file diff --git a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml b/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml deleted file mode 100644 index 4468b395..00000000 --- a/src/SubcircuitLibrary/ujt/ujt_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source><v1 name="Source type">0</v1><ve1 name="Source type">0</ve1><i1 name="Source type">dc<field1 name="Value">0.000001m</field1></i1><v2 name="Source type">0</v2></source><model /><devicemodel><d1><field>/home/bhargav/Downloads/eSim-1.1.2/src/deviceModelLibrary/Diode/emitter.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">5</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |