Added :

1. Power Examples
2. eSim_Power.lib
3. Subcircuit for diac, scr, triac
4. Device model for Power Diode

15 files changed, 1016 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/triac/.triac.s.swp b/src/SubcircuitLibrary/triac/.triac.s.swp
new file mode 100644
index 00000000..1a4c2d0e
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/.triac.s.swp
diff --git a/src/SubcircuitLibrary/triac/.triac.sub.swp b/src/SubcircuitLibrary/triac/.triac.sub.swp
new file mode 100644
index 00000000..521ce758
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/.triac.sub.swp
diff --git a/src/SubcircuitLibrary/triac/PowerDiode.lib b/src/SubcircuitLibrary/triac/PowerDiode.lib
new file mode 100644
index 00000000..a2f61dce
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/PowerDiode.lib
@@ -0,0 +1,20 @@
+.MODEL PowerDiode D(
++ Vj=.75
++ Nbvl=14.976
++ Cjo=175p
++ Rs=.25
++ Isr=1.859n
++ Eg=1.11
++ M=.5516
++ Nbv=1.6989
++ N=1
++ Tbv1=-21.277u
++ bv=1800
++ Fc=.5
++ Ikf=0
++ Nr=2
++ Ibv=20.245m
++ Is=2.2E-15
++ Xti=3
++ Ibvl=1.9556m
+)
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/triac/analysis b/src/SubcircuitLibrary/triac/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/triac/triac-cache.lib b/src/SubcircuitLibrary/triac/triac-cache.lib
new file mode 100644
index 00000000..0466a3e6
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac-cache.lib
@@ -0,0 +1,139 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20  -80 -30  80 -30 N
+P 2 0 1 20  -80 30  80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CCCS
+#
+DEF CCCS F 0 40 Y Y 1 F N
+F0 "F" 0 150 50 H V C CNN
+F1 "CCCS" -200 -50 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# D
+#
+DEF D D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "D" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ Diode_*
+ D-Pak_TO252AA
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+$ENDFPLIST
+DRAW
+P 2 0 1 6  50 50  50 -50 N
+P 3 0 1 0  -50 50  50 0  -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# aswitch
+#
+DEF aswitch U 0 40 Y Y 1 F N
+F0 "U" 450 300 60 H V C CNN
+F1 "aswitch" 450 200 60 H V C CNN
+F2 "" 450 100 60 H V C CNN
+F3 "" 450 100 60 H V C CNN
+DRAW
+S 200 250 650 100 0 1 0 N
+X ~ 2 0 150 200 R 50 50 1 1 O
+X ~ 3 850 150 200 L 50 50 1 1 O
+X ~ 1_IN 450 -100 200 U 50 20 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/triac/triac.bak b/src/SubcircuitLibrary/triac/triac.bak
new file mode 100644
index 00000000..f30533a0
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.bak
@@ -0,0 +1,308 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:triac-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 sep 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L PORT U3
+U 3 1 541D1606
+P 1250 1750
+F 0 "U3" H 1250 1700 30  0000 C CNN
+F 1 "PORT" H 1250 1750 30  0000 C CNN
+F 2 "" H 1250 1750 60  0001 C CNN
+F 3 "" H 1250 1750 60  0001 C CNN
+	3    1250 1750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U3
+U 2 1 541D1601
+P 1300 900
+F 0 "U3" H 1300 850 30  0000 C CNN
+F 1 "PORT" H 1300 900 30  0000 C CNN
+F 2 "" H 1300 900 60  0001 C CNN
+F 3 "" H 1300 900 60  0001 C CNN
+	2    1300 900 
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U3
+U 1 1 541D15F6
+P 1150 4050
+F 0 "U3" H 1150 4000 30  0000 C CNN
+F 1 "PORT" H 1150 4050 30  0000 C CNN
+F 2 "" H 1150 4050 60  0001 C CNN
+F 3 "" H 1150 4050 60  0001 C CNN
+	1    1150 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L CCCS F3
+U 1 1 541D1417
+P 6250 3100
+F 0 "F3" H 6050 3200 50  0000 C CNN
+F 1 "10" H 6050 3050 50  0000 C CNN
+F 2 "" H 6250 3100 60  0001 C CNN
+F 3 "" H 6250 3100 60  0001 C CNN
+	1    6250 3100
+	0    1    1    0   
+$EndComp
+$Comp
+L DC v3
+U 1 1 541D13FB
+P 6050 1950
+F 0 "v3" H 5850 2050 60  0000 C CNN
+F 1 "DC" H 5850 1900 60  0000 C CNN
+F 2 "R1" H 5750 1950 60  0000 C CNN
+F 3 "" H 6050 1950 60  0001 C CNN
+	1    6050 1950
+	-1   0    0    1   
+$EndComp
+$Comp
+L CCCS F2
+U 1 1 541D13A3
+P 3900 2550
+F 0 "F2" H 3700 2650 50  0000 C CNN
+F 1 "10" H 3700 2500 50  0000 C CNN
+F 2 "" H 3900 2550 60  0001 C CNN
+F 3 "" H 3900 2550 60  0001 C CNN
+	1    3900 2550
+	0    1    1    0   
+$EndComp
+$Comp
+L DC v2
+U 1 1 541D1398
+P 3700 1850
+F 0 "v2" H 3500 1950 60  0000 C CNN
+F 1 "DC" H 3500 1800 60  0000 C CNN
+F 2 "R1" H 3400 1850 60  0000 C CNN
+F 3 "" H 3700 1850 60  0001 C CNN
+	1    3700 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L C C1
+U 1 1 541D137C
+P 3300 4350
+F 0 "C1" H 3350 4450 50  0000 L CNN
+F 1 "10u" H 3350 4250 50  0000 L CNN
+F 2 "" H 3300 4350 60  0001 C CNN
+F 3 "" H 3300 4350 60  0001 C CNN
+	1    3300 4350
+	1    0    0    -1  
+$EndComp
+$Comp
+L CCCS F1
+U 1 1 541D1363
+P 2100 3600
+F 0 "F1" H 1900 3700 50  0000 C CNN
+F 1 "100" H 1900 3550 50  0000 C CNN
+F 2 "" H 2100 3600 60  0001 C CNN
+F 3 "" H 2100 3600 60  0001 C CNN
+	1    2100 3600
+	0    1    1    0   
+$EndComp
+$Comp
+L DC v1
+U 1 1 541D1357
+P 1900 2900
+F 0 "v1" H 1700 3000 60  0000 C CNN
+F 1 "DC" H 1700 2850 60  0000 C CNN
+F 2 "R1" H 1600 2900 60  0000 C CNN
+F 3 "" H 1900 2900 60  0001 C CNN
+	1    1900 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L aswitch U1
+U 1 1 56669B8A
+P 4600 1100
+F 0 "U1" H 5050 1400 60  0000 C CNN
+F 1 "aswitch" H 5050 1300 60  0000 C CNN
+F 2 "" H 5050 1200 60  0000 C CNN
+F 3 "" H 5050 1200 60  0000 C CNN
+	1    4600 1100
+	-1   0    0    1   
+$EndComp
+$Comp
+L aswitch U2
+U 1 1 56669DB5
+P 6400 1350
+F 0 "U2" H 6850 1650 60  0000 C CNN
+F 1 "aswitch" H 6850 1550 60  0000 C CNN
+F 2 "" H 6850 1450 60  0000 C CNN
+F 3 "" H 6850 1450 60  0000 C CNN
+	1    6400 1350
+	1    0    0    -1  
+$EndComp
+Connection ~ 4600 900 
+Wire Wire Line
+	4600 1250 4600 900 
+Wire Wire Line
+	1900 1750 1500 1750
+Connection ~ 6300 4900
+Wire Wire Line
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+Connection ~ 3950 4900
+Wire Wire Line
+	3950 2850 3950 4900
+Connection ~ 2700 4050
+Wire Wire Line
+	2700 3300 2700 4050
+Wire Wire Line
+	2150 3300 2700 3300
+Connection ~ 3300 4900
+Wire Wire Line
+	7450 4900 7450 700 
+Connection ~ 3700 4050
+Wire Wire Line
+	6050 4050 6050 3150
+Wire Wire Line
+	6050 2400 6050 2500
+Wire Wire Line
+	3700 1250 3750 1250
+Wire Wire Line
+	3700 1400 3700 1250
+Wire Wire Line
+	3700 2850 3700 2600
+Connection ~ 2750 4050
+Wire Wire Line
+	2750 4050 2750 4150
+Wire Wire Line
+	1900 3350 1900 3550
+Wire Wire Line
+	1900 2450 1900 1750
+Wire Wire Line
+	1900 4050 1900 3650
+Wire Wire Line
+	3300 4050 3300 4200
+Wire Wire Line
+	3700 3150 3700 4050
+Connection ~ 3300 4050
+Wire Wire Line
+	3700 2500 3700 2300
+Wire Wire Line
+	6050 1200 6050 1500
+Wire Wire Line
+	6400 1200 6050 1200
+Wire Wire Line
+	6050 2800 6050 3050
+Wire Wire Line
+	2750 4450 2750 4900
+Wire Wire Line
+	3300 4500 3300 4900
+Connection ~ 7450 1400
+Wire Wire Line
+	2150 4900 2150 3900
+Wire Wire Line
+	2150 4900 7450 4900
+Connection ~ 2750 4900
+Wire Wire Line
+	4450 2250 3950 2250
+Wire Wire Line
+	4450 4050 4450 2250
+Connection ~ 4450 4050
+Wire Wire Line
+	6650 2800 6300 2800
+Wire Wire Line
+	6650 4050 6650 2800
+Connection ~ 6050 4050
+Wire Wire Line
+	1550 900  7250 900 
+Wire Wire Line
+	1400 4050 6650 4050
+Connection ~ 1900 4050
+Wire Wire Line
+	7450 700  4150 700 
+Wire Wire Line
+	4150 700  4150 1000
+Wire Wire Line
+	6850 1450 7350 1450
+Wire Wire Line
+	7350 1450 7350 1400
+Wire Wire Line
+	7350 1400 7450 1400
+Wire Wire Line
+	7250 900  7250 1200
+$Comp
+L R R1
+U 1 1 5666A886
+P 2700 4250
+F 0 "R1" H 2750 4380 50  0000 C CNN
+F 1 "1" H 2750 4300 50  0000 C CNN
+F 2 "" H 2750 4230 30  0000 C CNN
+F 3 "" V 2750 4300 30  0000 C CNN
+	1    2700 4250
+	0    1    1    0   
+$EndComp
+$Comp
+L D D1
+U 1 1 5666A9A7
+P 3700 3000
+F 0 "D1" H 3700 3100 50  0000 C CNN
+F 1 "D" H 3700 2900 50  0000 C CNN
+F 2 "" H 3700 3000 60  0000 C CNN
+F 3 "" H 3700 3000 60  0000 C CNN
+	1    3700 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L D D2
+U 1 1 5666A9E4
+P 6050 2650
+F 0 "D2" H 6050 2750 50  0000 C CNN
+F 1 "D" H 6050 2550 50  0000 C CNN
+F 2 "" H 6050 2650 60  0000 C CNN
+F 3 "" H 6050 2650 60  0000 C CNN
+	1    6050 2650
+	0    -1   -1   0   
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/triac/triac.cir b/src/SubcircuitLibrary/triac/triac.cir
new file mode 100644
index 00000000..c533d42f
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.cir
@@ -0,0 +1,23 @@
+* /opt/eSim/src/SubcircuitLibrary/triac/triac.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec  8 15:32:06 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  8 11 10 PORT		
+F3  8 9 1 8 10		
+v3  7 2 DC		
+F2  8 9 3 5 10		
+v2  6 3 DC		
+C1  8 9 10u		
+F1  8 9 4 8 100		
+v1  10 4 DC		
+U1  9 11 6 aswitch		
+U2  9 2 11 aswitch		
+R1  8 9 1		
+D1  5 8 D		
+D2  1 7 D		
+
+.end
diff --git a/src/SubcircuitLibrary/triac/triac.cir.ckt b/src/SubcircuitLibrary/triac/triac.cir.ckt
new file mode 100644
index 00000000..821b417b
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.cir.ckt
@@ -0,0 +1,26 @@
+* eeschema netlist version 1.1 (spice format) creation date: 09/20/14 11:23:24

+.include diode.lib

+

+u3  7 4 5 port

+* f3

+d2  3 2 diode

+v3  2 1 dc 0

+* Analog Switch analogswitch

+d1  11 7 diode

+* f2

+v2  8 10 dc 0

+* Analog Switch analogswitch

+c1  7 9 10u

+r1  7 9 1

+* f1

+v1  5 6 dc 0

+Vf3 3 7 0

+f3 7 9 Vf3 10

+Vf2 10 11 0

+f2 7 9 Vf2 10

+Vf1 6 7 0

+f1 7 9 Vf1 100

+a1 9 (1 4) u2

+.model u2 aswitch(cntl_on=-1 cntl_off=-0.1 r_on=0.0125 r_off=1000000)

+a2 9 (4 8) u1

+.model u1 aswitch(cntl_on=1 cntl_off=0.1 r_on=0.0125 r_off=1000000)

diff --git a/src/SubcircuitLibrary/triac/triac.cir.out b/src/SubcircuitLibrary/triac/triac.cir.out
new file mode 100644
index 00000000..d2eb7c77
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.cir.out
@@ -0,0 +1,38 @@
+* /opt/esim/src/subcircuitlibrary/triac/triac.cir
+
+.include PowerDiode.lib
+* u3  8 11 10 port
+* f3
+v3 7 2  dc 0
+* f2
+v2 6 3  dc 0
+c1  8 9 10u
+* f1
+v1 10 4  dc 0
+* u1  9 11 6 aswitch
+* u2  9 2 11 aswitch
+r1  8 9 1
+d1 5 8 PowerDiode
+d2 1 7 PowerDiode
+Vf3 1 8 0
+f3 8 9 Vf3 10
+Vf2 3 5 0
+f2 8 9 Vf2 10
+Vf1 4 8 0
+f1 8 9 Vf1 100
+a1 9 (11 6)  u1
+a2 9 (2 11)  u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) 
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) 
+
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/triac/triac.cir.out~ b/src/SubcircuitLibrary/triac/triac.cir.out~
new file mode 100644
index 00000000..7bd15a7b
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.cir.out~
@@ -0,0 +1,41 @@
+* /opt/esim/src/subcircuitlibrary/triac/triac.cir
+
+.include PowerDiode.lib
+* u3  8 11 10 port
+* f3
+v3 7 2  dc 0
+* f2
+v2 6 3  dc 0
+c1  8 9 10u
+* f1
+v1 10 4  dc 0
+* u1  9 11 6 aswitch
+* u2  9 2 11 aswitch
+r1  8 9 1
+d1 5 8 PowerDiode
+d2 1 7 PowerDiode
+Vf3 1 8 0
+f3 8 9 Vf3 10
+Vf2 3 5 0
+f2 8 9 Vf2 10
+Vf1 4 8 0
+f1 8 9 Vf1 100
+a1 9 [11 6 ] u1
+a2 9 [2 11 ] u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) 
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) 
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) 
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/triac/triac.pro b/src/SubcircuitLibrary/triac/triac.pro
new file mode 100644
index 00000000..5b1f5f89
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.pro
@@ -0,0 +1,44 @@
+update=Tue Dec  8 14:16:32 2015
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Sources
+LibName7=eSim_Subckt
+LibName8=eSim_User
+LibName9=power
+LibName10=device
+LibName11=transistors
+LibName12=conn
+LibName13=linear
+LibName14=regul
+LibName15=74xx
+LibName16=cmos4000
+LibName17=adc-dac
+LibName18=memory
+LibName19=xilinx
+LibName20=special
+LibName21=microcontrollers
+LibName22=dsp
+LibName23=microchip
+LibName24=analog_switches
+LibName25=motorola
+LibName26=texas
+LibName27=intel
+LibName28=audio
+LibName29=interface
+LibName30=digital-audio
+LibName31=philips
+LibName32=display
+LibName33=cypress
+LibName34=siliconi
+LibName35=opto
+LibName36=atmel
+LibName37=contrib
+LibName38=valves
diff --git a/src/SubcircuitLibrary/triac/triac.sch b/src/SubcircuitLibrary/triac/triac.sch
new file mode 100644
index 00000000..f30533a0
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.sch
@@ -0,0 +1,308 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:triac-cache
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+F 3 "" H 3700 1850 60  0001 C CNN
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diff --git a/src/SubcircuitLibrary/triac/triac.sub b/src/SubcircuitLibrary/triac/triac.sub
new file mode 100644
index 00000000..760908b0
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.sub
@@ -0,0 +1,32 @@
+* Subcircuit triac
+.subckt triac 8 11 10 
+* /opt/esim/src/subcircuitlibrary/triac/triac.cir
+.include PowerDiode.lib
+* f3
+v3 7 2  dc 0
+* f2
+v2 6 3  dc 0
+c1  8 9 10u
+* f1
+v1 10 4  dc 0
+* u1  9 11 6 aswitch
+* u2  9 2 11 aswitch
+r1  8 9 1
+d1 5 8 PowerDiode
+d2 1 7 PowerDiode
+Vf3 1 8 0
+f3 8 9 Vf3 10
+Vf2 3 5 0
+f2 8 9 Vf2 10
+Vf1 4 8 0
+f1 8 9 Vf1 100
+a1 9 (11 6)  u1
+a2 9 (2 11)  u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
+
+* Control Statements
+
+.ends triac
diff --git a/src/SubcircuitLibrary/triac/triac.sub~ b/src/SubcircuitLibrary/triac/triac.sub~
new file mode 100644
index 00000000..ebbed05e
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac.sub~
@@ -0,0 +1,35 @@
+* Subcircuit triac
+.subckt triac 8 11 10 
+* /opt/esim/src/subcircuitlibrary/triac/triac.cir
+.include PowerDiode.lib
+* f3
+v3 7 2  dc 0
+* f2
+v2 6 3  dc 0
+c1  8 9 10u
+* f1
+v1 10 4  dc 0
+* u1  9 11 6 aswitch
+* u2  9 2 11 aswitch
+r1  8 9 1
+d1 5 8 PowerDiode
+d2 1 7 PowerDiode
+Vf3 1 8 0
+f3 8 9 Vf3 10
+Vf2 3 5 0
+f2 8 9 Vf2 10
+Vf1 4 8 0
+f1 8 9 Vf1 100
+a1 9 [11 6 ] u1
+a2 9 [2 11 ] u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
+* Control Statements
+
+.ends triac
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/triac/triac_Previous_Values.xml b/src/SubcircuitLibrary/triac/triac_Previous_Values.xml
new file mode 100644
index 00000000..80da52b3
--- /dev/null
+++ b/src/SubcircuitLibrary/triac/triac_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">1</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-1</field10></u2></model><devicemodel><d2><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d2><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file