remove temporary files

4 files changed, 0 insertions, 314 deletions

diff --git a/src/SubcircuitLibrary/scr/scr.bak b/src/SubcircuitLibrary/scr/scr.bak
deleted file mode 100644
index 58b985d9..00000000
--- a/src/SubcircuitLibrary/scr/scr.bak
+++ /dev/null
@@ -1,243 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:analogSpice
-LIBS:analogXSpice
-LIBS:convergenceAidSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:digitalXSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:eSim_Analog
-LIBS:scr-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "21 aug 2014"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
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-Wire Wire Line
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-Wire Wire Line
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-$Comp
-L PORT U2
-U 3 1 53F4C93D
-P 6650 2250
-F 0 "U2" H 6650 2200 30  0000 C CNN
-F 1 "PORT" H 6650 2250 30  0000 C CNN
-F 2 "" H 6650 2250 60  0001 C CNN
-F 3 "" H 6650 2250 60  0001 C CNN
-	3    6650 2250
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-$EndComp
-$Comp
-L PORT U2
-U 2 1 53F4C934
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-F 1 "PORT" H 2900 2300 30  0000 C CNN
-F 2 "" H 2900 2300 60  0001 C CNN
-F 3 "" H 2900 2300 60  0001 C CNN
-	2    2900 2300
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U2
-U 1 1 53F4C92A
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-F 0 "U2" H 6400 4900 30  0000 C CNN
-F 1 "PORT" H 6400 4950 30  0000 C CNN
-F 2 "" H 6400 4950 60  0001 C CNN
-F 3 "" H 6400 4950 60  0001 C CNN
-	1    6400 4950
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-$EndComp
-$Comp
-L CCCS F2
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-F 3 "" H 5750 4200 60  0001 C CNN
-	1    5750 4200
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-$EndComp
-$Comp
-L DIODE D1
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-F 2 "" H 5550 3800 60  0001 C CNN
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-$EndComp
-$Comp
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-$Comp
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-F 3 "" H 4250 5250 60  0001 C CNN
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-$EndComp
-$Comp
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-F 3 "" H 3800 4350 60  0001 C CNN
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-$EndComp
-$Comp
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-$EndComp
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-$EndComp
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-$EndComp
-$Comp
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-	1    6400 2100
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-$EndComp
-Wire Wire Line
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-$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/scr/scr.cir.ckt b/src/SubcircuitLibrary/scr/scr.cir.ckt
deleted file mode 100644
index b0e218fd..00000000
--- a/src/SubcircuitLibrary/scr/scr.cir.ckt
+++ /dev/null
@@ -1,19 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22

-.include diode.lib

-

-u2  5 8 1 port

-* f2

-* Analog Switch analogswitch

-d1  4 2 diode

-v2  3 4 dc 0

-c1  5 6 10u

-r2  5 6 1

-* f1

-v1  9 7 dc 0

-r1  8 9 50

-Vf2 2 5 0

-f2 5 6 Vf2 100

-Vf1 7 5 0

-f1 5 6 Vf1 10

-a1 6 (1 3) u1

-.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000)

diff --git a/src/SubcircuitLibrary/scr/scr.cir.out~ b/src/SubcircuitLibrary/scr/scr.cir.out~
deleted file mode 100644
index d600f25d..00000000
--- a/src/SubcircuitLibrary/scr/scr.cir.out~
+++ /dev/null
@@ -1,29 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-
-.include PowerDiode.lib
-* u2  3 7 1 port
-* f2
-d1 5 2 PowerDiode
-c1  3 9 10u
-* f1
-v1 8 4  dc 0
-v2 6 5  dc 0
-* u1  9 1 6 aswitch
-r1  7 8 50
-r2  3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 (1 6)  u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) 
-.tran 0e-12 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/src/SubcircuitLibrary/scr/scr.sub~ b/src/SubcircuitLibrary/scr/scr.sub~
deleted file mode 100644
index 0fdddbf4..00000000
--- a/src/SubcircuitLibrary/scr/scr.sub~
+++ /dev/null
@@ -1,23 +0,0 @@
-* Subcircuit scr
-.subckt scr 3 7 1 
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1  3 9 10u
-* f1
-v1 8 4  dc 0
-v2 6 5  dc 0
-* u1  9 1 6 aswitch
-r1  7 8 50
-r2  3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr
\ No newline at end of file