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authorFahim2015-12-30 12:20:39 +0530
committerFahim2015-12-30 12:20:39 +0530
commit5c21ac87792c7eee763afcd6df80fc0bb8524b6c (patch)
tree385a811388f218bc5ebd798a7b9bbbdfda537d1a /src/SubcircuitLibrary/scr/scr.sub~
parente4b74bcbaa07bfe96f808db4d9fe6e05c6cde87d (diff)
downloadeSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.tar.gz
eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.tar.bz2
eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.zip
Added :
1. Power Examples 2. eSim_Power.lib 3. Subcircuit for diac, scr, triac 4. Device model for Power Diode
Diffstat (limited to 'src/SubcircuitLibrary/scr/scr.sub~')
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diff --git a/src/SubcircuitLibrary/scr/scr.sub~ b/src/SubcircuitLibrary/scr/scr.sub~
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+* Subcircuit scr
+.subckt scr 3 7 1
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+.include PowerDiode.lib
+* f2
+d1 5 2 PowerDiode
+c1 3 9 10u
+* f1
+v1 8 4 dc 0
+v2 6 5 dc 0
+* u1 9 1 6 aswitch
+r1 7 8 50
+r2 3 9 1
+Vf2 2 3 0
+f2 3 9 Vf2 100
+Vf1 4 3 0
+f1 3 9 Vf1 10
+a1 9 [1 6 ] u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
+* Control Statements
+
+.ends scr \ No newline at end of file