Added subcircuit functionality

11 files changed, 1116 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/lm555n/analysis b/src/SubcircuitLibrary/lm555n/analysis
new file mode 100644
index 00000000..52ccc5ec
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/analysis
@@ -0,0 +1 @@
+.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.bak b/src/SubcircuitLibrary/lm555n/lm555n.bak
new file mode 100644
index 00000000..92d1f7a7
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.bak
@@ -0,0 +1,435 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 10:48:46 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:digitalXSpice
+LIBS:lm555n-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
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+Title ""
+Date "17 dec 2012"
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diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir
new file mode 100644
index 00000000..8f6f81c6
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir
@@ -0,0 +1,25 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U5  5 21 D_INVERTER		
+U6  1 4 5 21 21 8 10 D_SRLATCH		
+E2  18 0 23 14 10000		
+*U4  19 20 11 12 LIMIT8		
+*U3  8 10 7 9 DAC8		
+*U2  11 12 6 4 1 5 ADC8		
+U1  22 14 7 6 15 16 3 13 PORT		
+R8  9 2 1500		
+Q1  22 2 3 QNOM		
+R7  18 20 25		
+R6  17 19 25		
+E1  17 0 16 15 10000		
+R4  16 15 2E6		
+R5  23 14 2E6		
+R3  23 22 5000		
+R2  15 23 5000		
+R1  13 15 5000		
+
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt
new file mode 100644
index 00000000..90f04a32
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.ckt
@@ -0,0 +1,35 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+
+* Inverter d_inverter
+* SR Latch d_srlatch
+e2  18 0 23 14 10000
+* Limiter limit8
+* Digital to Analog converter dac8
+* Analog to Digital converter adc8
+u1  22 14 7 6 15 16 3 13 port
+r8  9 2 1500
+q1 3 2 22 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
+a2 1 4 5 21 21 8 10 u6
+.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
+a3 19 11 u4
+a4 20 12 u4
+.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0)
+a5 [8] [7] u3
+a6 [10] [9] u3
+.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
+a7 [11] [4] u2
+a8 [12] [1] u2
+a9 [6] [5] u2
+.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
new file mode 100644
index 00000000..f25b1e46
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
@@ -0,0 +1,31 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+
+* u5  5 21 d_inverter
+* u6  1 4 5 21 21 8 10 d_srlatch
+e2  18 0 23 14 10000
+* u1  22 14 7 6 15 16 3 13 port
+r8  9 2 1500
+q1  22 2 3 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+a2 1 4 5 21 21 8 10 u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
+.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out~ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~
new file mode 100644
index 00000000..bc50c640
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out~
@@ -0,0 +1,30 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+
+* u5  5 21 d_inverter
+* u6  1 4 5 21 21 8 10 d_srlatch
+e2  18 0 23 14 10000
+r8  9 2 1500
+q1  22 2 3 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+a2 1 4 5 21 21 8 10 u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
+.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir~ b/src/SubcircuitLibrary/lm555n/lm555n.cir~
new file mode 100644
index 00000000..7ef9e6a5
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir~
@@ -0,0 +1,25 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U5  5 21 D_INVERTER		
+U6  1 4 5 21 21 8 10 D_SRLATCH		
+E2  18 0 23 14 10000		
+*U4  19 20 11 12 LIMIT8		
+*U3  8 10 7 9 DAC8		
+*U2  11 12 6 4 1 5 ADC8		
+*U1  22 14 7 6 15 16 3 13 PORT		
+R8  9 2 1500		
+Q1  22 2 3 QNOM		
+R7  18 20 25		
+R6  17 19 25		
+E1  17 0 16 15 10000		
+R4  16 15 2E6		
+R5  23 14 2E6		
+R3  23 22 5000		
+R2  15 23 5000		
+R1  13 15 5000		
+
+.end
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro
new file mode 100644
index 00000000..c8e151fb
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.pro
@@ -0,0 +1,73 @@
+update=Monday 19 November 2012 04:56:38 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/FreeEDA/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=analogXSpice
+LibName33=converterSpice
+LibName34=digitalSpice
+LibName35=linearSpice
+LibName36=measurementSpice
+LibName37=portSpice
+LibName38=sourcesSpice
+LibName39=digitalXSpice
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch
new file mode 100644
index 00000000..fabbb666
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sch
@@ -0,0 +1,435 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 10:57:52 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
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+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
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+LIBS:cypress
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+LIBS:atmel
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+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
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+LIBS:portSpice
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+LIBS:lm555n-cache
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+encoding utf-8
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diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub
new file mode 100644
index 00000000..862626ea
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sub
@@ -0,0 +1,25 @@
+* Subcircuit lm555n
+.subckt lm555n 22 14 7 6 15 16 3 13 
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+* u5  5 21 d_inverter
+* u6  1 4 5 21 21 8 10 d_srlatch
+e2  18 0 23 14 10000
+r8  9 2 1500
+q1  22 2 3 qnom
+r7  18 20 25
+r6  17 19 25
+e1  17 0 16 15 10000
+r4  16 15 2e6
+r5  23 14 2e6
+r3  23 22 5000
+r2  15 23 5000
+r1  13 15 5000
+a1 5 21 u5
+a2 1 4 5 21 21 8 10 u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
+.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 )
+* Control Statements
+
+.ends lm555n
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml
new file mode 100644
index 00000000..7d81146a
--- /dev/null
+++ b/src/SubcircuitLibrary/lm555n/lm555n_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel></KicadtoNgspice>
\ No newline at end of file