update files from eSim-Examples

5 files changed, 90 insertions, 101 deletions

diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir b/src/SubcircuitLibrary/lm555n/lm555n.cir
index 8f6f81c6..144b7152 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir
@@ -1,4 +1,4 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 10:57:49 AM IST
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:00:36 AM IST
 
 * To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
 * To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
@@ -7,9 +7,9 @@
 U5  5 21 D_INVERTER		
 U6  1 4 5 21 21 8 10 D_SRLATCH		
 E2  18 0 23 14 10000		
-*U4  19 20 11 12 LIMIT8		
-*U3  8 10 7 9 DAC8		
-*U2  11 12 6 4 1 5 ADC8		
+U4  19 20 11 12 LIMIT8		
+U3  8 10 7 9 DAC8		
+U2  11 12 6 4 1 5 ADC8		
 U1  22 14 7 6 15 16 3 13 PORT		
 R8  9 2 1500		
 Q1  22 2 3 QNOM		
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
index 21ca75a9..f45920fd 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out
+++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out
@@ -1,11 +1,14 @@
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist
 
-* u5  5 21 d_inverter
-* u6  1 4 5 21 21 8 10 d_srlatch
+* Inverter d_inverter
+* SR Latch d_srlatch
 e2  18 0 23 14 10000
-* u1  22 14 7 6 15 16 3 13 port
+* Limiter limit8
+* Digital to Analog converter dac8
+* Analog to Digital converter adc8
+u1  22 14 7 6 15 16 3 13 port
 r8  9 2 1500
-q1  22 2 3 qnom
+q1 3 2 22 qnom
 r7  18 20 25
 r6  17 19 25
 e1  17 0 16 15 10000
@@ -15,17 +18,18 @@ r3  23 22 5000
 r2  15 23 5000
 r1  13 15 5000
 a1 5 21 u5
+.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
 a2 1 4 5 21 21 8 10 u6
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
-.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) 
-.ac oct 897897 kjadsfhHz jhdsakjHz
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
+a3 19 11 u4
+a4 20 12 u4
+.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0)
+a5 [8] [7] u3
+a6 [10] [9] u3
+.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
+a7 [11] [4] u2
+a8 [12] [1] u2
+a9 [6] [5] u2
+.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.pro b/src/SubcircuitLibrary/lm555n/lm555n.pro
index c8e151fb..1a966cc5 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.pro
+++ b/src/SubcircuitLibrary/lm555n/lm555n.pro
@@ -1,73 +1,46 @@
-update=Monday 19 November 2012 04:56:38 PM IST
+update=Thu May 19 16:58:03 2016
 last_client=eeschema
 [eeschema]
 version=1
-LibDir=/home/yogesh/FreeEDA/library
-NetFmt=1
-HPGLSpd=20
-HPGLDm=15
-HPGLNum=1
-offX_A4=0
-offY_A4=0
-offX_A3=0
-offY_A3=0
-offX_A2=0
-offY_A2=0
-offX_A1=0
-offY_A1=0
-offX_A0=0
-offY_A0=0
-offX_A=0
-offY_A=0
-offX_B=0
-offY_B=0
-offX_C=0
-offY_C=0
-offX_D=0
-offY_D=0
-offX_E=0
-offY_E=0
-RptD_X=0
-RptD_Y=100
-RptLab=1
-LabSize=60
+LibDir=
 [eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
-LibName15=microchip
-LibName16=analog_switches
-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
-LibName21=interface
-LibName22=digital-audio
-LibName23=philips
-LibName24=display
-LibName25=cypress
-LibName26=siliconi
-LibName27=opto
-LibName28=atmel
-LibName29=contrib
-LibName30=valves
-LibName31=analogSpice
-LibName32=analogXSpice
-LibName33=converterSpice
-LibName34=digitalSpice
-LibName35=linearSpice
-LibName36=measurementSpice
-LibName37=portSpice
-LibName38=sourcesSpice
-LibName39=digitalXSpice
+LibName1=lm555n-rescue
+LibName2=power
+LibName3=device
+LibName4=transistors
+LibName5=conn
+LibName6=linear
+LibName7=regul
+LibName8=74xx
+LibName9=cmos4000
+LibName10=adc-dac
+LibName11=memory
+LibName12=xilinx
+LibName13=special
+LibName14=microcontrollers
+LibName15=dsp
+LibName16=microchip
+LibName17=analog_switches
+LibName18=motorola
+LibName19=texas
+LibName20=intel
+LibName21=audio
+LibName22=interface
+LibName23=digital-audio
+LibName24=philips
+LibName25=display
+LibName26=cypress
+LibName27=siliconi
+LibName28=opto
+LibName29=atmel
+LibName30=contrib
+LibName31=valves
+LibName32=analogSpice
+LibName33=analogXSpice
+LibName34=converterSpice
+LibName35=digitalSpice
+LibName36=linearSpice
+LibName37=measurementSpice
+LibName38=portSpice
+LibName39=sourcesSpice
+LibName40=digitalXSpice
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sch b/src/SubcircuitLibrary/lm555n/lm555n.sch
index fabbb666..417063b1 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.sch
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Monday 17 December 2012 10:57:52 AM IST
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:00:43 AM IST
 LIBS:power
 LIBS:device
 LIBS:transistors
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub
index 862626ea..beeefc43 100644
--- a/src/SubcircuitLibrary/lm555n/lm555n.sub
+++ b/src/SubcircuitLibrary/lm555n/lm555n.sub
@@ -1,11 +1,14 @@
 * Subcircuit lm555n
 .subckt lm555n 22 14 7 6 15 16 3 13 
-* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist
-* u5  5 21 d_inverter
-* u6  1 4 5 21 21 8 10 d_srlatch
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist
+* Inverter d_inverter
+* SR Latch d_srlatch
 e2  18 0 23 14 10000
+* Limiter limit8
+* Digital to Analog converter dac8
+* Analog to Digital converter adc8
 r8  9 2 1500
-q1  22 2 3 qnom
+q1 3 2 22 qnom
 r7  18 20 25
 r6  17 19 25
 e1  17 0 16 15 10000
@@ -15,11 +18,20 @@ r3  23 22 5000
 r2  15 23 5000
 r1  13 15 5000
 a1 5 21 u5
+.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12)
 a2 1 4 5 21 21 8 10 u6
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_srlatch, NgSpice Name: d_srlatch
-.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 )
-* Control Statements
+.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0
++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12
++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12)
+a3 19 11 u4
+a4 20 12 u4
+.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0)
+a5 [8] [7] u3
+a6 [10] [9] u3
+.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 )
+a7 [11] [4] u2
+a8 [12] [1] u2
+a9 [6] [5] u2
+.model u2 adc_bridge(in_low=0.8 in_high=2.0 )
 
 .ends lm555n
\ No newline at end of file