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| author | Sunil Shetye | 2019-03-12 14:34:31 +0530 |
|---|---|---|
| committer | Sunil Shetye | 2019-07-01 18:04:00 +0530 |
| commit | d2b775bde7bde4396c251ddac6685d503d0577d8 (patch) | |
| tree | 182409f27bac4dec022d66aec01c7985849cc58e /src/SubcircuitLibrary/lm555n/lm555n.sub | |
| parent | be75bc43e5cd58c8c4e23b3f35911f4e69cd5928 (diff) | |
| download | eSim-d2b775bde7bde4396c251ddac6685d503d0577d8.tar.gz eSim-d2b775bde7bde4396c251ddac6685d503d0577d8.tar.bz2 eSim-d2b775bde7bde4396c251ddac6685d503d0577d8.zip | |
update files from eSim-Examples
Diffstat (limited to 'src/SubcircuitLibrary/lm555n/lm555n.sub')
| -rw-r--r-- | src/SubcircuitLibrary/lm555n/lm555n.sub | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.sub b/src/SubcircuitLibrary/lm555n/lm555n.sub index 862626ea..beeefc43 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.sub +++ b/src/SubcircuitLibrary/lm555n/lm555n.sub @@ -1,11 +1,14 @@ * Subcircuit lm555n .subckt lm555n 22 14 7 6 15 16 3 13 -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist -* u5 5 21 d_inverter -* u6 1 4 5 21 21 8 10 d_srlatch +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 r8 9 2 1500 -q1 22 2 3 qnom +q1 3 2 22 qnom r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -15,11 +18,20 @@ r3 23 22 5000 r2 15 23 5000 r1 13 15 5000 a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) a2 1 4 5 21 21 8 10 u6 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_srlatch, NgSpice Name: d_srlatch -.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) -* Control Statements +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) .ends lm555n
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