diff options
| author | Sunil Shetye | 2019-07-01 18:12:34 +0530 |
|---|---|---|
| committer | GitHub | 2019-07-01 18:12:34 +0530 |
| commit | 29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (patch) | |
| tree | 6d3b2a1ba2c92ba6bfb898f534576a2331cf9f9d /src/SubcircuitLibrary/lm555n/lm555n.cir.out | |
| parent | 6b410587b3101af7c6378c8e816e7d357beb1929 (diff) | |
| parent | aec27ddec95f30c155ad356da24eb7e3ce2247cd (diff) | |
| download | eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.gz eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.bz2 eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.zip | |
Merge pull request #114 from sunilshetye/masterfixes
Master fixes
Diffstat (limited to 'src/SubcircuitLibrary/lm555n/lm555n.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/lm555n/lm555n.cir.out | 40 |
1 files changed, 22 insertions, 18 deletions
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out index 21ca75a9..f45920fd 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -1,11 +1,14 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist -* u5 5 21 d_inverter -* u6 1 4 5 21 21 8 10 d_srlatch +* Inverter d_inverter +* SR Latch d_srlatch e2 18 0 23 14 10000 -* u1 22 14 7 6 15 16 3 13 port +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port r8 9 2 1500 -q1 22 2 3 qnom +q1 3 2 22 qnom r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -15,17 +18,18 @@ r3 23 22 5000 r2 15 23 5000 r1 13 15 5000 a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) a2 1 4 5 21 21 8 10 u6 -* Schematic Name: d_inverter, NgSpice Name: d_inverter -.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_srlatch, NgSpice Name: d_srlatch -.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) -.ac oct 897897 kjadsfhHz jhdsakjHz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) |