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| author | rahulp13 | 2020-02-14 15:16:35 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
| commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
| tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /src/SubcircuitLibrary/lm555n/lm555n.cir.out | |
| parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
| download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip | |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'src/SubcircuitLibrary/lm555n/lm555n.cir.out')
| -rw-r--r-- | src/SubcircuitLibrary/lm555n/lm555n.cir.out | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/SubcircuitLibrary/lm555n/lm555n.cir.out b/src/SubcircuitLibrary/lm555n/lm555n.cir.out index f45920fd..a81070a1 100644 --- a/src/SubcircuitLibrary/lm555n/lm555n.cir.out +++ b/src/SubcircuitLibrary/lm555n/lm555n.cir.out @@ -1,5 +1,5 @@ * eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist - +.include npn_1.lib * Inverter d_inverter * SR Latch d_srlatch e2 18 0 23 14 10000 @@ -8,7 +8,7 @@ e2 18 0 23 14 10000 * Analog to Digital converter adc8 u1 22 14 7 6 15 16 3 13 port r8 9 2 1500 -q1 3 2 22 qnom +q1 3 2 22 npn_1 r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -33,3 +33,10 @@ a7 [11] [4] u2 a8 [12] [1] u2 a9 [6] [5] u2 .model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |